./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix028_pso.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_a713965c-2e57-4a60-943c-972142842105/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_a713965c-2e57-4a60-943c-972142842105/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_a713965c-2e57-4a60-943c-972142842105/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_a713965c-2e57-4a60-943c-972142842105/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix028_pso.oepc.i -s /tmp/vcloud-vcloud-master/worker/run_dir_a713965c-2e57-4a60-943c-972142842105/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_a713965c-2e57-4a60-943c-972142842105/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c2da70db35e53acb3d8b5d515c77b284d097adf9 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:17:36,415 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:17:36,416 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:17:36,424 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:17:36,424 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:17:36,425 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:17:36,426 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:17:36,427 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:17:36,428 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:17:36,429 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:17:36,429 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:17:36,430 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:17:36,431 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:17:36,431 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:17:36,432 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:17:36,433 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:17:36,433 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:17:36,434 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:17:36,435 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:17:36,436 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:17:36,437 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:17:36,438 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:17:36,439 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:17:36,439 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:17:36,441 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:17:36,441 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:17:36,441 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:17:36,442 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:17:36,442 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:17:36,443 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:17:36,443 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:17:36,443 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:17:36,444 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:17:36,444 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:17:36,445 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:17:36,445 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:17:36,445 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:17:36,445 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:17:36,445 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:17:36,446 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:17:36,446 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:17:36,447 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_a713965c-2e57-4a60-943c-972142842105/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 18:17:36,456 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:17:36,456 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:17:36,457 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:17:36,457 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:17:36,457 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:17:36,457 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:17:36,457 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:17:36,457 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:17:36,457 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:17:36,457 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:17:36,457 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 18:17:36,458 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 18:17:36,458 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 18:17:36,458 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:17:36,458 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:17:36,458 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:17:36,458 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 18:17:36,458 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:17:36,458 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:17:36,458 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 18:17:36,459 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 18:17:36,459 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:17:36,459 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:17:36,459 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 18:17:36,459 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 18:17:36,459 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:17:36,459 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 18:17:36,459 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 18:17:36,460 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:17:36,460 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_a713965c-2e57-4a60-943c-972142842105/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c2da70db35e53acb3d8b5d515c77b284d097adf9 [2019-12-07 18:17:36,560 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:17:36,571 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:17:36,573 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:17:36,575 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:17:36,575 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:17:36,575 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_a713965c-2e57-4a60-943c-972142842105/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix028_pso.oepc.i [2019-12-07 18:17:36,618 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_a713965c-2e57-4a60-943c-972142842105/bin/uautomizer/data/78e55aa24/0fade8a5a330436c9e637ae8e9ac9190/FLAGdbda81f59 [2019-12-07 18:17:36,987 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:17:36,988 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_a713965c-2e57-4a60-943c-972142842105/sv-benchmarks/c/pthread-wmm/mix028_pso.oepc.i [2019-12-07 18:17:36,999 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_a713965c-2e57-4a60-943c-972142842105/bin/uautomizer/data/78e55aa24/0fade8a5a330436c9e637ae8e9ac9190/FLAGdbda81f59 [2019-12-07 18:17:37,009 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_a713965c-2e57-4a60-943c-972142842105/bin/uautomizer/data/78e55aa24/0fade8a5a330436c9e637ae8e9ac9190 [2019-12-07 18:17:37,010 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:17:37,011 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:17:37,012 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:17:37,012 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:17:37,014 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:17:37,015 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:17:37" (1/1) ... [2019-12-07 18:17:37,017 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3f8fae9c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:37, skipping insertion in model container [2019-12-07 18:17:37,017 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:17:37" (1/1) ... [2019-12-07 18:17:37,021 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:17:37,050 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:17:37,295 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:17:37,303 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:17:37,348 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:17:37,396 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:17:37,396 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:37 WrapperNode [2019-12-07 18:17:37,396 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:17:37,397 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:17:37,397 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:17:37,397 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:17:37,403 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:37" (1/1) ... [2019-12-07 18:17:37,417 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:37" (1/1) ... [2019-12-07 18:17:37,436 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:17:37,437 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:17:37,437 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:17:37,437 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:17:37,444 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:37" (1/1) ... [2019-12-07 18:17:37,444 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:37" (1/1) ... [2019-12-07 18:17:37,447 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:37" (1/1) ... [2019-12-07 18:17:37,447 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:37" (1/1) ... [2019-12-07 18:17:37,455 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:37" (1/1) ... [2019-12-07 18:17:37,458 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:37" (1/1) ... [2019-12-07 18:17:37,461 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:37" (1/1) ... [2019-12-07 18:17:37,465 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:17:37,465 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:17:37,465 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:17:37,465 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:17:37,466 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:37" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_a713965c-2e57-4a60-943c-972142842105/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:17:37,506 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 18:17:37,506 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 18:17:37,506 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 18:17:37,507 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 18:17:37,507 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 18:17:37,507 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 18:17:37,507 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 18:17:37,507 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 18:17:37,507 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 18:17:37,507 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 18:17:37,507 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 18:17:37,507 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:17:37,507 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:17:37,508 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 18:17:37,875 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:17:37,875 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 18:17:37,876 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:17:37 BoogieIcfgContainer [2019-12-07 18:17:37,877 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:17:37,877 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 18:17:37,878 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 18:17:37,880 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 18:17:37,880 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 06:17:37" (1/3) ... [2019-12-07 18:17:37,881 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@200a2f49 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:17:37, skipping insertion in model container [2019-12-07 18:17:37,881 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:37" (2/3) ... [2019-12-07 18:17:37,881 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@200a2f49 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:17:37, skipping insertion in model container [2019-12-07 18:17:37,882 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:17:37" (3/3) ... [2019-12-07 18:17:37,883 INFO L109 eAbstractionObserver]: Analyzing ICFG mix028_pso.oepc.i [2019-12-07 18:17:37,891 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 18:17:37,892 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 18:17:37,898 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 18:17:37,899 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 18:17:37,925 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,925 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,925 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,926 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,926 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,926 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,926 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,926 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,926 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,927 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,927 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,927 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,927 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,927 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,927 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,927 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,928 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,928 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,928 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,928 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,928 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,928 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,928 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,928 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,929 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,929 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,929 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,929 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,929 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,929 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,929 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,930 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,930 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,930 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,930 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,930 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,930 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,931 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,931 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,931 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,931 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,931 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,931 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,931 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,932 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,932 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,932 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,932 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,932 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,932 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,932 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,932 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,933 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,933 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,933 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,933 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,933 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,933 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,933 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,934 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,934 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,934 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,934 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,934 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,935 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,935 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,935 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~nondet16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,935 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,935 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,935 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,935 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,935 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~nondet16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,936 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,936 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,936 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,936 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,936 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,936 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,936 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,937 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,937 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,937 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,937 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,937 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,937 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,937 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,937 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,937 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,938 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,938 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,938 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,938 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,938 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,938 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,938 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,938 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,939 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,939 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,939 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,939 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,939 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,939 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,939 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,939 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,940 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,940 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,940 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,940 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,940 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,940 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,940 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,940 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,941 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,941 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,941 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,941 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,941 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,941 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,941 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,941 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,941 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,942 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,942 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,942 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,942 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,942 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,942 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,942 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,942 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,942 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,943 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,943 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,943 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,943 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,943 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,943 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,943 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,944 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,944 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,944 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,944 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,944 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,944 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,944 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,944 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,944 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,945 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,945 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,945 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,945 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,945 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,945 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,945 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,945 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,946 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,946 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,946 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,946 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,946 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,946 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,946 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,946 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,946 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,947 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,947 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,947 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,947 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,947 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,947 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,947 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,947 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,948 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,948 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,948 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,948 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,948 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,948 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,948 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,948 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,948 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,949 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,949 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:37,962 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 18:17:37,977 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 18:17:37,977 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 18:17:37,977 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 18:17:37,977 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:17:37,977 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:17:37,978 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 18:17:37,978 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:17:37,978 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 18:17:37,988 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 175 places, 212 transitions [2019-12-07 18:17:37,989 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 175 places, 212 transitions [2019-12-07 18:17:38,055 INFO L134 PetriNetUnfolder]: 47/209 cut-off events. [2019-12-07 18:17:38,055 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:17:38,065 INFO L76 FinitePrefix]: Finished finitePrefix Result has 219 conditions, 209 events. 47/209 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 682 event pairs. 9/169 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 18:17:38,081 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 175 places, 212 transitions [2019-12-07 18:17:38,109 INFO L134 PetriNetUnfolder]: 47/209 cut-off events. [2019-12-07 18:17:38,109 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:17:38,115 INFO L76 FinitePrefix]: Finished finitePrefix Result has 219 conditions, 209 events. 47/209 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 682 event pairs. 9/169 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 18:17:38,130 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 19004 [2019-12-07 18:17:38,131 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 18:17:41,355 WARN L192 SmtUtils]: Spent 127.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 44 [2019-12-07 18:17:41,619 WARN L192 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 89 DAG size of output: 87 [2019-12-07 18:17:41,706 INFO L206 etLargeBlockEncoding]: Checked pairs total: 87070 [2019-12-07 18:17:41,706 INFO L214 etLargeBlockEncoding]: Total number of compositions: 113 [2019-12-07 18:17:41,709 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 93 places, 102 transitions [2019-12-07 18:17:55,577 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 115112 states. [2019-12-07 18:17:55,579 INFO L276 IsEmpty]: Start isEmpty. Operand 115112 states. [2019-12-07 18:17:55,582 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-12-07 18:17:55,582 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:17:55,583 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-12-07 18:17:55,583 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:17:55,587 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:17:55,587 INFO L82 PathProgramCache]: Analyzing trace with hash 911890, now seen corresponding path program 1 times [2019-12-07 18:17:55,592 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:17:55,592 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184614929] [2019-12-07 18:17:55,592 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:17:55,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:17:55,731 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:17:55,732 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184614929] [2019-12-07 18:17:55,732 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:17:55,733 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:17:55,733 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2131549036] [2019-12-07 18:17:55,736 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:17:55,736 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:17:55,745 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:17:55,745 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:17:55,747 INFO L87 Difference]: Start difference. First operand 115112 states. Second operand 3 states. [2019-12-07 18:17:56,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:17:56,527 INFO L93 Difference]: Finished difference Result 114158 states and 484836 transitions. [2019-12-07 18:17:56,528 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:17:56,529 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-12-07 18:17:56,529 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:17:56,996 INFO L225 Difference]: With dead ends: 114158 [2019-12-07 18:17:56,996 INFO L226 Difference]: Without dead ends: 107060 [2019-12-07 18:17:56,997 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:18:02,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107060 states. [2019-12-07 18:18:04,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107060 to 107060. [2019-12-07 18:18:04,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 107060 states. [2019-12-07 18:18:04,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107060 states to 107060 states and 454078 transitions. [2019-12-07 18:18:04,455 INFO L78 Accepts]: Start accepts. Automaton has 107060 states and 454078 transitions. Word has length 3 [2019-12-07 18:18:04,456 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:18:04,456 INFO L462 AbstractCegarLoop]: Abstraction has 107060 states and 454078 transitions. [2019-12-07 18:18:04,456 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:18:04,456 INFO L276 IsEmpty]: Start isEmpty. Operand 107060 states and 454078 transitions. [2019-12-07 18:18:04,459 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 18:18:04,459 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:18:04,460 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:18:04,460 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:18:04,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:18:04,460 INFO L82 PathProgramCache]: Analyzing trace with hash 1487504284, now seen corresponding path program 1 times [2019-12-07 18:18:04,460 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:18:04,460 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [110323415] [2019-12-07 18:18:04,460 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:18:04,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:18:04,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:18:04,536 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [110323415] [2019-12-07 18:18:04,536 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:18:04,536 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:18:04,536 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1883584238] [2019-12-07 18:18:04,537 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:18:04,537 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:18:04,537 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:18:04,537 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:18:04,537 INFO L87 Difference]: Start difference. First operand 107060 states and 454078 transitions. Second operand 4 states. [2019-12-07 18:18:05,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:18:05,349 INFO L93 Difference]: Finished difference Result 166396 states and 678148 transitions. [2019-12-07 18:18:05,350 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:18:05,350 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 18:18:05,350 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:18:05,804 INFO L225 Difference]: With dead ends: 166396 [2019-12-07 18:18:05,804 INFO L226 Difference]: Without dead ends: 166347 [2019-12-07 18:18:05,805 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:18:13,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166347 states. [2019-12-07 18:18:15,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166347 to 151934. [2019-12-07 18:18:15,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151934 states. [2019-12-07 18:18:15,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151934 states to 151934 states and 627001 transitions. [2019-12-07 18:18:15,649 INFO L78 Accepts]: Start accepts. Automaton has 151934 states and 627001 transitions. Word has length 11 [2019-12-07 18:18:15,649 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:18:15,649 INFO L462 AbstractCegarLoop]: Abstraction has 151934 states and 627001 transitions. [2019-12-07 18:18:15,649 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:18:15,649 INFO L276 IsEmpty]: Start isEmpty. Operand 151934 states and 627001 transitions. [2019-12-07 18:18:15,655 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:18:15,656 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:18:15,656 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:18:15,656 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:18:15,656 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:18:15,656 INFO L82 PathProgramCache]: Analyzing trace with hash 881606285, now seen corresponding path program 1 times [2019-12-07 18:18:15,656 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:18:15,657 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1660332114] [2019-12-07 18:18:15,657 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:18:15,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:18:15,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:18:15,730 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1660332114] [2019-12-07 18:18:15,730 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:18:15,730 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:18:15,731 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [876248969] [2019-12-07 18:18:15,731 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:18:15,731 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:18:15,731 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:18:15,731 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:18:15,731 INFO L87 Difference]: Start difference. First operand 151934 states and 627001 transitions. Second operand 4 states. [2019-12-07 18:18:16,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:18:16,741 INFO L93 Difference]: Finished difference Result 219060 states and 883268 transitions. [2019-12-07 18:18:16,742 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:18:16,742 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 18:18:16,742 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:18:17,273 INFO L225 Difference]: With dead ends: 219060 [2019-12-07 18:18:17,273 INFO L226 Difference]: Without dead ends: 219004 [2019-12-07 18:18:17,274 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:18:23,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219004 states. [2019-12-07 18:18:28,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219004 to 183373. [2019-12-07 18:18:28,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 183373 states. [2019-12-07 18:18:28,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183373 states to 183373 states and 752501 transitions. [2019-12-07 18:18:28,910 INFO L78 Accepts]: Start accepts. Automaton has 183373 states and 752501 transitions. Word has length 13 [2019-12-07 18:18:28,911 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:18:28,911 INFO L462 AbstractCegarLoop]: Abstraction has 183373 states and 752501 transitions. [2019-12-07 18:18:28,911 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:18:28,911 INFO L276 IsEmpty]: Start isEmpty. Operand 183373 states and 752501 transitions. [2019-12-07 18:18:28,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 18:18:28,918 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:18:28,918 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:18:28,918 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:18:28,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:18:28,918 INFO L82 PathProgramCache]: Analyzing trace with hash 1702625862, now seen corresponding path program 1 times [2019-12-07 18:18:28,918 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:18:28,919 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014541622] [2019-12-07 18:18:28,919 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:18:28,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:18:28,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:18:28,969 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2014541622] [2019-12-07 18:18:28,969 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:18:28,969 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:18:28,969 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1902272703] [2019-12-07 18:18:28,969 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:18:28,970 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:18:28,970 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:18:28,970 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:18:28,970 INFO L87 Difference]: Start difference. First operand 183373 states and 752501 transitions. Second operand 4 states. [2019-12-07 18:18:30,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:18:30,003 INFO L93 Difference]: Finished difference Result 227077 states and 928818 transitions. [2019-12-07 18:18:30,004 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:18:30,004 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2019-12-07 18:18:30,004 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:18:30,583 INFO L225 Difference]: With dead ends: 227077 [2019-12-07 18:18:30,583 INFO L226 Difference]: Without dead ends: 227077 [2019-12-07 18:18:30,583 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:18:36,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 227077 states. [2019-12-07 18:18:39,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 227077 to 193528. [2019-12-07 18:18:39,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 193528 states. [2019-12-07 18:18:40,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193528 states to 193528 states and 795357 transitions. [2019-12-07 18:18:40,357 INFO L78 Accepts]: Start accepts. Automaton has 193528 states and 795357 transitions. Word has length 16 [2019-12-07 18:18:40,357 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:18:40,357 INFO L462 AbstractCegarLoop]: Abstraction has 193528 states and 795357 transitions. [2019-12-07 18:18:40,357 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:18:40,358 INFO L276 IsEmpty]: Start isEmpty. Operand 193528 states and 795357 transitions. [2019-12-07 18:18:40,369 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2019-12-07 18:18:40,369 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:18:40,369 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:18:40,369 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:18:40,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:18:40,369 INFO L82 PathProgramCache]: Analyzing trace with hash 233849806, now seen corresponding path program 1 times [2019-12-07 18:18:40,370 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:18:40,370 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2030263046] [2019-12-07 18:18:40,370 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:18:40,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:18:40,426 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:18:40,426 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2030263046] [2019-12-07 18:18:40,426 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:18:40,427 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:18:40,427 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2085562392] [2019-12-07 18:18:40,427 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:18:40,427 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:18:40,427 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:18:40,428 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:18:40,428 INFO L87 Difference]: Start difference. First operand 193528 states and 795357 transitions. Second operand 3 states. [2019-12-07 18:18:41,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:18:41,475 INFO L93 Difference]: Finished difference Result 193528 states and 787109 transitions. [2019-12-07 18:18:41,476 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:18:41,476 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 18 [2019-12-07 18:18:41,476 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:18:41,936 INFO L225 Difference]: With dead ends: 193528 [2019-12-07 18:18:41,936 INFO L226 Difference]: Without dead ends: 193528 [2019-12-07 18:18:41,937 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:18:49,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193528 states. [2019-12-07 18:18:51,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193528 to 190336. [2019-12-07 18:18:51,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190336 states. [2019-12-07 18:18:52,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190336 states to 190336 states and 775269 transitions. [2019-12-07 18:18:52,490 INFO L78 Accepts]: Start accepts. Automaton has 190336 states and 775269 transitions. Word has length 18 [2019-12-07 18:18:52,491 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:18:52,491 INFO L462 AbstractCegarLoop]: Abstraction has 190336 states and 775269 transitions. [2019-12-07 18:18:52,491 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:18:52,491 INFO L276 IsEmpty]: Start isEmpty. Operand 190336 states and 775269 transitions. [2019-12-07 18:18:52,499 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2019-12-07 18:18:52,499 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:18:52,499 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:18:52,500 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:18:52,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:18:52,500 INFO L82 PathProgramCache]: Analyzing trace with hash 1545006780, now seen corresponding path program 1 times [2019-12-07 18:18:52,500 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:18:52,500 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2111070258] [2019-12-07 18:18:52,500 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:18:52,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:18:52,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:18:52,552 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2111070258] [2019-12-07 18:18:52,552 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:18:52,552 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:18:52,552 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1821718938] [2019-12-07 18:18:52,553 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:18:52,553 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:18:52,553 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:18:52,553 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:18:52,553 INFO L87 Difference]: Start difference. First operand 190336 states and 775269 transitions. Second operand 3 states. [2019-12-07 18:18:54,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:18:54,211 INFO L93 Difference]: Finished difference Result 360741 states and 1458049 transitions. [2019-12-07 18:18:54,212 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:18:54,212 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 18 [2019-12-07 18:18:54,212 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:18:54,974 INFO L225 Difference]: With dead ends: 360741 [2019-12-07 18:18:54,974 INFO L226 Difference]: Without dead ends: 316805 [2019-12-07 18:18:54,974 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:02,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 316805 states. [2019-12-07 18:19:06,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 316805 to 301489. [2019-12-07 18:19:06,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 301489 states. [2019-12-07 18:19:12,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 301489 states to 301489 states and 1222745 transitions. [2019-12-07 18:19:12,280 INFO L78 Accepts]: Start accepts. Automaton has 301489 states and 1222745 transitions. Word has length 18 [2019-12-07 18:19:12,280 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:12,280 INFO L462 AbstractCegarLoop]: Abstraction has 301489 states and 1222745 transitions. [2019-12-07 18:19:12,280 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:19:12,280 INFO L276 IsEmpty]: Start isEmpty. Operand 301489 states and 1222745 transitions. [2019-12-07 18:19:12,300 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 18:19:12,300 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:12,300 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:12,300 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:12,301 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:12,301 INFO L82 PathProgramCache]: Analyzing trace with hash -984816045, now seen corresponding path program 1 times [2019-12-07 18:19:12,301 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:12,301 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1470223964] [2019-12-07 18:19:12,301 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:12,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:12,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:12,332 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1470223964] [2019-12-07 18:19:12,332 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:12,333 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:19:12,333 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1541850059] [2019-12-07 18:19:12,333 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:19:12,333 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:12,333 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:19:12,333 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:12,334 INFO L87 Difference]: Start difference. First operand 301489 states and 1222745 transitions. Second operand 3 states. [2019-12-07 18:19:12,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:12,489 INFO L93 Difference]: Finished difference Result 53586 states and 171749 transitions. [2019-12-07 18:19:12,490 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:19:12,490 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2019-12-07 18:19:12,490 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:12,570 INFO L225 Difference]: With dead ends: 53586 [2019-12-07 18:19:12,571 INFO L226 Difference]: Without dead ends: 53586 [2019-12-07 18:19:12,571 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:12,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53586 states. [2019-12-07 18:19:13,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53586 to 53586. [2019-12-07 18:19:13,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53586 states. [2019-12-07 18:19:13,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53586 states to 53586 states and 171749 transitions. [2019-12-07 18:19:13,412 INFO L78 Accepts]: Start accepts. Automaton has 53586 states and 171749 transitions. Word has length 19 [2019-12-07 18:19:13,412 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:13,412 INFO L462 AbstractCegarLoop]: Abstraction has 53586 states and 171749 transitions. [2019-12-07 18:19:13,412 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:19:13,412 INFO L276 IsEmpty]: Start isEmpty. Operand 53586 states and 171749 transitions. [2019-12-07 18:19:13,421 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 18:19:13,421 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:13,421 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:13,421 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:13,421 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:13,421 INFO L82 PathProgramCache]: Analyzing trace with hash -989401703, now seen corresponding path program 1 times [2019-12-07 18:19:13,422 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:13,422 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2085968899] [2019-12-07 18:19:13,422 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:13,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:13,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:13,482 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2085968899] [2019-12-07 18:19:13,482 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:13,482 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:19:13,483 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [189594641] [2019-12-07 18:19:13,483 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:19:13,483 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:13,483 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:19:13,484 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:13,484 INFO L87 Difference]: Start difference. First operand 53586 states and 171749 transitions. Second operand 5 states. [2019-12-07 18:19:13,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:13,948 INFO L93 Difference]: Finished difference Result 68610 states and 216432 transitions. [2019-12-07 18:19:13,949 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:19:13,949 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 22 [2019-12-07 18:19:13,949 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:14,047 INFO L225 Difference]: With dead ends: 68610 [2019-12-07 18:19:14,047 INFO L226 Difference]: Without dead ends: 68561 [2019-12-07 18:19:14,048 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 0 SyntacticMatches, 3 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:19:14,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68561 states. [2019-12-07 18:19:14,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68561 to 53771. [2019-12-07 18:19:14,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53771 states. [2019-12-07 18:19:15,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53771 states to 53771 states and 172017 transitions. [2019-12-07 18:19:15,086 INFO L78 Accepts]: Start accepts. Automaton has 53771 states and 172017 transitions. Word has length 22 [2019-12-07 18:19:15,086 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:15,086 INFO L462 AbstractCegarLoop]: Abstraction has 53771 states and 172017 transitions. [2019-12-07 18:19:15,086 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:19:15,087 INFO L276 IsEmpty]: Start isEmpty. Operand 53771 states and 172017 transitions. [2019-12-07 18:19:15,100 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 18:19:15,100 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:15,101 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:15,101 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:15,101 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:15,101 INFO L82 PathProgramCache]: Analyzing trace with hash -2090054503, now seen corresponding path program 1 times [2019-12-07 18:19:15,101 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:15,101 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806303803] [2019-12-07 18:19:15,101 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:15,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:15,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:15,150 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1806303803] [2019-12-07 18:19:15,150 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:15,151 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:19:15,151 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1383191157] [2019-12-07 18:19:15,151 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:19:15,151 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:15,151 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:19:15,151 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:15,152 INFO L87 Difference]: Start difference. First operand 53771 states and 172017 transitions. Second operand 5 states. [2019-12-07 18:19:15,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:15,604 INFO L93 Difference]: Finished difference Result 74631 states and 234595 transitions. [2019-12-07 18:19:15,605 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:19:15,605 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 25 [2019-12-07 18:19:15,605 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:15,711 INFO L225 Difference]: With dead ends: 74631 [2019-12-07 18:19:15,711 INFO L226 Difference]: Without dead ends: 74618 [2019-12-07 18:19:15,711 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:19:16,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74618 states. [2019-12-07 18:19:16,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74618 to 64019. [2019-12-07 18:19:16,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64019 states. [2019-12-07 18:19:17,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64019 states to 64019 states and 203607 transitions. [2019-12-07 18:19:17,010 INFO L78 Accepts]: Start accepts. Automaton has 64019 states and 203607 transitions. Word has length 25 [2019-12-07 18:19:17,010 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:17,010 INFO L462 AbstractCegarLoop]: Abstraction has 64019 states and 203607 transitions. [2019-12-07 18:19:17,010 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:19:17,010 INFO L276 IsEmpty]: Start isEmpty. Operand 64019 states and 203607 transitions. [2019-12-07 18:19:17,027 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 18:19:17,027 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:17,028 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:17,028 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:17,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:17,028 INFO L82 PathProgramCache]: Analyzing trace with hash 1906532401, now seen corresponding path program 1 times [2019-12-07 18:19:17,028 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:17,028 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [45829615] [2019-12-07 18:19:17,028 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:17,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:17,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:17,052 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [45829615] [2019-12-07 18:19:17,052 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:17,052 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:19:17,052 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [161304217] [2019-12-07 18:19:17,052 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:19:17,053 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:17,053 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:19:17,053 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:17,053 INFO L87 Difference]: Start difference. First operand 64019 states and 203607 transitions. Second operand 3 states. [2019-12-07 18:19:17,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:17,261 INFO L93 Difference]: Finished difference Result 83290 states and 260883 transitions. [2019-12-07 18:19:17,261 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:19:17,262 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 18:19:17,262 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:17,379 INFO L225 Difference]: With dead ends: 83290 [2019-12-07 18:19:17,379 INFO L226 Difference]: Without dead ends: 83290 [2019-12-07 18:19:17,380 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:17,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83290 states. [2019-12-07 18:19:18,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83290 to 68773. [2019-12-07 18:19:18,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68773 states. [2019-12-07 18:19:18,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68773 states to 68773 states and 217741 transitions. [2019-12-07 18:19:18,605 INFO L78 Accepts]: Start accepts. Automaton has 68773 states and 217741 transitions. Word has length 27 [2019-12-07 18:19:18,605 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:18,605 INFO L462 AbstractCegarLoop]: Abstraction has 68773 states and 217741 transitions. [2019-12-07 18:19:18,605 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:19:18,606 INFO L276 IsEmpty]: Start isEmpty. Operand 68773 states and 217741 transitions. [2019-12-07 18:19:18,624 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 18:19:18,624 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:18,624 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:18,624 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:18,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:18,625 INFO L82 PathProgramCache]: Analyzing trace with hash 1466938041, now seen corresponding path program 1 times [2019-12-07 18:19:18,625 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:18,625 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [271493932] [2019-12-07 18:19:18,625 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:18,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:18,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:18,693 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [271493932] [2019-12-07 18:19:18,693 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:18,693 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:19:18,694 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1448400725] [2019-12-07 18:19:18,694 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:19:18,694 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:18,694 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:19:18,694 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:19:18,694 INFO L87 Difference]: Start difference. First operand 68773 states and 217741 transitions. Second operand 6 states. [2019-12-07 18:19:19,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:19,588 INFO L93 Difference]: Finished difference Result 161524 states and 504565 transitions. [2019-12-07 18:19:19,589 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 18:19:19,589 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 27 [2019-12-07 18:19:19,589 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:19,817 INFO L225 Difference]: With dead ends: 161524 [2019-12-07 18:19:19,818 INFO L226 Difference]: Without dead ends: 161395 [2019-12-07 18:19:19,818 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=71, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:19:20,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161395 states. [2019-12-07 18:19:21,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161395 to 88335. [2019-12-07 18:19:21,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88335 states. [2019-12-07 18:19:22,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88335 states to 88335 states and 283628 transitions. [2019-12-07 18:19:22,002 INFO L78 Accepts]: Start accepts. Automaton has 88335 states and 283628 transitions. Word has length 27 [2019-12-07 18:19:22,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:22,002 INFO L462 AbstractCegarLoop]: Abstraction has 88335 states and 283628 transitions. [2019-12-07 18:19:22,002 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:19:22,002 INFO L276 IsEmpty]: Start isEmpty. Operand 88335 states and 283628 transitions. [2019-12-07 18:19:22,022 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 18:19:22,022 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:22,022 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:22,022 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:22,022 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:22,022 INFO L82 PathProgramCache]: Analyzing trace with hash -1177717026, now seen corresponding path program 1 times [2019-12-07 18:19:22,022 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:22,023 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [300536244] [2019-12-07 18:19:22,023 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:22,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:22,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:22,098 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [300536244] [2019-12-07 18:19:22,098 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:22,098 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:19:22,098 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [540390133] [2019-12-07 18:19:22,098 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:19:22,099 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:22,099 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:19:22,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:19:22,099 INFO L87 Difference]: Start difference. First operand 88335 states and 283628 transitions. Second operand 6 states. [2019-12-07 18:19:22,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:22,885 INFO L93 Difference]: Finished difference Result 136862 states and 426977 transitions. [2019-12-07 18:19:22,886 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 18:19:22,886 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 28 [2019-12-07 18:19:22,886 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:23,091 INFO L225 Difference]: With dead ends: 136862 [2019-12-07 18:19:23,091 INFO L226 Difference]: Without dead ends: 136798 [2019-12-07 18:19:23,091 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=71, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:19:23,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136798 states. [2019-12-07 18:19:24,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136798 to 88027. [2019-12-07 18:19:24,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88027 states. [2019-12-07 18:19:25,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88027 states to 88027 states and 282986 transitions. [2019-12-07 18:19:25,007 INFO L78 Accepts]: Start accepts. Automaton has 88027 states and 282986 transitions. Word has length 28 [2019-12-07 18:19:25,008 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:25,008 INFO L462 AbstractCegarLoop]: Abstraction has 88027 states and 282986 transitions. [2019-12-07 18:19:25,008 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:19:25,008 INFO L276 IsEmpty]: Start isEmpty. Operand 88027 states and 282986 transitions. [2019-12-07 18:19:25,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2019-12-07 18:19:25,038 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:25,038 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:25,038 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:25,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:25,039 INFO L82 PathProgramCache]: Analyzing trace with hash 361978144, now seen corresponding path program 1 times [2019-12-07 18:19:25,039 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:25,039 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [164299218] [2019-12-07 18:19:25,039 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:25,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:25,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:25,092 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [164299218] [2019-12-07 18:19:25,092 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:25,092 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:19:25,092 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1330650715] [2019-12-07 18:19:25,092 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:19:25,092 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:25,093 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:19:25,093 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:19:25,093 INFO L87 Difference]: Start difference. First operand 88027 states and 282986 transitions. Second operand 4 states. [2019-12-07 18:19:25,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:25,496 INFO L93 Difference]: Finished difference Result 140276 states and 454845 transitions. [2019-12-07 18:19:25,497 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:19:25,497 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 30 [2019-12-07 18:19:25,497 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:25,597 INFO L225 Difference]: With dead ends: 140276 [2019-12-07 18:19:25,598 INFO L226 Difference]: Without dead ends: 67488 [2019-12-07 18:19:25,598 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:19:25,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67488 states. [2019-12-07 18:19:26,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67488 to 65314. [2019-12-07 18:19:26,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65314 states. [2019-12-07 18:19:26,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65314 states to 65314 states and 208511 transitions. [2019-12-07 18:19:26,872 INFO L78 Accepts]: Start accepts. Automaton has 65314 states and 208511 transitions. Word has length 30 [2019-12-07 18:19:26,873 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:26,873 INFO L462 AbstractCegarLoop]: Abstraction has 65314 states and 208511 transitions. [2019-12-07 18:19:26,873 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:19:26,873 INFO L276 IsEmpty]: Start isEmpty. Operand 65314 states and 208511 transitions. [2019-12-07 18:19:26,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 18:19:26,893 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:26,894 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:26,894 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:26,894 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:26,894 INFO L82 PathProgramCache]: Analyzing trace with hash 1788536026, now seen corresponding path program 1 times [2019-12-07 18:19:26,894 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:26,894 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [833691707] [2019-12-07 18:19:26,894 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:26,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:26,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:26,926 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [833691707] [2019-12-07 18:19:26,926 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:26,926 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:19:26,926 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [732624794] [2019-12-07 18:19:26,927 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:19:26,927 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:26,927 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:19:26,927 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:19:26,927 INFO L87 Difference]: Start difference. First operand 65314 states and 208511 transitions. Second operand 4 states. [2019-12-07 18:19:27,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:27,015 INFO L93 Difference]: Finished difference Result 25706 states and 78644 transitions. [2019-12-07 18:19:27,015 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:19:27,015 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 31 [2019-12-07 18:19:27,016 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:27,046 INFO L225 Difference]: With dead ends: 25706 [2019-12-07 18:19:27,047 INFO L226 Difference]: Without dead ends: 25689 [2019-12-07 18:19:27,047 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:19:27,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25689 states. [2019-12-07 18:19:27,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25689 to 23461. [2019-12-07 18:19:27,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23461 states. [2019-12-07 18:19:27,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23461 states to 23461 states and 73105 transitions. [2019-12-07 18:19:27,395 INFO L78 Accepts]: Start accepts. Automaton has 23461 states and 73105 transitions. Word has length 31 [2019-12-07 18:19:27,395 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:27,395 INFO L462 AbstractCegarLoop]: Abstraction has 23461 states and 73105 transitions. [2019-12-07 18:19:27,395 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:19:27,395 INFO L276 IsEmpty]: Start isEmpty. Operand 23461 states and 73105 transitions. [2019-12-07 18:19:27,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 18:19:27,411 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:27,411 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:27,411 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:27,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:27,412 INFO L82 PathProgramCache]: Analyzing trace with hash 1088633804, now seen corresponding path program 1 times [2019-12-07 18:19:27,412 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:27,412 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328867045] [2019-12-07 18:19:27,412 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:27,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:27,483 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:27,483 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328867045] [2019-12-07 18:19:27,483 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:27,483 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:19:27,483 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1116552671] [2019-12-07 18:19:27,484 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:19:27,484 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:27,484 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:19:27,484 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:19:27,484 INFO L87 Difference]: Start difference. First operand 23461 states and 73105 transitions. Second operand 7 states. [2019-12-07 18:19:28,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:28,330 INFO L93 Difference]: Finished difference Result 46299 states and 137696 transitions. [2019-12-07 18:19:28,331 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 18:19:28,331 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 33 [2019-12-07 18:19:28,331 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:28,393 INFO L225 Difference]: With dead ends: 46299 [2019-12-07 18:19:28,393 INFO L226 Difference]: Without dead ends: 46299 [2019-12-07 18:19:28,393 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 82 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=117, Invalid=303, Unknown=0, NotChecked=0, Total=420 [2019-12-07 18:19:28,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46299 states. [2019-12-07 18:19:28,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46299 to 23277. [2019-12-07 18:19:28,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23277 states. [2019-12-07 18:19:28,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23277 states to 23277 states and 72459 transitions. [2019-12-07 18:19:28,901 INFO L78 Accepts]: Start accepts. Automaton has 23277 states and 72459 transitions. Word has length 33 [2019-12-07 18:19:28,901 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:28,901 INFO L462 AbstractCegarLoop]: Abstraction has 23277 states and 72459 transitions. [2019-12-07 18:19:28,901 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:19:28,902 INFO L276 IsEmpty]: Start isEmpty. Operand 23277 states and 72459 transitions. [2019-12-07 18:19:28,919 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 18:19:28,919 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:28,919 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:28,919 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:28,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:28,919 INFO L82 PathProgramCache]: Analyzing trace with hash 1082826604, now seen corresponding path program 1 times [2019-12-07 18:19:28,919 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:28,920 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [229778957] [2019-12-07 18:19:28,920 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:28,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:28,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:28,946 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [229778957] [2019-12-07 18:19:28,946 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:28,946 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:19:28,947 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [885794138] [2019-12-07 18:19:28,947 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:19:28,947 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:28,947 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:19:28,947 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:28,947 INFO L87 Difference]: Start difference. First operand 23277 states and 72459 transitions. Second operand 3 states. [2019-12-07 18:19:29,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:29,031 INFO L93 Difference]: Finished difference Result 28556 states and 85609 transitions. [2019-12-07 18:19:29,032 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:19:29,032 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 33 [2019-12-07 18:19:29,032 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:29,065 INFO L225 Difference]: With dead ends: 28556 [2019-12-07 18:19:29,065 INFO L226 Difference]: Without dead ends: 28556 [2019-12-07 18:19:29,065 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:29,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28556 states. [2019-12-07 18:19:29,364 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28556 to 20083. [2019-12-07 18:19:29,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20083 states. [2019-12-07 18:19:29,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20083 states to 20083 states and 60491 transitions. [2019-12-07 18:19:29,393 INFO L78 Accepts]: Start accepts. Automaton has 20083 states and 60491 transitions. Word has length 33 [2019-12-07 18:19:29,393 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:29,393 INFO L462 AbstractCegarLoop]: Abstraction has 20083 states and 60491 transitions. [2019-12-07 18:19:29,393 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:19:29,393 INFO L276 IsEmpty]: Start isEmpty. Operand 20083 states and 60491 transitions. [2019-12-07 18:19:29,407 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 18:19:29,407 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:29,407 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:29,407 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:29,407 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:29,408 INFO L82 PathProgramCache]: Analyzing trace with hash 1090977820, now seen corresponding path program 2 times [2019-12-07 18:19:29,408 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:29,408 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [197935469] [2019-12-07 18:19:29,408 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:29,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:29,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:29,491 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [197935469] [2019-12-07 18:19:29,491 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:29,491 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:19:29,491 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1576732334] [2019-12-07 18:19:29,491 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 18:19:29,492 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:29,492 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 18:19:29,492 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:19:29,492 INFO L87 Difference]: Start difference. First operand 20083 states and 60491 transitions. Second operand 8 states. [2019-12-07 18:19:30,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:30,967 INFO L93 Difference]: Finished difference Result 43718 states and 127185 transitions. [2019-12-07 18:19:30,968 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2019-12-07 18:19:30,968 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 33 [2019-12-07 18:19:30,969 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:31,029 INFO L225 Difference]: With dead ends: 43718 [2019-12-07 18:19:31,029 INFO L226 Difference]: Without dead ends: 43718 [2019-12-07 18:19:31,030 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 155 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=161, Invalid=489, Unknown=0, NotChecked=0, Total=650 [2019-12-07 18:19:31,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43718 states. [2019-12-07 18:19:31,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43718 to 20012. [2019-12-07 18:19:31,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20012 states. [2019-12-07 18:19:31,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20012 states to 20012 states and 60280 transitions. [2019-12-07 18:19:31,462 INFO L78 Accepts]: Start accepts. Automaton has 20012 states and 60280 transitions. Word has length 33 [2019-12-07 18:19:31,462 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:31,462 INFO L462 AbstractCegarLoop]: Abstraction has 20012 states and 60280 transitions. [2019-12-07 18:19:31,462 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 18:19:31,463 INFO L276 IsEmpty]: Start isEmpty. Operand 20012 states and 60280 transitions. [2019-12-07 18:19:31,477 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 18:19:31,477 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:31,477 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:31,477 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:31,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:31,477 INFO L82 PathProgramCache]: Analyzing trace with hash 791261483, now seen corresponding path program 1 times [2019-12-07 18:19:31,478 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:31,478 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1019645705] [2019-12-07 18:19:31,478 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:31,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:31,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:31,547 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1019645705] [2019-12-07 18:19:31,547 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:31,548 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:19:31,548 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [710557617] [2019-12-07 18:19:31,548 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:19:31,548 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:31,548 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:19:31,548 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:19:31,548 INFO L87 Difference]: Start difference. First operand 20012 states and 60280 transitions. Second operand 7 states. [2019-12-07 18:19:32,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:32,301 INFO L93 Difference]: Finished difference Result 31547 states and 92567 transitions. [2019-12-07 18:19:32,301 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 18:19:32,301 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 34 [2019-12-07 18:19:32,301 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:32,334 INFO L225 Difference]: With dead ends: 31547 [2019-12-07 18:19:32,334 INFO L226 Difference]: Without dead ends: 31547 [2019-12-07 18:19:32,335 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 62 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=89, Invalid=253, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:19:32,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31547 states. [2019-12-07 18:19:32,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31547 to 19642. [2019-12-07 18:19:32,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19642 states. [2019-12-07 18:19:32,716 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19642 states to 19642 states and 59394 transitions. [2019-12-07 18:19:32,716 INFO L78 Accepts]: Start accepts. Automaton has 19642 states and 59394 transitions. Word has length 34 [2019-12-07 18:19:32,716 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:32,717 INFO L462 AbstractCegarLoop]: Abstraction has 19642 states and 59394 transitions. [2019-12-07 18:19:32,717 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:19:32,717 INFO L276 IsEmpty]: Start isEmpty. Operand 19642 states and 59394 transitions. [2019-12-07 18:19:32,730 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 18:19:32,730 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:32,730 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:32,730 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:32,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:32,730 INFO L82 PathProgramCache]: Analyzing trace with hash -1244987983, now seen corresponding path program 2 times [2019-12-07 18:19:32,731 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:32,731 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267488989] [2019-12-07 18:19:32,731 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:32,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:32,805 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:32,805 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1267488989] [2019-12-07 18:19:32,806 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:32,806 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:19:32,806 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1165673043] [2019-12-07 18:19:32,806 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:19:32,806 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:32,806 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:19:32,806 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:19:32,806 INFO L87 Difference]: Start difference. First operand 19642 states and 59394 transitions. Second operand 7 states. [2019-12-07 18:19:33,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:33,614 INFO L93 Difference]: Finished difference Result 37369 states and 107541 transitions. [2019-12-07 18:19:33,614 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 18:19:33,614 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 34 [2019-12-07 18:19:33,614 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:33,653 INFO L225 Difference]: With dead ends: 37369 [2019-12-07 18:19:33,653 INFO L226 Difference]: Without dead ends: 37369 [2019-12-07 18:19:33,653 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 0 SyntacticMatches, 4 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 58 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=81, Invalid=225, Unknown=0, NotChecked=0, Total=306 [2019-12-07 18:19:33,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37369 states. [2019-12-07 18:19:34,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37369 to 19572. [2019-12-07 18:19:34,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19572 states. [2019-12-07 18:19:34,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19572 states to 19572 states and 59180 transitions. [2019-12-07 18:19:34,036 INFO L78 Accepts]: Start accepts. Automaton has 19572 states and 59180 transitions. Word has length 34 [2019-12-07 18:19:34,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:34,036 INFO L462 AbstractCegarLoop]: Abstraction has 19572 states and 59180 transitions. [2019-12-07 18:19:34,036 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:19:34,036 INFO L276 IsEmpty]: Start isEmpty. Operand 19572 states and 59180 transitions. [2019-12-07 18:19:34,050 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 18:19:34,050 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:34,051 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:34,051 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:34,051 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:34,051 INFO L82 PathProgramCache]: Analyzing trace with hash -851207469, now seen corresponding path program 3 times [2019-12-07 18:19:34,051 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:34,051 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1931981079] [2019-12-07 18:19:34,051 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:34,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:34,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:34,198 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1931981079] [2019-12-07 18:19:34,198 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:34,199 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:19:34,199 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1566661196] [2019-12-07 18:19:34,199 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 18:19:34,199 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:34,199 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 18:19:34,199 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=65, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:19:34,199 INFO L87 Difference]: Start difference. First operand 19572 states and 59180 transitions. Second operand 10 states. [2019-12-07 18:19:36,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:36,044 INFO L93 Difference]: Finished difference Result 33392 states and 97289 transitions. [2019-12-07 18:19:36,044 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2019-12-07 18:19:36,045 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 34 [2019-12-07 18:19:36,045 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:36,087 INFO L225 Difference]: With dead ends: 33392 [2019-12-07 18:19:36,088 INFO L226 Difference]: Without dead ends: 33392 [2019-12-07 18:19:36,088 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 151 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=156, Invalid=494, Unknown=0, NotChecked=0, Total=650 [2019-12-07 18:19:36,190 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33392 states. [2019-12-07 18:19:36,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33392 to 19330. [2019-12-07 18:19:36,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19330 states. [2019-12-07 18:19:36,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19330 states to 19330 states and 58490 transitions. [2019-12-07 18:19:36,443 INFO L78 Accepts]: Start accepts. Automaton has 19330 states and 58490 transitions. Word has length 34 [2019-12-07 18:19:36,443 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:36,443 INFO L462 AbstractCegarLoop]: Abstraction has 19330 states and 58490 transitions. [2019-12-07 18:19:36,443 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 18:19:36,443 INFO L276 IsEmpty]: Start isEmpty. Operand 19330 states and 58490 transitions. [2019-12-07 18:19:36,458 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-12-07 18:19:36,458 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:36,458 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:36,459 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:36,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:36,459 INFO L82 PathProgramCache]: Analyzing trace with hash 217064285, now seen corresponding path program 1 times [2019-12-07 18:19:36,459 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:36,459 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [918021162] [2019-12-07 18:19:36,459 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:36,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:36,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:36,500 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [918021162] [2019-12-07 18:19:36,500 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:36,500 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:19:36,500 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1010132351] [2019-12-07 18:19:36,500 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:19:36,500 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:36,500 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:19:36,501 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:36,501 INFO L87 Difference]: Start difference. First operand 19330 states and 58490 transitions. Second operand 5 states. [2019-12-07 18:19:36,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:36,924 INFO L93 Difference]: Finished difference Result 30678 states and 91368 transitions. [2019-12-07 18:19:36,925 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:19:36,925 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 41 [2019-12-07 18:19:36,925 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:36,969 INFO L225 Difference]: With dead ends: 30678 [2019-12-07 18:19:36,969 INFO L226 Difference]: Without dead ends: 30678 [2019-12-07 18:19:36,970 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:19:37,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30678 states. [2019-12-07 18:19:37,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30678 to 26831. [2019-12-07 18:19:37,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26831 states. [2019-12-07 18:19:37,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26831 states to 26831 states and 80628 transitions. [2019-12-07 18:19:37,388 INFO L78 Accepts]: Start accepts. Automaton has 26831 states and 80628 transitions. Word has length 41 [2019-12-07 18:19:37,388 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:37,388 INFO L462 AbstractCegarLoop]: Abstraction has 26831 states and 80628 transitions. [2019-12-07 18:19:37,388 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:19:37,388 INFO L276 IsEmpty]: Start isEmpty. Operand 26831 states and 80628 transitions. [2019-12-07 18:19:37,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-12-07 18:19:37,414 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:37,414 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:37,414 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:37,414 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:37,415 INFO L82 PathProgramCache]: Analyzing trace with hash 1862086557, now seen corresponding path program 2 times [2019-12-07 18:19:37,415 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:37,415 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1581307065] [2019-12-07 18:19:37,415 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:37,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:37,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:37,455 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1581307065] [2019-12-07 18:19:37,455 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:37,456 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:19:37,456 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [83285350] [2019-12-07 18:19:37,456 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:19:37,456 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:37,456 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:19:37,456 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:37,456 INFO L87 Difference]: Start difference. First operand 26831 states and 80628 transitions. Second operand 5 states. [2019-12-07 18:19:37,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:37,529 INFO L93 Difference]: Finished difference Result 25175 states and 77019 transitions. [2019-12-07 18:19:37,530 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:19:37,530 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 41 [2019-12-07 18:19:37,530 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:37,555 INFO L225 Difference]: With dead ends: 25175 [2019-12-07 18:19:37,555 INFO L226 Difference]: Without dead ends: 23375 [2019-12-07 18:19:37,555 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:37,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23375 states. [2019-12-07 18:19:37,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23375 to 15041. [2019-12-07 18:19:37,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15041 states. [2019-12-07 18:19:37,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15041 states to 15041 states and 46537 transitions. [2019-12-07 18:19:37,825 INFO L78 Accepts]: Start accepts. Automaton has 15041 states and 46537 transitions. Word has length 41 [2019-12-07 18:19:37,825 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:37,825 INFO L462 AbstractCegarLoop]: Abstraction has 15041 states and 46537 transitions. [2019-12-07 18:19:37,825 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:19:37,825 INFO L276 IsEmpty]: Start isEmpty. Operand 15041 states and 46537 transitions. [2019-12-07 18:19:37,837 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:19:37,838 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:37,838 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:37,838 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:37,838 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:37,838 INFO L82 PathProgramCache]: Analyzing trace with hash -392919645, now seen corresponding path program 1 times [2019-12-07 18:19:37,838 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:37,838 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [717961616] [2019-12-07 18:19:37,838 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:37,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:37,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:37,914 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [717961616] [2019-12-07 18:19:37,914 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:37,914 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 18:19:37,914 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [824948495] [2019-12-07 18:19:37,915 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:19:37,915 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:37,915 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:19:37,915 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:19:37,915 INFO L87 Difference]: Start difference. First operand 15041 states and 46537 transitions. Second operand 7 states. [2019-12-07 18:19:39,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:39,378 INFO L93 Difference]: Finished difference Result 30983 states and 94534 transitions. [2019-12-07 18:19:39,379 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 18:19:39,379 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 65 [2019-12-07 18:19:39,380 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:39,428 INFO L225 Difference]: With dead ends: 30983 [2019-12-07 18:19:39,428 INFO L226 Difference]: Without dead ends: 30983 [2019-12-07 18:19:39,428 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 7 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=81, Invalid=225, Unknown=0, NotChecked=0, Total=306 [2019-12-07 18:19:39,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30983 states. [2019-12-07 18:19:39,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30983 to 15614. [2019-12-07 18:19:39,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15614 states. [2019-12-07 18:19:39,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15614 states to 15614 states and 48371 transitions. [2019-12-07 18:19:39,778 INFO L78 Accepts]: Start accepts. Automaton has 15614 states and 48371 transitions. Word has length 65 [2019-12-07 18:19:39,779 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:39,779 INFO L462 AbstractCegarLoop]: Abstraction has 15614 states and 48371 transitions. [2019-12-07 18:19:39,779 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:19:39,779 INFO L276 IsEmpty]: Start isEmpty. Operand 15614 states and 48371 transitions. [2019-12-07 18:19:39,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:19:39,791 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:39,791 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:39,791 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:39,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:39,792 INFO L82 PathProgramCache]: Analyzing trace with hash 1475299999, now seen corresponding path program 2 times [2019-12-07 18:19:39,792 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:39,792 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694870785] [2019-12-07 18:19:39,792 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:39,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:39,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:39,918 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [694870785] [2019-12-07 18:19:39,918 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:39,919 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:19:39,919 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1075475794] [2019-12-07 18:19:39,919 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 18:19:39,919 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:39,919 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 18:19:39,919 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:19:39,919 INFO L87 Difference]: Start difference. First operand 15614 states and 48371 transitions. Second operand 8 states. [2019-12-07 18:19:41,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:41,459 INFO L93 Difference]: Finished difference Result 33560 states and 102602 transitions. [2019-12-07 18:19:41,459 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 18:19:41,459 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 65 [2019-12-07 18:19:41,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:41,496 INFO L225 Difference]: With dead ends: 33560 [2019-12-07 18:19:41,497 INFO L226 Difference]: Without dead ends: 33560 [2019-12-07 18:19:41,497 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 6 SyntacticMatches, 1 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 65 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=99, Invalid=281, Unknown=0, NotChecked=0, Total=380 [2019-12-07 18:19:41,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33560 states. [2019-12-07 18:19:41,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33560 to 15632. [2019-12-07 18:19:41,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15632 states. [2019-12-07 18:19:41,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15632 states to 15632 states and 48422 transitions. [2019-12-07 18:19:41,865 INFO L78 Accepts]: Start accepts. Automaton has 15632 states and 48422 transitions. Word has length 65 [2019-12-07 18:19:41,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:41,865 INFO L462 AbstractCegarLoop]: Abstraction has 15632 states and 48422 transitions. [2019-12-07 18:19:41,865 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 18:19:41,866 INFO L276 IsEmpty]: Start isEmpty. Operand 15632 states and 48422 transitions. [2019-12-07 18:19:41,878 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:19:41,879 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:41,879 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:41,879 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:41,879 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:41,879 INFO L82 PathProgramCache]: Analyzing trace with hash 1581772465, now seen corresponding path program 3 times [2019-12-07 18:19:41,879 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:41,879 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1501210931] [2019-12-07 18:19:41,879 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:41,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:41,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:41,926 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1501210931] [2019-12-07 18:19:41,926 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:41,926 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:19:41,926 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [19839181] [2019-12-07 18:19:41,927 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:19:41,927 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:41,927 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:19:41,927 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:41,927 INFO L87 Difference]: Start difference. First operand 15632 states and 48422 transitions. Second operand 5 states. [2019-12-07 18:19:42,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:42,125 INFO L93 Difference]: Finished difference Result 17339 states and 53198 transitions. [2019-12-07 18:19:42,125 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:19:42,125 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 65 [2019-12-07 18:19:42,125 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:42,143 INFO L225 Difference]: With dead ends: 17339 [2019-12-07 18:19:42,143 INFO L226 Difference]: Without dead ends: 17339 [2019-12-07 18:19:42,143 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:19:42,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17339 states. [2019-12-07 18:19:42,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17339 to 15735. [2019-12-07 18:19:42,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15735 states. [2019-12-07 18:19:42,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15735 states to 15735 states and 48793 transitions. [2019-12-07 18:19:42,384 INFO L78 Accepts]: Start accepts. Automaton has 15735 states and 48793 transitions. Word has length 65 [2019-12-07 18:19:42,384 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:42,384 INFO L462 AbstractCegarLoop]: Abstraction has 15735 states and 48793 transitions. [2019-12-07 18:19:42,384 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:19:42,384 INFO L276 IsEmpty]: Start isEmpty. Operand 15735 states and 48793 transitions. [2019-12-07 18:19:42,397 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:19:42,397 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:42,398 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:42,398 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:42,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:42,398 INFO L82 PathProgramCache]: Analyzing trace with hash 30446035, now seen corresponding path program 4 times [2019-12-07 18:19:42,398 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:42,398 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [688293223] [2019-12-07 18:19:42,398 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:42,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:42,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:42,427 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [688293223] [2019-12-07 18:19:42,427 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:42,427 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:19:42,427 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1506841280] [2019-12-07 18:19:42,428 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:19:42,428 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:42,428 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:19:42,428 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:42,428 INFO L87 Difference]: Start difference. First operand 15735 states and 48793 transitions. Second operand 3 states. [2019-12-07 18:19:42,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:42,463 INFO L93 Difference]: Finished difference Result 14602 states and 44471 transitions. [2019-12-07 18:19:42,464 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:19:42,464 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 18:19:42,464 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:42,479 INFO L225 Difference]: With dead ends: 14602 [2019-12-07 18:19:42,479 INFO L226 Difference]: Without dead ends: 14602 [2019-12-07 18:19:42,479 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:42,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14602 states. [2019-12-07 18:19:42,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14602 to 14291. [2019-12-07 18:19:42,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14291 states. [2019-12-07 18:19:42,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14291 states to 14291 states and 43581 transitions. [2019-12-07 18:19:42,679 INFO L78 Accepts]: Start accepts. Automaton has 14291 states and 43581 transitions. Word has length 65 [2019-12-07 18:19:42,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:42,679 INFO L462 AbstractCegarLoop]: Abstraction has 14291 states and 43581 transitions. [2019-12-07 18:19:42,679 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:19:42,679 INFO L276 IsEmpty]: Start isEmpty. Operand 14291 states and 43581 transitions. [2019-12-07 18:19:42,691 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 18:19:42,691 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:42,691 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:42,691 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:42,691 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:42,691 INFO L82 PathProgramCache]: Analyzing trace with hash 712249250, now seen corresponding path program 1 times [2019-12-07 18:19:42,691 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:42,691 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [991942819] [2019-12-07 18:19:42,692 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:42,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:42,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:42,789 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [991942819] [2019-12-07 18:19:42,789 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:42,790 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:19:42,790 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [655181264] [2019-12-07 18:19:42,790 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 18:19:42,790 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:42,790 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 18:19:42,790 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:19:42,790 INFO L87 Difference]: Start difference. First operand 14291 states and 43581 transitions. Second operand 9 states. [2019-12-07 18:19:44,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:44,728 INFO L93 Difference]: Finished difference Result 30862 states and 92399 transitions. [2019-12-07 18:19:44,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2019-12-07 18:19:44,728 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 66 [2019-12-07 18:19:44,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:44,772 INFO L225 Difference]: With dead ends: 30862 [2019-12-07 18:19:44,773 INFO L226 Difference]: Without dead ends: 30862 [2019-12-07 18:19:44,773 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 8 SyntacticMatches, 2 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 138 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=140, Invalid=562, Unknown=0, NotChecked=0, Total=702 [2019-12-07 18:19:44,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30862 states. [2019-12-07 18:19:45,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30862 to 14278. [2019-12-07 18:19:45,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14278 states. [2019-12-07 18:19:45,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14278 states to 14278 states and 43519 transitions. [2019-12-07 18:19:45,106 INFO L78 Accepts]: Start accepts. Automaton has 14278 states and 43519 transitions. Word has length 66 [2019-12-07 18:19:45,106 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:45,106 INFO L462 AbstractCegarLoop]: Abstraction has 14278 states and 43519 transitions. [2019-12-07 18:19:45,106 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 18:19:45,106 INFO L276 IsEmpty]: Start isEmpty. Operand 14278 states and 43519 transitions. [2019-12-07 18:19:45,118 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 18:19:45,118 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:45,118 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:45,118 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:45,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:45,119 INFO L82 PathProgramCache]: Analyzing trace with hash 257156348, now seen corresponding path program 2 times [2019-12-07 18:19:45,119 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:45,119 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1563222197] [2019-12-07 18:19:45,119 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:45,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:45,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:45,201 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1563222197] [2019-12-07 18:19:45,201 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:45,201 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:19:45,202 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1441246465] [2019-12-07 18:19:45,202 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 18:19:45,202 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:45,202 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 18:19:45,202 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:19:45,202 INFO L87 Difference]: Start difference. First operand 14278 states and 43519 transitions. Second operand 9 states. [2019-12-07 18:19:46,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:46,752 INFO L93 Difference]: Finished difference Result 34595 states and 102983 transitions. [2019-12-07 18:19:46,752 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2019-12-07 18:19:46,752 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 66 [2019-12-07 18:19:46,753 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:46,787 INFO L225 Difference]: With dead ends: 34595 [2019-12-07 18:19:46,787 INFO L226 Difference]: Without dead ends: 34595 [2019-12-07 18:19:46,788 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 9 SyntacticMatches, 2 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 450 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=283, Invalid=1277, Unknown=0, NotChecked=0, Total=1560 [2019-12-07 18:19:46,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34595 states. [2019-12-07 18:19:47,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34595 to 14074. [2019-12-07 18:19:47,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14074 states. [2019-12-07 18:19:47,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14074 states to 14074 states and 42897 transitions. [2019-12-07 18:19:47,142 INFO L78 Accepts]: Start accepts. Automaton has 14074 states and 42897 transitions. Word has length 66 [2019-12-07 18:19:47,142 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:47,142 INFO L462 AbstractCegarLoop]: Abstraction has 14074 states and 42897 transitions. [2019-12-07 18:19:47,142 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 18:19:47,142 INFO L276 IsEmpty]: Start isEmpty. Operand 14074 states and 42897 transitions. [2019-12-07 18:19:47,154 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 18:19:47,154 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:47,154 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:47,154 INFO L410 AbstractCegarLoop]: === Iteration 29 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:47,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:47,154 INFO L82 PathProgramCache]: Analyzing trace with hash 1254491896, now seen corresponding path program 3 times [2019-12-07 18:19:47,155 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:47,155 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [580795742] [2019-12-07 18:19:47,155 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:47,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:47,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:47,222 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [580795742] [2019-12-07 18:19:47,222 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:47,222 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:19:47,222 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1458925135] [2019-12-07 18:19:47,222 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:19:47,222 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:47,222 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:19:47,223 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:19:47,223 INFO L87 Difference]: Start difference. First operand 14074 states and 42897 transitions. Second operand 7 states. [2019-12-07 18:19:47,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:47,630 INFO L93 Difference]: Finished difference Result 56897 states and 171481 transitions. [2019-12-07 18:19:47,630 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 18:19:47,630 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 66 [2019-12-07 18:19:47,630 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:47,674 INFO L225 Difference]: With dead ends: 56897 [2019-12-07 18:19:47,674 INFO L226 Difference]: Without dead ends: 40231 [2019-12-07 18:19:47,674 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 50 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=78, Invalid=228, Unknown=0, NotChecked=0, Total=306 [2019-12-07 18:19:47,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40231 states. [2019-12-07 18:19:48,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40231 to 16660. [2019-12-07 18:19:48,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16660 states. [2019-12-07 18:19:48,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16660 states to 16660 states and 50284 transitions. [2019-12-07 18:19:48,058 INFO L78 Accepts]: Start accepts. Automaton has 16660 states and 50284 transitions. Word has length 66 [2019-12-07 18:19:48,059 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:48,059 INFO L462 AbstractCegarLoop]: Abstraction has 16660 states and 50284 transitions. [2019-12-07 18:19:48,059 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:19:48,059 INFO L276 IsEmpty]: Start isEmpty. Operand 16660 states and 50284 transitions. [2019-12-07 18:19:48,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 18:19:48,072 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:48,072 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:48,072 INFO L410 AbstractCegarLoop]: === Iteration 30 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:48,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:48,073 INFO L82 PathProgramCache]: Analyzing trace with hash 508796180, now seen corresponding path program 4 times [2019-12-07 18:19:48,073 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:48,073 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1178520234] [2019-12-07 18:19:48,073 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:48,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:48,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:48,128 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1178520234] [2019-12-07 18:19:48,128 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:48,128 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:19:48,128 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1498548821] [2019-12-07 18:19:48,128 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:19:48,128 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:48,128 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:19:48,128 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:19:48,129 INFO L87 Difference]: Start difference. First operand 16660 states and 50284 transitions. Second operand 4 states. [2019-12-07 18:19:48,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:48,204 INFO L93 Difference]: Finished difference Result 18784 states and 56734 transitions. [2019-12-07 18:19:48,205 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:19:48,205 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 66 [2019-12-07 18:19:48,205 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:48,223 INFO L225 Difference]: With dead ends: 18784 [2019-12-07 18:19:48,223 INFO L226 Difference]: Without dead ends: 18784 [2019-12-07 18:19:48,224 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:19:48,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18784 states. [2019-12-07 18:19:48,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18784 to 15382. [2019-12-07 18:19:48,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15382 states. [2019-12-07 18:19:48,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15382 states to 15382 states and 46702 transitions. [2019-12-07 18:19:48,464 INFO L78 Accepts]: Start accepts. Automaton has 15382 states and 46702 transitions. Word has length 66 [2019-12-07 18:19:48,464 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:48,464 INFO L462 AbstractCegarLoop]: Abstraction has 15382 states and 46702 transitions. [2019-12-07 18:19:48,464 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:19:48,464 INFO L276 IsEmpty]: Start isEmpty. Operand 15382 states and 46702 transitions. [2019-12-07 18:19:48,476 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:19:48,476 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:48,476 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:48,476 INFO L410 AbstractCegarLoop]: === Iteration 31 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:48,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:48,477 INFO L82 PathProgramCache]: Analyzing trace with hash -2089790483, now seen corresponding path program 1 times [2019-12-07 18:19:48,477 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:48,477 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [222307360] [2019-12-07 18:19:48,477 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:48,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:48,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:48,530 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [222307360] [2019-12-07 18:19:48,530 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:48,530 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:19:48,530 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1273070540] [2019-12-07 18:19:48,530 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:19:48,530 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:48,530 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:19:48,530 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:19:48,530 INFO L87 Difference]: Start difference. First operand 15382 states and 46702 transitions. Second operand 4 states. [2019-12-07 18:19:48,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:48,599 INFO L93 Difference]: Finished difference Result 27871 states and 84723 transitions. [2019-12-07 18:19:48,599 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:19:48,599 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 67 [2019-12-07 18:19:48,600 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:48,612 INFO L225 Difference]: With dead ends: 27871 [2019-12-07 18:19:48,613 INFO L226 Difference]: Without dead ends: 12635 [2019-12-07 18:19:48,613 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:19:48,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12635 states. [2019-12-07 18:19:48,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12635 to 12635. [2019-12-07 18:19:48,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12635 states. [2019-12-07 18:19:48,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12635 states to 12635 states and 38176 transitions. [2019-12-07 18:19:48,796 INFO L78 Accepts]: Start accepts. Automaton has 12635 states and 38176 transitions. Word has length 67 [2019-12-07 18:19:48,797 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:48,797 INFO L462 AbstractCegarLoop]: Abstraction has 12635 states and 38176 transitions. [2019-12-07 18:19:48,797 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:19:48,797 INFO L276 IsEmpty]: Start isEmpty. Operand 12635 states and 38176 transitions. [2019-12-07 18:19:48,807 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:19:48,807 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:48,808 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:48,808 INFO L410 AbstractCegarLoop]: === Iteration 32 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:48,808 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:48,808 INFO L82 PathProgramCache]: Analyzing trace with hash -2050480149, now seen corresponding path program 2 times [2019-12-07 18:19:48,808 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:48,808 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1520599590] [2019-12-07 18:19:48,808 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:48,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:48,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:48,915 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1520599590] [2019-12-07 18:19:48,915 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:48,915 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:19:48,915 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1837103608] [2019-12-07 18:19:48,915 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 18:19:48,915 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:48,915 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 18:19:48,915 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:19:48,915 INFO L87 Difference]: Start difference. First operand 12635 states and 38176 transitions. Second operand 10 states. [2019-12-07 18:19:49,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:49,289 INFO L93 Difference]: Finished difference Result 21523 states and 64693 transitions. [2019-12-07 18:19:49,289 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 18:19:49,289 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 67 [2019-12-07 18:19:49,289 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:49,308 INFO L225 Difference]: With dead ends: 21523 [2019-12-07 18:19:49,308 INFO L226 Difference]: Without dead ends: 20225 [2019-12-07 18:19:49,309 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 95 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=110, Invalid=442, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:19:49,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20225 states. [2019-12-07 18:19:49,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20225 to 16939. [2019-12-07 18:19:49,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16939 states. [2019-12-07 18:19:49,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16939 states to 16939 states and 50849 transitions. [2019-12-07 18:19:49,575 INFO L78 Accepts]: Start accepts. Automaton has 16939 states and 50849 transitions. Word has length 67 [2019-12-07 18:19:49,576 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:49,576 INFO L462 AbstractCegarLoop]: Abstraction has 16939 states and 50849 transitions. [2019-12-07 18:19:49,576 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 18:19:49,576 INFO L276 IsEmpty]: Start isEmpty. Operand 16939 states and 50849 transitions. [2019-12-07 18:19:49,588 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:19:49,589 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:49,589 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:49,589 INFO L410 AbstractCegarLoop]: === Iteration 33 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:49,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:49,589 INFO L82 PathProgramCache]: Analyzing trace with hash 13478945, now seen corresponding path program 3 times [2019-12-07 18:19:49,589 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:49,589 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [86457317] [2019-12-07 18:19:49,589 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:49,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:49,681 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:49,681 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [86457317] [2019-12-07 18:19:49,682 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:49,682 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:19:49,682 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1512282275] [2019-12-07 18:19:49,682 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 18:19:49,682 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:49,682 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 18:19:49,682 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:19:49,682 INFO L87 Difference]: Start difference. First operand 16939 states and 50849 transitions. Second operand 10 states. [2019-12-07 18:19:50,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:50,065 INFO L93 Difference]: Finished difference Result 21008 states and 62187 transitions. [2019-12-07 18:19:50,065 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 18:19:50,065 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 67 [2019-12-07 18:19:50,065 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:50,081 INFO L225 Difference]: With dead ends: 21008 [2019-12-07 18:19:50,081 INFO L226 Difference]: Without dead ends: 16219 [2019-12-07 18:19:50,082 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 72 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=100, Invalid=362, Unknown=0, NotChecked=0, Total=462 [2019-12-07 18:19:50,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16219 states. [2019-12-07 18:19:50,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16219 to 12978. [2019-12-07 18:19:50,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12978 states. [2019-12-07 18:19:50,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12978 states to 12978 states and 38837 transitions. [2019-12-07 18:19:50,284 INFO L78 Accepts]: Start accepts. Automaton has 12978 states and 38837 transitions. Word has length 67 [2019-12-07 18:19:50,284 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:50,285 INFO L462 AbstractCegarLoop]: Abstraction has 12978 states and 38837 transitions. [2019-12-07 18:19:50,285 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 18:19:50,285 INFO L276 IsEmpty]: Start isEmpty. Operand 12978 states and 38837 transitions. [2019-12-07 18:19:50,295 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:19:50,295 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:50,295 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:50,296 INFO L410 AbstractCegarLoop]: === Iteration 34 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:50,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:50,296 INFO L82 PathProgramCache]: Analyzing trace with hash 1111193301, now seen corresponding path program 4 times [2019-12-07 18:19:50,296 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:50,296 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1746016456] [2019-12-07 18:19:50,296 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:50,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:50,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:50,443 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1746016456] [2019-12-07 18:19:50,443 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:50,443 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:19:50,443 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2079436236] [2019-12-07 18:19:50,443 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:19:50,443 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:50,444 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:19:50,444 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:19:50,444 INFO L87 Difference]: Start difference. First operand 12978 states and 38837 transitions. Second operand 11 states. [2019-12-07 18:19:51,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:51,148 INFO L93 Difference]: Finished difference Result 20447 states and 61222 transitions. [2019-12-07 18:19:51,149 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2019-12-07 18:19:51,150 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 67 [2019-12-07 18:19:51,150 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:51,176 INFO L225 Difference]: With dead ends: 20447 [2019-12-07 18:19:51,177 INFO L226 Difference]: Without dead ends: 19149 [2019-12-07 18:19:51,177 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 263 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=220, Invalid=902, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 18:19:51,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19149 states. [2019-12-07 18:19:51,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19149 to 16901. [2019-12-07 18:19:51,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16901 states. [2019-12-07 18:19:51,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16901 states to 16901 states and 50424 transitions. [2019-12-07 18:19:51,436 INFO L78 Accepts]: Start accepts. Automaton has 16901 states and 50424 transitions. Word has length 67 [2019-12-07 18:19:51,436 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:51,436 INFO L462 AbstractCegarLoop]: Abstraction has 16901 states and 50424 transitions. [2019-12-07 18:19:51,436 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:19:51,436 INFO L276 IsEmpty]: Start isEmpty. Operand 16901 states and 50424 transitions. [2019-12-07 18:19:51,449 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:19:51,449 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:51,450 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:51,450 INFO L410 AbstractCegarLoop]: === Iteration 35 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:51,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:51,450 INFO L82 PathProgramCache]: Analyzing trace with hash -1179614883, now seen corresponding path program 5 times [2019-12-07 18:19:51,450 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:51,450 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659404646] [2019-12-07 18:19:51,450 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:51,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:51,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:51,579 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1659404646] [2019-12-07 18:19:51,579 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:51,579 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:19:51,580 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [19243492] [2019-12-07 18:19:51,580 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:19:51,580 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:51,580 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:19:51,580 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:19:51,580 INFO L87 Difference]: Start difference. First operand 16901 states and 50424 transitions. Second operand 11 states. [2019-12-07 18:19:52,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:52,818 INFO L93 Difference]: Finished difference Result 19932 states and 58716 transitions. [2019-12-07 18:19:52,819 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2019-12-07 18:19:52,819 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 67 [2019-12-07 18:19:52,819 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:52,845 INFO L225 Difference]: With dead ends: 19932 [2019-12-07 18:19:52,845 INFO L226 Difference]: Without dead ends: 15430 [2019-12-07 18:19:52,846 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 260 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=220, Invalid=902, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 18:19:52,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15430 states. [2019-12-07 18:19:53,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15430 to 12932. [2019-12-07 18:19:53,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12932 states. [2019-12-07 18:19:53,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12932 states to 12932 states and 38630 transitions. [2019-12-07 18:19:53,051 INFO L78 Accepts]: Start accepts. Automaton has 12932 states and 38630 transitions. Word has length 67 [2019-12-07 18:19:53,052 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:53,052 INFO L462 AbstractCegarLoop]: Abstraction has 12932 states and 38630 transitions. [2019-12-07 18:19:53,052 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:19:53,052 INFO L276 IsEmpty]: Start isEmpty. Operand 12932 states and 38630 transitions. [2019-12-07 18:19:53,062 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:19:53,062 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:53,062 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:53,062 INFO L410 AbstractCegarLoop]: === Iteration 36 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:53,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:53,062 INFO L82 PathProgramCache]: Analyzing trace with hash 765672949, now seen corresponding path program 6 times [2019-12-07 18:19:53,062 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:53,063 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [38835659] [2019-12-07 18:19:53,063 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:53,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:53,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:53,186 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [38835659] [2019-12-07 18:19:53,186 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:53,186 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 18:19:53,186 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596208154] [2019-12-07 18:19:53,186 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 18:19:53,186 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:53,186 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 18:19:53,186 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:19:53,186 INFO L87 Difference]: Start difference. First operand 12932 states and 38630 transitions. Second operand 12 states. [2019-12-07 18:19:53,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:53,968 INFO L93 Difference]: Finished difference Result 15978 states and 46950 transitions. [2019-12-07 18:19:53,969 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-12-07 18:19:53,969 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 67 [2019-12-07 18:19:53,969 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:53,994 INFO L225 Difference]: With dead ends: 15978 [2019-12-07 18:19:53,994 INFO L226 Difference]: Without dead ends: 15000 [2019-12-07 18:19:53,995 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 285 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=231, Invalid=1029, Unknown=0, NotChecked=0, Total=1260 [2019-12-07 18:19:54,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15000 states. [2019-12-07 18:19:54,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15000 to 12270. [2019-12-07 18:19:54,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12270 states. [2019-12-07 18:19:54,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12270 states to 12270 states and 36809 transitions. [2019-12-07 18:19:54,186 INFO L78 Accepts]: Start accepts. Automaton has 12270 states and 36809 transitions. Word has length 67 [2019-12-07 18:19:54,187 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:54,187 INFO L462 AbstractCegarLoop]: Abstraction has 12270 states and 36809 transitions. [2019-12-07 18:19:54,187 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 18:19:54,187 INFO L276 IsEmpty]: Start isEmpty. Operand 12270 states and 36809 transitions. [2019-12-07 18:19:54,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:19:54,196 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:54,196 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:54,196 INFO L410 AbstractCegarLoop]: === Iteration 37 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:54,196 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:54,197 INFO L82 PathProgramCache]: Analyzing trace with hash -1127178005, now seen corresponding path program 7 times [2019-12-07 18:19:54,197 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:54,197 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1774674568] [2019-12-07 18:19:54,197 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:54,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:19:54,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:19:54,260 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:19:54,260 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 18:19:54,262 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [893] [893] ULTIMATE.startENTRY-->L823: Formula: (let ((.cse0 (store |v_#valid_82| 0 0))) (and (= 0 |v_ULTIMATE.start_main_~#t751~0.offset_29|) (= 0 v_~z$r_buff1_thd3~0_333) (= 0 v_~__unbuffered_cnt~0_79) (= v_~z~0_222 0) (= 0 v_~x~0_150) (= 0 v_~z$flush_delayed~0_66) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t751~0.base_43|)) (= (store .cse0 |v_ULTIMATE.start_main_~#t751~0.base_43| 1) |v_#valid_80|) (= v_~__unbuffered_p2_EBX~0_70 0) (= v_~y~0_71 0) (= v_~z$read_delayed_var~0.base_8 0) (< 0 |v_#StackHeapBarrier_17|) (= v_~z$r_buff0_thd1~0_186 0) (= v_~z$w_buff1_used~0_670 0) (= v_~z$r_buff0_thd2~0_110 0) (= 0 v_~weak$$choice0~0_29) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t751~0.base_43| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t751~0.base_43|) |v_ULTIMATE.start_main_~#t751~0.offset_29| 0)) |v_#memory_int_17|) (= v_~z$w_buff0~0_701 0) (= v_~z$r_buff1_thd0~0_201 0) (= v_~z$read_delayed~0_7 0) (= 0 v_~z$r_buff0_thd3~0_363) (= 0 v_~__unbuffered_p2_EAX~0_62) (= |v_#NULL.offset_5| 0) (= v_~z$mem_tmp~0_43 0) (= v_~z$r_buff0_thd0~0_137 0) (= |v_#length_27| (store |v_#length_28| |v_ULTIMATE.start_main_~#t751~0.base_43| 4)) (= v_~weak$$choice2~0_160 0) (= v_~z$r_buff1_thd1~0_144 0) (= v_~z$r_buff1_thd2~0_165 0) (= v_~z$w_buff0_used~0_1072 0) (= v_~z$w_buff1~0_410 0) (= v_~main$tmp_guard0~0_24 0) (= v_~main$tmp_guard1~0_54 0) (= 0 |v_#NULL.base_5|) (= v_~z$read_delayed_var~0.offset_8 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t751~0.base_43|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_82|, #memory_int=|v_#memory_int_18|, #length=|v_#length_28|} OutVars{~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_165, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_46|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_~#t751~0.base=|v_ULTIMATE.start_main_~#t751~0.base_43|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_202|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_46|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_120|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_137, ULTIMATE.start_main_~#t751~0.offset=|v_ULTIMATE.start_main_~#t751~0.offset_29|, #length=|v_#length_27|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_62, ~z$mem_tmp~0=v_~z$mem_tmp~0_43, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_70, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_10|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_670, ~z$flush_delayed~0=v_~z$flush_delayed~0_66, ~weak$$choice0~0=v_~weak$$choice0~0_29, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_144, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_8, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_363, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_79, ULTIMATE.start_main_~#t753~0.base=|v_ULTIMATE.start_main_~#t753~0.base_29|, ~x~0=v_~x~0_150, ~z$read_delayed~0=v_~z$read_delayed~0_7, ~z$w_buff1~0=v_~z$w_buff1~0_410, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_54, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_74|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_8, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_34|, ULTIMATE.start_main_~#t752~0.base=|v_ULTIMATE.start_main_~#t752~0.base_37|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_201, ~y~0=v_~y~0_71, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_110, ULTIMATE.start_main_~#t753~0.offset=|v_ULTIMATE.start_main_~#t753~0.offset_21|, ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_26|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_1072, ~z$w_buff0~0=v_~z$w_buff0~0_701, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_10|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_333, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_~#t752~0.offset=|v_ULTIMATE.start_main_~#t752~0.offset_22|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_31|, #valid=|v_#valid_80|, #memory_int=|v_#memory_int_17|, ~z~0=v_~z~0_222, ~weak$$choice2~0=v_~weak$$choice2~0_160, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_186} AuxVars[] AssignedVars[~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite47, ~z$read_delayed~0, #NULL.offset, ~z$w_buff1~0, ULTIMATE.start_main_~#t751~0.base, ULTIMATE.start_main_#t~ite49, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite51, ULTIMATE.start_main_~#t752~0.base, ~z$r_buff1_thd0~0, ULTIMATE.start_main_~#t751~0.offset, #length, ~__unbuffered_p2_EAX~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_~#t753~0.offset, ~z$mem_tmp~0, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_#t~nondet46, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~nondet44, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~nondet45, ~z$w_buff1_used~0, ~z$flush_delayed~0, ~main$tmp_guard0~0, #NULL.base, ~weak$$choice0~0, ULTIMATE.start_main_~#t752~0.offset, ULTIMATE.start_main_#res, ~z$r_buff1_thd1~0, #valid, #memory_int, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ULTIMATE.start_main_~#t753~0.base, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0, ~x~0] because there is no mapped edge [2019-12-07 18:19:54,263 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [865] [865] L823-1-->L825: Formula: (and (= 0 |v_ULTIMATE.start_main_~#t752~0.offset_10|) (= (select |v_#valid_34| |v_ULTIMATE.start_main_~#t752~0.base_11|) 0) (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t752~0.base_11| 1)) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t752~0.base_11| 4)) (not (= |v_ULTIMATE.start_main_~#t752~0.base_11| 0)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t752~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t752~0.base_11|) |v_ULTIMATE.start_main_~#t752~0.offset_10| 1)) |v_#memory_int_13|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t752~0.base_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t752~0.base=|v_ULTIMATE.start_main_~#t752~0.base_11|, ULTIMATE.start_main_~#t752~0.offset=|v_ULTIMATE.start_main_~#t752~0.offset_10|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_5|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_13|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t752~0.base, ULTIMATE.start_main_~#t752~0.offset, ULTIMATE.start_main_#t~nondet44, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 18:19:54,263 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] P0ENTRY-->L4-3: Formula: (and (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_21 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_19|) (= |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_19| (ite (not (and (not (= (mod v_~z$w_buff0_used~0_174 256) 0)) (not (= (mod v_~z$w_buff1_used~0_104 256) 0)))) 1 0)) (= v_~z$w_buff0_used~0_174 1) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_21 0)) (= v_~z$w_buff0~0_53 v_~z$w_buff1~0_38) (= v_~z$w_buff0_used~0_175 v_~z$w_buff1_used~0_104) (= v_P0Thread1of1ForFork0_~arg.offset_19 |v_P0Thread1of1ForFork0_#in~arg.offset_21|) (= v_P0Thread1of1ForFork0_~arg.base_19 |v_P0Thread1of1ForFork0_#in~arg.base_21|) (= 1 v_~z$w_buff0~0_52)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_21|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_175, ~z$w_buff0~0=v_~z$w_buff0~0_53, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_21|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_21|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_174, ~z$w_buff0~0=v_~z$w_buff0~0_52, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_21, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_104, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_21|, ~z$w_buff1~0=v_~z$w_buff1~0_38, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_19, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_19|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_19} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 18:19:54,264 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L825-1-->L827: Formula: (and (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t753~0.base_10| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t753~0.base_10|) |v_ULTIMATE.start_main_~#t753~0.offset_9| 2)) |v_#memory_int_11|) (= (select |v_#valid_30| |v_ULTIMATE.start_main_~#t753~0.base_10|) 0) (= |v_#valid_29| (store |v_#valid_30| |v_ULTIMATE.start_main_~#t753~0.base_10| 1)) (= |v_ULTIMATE.start_main_~#t753~0.offset_9| 0) (not (= 0 |v_ULTIMATE.start_main_~#t753~0.base_10|)) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t753~0.base_10| 4)) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t753~0.base_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_12|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t753~0.offset=|v_ULTIMATE.start_main_~#t753~0.offset_9|, #StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_29|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_5|, #memory_int=|v_#memory_int_11|, #length=|v_#length_15|, ULTIMATE.start_main_~#t753~0.base=|v_ULTIMATE.start_main_~#t753~0.base_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t753~0.offset, #valid, ULTIMATE.start_main_#t~nondet45, #memory_int, #length, ULTIMATE.start_main_~#t753~0.base] because there is no mapped edge [2019-12-07 18:19:54,265 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [819] [819] L764-2-->L764-4: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd2~0_In1531763723 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In1531763723 256) 0))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork1_#t~ite9_Out1531763723| ~z$w_buff1~0_In1531763723)) (and (or .cse1 .cse0) (= |P1Thread1of1ForFork1_#t~ite9_Out1531763723| ~z~0_In1531763723)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1531763723, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1531763723, ~z$w_buff1~0=~z$w_buff1~0_In1531763723, ~z~0=~z~0_In1531763723} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out1531763723|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1531763723, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1531763723, ~z$w_buff1~0=~z$w_buff1~0_In1531763723, ~z~0=~z~0_In1531763723} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-12-07 18:19:54,266 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [875] [875] L789-->L789-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-153471672 256)))) (or (and (not .cse0) (= |P2Thread1of1ForFork2_#t~ite20_In-153471672| |P2Thread1of1ForFork2_#t~ite20_Out-153471672|) (= ~z$w_buff0~0_In-153471672 |P2Thread1of1ForFork2_#t~ite21_Out-153471672|)) (and (= |P2Thread1of1ForFork2_#t~ite20_Out-153471672| |P2Thread1of1ForFork2_#t~ite21_Out-153471672|) .cse0 (= |P2Thread1of1ForFork2_#t~ite20_Out-153471672| ~z$w_buff0~0_In-153471672) (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-153471672 256)))) (or (and (= (mod ~z$r_buff1_thd3~0_In-153471672 256) 0) .cse1) (= 0 (mod ~z$w_buff0_used~0_In-153471672 256)) (and (= 0 (mod ~z$w_buff1_used~0_In-153471672 256)) .cse1)))))) InVars {~z$w_buff0~0=~z$w_buff0~0_In-153471672, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-153471672, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_In-153471672|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-153471672, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-153471672, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-153471672, ~weak$$choice2~0=~weak$$choice2~0_In-153471672} OutVars{~z$w_buff0~0=~z$w_buff0~0_In-153471672, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-153471672|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-153471672, P2Thread1of1ForFork2_#t~ite21=|P2Thread1of1ForFork2_#t~ite21_Out-153471672|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-153471672, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-153471672, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-153471672, ~weak$$choice2~0=~weak$$choice2~0_In-153471672} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, P2Thread1of1ForFork2_#t~ite21] because there is no mapped edge [2019-12-07 18:19:54,266 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [839] [839] L745-->L745-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In-902705016 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In-902705016 256)))) (or (and (= |P0Thread1of1ForFork0_#t~ite5_Out-902705016| 0) (not .cse0) (not .cse1)) (and (= |P0Thread1of1ForFork0_#t~ite5_Out-902705016| ~z$w_buff0_used~0_In-902705016) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-902705016, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-902705016} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-902705016|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-902705016, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-902705016} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 18:19:54,267 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [833] [833] L746-->L746-2: Formula: (let ((.cse2 (= (mod ~z$w_buff1_used~0_In1326162148 256) 0)) (.cse3 (= (mod ~z$r_buff1_thd1~0_In1326162148 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In1326162148 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In1326162148 256)))) (or (and (= 0 |P0Thread1of1ForFork0_#t~ite6_Out1326162148|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$w_buff1_used~0_In1326162148 |P0Thread1of1ForFork0_#t~ite6_Out1326162148|) (or .cse2 .cse3) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1326162148, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1326162148, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1326162148, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1326162148} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out1326162148|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1326162148, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1326162148, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1326162148, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1326162148} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 18:19:54,267 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] L747-->L748: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In548479969 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In548479969 256))) (.cse2 (= ~z$r_buff0_thd1~0_In548479969 ~z$r_buff0_thd1~0_Out548479969))) (or (and (not .cse0) (= 0 ~z$r_buff0_thd1~0_Out548479969) (not .cse1)) (and .cse1 .cse2) (and .cse0 .cse2))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In548479969, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In548479969} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In548479969, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out548479969|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out548479969} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 18:19:54,267 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [828] [828] L748-->L748-2: Formula: (let ((.cse1 (= (mod ~z$r_buff1_thd1~0_In687980324 256) 0)) (.cse0 (= (mod ~z$w_buff1_used~0_In687980324 256) 0)) (.cse2 (= 0 (mod ~z$r_buff0_thd1~0_In687980324 256))) (.cse3 (= (mod ~z$w_buff0_used~0_In687980324 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork0_#t~ite8_Out687980324|)) (and (or .cse1 .cse0) (or .cse2 .cse3) (= ~z$r_buff1_thd1~0_In687980324 |P0Thread1of1ForFork0_#t~ite8_Out687980324|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In687980324, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In687980324, ~z$w_buff1_used~0=~z$w_buff1_used~0_In687980324, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In687980324} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In687980324, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out687980324|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In687980324, ~z$w_buff1_used~0=~z$w_buff1_used~0_In687980324, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In687980324} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 18:19:54,267 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [851] [851] L748-2-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_62 |v_P0Thread1of1ForFork0_#t~ite8_22|) (= (+ v_~__unbuffered_cnt~0_56 1) v_~__unbuffered_cnt~0_55) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_22|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_21|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_62, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 18:19:54,268 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [874] [874] L790-->L790-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In-99536597 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite23_Out-99536597| ~z$w_buff1~0_In-99536597) (let ((.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In-99536597 256)))) (or (and (= (mod ~z$r_buff1_thd3~0_In-99536597 256) 0) .cse0) (and (= (mod ~z$w_buff1_used~0_In-99536597 256) 0) .cse0) (= (mod ~z$w_buff0_used~0_In-99536597 256) 0))) .cse1 (= |P2Thread1of1ForFork2_#t~ite24_Out-99536597| |P2Thread1of1ForFork2_#t~ite23_Out-99536597|)) (and (= |P2Thread1of1ForFork2_#t~ite23_In-99536597| |P2Thread1of1ForFork2_#t~ite23_Out-99536597|) (= |P2Thread1of1ForFork2_#t~ite24_Out-99536597| ~z$w_buff1~0_In-99536597) (not .cse1)))) InVars {P2Thread1of1ForFork2_#t~ite23=|P2Thread1of1ForFork2_#t~ite23_In-99536597|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-99536597, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-99536597, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-99536597, ~z$w_buff1~0=~z$w_buff1~0_In-99536597, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-99536597, ~weak$$choice2~0=~weak$$choice2~0_In-99536597} OutVars{P2Thread1of1ForFork2_#t~ite23=|P2Thread1of1ForFork2_#t~ite23_Out-99536597|, P2Thread1of1ForFork2_#t~ite24=|P2Thread1of1ForFork2_#t~ite24_Out-99536597|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-99536597, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-99536597, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-99536597, ~z$w_buff1~0=~z$w_buff1~0_In-99536597, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-99536597, ~weak$$choice2~0=~weak$$choice2~0_In-99536597} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite23, P2Thread1of1ForFork2_#t~ite24] because there is no mapped edge [2019-12-07 18:19:54,268 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [873] [873] L791-->L791-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In-113250275 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite26_Out-113250275| ~z$w_buff0_used~0_In-113250275) (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In-113250275 256) 0))) (or (and (= 0 (mod ~z$r_buff1_thd3~0_In-113250275 256)) .cse0) (= 0 (mod ~z$w_buff0_used~0_In-113250275 256)) (and (= (mod ~z$w_buff1_used~0_In-113250275 256) 0) .cse0))) .cse1 (= |P2Thread1of1ForFork2_#t~ite26_Out-113250275| |P2Thread1of1ForFork2_#t~ite27_Out-113250275|)) (and (= |P2Thread1of1ForFork2_#t~ite27_Out-113250275| ~z$w_buff0_used~0_In-113250275) (= |P2Thread1of1ForFork2_#t~ite26_In-113250275| |P2Thread1of1ForFork2_#t~ite26_Out-113250275|) (not .cse1)))) InVars {P2Thread1of1ForFork2_#t~ite26=|P2Thread1of1ForFork2_#t~ite26_In-113250275|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-113250275, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-113250275, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-113250275, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-113250275, ~weak$$choice2~0=~weak$$choice2~0_In-113250275} OutVars{P2Thread1of1ForFork2_#t~ite26=|P2Thread1of1ForFork2_#t~ite26_Out-113250275|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-113250275, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-113250275, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-113250275, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-113250275, ~weak$$choice2~0=~weak$$choice2~0_In-113250275, P2Thread1of1ForFork2_#t~ite27=|P2Thread1of1ForFork2_#t~ite27_Out-113250275|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite26, P2Thread1of1ForFork2_#t~ite27] because there is no mapped edge [2019-12-07 18:19:54,269 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [812] [812] L793-->L794: Formula: (and (not (= (mod v_~weak$$choice2~0_37 256) 0)) (= v_~z$r_buff0_thd3~0_119 v_~z$r_buff0_thd3~0_118)) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_119, ~weak$$choice2~0=v_~weak$$choice2~0_37} OutVars{P2Thread1of1ForFork2_#t~ite31=|v_P2Thread1of1ForFork2_#t~ite31_6|, P2Thread1of1ForFork2_#t~ite33=|v_P2Thread1of1ForFork2_#t~ite33_6|, P2Thread1of1ForFork2_#t~ite32=|v_P2Thread1of1ForFork2_#t~ite32_7|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_118, ~weak$$choice2~0=v_~weak$$choice2~0_37} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite31, P2Thread1of1ForFork2_#t~ite33, P2Thread1of1ForFork2_#t~ite32, ~z$r_buff0_thd3~0] because there is no mapped edge [2019-12-07 18:19:54,269 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [750] [750] L764-4-->L765: Formula: (= |v_P1Thread1of1ForFork1_#t~ite9_6| v_~z~0_16) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_6|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_5|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_5|, ~z~0=v_~z~0_16} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~z~0] because there is no mapped edge [2019-12-07 18:19:54,269 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] L765-->L765-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd2~0_In-1073800007 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1073800007 256)))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out-1073800007| ~z$w_buff0_used~0_In-1073800007)) (and (= |P1Thread1of1ForFork1_#t~ite11_Out-1073800007| 0) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1073800007, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1073800007} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1073800007, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out-1073800007|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1073800007} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 18:19:54,270 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [816] [816] L766-->L766-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In875675962 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In875675962 256))) (.cse3 (= (mod ~z$r_buff1_thd2~0_In875675962 256) 0)) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In875675962 256)))) (or (and (= |P1Thread1of1ForFork1_#t~ite12_Out875675962| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse3 .cse2) (= |P1Thread1of1ForFork1_#t~ite12_Out875675962| ~z$w_buff1_used~0_In875675962)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In875675962, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In875675962, ~z$w_buff1_used~0=~z$w_buff1_used~0_In875675962, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In875675962} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In875675962, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In875675962, ~z$w_buff1_used~0=~z$w_buff1_used~0_In875675962, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out875675962|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In875675962} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 18:19:54,270 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [817] [817] L767-->L767-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd2~0_In1857803482 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In1857803482 256)))) (or (and (= ~z$r_buff0_thd2~0_In1857803482 |P1Thread1of1ForFork1_#t~ite13_Out1857803482|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork1_#t~ite13_Out1857803482| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1857803482, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1857803482} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1857803482, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out1857803482|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1857803482} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 18:19:54,270 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [811] [811] L796-->L800: Formula: (and (= v_~z~0_64 v_~z$mem_tmp~0_7) (not (= 0 (mod v_~z$flush_delayed~0_10 256))) (= 0 v_~z$flush_delayed~0_9)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_7, ~z$flush_delayed~0=v_~z$flush_delayed~0_10} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_7, P2Thread1of1ForFork2_#t~ite37=|v_P2Thread1of1ForFork2_#t~ite37_5|, ~z$flush_delayed~0=v_~z$flush_delayed~0_9, ~z~0=v_~z~0_64} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite37, ~z$flush_delayed~0, ~z~0] because there is no mapped edge [2019-12-07 18:19:54,271 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [822] [822] L800-2-->L800-5: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd3~0_In1311890741 256) 0)) (.cse2 (= |P2Thread1of1ForFork2_#t~ite38_Out1311890741| |P2Thread1of1ForFork2_#t~ite39_Out1311890741|)) (.cse1 (= (mod ~z$w_buff1_used~0_In1311890741 256) 0))) (or (and (or .cse0 .cse1) .cse2 (= |P2Thread1of1ForFork2_#t~ite38_Out1311890741| ~z~0_In1311890741)) (and (not .cse0) (= |P2Thread1of1ForFork2_#t~ite38_Out1311890741| ~z$w_buff1~0_In1311890741) .cse2 (not .cse1)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1311890741, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1311890741, ~z$w_buff1~0=~z$w_buff1~0_In1311890741, ~z~0=~z~0_In1311890741} OutVars{~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1311890741, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1311890741, ~z$w_buff1~0=~z$w_buff1~0_In1311890741, ~z~0=~z~0_In1311890741, P2Thread1of1ForFork2_#t~ite39=|P2Thread1of1ForFork2_#t~ite39_Out1311890741|, P2Thread1of1ForFork2_#t~ite38=|P2Thread1of1ForFork2_#t~ite38_Out1311890741|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite39, P2Thread1of1ForFork2_#t~ite38] because there is no mapped edge [2019-12-07 18:19:54,271 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [818] [818] L801-->L801-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In-1675012109 256))) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1675012109 256)))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite40_Out-1675012109|) (not .cse0) (not .cse1)) (and (= ~z$w_buff0_used~0_In-1675012109 |P2Thread1of1ForFork2_#t~ite40_Out-1675012109|) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1675012109, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1675012109} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1675012109, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1675012109, P2Thread1of1ForFork2_#t~ite40=|P2Thread1of1ForFork2_#t~ite40_Out-1675012109|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite40] because there is no mapped edge [2019-12-07 18:19:54,272 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [821] [821] L802-->L802-2: Formula: (let ((.cse3 (= (mod ~z$r_buff1_thd3~0_In-1976866958 256) 0)) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-1976866958 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-1976866958 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-1976866958 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite41_Out-1976866958|)) (and (or .cse3 .cse2) (= |P2Thread1of1ForFork2_#t~ite41_Out-1976866958| ~z$w_buff1_used~0_In-1976866958) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1976866958, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1976866958, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1976866958, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1976866958} OutVars{P2Thread1of1ForFork2_#t~ite41=|P2Thread1of1ForFork2_#t~ite41_Out-1976866958|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1976866958, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1976866958, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1976866958, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1976866958} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite41] because there is no mapped edge [2019-12-07 18:19:54,272 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L768-->L768-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In348512507 256) 0)) (.cse1 (= (mod ~z$r_buff0_thd2~0_In348512507 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In348512507 256))) (.cse2 (= (mod ~z$r_buff1_thd2~0_In348512507 256) 0))) (or (and (= |P1Thread1of1ForFork1_#t~ite14_Out348512507| ~z$r_buff1_thd2~0_In348512507) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2))) (= |P1Thread1of1ForFork1_#t~ite14_Out348512507| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In348512507, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In348512507, ~z$w_buff1_used~0=~z$w_buff1_used~0_In348512507, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In348512507} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In348512507, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In348512507, ~z$w_buff1_used~0=~z$w_buff1_used~0_In348512507, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out348512507|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In348512507} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 18:19:54,272 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [849] [849] L768-2-->P1EXIT: Formula: (and (= |v_P1Thread1of1ForFork1_#t~ite14_26| v_~z$r_buff1_thd2~0_70) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= v_~__unbuffered_cnt~0_49 (+ v_~__unbuffered_cnt~0_50 1)) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_50, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_26|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_70, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_49, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_25|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 18:19:54,272 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [840] [840] L803-->L803-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-114217454 256))) (.cse1 (= (mod ~z$r_buff0_thd3~0_In-114217454 256) 0))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite42_Out-114217454|) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite42_Out-114217454| ~z$r_buff0_thd3~0_In-114217454)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-114217454, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-114217454} OutVars{P2Thread1of1ForFork2_#t~ite42=|P2Thread1of1ForFork2_#t~ite42_Out-114217454|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-114217454, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-114217454} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite42] because there is no mapped edge [2019-12-07 18:19:54,273 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [830] [830] L804-->L804-2: Formula: (let ((.cse2 (= 0 (mod ~z$w_buff1_used~0_In-1119912684 256))) (.cse3 (= 0 (mod ~z$r_buff1_thd3~0_In-1119912684 256))) (.cse1 (= (mod ~z$r_buff0_thd3~0_In-1119912684 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1119912684 256)))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite43_Out-1119912684|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (or .cse1 .cse0) (= ~z$r_buff1_thd3~0_In-1119912684 |P2Thread1of1ForFork2_#t~ite43_Out-1119912684|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1119912684, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1119912684, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1119912684, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1119912684} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1119912684, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1119912684, P2Thread1of1ForFork2_#t~ite43=|P2Thread1of1ForFork2_#t~ite43_Out-1119912684|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1119912684, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1119912684} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite43] because there is no mapped edge [2019-12-07 18:19:54,273 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L804-2-->P2EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_44 1) v_~__unbuffered_cnt~0_43) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= v_~z$r_buff1_thd3~0_119 |v_P2Thread1of1ForFork2_#t~ite43_26|)) InVars {P2Thread1of1ForFork2_#t~ite43=|v_P2Thread1of1ForFork2_#t~ite43_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_44} OutVars{~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_119, P2Thread1of1ForFork2_#t~ite43=|v_P2Thread1of1ForFork2_#t~ite43_25|, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_43, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#t~ite43, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 18:19:54,273 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L827-1-->L833: Formula: (and (= v_~main$tmp_guard0~0_9 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_34) 1 0)) 0 1)) (not (= 0 (mod v_~main$tmp_guard0~0_9 256)))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_34} OutVars{ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_34, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_9} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet46, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:19:54,273 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [837] [837] L833-2-->L833-5: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In-690471220 256))) (.cse2 (= |ULTIMATE.start_main_#t~ite48_Out-690471220| |ULTIMATE.start_main_#t~ite47_Out-690471220|)) (.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In-690471220 256)))) (or (and (= ~z~0_In-690471220 |ULTIMATE.start_main_#t~ite47_Out-690471220|) (or .cse0 .cse1) .cse2) (and (= ~z$w_buff1~0_In-690471220 |ULTIMATE.start_main_#t~ite47_Out-690471220|) (not .cse0) .cse2 (not .cse1)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-690471220, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-690471220, ~z$w_buff1~0=~z$w_buff1~0_In-690471220, ~z~0=~z~0_In-690471220} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-690471220, ULTIMATE.start_main_#t~ite47=|ULTIMATE.start_main_#t~ite47_Out-690471220|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-690471220, ~z$w_buff1~0=~z$w_buff1~0_In-690471220, ULTIMATE.start_main_#t~ite48=|ULTIMATE.start_main_#t~ite48_Out-690471220|, ~z~0=~z~0_In-690471220} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 18:19:54,274 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [820] [820] L834-->L834-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In1047871323 256) 0)) (.cse0 (= (mod ~z$w_buff0_used~0_In1047871323 256) 0))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite49_Out1047871323| 0) (not .cse1)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite49_Out1047871323| ~z$w_buff0_used~0_In1047871323)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1047871323, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1047871323} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1047871323, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1047871323, ULTIMATE.start_main_#t~ite49=|ULTIMATE.start_main_#t~ite49_Out1047871323|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite49] because there is no mapped edge [2019-12-07 18:19:54,274 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] L835-->L835-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In974507265 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In974507265 256))) (.cse2 (= (mod ~z$r_buff0_thd0~0_In974507265 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In974507265 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite50_Out974507265|)) (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In974507265 |ULTIMATE.start_main_#t~ite50_Out974507265|) (or .cse2 .cse3)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In974507265, ~z$w_buff0_used~0=~z$w_buff0_used~0_In974507265, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In974507265, ~z$w_buff1_used~0=~z$w_buff1_used~0_In974507265} OutVars{ULTIMATE.start_main_#t~ite50=|ULTIMATE.start_main_#t~ite50_Out974507265|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In974507265, ~z$w_buff0_used~0=~z$w_buff0_used~0_In974507265, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In974507265, ~z$w_buff1_used~0=~z$w_buff1_used~0_In974507265} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite50] because there is no mapped edge [2019-12-07 18:19:54,275 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [824] [824] L836-->L836-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In974088491 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In974088491 256)))) (or (and (= ~z$r_buff0_thd0~0_In974088491 |ULTIMATE.start_main_#t~ite51_Out974088491|) (or .cse0 .cse1)) (and (= 0 |ULTIMATE.start_main_#t~ite51_Out974088491|) (not .cse1) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In974088491, ~z$w_buff0_used~0=~z$w_buff0_used~0_In974088491} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In974088491, ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_Out974088491|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In974088491} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite51] because there is no mapped edge [2019-12-07 18:19:54,275 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [814] [814] L837-->L837-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd0~0_In1605449687 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In1605449687 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In1605449687 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In1605449687 256)))) (or (and (= |ULTIMATE.start_main_#t~ite52_Out1605449687| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite52_Out1605449687| ~z$r_buff1_thd0~0_In1605449687)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1605449687, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1605449687, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1605449687, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1605449687} OutVars{ULTIMATE.start_main_#t~ite52=|ULTIMATE.start_main_#t~ite52_Out1605449687|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1605449687, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1605449687, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1605449687, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1605449687} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52] because there is no mapped edge [2019-12-07 18:19:54,275 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [878] [878] L837-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_~main$tmp_guard1~0_27 (ite (= 0 (ite (not (and (= v_~y~0_37 2) (= 2 v_~__unbuffered_p2_EAX~0_30) (= v_~__unbuffered_p2_EBX~0_37 0) (= 2 v_~x~0_117))) 1 0)) 0 1)) (= v_ULTIMATE.start___VERIFIER_assert_~expression_16 0) (= v_ULTIMATE.start___VERIFIER_assert_~expression_16 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_12|) (= (mod v_~main$tmp_guard1~0_27 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_12|) (= v_~z$r_buff1_thd0~0_162 |v_ULTIMATE.start_main_#t~ite52_69|)) InVars {ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_69|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_37, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_30, ~y~0=v_~y~0_37, ~x~0=v_~x~0_117} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_68|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_16, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_37, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_162, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_27, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_30, ~y~0=v_~y~0_37, ~x~0=v_~x~0_117, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:19:54,326 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 06:19:54 BasicIcfg [2019-12-07 18:19:54,326 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 18:19:54,326 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:19:54,326 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:19:54,327 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:19:54,327 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:17:37" (3/4) ... [2019-12-07 18:19:54,329 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 18:19:54,329 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [893] [893] ULTIMATE.startENTRY-->L823: Formula: (let ((.cse0 (store |v_#valid_82| 0 0))) (and (= 0 |v_ULTIMATE.start_main_~#t751~0.offset_29|) (= 0 v_~z$r_buff1_thd3~0_333) (= 0 v_~__unbuffered_cnt~0_79) (= v_~z~0_222 0) (= 0 v_~x~0_150) (= 0 v_~z$flush_delayed~0_66) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t751~0.base_43|)) (= (store .cse0 |v_ULTIMATE.start_main_~#t751~0.base_43| 1) |v_#valid_80|) (= v_~__unbuffered_p2_EBX~0_70 0) (= v_~y~0_71 0) (= v_~z$read_delayed_var~0.base_8 0) (< 0 |v_#StackHeapBarrier_17|) (= v_~z$r_buff0_thd1~0_186 0) (= v_~z$w_buff1_used~0_670 0) (= v_~z$r_buff0_thd2~0_110 0) (= 0 v_~weak$$choice0~0_29) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t751~0.base_43| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t751~0.base_43|) |v_ULTIMATE.start_main_~#t751~0.offset_29| 0)) |v_#memory_int_17|) (= v_~z$w_buff0~0_701 0) (= v_~z$r_buff1_thd0~0_201 0) (= v_~z$read_delayed~0_7 0) (= 0 v_~z$r_buff0_thd3~0_363) (= 0 v_~__unbuffered_p2_EAX~0_62) (= |v_#NULL.offset_5| 0) (= v_~z$mem_tmp~0_43 0) (= v_~z$r_buff0_thd0~0_137 0) (= |v_#length_27| (store |v_#length_28| |v_ULTIMATE.start_main_~#t751~0.base_43| 4)) (= v_~weak$$choice2~0_160 0) (= v_~z$r_buff1_thd1~0_144 0) (= v_~z$r_buff1_thd2~0_165 0) (= v_~z$w_buff0_used~0_1072 0) (= v_~z$w_buff1~0_410 0) (= v_~main$tmp_guard0~0_24 0) (= v_~main$tmp_guard1~0_54 0) (= 0 |v_#NULL.base_5|) (= v_~z$read_delayed_var~0.offset_8 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t751~0.base_43|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_82|, #memory_int=|v_#memory_int_18|, #length=|v_#length_28|} OutVars{~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_165, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_46|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_~#t751~0.base=|v_ULTIMATE.start_main_~#t751~0.base_43|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_202|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_46|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_120|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_137, ULTIMATE.start_main_~#t751~0.offset=|v_ULTIMATE.start_main_~#t751~0.offset_29|, #length=|v_#length_27|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_62, ~z$mem_tmp~0=v_~z$mem_tmp~0_43, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_70, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_10|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_670, ~z$flush_delayed~0=v_~z$flush_delayed~0_66, ~weak$$choice0~0=v_~weak$$choice0~0_29, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_144, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_8, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_363, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_79, ULTIMATE.start_main_~#t753~0.base=|v_ULTIMATE.start_main_~#t753~0.base_29|, ~x~0=v_~x~0_150, ~z$read_delayed~0=v_~z$read_delayed~0_7, ~z$w_buff1~0=v_~z$w_buff1~0_410, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_54, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_74|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_8, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_34|, ULTIMATE.start_main_~#t752~0.base=|v_ULTIMATE.start_main_~#t752~0.base_37|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_201, ~y~0=v_~y~0_71, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_110, ULTIMATE.start_main_~#t753~0.offset=|v_ULTIMATE.start_main_~#t753~0.offset_21|, ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_26|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_1072, ~z$w_buff0~0=v_~z$w_buff0~0_701, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_10|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_333, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_~#t752~0.offset=|v_ULTIMATE.start_main_~#t752~0.offset_22|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_31|, #valid=|v_#valid_80|, #memory_int=|v_#memory_int_17|, ~z~0=v_~z~0_222, ~weak$$choice2~0=v_~weak$$choice2~0_160, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_186} AuxVars[] AssignedVars[~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite47, ~z$read_delayed~0, #NULL.offset, ~z$w_buff1~0, ULTIMATE.start_main_~#t751~0.base, ULTIMATE.start_main_#t~ite49, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite51, ULTIMATE.start_main_~#t752~0.base, ~z$r_buff1_thd0~0, ULTIMATE.start_main_~#t751~0.offset, #length, ~__unbuffered_p2_EAX~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_~#t753~0.offset, ~z$mem_tmp~0, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_#t~nondet46, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~nondet44, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~nondet45, ~z$w_buff1_used~0, ~z$flush_delayed~0, ~main$tmp_guard0~0, #NULL.base, ~weak$$choice0~0, ULTIMATE.start_main_~#t752~0.offset, ULTIMATE.start_main_#res, ~z$r_buff1_thd1~0, #valid, #memory_int, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ULTIMATE.start_main_~#t753~0.base, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0, ~x~0] because there is no mapped edge [2019-12-07 18:19:54,329 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [865] [865] L823-1-->L825: Formula: (and (= 0 |v_ULTIMATE.start_main_~#t752~0.offset_10|) (= (select |v_#valid_34| |v_ULTIMATE.start_main_~#t752~0.base_11|) 0) (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t752~0.base_11| 1)) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t752~0.base_11| 4)) (not (= |v_ULTIMATE.start_main_~#t752~0.base_11| 0)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t752~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t752~0.base_11|) |v_ULTIMATE.start_main_~#t752~0.offset_10| 1)) |v_#memory_int_13|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t752~0.base_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t752~0.base=|v_ULTIMATE.start_main_~#t752~0.base_11|, ULTIMATE.start_main_~#t752~0.offset=|v_ULTIMATE.start_main_~#t752~0.offset_10|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_5|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_13|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t752~0.base, ULTIMATE.start_main_~#t752~0.offset, ULTIMATE.start_main_#t~nondet44, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 18:19:54,329 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] P0ENTRY-->L4-3: Formula: (and (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_21 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_19|) (= |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_19| (ite (not (and (not (= (mod v_~z$w_buff0_used~0_174 256) 0)) (not (= (mod v_~z$w_buff1_used~0_104 256) 0)))) 1 0)) (= v_~z$w_buff0_used~0_174 1) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_21 0)) (= v_~z$w_buff0~0_53 v_~z$w_buff1~0_38) (= v_~z$w_buff0_used~0_175 v_~z$w_buff1_used~0_104) (= v_P0Thread1of1ForFork0_~arg.offset_19 |v_P0Thread1of1ForFork0_#in~arg.offset_21|) (= v_P0Thread1of1ForFork0_~arg.base_19 |v_P0Thread1of1ForFork0_#in~arg.base_21|) (= 1 v_~z$w_buff0~0_52)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_21|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_175, ~z$w_buff0~0=v_~z$w_buff0~0_53, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_21|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_21|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_174, ~z$w_buff0~0=v_~z$w_buff0~0_52, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_21, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_104, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_21|, ~z$w_buff1~0=v_~z$w_buff1~0_38, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_19, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_19|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_19} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 18:19:54,330 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L825-1-->L827: Formula: (and (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t753~0.base_10| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t753~0.base_10|) |v_ULTIMATE.start_main_~#t753~0.offset_9| 2)) |v_#memory_int_11|) (= (select |v_#valid_30| |v_ULTIMATE.start_main_~#t753~0.base_10|) 0) (= |v_#valid_29| (store |v_#valid_30| |v_ULTIMATE.start_main_~#t753~0.base_10| 1)) (= |v_ULTIMATE.start_main_~#t753~0.offset_9| 0) (not (= 0 |v_ULTIMATE.start_main_~#t753~0.base_10|)) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t753~0.base_10| 4)) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t753~0.base_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_12|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t753~0.offset=|v_ULTIMATE.start_main_~#t753~0.offset_9|, #StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_29|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_5|, #memory_int=|v_#memory_int_11|, #length=|v_#length_15|, ULTIMATE.start_main_~#t753~0.base=|v_ULTIMATE.start_main_~#t753~0.base_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t753~0.offset, #valid, ULTIMATE.start_main_#t~nondet45, #memory_int, #length, ULTIMATE.start_main_~#t753~0.base] because there is no mapped edge [2019-12-07 18:19:54,331 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [819] [819] L764-2-->L764-4: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd2~0_In1531763723 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In1531763723 256) 0))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork1_#t~ite9_Out1531763723| ~z$w_buff1~0_In1531763723)) (and (or .cse1 .cse0) (= |P1Thread1of1ForFork1_#t~ite9_Out1531763723| ~z~0_In1531763723)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1531763723, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1531763723, ~z$w_buff1~0=~z$w_buff1~0_In1531763723, ~z~0=~z~0_In1531763723} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out1531763723|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1531763723, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1531763723, ~z$w_buff1~0=~z$w_buff1~0_In1531763723, ~z~0=~z~0_In1531763723} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-12-07 18:19:54,332 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [875] [875] L789-->L789-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-153471672 256)))) (or (and (not .cse0) (= |P2Thread1of1ForFork2_#t~ite20_In-153471672| |P2Thread1of1ForFork2_#t~ite20_Out-153471672|) (= ~z$w_buff0~0_In-153471672 |P2Thread1of1ForFork2_#t~ite21_Out-153471672|)) (and (= |P2Thread1of1ForFork2_#t~ite20_Out-153471672| |P2Thread1of1ForFork2_#t~ite21_Out-153471672|) .cse0 (= |P2Thread1of1ForFork2_#t~ite20_Out-153471672| ~z$w_buff0~0_In-153471672) (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-153471672 256)))) (or (and (= (mod ~z$r_buff1_thd3~0_In-153471672 256) 0) .cse1) (= 0 (mod ~z$w_buff0_used~0_In-153471672 256)) (and (= 0 (mod ~z$w_buff1_used~0_In-153471672 256)) .cse1)))))) InVars {~z$w_buff0~0=~z$w_buff0~0_In-153471672, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-153471672, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_In-153471672|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-153471672, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-153471672, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-153471672, ~weak$$choice2~0=~weak$$choice2~0_In-153471672} OutVars{~z$w_buff0~0=~z$w_buff0~0_In-153471672, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-153471672|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-153471672, P2Thread1of1ForFork2_#t~ite21=|P2Thread1of1ForFork2_#t~ite21_Out-153471672|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-153471672, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-153471672, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-153471672, ~weak$$choice2~0=~weak$$choice2~0_In-153471672} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, P2Thread1of1ForFork2_#t~ite21] because there is no mapped edge [2019-12-07 18:19:54,332 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [839] [839] L745-->L745-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In-902705016 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In-902705016 256)))) (or (and (= |P0Thread1of1ForFork0_#t~ite5_Out-902705016| 0) (not .cse0) (not .cse1)) (and (= |P0Thread1of1ForFork0_#t~ite5_Out-902705016| ~z$w_buff0_used~0_In-902705016) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-902705016, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-902705016} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-902705016|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-902705016, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-902705016} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 18:19:54,333 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [833] [833] L746-->L746-2: Formula: (let ((.cse2 (= (mod ~z$w_buff1_used~0_In1326162148 256) 0)) (.cse3 (= (mod ~z$r_buff1_thd1~0_In1326162148 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In1326162148 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In1326162148 256)))) (or (and (= 0 |P0Thread1of1ForFork0_#t~ite6_Out1326162148|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$w_buff1_used~0_In1326162148 |P0Thread1of1ForFork0_#t~ite6_Out1326162148|) (or .cse2 .cse3) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1326162148, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1326162148, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1326162148, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1326162148} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out1326162148|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1326162148, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1326162148, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1326162148, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1326162148} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 18:19:54,333 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] L747-->L748: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In548479969 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In548479969 256))) (.cse2 (= ~z$r_buff0_thd1~0_In548479969 ~z$r_buff0_thd1~0_Out548479969))) (or (and (not .cse0) (= 0 ~z$r_buff0_thd1~0_Out548479969) (not .cse1)) (and .cse1 .cse2) (and .cse0 .cse2))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In548479969, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In548479969} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In548479969, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out548479969|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out548479969} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 18:19:54,333 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [828] [828] L748-->L748-2: Formula: (let ((.cse1 (= (mod ~z$r_buff1_thd1~0_In687980324 256) 0)) (.cse0 (= (mod ~z$w_buff1_used~0_In687980324 256) 0)) (.cse2 (= 0 (mod ~z$r_buff0_thd1~0_In687980324 256))) (.cse3 (= (mod ~z$w_buff0_used~0_In687980324 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork0_#t~ite8_Out687980324|)) (and (or .cse1 .cse0) (or .cse2 .cse3) (= ~z$r_buff1_thd1~0_In687980324 |P0Thread1of1ForFork0_#t~ite8_Out687980324|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In687980324, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In687980324, ~z$w_buff1_used~0=~z$w_buff1_used~0_In687980324, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In687980324} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In687980324, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out687980324|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In687980324, ~z$w_buff1_used~0=~z$w_buff1_used~0_In687980324, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In687980324} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 18:19:54,333 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [851] [851] L748-2-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_62 |v_P0Thread1of1ForFork0_#t~ite8_22|) (= (+ v_~__unbuffered_cnt~0_56 1) v_~__unbuffered_cnt~0_55) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_22|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_21|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_62, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 18:19:54,333 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [874] [874] L790-->L790-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In-99536597 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite23_Out-99536597| ~z$w_buff1~0_In-99536597) (let ((.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In-99536597 256)))) (or (and (= (mod ~z$r_buff1_thd3~0_In-99536597 256) 0) .cse0) (and (= (mod ~z$w_buff1_used~0_In-99536597 256) 0) .cse0) (= (mod ~z$w_buff0_used~0_In-99536597 256) 0))) .cse1 (= |P2Thread1of1ForFork2_#t~ite24_Out-99536597| |P2Thread1of1ForFork2_#t~ite23_Out-99536597|)) (and (= |P2Thread1of1ForFork2_#t~ite23_In-99536597| |P2Thread1of1ForFork2_#t~ite23_Out-99536597|) (= |P2Thread1of1ForFork2_#t~ite24_Out-99536597| ~z$w_buff1~0_In-99536597) (not .cse1)))) InVars {P2Thread1of1ForFork2_#t~ite23=|P2Thread1of1ForFork2_#t~ite23_In-99536597|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-99536597, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-99536597, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-99536597, ~z$w_buff1~0=~z$w_buff1~0_In-99536597, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-99536597, ~weak$$choice2~0=~weak$$choice2~0_In-99536597} OutVars{P2Thread1of1ForFork2_#t~ite23=|P2Thread1of1ForFork2_#t~ite23_Out-99536597|, P2Thread1of1ForFork2_#t~ite24=|P2Thread1of1ForFork2_#t~ite24_Out-99536597|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-99536597, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-99536597, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-99536597, ~z$w_buff1~0=~z$w_buff1~0_In-99536597, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-99536597, ~weak$$choice2~0=~weak$$choice2~0_In-99536597} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite23, P2Thread1of1ForFork2_#t~ite24] because there is no mapped edge [2019-12-07 18:19:54,334 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [873] [873] L791-->L791-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In-113250275 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite26_Out-113250275| ~z$w_buff0_used~0_In-113250275) (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In-113250275 256) 0))) (or (and (= 0 (mod ~z$r_buff1_thd3~0_In-113250275 256)) .cse0) (= 0 (mod ~z$w_buff0_used~0_In-113250275 256)) (and (= (mod ~z$w_buff1_used~0_In-113250275 256) 0) .cse0))) .cse1 (= |P2Thread1of1ForFork2_#t~ite26_Out-113250275| |P2Thread1of1ForFork2_#t~ite27_Out-113250275|)) (and (= |P2Thread1of1ForFork2_#t~ite27_Out-113250275| ~z$w_buff0_used~0_In-113250275) (= |P2Thread1of1ForFork2_#t~ite26_In-113250275| |P2Thread1of1ForFork2_#t~ite26_Out-113250275|) (not .cse1)))) InVars {P2Thread1of1ForFork2_#t~ite26=|P2Thread1of1ForFork2_#t~ite26_In-113250275|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-113250275, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-113250275, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-113250275, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-113250275, ~weak$$choice2~0=~weak$$choice2~0_In-113250275} OutVars{P2Thread1of1ForFork2_#t~ite26=|P2Thread1of1ForFork2_#t~ite26_Out-113250275|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-113250275, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-113250275, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-113250275, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-113250275, ~weak$$choice2~0=~weak$$choice2~0_In-113250275, P2Thread1of1ForFork2_#t~ite27=|P2Thread1of1ForFork2_#t~ite27_Out-113250275|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite26, P2Thread1of1ForFork2_#t~ite27] because there is no mapped edge [2019-12-07 18:19:54,335 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [812] [812] L793-->L794: Formula: (and (not (= (mod v_~weak$$choice2~0_37 256) 0)) (= v_~z$r_buff0_thd3~0_119 v_~z$r_buff0_thd3~0_118)) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_119, ~weak$$choice2~0=v_~weak$$choice2~0_37} OutVars{P2Thread1of1ForFork2_#t~ite31=|v_P2Thread1of1ForFork2_#t~ite31_6|, P2Thread1of1ForFork2_#t~ite33=|v_P2Thread1of1ForFork2_#t~ite33_6|, P2Thread1of1ForFork2_#t~ite32=|v_P2Thread1of1ForFork2_#t~ite32_7|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_118, ~weak$$choice2~0=v_~weak$$choice2~0_37} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite31, P2Thread1of1ForFork2_#t~ite33, P2Thread1of1ForFork2_#t~ite32, ~z$r_buff0_thd3~0] because there is no mapped edge [2019-12-07 18:19:54,335 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [750] [750] L764-4-->L765: Formula: (= |v_P1Thread1of1ForFork1_#t~ite9_6| v_~z~0_16) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_6|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_5|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_5|, ~z~0=v_~z~0_16} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~z~0] because there is no mapped edge [2019-12-07 18:19:54,335 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] L765-->L765-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd2~0_In-1073800007 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1073800007 256)))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out-1073800007| ~z$w_buff0_used~0_In-1073800007)) (and (= |P1Thread1of1ForFork1_#t~ite11_Out-1073800007| 0) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1073800007, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1073800007} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1073800007, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out-1073800007|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1073800007} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 18:19:54,336 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [816] [816] L766-->L766-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In875675962 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In875675962 256))) (.cse3 (= (mod ~z$r_buff1_thd2~0_In875675962 256) 0)) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In875675962 256)))) (or (and (= |P1Thread1of1ForFork1_#t~ite12_Out875675962| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse3 .cse2) (= |P1Thread1of1ForFork1_#t~ite12_Out875675962| ~z$w_buff1_used~0_In875675962)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In875675962, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In875675962, ~z$w_buff1_used~0=~z$w_buff1_used~0_In875675962, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In875675962} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In875675962, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In875675962, ~z$w_buff1_used~0=~z$w_buff1_used~0_In875675962, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out875675962|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In875675962} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 18:19:54,336 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [817] [817] L767-->L767-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd2~0_In1857803482 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In1857803482 256)))) (or (and (= ~z$r_buff0_thd2~0_In1857803482 |P1Thread1of1ForFork1_#t~ite13_Out1857803482|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork1_#t~ite13_Out1857803482| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1857803482, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1857803482} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1857803482, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out1857803482|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1857803482} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 18:19:54,336 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [811] [811] L796-->L800: Formula: (and (= v_~z~0_64 v_~z$mem_tmp~0_7) (not (= 0 (mod v_~z$flush_delayed~0_10 256))) (= 0 v_~z$flush_delayed~0_9)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_7, ~z$flush_delayed~0=v_~z$flush_delayed~0_10} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_7, P2Thread1of1ForFork2_#t~ite37=|v_P2Thread1of1ForFork2_#t~ite37_5|, ~z$flush_delayed~0=v_~z$flush_delayed~0_9, ~z~0=v_~z~0_64} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite37, ~z$flush_delayed~0, ~z~0] because there is no mapped edge [2019-12-07 18:19:54,337 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [822] [822] L800-2-->L800-5: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd3~0_In1311890741 256) 0)) (.cse2 (= |P2Thread1of1ForFork2_#t~ite38_Out1311890741| |P2Thread1of1ForFork2_#t~ite39_Out1311890741|)) (.cse1 (= (mod ~z$w_buff1_used~0_In1311890741 256) 0))) (or (and (or .cse0 .cse1) .cse2 (= |P2Thread1of1ForFork2_#t~ite38_Out1311890741| ~z~0_In1311890741)) (and (not .cse0) (= |P2Thread1of1ForFork2_#t~ite38_Out1311890741| ~z$w_buff1~0_In1311890741) .cse2 (not .cse1)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1311890741, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1311890741, ~z$w_buff1~0=~z$w_buff1~0_In1311890741, ~z~0=~z~0_In1311890741} OutVars{~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1311890741, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1311890741, ~z$w_buff1~0=~z$w_buff1~0_In1311890741, ~z~0=~z~0_In1311890741, P2Thread1of1ForFork2_#t~ite39=|P2Thread1of1ForFork2_#t~ite39_Out1311890741|, P2Thread1of1ForFork2_#t~ite38=|P2Thread1of1ForFork2_#t~ite38_Out1311890741|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite39, P2Thread1of1ForFork2_#t~ite38] because there is no mapped edge [2019-12-07 18:19:54,337 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [818] [818] L801-->L801-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In-1675012109 256))) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1675012109 256)))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite40_Out-1675012109|) (not .cse0) (not .cse1)) (and (= ~z$w_buff0_used~0_In-1675012109 |P2Thread1of1ForFork2_#t~ite40_Out-1675012109|) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1675012109, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1675012109} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1675012109, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1675012109, P2Thread1of1ForFork2_#t~ite40=|P2Thread1of1ForFork2_#t~ite40_Out-1675012109|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite40] because there is no mapped edge [2019-12-07 18:19:54,337 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [821] [821] L802-->L802-2: Formula: (let ((.cse3 (= (mod ~z$r_buff1_thd3~0_In-1976866958 256) 0)) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-1976866958 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-1976866958 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-1976866958 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite41_Out-1976866958|)) (and (or .cse3 .cse2) (= |P2Thread1of1ForFork2_#t~ite41_Out-1976866958| ~z$w_buff1_used~0_In-1976866958) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1976866958, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1976866958, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1976866958, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1976866958} OutVars{P2Thread1of1ForFork2_#t~ite41=|P2Thread1of1ForFork2_#t~ite41_Out-1976866958|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1976866958, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1976866958, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1976866958, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1976866958} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite41] because there is no mapped edge [2019-12-07 18:19:54,338 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L768-->L768-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In348512507 256) 0)) (.cse1 (= (mod ~z$r_buff0_thd2~0_In348512507 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In348512507 256))) (.cse2 (= (mod ~z$r_buff1_thd2~0_In348512507 256) 0))) (or (and (= |P1Thread1of1ForFork1_#t~ite14_Out348512507| ~z$r_buff1_thd2~0_In348512507) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2))) (= |P1Thread1of1ForFork1_#t~ite14_Out348512507| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In348512507, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In348512507, ~z$w_buff1_used~0=~z$w_buff1_used~0_In348512507, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In348512507} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In348512507, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In348512507, ~z$w_buff1_used~0=~z$w_buff1_used~0_In348512507, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out348512507|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In348512507} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 18:19:54,338 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [849] [849] L768-2-->P1EXIT: Formula: (and (= |v_P1Thread1of1ForFork1_#t~ite14_26| v_~z$r_buff1_thd2~0_70) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= v_~__unbuffered_cnt~0_49 (+ v_~__unbuffered_cnt~0_50 1)) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_50, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_26|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_70, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_49, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_25|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 18:19:54,338 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [840] [840] L803-->L803-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-114217454 256))) (.cse1 (= (mod ~z$r_buff0_thd3~0_In-114217454 256) 0))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite42_Out-114217454|) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite42_Out-114217454| ~z$r_buff0_thd3~0_In-114217454)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-114217454, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-114217454} OutVars{P2Thread1of1ForFork2_#t~ite42=|P2Thread1of1ForFork2_#t~ite42_Out-114217454|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-114217454, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-114217454} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite42] because there is no mapped edge [2019-12-07 18:19:54,339 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [830] [830] L804-->L804-2: Formula: (let ((.cse2 (= 0 (mod ~z$w_buff1_used~0_In-1119912684 256))) (.cse3 (= 0 (mod ~z$r_buff1_thd3~0_In-1119912684 256))) (.cse1 (= (mod ~z$r_buff0_thd3~0_In-1119912684 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1119912684 256)))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite43_Out-1119912684|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (or .cse1 .cse0) (= ~z$r_buff1_thd3~0_In-1119912684 |P2Thread1of1ForFork2_#t~ite43_Out-1119912684|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1119912684, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1119912684, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1119912684, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1119912684} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1119912684, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1119912684, P2Thread1of1ForFork2_#t~ite43=|P2Thread1of1ForFork2_#t~ite43_Out-1119912684|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1119912684, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1119912684} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite43] because there is no mapped edge [2019-12-07 18:19:54,339 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L804-2-->P2EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_44 1) v_~__unbuffered_cnt~0_43) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= v_~z$r_buff1_thd3~0_119 |v_P2Thread1of1ForFork2_#t~ite43_26|)) InVars {P2Thread1of1ForFork2_#t~ite43=|v_P2Thread1of1ForFork2_#t~ite43_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_44} OutVars{~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_119, P2Thread1of1ForFork2_#t~ite43=|v_P2Thread1of1ForFork2_#t~ite43_25|, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_43, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#t~ite43, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 18:19:54,339 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L827-1-->L833: Formula: (and (= v_~main$tmp_guard0~0_9 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_34) 1 0)) 0 1)) (not (= 0 (mod v_~main$tmp_guard0~0_9 256)))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_34} OutVars{ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_34, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_9} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet46, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:19:54,339 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [837] [837] L833-2-->L833-5: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In-690471220 256))) (.cse2 (= |ULTIMATE.start_main_#t~ite48_Out-690471220| |ULTIMATE.start_main_#t~ite47_Out-690471220|)) (.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In-690471220 256)))) (or (and (= ~z~0_In-690471220 |ULTIMATE.start_main_#t~ite47_Out-690471220|) (or .cse0 .cse1) .cse2) (and (= ~z$w_buff1~0_In-690471220 |ULTIMATE.start_main_#t~ite47_Out-690471220|) (not .cse0) .cse2 (not .cse1)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-690471220, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-690471220, ~z$w_buff1~0=~z$w_buff1~0_In-690471220, ~z~0=~z~0_In-690471220} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-690471220, ULTIMATE.start_main_#t~ite47=|ULTIMATE.start_main_#t~ite47_Out-690471220|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-690471220, ~z$w_buff1~0=~z$w_buff1~0_In-690471220, ULTIMATE.start_main_#t~ite48=|ULTIMATE.start_main_#t~ite48_Out-690471220|, ~z~0=~z~0_In-690471220} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 18:19:54,340 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [820] [820] L834-->L834-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In1047871323 256) 0)) (.cse0 (= (mod ~z$w_buff0_used~0_In1047871323 256) 0))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite49_Out1047871323| 0) (not .cse1)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite49_Out1047871323| ~z$w_buff0_used~0_In1047871323)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1047871323, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1047871323} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1047871323, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1047871323, ULTIMATE.start_main_#t~ite49=|ULTIMATE.start_main_#t~ite49_Out1047871323|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite49] because there is no mapped edge [2019-12-07 18:19:54,340 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] L835-->L835-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In974507265 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In974507265 256))) (.cse2 (= (mod ~z$r_buff0_thd0~0_In974507265 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In974507265 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite50_Out974507265|)) (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In974507265 |ULTIMATE.start_main_#t~ite50_Out974507265|) (or .cse2 .cse3)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In974507265, ~z$w_buff0_used~0=~z$w_buff0_used~0_In974507265, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In974507265, ~z$w_buff1_used~0=~z$w_buff1_used~0_In974507265} OutVars{ULTIMATE.start_main_#t~ite50=|ULTIMATE.start_main_#t~ite50_Out974507265|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In974507265, ~z$w_buff0_used~0=~z$w_buff0_used~0_In974507265, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In974507265, ~z$w_buff1_used~0=~z$w_buff1_used~0_In974507265} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite50] because there is no mapped edge [2019-12-07 18:19:54,340 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [824] [824] L836-->L836-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In974088491 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In974088491 256)))) (or (and (= ~z$r_buff0_thd0~0_In974088491 |ULTIMATE.start_main_#t~ite51_Out974088491|) (or .cse0 .cse1)) (and (= 0 |ULTIMATE.start_main_#t~ite51_Out974088491|) (not .cse1) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In974088491, ~z$w_buff0_used~0=~z$w_buff0_used~0_In974088491} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In974088491, ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_Out974088491|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In974088491} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite51] because there is no mapped edge [2019-12-07 18:19:54,341 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [814] [814] L837-->L837-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd0~0_In1605449687 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In1605449687 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In1605449687 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In1605449687 256)))) (or (and (= |ULTIMATE.start_main_#t~ite52_Out1605449687| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite52_Out1605449687| ~z$r_buff1_thd0~0_In1605449687)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1605449687, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1605449687, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1605449687, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1605449687} OutVars{ULTIMATE.start_main_#t~ite52=|ULTIMATE.start_main_#t~ite52_Out1605449687|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1605449687, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1605449687, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1605449687, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1605449687} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52] because there is no mapped edge [2019-12-07 18:19:54,341 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [878] [878] L837-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_~main$tmp_guard1~0_27 (ite (= 0 (ite (not (and (= v_~y~0_37 2) (= 2 v_~__unbuffered_p2_EAX~0_30) (= v_~__unbuffered_p2_EBX~0_37 0) (= 2 v_~x~0_117))) 1 0)) 0 1)) (= v_ULTIMATE.start___VERIFIER_assert_~expression_16 0) (= v_ULTIMATE.start___VERIFIER_assert_~expression_16 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_12|) (= (mod v_~main$tmp_guard1~0_27 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_12|) (= v_~z$r_buff1_thd0~0_162 |v_ULTIMATE.start_main_#t~ite52_69|)) InVars {ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_69|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_37, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_30, ~y~0=v_~y~0_37, ~x~0=v_~x~0_117} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_68|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_16, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_37, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_162, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_27, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_30, ~y~0=v_~y~0_37, ~x~0=v_~x~0_117, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:19:54,393 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_a713965c-2e57-4a60-943c-972142842105/bin/uautomizer/witness.graphml [2019-12-07 18:19:54,393 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:19:54,394 INFO L168 Benchmark]: Toolchain (without parser) took 137382.47 ms. Allocated memory was 1.0 GB in the beginning and 9.4 GB in the end (delta: 8.4 GB). Free memory was 934.0 MB in the beginning and 4.4 GB in the end (delta: -3.5 GB). Peak memory consumption was 4.9 GB. Max. memory is 11.5 GB. [2019-12-07 18:19:54,394 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 955.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:19:54,394 INFO L168 Benchmark]: CACSL2BoogieTranslator took 384.39 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 88.6 MB). Free memory was 934.0 MB in the beginning and 1.1 GB in the end (delta: -122.1 MB). Peak memory consumption was 18.7 MB. Max. memory is 11.5 GB. [2019-12-07 18:19:54,394 INFO L168 Benchmark]: Boogie Procedure Inliner took 39.99 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:19:54,395 INFO L168 Benchmark]: Boogie Preprocessor took 27.91 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:19:54,395 INFO L168 Benchmark]: RCFGBuilder took 411.72 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 995.3 MB in the end (delta: 55.5 MB). Peak memory consumption was 55.5 MB. Max. memory is 11.5 GB. [2019-12-07 18:19:54,395 INFO L168 Benchmark]: TraceAbstraction took 136448.69 ms. Allocated memory was 1.1 GB in the beginning and 9.4 GB in the end (delta: 8.3 GB). Free memory was 995.3 MB in the beginning and 4.4 GB in the end (delta: -3.5 GB). Peak memory consumption was 4.8 GB. Max. memory is 11.5 GB. [2019-12-07 18:19:54,395 INFO L168 Benchmark]: Witness Printer took 66.41 ms. Allocated memory is still 9.4 GB. Free memory was 4.4 GB in the beginning and 4.4 GB in the end (delta: 49.7 MB). Peak memory consumption was 49.7 MB. Max. memory is 11.5 GB. [2019-12-07 18:19:54,397 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 955.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 384.39 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 88.6 MB). Free memory was 934.0 MB in the beginning and 1.1 GB in the end (delta: -122.1 MB). Peak memory consumption was 18.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 39.99 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 27.91 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 411.72 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 995.3 MB in the end (delta: 55.5 MB). Peak memory consumption was 55.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 136448.69 ms. Allocated memory was 1.1 GB in the beginning and 9.4 GB in the end (delta: 8.3 GB). Free memory was 995.3 MB in the beginning and 4.4 GB in the end (delta: -3.5 GB). Peak memory consumption was 4.8 GB. Max. memory is 11.5 GB. * Witness Printer took 66.41 ms. Allocated memory is still 9.4 GB. Free memory was 4.4 GB in the beginning and 4.4 GB in the end (delta: 49.7 MB). Peak memory consumption was 49.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.7s, 175 ProgramPointsBefore, 93 ProgramPointsAfterwards, 212 TransitionsBefore, 102 TransitionsAfterwards, 19004 CoEnabledTransitionPairs, 8 FixpointIterations, 32 TrivialSequentialCompositions, 49 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 32 ConcurrentYvCompositions, 32 ChoiceCompositions, 6798 VarBasedMoverChecksPositive, 289 VarBasedMoverChecksNegative, 75 SemBasedMoverChecksPositive, 285 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.2s, 0 MoverChecksTotal, 87070 CheckedPairsTotal, 113 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L823] FCALL, FORK 0 pthread_create(&t751, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L734] 1 z$r_buff1_thd0 = z$r_buff0_thd0 [L735] 1 z$r_buff1_thd1 = z$r_buff0_thd1 [L736] 1 z$r_buff1_thd2 = z$r_buff0_thd2 [L737] 1 z$r_buff1_thd3 = z$r_buff0_thd3 [L738] 1 z$r_buff0_thd1 = (_Bool)1 [L741] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L744] EXPR 1 z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L825] FCALL, FORK 0 pthread_create(&t752, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L827] FCALL, FORK 0 pthread_create(&t753, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L758] 2 x = 2 [L761] 2 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L764] 2 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L778] 3 y = 2 [L781] 3 __unbuffered_p2_EAX = y [L784] 3 weak$$choice0 = __VERIFIER_nondet_bool() [L785] 3 weak$$choice2 = __VERIFIER_nondet_bool() [L786] 3 z$flush_delayed = weak$$choice2 [L787] 3 z$mem_tmp = z VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=2, y=2, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L788] EXPR 3 !z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1) VAL [!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=2, y=2, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=0] [L788] 3 z = !z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1) [L744] 1 z = z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) [L745] 1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used [L746] 1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used [L789] 3 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff0)) [L790] 3 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff1 : z$w_buff1)) [L791] 3 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used)) [L792] EXPR 3 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=1, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0))=0, x=2, y=2, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=0] [L792] 3 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L794] EXPR 3 weak$$choice2 ? z$r_buff1_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff1_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=1, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, weak$$choice2 ? z$r_buff1_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff1_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0))=0, x=2, y=2, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=0] [L765] 2 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used [L794] 3 z$r_buff1_thd3 = weak$$choice2 ? z$r_buff1_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff1_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L795] 3 __unbuffered_p2_EBX = z VAL [__unbuffered_cnt=1, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=2, y=2, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used=0, z$w_buff1=0, z$w_buff1_used=0] [L766] 2 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used [L800] EXPR 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=2, y=2, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2=0, z$w_buff1=0, z$w_buff1_used=0] [L800] 3 z = z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) [L801] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L767] 2 z$r_buff0_thd2 = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 [L802] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L803] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L833] EXPR 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=2, y=2, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L833] 0 z = z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) [L834] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L835] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L836] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 166 locations, 2 error locations. Result: UNSAFE, OverallTime: 136.2s, OverallIterations: 37, TraceHistogramMax: 1, AutomataDifference: 31.8s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 8163 SDtfs, 13213 SDslu, 25680 SDs, 0 SdLazy, 15401 SolverSat, 711 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 11.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 523 GetRequests, 64 SyntacticMatches, 41 SemanticMatches, 418 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2258 ImplicationChecksByTransitivity, 4.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=301489occurred in iteration=6, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 83.5s AutomataMinimizationTime, 36 MinimizatonAttempts, 492679 StatesRemovedByMinimization, 33 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.9s InterpolantComputationTime, 1564 NumberOfCodeBlocks, 1564 NumberOfCodeBlocksAsserted, 37 NumberOfCheckSat, 1461 ConstructedInterpolants, 0 QuantifiedInterpolants, 454903 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 36 InterpolantComputations, 36 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...