./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix029_power.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_0895eb14-1481-4887-8296-220dee113e49/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_0895eb14-1481-4887-8296-220dee113e49/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_0895eb14-1481-4887-8296-220dee113e49/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_0895eb14-1481-4887-8296-220dee113e49/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix029_power.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_0895eb14-1481-4887-8296-220dee113e49/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_0895eb14-1481-4887-8296-220dee113e49/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 35daa092837ea7036b63be309b1abf4903b02e9b ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 12:37:56,217 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 12:37:56,218 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 12:37:56,225 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 12:37:56,226 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 12:37:56,226 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 12:37:56,228 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 12:37:56,229 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 12:37:56,231 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 12:37:56,232 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 12:37:56,233 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 12:37:56,234 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 12:37:56,234 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 12:37:56,235 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 12:37:56,236 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 12:37:56,237 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 12:37:56,237 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 12:37:56,238 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 12:37:56,239 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 12:37:56,241 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 12:37:56,242 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 12:37:56,243 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 12:37:56,243 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 12:37:56,244 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 12:37:56,245 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 12:37:56,246 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 12:37:56,246 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 12:37:56,246 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 12:37:56,246 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 12:37:56,247 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 12:37:56,247 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 12:37:56,247 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 12:37:56,248 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 12:37:56,249 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 12:37:56,249 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 12:37:56,250 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 12:37:56,250 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 12:37:56,250 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 12:37:56,251 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 12:37:56,251 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 12:37:56,252 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 12:37:56,252 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_0895eb14-1481-4887-8296-220dee113e49/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 12:37:56,265 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 12:37:56,265 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 12:37:56,266 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 12:37:56,266 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 12:37:56,266 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 12:37:56,267 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 12:37:56,267 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 12:37:56,267 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 12:37:56,267 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 12:37:56,267 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 12:37:56,268 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 12:37:56,268 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 12:37:56,268 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 12:37:56,268 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 12:37:56,268 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 12:37:56,269 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 12:37:56,269 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 12:37:56,269 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 12:37:56,269 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 12:37:56,269 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 12:37:56,270 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 12:37:56,270 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 12:37:56,270 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 12:37:56,270 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 12:37:56,270 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 12:37:56,271 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 12:37:56,271 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 12:37:56,271 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 12:37:56,271 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 12:37:56,271 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_0895eb14-1481-4887-8296-220dee113e49/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 35daa092837ea7036b63be309b1abf4903b02e9b [2019-12-07 12:37:56,380 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 12:37:56,388 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 12:37:56,390 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 12:37:56,391 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 12:37:56,392 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 12:37:56,392 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_0895eb14-1481-4887-8296-220dee113e49/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix029_power.opt.i [2019-12-07 12:37:56,429 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_0895eb14-1481-4887-8296-220dee113e49/bin/uautomizer/data/3f6272c0e/1290d72629a74530abf447254953abe8/FLAG9dbb16f01 [2019-12-07 12:37:56,895 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 12:37:56,896 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_0895eb14-1481-4887-8296-220dee113e49/sv-benchmarks/c/pthread-wmm/mix029_power.opt.i [2019-12-07 12:37:56,906 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_0895eb14-1481-4887-8296-220dee113e49/bin/uautomizer/data/3f6272c0e/1290d72629a74530abf447254953abe8/FLAG9dbb16f01 [2019-12-07 12:37:56,916 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_0895eb14-1481-4887-8296-220dee113e49/bin/uautomizer/data/3f6272c0e/1290d72629a74530abf447254953abe8 [2019-12-07 12:37:56,918 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 12:37:56,919 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 12:37:56,919 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 12:37:56,920 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 12:37:56,922 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 12:37:56,922 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 12:37:56" (1/1) ... [2019-12-07 12:37:56,924 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@551fb3cf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:37:56, skipping insertion in model container [2019-12-07 12:37:56,924 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 12:37:56" (1/1) ... [2019-12-07 12:37:56,929 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 12:37:56,962 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 12:37:57,210 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 12:37:57,217 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 12:37:57,261 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 12:37:57,306 INFO L208 MainTranslator]: Completed translation [2019-12-07 12:37:57,307 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:37:57 WrapperNode [2019-12-07 12:37:57,307 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 12:37:57,307 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 12:37:57,307 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 12:37:57,307 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 12:37:57,313 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:37:57" (1/1) ... [2019-12-07 12:37:57,326 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:37:57" (1/1) ... [2019-12-07 12:37:57,347 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 12:37:57,348 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 12:37:57,348 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 12:37:57,348 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 12:37:57,354 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:37:57" (1/1) ... [2019-12-07 12:37:57,354 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:37:57" (1/1) ... [2019-12-07 12:37:57,358 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:37:57" (1/1) ... [2019-12-07 12:37:57,358 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:37:57" (1/1) ... [2019-12-07 12:37:57,365 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:37:57" (1/1) ... [2019-12-07 12:37:57,368 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:37:57" (1/1) ... [2019-12-07 12:37:57,371 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:37:57" (1/1) ... [2019-12-07 12:37:57,374 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 12:37:57,375 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 12:37:57,375 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 12:37:57,375 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 12:37:57,375 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:37:57" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_0895eb14-1481-4887-8296-220dee113e49/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 12:37:57,419 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 12:37:57,419 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 12:37:57,420 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 12:37:57,420 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 12:37:57,420 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 12:37:57,420 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 12:37:57,420 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 12:37:57,420 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 12:37:57,420 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 12:37:57,420 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 12:37:57,421 INFO L130 BoogieDeclarations]: Found specification of procedure P3 [2019-12-07 12:37:57,421 INFO L138 BoogieDeclarations]: Found implementation of procedure P3 [2019-12-07 12:37:57,421 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 12:37:57,421 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 12:37:57,421 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 12:37:57,422 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 12:37:57,806 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 12:37:57,806 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 12:37:57,807 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:37:57 BoogieIcfgContainer [2019-12-07 12:37:57,807 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 12:37:57,808 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 12:37:57,808 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 12:37:57,810 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 12:37:57,810 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 12:37:56" (1/3) ... [2019-12-07 12:37:57,811 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3f0ea148 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 12:37:57, skipping insertion in model container [2019-12-07 12:37:57,811 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:37:57" (2/3) ... [2019-12-07 12:37:57,811 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3f0ea148 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 12:37:57, skipping insertion in model container [2019-12-07 12:37:57,811 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:37:57" (3/3) ... [2019-12-07 12:37:57,813 INFO L109 eAbstractionObserver]: Analyzing ICFG mix029_power.opt.i [2019-12-07 12:37:57,819 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 12:37:57,819 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 12:37:57,825 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 12:37:57,825 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 12:37:57,854 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,854 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,854 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,855 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,855 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,855 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,855 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,855 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,856 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork3_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,856 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork3_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,856 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,856 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,856 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,856 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,856 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,857 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,857 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,857 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,857 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,857 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,857 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,858 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,858 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,858 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,858 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,858 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,858 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,859 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,859 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,859 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,859 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,859 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,860 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,860 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,860 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,860 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,861 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,861 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,861 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,861 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,861 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,861 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,862 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,862 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,862 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,862 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,862 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,862 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,862 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,862 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,863 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,863 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,863 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,863 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,863 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,863 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,864 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,864 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,864 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,864 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,864 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,864 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,864 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,865 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,865 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,865 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,865 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,865 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,865 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,865 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,866 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,866 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,866 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,866 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,866 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,866 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,866 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,866 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,867 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,867 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,867 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,867 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,867 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,867 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,867 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,868 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,868 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,868 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,868 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,868 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,868 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,868 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,868 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,869 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,869 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,869 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,869 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,869 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,869 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,869 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 12:37:57,881 INFO L249 AbstractCegarLoop]: Starting to check reachability of 7 error locations. [2019-12-07 12:37:57,894 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 12:37:57,894 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 12:37:57,894 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 12:37:57,895 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 12:37:57,895 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 12:37:57,895 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 12:37:57,895 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 12:37:57,895 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 12:37:57,907 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 192 places, 226 transitions [2019-12-07 12:37:57,909 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 192 places, 226 transitions [2019-12-07 12:37:57,977 INFO L134 PetriNetUnfolder]: 47/222 cut-off events. [2019-12-07 12:37:57,977 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 12:37:57,987 INFO L76 FinitePrefix]: Finished finitePrefix Result has 235 conditions, 222 events. 47/222 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 586 event pairs. 12/185 useless extension candidates. Maximal degree in co-relation 190. Up to 2 conditions per place. [2019-12-07 12:37:58,003 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 192 places, 226 transitions [2019-12-07 12:37:58,044 INFO L134 PetriNetUnfolder]: 47/222 cut-off events. [2019-12-07 12:37:58,045 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 12:37:58,051 INFO L76 FinitePrefix]: Finished finitePrefix Result has 235 conditions, 222 events. 47/222 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 586 event pairs. 12/185 useless extension candidates. Maximal degree in co-relation 190. Up to 2 conditions per place. [2019-12-07 12:37:58,067 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 18432 [2019-12-07 12:37:58,067 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 12:38:01,143 WARN L192 SmtUtils]: Spent 176.00 ms on a formula simplification. DAG size of input: 97 DAG size of output: 95 [2019-12-07 12:38:01,250 INFO L206 etLargeBlockEncoding]: Checked pairs total: 86545 [2019-12-07 12:38:01,250 INFO L214 etLargeBlockEncoding]: Total number of compositions: 127 [2019-12-07 12:38:01,253 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 97 places, 103 transitions [2019-12-07 12:38:39,980 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 199530 states. [2019-12-07 12:38:39,981 INFO L276 IsEmpty]: Start isEmpty. Operand 199530 states. [2019-12-07 12:38:39,986 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-12-07 12:38:39,986 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:38:39,987 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:38:39,987 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:38:39,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:38:39,991 INFO L82 PathProgramCache]: Analyzing trace with hash 1574015469, now seen corresponding path program 1 times [2019-12-07 12:38:39,996 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:38:39,997 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [591339500] [2019-12-07 12:38:39,997 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:38:40,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:38:40,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:38:40,165 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [591339500] [2019-12-07 12:38:40,165 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:38:40,166 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 12:38:40,166 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2136920293] [2019-12-07 12:38:40,169 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:38:40,169 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:38:40,178 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:38:40,178 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:38:40,180 INFO L87 Difference]: Start difference. First operand 199530 states. Second operand 3 states. [2019-12-07 12:38:42,941 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:38:42,942 INFO L93 Difference]: Finished difference Result 198930 states and 939730 transitions. [2019-12-07 12:38:42,943 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:38:42,944 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-12-07 12:38:42,944 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:38:43,689 INFO L225 Difference]: With dead ends: 198930 [2019-12-07 12:38:43,689 INFO L226 Difference]: Without dead ends: 194562 [2019-12-07 12:38:43,690 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:38:50,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 194562 states. [2019-12-07 12:38:52,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 194562 to 194562. [2019-12-07 12:38:52,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194562 states. [2019-12-07 12:38:53,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194562 states to 194562 states and 919710 transitions. [2019-12-07 12:38:53,513 INFO L78 Accepts]: Start accepts. Automaton has 194562 states and 919710 transitions. Word has length 7 [2019-12-07 12:38:53,514 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:38:53,514 INFO L462 AbstractCegarLoop]: Abstraction has 194562 states and 919710 transitions. [2019-12-07 12:38:53,514 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:38:53,515 INFO L276 IsEmpty]: Start isEmpty. Operand 194562 states and 919710 transitions. [2019-12-07 12:38:53,518 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 12:38:53,518 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:38:53,518 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:38:53,518 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:38:53,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:38:53,519 INFO L82 PathProgramCache]: Analyzing trace with hash 1968556431, now seen corresponding path program 1 times [2019-12-07 12:38:53,519 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:38:53,519 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [30139098] [2019-12-07 12:38:53,519 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:38:53,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:38:53,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:38:53,586 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [30139098] [2019-12-07 12:38:53,586 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:38:53,587 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:38:53,587 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1790452336] [2019-12-07 12:38:53,588 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 12:38:53,588 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:38:53,588 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 12:38:53,588 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 12:38:53,588 INFO L87 Difference]: Start difference. First operand 194562 states and 919710 transitions. Second operand 4 states. [2019-12-07 12:38:58,057 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:38:58,057 INFO L93 Difference]: Finished difference Result 312518 states and 1424536 transitions. [2019-12-07 12:38:58,058 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 12:38:58,058 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 12:38:58,058 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:38:58,968 INFO L225 Difference]: With dead ends: 312518 [2019-12-07 12:38:58,968 INFO L226 Difference]: Without dead ends: 312420 [2019-12-07 12:38:58,969 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:39:06,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312420 states. [2019-12-07 12:39:10,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312420 to 280564. [2019-12-07 12:39:10,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280564 states. [2019-12-07 12:39:11,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280564 states to 280564 states and 1291349 transitions. [2019-12-07 12:39:11,928 INFO L78 Accepts]: Start accepts. Automaton has 280564 states and 1291349 transitions. Word has length 13 [2019-12-07 12:39:11,928 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:39:11,928 INFO L462 AbstractCegarLoop]: Abstraction has 280564 states and 1291349 transitions. [2019-12-07 12:39:11,928 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 12:39:11,928 INFO L276 IsEmpty]: Start isEmpty. Operand 280564 states and 1291349 transitions. [2019-12-07 12:39:11,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 12:39:11,933 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:39:11,933 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:39:11,933 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:39:11,933 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:39:11,933 INFO L82 PathProgramCache]: Analyzing trace with hash 381664219, now seen corresponding path program 1 times [2019-12-07 12:39:11,933 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:39:11,933 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1820762636] [2019-12-07 12:39:11,933 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:39:11,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:39:11,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:39:11,992 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1820762636] [2019-12-07 12:39:11,992 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:39:11,992 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:39:11,992 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1337249236] [2019-12-07 12:39:11,992 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 12:39:11,992 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:39:11,992 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 12:39:11,993 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 12:39:11,993 INFO L87 Difference]: Start difference. First operand 280564 states and 1291349 transitions. Second operand 4 states. [2019-12-07 12:39:18,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:39:18,011 INFO L93 Difference]: Finished difference Result 400666 states and 1806688 transitions. [2019-12-07 12:39:18,012 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 12:39:18,012 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 12:39:18,012 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:39:19,265 INFO L225 Difference]: With dead ends: 400666 [2019-12-07 12:39:19,265 INFO L226 Difference]: Without dead ends: 400540 [2019-12-07 12:39:19,266 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:39:27,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 400540 states. [2019-12-07 12:39:33,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 400540 to 335984. [2019-12-07 12:39:33,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 335984 states. [2019-12-07 12:39:34,789 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 335984 states to 335984 states and 1536425 transitions. [2019-12-07 12:39:34,789 INFO L78 Accepts]: Start accepts. Automaton has 335984 states and 1536425 transitions. Word has length 15 [2019-12-07 12:39:34,789 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:39:34,789 INFO L462 AbstractCegarLoop]: Abstraction has 335984 states and 1536425 transitions. [2019-12-07 12:39:34,790 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 12:39:34,790 INFO L276 IsEmpty]: Start isEmpty. Operand 335984 states and 1536425 transitions. [2019-12-07 12:39:34,793 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 12:39:34,793 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:39:34,793 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:39:34,793 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:39:34,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:39:34,794 INFO L82 PathProgramCache]: Analyzing trace with hash 1895054000, now seen corresponding path program 1 times [2019-12-07 12:39:34,794 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:39:34,794 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [529541036] [2019-12-07 12:39:34,794 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:39:34,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:39:34,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:39:34,854 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [529541036] [2019-12-07 12:39:34,854 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:39:34,854 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:39:34,854 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1920997787] [2019-12-07 12:39:34,855 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 12:39:34,855 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:39:34,855 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 12:39:34,855 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 12:39:34,855 INFO L87 Difference]: Start difference. First operand 335984 states and 1536425 transitions. Second operand 4 states. [2019-12-07 12:39:41,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:39:41,334 INFO L93 Difference]: Finished difference Result 416162 states and 1884830 transitions. [2019-12-07 12:39:41,335 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 12:39:41,335 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 12:39:41,335 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:39:42,655 INFO L225 Difference]: With dead ends: 416162 [2019-12-07 12:39:42,656 INFO L226 Difference]: Without dead ends: 416162 [2019-12-07 12:39:42,656 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:39:51,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 416162 states. [2019-12-07 12:39:57,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 416162 to 354242. [2019-12-07 12:39:57,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 354242 states. [2019-12-07 12:39:58,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 354242 states to 354242 states and 1619952 transitions. [2019-12-07 12:39:58,602 INFO L78 Accepts]: Start accepts. Automaton has 354242 states and 1619952 transitions. Word has length 15 [2019-12-07 12:39:58,602 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:39:58,602 INFO L462 AbstractCegarLoop]: Abstraction has 354242 states and 1619952 transitions. [2019-12-07 12:39:58,602 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 12:39:58,602 INFO L276 IsEmpty]: Start isEmpty. Operand 354242 states and 1619952 transitions. [2019-12-07 12:39:58,629 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 12:39:58,629 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:39:58,629 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:39:58,629 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:39:58,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:39:58,630 INFO L82 PathProgramCache]: Analyzing trace with hash -244633219, now seen corresponding path program 1 times [2019-12-07 12:39:58,630 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:39:58,630 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [173907880] [2019-12-07 12:39:58,630 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:39:58,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:39:58,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:39:58,691 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [173907880] [2019-12-07 12:39:58,691 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:39:58,691 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:39:58,691 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1265858362] [2019-12-07 12:39:58,691 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 12:39:58,692 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:39:58,692 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 12:39:58,692 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:39:58,692 INFO L87 Difference]: Start difference. First operand 354242 states and 1619952 transitions. Second operand 5 states. [2019-12-07 12:40:07,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:07,204 INFO L93 Difference]: Finished difference Result 524522 states and 2349272 transitions. [2019-12-07 12:40:07,205 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 12:40:07,205 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2019-12-07 12:40:07,205 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:08,811 INFO L225 Difference]: With dead ends: 524522 [2019-12-07 12:40:08,811 INFO L226 Difference]: Without dead ends: 524242 [2019-12-07 12:40:08,811 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 12:40:18,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 524242 states. [2019-12-07 12:40:25,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 524242 to 389200. [2019-12-07 12:40:25,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 389200 states. [2019-12-07 12:40:27,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389200 states to 389200 states and 1771393 transitions. [2019-12-07 12:40:27,041 INFO L78 Accepts]: Start accepts. Automaton has 389200 states and 1771393 transitions. Word has length 21 [2019-12-07 12:40:27,041 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:27,042 INFO L462 AbstractCegarLoop]: Abstraction has 389200 states and 1771393 transitions. [2019-12-07 12:40:27,042 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 12:40:27,042 INFO L276 IsEmpty]: Start isEmpty. Operand 389200 states and 1771393 transitions. [2019-12-07 12:40:27,065 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 12:40:27,065 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:27,066 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:27,066 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:27,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:27,066 INFO L82 PathProgramCache]: Analyzing trace with hash 1268756562, now seen corresponding path program 1 times [2019-12-07 12:40:27,066 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:27,066 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335769762] [2019-12-07 12:40:27,066 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:27,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:40:27,111 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:40:27,111 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [335769762] [2019-12-07 12:40:27,111 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:40:27,111 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:40:27,111 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1565052555] [2019-12-07 12:40:27,112 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 12:40:27,112 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:40:27,112 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 12:40:27,112 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 12:40:27,112 INFO L87 Difference]: Start difference. First operand 389200 states and 1771393 transitions. Second operand 4 states. [2019-12-07 12:40:28,821 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:28,821 INFO L93 Difference]: Finished difference Result 238312 states and 967580 transitions. [2019-12-07 12:40:28,822 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 12:40:28,822 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 21 [2019-12-07 12:40:28,822 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:29,447 INFO L225 Difference]: With dead ends: 238312 [2019-12-07 12:40:29,448 INFO L226 Difference]: Without dead ends: 229238 [2019-12-07 12:40:29,448 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:40:37,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 229238 states. [2019-12-07 12:40:40,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 229238 to 229238. [2019-12-07 12:40:40,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 229238 states. [2019-12-07 12:40:41,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 229238 states to 229238 states and 933345 transitions. [2019-12-07 12:40:41,128 INFO L78 Accepts]: Start accepts. Automaton has 229238 states and 933345 transitions. Word has length 21 [2019-12-07 12:40:41,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:41,128 INFO L462 AbstractCegarLoop]: Abstraction has 229238 states and 933345 transitions. [2019-12-07 12:40:41,128 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 12:40:41,128 INFO L276 IsEmpty]: Start isEmpty. Operand 229238 states and 933345 transitions. [2019-12-07 12:40:41,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 12:40:41,141 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:41,141 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:41,141 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:41,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:41,142 INFO L82 PathProgramCache]: Analyzing trace with hash -1702977174, now seen corresponding path program 1 times [2019-12-07 12:40:41,142 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:41,142 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706530668] [2019-12-07 12:40:41,142 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:41,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:40:41,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:40:41,195 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1706530668] [2019-12-07 12:40:41,195 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:40:41,196 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 12:40:41,196 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1640361812] [2019-12-07 12:40:41,196 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 12:40:41,196 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:40:41,196 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 12:40:41,197 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:40:41,197 INFO L87 Difference]: Start difference. First operand 229238 states and 933345 transitions. Second operand 5 states. [2019-12-07 12:40:41,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:41,377 INFO L93 Difference]: Finished difference Result 47123 states and 156709 transitions. [2019-12-07 12:40:41,378 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 12:40:41,378 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 22 [2019-12-07 12:40:41,378 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:41,442 INFO L225 Difference]: With dead ends: 47123 [2019-12-07 12:40:41,442 INFO L226 Difference]: Without dead ends: 41581 [2019-12-07 12:40:41,443 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 12:40:41,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41581 states. [2019-12-07 12:40:42,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41581 to 41581. [2019-12-07 12:40:42,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41581 states. [2019-12-07 12:40:42,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41581 states to 41581 states and 136155 transitions. [2019-12-07 12:40:42,105 INFO L78 Accepts]: Start accepts. Automaton has 41581 states and 136155 transitions. Word has length 22 [2019-12-07 12:40:42,106 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:42,106 INFO L462 AbstractCegarLoop]: Abstraction has 41581 states and 136155 transitions. [2019-12-07 12:40:42,106 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 12:40:42,106 INFO L276 IsEmpty]: Start isEmpty. Operand 41581 states and 136155 transitions. [2019-12-07 12:40:42,117 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 12:40:42,118 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:42,118 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:42,118 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:42,118 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:42,118 INFO L82 PathProgramCache]: Analyzing trace with hash 680964803, now seen corresponding path program 1 times [2019-12-07 12:40:42,118 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:42,118 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [367516276] [2019-12-07 12:40:42,118 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:42,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:40:42,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:40:42,176 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [367516276] [2019-12-07 12:40:42,177 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:40:42,177 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:40:42,177 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [900329895] [2019-12-07 12:40:42,177 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 12:40:42,177 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:40:42,178 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 12:40:42,178 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:40:42,178 INFO L87 Difference]: Start difference. First operand 41581 states and 136155 transitions. Second operand 5 states. [2019-12-07 12:40:42,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:42,911 INFO L93 Difference]: Finished difference Result 56318 states and 180086 transitions. [2019-12-07 12:40:42,911 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 12:40:42,911 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2019-12-07 12:40:42,912 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:42,993 INFO L225 Difference]: With dead ends: 56318 [2019-12-07 12:40:42,993 INFO L226 Difference]: Without dead ends: 56318 [2019-12-07 12:40:42,994 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 12:40:43,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56318 states. [2019-12-07 12:40:43,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56318 to 46548. [2019-12-07 12:40:43,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46548 states. [2019-12-07 12:40:43,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46548 states to 46548 states and 151553 transitions. [2019-12-07 12:40:43,776 INFO L78 Accepts]: Start accepts. Automaton has 46548 states and 151553 transitions. Word has length 28 [2019-12-07 12:40:43,776 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:43,776 INFO L462 AbstractCegarLoop]: Abstraction has 46548 states and 151553 transitions. [2019-12-07 12:40:43,776 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 12:40:43,776 INFO L276 IsEmpty]: Start isEmpty. Operand 46548 states and 151553 transitions. [2019-12-07 12:40:43,789 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 12:40:43,790 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:43,790 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:43,790 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:43,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:43,790 INFO L82 PathProgramCache]: Analyzing trace with hash 1665046243, now seen corresponding path program 1 times [2019-12-07 12:40:43,790 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:43,790 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1405139369] [2019-12-07 12:40:43,790 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:43,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:40:43,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:40:43,843 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1405139369] [2019-12-07 12:40:43,843 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:40:43,843 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:40:43,843 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [467913653] [2019-12-07 12:40:43,844 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 12:40:43,844 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:40:43,844 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 12:40:43,844 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:40:43,844 INFO L87 Difference]: Start difference. First operand 46548 states and 151553 transitions. Second operand 5 states. [2019-12-07 12:40:44,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:44,224 INFO L93 Difference]: Finished difference Result 61151 states and 195257 transitions. [2019-12-07 12:40:44,225 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 12:40:44,225 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2019-12-07 12:40:44,225 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:44,315 INFO L225 Difference]: With dead ends: 61151 [2019-12-07 12:40:44,315 INFO L226 Difference]: Without dead ends: 61151 [2019-12-07 12:40:44,315 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 12:40:44,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61151 states. [2019-12-07 12:40:45,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61151 to 48725. [2019-12-07 12:40:45,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48725 states. [2019-12-07 12:40:45,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48725 states to 48725 states and 158325 transitions. [2019-12-07 12:40:45,420 INFO L78 Accepts]: Start accepts. Automaton has 48725 states and 158325 transitions. Word has length 28 [2019-12-07 12:40:45,420 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:45,420 INFO L462 AbstractCegarLoop]: Abstraction has 48725 states and 158325 transitions. [2019-12-07 12:40:45,420 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 12:40:45,421 INFO L276 IsEmpty]: Start isEmpty. Operand 48725 states and 158325 transitions. [2019-12-07 12:40:45,443 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 12:40:45,443 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:45,444 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:45,444 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:45,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:45,444 INFO L82 PathProgramCache]: Analyzing trace with hash -1021179047, now seen corresponding path program 1 times [2019-12-07 12:40:45,444 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:45,444 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [9765106] [2019-12-07 12:40:45,444 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:45,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:40:45,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:40:45,562 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [9765106] [2019-12-07 12:40:45,562 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:40:45,562 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:40:45,562 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [727064358] [2019-12-07 12:40:45,562 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 12:40:45,562 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:40:45,562 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 12:40:45,563 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 12:40:45,563 INFO L87 Difference]: Start difference. First operand 48725 states and 158325 transitions. Second operand 7 states. [2019-12-07 12:40:46,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:46,622 INFO L93 Difference]: Finished difference Result 64924 states and 206124 transitions. [2019-12-07 12:40:46,622 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-12-07 12:40:46,622 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 34 [2019-12-07 12:40:46,622 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:46,715 INFO L225 Difference]: With dead ends: 64924 [2019-12-07 12:40:46,716 INFO L226 Difference]: Without dead ends: 64917 [2019-12-07 12:40:46,716 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 1 SyntacticMatches, 4 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 28 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=68, Invalid=172, Unknown=0, NotChecked=0, Total=240 [2019-12-07 12:40:46,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64917 states. [2019-12-07 12:40:47,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64917 to 47680. [2019-12-07 12:40:47,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47680 states. [2019-12-07 12:40:47,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47680 states to 47680 states and 154680 transitions. [2019-12-07 12:40:47,575 INFO L78 Accepts]: Start accepts. Automaton has 47680 states and 154680 transitions. Word has length 34 [2019-12-07 12:40:47,575 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:47,575 INFO L462 AbstractCegarLoop]: Abstraction has 47680 states and 154680 transitions. [2019-12-07 12:40:47,575 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 12:40:47,575 INFO L276 IsEmpty]: Start isEmpty. Operand 47680 states and 154680 transitions. [2019-12-07 12:40:47,592 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 12:40:47,592 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:47,592 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:47,593 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:47,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:47,593 INFO L82 PathProgramCache]: Analyzing trace with hash 757208249, now seen corresponding path program 2 times [2019-12-07 12:40:47,593 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:47,593 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1445409221] [2019-12-07 12:40:47,593 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:47,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:40:47,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:40:47,643 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1445409221] [2019-12-07 12:40:47,643 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:40:47,643 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:40:47,643 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [752922409] [2019-12-07 12:40:47,644 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 12:40:47,644 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:40:47,644 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 12:40:47,644 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-12-07 12:40:47,644 INFO L87 Difference]: Start difference. First operand 47680 states and 154680 transitions. Second operand 6 states. [2019-12-07 12:40:47,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:47,734 INFO L93 Difference]: Finished difference Result 14800 states and 46361 transitions. [2019-12-07 12:40:47,735 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 12:40:47,735 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 34 [2019-12-07 12:40:47,735 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:47,752 INFO L225 Difference]: With dead ends: 14800 [2019-12-07 12:40:47,752 INFO L226 Difference]: Without dead ends: 13527 [2019-12-07 12:40:47,753 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-12-07 12:40:47,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13527 states. [2019-12-07 12:40:47,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13527 to 13247. [2019-12-07 12:40:47,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13247 states. [2019-12-07 12:40:47,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13247 states to 13247 states and 41733 transitions. [2019-12-07 12:40:47,943 INFO L78 Accepts]: Start accepts. Automaton has 13247 states and 41733 transitions. Word has length 34 [2019-12-07 12:40:47,943 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:47,943 INFO L462 AbstractCegarLoop]: Abstraction has 13247 states and 41733 transitions. [2019-12-07 12:40:47,943 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 12:40:47,943 INFO L276 IsEmpty]: Start isEmpty. Operand 13247 states and 41733 transitions. [2019-12-07 12:40:47,955 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-12-07 12:40:47,955 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:47,955 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:47,955 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:47,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:47,956 INFO L82 PathProgramCache]: Analyzing trace with hash 389547658, now seen corresponding path program 1 times [2019-12-07 12:40:47,956 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:47,956 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [444905875] [2019-12-07 12:40:47,956 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:47,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:40:48,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:40:48,087 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [444905875] [2019-12-07 12:40:48,087 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:40:48,087 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 12:40:48,088 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [790008813] [2019-12-07 12:40:48,088 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 12:40:48,088 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:40:48,088 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 12:40:48,088 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2019-12-07 12:40:48,088 INFO L87 Difference]: Start difference. First operand 13247 states and 41733 transitions. Second operand 8 states. [2019-12-07 12:40:48,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:48,617 INFO L93 Difference]: Finished difference Result 16899 states and 51970 transitions. [2019-12-07 12:40:48,617 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-12-07 12:40:48,618 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 40 [2019-12-07 12:40:48,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:48,638 INFO L225 Difference]: With dead ends: 16899 [2019-12-07 12:40:48,638 INFO L226 Difference]: Without dead ends: 16899 [2019-12-07 12:40:48,638 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 1 SyntacticMatches, 4 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=67, Invalid=173, Unknown=0, NotChecked=0, Total=240 [2019-12-07 12:40:48,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16899 states. [2019-12-07 12:40:48,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16899 to 12329. [2019-12-07 12:40:48,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12329 states. [2019-12-07 12:40:48,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12329 states to 12329 states and 38961 transitions. [2019-12-07 12:40:48,865 INFO L78 Accepts]: Start accepts. Automaton has 12329 states and 38961 transitions. Word has length 40 [2019-12-07 12:40:48,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:48,865 INFO L462 AbstractCegarLoop]: Abstraction has 12329 states and 38961 transitions. [2019-12-07 12:40:48,866 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 12:40:48,866 INFO L276 IsEmpty]: Start isEmpty. Operand 12329 states and 38961 transitions. [2019-12-07 12:40:48,878 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-12-07 12:40:48,878 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:48,878 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:48,878 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:48,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:48,879 INFO L82 PathProgramCache]: Analyzing trace with hash -963635776, now seen corresponding path program 1 times [2019-12-07 12:40:48,879 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:48,879 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [181041280] [2019-12-07 12:40:48,879 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:48,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:40:48,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:40:48,978 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [181041280] [2019-12-07 12:40:48,978 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:40:48,978 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 12:40:48,978 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497377935] [2019-12-07 12:40:48,979 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 12:40:48,979 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:40:48,979 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 12:40:48,979 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2019-12-07 12:40:48,979 INFO L87 Difference]: Start difference. First operand 12329 states and 38961 transitions. Second operand 8 states. [2019-12-07 12:40:50,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:50,500 INFO L93 Difference]: Finished difference Result 13718 states and 42086 transitions. [2019-12-07 12:40:50,501 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-12-07 12:40:50,501 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 54 [2019-12-07 12:40:50,501 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:50,531 INFO L225 Difference]: With dead ends: 13718 [2019-12-07 12:40:50,531 INFO L226 Difference]: Without dead ends: 13716 [2019-12-07 12:40:50,532 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 0 SyntacticMatches, 4 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 110 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=119, Invalid=433, Unknown=0, NotChecked=0, Total=552 [2019-12-07 12:40:50,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13716 states. [2019-12-07 12:40:50,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13716 to 12806. [2019-12-07 12:40:50,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12806 states. [2019-12-07 12:40:50,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12806 states to 12806 states and 39936 transitions. [2019-12-07 12:40:50,721 INFO L78 Accepts]: Start accepts. Automaton has 12806 states and 39936 transitions. Word has length 54 [2019-12-07 12:40:50,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:50,721 INFO L462 AbstractCegarLoop]: Abstraction has 12806 states and 39936 transitions. [2019-12-07 12:40:50,721 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 12:40:50,721 INFO L276 IsEmpty]: Start isEmpty. Operand 12806 states and 39936 transitions. [2019-12-07 12:40:50,734 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 12:40:50,734 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:50,734 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:50,734 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:50,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:50,734 INFO L82 PathProgramCache]: Analyzing trace with hash 1576557291, now seen corresponding path program 1 times [2019-12-07 12:40:50,734 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:50,735 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1781900723] [2019-12-07 12:40:50,735 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:50,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:40:50,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:40:50,774 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1781900723] [2019-12-07 12:40:50,774 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:40:50,774 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:40:50,775 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [97773290] [2019-12-07 12:40:50,775 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:40:50,775 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:40:50,775 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:40:50,775 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:40:50,775 INFO L87 Difference]: Start difference. First operand 12806 states and 39936 transitions. Second operand 3 states. [2019-12-07 12:40:50,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:50,833 INFO L93 Difference]: Finished difference Result 13456 states and 41374 transitions. [2019-12-07 12:40:50,834 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:40:50,834 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 56 [2019-12-07 12:40:50,834 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:50,849 INFO L225 Difference]: With dead ends: 13456 [2019-12-07 12:40:50,850 INFO L226 Difference]: Without dead ends: 13456 [2019-12-07 12:40:50,850 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:40:50,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13456 states. [2019-12-07 12:40:51,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13456 to 13005. [2019-12-07 12:40:51,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13005 states. [2019-12-07 12:40:51,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13005 states to 13005 states and 40432 transitions. [2019-12-07 12:40:51,053 INFO L78 Accepts]: Start accepts. Automaton has 13005 states and 40432 transitions. Word has length 56 [2019-12-07 12:40:51,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:51,053 INFO L462 AbstractCegarLoop]: Abstraction has 13005 states and 40432 transitions. [2019-12-07 12:40:51,053 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:40:51,054 INFO L276 IsEmpty]: Start isEmpty. Operand 13005 states and 40432 transitions. [2019-12-07 12:40:51,071 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 12:40:51,071 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:51,071 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:51,071 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:51,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:51,071 INFO L82 PathProgramCache]: Analyzing trace with hash 1392512628, now seen corresponding path program 1 times [2019-12-07 12:40:51,071 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:51,072 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [152612139] [2019-12-07 12:40:51,072 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:51,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:40:51,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:40:51,127 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [152612139] [2019-12-07 12:40:51,127 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:40:51,127 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:40:51,128 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2008404570] [2019-12-07 12:40:51,128 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 12:40:51,128 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:40:51,128 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 12:40:51,128 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:40:51,128 INFO L87 Difference]: Start difference. First operand 13005 states and 40432 transitions. Second operand 5 states. [2019-12-07 12:40:51,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:51,521 INFO L93 Difference]: Finished difference Result 19736 states and 61251 transitions. [2019-12-07 12:40:51,521 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 12:40:51,521 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2019-12-07 12:40:51,521 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:51,545 INFO L225 Difference]: With dead ends: 19736 [2019-12-07 12:40:51,545 INFO L226 Difference]: Without dead ends: 19736 [2019-12-07 12:40:51,545 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 12:40:51,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19736 states. [2019-12-07 12:40:51,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19736 to 16818. [2019-12-07 12:40:51,773 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16818 states. [2019-12-07 12:40:51,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16818 states to 16818 states and 52673 transitions. [2019-12-07 12:40:51,804 INFO L78 Accepts]: Start accepts. Automaton has 16818 states and 52673 transitions. Word has length 56 [2019-12-07 12:40:51,804 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:51,804 INFO L462 AbstractCegarLoop]: Abstraction has 16818 states and 52673 transitions. [2019-12-07 12:40:51,804 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 12:40:51,804 INFO L276 IsEmpty]: Start isEmpty. Operand 16818 states and 52673 transitions. [2019-12-07 12:40:51,820 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 12:40:51,820 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:51,821 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:51,821 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:51,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:51,821 INFO L82 PathProgramCache]: Analyzing trace with hash 2137051444, now seen corresponding path program 2 times [2019-12-07 12:40:51,821 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:51,821 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430457702] [2019-12-07 12:40:51,821 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:51,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:40:51,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:40:51,907 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [430457702] [2019-12-07 12:40:51,907 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:40:51,907 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 12:40:51,907 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [890944461] [2019-12-07 12:40:51,907 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 12:40:51,907 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:40:51,908 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 12:40:51,908 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 12:40:51,908 INFO L87 Difference]: Start difference. First operand 16818 states and 52673 transitions. Second operand 6 states. [2019-12-07 12:40:52,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:52,066 INFO L93 Difference]: Finished difference Result 21337 states and 67974 transitions. [2019-12-07 12:40:52,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 12:40:52,066 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 56 [2019-12-07 12:40:52,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:52,092 INFO L225 Difference]: With dead ends: 21337 [2019-12-07 12:40:52,092 INFO L226 Difference]: Without dead ends: 21220 [2019-12-07 12:40:52,092 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2019-12-07 12:40:52,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21220 states. [2019-12-07 12:40:52,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21220 to 17092. [2019-12-07 12:40:52,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17092 states. [2019-12-07 12:40:52,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17092 states to 17092 states and 53329 transitions. [2019-12-07 12:40:52,355 INFO L78 Accepts]: Start accepts. Automaton has 17092 states and 53329 transitions. Word has length 56 [2019-12-07 12:40:52,355 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:52,355 INFO L462 AbstractCegarLoop]: Abstraction has 17092 states and 53329 transitions. [2019-12-07 12:40:52,355 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 12:40:52,355 INFO L276 IsEmpty]: Start isEmpty. Operand 17092 states and 53329 transitions. [2019-12-07 12:40:52,372 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 12:40:52,372 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:52,372 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:52,372 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:52,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:52,372 INFO L82 PathProgramCache]: Analyzing trace with hash -23503317, now seen corresponding path program 1 times [2019-12-07 12:40:52,372 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:52,372 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [379938249] [2019-12-07 12:40:52,373 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:52,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:40:52,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:40:52,412 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [379938249] [2019-12-07 12:40:52,413 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:40:52,413 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:40:52,413 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [937372779] [2019-12-07 12:40:52,413 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 12:40:52,413 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:40:52,413 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 12:40:52,413 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:40:52,413 INFO L87 Difference]: Start difference. First operand 17092 states and 53329 transitions. Second operand 5 states. [2019-12-07 12:40:52,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:52,958 INFO L93 Difference]: Finished difference Result 23794 states and 73955 transitions. [2019-12-07 12:40:52,959 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 12:40:52,959 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2019-12-07 12:40:52,960 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:53,002 INFO L225 Difference]: With dead ends: 23794 [2019-12-07 12:40:53,002 INFO L226 Difference]: Without dead ends: 23794 [2019-12-07 12:40:53,002 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 12:40:53,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23794 states. [2019-12-07 12:40:53,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23794 to 19596. [2019-12-07 12:40:53,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19596 states. [2019-12-07 12:40:53,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19596 states to 19596 states and 61427 transitions. [2019-12-07 12:40:53,299 INFO L78 Accepts]: Start accepts. Automaton has 19596 states and 61427 transitions. Word has length 56 [2019-12-07 12:40:53,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:53,300 INFO L462 AbstractCegarLoop]: Abstraction has 19596 states and 61427 transitions. [2019-12-07 12:40:53,300 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 12:40:53,300 INFO L276 IsEmpty]: Start isEmpty. Operand 19596 states and 61427 transitions. [2019-12-07 12:40:53,319 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 12:40:53,319 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:53,320 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:53,320 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:53,320 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:53,320 INFO L82 PathProgramCache]: Analyzing trace with hash 1567548645, now seen corresponding path program 2 times [2019-12-07 12:40:53,320 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:53,320 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1450178536] [2019-12-07 12:40:53,320 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:53,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:40:53,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:40:53,356 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1450178536] [2019-12-07 12:40:53,356 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:40:53,356 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:40:53,356 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [381807307] [2019-12-07 12:40:53,357 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:40:53,357 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:40:53,357 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:40:53,357 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:40:53,357 INFO L87 Difference]: Start difference. First operand 19596 states and 61427 transitions. Second operand 3 states. [2019-12-07 12:40:53,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:53,435 INFO L93 Difference]: Finished difference Result 19596 states and 61381 transitions. [2019-12-07 12:40:53,436 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:40:53,436 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 56 [2019-12-07 12:40:53,436 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:53,461 INFO L225 Difference]: With dead ends: 19596 [2019-12-07 12:40:53,461 INFO L226 Difference]: Without dead ends: 19596 [2019-12-07 12:40:53,461 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:40:53,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19596 states. [2019-12-07 12:40:53,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19596 to 17573. [2019-12-07 12:40:53,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17573 states. [2019-12-07 12:40:53,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17573 states to 17573 states and 55009 transitions. [2019-12-07 12:40:53,712 INFO L78 Accepts]: Start accepts. Automaton has 17573 states and 55009 transitions. Word has length 56 [2019-12-07 12:40:53,712 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:53,712 INFO L462 AbstractCegarLoop]: Abstraction has 17573 states and 55009 transitions. [2019-12-07 12:40:53,712 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:40:53,712 INFO L276 IsEmpty]: Start isEmpty. Operand 17573 states and 55009 transitions. [2019-12-07 12:40:53,729 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-12-07 12:40:53,729 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:53,729 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:53,729 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:53,729 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:53,729 INFO L82 PathProgramCache]: Analyzing trace with hash -118181578, now seen corresponding path program 1 times [2019-12-07 12:40:53,729 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:53,729 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [608017275] [2019-12-07 12:40:53,730 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:53,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:40:53,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:40:53,780 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [608017275] [2019-12-07 12:40:53,780 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:40:53,780 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 12:40:53,781 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [833519460] [2019-12-07 12:40:53,781 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 12:40:53,781 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:40:53,781 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 12:40:53,781 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 12:40:53,781 INFO L87 Difference]: Start difference. First operand 17573 states and 55009 transitions. Second operand 7 states. [2019-12-07 12:40:53,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:53,887 INFO L93 Difference]: Finished difference Result 13931 states and 46873 transitions. [2019-12-07 12:40:53,888 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 12:40:53,888 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 57 [2019-12-07 12:40:53,888 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:53,909 INFO L225 Difference]: With dead ends: 13931 [2019-12-07 12:40:53,909 INFO L226 Difference]: Without dead ends: 13837 [2019-12-07 12:40:53,910 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2019-12-07 12:40:53,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13837 states. [2019-12-07 12:40:54,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13837 to 11273. [2019-12-07 12:40:54,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11273 states. [2019-12-07 12:40:54,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11273 states to 11273 states and 38292 transitions. [2019-12-07 12:40:54,089 INFO L78 Accepts]: Start accepts. Automaton has 11273 states and 38292 transitions. Word has length 57 [2019-12-07 12:40:54,090 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:54,090 INFO L462 AbstractCegarLoop]: Abstraction has 11273 states and 38292 transitions. [2019-12-07 12:40:54,090 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 12:40:54,090 INFO L276 IsEmpty]: Start isEmpty. Operand 11273 states and 38292 transitions. [2019-12-07 12:40:54,100 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 12:40:54,100 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:54,100 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:54,101 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:54,101 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:54,101 INFO L82 PathProgramCache]: Analyzing trace with hash 42152852, now seen corresponding path program 1 times [2019-12-07 12:40:54,101 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:54,101 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345964964] [2019-12-07 12:40:54,101 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:54,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:40:54,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:40:54,167 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [345964964] [2019-12-07 12:40:54,167 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:40:54,167 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:40:54,167 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [59663249] [2019-12-07 12:40:54,167 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 12:40:54,167 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:40:54,167 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 12:40:54,167 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 12:40:54,168 INFO L87 Difference]: Start difference. First operand 11273 states and 38292 transitions. Second operand 6 states. [2019-12-07 12:40:54,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:54,247 INFO L93 Difference]: Finished difference Result 15761 states and 51280 transitions. [2019-12-07 12:40:54,247 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 12:40:54,247 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 68 [2019-12-07 12:40:54,247 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:54,260 INFO L225 Difference]: With dead ends: 15761 [2019-12-07 12:40:54,260 INFO L226 Difference]: Without dead ends: 10090 [2019-12-07 12:40:54,260 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 12:40:54,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10090 states. [2019-12-07 12:40:54,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10090 to 10090. [2019-12-07 12:40:54,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10090 states. [2019-12-07 12:40:54,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10090 states to 10090 states and 33709 transitions. [2019-12-07 12:40:54,405 INFO L78 Accepts]: Start accepts. Automaton has 10090 states and 33709 transitions. Word has length 68 [2019-12-07 12:40:54,405 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:54,405 INFO L462 AbstractCegarLoop]: Abstraction has 10090 states and 33709 transitions. [2019-12-07 12:40:54,405 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 12:40:54,405 INFO L276 IsEmpty]: Start isEmpty. Operand 10090 states and 33709 transitions. [2019-12-07 12:40:54,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 12:40:54,415 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:54,415 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:54,415 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:54,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:54,416 INFO L82 PathProgramCache]: Analyzing trace with hash -90149360, now seen corresponding path program 2 times [2019-12-07 12:40:54,416 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:54,416 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133186887] [2019-12-07 12:40:54,416 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:54,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:40:54,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:40:54,447 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [133186887] [2019-12-07 12:40:54,447 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:40:54,447 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:40:54,447 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [921770625] [2019-12-07 12:40:54,447 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:40:54,447 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:40:54,447 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:40:54,448 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:40:54,448 INFO L87 Difference]: Start difference. First operand 10090 states and 33709 transitions. Second operand 3 states. [2019-12-07 12:40:54,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:54,488 INFO L93 Difference]: Finished difference Result 8802 states and 28807 transitions. [2019-12-07 12:40:54,488 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:40:54,488 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 68 [2019-12-07 12:40:54,488 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:54,499 INFO L225 Difference]: With dead ends: 8802 [2019-12-07 12:40:54,499 INFO L226 Difference]: Without dead ends: 8802 [2019-12-07 12:40:54,500 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:40:54,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8802 states. [2019-12-07 12:40:54,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8802 to 8302. [2019-12-07 12:40:54,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8302 states. [2019-12-07 12:40:54,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8302 states to 8302 states and 27307 transitions. [2019-12-07 12:40:54,620 INFO L78 Accepts]: Start accepts. Automaton has 8302 states and 27307 transitions. Word has length 68 [2019-12-07 12:40:54,620 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:54,620 INFO L462 AbstractCegarLoop]: Abstraction has 8302 states and 27307 transitions. [2019-12-07 12:40:54,620 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:40:54,620 INFO L276 IsEmpty]: Start isEmpty. Operand 8302 states and 27307 transitions. [2019-12-07 12:40:54,628 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-12-07 12:40:54,628 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:54,628 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:54,628 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:54,628 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:54,628 INFO L82 PathProgramCache]: Analyzing trace with hash -1676616056, now seen corresponding path program 1 times [2019-12-07 12:40:54,628 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:54,628 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296097104] [2019-12-07 12:40:54,629 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:54,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:40:54,678 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:40:54,678 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1296097104] [2019-12-07 12:40:54,678 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:40:54,678 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 12:40:54,678 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [843043276] [2019-12-07 12:40:54,678 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 12:40:54,679 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:40:54,679 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 12:40:54,679 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 12:40:54,679 INFO L87 Difference]: Start difference. First operand 8302 states and 27307 transitions. Second operand 6 states. [2019-12-07 12:40:54,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:54,986 INFO L93 Difference]: Finished difference Result 12121 states and 39504 transitions. [2019-12-07 12:40:54,987 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 12:40:54,987 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 69 [2019-12-07 12:40:54,987 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:55,001 INFO L225 Difference]: With dead ends: 12121 [2019-12-07 12:40:55,001 INFO L226 Difference]: Without dead ends: 12121 [2019-12-07 12:40:55,001 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 6 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-12-07 12:40:55,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12121 states. [2019-12-07 12:40:55,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12121 to 8330. [2019-12-07 12:40:55,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8330 states. [2019-12-07 12:40:55,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8330 states to 8330 states and 27401 transitions. [2019-12-07 12:40:55,144 INFO L78 Accepts]: Start accepts. Automaton has 8330 states and 27401 transitions. Word has length 69 [2019-12-07 12:40:55,144 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:55,144 INFO L462 AbstractCegarLoop]: Abstraction has 8330 states and 27401 transitions. [2019-12-07 12:40:55,144 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 12:40:55,144 INFO L276 IsEmpty]: Start isEmpty. Operand 8330 states and 27401 transitions. [2019-12-07 12:40:55,152 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-12-07 12:40:55,152 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:55,152 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:55,152 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:55,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:55,152 INFO L82 PathProgramCache]: Analyzing trace with hash 2070982184, now seen corresponding path program 2 times [2019-12-07 12:40:55,152 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:55,153 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175904844] [2019-12-07 12:40:55,153 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:55,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:40:55,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:40:55,186 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1175904844] [2019-12-07 12:40:55,186 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:40:55,186 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:40:55,186 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1517834810] [2019-12-07 12:40:55,186 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:40:55,186 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:40:55,187 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:40:55,187 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:40:55,187 INFO L87 Difference]: Start difference. First operand 8330 states and 27401 transitions. Second operand 3 states. [2019-12-07 12:40:55,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:55,214 INFO L93 Difference]: Finished difference Result 7986 states and 25860 transitions. [2019-12-07 12:40:55,215 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:40:55,215 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 69 [2019-12-07 12:40:55,215 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:55,225 INFO L225 Difference]: With dead ends: 7986 [2019-12-07 12:40:55,225 INFO L226 Difference]: Without dead ends: 7986 [2019-12-07 12:40:55,225 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:40:55,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7986 states. [2019-12-07 12:40:55,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7986 to 7986. [2019-12-07 12:40:55,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7986 states. [2019-12-07 12:40:55,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7986 states to 7986 states and 25860 transitions. [2019-12-07 12:40:55,387 INFO L78 Accepts]: Start accepts. Automaton has 7986 states and 25860 transitions. Word has length 69 [2019-12-07 12:40:55,387 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:55,387 INFO L462 AbstractCegarLoop]: Abstraction has 7986 states and 25860 transitions. [2019-12-07 12:40:55,387 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:40:55,387 INFO L276 IsEmpty]: Start isEmpty. Operand 7986 states and 25860 transitions. [2019-12-07 12:40:55,395 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 12:40:55,395 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:55,395 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:55,395 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:55,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:55,396 INFO L82 PathProgramCache]: Analyzing trace with hash -1196877625, now seen corresponding path program 1 times [2019-12-07 12:40:55,396 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:55,396 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432167747] [2019-12-07 12:40:55,396 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:55,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:40:55,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:40:55,467 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [432167747] [2019-12-07 12:40:55,467 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:40:55,467 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:40:55,467 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [711265203] [2019-12-07 12:40:55,467 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 12:40:55,467 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:40:55,468 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 12:40:55,468 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 12:40:55,468 INFO L87 Difference]: Start difference. First operand 7986 states and 25860 transitions. Second operand 6 states. [2019-12-07 12:40:55,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:40:55,540 INFO L93 Difference]: Finished difference Result 11350 states and 35165 transitions. [2019-12-07 12:40:55,540 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 12:40:55,540 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 70 [2019-12-07 12:40:55,540 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:40:55,543 INFO L225 Difference]: With dead ends: 11350 [2019-12-07 12:40:55,543 INFO L226 Difference]: Without dead ends: 3914 [2019-12-07 12:40:55,543 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 12:40:55,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3914 states. [2019-12-07 12:40:55,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3914 to 3914. [2019-12-07 12:40:55,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3914 states. [2019-12-07 12:40:55,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3914 states to 3914 states and 10838 transitions. [2019-12-07 12:40:55,585 INFO L78 Accepts]: Start accepts. Automaton has 3914 states and 10838 transitions. Word has length 70 [2019-12-07 12:40:55,585 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:40:55,585 INFO L462 AbstractCegarLoop]: Abstraction has 3914 states and 10838 transitions. [2019-12-07 12:40:55,585 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 12:40:55,585 INFO L276 IsEmpty]: Start isEmpty. Operand 3914 states and 10838 transitions. [2019-12-07 12:40:55,587 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 12:40:55,588 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:40:55,588 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:40:55,588 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:40:55,588 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:40:55,588 INFO L82 PathProgramCache]: Analyzing trace with hash -1078025367, now seen corresponding path program 2 times [2019-12-07 12:40:55,588 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:40:55,588 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948328231] [2019-12-07 12:40:55,588 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:40:55,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:40:55,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:40:55,662 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:40:55,662 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 12:40:55,664 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [876] [876] ULTIMATE.startENTRY-->L833: Formula: (let ((.cse0 (store |v_#valid_73| 0 0))) (and (= v_~x~0_55 0) (= |v_ULTIMATE.start_main_~#t773~0.offset_18| 0) (= v_~a~0_26 0) (= 0 v_~y$read_delayed_var~0.offset_7) (= v_~y$r_buff1_thd0~0_273 0) (= v_~y$r_buff0_thd1~0_30 0) (= v_~y$r_buff0_thd4~0_83 0) (= v_~main$tmp_guard0~0_39 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t773~0.base_24|)) (= (store .cse0 |v_ULTIMATE.start_main_~#t773~0.base_24| 1) |v_#valid_71|) (= 0 v_~y$r_buff1_thd1~0_94) (= 0 v_~y$r_buff0_thd3~0_170) (< |v_#StackHeapBarrier_20| |v_ULTIMATE.start_main_~#t773~0.base_24|) (= v_~y~0_170 0) (= 0 v_~__unbuffered_p3_EBX~0_25) (= v_~y$read_delayed~0_6 0) (= v_~y$r_buff0_thd0~0_357 0) (= v_~y$mem_tmp~0_18 0) (= 0 v_~y$flush_delayed~0_35) (= 0 v_~__unbuffered_p3_EAX~0_21) (= v_~__unbuffered_cnt~0_136 0) (= v_~y$w_buff1_used~0_387 0) (= 0 v_~y$r_buff1_thd2~0_158) (= 0 |v_#NULL.base_4|) (= v_~y$w_buff1~0_158 0) (= 0 v_~y$read_delayed_var~0.base_7) (< 0 |v_#StackHeapBarrier_20|) (= v_~y$r_buff0_thd2~0_97 0) (= (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t773~0.base_24| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t773~0.base_24|) |v_ULTIMATE.start_main_~#t773~0.offset_18| 0)) |v_#memory_int_27|) (= v_~z~0_109 0) (= 0 v_~__unbuffered_p0_EAX~0_27) (= 0 v_~y$w_buff0~0_171) (= 0 v_~y$r_buff1_thd4~0_149) (= |v_#NULL.offset_4| 0) (= v_~main$tmp_guard1~0_24 0) (= 0 v_~weak$$choice0~0_13) (= 0 v_~y$r_buff1_thd3~0_146) (= |v_#length_31| (store |v_#length_32| |v_ULTIMATE.start_main_~#t773~0.base_24| 4)) (= v_~weak$$choice2~0_110 0) (= v_~y$w_buff0_used~0_739 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_20|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_28|, #length=|v_#length_32|} OutVars{ULTIMATE.start_main_#t~nondet32=|v_ULTIMATE.start_main_#t~nondet32_21|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_33|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_30|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_28|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_33|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_284|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_37|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_41|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~a~0=v_~a~0_26, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_29|, ~y$mem_tmp~0=v_~y$mem_tmp~0_18, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_27, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_146, ULTIMATE.start_main_~#t775~0.base=|v_ULTIMATE.start_main_~#t775~0.base_20|, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_30, ~y$flush_delayed~0=v_~y$flush_delayed~0_35, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_21, #length=|v_#length_31|, ULTIMATE.start_main_~#t774~0.offset=|v_ULTIMATE.start_main_~#t774~0.offset_18|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_54|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_28|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_25|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_55|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_20|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_46|, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_149, ~y$w_buff1~0=v_~y$w_buff1~0_158, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_97, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_136, ULTIMATE.start_main_~#t776~0.offset=|v_ULTIMATE.start_main_~#t776~0.offset_16|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_273, ~x~0=v_~x~0_55, ULTIMATE.start_main_~#t776~0.base=|v_ULTIMATE.start_main_~#t776~0.base_20|, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_739, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_27|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_29|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_40|, ULTIMATE.start_main_~#t775~0.offset=|v_ULTIMATE.start_main_~#t775~0.offset_17|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_24, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_25|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_36|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_158|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_39|, ULTIMATE.start_main_~#t774~0.base=|v_ULTIMATE.start_main_~#t774~0.base_23|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_94, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_33|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_51|, ~y$w_buff0~0=v_~y$w_buff0~0_171, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_170, ~y~0=v_~y~0_170, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_9|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_9|, ULTIMATE.start_main_~#t773~0.base=|v_ULTIMATE.start_main_~#t773~0.base_24|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_46|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_52|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_39, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_25, ULTIMATE.start_main_~#t773~0.offset=|v_ULTIMATE.start_main_~#t773~0.offset_18|, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_32|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_103|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_158, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_83, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_154|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_357, #valid=|v_#valid_71|, #memory_int=|v_#memory_int_27|, ~z~0=v_~z~0_109, ~weak$$choice2~0=v_~weak$$choice2~0_110, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_387} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet32, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ~y$read_delayed~0, ~a~0, ULTIMATE.start_main_#t~ite52, ~y$mem_tmp~0, ~__unbuffered_p0_EAX~0, ~y$r_buff1_thd3~0, ULTIMATE.start_main_~#t775~0.base, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ~__unbuffered_p3_EAX~0, #length, ULTIMATE.start_main_~#t774~0.offset, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$r_buff1_thd4~0, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ~__unbuffered_cnt~0, ULTIMATE.start_main_~#t776~0.offset, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_~#t776~0.base, ULTIMATE.start_main_#t~nondet31, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_~#t775~0.offset, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t774~0.base, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite51, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_~#t773~0.base, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~__unbuffered_p3_EBX~0, ULTIMATE.start_main_~#t773~0.offset, ULTIMATE.start_main_#t~ite53, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ~y$r_buff0_thd4~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 12:40:55,664 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L833-1-->L835: Formula: (and (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t774~0.base_10| 4)) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t774~0.base_10|) (= |v_#valid_42| (store |v_#valid_43| |v_ULTIMATE.start_main_~#t774~0.base_10| 1)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t774~0.base_10| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t774~0.base_10|) |v_ULTIMATE.start_main_~#t774~0.offset_9| 1)) |v_#memory_int_15|) (not (= |v_ULTIMATE.start_main_~#t774~0.base_10| 0)) (= |v_ULTIMATE.start_main_~#t774~0.offset_9| 0) (= (select |v_#valid_43| |v_ULTIMATE.start_main_~#t774~0.base_10|) 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_43|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, #valid=|v_#valid_42|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_~#t774~0.offset=|v_ULTIMATE.start_main_~#t774~0.offset_9|, #length=|v_#length_19|, ULTIMATE.start_main_~#t774~0.base=|v_ULTIMATE.start_main_~#t774~0.base_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, #valid, #memory_int, ULTIMATE.start_main_~#t774~0.offset, #length, ULTIMATE.start_main_~#t774~0.base] because there is no mapped edge [2019-12-07 12:40:55,665 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [835] [835] L835-1-->L837: Formula: (and (= (store |v_#length_18| |v_ULTIMATE.start_main_~#t775~0.base_11| 4) |v_#length_17|) (= (store |v_#valid_39| |v_ULTIMATE.start_main_~#t775~0.base_11| 1) |v_#valid_38|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t775~0.base_11|) (not (= 0 |v_ULTIMATE.start_main_~#t775~0.base_11|)) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t775~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t775~0.base_11|) |v_ULTIMATE.start_main_~#t775~0.offset_10| 2))) (= (select |v_#valid_39| |v_ULTIMATE.start_main_~#t775~0.base_11|) 0) (= |v_ULTIMATE.start_main_~#t775~0.offset_10| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, ULTIMATE.start_main_~#t775~0.base=|v_ULTIMATE.start_main_~#t775~0.base_11|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t775~0.offset=|v_ULTIMATE.start_main_~#t775~0.offset_10|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_~#t775~0.base, #valid, #memory_int, ULTIMATE.start_main_~#t775~0.offset, #length] because there is no mapped edge [2019-12-07 12:40:55,665 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] P2ENTRY-->L4-3: Formula: (and (= (ite (not (and (not (= 0 (mod v_~y$w_buff1_used~0_105 256))) (not (= 0 (mod v_~y$w_buff0_used~0_178 256))))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~y$w_buff0~0_34 v_~y$w_buff1~0_39) (= |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8)) (= 2 v_~y$w_buff0~0_33) (= v_P2Thread1of1ForFork0_~arg.base_6 |v_P2Thread1of1ForFork0_#in~arg.base_8|) (= v_~y$w_buff0_used~0_179 v_~y$w_buff1_used~0_105) (= v_~y$w_buff0_used~0_178 1) (= v_P2Thread1of1ForFork0_~arg.offset_6 |v_P2Thread1of1ForFork0_#in~arg.offset_8|)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_179, ~y$w_buff0~0=v_~y$w_buff0~0_34, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_6, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_178, ~y$w_buff1~0=v_~y$w_buff1~0_39, ~y$w_buff0~0=v_~y$w_buff0~0_33, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_6, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_105} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 12:40:55,665 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L837-1-->L839: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t776~0.base_11|)) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t776~0.base_11| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t776~0.base_11|) |v_ULTIMATE.start_main_~#t776~0.offset_9| 3)) |v_#memory_int_17|) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t776~0.base_11|) (= |v_#valid_44| (store |v_#valid_45| |v_ULTIMATE.start_main_~#t776~0.base_11| 1)) (= 0 (select |v_#valid_45| |v_ULTIMATE.start_main_~#t776~0.base_11|)) (= |v_ULTIMATE.start_main_~#t776~0.offset_9| 0) (= (store |v_#length_22| |v_ULTIMATE.start_main_~#t776~0.base_11| 4) |v_#length_21|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_4|, #valid=|v_#valid_44|, #memory_int=|v_#memory_int_17|, #length=|v_#length_21|, ULTIMATE.start_main_~#t776~0.offset=|v_ULTIMATE.start_main_~#t776~0.offset_9|, ULTIMATE.start_main_~#t776~0.base=|v_ULTIMATE.start_main_~#t776~0.base_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, #valid, #memory_int, #length, ULTIMATE.start_main_~#t776~0.offset, ULTIMATE.start_main_~#t776~0.base] because there is no mapped edge [2019-12-07 12:40:55,666 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] P0ENTRY-->P0EXIT: Formula: (and (= v_P0Thread1of1ForFork2_~arg.base_6 |v_P0Thread1of1ForFork2_#in~arg.base_8|) (= v_~a~0_12 1) (= (+ v_~__unbuffered_cnt~0_48 1) v_~__unbuffered_cnt~0_47) (= |v_P0Thread1of1ForFork2_#res.offset_3| 0) (= v_P0Thread1of1ForFork2_~arg.offset_6 |v_P0Thread1of1ForFork2_#in~arg.offset_8|) (= v_~x~0_36 v_~__unbuffered_p0_EAX~0_17) (= 0 |v_P0Thread1of1ForFork2_#res.base_3|)) InVars {P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_48, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_8|, ~x~0=v_~x~0_36} OutVars{~a~0=v_~a~0_12, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_17, P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_8|, P0Thread1of1ForFork2_~arg.offset=v_P0Thread1of1ForFork2_~arg.offset_6, P0Thread1of1ForFork2_#res.offset=|v_P0Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_47, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_8|, P0Thread1of1ForFork2_#res.base=|v_P0Thread1of1ForFork2_#res.base_3|, ~x~0=v_~x~0_36, P0Thread1of1ForFork2_~arg.base=v_P0Thread1of1ForFork2_~arg.base_6} AuxVars[] AssignedVars[~a~0, ~__unbuffered_p0_EAX~0, P0Thread1of1ForFork2_~arg.offset, P0Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0, P0Thread1of1ForFork2_#res.base, P0Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-12-07 12:40:55,667 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L757-2-->L757-5: Formula: (let ((.cse2 (= |P1Thread1of1ForFork3_#t~ite4_Out-2091624068| |P1Thread1of1ForFork3_#t~ite3_Out-2091624068|)) (.cse1 (= (mod ~y$w_buff1_used~0_In-2091624068 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd2~0_In-2091624068 256) 0))) (or (and (or .cse0 .cse1) .cse2 (= |P1Thread1of1ForFork3_#t~ite3_Out-2091624068| ~y~0_In-2091624068)) (and .cse2 (not .cse1) (not .cse0) (= |P1Thread1of1ForFork3_#t~ite3_Out-2091624068| ~y$w_buff1~0_In-2091624068)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2091624068, ~y$w_buff1~0=~y$w_buff1~0_In-2091624068, ~y~0=~y~0_In-2091624068, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2091624068} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2091624068, ~y$w_buff1~0=~y$w_buff1~0_In-2091624068, P1Thread1of1ForFork3_#t~ite4=|P1Thread1of1ForFork3_#t~ite4_Out-2091624068|, P1Thread1of1ForFork3_#t~ite3=|P1Thread1of1ForFork3_#t~ite3_Out-2091624068|, ~y~0=~y~0_In-2091624068, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2091624068} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite4, P1Thread1of1ForFork3_#t~ite3] because there is no mapped edge [2019-12-07 12:40:55,667 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L758-->L758-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd2~0_In1092105639 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In1092105639 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork3_#t~ite5_Out1092105639|)) (and (= ~y$w_buff0_used~0_In1092105639 |P1Thread1of1ForFork3_#t~ite5_Out1092105639|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1092105639, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1092105639} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1092105639, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1092105639, P1Thread1of1ForFork3_#t~ite5=|P1Thread1of1ForFork3_#t~ite5_Out1092105639|} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite5] because there is no mapped edge [2019-12-07 12:40:55,667 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [807] [807] L810-2-->L810-4: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In1209029031 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd4~0_In1209029031 256)))) (or (and (= |P3Thread1of1ForFork1_#t~ite15_Out1209029031| ~y$w_buff1~0_In1209029031) (not .cse0) (not .cse1)) (and (= |P3Thread1of1ForFork1_#t~ite15_Out1209029031| ~y~0_In1209029031) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1209029031, ~y$w_buff1~0=~y$w_buff1~0_In1209029031, ~y~0=~y~0_In1209029031, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1209029031} OutVars{~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1209029031, ~y$w_buff1~0=~y$w_buff1~0_In1209029031, P3Thread1of1ForFork1_#t~ite15=|P3Thread1of1ForFork1_#t~ite15_Out1209029031|, ~y~0=~y~0_In1209029031, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1209029031} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite15] because there is no mapped edge [2019-12-07 12:40:55,668 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [794] [794] L759-->L759-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In656216847 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In656216847 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In656216847 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd2~0_In656216847 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork3_#t~ite6_Out656216847| 0)) (and (or .cse1 .cse0) (or .cse3 .cse2) (= |P1Thread1of1ForFork3_#t~ite6_Out656216847| ~y$w_buff1_used~0_In656216847)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In656216847, ~y$w_buff0_used~0=~y$w_buff0_used~0_In656216847, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In656216847, ~y$w_buff1_used~0=~y$w_buff1_used~0_In656216847} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In656216847, ~y$w_buff0_used~0=~y$w_buff0_used~0_In656216847, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In656216847, P1Thread1of1ForFork3_#t~ite6=|P1Thread1of1ForFork3_#t~ite6_Out656216847|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In656216847} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite6] because there is no mapped edge [2019-12-07 12:40:55,668 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [731] [731] L810-4-->L811: Formula: (= v_~y~0_28 |v_P3Thread1of1ForFork1_#t~ite15_8|) InVars {P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_8|} OutVars{P3Thread1of1ForFork1_#t~ite16=|v_P3Thread1of1ForFork1_#t~ite16_13|, P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_7|, ~y~0=v_~y~0_28} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite16, P3Thread1of1ForFork1_#t~ite15, ~y~0] because there is no mapped edge [2019-12-07 12:40:55,668 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L811-->L811-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1113608328 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd4~0_In-1113608328 256)))) (or (and (not .cse0) (= 0 |P3Thread1of1ForFork1_#t~ite17_Out-1113608328|) (not .cse1)) (and (= ~y$w_buff0_used~0_In-1113608328 |P3Thread1of1ForFork1_#t~ite17_Out-1113608328|) (or .cse1 .cse0)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1113608328, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1113608328} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1113608328, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1113608328, P3Thread1of1ForFork1_#t~ite17=|P3Thread1of1ForFork1_#t~ite17_Out-1113608328|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite17] because there is no mapped edge [2019-12-07 12:40:55,668 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L812-->L812-2: Formula: (let ((.cse0 (= (mod ~y$r_buff1_thd4~0_In1765617603 256) 0)) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In1765617603 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In1765617603 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd4~0_In1765617603 256) 0))) (or (and (= 0 |P3Thread1of1ForFork1_#t~ite18_Out1765617603|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse3 .cse2) (= ~y$w_buff1_used~0_In1765617603 |P3Thread1of1ForFork1_#t~ite18_Out1765617603|)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1765617603, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1765617603, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1765617603, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1765617603} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1765617603, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1765617603, P3Thread1of1ForFork1_#t~ite18=|P3Thread1of1ForFork1_#t~ite18_Out1765617603|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1765617603, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1765617603} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite18] because there is no mapped edge [2019-12-07 12:40:55,669 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L813-->L813-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-744130934 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd4~0_In-744130934 256) 0))) (or (and (not .cse0) (= |P3Thread1of1ForFork1_#t~ite19_Out-744130934| 0) (not .cse1)) (and (or .cse0 .cse1) (= |P3Thread1of1ForFork1_#t~ite19_Out-744130934| ~y$r_buff0_thd4~0_In-744130934)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-744130934, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-744130934} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-744130934, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-744130934, P3Thread1of1ForFork1_#t~ite19=|P3Thread1of1ForFork1_#t~ite19_Out-744130934|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite19] because there is no mapped edge [2019-12-07 12:40:55,669 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L760-->L760-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In1412484338 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In1412484338 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork3_#t~ite7_Out1412484338|)) (and (= ~y$r_buff0_thd2~0_In1412484338 |P1Thread1of1ForFork3_#t~ite7_Out1412484338|) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1412484338, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1412484338} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1412484338, P1Thread1of1ForFork3_#t~ite7=|P1Thread1of1ForFork3_#t~ite7_Out1412484338|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1412484338} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite7] because there is no mapped edge [2019-12-07 12:40:55,670 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [810] [810] L761-->L761-2: Formula: (let ((.cse3 (= 0 (mod ~y$r_buff0_thd2~0_In1697616862 256))) (.cse2 (= (mod ~y$w_buff0_used~0_In1697616862 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In1697616862 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In1697616862 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~y$r_buff1_thd2~0_In1697616862 |P1Thread1of1ForFork3_#t~ite8_Out1697616862|)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= 0 |P1Thread1of1ForFork3_#t~ite8_Out1697616862|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1697616862, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1697616862, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1697616862, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1697616862} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1697616862, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1697616862, P1Thread1of1ForFork3_#t~ite8=|P1Thread1of1ForFork3_#t~ite8_Out1697616862|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1697616862, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1697616862} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite8] because there is no mapped edge [2019-12-07 12:40:55,670 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L761-2-->P1EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_41 1) v_~__unbuffered_cnt~0_40) (= 0 |v_P1Thread1of1ForFork3_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork3_#res.base_3|) (= |v_P1Thread1of1ForFork3_#t~ite8_24| v_~y$r_buff1_thd2~0_111)) InVars {P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_41} OutVars{P1Thread1of1ForFork3_#res.base=|v_P1Thread1of1ForFork3_#res.base_3|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_111, P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_23|, P1Thread1of1ForFork3_#res.offset=|v_P1Thread1of1ForFork3_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#res.base, ~y$r_buff1_thd2~0, P1Thread1of1ForFork3_#t~ite8, P1Thread1of1ForFork3_#res.offset, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 12:40:55,670 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L788-->L788-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd3~0_In-92950177 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-92950177 256)))) (or (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out-92950177| 0) (not .cse1)) (and (= |P2Thread1of1ForFork0_#t~ite11_Out-92950177| ~y$w_buff0_used~0_In-92950177) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-92950177, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-92950177} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-92950177, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-92950177|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-92950177} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 12:40:55,670 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [813] [813] L789-->L789-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd3~0_In832014852 256) 0)) (.cse2 (= (mod ~y$w_buff1_used~0_In832014852 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In832014852 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In832014852 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite12_Out832014852| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse1 .cse0) (= |P2Thread1of1ForFork0_#t~ite12_Out832014852| ~y$w_buff1_used~0_In832014852)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In832014852, ~y$w_buff0_used~0=~y$w_buff0_used~0_In832014852, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In832014852, ~y$w_buff1_used~0=~y$w_buff1_used~0_In832014852} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In832014852, ~y$w_buff0_used~0=~y$w_buff0_used~0_In832014852, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out832014852|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In832014852, ~y$w_buff1_used~0=~y$w_buff1_used~0_In832014852} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 12:40:55,671 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L790-->L791: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In-1829382286 256))) (.cse2 (= (mod ~y$w_buff0_used~0_In-1829382286 256) 0)) (.cse1 (= ~y$r_buff0_thd3~0_In-1829382286 ~y$r_buff0_thd3~0_Out-1829382286))) (or (and .cse0 .cse1) (and (not .cse0) (= 0 ~y$r_buff0_thd3~0_Out-1829382286) (not .cse2)) (and .cse2 .cse1))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1829382286, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1829382286} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1829382286, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-1829382286, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-1829382286|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 12:40:55,671 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L791-->L791-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In75093928 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd3~0_In75093928 256))) (.cse2 (= (mod ~y$w_buff0_used~0_In75093928 256) 0)) (.cse3 (= (mod ~y$r_buff0_thd3~0_In75093928 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite14_Out75093928| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite14_Out75093928| ~y$r_buff1_thd3~0_In75093928) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In75093928, ~y$w_buff0_used~0=~y$w_buff0_used~0_In75093928, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In75093928, ~y$w_buff1_used~0=~y$w_buff1_used~0_In75093928} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out75093928|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In75093928, ~y$w_buff0_used~0=~y$w_buff0_used~0_In75093928, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In75093928, ~y$w_buff1_used~0=~y$w_buff1_used~0_In75093928} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 12:40:55,671 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [847] [847] L791-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= v_~__unbuffered_cnt~0_59 (+ v_~__unbuffered_cnt~0_60 1)) (= v_~y$r_buff1_thd3~0_114 |v_P2Thread1of1ForFork0_#t~ite14_20|) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_20|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_60} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_19|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_114, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_59, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 12:40:55,671 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [792] [792] L814-->L814-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd4~0_In-779818325 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-779818325 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In-779818325 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd4~0_In-779818325 256)))) (or (and (= |P3Thread1of1ForFork1_#t~ite20_Out-779818325| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P3Thread1of1ForFork1_#t~ite20_Out-779818325| ~y$r_buff1_thd4~0_In-779818325) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-779818325, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-779818325, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-779818325, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-779818325} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-779818325, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-779818325, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-779818325, P3Thread1of1ForFork1_#t~ite20=|P3Thread1of1ForFork1_#t~ite20_Out-779818325|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-779818325} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 12:40:55,671 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [846] [846] L814-2-->P3EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_54 1) v_~__unbuffered_cnt~0_53) (= |v_P3Thread1of1ForFork1_#t~ite20_28| v_~y$r_buff1_thd4~0_111) (= |v_P3Thread1of1ForFork1_#res.offset_3| 0) (= |v_P3Thread1of1ForFork1_#res.base_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_28|} OutVars{~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_111, P3Thread1of1ForFork1_#res.base=|v_P3Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_53, P3Thread1of1ForFork1_#res.offset=|v_P3Thread1of1ForFork1_#res.offset_3|, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_27|} AuxVars[] AssignedVars[~y$r_buff1_thd4~0, P3Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork1_#res.offset, P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 12:40:55,672 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L843-->L845-2: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (or (= (mod v_~y$w_buff0_used~0_216 256) 0) (= 0 (mod v_~y$r_buff0_thd0~0_104 256)))) InVars {~y$w_buff0_used~0=v_~y$w_buff0_used~0_216, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} OutVars{~y$w_buff0_used~0=v_~y$w_buff0_used~0_216, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 12:40:55,672 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L845-2-->L845-5: Formula: (let ((.cse1 (= (mod ~y$r_buff1_thd0~0_In-2107457801 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In-2107457801 256) 0)) (.cse2 (= |ULTIMATE.start_main_#t~ite25_Out-2107457801| |ULTIMATE.start_main_#t~ite26_Out-2107457801|))) (or (and (= |ULTIMATE.start_main_#t~ite25_Out-2107457801| ~y~0_In-2107457801) (or .cse0 .cse1) .cse2) (and (= |ULTIMATE.start_main_#t~ite25_Out-2107457801| ~y$w_buff1~0_In-2107457801) (not .cse1) (not .cse0) .cse2))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-2107457801, ~y~0=~y~0_In-2107457801, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-2107457801, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2107457801} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-2107457801, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-2107457801|, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-2107457801|, ~y~0=~y~0_In-2107457801, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-2107457801, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2107457801} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 12:40:55,672 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [797] [797] L846-->L846-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In556539303 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In556539303 256)))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite27_Out556539303| 0)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite27_Out556539303| ~y$w_buff0_used~0_In556539303)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In556539303, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In556539303} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In556539303, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In556539303, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out556539303|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 12:40:55,673 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L847-->L847-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff1_used~0_In530121068 256))) (.cse2 (= (mod ~y$r_buff1_thd0~0_In530121068 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In530121068 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In530121068 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite28_Out530121068| 0)) (and (= |ULTIMATE.start_main_#t~ite28_Out530121068| ~y$w_buff1_used~0_In530121068) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In530121068, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In530121068, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In530121068, ~y$w_buff1_used~0=~y$w_buff1_used~0_In530121068} OutVars{ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out530121068|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In530121068, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In530121068, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In530121068, ~y$w_buff1_used~0=~y$w_buff1_used~0_In530121068} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 12:40:55,673 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [812] [812] L848-->L848-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-219992588 256))) (.cse0 (= (mod ~y$r_buff0_thd0~0_In-219992588 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite29_Out-219992588| ~y$r_buff0_thd0~0_In-219992588)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite29_Out-219992588| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-219992588, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-219992588} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-219992588, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-219992588|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-219992588} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 12:40:55,673 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [790] [790] L849-->L849-2: Formula: (let ((.cse2 (= (mod ~y$r_buff0_thd0~0_In-1833700979 256) 0)) (.cse3 (= (mod ~y$w_buff0_used~0_In-1833700979 256) 0)) (.cse1 (= (mod ~y$w_buff1_used~0_In-1833700979 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-1833700979 256)))) (or (and (= ~y$r_buff1_thd0~0_In-1833700979 |ULTIMATE.start_main_#t~ite30_Out-1833700979|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |ULTIMATE.start_main_#t~ite30_Out-1833700979|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1833700979, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1833700979, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1833700979, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1833700979} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out-1833700979|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1833700979, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1833700979, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1833700979, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1833700979} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30] because there is no mapped edge [2019-12-07 12:40:55,675 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [852] [852] L858-->L858-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In319421602 256)))) (or (and (= |ULTIMATE.start_main_#t~ite39_Out319421602| |ULTIMATE.start_main_#t~ite40_Out319421602|) (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In319421602 256)))) (or (= (mod ~y$w_buff0_used~0_In319421602 256) 0) (and (= 0 (mod ~y$w_buff1_used~0_In319421602 256)) .cse0) (and (= 0 (mod ~y$r_buff1_thd0~0_In319421602 256)) .cse0))) (= |ULTIMATE.start_main_#t~ite39_Out319421602| ~y$w_buff1~0_In319421602) .cse1) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite40_Out319421602| ~y$w_buff1~0_In319421602) (= |ULTIMATE.start_main_#t~ite39_In319421602| |ULTIMATE.start_main_#t~ite39_Out319421602|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In319421602, ~y$w_buff0_used~0=~y$w_buff0_used~0_In319421602, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_In319421602|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In319421602, ~weak$$choice2~0=~weak$$choice2~0_In319421602, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In319421602, ~y$w_buff1_used~0=~y$w_buff1_used~0_In319421602} OutVars{ULTIMATE.start_main_#t~ite40=|ULTIMATE.start_main_#t~ite40_Out319421602|, ~y$w_buff1~0=~y$w_buff1~0_In319421602, ~y$w_buff0_used~0=~y$w_buff0_used~0_In319421602, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out319421602|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In319421602, ~weak$$choice2~0=~weak$$choice2~0_In319421602, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In319421602, ~y$w_buff1_used~0=~y$w_buff1_used~0_In319421602} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 12:40:55,675 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L859-->L859-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-981678590 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite42_In-981678590| |ULTIMATE.start_main_#t~ite42_Out-981678590|) (not .cse0) (= |ULTIMATE.start_main_#t~ite43_Out-981678590| ~y$w_buff0_used~0_In-981678590)) (and (= ~y$w_buff0_used~0_In-981678590 |ULTIMATE.start_main_#t~ite42_Out-981678590|) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-981678590 256)))) (or (and .cse1 (= (mod ~y$w_buff1_used~0_In-981678590 256) 0)) (= 0 (mod ~y$w_buff0_used~0_In-981678590 256)) (and (= 0 (mod ~y$r_buff1_thd0~0_In-981678590 256)) .cse1))) .cse0 (= |ULTIMATE.start_main_#t~ite43_Out-981678590| |ULTIMATE.start_main_#t~ite42_Out-981678590|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-981678590, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-981678590, ~weak$$choice2~0=~weak$$choice2~0_In-981678590, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-981678590, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_In-981678590|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-981678590} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-981678590, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-981678590, ULTIMATE.start_main_#t~ite43=|ULTIMATE.start_main_#t~ite43_Out-981678590|, ~weak$$choice2~0=~weak$$choice2~0_In-981678590, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_Out-981678590|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-981678590, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-981678590} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 12:40:55,676 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [865] [865] L860-->L860-8: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite45_Out2011853808| |ULTIMATE.start_main_#t~ite46_Out2011853808|)) (.cse1 (= (mod ~weak$$choice2~0_In2011853808 256) 0)) (.cse3 (= (mod ~y$r_buff1_thd0~0_In2011853808 256) 0)) (.cse4 (= (mod ~y$w_buff0_used~0_In2011853808 256) 0)) (.cse6 (= (mod ~y$r_buff0_thd0~0_In2011853808 256) 0)) (.cse5 (= (mod ~y$w_buff1_used~0_In2011853808 256) 0))) (or (let ((.cse2 (not .cse6))) (and .cse0 .cse1 (or .cse2 (not .cse3)) (= |ULTIMATE.start_main_#t~ite44_Out2011853808| |ULTIMATE.start_main_#t~ite45_Out2011853808|) (not .cse4) (or .cse2 (not .cse5)) (= |ULTIMATE.start_main_#t~ite44_Out2011853808| 0))) (and (= |ULTIMATE.start_main_#t~ite44_In2011853808| |ULTIMATE.start_main_#t~ite44_Out2011853808|) (or (and (not .cse1) (= |ULTIMATE.start_main_#t~ite45_In2011853808| |ULTIMATE.start_main_#t~ite45_Out2011853808|) (= ~y$w_buff1_used~0_In2011853808 |ULTIMATE.start_main_#t~ite46_Out2011853808|)) (and .cse0 .cse1 (= ~y$w_buff1_used~0_In2011853808 |ULTIMATE.start_main_#t~ite45_Out2011853808|) (or (and .cse3 .cse6) .cse4 (and .cse6 .cse5))))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In2011853808, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In2011853808, ~weak$$choice2~0=~weak$$choice2~0_In2011853808, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In2011853808, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In2011853808|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2011853808, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_In2011853808|} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In2011853808, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In2011853808, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out2011853808|, ~weak$$choice2~0=~weak$$choice2~0_In2011853808, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In2011853808, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out2011853808|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2011853808, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_Out2011853808|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-12-07 12:40:55,676 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [868] [868] L860-8-->L862: Formula: (and (not (= (mod v_~weak$$choice2~0_106 256) 0)) (= v_~y$w_buff1_used~0_383 |v_ULTIMATE.start_main_#t~ite46_36|) (= v_~y$r_buff0_thd0~0_352 v_~y$r_buff0_thd0~0_351)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_352, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~weak$$choice2~0=v_~weak$$choice2~0_106} OutVars{~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_351, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_35|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_31|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_34|, ~weak$$choice2~0=v_~weak$$choice2~0_106, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_33|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_383} AuxVars[] AssignedVars[~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 12:40:55,676 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L864-->L4: Formula: (and (= 0 v_~y$flush_delayed~0_25) (= v_~y~0_116 v_~y$mem_tmp~0_11) (not (= (mod v_~y$flush_delayed~0_26 256) 0)) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5| (mod v_~main$tmp_guard1~0_15 256))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_26, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_11, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ~y$flush_delayed~0=v_~y$flush_delayed~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15, ~y~0=v_~y~0_116, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_23|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ~y~0, ULTIMATE.start_main_#t~ite53, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 12:40:55,676 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 12:40:55,734 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 12:40:55 BasicIcfg [2019-12-07 12:40:55,734 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 12:40:55,734 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 12:40:55,734 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 12:40:55,734 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 12:40:55,735 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:37:57" (3/4) ... [2019-12-07 12:40:55,736 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 12:40:55,736 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [876] [876] ULTIMATE.startENTRY-->L833: Formula: (let ((.cse0 (store |v_#valid_73| 0 0))) (and (= v_~x~0_55 0) (= |v_ULTIMATE.start_main_~#t773~0.offset_18| 0) (= v_~a~0_26 0) (= 0 v_~y$read_delayed_var~0.offset_7) (= v_~y$r_buff1_thd0~0_273 0) (= v_~y$r_buff0_thd1~0_30 0) (= v_~y$r_buff0_thd4~0_83 0) (= v_~main$tmp_guard0~0_39 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t773~0.base_24|)) (= (store .cse0 |v_ULTIMATE.start_main_~#t773~0.base_24| 1) |v_#valid_71|) (= 0 v_~y$r_buff1_thd1~0_94) (= 0 v_~y$r_buff0_thd3~0_170) (< |v_#StackHeapBarrier_20| |v_ULTIMATE.start_main_~#t773~0.base_24|) (= v_~y~0_170 0) (= 0 v_~__unbuffered_p3_EBX~0_25) (= v_~y$read_delayed~0_6 0) (= v_~y$r_buff0_thd0~0_357 0) (= v_~y$mem_tmp~0_18 0) (= 0 v_~y$flush_delayed~0_35) (= 0 v_~__unbuffered_p3_EAX~0_21) (= v_~__unbuffered_cnt~0_136 0) (= v_~y$w_buff1_used~0_387 0) (= 0 v_~y$r_buff1_thd2~0_158) (= 0 |v_#NULL.base_4|) (= v_~y$w_buff1~0_158 0) (= 0 v_~y$read_delayed_var~0.base_7) (< 0 |v_#StackHeapBarrier_20|) (= v_~y$r_buff0_thd2~0_97 0) (= (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t773~0.base_24| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t773~0.base_24|) |v_ULTIMATE.start_main_~#t773~0.offset_18| 0)) |v_#memory_int_27|) (= v_~z~0_109 0) (= 0 v_~__unbuffered_p0_EAX~0_27) (= 0 v_~y$w_buff0~0_171) (= 0 v_~y$r_buff1_thd4~0_149) (= |v_#NULL.offset_4| 0) (= v_~main$tmp_guard1~0_24 0) (= 0 v_~weak$$choice0~0_13) (= 0 v_~y$r_buff1_thd3~0_146) (= |v_#length_31| (store |v_#length_32| |v_ULTIMATE.start_main_~#t773~0.base_24| 4)) (= v_~weak$$choice2~0_110 0) (= v_~y$w_buff0_used~0_739 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_20|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_28|, #length=|v_#length_32|} OutVars{ULTIMATE.start_main_#t~nondet32=|v_ULTIMATE.start_main_#t~nondet32_21|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_33|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_30|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_28|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_33|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_284|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_37|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_41|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~a~0=v_~a~0_26, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_29|, ~y$mem_tmp~0=v_~y$mem_tmp~0_18, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_27, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_146, ULTIMATE.start_main_~#t775~0.base=|v_ULTIMATE.start_main_~#t775~0.base_20|, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_30, ~y$flush_delayed~0=v_~y$flush_delayed~0_35, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_21, #length=|v_#length_31|, ULTIMATE.start_main_~#t774~0.offset=|v_ULTIMATE.start_main_~#t774~0.offset_18|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_54|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_28|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_25|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_55|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_20|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_46|, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_149, ~y$w_buff1~0=v_~y$w_buff1~0_158, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_97, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_136, ULTIMATE.start_main_~#t776~0.offset=|v_ULTIMATE.start_main_~#t776~0.offset_16|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_273, ~x~0=v_~x~0_55, ULTIMATE.start_main_~#t776~0.base=|v_ULTIMATE.start_main_~#t776~0.base_20|, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_739, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_27|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_29|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_40|, ULTIMATE.start_main_~#t775~0.offset=|v_ULTIMATE.start_main_~#t775~0.offset_17|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_24, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_25|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_36|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_158|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_39|, ULTIMATE.start_main_~#t774~0.base=|v_ULTIMATE.start_main_~#t774~0.base_23|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_94, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_33|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_51|, ~y$w_buff0~0=v_~y$w_buff0~0_171, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_170, ~y~0=v_~y~0_170, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_9|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_9|, ULTIMATE.start_main_~#t773~0.base=|v_ULTIMATE.start_main_~#t773~0.base_24|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_46|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_52|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_39, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_25, ULTIMATE.start_main_~#t773~0.offset=|v_ULTIMATE.start_main_~#t773~0.offset_18|, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_32|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_103|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_158, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_83, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_154|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_357, #valid=|v_#valid_71|, #memory_int=|v_#memory_int_27|, ~z~0=v_~z~0_109, ~weak$$choice2~0=v_~weak$$choice2~0_110, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_387} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet32, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ~y$read_delayed~0, ~a~0, ULTIMATE.start_main_#t~ite52, ~y$mem_tmp~0, ~__unbuffered_p0_EAX~0, ~y$r_buff1_thd3~0, ULTIMATE.start_main_~#t775~0.base, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ~__unbuffered_p3_EAX~0, #length, ULTIMATE.start_main_~#t774~0.offset, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$r_buff1_thd4~0, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ~__unbuffered_cnt~0, ULTIMATE.start_main_~#t776~0.offset, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_~#t776~0.base, ULTIMATE.start_main_#t~nondet31, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_~#t775~0.offset, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t774~0.base, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite51, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_~#t773~0.base, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~__unbuffered_p3_EBX~0, ULTIMATE.start_main_~#t773~0.offset, ULTIMATE.start_main_#t~ite53, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ~y$r_buff0_thd4~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 12:40:55,737 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L833-1-->L835: Formula: (and (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t774~0.base_10| 4)) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t774~0.base_10|) (= |v_#valid_42| (store |v_#valid_43| |v_ULTIMATE.start_main_~#t774~0.base_10| 1)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t774~0.base_10| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t774~0.base_10|) |v_ULTIMATE.start_main_~#t774~0.offset_9| 1)) |v_#memory_int_15|) (not (= |v_ULTIMATE.start_main_~#t774~0.base_10| 0)) (= |v_ULTIMATE.start_main_~#t774~0.offset_9| 0) (= (select |v_#valid_43| |v_ULTIMATE.start_main_~#t774~0.base_10|) 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_43|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, #valid=|v_#valid_42|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_~#t774~0.offset=|v_ULTIMATE.start_main_~#t774~0.offset_9|, #length=|v_#length_19|, ULTIMATE.start_main_~#t774~0.base=|v_ULTIMATE.start_main_~#t774~0.base_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, #valid, #memory_int, ULTIMATE.start_main_~#t774~0.offset, #length, ULTIMATE.start_main_~#t774~0.base] because there is no mapped edge [2019-12-07 12:40:55,737 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [835] [835] L835-1-->L837: Formula: (and (= (store |v_#length_18| |v_ULTIMATE.start_main_~#t775~0.base_11| 4) |v_#length_17|) (= (store |v_#valid_39| |v_ULTIMATE.start_main_~#t775~0.base_11| 1) |v_#valid_38|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t775~0.base_11|) (not (= 0 |v_ULTIMATE.start_main_~#t775~0.base_11|)) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t775~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t775~0.base_11|) |v_ULTIMATE.start_main_~#t775~0.offset_10| 2))) (= (select |v_#valid_39| |v_ULTIMATE.start_main_~#t775~0.base_11|) 0) (= |v_ULTIMATE.start_main_~#t775~0.offset_10| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, ULTIMATE.start_main_~#t775~0.base=|v_ULTIMATE.start_main_~#t775~0.base_11|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t775~0.offset=|v_ULTIMATE.start_main_~#t775~0.offset_10|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_~#t775~0.base, #valid, #memory_int, ULTIMATE.start_main_~#t775~0.offset, #length] because there is no mapped edge [2019-12-07 12:40:55,737 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] P2ENTRY-->L4-3: Formula: (and (= (ite (not (and (not (= 0 (mod v_~y$w_buff1_used~0_105 256))) (not (= 0 (mod v_~y$w_buff0_used~0_178 256))))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~y$w_buff0~0_34 v_~y$w_buff1~0_39) (= |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8)) (= 2 v_~y$w_buff0~0_33) (= v_P2Thread1of1ForFork0_~arg.base_6 |v_P2Thread1of1ForFork0_#in~arg.base_8|) (= v_~y$w_buff0_used~0_179 v_~y$w_buff1_used~0_105) (= v_~y$w_buff0_used~0_178 1) (= v_P2Thread1of1ForFork0_~arg.offset_6 |v_P2Thread1of1ForFork0_#in~arg.offset_8|)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_179, ~y$w_buff0~0=v_~y$w_buff0~0_34, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_6, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_178, ~y$w_buff1~0=v_~y$w_buff1~0_39, ~y$w_buff0~0=v_~y$w_buff0~0_33, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_6, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_105} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 12:40:55,738 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L837-1-->L839: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t776~0.base_11|)) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t776~0.base_11| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t776~0.base_11|) |v_ULTIMATE.start_main_~#t776~0.offset_9| 3)) |v_#memory_int_17|) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t776~0.base_11|) (= |v_#valid_44| (store |v_#valid_45| |v_ULTIMATE.start_main_~#t776~0.base_11| 1)) (= 0 (select |v_#valid_45| |v_ULTIMATE.start_main_~#t776~0.base_11|)) (= |v_ULTIMATE.start_main_~#t776~0.offset_9| 0) (= (store |v_#length_22| |v_ULTIMATE.start_main_~#t776~0.base_11| 4) |v_#length_21|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_4|, #valid=|v_#valid_44|, #memory_int=|v_#memory_int_17|, #length=|v_#length_21|, ULTIMATE.start_main_~#t776~0.offset=|v_ULTIMATE.start_main_~#t776~0.offset_9|, ULTIMATE.start_main_~#t776~0.base=|v_ULTIMATE.start_main_~#t776~0.base_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, #valid, #memory_int, #length, ULTIMATE.start_main_~#t776~0.offset, ULTIMATE.start_main_~#t776~0.base] because there is no mapped edge [2019-12-07 12:40:55,738 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] P0ENTRY-->P0EXIT: Formula: (and (= v_P0Thread1of1ForFork2_~arg.base_6 |v_P0Thread1of1ForFork2_#in~arg.base_8|) (= v_~a~0_12 1) (= (+ v_~__unbuffered_cnt~0_48 1) v_~__unbuffered_cnt~0_47) (= |v_P0Thread1of1ForFork2_#res.offset_3| 0) (= v_P0Thread1of1ForFork2_~arg.offset_6 |v_P0Thread1of1ForFork2_#in~arg.offset_8|) (= v_~x~0_36 v_~__unbuffered_p0_EAX~0_17) (= 0 |v_P0Thread1of1ForFork2_#res.base_3|)) InVars {P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_48, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_8|, ~x~0=v_~x~0_36} OutVars{~a~0=v_~a~0_12, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_17, P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_8|, P0Thread1of1ForFork2_~arg.offset=v_P0Thread1of1ForFork2_~arg.offset_6, P0Thread1of1ForFork2_#res.offset=|v_P0Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_47, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_8|, P0Thread1of1ForFork2_#res.base=|v_P0Thread1of1ForFork2_#res.base_3|, ~x~0=v_~x~0_36, P0Thread1of1ForFork2_~arg.base=v_P0Thread1of1ForFork2_~arg.base_6} AuxVars[] AssignedVars[~a~0, ~__unbuffered_p0_EAX~0, P0Thread1of1ForFork2_~arg.offset, P0Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0, P0Thread1of1ForFork2_#res.base, P0Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-12-07 12:40:55,739 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L757-2-->L757-5: Formula: (let ((.cse2 (= |P1Thread1of1ForFork3_#t~ite4_Out-2091624068| |P1Thread1of1ForFork3_#t~ite3_Out-2091624068|)) (.cse1 (= (mod ~y$w_buff1_used~0_In-2091624068 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd2~0_In-2091624068 256) 0))) (or (and (or .cse0 .cse1) .cse2 (= |P1Thread1of1ForFork3_#t~ite3_Out-2091624068| ~y~0_In-2091624068)) (and .cse2 (not .cse1) (not .cse0) (= |P1Thread1of1ForFork3_#t~ite3_Out-2091624068| ~y$w_buff1~0_In-2091624068)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2091624068, ~y$w_buff1~0=~y$w_buff1~0_In-2091624068, ~y~0=~y~0_In-2091624068, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2091624068} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2091624068, ~y$w_buff1~0=~y$w_buff1~0_In-2091624068, P1Thread1of1ForFork3_#t~ite4=|P1Thread1of1ForFork3_#t~ite4_Out-2091624068|, P1Thread1of1ForFork3_#t~ite3=|P1Thread1of1ForFork3_#t~ite3_Out-2091624068|, ~y~0=~y~0_In-2091624068, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2091624068} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite4, P1Thread1of1ForFork3_#t~ite3] because there is no mapped edge [2019-12-07 12:40:55,739 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L758-->L758-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd2~0_In1092105639 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In1092105639 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork3_#t~ite5_Out1092105639|)) (and (= ~y$w_buff0_used~0_In1092105639 |P1Thread1of1ForFork3_#t~ite5_Out1092105639|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1092105639, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1092105639} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1092105639, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1092105639, P1Thread1of1ForFork3_#t~ite5=|P1Thread1of1ForFork3_#t~ite5_Out1092105639|} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite5] because there is no mapped edge [2019-12-07 12:40:55,739 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [807] [807] L810-2-->L810-4: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In1209029031 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd4~0_In1209029031 256)))) (or (and (= |P3Thread1of1ForFork1_#t~ite15_Out1209029031| ~y$w_buff1~0_In1209029031) (not .cse0) (not .cse1)) (and (= |P3Thread1of1ForFork1_#t~ite15_Out1209029031| ~y~0_In1209029031) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1209029031, ~y$w_buff1~0=~y$w_buff1~0_In1209029031, ~y~0=~y~0_In1209029031, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1209029031} OutVars{~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1209029031, ~y$w_buff1~0=~y$w_buff1~0_In1209029031, P3Thread1of1ForFork1_#t~ite15=|P3Thread1of1ForFork1_#t~ite15_Out1209029031|, ~y~0=~y~0_In1209029031, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1209029031} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite15] because there is no mapped edge [2019-12-07 12:40:55,740 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [794] [794] L759-->L759-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In656216847 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In656216847 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In656216847 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd2~0_In656216847 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork3_#t~ite6_Out656216847| 0)) (and (or .cse1 .cse0) (or .cse3 .cse2) (= |P1Thread1of1ForFork3_#t~ite6_Out656216847| ~y$w_buff1_used~0_In656216847)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In656216847, ~y$w_buff0_used~0=~y$w_buff0_used~0_In656216847, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In656216847, ~y$w_buff1_used~0=~y$w_buff1_used~0_In656216847} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In656216847, ~y$w_buff0_used~0=~y$w_buff0_used~0_In656216847, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In656216847, P1Thread1of1ForFork3_#t~ite6=|P1Thread1of1ForFork3_#t~ite6_Out656216847|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In656216847} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite6] because there is no mapped edge [2019-12-07 12:40:55,740 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [731] [731] L810-4-->L811: Formula: (= v_~y~0_28 |v_P3Thread1of1ForFork1_#t~ite15_8|) InVars {P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_8|} OutVars{P3Thread1of1ForFork1_#t~ite16=|v_P3Thread1of1ForFork1_#t~ite16_13|, P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_7|, ~y~0=v_~y~0_28} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite16, P3Thread1of1ForFork1_#t~ite15, ~y~0] because there is no mapped edge [2019-12-07 12:40:55,740 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L811-->L811-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1113608328 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd4~0_In-1113608328 256)))) (or (and (not .cse0) (= 0 |P3Thread1of1ForFork1_#t~ite17_Out-1113608328|) (not .cse1)) (and (= ~y$w_buff0_used~0_In-1113608328 |P3Thread1of1ForFork1_#t~ite17_Out-1113608328|) (or .cse1 .cse0)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1113608328, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1113608328} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1113608328, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1113608328, P3Thread1of1ForFork1_#t~ite17=|P3Thread1of1ForFork1_#t~ite17_Out-1113608328|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite17] because there is no mapped edge [2019-12-07 12:40:55,740 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L812-->L812-2: Formula: (let ((.cse0 (= (mod ~y$r_buff1_thd4~0_In1765617603 256) 0)) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In1765617603 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In1765617603 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd4~0_In1765617603 256) 0))) (or (and (= 0 |P3Thread1of1ForFork1_#t~ite18_Out1765617603|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse3 .cse2) (= ~y$w_buff1_used~0_In1765617603 |P3Thread1of1ForFork1_#t~ite18_Out1765617603|)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1765617603, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1765617603, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1765617603, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1765617603} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1765617603, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1765617603, P3Thread1of1ForFork1_#t~ite18=|P3Thread1of1ForFork1_#t~ite18_Out1765617603|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1765617603, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1765617603} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite18] because there is no mapped edge [2019-12-07 12:40:55,741 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L813-->L813-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-744130934 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd4~0_In-744130934 256) 0))) (or (and (not .cse0) (= |P3Thread1of1ForFork1_#t~ite19_Out-744130934| 0) (not .cse1)) (and (or .cse0 .cse1) (= |P3Thread1of1ForFork1_#t~ite19_Out-744130934| ~y$r_buff0_thd4~0_In-744130934)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-744130934, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-744130934} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-744130934, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-744130934, P3Thread1of1ForFork1_#t~ite19=|P3Thread1of1ForFork1_#t~ite19_Out-744130934|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite19] because there is no mapped edge [2019-12-07 12:40:55,741 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L760-->L760-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In1412484338 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In1412484338 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork3_#t~ite7_Out1412484338|)) (and (= ~y$r_buff0_thd2~0_In1412484338 |P1Thread1of1ForFork3_#t~ite7_Out1412484338|) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1412484338, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1412484338} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1412484338, P1Thread1of1ForFork3_#t~ite7=|P1Thread1of1ForFork3_#t~ite7_Out1412484338|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1412484338} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite7] because there is no mapped edge [2019-12-07 12:40:55,741 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [810] [810] L761-->L761-2: Formula: (let ((.cse3 (= 0 (mod ~y$r_buff0_thd2~0_In1697616862 256))) (.cse2 (= (mod ~y$w_buff0_used~0_In1697616862 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In1697616862 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In1697616862 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~y$r_buff1_thd2~0_In1697616862 |P1Thread1of1ForFork3_#t~ite8_Out1697616862|)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= 0 |P1Thread1of1ForFork3_#t~ite8_Out1697616862|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1697616862, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1697616862, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1697616862, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1697616862} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1697616862, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1697616862, P1Thread1of1ForFork3_#t~ite8=|P1Thread1of1ForFork3_#t~ite8_Out1697616862|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1697616862, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1697616862} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite8] because there is no mapped edge [2019-12-07 12:40:55,741 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L761-2-->P1EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_41 1) v_~__unbuffered_cnt~0_40) (= 0 |v_P1Thread1of1ForFork3_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork3_#res.base_3|) (= |v_P1Thread1of1ForFork3_#t~ite8_24| v_~y$r_buff1_thd2~0_111)) InVars {P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_41} OutVars{P1Thread1of1ForFork3_#res.base=|v_P1Thread1of1ForFork3_#res.base_3|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_111, P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_23|, P1Thread1of1ForFork3_#res.offset=|v_P1Thread1of1ForFork3_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#res.base, ~y$r_buff1_thd2~0, P1Thread1of1ForFork3_#t~ite8, P1Thread1of1ForFork3_#res.offset, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 12:40:55,742 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L788-->L788-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd3~0_In-92950177 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-92950177 256)))) (or (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out-92950177| 0) (not .cse1)) (and (= |P2Thread1of1ForFork0_#t~ite11_Out-92950177| ~y$w_buff0_used~0_In-92950177) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-92950177, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-92950177} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-92950177, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-92950177|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-92950177} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 12:40:55,742 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [813] [813] L789-->L789-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd3~0_In832014852 256) 0)) (.cse2 (= (mod ~y$w_buff1_used~0_In832014852 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In832014852 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In832014852 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite12_Out832014852| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse1 .cse0) (= |P2Thread1of1ForFork0_#t~ite12_Out832014852| ~y$w_buff1_used~0_In832014852)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In832014852, ~y$w_buff0_used~0=~y$w_buff0_used~0_In832014852, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In832014852, ~y$w_buff1_used~0=~y$w_buff1_used~0_In832014852} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In832014852, ~y$w_buff0_used~0=~y$w_buff0_used~0_In832014852, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out832014852|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In832014852, ~y$w_buff1_used~0=~y$w_buff1_used~0_In832014852} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 12:40:55,743 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L790-->L791: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In-1829382286 256))) (.cse2 (= (mod ~y$w_buff0_used~0_In-1829382286 256) 0)) (.cse1 (= ~y$r_buff0_thd3~0_In-1829382286 ~y$r_buff0_thd3~0_Out-1829382286))) (or (and .cse0 .cse1) (and (not .cse0) (= 0 ~y$r_buff0_thd3~0_Out-1829382286) (not .cse2)) (and .cse2 .cse1))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1829382286, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1829382286} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1829382286, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-1829382286, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-1829382286|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 12:40:55,743 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L791-->L791-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In75093928 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd3~0_In75093928 256))) (.cse2 (= (mod ~y$w_buff0_used~0_In75093928 256) 0)) (.cse3 (= (mod ~y$r_buff0_thd3~0_In75093928 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite14_Out75093928| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite14_Out75093928| ~y$r_buff1_thd3~0_In75093928) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In75093928, ~y$w_buff0_used~0=~y$w_buff0_used~0_In75093928, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In75093928, ~y$w_buff1_used~0=~y$w_buff1_used~0_In75093928} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out75093928|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In75093928, ~y$w_buff0_used~0=~y$w_buff0_used~0_In75093928, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In75093928, ~y$w_buff1_used~0=~y$w_buff1_used~0_In75093928} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 12:40:55,743 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [847] [847] L791-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= v_~__unbuffered_cnt~0_59 (+ v_~__unbuffered_cnt~0_60 1)) (= v_~y$r_buff1_thd3~0_114 |v_P2Thread1of1ForFork0_#t~ite14_20|) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_20|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_60} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_19|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_114, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_59, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 12:40:55,743 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [792] [792] L814-->L814-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd4~0_In-779818325 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-779818325 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In-779818325 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd4~0_In-779818325 256)))) (or (and (= |P3Thread1of1ForFork1_#t~ite20_Out-779818325| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P3Thread1of1ForFork1_#t~ite20_Out-779818325| ~y$r_buff1_thd4~0_In-779818325) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-779818325, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-779818325, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-779818325, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-779818325} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-779818325, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-779818325, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-779818325, P3Thread1of1ForFork1_#t~ite20=|P3Thread1of1ForFork1_#t~ite20_Out-779818325|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-779818325} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 12:40:55,743 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [846] [846] L814-2-->P3EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_54 1) v_~__unbuffered_cnt~0_53) (= |v_P3Thread1of1ForFork1_#t~ite20_28| v_~y$r_buff1_thd4~0_111) (= |v_P3Thread1of1ForFork1_#res.offset_3| 0) (= |v_P3Thread1of1ForFork1_#res.base_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_28|} OutVars{~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_111, P3Thread1of1ForFork1_#res.base=|v_P3Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_53, P3Thread1of1ForFork1_#res.offset=|v_P3Thread1of1ForFork1_#res.offset_3|, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_27|} AuxVars[] AssignedVars[~y$r_buff1_thd4~0, P3Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork1_#res.offset, P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 12:40:55,743 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L843-->L845-2: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (or (= (mod v_~y$w_buff0_used~0_216 256) 0) (= 0 (mod v_~y$r_buff0_thd0~0_104 256)))) InVars {~y$w_buff0_used~0=v_~y$w_buff0_used~0_216, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} OutVars{~y$w_buff0_used~0=v_~y$w_buff0_used~0_216, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 12:40:55,743 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L845-2-->L845-5: Formula: (let ((.cse1 (= (mod ~y$r_buff1_thd0~0_In-2107457801 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In-2107457801 256) 0)) (.cse2 (= |ULTIMATE.start_main_#t~ite25_Out-2107457801| |ULTIMATE.start_main_#t~ite26_Out-2107457801|))) (or (and (= |ULTIMATE.start_main_#t~ite25_Out-2107457801| ~y~0_In-2107457801) (or .cse0 .cse1) .cse2) (and (= |ULTIMATE.start_main_#t~ite25_Out-2107457801| ~y$w_buff1~0_In-2107457801) (not .cse1) (not .cse0) .cse2))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-2107457801, ~y~0=~y~0_In-2107457801, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-2107457801, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2107457801} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-2107457801, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-2107457801|, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-2107457801|, ~y~0=~y~0_In-2107457801, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-2107457801, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2107457801} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 12:40:55,744 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [797] [797] L846-->L846-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In556539303 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In556539303 256)))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite27_Out556539303| 0)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite27_Out556539303| ~y$w_buff0_used~0_In556539303)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In556539303, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In556539303} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In556539303, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In556539303, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out556539303|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 12:40:55,744 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L847-->L847-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff1_used~0_In530121068 256))) (.cse2 (= (mod ~y$r_buff1_thd0~0_In530121068 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In530121068 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In530121068 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite28_Out530121068| 0)) (and (= |ULTIMATE.start_main_#t~ite28_Out530121068| ~y$w_buff1_used~0_In530121068) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In530121068, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In530121068, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In530121068, ~y$w_buff1_used~0=~y$w_buff1_used~0_In530121068} OutVars{ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out530121068|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In530121068, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In530121068, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In530121068, ~y$w_buff1_used~0=~y$w_buff1_used~0_In530121068} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 12:40:55,745 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [812] [812] L848-->L848-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-219992588 256))) (.cse0 (= (mod ~y$r_buff0_thd0~0_In-219992588 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite29_Out-219992588| ~y$r_buff0_thd0~0_In-219992588)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite29_Out-219992588| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-219992588, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-219992588} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-219992588, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-219992588|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-219992588} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 12:40:55,745 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [790] [790] L849-->L849-2: Formula: (let ((.cse2 (= (mod ~y$r_buff0_thd0~0_In-1833700979 256) 0)) (.cse3 (= (mod ~y$w_buff0_used~0_In-1833700979 256) 0)) (.cse1 (= (mod ~y$w_buff1_used~0_In-1833700979 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-1833700979 256)))) (or (and (= ~y$r_buff1_thd0~0_In-1833700979 |ULTIMATE.start_main_#t~ite30_Out-1833700979|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |ULTIMATE.start_main_#t~ite30_Out-1833700979|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1833700979, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1833700979, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1833700979, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1833700979} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out-1833700979|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1833700979, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1833700979, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1833700979, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1833700979} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30] because there is no mapped edge [2019-12-07 12:40:55,746 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [852] [852] L858-->L858-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In319421602 256)))) (or (and (= |ULTIMATE.start_main_#t~ite39_Out319421602| |ULTIMATE.start_main_#t~ite40_Out319421602|) (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In319421602 256)))) (or (= (mod ~y$w_buff0_used~0_In319421602 256) 0) (and (= 0 (mod ~y$w_buff1_used~0_In319421602 256)) .cse0) (and (= 0 (mod ~y$r_buff1_thd0~0_In319421602 256)) .cse0))) (= |ULTIMATE.start_main_#t~ite39_Out319421602| ~y$w_buff1~0_In319421602) .cse1) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite40_Out319421602| ~y$w_buff1~0_In319421602) (= |ULTIMATE.start_main_#t~ite39_In319421602| |ULTIMATE.start_main_#t~ite39_Out319421602|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In319421602, ~y$w_buff0_used~0=~y$w_buff0_used~0_In319421602, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_In319421602|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In319421602, ~weak$$choice2~0=~weak$$choice2~0_In319421602, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In319421602, ~y$w_buff1_used~0=~y$w_buff1_used~0_In319421602} OutVars{ULTIMATE.start_main_#t~ite40=|ULTIMATE.start_main_#t~ite40_Out319421602|, ~y$w_buff1~0=~y$w_buff1~0_In319421602, ~y$w_buff0_used~0=~y$w_buff0_used~0_In319421602, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out319421602|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In319421602, ~weak$$choice2~0=~weak$$choice2~0_In319421602, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In319421602, ~y$w_buff1_used~0=~y$w_buff1_used~0_In319421602} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 12:40:55,747 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L859-->L859-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-981678590 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite42_In-981678590| |ULTIMATE.start_main_#t~ite42_Out-981678590|) (not .cse0) (= |ULTIMATE.start_main_#t~ite43_Out-981678590| ~y$w_buff0_used~0_In-981678590)) (and (= ~y$w_buff0_used~0_In-981678590 |ULTIMATE.start_main_#t~ite42_Out-981678590|) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-981678590 256)))) (or (and .cse1 (= (mod ~y$w_buff1_used~0_In-981678590 256) 0)) (= 0 (mod ~y$w_buff0_used~0_In-981678590 256)) (and (= 0 (mod ~y$r_buff1_thd0~0_In-981678590 256)) .cse1))) .cse0 (= |ULTIMATE.start_main_#t~ite43_Out-981678590| |ULTIMATE.start_main_#t~ite42_Out-981678590|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-981678590, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-981678590, ~weak$$choice2~0=~weak$$choice2~0_In-981678590, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-981678590, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_In-981678590|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-981678590} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-981678590, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-981678590, ULTIMATE.start_main_#t~ite43=|ULTIMATE.start_main_#t~ite43_Out-981678590|, ~weak$$choice2~0=~weak$$choice2~0_In-981678590, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_Out-981678590|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-981678590, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-981678590} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 12:40:55,747 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [865] [865] L860-->L860-8: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite45_Out2011853808| |ULTIMATE.start_main_#t~ite46_Out2011853808|)) (.cse1 (= (mod ~weak$$choice2~0_In2011853808 256) 0)) (.cse3 (= (mod ~y$r_buff1_thd0~0_In2011853808 256) 0)) (.cse4 (= (mod ~y$w_buff0_used~0_In2011853808 256) 0)) (.cse6 (= (mod ~y$r_buff0_thd0~0_In2011853808 256) 0)) (.cse5 (= (mod ~y$w_buff1_used~0_In2011853808 256) 0))) (or (let ((.cse2 (not .cse6))) (and .cse0 .cse1 (or .cse2 (not .cse3)) (= |ULTIMATE.start_main_#t~ite44_Out2011853808| |ULTIMATE.start_main_#t~ite45_Out2011853808|) (not .cse4) (or .cse2 (not .cse5)) (= |ULTIMATE.start_main_#t~ite44_Out2011853808| 0))) (and (= |ULTIMATE.start_main_#t~ite44_In2011853808| |ULTIMATE.start_main_#t~ite44_Out2011853808|) (or (and (not .cse1) (= |ULTIMATE.start_main_#t~ite45_In2011853808| |ULTIMATE.start_main_#t~ite45_Out2011853808|) (= ~y$w_buff1_used~0_In2011853808 |ULTIMATE.start_main_#t~ite46_Out2011853808|)) (and .cse0 .cse1 (= ~y$w_buff1_used~0_In2011853808 |ULTIMATE.start_main_#t~ite45_Out2011853808|) (or (and .cse3 .cse6) .cse4 (and .cse6 .cse5))))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In2011853808, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In2011853808, ~weak$$choice2~0=~weak$$choice2~0_In2011853808, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In2011853808, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In2011853808|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2011853808, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_In2011853808|} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In2011853808, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In2011853808, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out2011853808|, ~weak$$choice2~0=~weak$$choice2~0_In2011853808, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In2011853808, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out2011853808|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2011853808, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_Out2011853808|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-12-07 12:40:55,747 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [868] [868] L860-8-->L862: Formula: (and (not (= (mod v_~weak$$choice2~0_106 256) 0)) (= v_~y$w_buff1_used~0_383 |v_ULTIMATE.start_main_#t~ite46_36|) (= v_~y$r_buff0_thd0~0_352 v_~y$r_buff0_thd0~0_351)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_352, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~weak$$choice2~0=v_~weak$$choice2~0_106} OutVars{~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_351, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_35|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_31|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_34|, ~weak$$choice2~0=v_~weak$$choice2~0_106, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_33|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_383} AuxVars[] AssignedVars[~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 12:40:55,748 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L864-->L4: Formula: (and (= 0 v_~y$flush_delayed~0_25) (= v_~y~0_116 v_~y$mem_tmp~0_11) (not (= (mod v_~y$flush_delayed~0_26 256) 0)) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5| (mod v_~main$tmp_guard1~0_15 256))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_26, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_11, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ~y$flush_delayed~0=v_~y$flush_delayed~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15, ~y~0=v_~y~0_116, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_23|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ~y~0, ULTIMATE.start_main_#t~ite53, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 12:40:55,748 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 12:40:55,811 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_0895eb14-1481-4887-8296-220dee113e49/bin/uautomizer/witness.graphml [2019-12-07 12:40:55,811 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 12:40:55,812 INFO L168 Benchmark]: Toolchain (without parser) took 178893.52 ms. Allocated memory was 1.0 GB in the beginning and 9.3 GB in the end (delta: 8.3 GB). Free memory was 937.1 MB in the beginning and 5.0 GB in the end (delta: -4.1 GB). Peak memory consumption was 4.2 GB. Max. memory is 11.5 GB. [2019-12-07 12:40:55,812 INFO L168 Benchmark]: CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 12:40:55,813 INFO L168 Benchmark]: CACSL2BoogieTranslator took 387.52 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 102.2 MB). Free memory was 937.1 MB in the beginning and 1.1 GB in the end (delta: -127.4 MB). Peak memory consumption was 18.5 MB. Max. memory is 11.5 GB. [2019-12-07 12:40:55,813 INFO L168 Benchmark]: Boogie Procedure Inliner took 40.40 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 12:40:55,813 INFO L168 Benchmark]: Boogie Preprocessor took 26.68 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 12:40:55,813 INFO L168 Benchmark]: RCFGBuilder took 432.70 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 56.3 MB). Peak memory consumption was 56.3 MB. Max. memory is 11.5 GB. [2019-12-07 12:40:55,813 INFO L168 Benchmark]: TraceAbstraction took 177925.69 ms. Allocated memory was 1.1 GB in the beginning and 9.3 GB in the end (delta: 8.2 GB). Free memory was 1.0 GB in the beginning and 5.1 GB in the end (delta: -4.0 GB). Peak memory consumption was 4.2 GB. Max. memory is 11.5 GB. [2019-12-07 12:40:55,814 INFO L168 Benchmark]: Witness Printer took 77.01 ms. Allocated memory is still 9.3 GB. Free memory was 5.1 GB in the beginning and 5.0 GB in the end (delta: 41.5 MB). Peak memory consumption was 41.5 MB. Max. memory is 11.5 GB. [2019-12-07 12:40:55,815 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 387.52 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 102.2 MB). Free memory was 937.1 MB in the beginning and 1.1 GB in the end (delta: -127.4 MB). Peak memory consumption was 18.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 40.40 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.68 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 432.70 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 56.3 MB). Peak memory consumption was 56.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 177925.69 ms. Allocated memory was 1.1 GB in the beginning and 9.3 GB in the end (delta: 8.2 GB). Free memory was 1.0 GB in the beginning and 5.1 GB in the end (delta: -4.0 GB). Peak memory consumption was 4.2 GB. Max. memory is 11.5 GB. * Witness Printer took 77.01 ms. Allocated memory is still 9.3 GB. Free memory was 5.1 GB in the beginning and 5.0 GB in the end (delta: 41.5 MB). Peak memory consumption was 41.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.3s, 192 ProgramPointsBefore, 97 ProgramPointsAfterwards, 226 TransitionsBefore, 103 TransitionsAfterwards, 18432 CoEnabledTransitionPairs, 8 FixpointIterations, 36 TrivialSequentialCompositions, 54 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 37 ConcurrentYvCompositions, 33 ChoiceCompositions, 6018 VarBasedMoverChecksPositive, 223 VarBasedMoverChecksNegative, 64 SemBasedMoverChecksPositive, 227 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.7s, 0 MoverChecksTotal, 86545 CheckedPairsTotal, 127 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L833] FCALL, FORK 0 pthread_create(&t773, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L835] FCALL, FORK 0 pthread_create(&t774, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L837] FCALL, FORK 0 pthread_create(&t775, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L776] 3 y$r_buff1_thd0 = y$r_buff0_thd0 [L777] 3 y$r_buff1_thd1 = y$r_buff0_thd1 [L778] 3 y$r_buff1_thd2 = y$r_buff0_thd2 [L779] 3 y$r_buff1_thd3 = y$r_buff0_thd3 [L780] 3 y$r_buff1_thd4 = y$r_buff0_thd4 [L781] 3 y$r_buff0_thd3 = (_Bool)1 [L784] 3 z = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L839] FCALL, FORK 0 pthread_create(&t776, ((void *)0), P3, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L801] 4 z = 2 [L804] 4 __unbuffered_p3_EAX = z [L807] 4 __unbuffered_p3_EBX = a VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L810] 4 y$w_buff0_used && y$r_buff0_thd4 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd4 ? y$w_buff1 : y) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L751] 2 x = 1 [L754] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L757] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L757] 2 y = y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) [L758] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L811] 4 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd4 ? (_Bool)0 : y$w_buff0_used [L812] 4 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd4 || y$w_buff1_used && y$r_buff1_thd4 ? (_Bool)0 : y$w_buff1_used [L787] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L759] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L760] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L787] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L788] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L789] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L813] 4 y$r_buff0_thd4 = y$w_buff0_used && y$r_buff0_thd4 ? (_Bool)0 : y$r_buff0_thd4 [L841] 0 main$tmp_guard0 = __unbuffered_cnt == 4 VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L845] 0 y = y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L846] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L847] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L848] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L849] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L852] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L853] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L854] 0 y$flush_delayed = weak$$choice2 [L855] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L856] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L856] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L857] EXPR 0 weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L857] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L858] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L859] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L862] EXPR 0 weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L862] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L863] 0 main$tmp_guard1 = !(y == 2 && z == 2 && __unbuffered_p0_EAX == 0 && __unbuffered_p3_EAX == 2 && __unbuffered_p3_EBX == 0) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 180 locations, 2 error locations. Result: UNSAFE, OverallTime: 177.7s, OverallIterations: 25, TraceHistogramMax: 1, AutomataDifference: 43.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 4677 SDtfs, 4853 SDslu, 10103 SDs, 0 SdLazy, 5589 SolverSat, 262 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 4.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 208 GetRequests, 33 SyntacticMatches, 29 SemanticMatches, 146 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 212 ImplicationChecksByTransitivity, 1.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=389200occurred in iteration=5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 90.2s AutomataMinimizationTime, 24 MinimizatonAttempts, 359140 StatesRemovedByMinimization, 18 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.1s InterpolantComputationTime, 1083 NumberOfCodeBlocks, 1083 NumberOfCodeBlocksAsserted, 25 NumberOfCheckSat, 989 ConstructedInterpolants, 0 QuantifiedInterpolants, 163785 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 24 InterpolantComputations, 24 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...