./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix029_pso.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_b2944d01-8133-423d-a01f-2142f92440a1/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_b2944d01-8133-423d-a01f-2142f92440a1/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_b2944d01-8133-423d-a01f-2142f92440a1/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_b2944d01-8133-423d-a01f-2142f92440a1/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix029_pso.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_b2944d01-8133-423d-a01f-2142f92440a1/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_b2944d01-8133-423d-a01f-2142f92440a1/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a5da3748fa245dff4595e6843fea81f981082d92 ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 10:35:16,691 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 10:35:16,692 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 10:35:16,700 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 10:35:16,700 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 10:35:16,701 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 10:35:16,702 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 10:35:16,703 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 10:35:16,705 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 10:35:16,705 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 10:35:16,706 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 10:35:16,707 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 10:35:16,707 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 10:35:16,708 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 10:35:16,708 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 10:35:16,709 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 10:35:16,710 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 10:35:16,710 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 10:35:16,712 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 10:35:16,713 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 10:35:16,715 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 10:35:16,716 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 10:35:16,717 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 10:35:16,717 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 10:35:16,719 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 10:35:16,719 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 10:35:16,720 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 10:35:16,720 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 10:35:16,720 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 10:35:16,721 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 10:35:16,721 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 10:35:16,722 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 10:35:16,723 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 10:35:16,723 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 10:35:16,724 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 10:35:16,724 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 10:35:16,725 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 10:35:16,725 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 10:35:16,725 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 10:35:16,726 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 10:35:16,726 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 10:35:16,727 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_b2944d01-8133-423d-a01f-2142f92440a1/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 10:35:16,740 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 10:35:16,740 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 10:35:16,741 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 10:35:16,741 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 10:35:16,741 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 10:35:16,742 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 10:35:16,742 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 10:35:16,742 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 10:35:16,742 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 10:35:16,742 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 10:35:16,743 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 10:35:16,743 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 10:35:16,743 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 10:35:16,743 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 10:35:16,743 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 10:35:16,744 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 10:35:16,744 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 10:35:16,744 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 10:35:16,744 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 10:35:16,744 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 10:35:16,745 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 10:35:16,745 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 10:35:16,745 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 10:35:16,745 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 10:35:16,745 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 10:35:16,745 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 10:35:16,746 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 10:35:16,746 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 10:35:16,746 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 10:35:16,746 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_b2944d01-8133-423d-a01f-2142f92440a1/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a5da3748fa245dff4595e6843fea81f981082d92 [2019-12-07 10:35:16,866 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 10:35:16,877 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 10:35:16,880 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 10:35:16,881 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 10:35:16,882 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 10:35:16,882 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_b2944d01-8133-423d-a01f-2142f92440a1/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix029_pso.opt.i [2019-12-07 10:35:16,924 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_b2944d01-8133-423d-a01f-2142f92440a1/bin/uautomizer/data/f7fab57d6/e2043bf00f27400ab6d59b39894498a8/FLAGd7be4db44 [2019-12-07 10:35:17,401 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 10:35:17,402 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_b2944d01-8133-423d-a01f-2142f92440a1/sv-benchmarks/c/pthread-wmm/mix029_pso.opt.i [2019-12-07 10:35:17,413 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_b2944d01-8133-423d-a01f-2142f92440a1/bin/uautomizer/data/f7fab57d6/e2043bf00f27400ab6d59b39894498a8/FLAGd7be4db44 [2019-12-07 10:35:17,423 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_b2944d01-8133-423d-a01f-2142f92440a1/bin/uautomizer/data/f7fab57d6/e2043bf00f27400ab6d59b39894498a8 [2019-12-07 10:35:17,425 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 10:35:17,426 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 10:35:17,427 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 10:35:17,427 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 10:35:17,429 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 10:35:17,430 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 10:35:17" (1/1) ... [2019-12-07 10:35:17,431 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3f8fae9c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 10:35:17, skipping insertion in model container [2019-12-07 10:35:17,431 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 10:35:17" (1/1) ... [2019-12-07 10:35:17,436 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 10:35:17,467 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 10:35:17,748 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 10:35:17,758 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 10:35:17,814 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 10:35:17,865 INFO L208 MainTranslator]: Completed translation [2019-12-07 10:35:17,866 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 10:35:17 WrapperNode [2019-12-07 10:35:17,866 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 10:35:17,866 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 10:35:17,866 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 10:35:17,866 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 10:35:17,872 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 10:35:17" (1/1) ... [2019-12-07 10:35:17,890 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 10:35:17" (1/1) ... [2019-12-07 10:35:17,917 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 10:35:17,918 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 10:35:17,918 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 10:35:17,918 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 10:35:17,926 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 10:35:17" (1/1) ... [2019-12-07 10:35:17,926 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 10:35:17" (1/1) ... [2019-12-07 10:35:17,931 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 10:35:17" (1/1) ... [2019-12-07 10:35:17,931 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 10:35:17" (1/1) ... [2019-12-07 10:35:17,941 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 10:35:17" (1/1) ... [2019-12-07 10:35:17,944 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 10:35:17" (1/1) ... [2019-12-07 10:35:17,946 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 10:35:17" (1/1) ... [2019-12-07 10:35:17,949 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 10:35:17,950 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 10:35:17,950 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 10:35:17,950 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 10:35:17,950 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 10:35:17" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b2944d01-8133-423d-a01f-2142f92440a1/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 10:35:17,997 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 10:35:17,997 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 10:35:17,997 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 10:35:17,997 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 10:35:17,997 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 10:35:17,997 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 10:35:17,998 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 10:35:17,998 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 10:35:17,998 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 10:35:17,998 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 10:35:17,998 INFO L130 BoogieDeclarations]: Found specification of procedure P3 [2019-12-07 10:35:17,998 INFO L138 BoogieDeclarations]: Found implementation of procedure P3 [2019-12-07 10:35:17,998 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 10:35:17,998 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 10:35:17,998 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 10:35:17,999 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 10:35:18,380 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 10:35:18,381 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 10:35:18,381 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 10:35:18 BoogieIcfgContainer [2019-12-07 10:35:18,382 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 10:35:18,382 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 10:35:18,382 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 10:35:18,384 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 10:35:18,384 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 10:35:17" (1/3) ... [2019-12-07 10:35:18,385 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4ff97fc6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 10:35:18, skipping insertion in model container [2019-12-07 10:35:18,385 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 10:35:17" (2/3) ... [2019-12-07 10:35:18,385 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4ff97fc6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 10:35:18, skipping insertion in model container [2019-12-07 10:35:18,385 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 10:35:18" (3/3) ... [2019-12-07 10:35:18,386 INFO L109 eAbstractionObserver]: Analyzing ICFG mix029_pso.opt.i [2019-12-07 10:35:18,393 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 10:35:18,393 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 10:35:18,398 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 10:35:18,398 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 10:35:18,423 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,423 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,423 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,423 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,423 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,423 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,424 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,424 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,424 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork3_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,424 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork3_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,424 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,425 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,425 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,425 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,425 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,425 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,425 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,425 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,426 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,426 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,426 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,426 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,426 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,426 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,426 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,426 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,427 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,427 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,427 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,427 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,427 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,427 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,427 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,428 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,428 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,428 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,428 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,428 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,429 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,429 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,429 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,429 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,429 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,429 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,429 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,430 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,430 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,430 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,430 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,430 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,430 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,430 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,430 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,431 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,431 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,431 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,431 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,431 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,431 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,431 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,431 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,432 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,432 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,432 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,432 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,432 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,432 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,432 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,432 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,433 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,433 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,433 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,433 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,433 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,433 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,433 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,434 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,434 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,434 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,434 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,434 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,434 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,434 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,434 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,435 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,435 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,435 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,435 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,435 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,435 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,435 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,435 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,436 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,436 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,436 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,436 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,436 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,436 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,436 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,436 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 10:35:18,449 INFO L249 AbstractCegarLoop]: Starting to check reachability of 7 error locations. [2019-12-07 10:35:18,461 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 10:35:18,461 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 10:35:18,461 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 10:35:18,461 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 10:35:18,461 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 10:35:18,462 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 10:35:18,462 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 10:35:18,462 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 10:35:18,473 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 192 places, 226 transitions [2019-12-07 10:35:18,474 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 192 places, 226 transitions [2019-12-07 10:35:18,531 INFO L134 PetriNetUnfolder]: 47/222 cut-off events. [2019-12-07 10:35:18,531 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 10:35:18,541 INFO L76 FinitePrefix]: Finished finitePrefix Result has 235 conditions, 222 events. 47/222 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 586 event pairs. 12/185 useless extension candidates. Maximal degree in co-relation 190. Up to 2 conditions per place. [2019-12-07 10:35:18,557 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 192 places, 226 transitions [2019-12-07 10:35:18,588 INFO L134 PetriNetUnfolder]: 47/222 cut-off events. [2019-12-07 10:35:18,588 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 10:35:18,594 INFO L76 FinitePrefix]: Finished finitePrefix Result has 235 conditions, 222 events. 47/222 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 586 event pairs. 12/185 useless extension candidates. Maximal degree in co-relation 190. Up to 2 conditions per place. [2019-12-07 10:35:18,609 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 18432 [2019-12-07 10:35:18,610 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 10:35:21,722 WARN L192 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 97 DAG size of output: 95 [2019-12-07 10:35:21,831 INFO L206 etLargeBlockEncoding]: Checked pairs total: 86545 [2019-12-07 10:35:21,831 INFO L214 etLargeBlockEncoding]: Total number of compositions: 127 [2019-12-07 10:35:21,833 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 97 places, 103 transitions [2019-12-07 10:35:57,986 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 199530 states. [2019-12-07 10:35:57,988 INFO L276 IsEmpty]: Start isEmpty. Operand 199530 states. [2019-12-07 10:35:57,992 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-12-07 10:35:57,992 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:35:57,992 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:35:57,993 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:35:57,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:35:57,996 INFO L82 PathProgramCache]: Analyzing trace with hash 1574015469, now seen corresponding path program 1 times [2019-12-07 10:35:58,002 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:35:58,002 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497264777] [2019-12-07 10:35:58,002 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:35:58,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:35:58,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:35:58,166 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [497264777] [2019-12-07 10:35:58,167 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:35:58,167 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 10:35:58,167 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [946397640] [2019-12-07 10:35:58,170 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 10:35:58,170 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:35:58,179 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 10:35:58,179 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 10:35:58,181 INFO L87 Difference]: Start difference. First operand 199530 states. Second operand 3 states. [2019-12-07 10:36:01,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:36:01,277 INFO L93 Difference]: Finished difference Result 198930 states and 939730 transitions. [2019-12-07 10:36:01,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 10:36:01,279 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-12-07 10:36:01,279 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:36:02,089 INFO L225 Difference]: With dead ends: 198930 [2019-12-07 10:36:02,090 INFO L226 Difference]: Without dead ends: 194562 [2019-12-07 10:36:02,090 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 10:36:07,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 194562 states. [2019-12-07 10:36:10,682 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 194562 to 194562. [2019-12-07 10:36:10,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194562 states. [2019-12-07 10:36:11,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194562 states to 194562 states and 919710 transitions. [2019-12-07 10:36:11,772 INFO L78 Accepts]: Start accepts. Automaton has 194562 states and 919710 transitions. Word has length 7 [2019-12-07 10:36:11,772 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:36:11,772 INFO L462 AbstractCegarLoop]: Abstraction has 194562 states and 919710 transitions. [2019-12-07 10:36:11,773 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 10:36:11,773 INFO L276 IsEmpty]: Start isEmpty. Operand 194562 states and 919710 transitions. [2019-12-07 10:36:11,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 10:36:11,776 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:36:11,776 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:36:11,776 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:36:11,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:36:11,776 INFO L82 PathProgramCache]: Analyzing trace with hash 1968556431, now seen corresponding path program 1 times [2019-12-07 10:36:11,777 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:36:11,777 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [975101153] [2019-12-07 10:36:11,777 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:36:11,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:36:11,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:36:11,849 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [975101153] [2019-12-07 10:36:11,850 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:36:11,850 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 10:36:11,850 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [166798072] [2019-12-07 10:36:11,851 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 10:36:11,851 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:36:11,851 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 10:36:11,851 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 10:36:11,851 INFO L87 Difference]: Start difference. First operand 194562 states and 919710 transitions. Second operand 4 states. [2019-12-07 10:36:13,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:36:13,643 INFO L93 Difference]: Finished difference Result 312518 states and 1424536 transitions. [2019-12-07 10:36:13,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 10:36:13,643 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 10:36:13,643 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:36:18,089 INFO L225 Difference]: With dead ends: 312518 [2019-12-07 10:36:18,089 INFO L226 Difference]: Without dead ends: 312420 [2019-12-07 10:36:18,090 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 10:36:25,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312420 states. [2019-12-07 10:36:29,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312420 to 280564. [2019-12-07 10:36:29,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280564 states. [2019-12-07 10:36:30,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280564 states to 280564 states and 1291349 transitions. [2019-12-07 10:36:30,606 INFO L78 Accepts]: Start accepts. Automaton has 280564 states and 1291349 transitions. Word has length 13 [2019-12-07 10:36:30,606 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:36:30,606 INFO L462 AbstractCegarLoop]: Abstraction has 280564 states and 1291349 transitions. [2019-12-07 10:36:30,606 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 10:36:30,606 INFO L276 IsEmpty]: Start isEmpty. Operand 280564 states and 1291349 transitions. [2019-12-07 10:36:30,611 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 10:36:30,611 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:36:30,611 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:36:30,611 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:36:30,611 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:36:30,612 INFO L82 PathProgramCache]: Analyzing trace with hash 381664219, now seen corresponding path program 1 times [2019-12-07 10:36:30,612 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:36:30,612 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [164510942] [2019-12-07 10:36:30,612 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:36:30,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:36:30,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:36:30,663 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [164510942] [2019-12-07 10:36:30,663 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:36:30,664 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 10:36:30,664 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1417504879] [2019-12-07 10:36:30,664 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 10:36:30,664 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:36:30,664 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 10:36:30,664 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 10:36:30,664 INFO L87 Difference]: Start difference. First operand 280564 states and 1291349 transitions. Second operand 4 states. [2019-12-07 10:36:33,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:36:33,447 INFO L93 Difference]: Finished difference Result 400666 states and 1806688 transitions. [2019-12-07 10:36:33,447 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 10:36:33,447 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 10:36:33,448 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:36:34,660 INFO L225 Difference]: With dead ends: 400666 [2019-12-07 10:36:34,660 INFO L226 Difference]: Without dead ends: 400540 [2019-12-07 10:36:34,661 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 10:36:46,712 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 400540 states. [2019-12-07 10:36:51,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 400540 to 335984. [2019-12-07 10:36:51,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 335984 states. [2019-12-07 10:36:53,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 335984 states to 335984 states and 1536425 transitions. [2019-12-07 10:36:53,473 INFO L78 Accepts]: Start accepts. Automaton has 335984 states and 1536425 transitions. Word has length 15 [2019-12-07 10:36:53,473 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:36:53,473 INFO L462 AbstractCegarLoop]: Abstraction has 335984 states and 1536425 transitions. [2019-12-07 10:36:53,473 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 10:36:53,473 INFO L276 IsEmpty]: Start isEmpty. Operand 335984 states and 1536425 transitions. [2019-12-07 10:36:53,476 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 10:36:53,476 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:36:53,476 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:36:53,477 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:36:53,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:36:53,477 INFO L82 PathProgramCache]: Analyzing trace with hash 1895054000, now seen corresponding path program 1 times [2019-12-07 10:36:53,477 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:36:53,477 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1307766043] [2019-12-07 10:36:53,477 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:36:53,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:36:53,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:36:53,522 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1307766043] [2019-12-07 10:36:53,522 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:36:53,522 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 10:36:53,523 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [732529391] [2019-12-07 10:36:53,523 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 10:36:53,523 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:36:53,523 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 10:36:53,523 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 10:36:53,523 INFO L87 Difference]: Start difference. First operand 335984 states and 1536425 transitions. Second operand 4 states. [2019-12-07 10:36:56,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:36:56,559 INFO L93 Difference]: Finished difference Result 416162 states and 1884830 transitions. [2019-12-07 10:36:56,560 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 10:36:56,560 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 10:36:56,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:37:02,607 INFO L225 Difference]: With dead ends: 416162 [2019-12-07 10:37:02,607 INFO L226 Difference]: Without dead ends: 416162 [2019-12-07 10:37:02,607 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 10:37:10,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 416162 states. [2019-12-07 10:37:16,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 416162 to 354242. [2019-12-07 10:37:16,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 354242 states. [2019-12-07 10:37:18,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 354242 states to 354242 states and 1619952 transitions. [2019-12-07 10:37:18,005 INFO L78 Accepts]: Start accepts. Automaton has 354242 states and 1619952 transitions. Word has length 15 [2019-12-07 10:37:18,006 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:37:18,006 INFO L462 AbstractCegarLoop]: Abstraction has 354242 states and 1619952 transitions. [2019-12-07 10:37:18,006 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 10:37:18,006 INFO L276 IsEmpty]: Start isEmpty. Operand 354242 states and 1619952 transitions. [2019-12-07 10:37:18,040 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 10:37:18,040 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:37:18,040 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:37:18,040 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:37:18,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:37:18,041 INFO L82 PathProgramCache]: Analyzing trace with hash -244633219, now seen corresponding path program 1 times [2019-12-07 10:37:18,041 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:37:18,041 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421083994] [2019-12-07 10:37:18,041 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:37:18,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:37:18,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:37:18,109 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [421083994] [2019-12-07 10:37:18,109 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:37:18,109 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 10:37:18,110 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [236643454] [2019-12-07 10:37:18,110 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 10:37:18,110 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:37:18,110 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 10:37:18,110 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 10:37:18,110 INFO L87 Difference]: Start difference. First operand 354242 states and 1619952 transitions. Second operand 5 states. [2019-12-07 10:37:21,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:37:21,963 INFO L93 Difference]: Finished difference Result 524522 states and 2349272 transitions. [2019-12-07 10:37:21,963 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 10:37:21,964 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2019-12-07 10:37:21,964 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:37:28,238 INFO L225 Difference]: With dead ends: 524522 [2019-12-07 10:37:28,238 INFO L226 Difference]: Without dead ends: 524242 [2019-12-07 10:37:28,239 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 10:37:37,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 524242 states. [2019-12-07 10:37:43,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 524242 to 389200. [2019-12-07 10:37:43,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 389200 states. [2019-12-07 10:37:45,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389200 states to 389200 states and 1771393 transitions. [2019-12-07 10:37:45,853 INFO L78 Accepts]: Start accepts. Automaton has 389200 states and 1771393 transitions. Word has length 21 [2019-12-07 10:37:45,853 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:37:45,854 INFO L462 AbstractCegarLoop]: Abstraction has 389200 states and 1771393 transitions. [2019-12-07 10:37:45,854 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 10:37:45,854 INFO L276 IsEmpty]: Start isEmpty. Operand 389200 states and 1771393 transitions. [2019-12-07 10:37:45,874 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 10:37:45,874 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:37:45,874 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:37:45,875 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:37:45,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:37:45,875 INFO L82 PathProgramCache]: Analyzing trace with hash 1268756562, now seen corresponding path program 1 times [2019-12-07 10:37:45,875 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:37:45,875 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [850381708] [2019-12-07 10:37:45,875 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:37:45,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:37:45,929 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:37:45,929 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [850381708] [2019-12-07 10:37:45,929 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:37:45,929 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 10:37:45,930 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1407448756] [2019-12-07 10:37:45,930 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 10:37:45,930 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:37:45,930 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 10:37:45,930 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 10:37:45,931 INFO L87 Difference]: Start difference. First operand 389200 states and 1771393 transitions. Second operand 4 states. [2019-12-07 10:37:47,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:37:47,065 INFO L93 Difference]: Finished difference Result 238312 states and 967580 transitions. [2019-12-07 10:37:47,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 10:37:47,066 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 21 [2019-12-07 10:37:47,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:37:48,224 INFO L225 Difference]: With dead ends: 238312 [2019-12-07 10:37:48,224 INFO L226 Difference]: Without dead ends: 229238 [2019-12-07 10:37:48,225 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 10:37:56,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 229238 states. [2019-12-07 10:37:59,005 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 229238 to 229238. [2019-12-07 10:37:59,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 229238 states. [2019-12-07 10:38:00,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 229238 states to 229238 states and 933345 transitions. [2019-12-07 10:38:00,057 INFO L78 Accepts]: Start accepts. Automaton has 229238 states and 933345 transitions. Word has length 21 [2019-12-07 10:38:00,057 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:38:00,057 INFO L462 AbstractCegarLoop]: Abstraction has 229238 states and 933345 transitions. [2019-12-07 10:38:00,057 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 10:38:00,057 INFO L276 IsEmpty]: Start isEmpty. Operand 229238 states and 933345 transitions. [2019-12-07 10:38:00,069 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 10:38:00,069 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:38:00,069 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:38:00,070 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:38:00,070 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:38:00,070 INFO L82 PathProgramCache]: Analyzing trace with hash -1702977174, now seen corresponding path program 1 times [2019-12-07 10:38:00,070 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:38:00,070 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814381963] [2019-12-07 10:38:00,070 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:38:00,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:38:00,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:38:00,121 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [814381963] [2019-12-07 10:38:00,122 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:38:00,122 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 10:38:00,122 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1840667873] [2019-12-07 10:38:00,122 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 10:38:00,122 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:38:00,123 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 10:38:00,123 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 10:38:00,123 INFO L87 Difference]: Start difference. First operand 229238 states and 933345 transitions. Second operand 5 states. [2019-12-07 10:38:00,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:38:00,312 INFO L93 Difference]: Finished difference Result 47123 states and 156709 transitions. [2019-12-07 10:38:00,313 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 10:38:00,313 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 22 [2019-12-07 10:38:00,313 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:38:00,375 INFO L225 Difference]: With dead ends: 47123 [2019-12-07 10:38:00,376 INFO L226 Difference]: Without dead ends: 41581 [2019-12-07 10:38:00,376 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 10:38:00,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41581 states. [2019-12-07 10:38:00,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41581 to 41581. [2019-12-07 10:38:00,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41581 states. [2019-12-07 10:38:01,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41581 states to 41581 states and 136155 transitions. [2019-12-07 10:38:01,029 INFO L78 Accepts]: Start accepts. Automaton has 41581 states and 136155 transitions. Word has length 22 [2019-12-07 10:38:01,029 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:38:01,029 INFO L462 AbstractCegarLoop]: Abstraction has 41581 states and 136155 transitions. [2019-12-07 10:38:01,029 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 10:38:01,029 INFO L276 IsEmpty]: Start isEmpty. Operand 41581 states and 136155 transitions. [2019-12-07 10:38:01,040 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 10:38:01,041 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:38:01,041 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:38:01,041 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:38:01,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:38:01,041 INFO L82 PathProgramCache]: Analyzing trace with hash 680964803, now seen corresponding path program 1 times [2019-12-07 10:38:01,041 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:38:01,041 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [576738047] [2019-12-07 10:38:01,041 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:38:01,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:38:01,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:38:01,136 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [576738047] [2019-12-07 10:38:01,136 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:38:01,137 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 10:38:01,137 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [207407194] [2019-12-07 10:38:01,137 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 10:38:01,137 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:38:01,137 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 10:38:01,137 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 10:38:01,138 INFO L87 Difference]: Start difference. First operand 41581 states and 136155 transitions. Second operand 5 states. [2019-12-07 10:38:01,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:38:01,504 INFO L93 Difference]: Finished difference Result 56318 states and 180086 transitions. [2019-12-07 10:38:01,504 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 10:38:01,504 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2019-12-07 10:38:01,504 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:38:01,588 INFO L225 Difference]: With dead ends: 56318 [2019-12-07 10:38:01,588 INFO L226 Difference]: Without dead ends: 56318 [2019-12-07 10:38:01,588 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 0 SyntacticMatches, 4 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 10:38:01,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56318 states. [2019-12-07 10:38:02,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56318 to 46548. [2019-12-07 10:38:02,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46548 states. [2019-12-07 10:38:02,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46548 states to 46548 states and 151553 transitions. [2019-12-07 10:38:02,711 INFO L78 Accepts]: Start accepts. Automaton has 46548 states and 151553 transitions. Word has length 28 [2019-12-07 10:38:02,711 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:38:02,711 INFO L462 AbstractCegarLoop]: Abstraction has 46548 states and 151553 transitions. [2019-12-07 10:38:02,711 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 10:38:02,711 INFO L276 IsEmpty]: Start isEmpty. Operand 46548 states and 151553 transitions. [2019-12-07 10:38:02,723 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 10:38:02,723 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:38:02,723 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:38:02,723 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:38:02,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:38:02,723 INFO L82 PathProgramCache]: Analyzing trace with hash 1665046243, now seen corresponding path program 1 times [2019-12-07 10:38:02,723 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:38:02,723 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069463709] [2019-12-07 10:38:02,724 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:38:02,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:38:02,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:38:02,772 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2069463709] [2019-12-07 10:38:02,772 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:38:02,773 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 10:38:02,773 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [931305761] [2019-12-07 10:38:02,773 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 10:38:02,773 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:38:02,773 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 10:38:02,773 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-12-07 10:38:02,774 INFO L87 Difference]: Start difference. First operand 46548 states and 151553 transitions. Second operand 6 states. [2019-12-07 10:38:02,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:38:02,863 INFO L93 Difference]: Finished difference Result 15498 states and 48783 transitions. [2019-12-07 10:38:02,863 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 10:38:02,863 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 28 [2019-12-07 10:38:02,864 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:38:02,881 INFO L225 Difference]: With dead ends: 15498 [2019-12-07 10:38:02,881 INFO L226 Difference]: Without dead ends: 14145 [2019-12-07 10:38:02,881 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-12-07 10:38:02,930 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14145 states. [2019-12-07 10:38:03,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14145 to 13865. [2019-12-07 10:38:03,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13865 states. [2019-12-07 10:38:03,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13865 states to 13865 states and 43922 transitions. [2019-12-07 10:38:03,081 INFO L78 Accepts]: Start accepts. Automaton has 13865 states and 43922 transitions. Word has length 28 [2019-12-07 10:38:03,081 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:38:03,081 INFO L462 AbstractCegarLoop]: Abstraction has 13865 states and 43922 transitions. [2019-12-07 10:38:03,081 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 10:38:03,081 INFO L276 IsEmpty]: Start isEmpty. Operand 13865 states and 43922 transitions. [2019-12-07 10:38:03,098 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-12-07 10:38:03,098 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:38:03,098 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:38:03,098 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:38:03,099 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:38:03,099 INFO L82 PathProgramCache]: Analyzing trace with hash -1672770928, now seen corresponding path program 1 times [2019-12-07 10:38:03,099 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:38:03,099 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934137366] [2019-12-07 10:38:03,099 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:38:03,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:38:03,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:38:03,159 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934137366] [2019-12-07 10:38:03,159 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:38:03,159 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 10:38:03,159 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1901156901] [2019-12-07 10:38:03,160 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 10:38:03,160 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:38:03,160 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 10:38:03,160 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 10:38:03,160 INFO L87 Difference]: Start difference. First operand 13865 states and 43922 transitions. Second operand 7 states. [2019-12-07 10:38:03,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:38:03,248 INFO L93 Difference]: Finished difference Result 11702 states and 38970 transitions. [2019-12-07 10:38:03,248 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 10:38:03,248 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 40 [2019-12-07 10:38:03,248 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:38:03,262 INFO L225 Difference]: With dead ends: 11702 [2019-12-07 10:38:03,263 INFO L226 Difference]: Without dead ends: 11593 [2019-12-07 10:38:03,263 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2019-12-07 10:38:03,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11593 states. [2019-12-07 10:38:03,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11593 to 10095. [2019-12-07 10:38:03,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10095 states. [2019-12-07 10:38:03,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10095 states to 10095 states and 33950 transitions. [2019-12-07 10:38:03,418 INFO L78 Accepts]: Start accepts. Automaton has 10095 states and 33950 transitions. Word has length 40 [2019-12-07 10:38:03,418 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:38:03,418 INFO L462 AbstractCegarLoop]: Abstraction has 10095 states and 33950 transitions. [2019-12-07 10:38:03,419 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 10:38:03,419 INFO L276 IsEmpty]: Start isEmpty. Operand 10095 states and 33950 transitions. [2019-12-07 10:38:03,432 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 10:38:03,432 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:38:03,432 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:38:03,432 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:38:03,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:38:03,433 INFO L82 PathProgramCache]: Analyzing trace with hash 1196827384, now seen corresponding path program 1 times [2019-12-07 10:38:03,433 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:38:03,433 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [455085535] [2019-12-07 10:38:03,433 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:38:03,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:38:03,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:38:03,480 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [455085535] [2019-12-07 10:38:03,480 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:38:03,480 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 10:38:03,480 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1042153844] [2019-12-07 10:38:03,480 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 10:38:03,480 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:38:03,481 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 10:38:03,481 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 10:38:03,481 INFO L87 Difference]: Start difference. First operand 10095 states and 33950 transitions. Second operand 3 states. [2019-12-07 10:38:03,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:38:03,534 INFO L93 Difference]: Finished difference Result 10110 states and 33968 transitions. [2019-12-07 10:38:03,534 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 10:38:03,534 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 10:38:03,535 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:38:03,548 INFO L225 Difference]: With dead ends: 10110 [2019-12-07 10:38:03,548 INFO L226 Difference]: Without dead ends: 10110 [2019-12-07 10:38:03,549 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 10:38:03,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10110 states. [2019-12-07 10:38:03,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10110 to 10105. [2019-12-07 10:38:03,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10105 states. [2019-12-07 10:38:03,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10105 states to 10105 states and 33962 transitions. [2019-12-07 10:38:03,698 INFO L78 Accepts]: Start accepts. Automaton has 10105 states and 33962 transitions. Word has length 67 [2019-12-07 10:38:03,698 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:38:03,698 INFO L462 AbstractCegarLoop]: Abstraction has 10105 states and 33962 transitions. [2019-12-07 10:38:03,699 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 10:38:03,699 INFO L276 IsEmpty]: Start isEmpty. Operand 10105 states and 33962 transitions. [2019-12-07 10:38:03,709 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 10:38:03,709 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:38:03,709 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:38:03,709 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:38:03,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:38:03,709 INFO L82 PathProgramCache]: Analyzing trace with hash 1012782721, now seen corresponding path program 1 times [2019-12-07 10:38:03,710 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:38:03,710 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1148714535] [2019-12-07 10:38:03,710 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:38:03,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:38:03,763 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:38:03,763 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1148714535] [2019-12-07 10:38:03,763 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:38:03,763 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 10:38:03,763 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [879300161] [2019-12-07 10:38:03,763 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 10:38:03,764 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:38:03,764 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 10:38:03,764 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 10:38:03,764 INFO L87 Difference]: Start difference. First operand 10105 states and 33962 transitions. Second operand 5 states. [2019-12-07 10:38:03,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:38:03,989 INFO L93 Difference]: Finished difference Result 14800 states and 49449 transitions. [2019-12-07 10:38:03,989 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 10:38:03,989 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 67 [2019-12-07 10:38:03,989 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:38:04,008 INFO L225 Difference]: With dead ends: 14800 [2019-12-07 10:38:04,009 INFO L226 Difference]: Without dead ends: 14800 [2019-12-07 10:38:04,009 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 10:38:04,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14800 states. [2019-12-07 10:38:04,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14800 to 11665. [2019-12-07 10:38:04,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11665 states. [2019-12-07 10:38:04,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11665 states to 11665 states and 39346 transitions. [2019-12-07 10:38:04,198 INFO L78 Accepts]: Start accepts. Automaton has 11665 states and 39346 transitions. Word has length 67 [2019-12-07 10:38:04,198 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:38:04,198 INFO L462 AbstractCegarLoop]: Abstraction has 11665 states and 39346 transitions. [2019-12-07 10:38:04,198 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 10:38:04,198 INFO L276 IsEmpty]: Start isEmpty. Operand 11665 states and 39346 transitions. [2019-12-07 10:38:04,211 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 10:38:04,211 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:38:04,211 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:38:04,211 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:38:04,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:38:04,211 INFO L82 PathProgramCache]: Analyzing trace with hash 1925623137, now seen corresponding path program 2 times [2019-12-07 10:38:04,211 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:38:04,212 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1173864732] [2019-12-07 10:38:04,212 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:38:04,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:38:04,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:38:04,286 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1173864732] [2019-12-07 10:38:04,286 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:38:04,286 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 10:38:04,286 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2075879277] [2019-12-07 10:38:04,287 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 10:38:04,287 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:38:04,287 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 10:38:04,287 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 10:38:04,287 INFO L87 Difference]: Start difference. First operand 11665 states and 39346 transitions. Second operand 6 states. [2019-12-07 10:38:04,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:38:04,633 INFO L93 Difference]: Finished difference Result 19377 states and 65098 transitions. [2019-12-07 10:38:04,634 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 10:38:04,634 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 67 [2019-12-07 10:38:04,634 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:38:04,658 INFO L225 Difference]: With dead ends: 19377 [2019-12-07 10:38:04,658 INFO L226 Difference]: Without dead ends: 19377 [2019-12-07 10:38:04,658 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-12-07 10:38:04,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19377 states. [2019-12-07 10:38:04,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19377 to 12669. [2019-12-07 10:38:04,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12669 states. [2019-12-07 10:38:04,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12669 states to 12669 states and 42832 transitions. [2019-12-07 10:38:04,891 INFO L78 Accepts]: Start accepts. Automaton has 12669 states and 42832 transitions. Word has length 67 [2019-12-07 10:38:04,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:38:04,892 INFO L462 AbstractCegarLoop]: Abstraction has 12669 states and 42832 transitions. [2019-12-07 10:38:04,892 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 10:38:04,892 INFO L276 IsEmpty]: Start isEmpty. Operand 12669 states and 42832 transitions. [2019-12-07 10:38:04,905 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 10:38:04,905 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:38:04,905 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:38:04,906 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:38:04,906 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:38:04,906 INFO L82 PathProgramCache]: Analyzing trace with hash 1157078727, now seen corresponding path program 3 times [2019-12-07 10:38:04,906 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:38:04,906 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2015787063] [2019-12-07 10:38:04,906 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:38:04,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:38:04,982 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:38:04,983 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2015787063] [2019-12-07 10:38:04,983 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:38:04,983 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 10:38:04,983 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707474072] [2019-12-07 10:38:04,983 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 10:38:04,983 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:38:04,983 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 10:38:04,983 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 10:38:04,984 INFO L87 Difference]: Start difference. First operand 12669 states and 42832 transitions. Second operand 6 states. [2019-12-07 10:38:05,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:38:05,313 INFO L93 Difference]: Finished difference Result 17229 states and 57451 transitions. [2019-12-07 10:38:05,314 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 10:38:05,314 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 67 [2019-12-07 10:38:05,314 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:38:05,336 INFO L225 Difference]: With dead ends: 17229 [2019-12-07 10:38:05,336 INFO L226 Difference]: Without dead ends: 17229 [2019-12-07 10:38:05,336 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 6 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-12-07 10:38:05,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17229 states. [2019-12-07 10:38:05,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17229 to 14027. [2019-12-07 10:38:05,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14027 states. [2019-12-07 10:38:05,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14027 states to 14027 states and 47321 transitions. [2019-12-07 10:38:05,576 INFO L78 Accepts]: Start accepts. Automaton has 14027 states and 47321 transitions. Word has length 67 [2019-12-07 10:38:05,577 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:38:05,577 INFO L462 AbstractCegarLoop]: Abstraction has 14027 states and 47321 transitions. [2019-12-07 10:38:05,577 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 10:38:05,577 INFO L276 IsEmpty]: Start isEmpty. Operand 14027 states and 47321 transitions. [2019-12-07 10:38:05,592 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 10:38:05,592 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:38:05,593 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:38:05,593 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:38:05,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:38:05,593 INFO L82 PathProgramCache]: Analyzing trace with hash -153275837, now seen corresponding path program 4 times [2019-12-07 10:38:05,593 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:38:05,593 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1096824747] [2019-12-07 10:38:05,593 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:38:05,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:38:05,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:38:05,653 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1096824747] [2019-12-07 10:38:05,653 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:38:05,653 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 10:38:05,653 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [902060714] [2019-12-07 10:38:05,653 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 10:38:05,653 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:38:05,653 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 10:38:05,653 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 10:38:05,653 INFO L87 Difference]: Start difference. First operand 14027 states and 47321 transitions. Second operand 7 states. [2019-12-07 10:38:06,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:38:06,078 INFO L93 Difference]: Finished difference Result 20701 states and 69432 transitions. [2019-12-07 10:38:06,078 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 10:38:06,078 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 67 [2019-12-07 10:38:06,078 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:38:06,105 INFO L225 Difference]: With dead ends: 20701 [2019-12-07 10:38:06,105 INFO L226 Difference]: Without dead ends: 20701 [2019-12-07 10:38:06,105 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 7 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2019-12-07 10:38:06,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20701 states. [2019-12-07 10:38:06,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20701 to 14657. [2019-12-07 10:38:06,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14657 states. [2019-12-07 10:38:06,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14657 states to 14657 states and 49450 transitions. [2019-12-07 10:38:06,373 INFO L78 Accepts]: Start accepts. Automaton has 14657 states and 49450 transitions. Word has length 67 [2019-12-07 10:38:06,373 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:38:06,373 INFO L462 AbstractCegarLoop]: Abstraction has 14657 states and 49450 transitions. [2019-12-07 10:38:06,373 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 10:38:06,374 INFO L276 IsEmpty]: Start isEmpty. Operand 14657 states and 49450 transitions. [2019-12-07 10:38:06,390 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 10:38:06,390 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:38:06,390 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:38:06,390 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:38:06,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:38:06,390 INFO L82 PathProgramCache]: Analyzing trace with hash -437107389, now seen corresponding path program 5 times [2019-12-07 10:38:06,390 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:38:06,391 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097959487] [2019-12-07 10:38:06,391 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:38:06,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:38:06,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:38:06,445 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1097959487] [2019-12-07 10:38:06,445 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:38:06,445 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 10:38:06,446 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1674225157] [2019-12-07 10:38:06,446 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 10:38:06,446 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:38:06,446 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 10:38:06,446 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 10:38:06,446 INFO L87 Difference]: Start difference. First operand 14657 states and 49450 transitions. Second operand 6 states. [2019-12-07 10:38:06,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:38:06,790 INFO L93 Difference]: Finished difference Result 19098 states and 63293 transitions. [2019-12-07 10:38:06,790 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 10:38:06,790 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 67 [2019-12-07 10:38:06,790 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:38:06,814 INFO L225 Difference]: With dead ends: 19098 [2019-12-07 10:38:06,814 INFO L226 Difference]: Without dead ends: 19098 [2019-12-07 10:38:06,815 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2019-12-07 10:38:06,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19098 states. [2019-12-07 10:38:07,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19098 to 14717. [2019-12-07 10:38:07,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14717 states. [2019-12-07 10:38:07,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14717 states to 14717 states and 49160 transitions. [2019-12-07 10:38:07,077 INFO L78 Accepts]: Start accepts. Automaton has 14717 states and 49160 transitions. Word has length 67 [2019-12-07 10:38:07,077 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:38:07,077 INFO L462 AbstractCegarLoop]: Abstraction has 14717 states and 49160 transitions. [2019-12-07 10:38:07,077 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 10:38:07,077 INFO L276 IsEmpty]: Start isEmpty. Operand 14717 states and 49160 transitions. [2019-12-07 10:38:07,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 10:38:07,092 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:38:07,092 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:38:07,092 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:38:07,092 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:38:07,092 INFO L82 PathProgramCache]: Analyzing trace with hash -1100636955, now seen corresponding path program 6 times [2019-12-07 10:38:07,092 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:38:07,092 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [732612878] [2019-12-07 10:38:07,093 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:38:07,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:38:07,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:38:07,189 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [732612878] [2019-12-07 10:38:07,189 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:38:07,189 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 10:38:07,189 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2015046922] [2019-12-07 10:38:07,190 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 10:38:07,190 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:38:07,190 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 10:38:07,190 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 10:38:07,190 INFO L87 Difference]: Start difference. First operand 14717 states and 49160 transitions. Second operand 7 states. [2019-12-07 10:38:07,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:38:07,357 INFO L93 Difference]: Finished difference Result 26357 states and 85597 transitions. [2019-12-07 10:38:07,357 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 10:38:07,357 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 67 [2019-12-07 10:38:07,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:38:07,382 INFO L225 Difference]: With dead ends: 26357 [2019-12-07 10:38:07,382 INFO L226 Difference]: Without dead ends: 18571 [2019-12-07 10:38:07,383 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=40, Invalid=70, Unknown=0, NotChecked=0, Total=110 [2019-12-07 10:38:07,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18571 states. [2019-12-07 10:38:07,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18571 to 13495. [2019-12-07 10:38:07,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13495 states. [2019-12-07 10:38:07,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13495 states to 13495 states and 44481 transitions. [2019-12-07 10:38:07,615 INFO L78 Accepts]: Start accepts. Automaton has 13495 states and 44481 transitions. Word has length 67 [2019-12-07 10:38:07,615 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:38:07,615 INFO L462 AbstractCegarLoop]: Abstraction has 13495 states and 44481 transitions. [2019-12-07 10:38:07,615 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 10:38:07,616 INFO L276 IsEmpty]: Start isEmpty. Operand 13495 states and 44481 transitions. [2019-12-07 10:38:07,629 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 10:38:07,629 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:38:07,629 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:38:07,629 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:38:07,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:38:07,629 INFO L82 PathProgramCache]: Analyzing trace with hash 280568553, now seen corresponding path program 7 times [2019-12-07 10:38:07,629 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:38:07,630 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [258075680] [2019-12-07 10:38:07,630 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:38:07,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:38:07,658 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:38:07,658 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [258075680] [2019-12-07 10:38:07,659 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:38:07,659 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 10:38:07,659 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1490555125] [2019-12-07 10:38:07,659 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 10:38:07,659 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:38:07,659 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 10:38:07,659 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 10:38:07,660 INFO L87 Difference]: Start difference. First operand 13495 states and 44481 transitions. Second operand 3 states. [2019-12-07 10:38:07,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:38:07,701 INFO L93 Difference]: Finished difference Result 12276 states and 40027 transitions. [2019-12-07 10:38:07,701 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 10:38:07,701 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 10:38:07,701 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:38:07,716 INFO L225 Difference]: With dead ends: 12276 [2019-12-07 10:38:07,716 INFO L226 Difference]: Without dead ends: 12276 [2019-12-07 10:38:07,716 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 10:38:07,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12276 states. [2019-12-07 10:38:07,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12276 to 12024. [2019-12-07 10:38:07,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12024 states. [2019-12-07 10:38:07,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12024 states to 12024 states and 39209 transitions. [2019-12-07 10:38:07,900 INFO L78 Accepts]: Start accepts. Automaton has 12024 states and 39209 transitions. Word has length 67 [2019-12-07 10:38:07,900 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:38:07,900 INFO L462 AbstractCegarLoop]: Abstraction has 12024 states and 39209 transitions. [2019-12-07 10:38:07,900 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 10:38:07,900 INFO L276 IsEmpty]: Start isEmpty. Operand 12024 states and 39209 transitions. [2019-12-07 10:38:07,910 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 10:38:07,910 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:38:07,910 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:38:07,910 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:38:07,911 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:38:07,911 INFO L82 PathProgramCache]: Analyzing trace with hash 469346632, now seen corresponding path program 1 times [2019-12-07 10:38:07,911 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:38:07,911 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665033060] [2019-12-07 10:38:07,911 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:38:07,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:38:08,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:38:08,010 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665033060] [2019-12-07 10:38:08,010 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:38:08,011 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 10:38:08,011 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2076463080] [2019-12-07 10:38:08,011 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 10:38:08,011 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:38:08,011 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 10:38:08,011 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2019-12-07 10:38:08,012 INFO L87 Difference]: Start difference. First operand 12024 states and 39209 transitions. Second operand 7 states. [2019-12-07 10:38:08,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:38:08,304 INFO L93 Difference]: Finished difference Result 17247 states and 55813 transitions. [2019-12-07 10:38:08,304 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 10:38:08,304 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 68 [2019-12-07 10:38:08,304 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:38:08,325 INFO L225 Difference]: With dead ends: 17247 [2019-12-07 10:38:08,325 INFO L226 Difference]: Without dead ends: 17247 [2019-12-07 10:38:08,325 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 1 SyntacticMatches, 5 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=47, Invalid=109, Unknown=0, NotChecked=0, Total=156 [2019-12-07 10:38:08,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17247 states. [2019-12-07 10:38:08,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17247 to 11877. [2019-12-07 10:38:08,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11877 states. [2019-12-07 10:38:08,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11877 states to 11877 states and 38733 transitions. [2019-12-07 10:38:08,536 INFO L78 Accepts]: Start accepts. Automaton has 11877 states and 38733 transitions. Word has length 68 [2019-12-07 10:38:08,537 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:38:08,537 INFO L462 AbstractCegarLoop]: Abstraction has 11877 states and 38733 transitions. [2019-12-07 10:38:08,537 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 10:38:08,537 INFO L276 IsEmpty]: Start isEmpty. Operand 11877 states and 38733 transitions. [2019-12-07 10:38:08,548 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 10:38:08,548 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:38:08,548 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:38:08,549 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:38:08,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:38:08,549 INFO L82 PathProgramCache]: Analyzing trace with hash 597575012, now seen corresponding path program 2 times [2019-12-07 10:38:08,549 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:38:08,549 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1414051391] [2019-12-07 10:38:08,549 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:38:08,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:38:08,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:38:08,607 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1414051391] [2019-12-07 10:38:08,607 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:38:08,607 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 10:38:08,608 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [879627590] [2019-12-07 10:38:08,608 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 10:38:08,608 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:38:08,608 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 10:38:08,608 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 10:38:08,608 INFO L87 Difference]: Start difference. First operand 11877 states and 38733 transitions. Second operand 7 states. [2019-12-07 10:38:09,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:38:09,182 INFO L93 Difference]: Finished difference Result 17374 states and 56335 transitions. [2019-12-07 10:38:09,183 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 10:38:09,183 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 68 [2019-12-07 10:38:09,184 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:38:09,216 INFO L225 Difference]: With dead ends: 17374 [2019-12-07 10:38:09,216 INFO L226 Difference]: Without dead ends: 17374 [2019-12-07 10:38:09,216 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 9 SyntacticMatches, 2 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=55, Invalid=155, Unknown=0, NotChecked=0, Total=210 [2019-12-07 10:38:09,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17374 states. [2019-12-07 10:38:09,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17374 to 11520. [2019-12-07 10:38:09,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11520 states. [2019-12-07 10:38:09,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11520 states to 11520 states and 37643 transitions. [2019-12-07 10:38:09,427 INFO L78 Accepts]: Start accepts. Automaton has 11520 states and 37643 transitions. Word has length 68 [2019-12-07 10:38:09,427 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:38:09,427 INFO L462 AbstractCegarLoop]: Abstraction has 11520 states and 37643 transitions. [2019-12-07 10:38:09,427 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 10:38:09,427 INFO L276 IsEmpty]: Start isEmpty. Operand 11520 states and 37643 transitions. [2019-12-07 10:38:09,437 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 10:38:09,437 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:38:09,438 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:38:09,438 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:38:09,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:38:09,438 INFO L82 PathProgramCache]: Analyzing trace with hash -2095319094, now seen corresponding path program 3 times [2019-12-07 10:38:09,438 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:38:09,438 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577980975] [2019-12-07 10:38:09,438 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:38:09,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:38:09,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:38:09,465 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [577980975] [2019-12-07 10:38:09,465 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:38:09,466 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 10:38:09,466 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [274763504] [2019-12-07 10:38:09,466 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 10:38:09,466 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:38:09,466 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 10:38:09,466 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 10:38:09,466 INFO L87 Difference]: Start difference. First operand 11520 states and 37643 transitions. Second operand 3 states. [2019-12-07 10:38:09,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:38:09,501 INFO L93 Difference]: Finished difference Result 10462 states and 33744 transitions. [2019-12-07 10:38:09,502 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 10:38:09,502 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 68 [2019-12-07 10:38:09,502 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:38:09,514 INFO L225 Difference]: With dead ends: 10462 [2019-12-07 10:38:09,514 INFO L226 Difference]: Without dead ends: 10462 [2019-12-07 10:38:09,514 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 10:38:09,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10462 states. [2019-12-07 10:38:09,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10462 to 10462. [2019-12-07 10:38:09,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10462 states. [2019-12-07 10:38:09,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10462 states to 10462 states and 33744 transitions. [2019-12-07 10:38:09,654 INFO L78 Accepts]: Start accepts. Automaton has 10462 states and 33744 transitions. Word has length 68 [2019-12-07 10:38:09,654 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:38:09,654 INFO L462 AbstractCegarLoop]: Abstraction has 10462 states and 33744 transitions. [2019-12-07 10:38:09,654 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 10:38:09,654 INFO L276 IsEmpty]: Start isEmpty. Operand 10462 states and 33744 transitions. [2019-12-07 10:38:09,663 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-12-07 10:38:09,663 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:38:09,663 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:38:09,663 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:38:09,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:38:09,664 INFO L82 PathProgramCache]: Analyzing trace with hash 1254968342, now seen corresponding path program 1 times [2019-12-07 10:38:09,664 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:38:09,664 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445537505] [2019-12-07 10:38:09,664 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:38:09,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:38:09,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:38:09,766 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [445537505] [2019-12-07 10:38:09,766 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:38:09,766 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 10:38:09,766 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1481349733] [2019-12-07 10:38:09,767 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 10:38:09,767 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:38:09,767 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 10:38:09,767 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2019-12-07 10:38:09,767 INFO L87 Difference]: Start difference. First operand 10462 states and 33744 transitions. Second operand 9 states. [2019-12-07 10:38:10,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:38:10,302 INFO L93 Difference]: Finished difference Result 19165 states and 61581 transitions. [2019-12-07 10:38:10,302 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 10:38:10,303 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 69 [2019-12-07 10:38:10,303 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:38:10,326 INFO L225 Difference]: With dead ends: 19165 [2019-12-07 10:38:10,326 INFO L226 Difference]: Without dead ends: 19165 [2019-12-07 10:38:10,326 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 9 SyntacticMatches, 3 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=74, Invalid=198, Unknown=0, NotChecked=0, Total=272 [2019-12-07 10:38:10,378 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19165 states. [2019-12-07 10:38:10,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19165 to 11092. [2019-12-07 10:38:10,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11092 states. [2019-12-07 10:38:10,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11092 states to 11092 states and 35898 transitions. [2019-12-07 10:38:10,540 INFO L78 Accepts]: Start accepts. Automaton has 11092 states and 35898 transitions. Word has length 69 [2019-12-07 10:38:10,541 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:38:10,541 INFO L462 AbstractCegarLoop]: Abstraction has 11092 states and 35898 transitions. [2019-12-07 10:38:10,541 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 10:38:10,541 INFO L276 IsEmpty]: Start isEmpty. Operand 11092 states and 35898 transitions. [2019-12-07 10:38:10,551 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-12-07 10:38:10,551 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:38:10,551 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:38:10,551 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:38:10,551 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:38:10,551 INFO L82 PathProgramCache]: Analyzing trace with hash -38588582, now seen corresponding path program 2 times [2019-12-07 10:38:10,551 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:38:10,551 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [913166596] [2019-12-07 10:38:10,552 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:38:10,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:38:10,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:38:10,583 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [913166596] [2019-12-07 10:38:10,583 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:38:10,583 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 10:38:10,583 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1371081288] [2019-12-07 10:38:10,583 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 10:38:10,584 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:38:10,584 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 10:38:10,584 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 10:38:10,584 INFO L87 Difference]: Start difference. First operand 11092 states and 35898 transitions. Second operand 3 states. [2019-12-07 10:38:10,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:38:10,637 INFO L93 Difference]: Finished difference Result 11092 states and 35897 transitions. [2019-12-07 10:38:10,637 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 10:38:10,637 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 69 [2019-12-07 10:38:10,637 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:38:10,650 INFO L225 Difference]: With dead ends: 11092 [2019-12-07 10:38:10,650 INFO L226 Difference]: Without dead ends: 11092 [2019-12-07 10:38:10,651 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 10:38:10,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11092 states. [2019-12-07 10:38:10,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11092 to 7062. [2019-12-07 10:38:10,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7062 states. [2019-12-07 10:38:10,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7062 states to 7062 states and 22907 transitions. [2019-12-07 10:38:10,805 INFO L78 Accepts]: Start accepts. Automaton has 7062 states and 22907 transitions. Word has length 69 [2019-12-07 10:38:10,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:38:10,805 INFO L462 AbstractCegarLoop]: Abstraction has 7062 states and 22907 transitions. [2019-12-07 10:38:10,805 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 10:38:10,805 INFO L276 IsEmpty]: Start isEmpty. Operand 7062 states and 22907 transitions. [2019-12-07 10:38:10,811 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 10:38:10,811 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:38:10,812 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:38:10,812 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:38:10,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:38:10,812 INFO L82 PathProgramCache]: Analyzing trace with hash -1196877625, now seen corresponding path program 1 times [2019-12-07 10:38:10,812 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:38:10,812 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1746373759] [2019-12-07 10:38:10,812 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:38:10,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 10:38:10,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 10:38:10,884 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1746373759] [2019-12-07 10:38:10,885 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 10:38:10,885 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 10:38:10,885 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1474864215] [2019-12-07 10:38:10,885 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 10:38:10,885 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 10:38:10,886 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 10:38:10,886 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 10:38:10,886 INFO L87 Difference]: Start difference. First operand 7062 states and 22907 transitions. Second operand 6 states. [2019-12-07 10:38:10,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 10:38:10,948 INFO L93 Difference]: Finished difference Result 10118 states and 31364 transitions. [2019-12-07 10:38:10,948 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 10:38:10,948 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 70 [2019-12-07 10:38:10,948 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 10:38:10,951 INFO L225 Difference]: With dead ends: 10118 [2019-12-07 10:38:10,951 INFO L226 Difference]: Without dead ends: 3477 [2019-12-07 10:38:10,951 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 10:38:10,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3477 states. [2019-12-07 10:38:10,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3477 to 3477. [2019-12-07 10:38:10,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3477 states. [2019-12-07 10:38:10,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3477 states to 3477 states and 9623 transitions. [2019-12-07 10:38:10,994 INFO L78 Accepts]: Start accepts. Automaton has 3477 states and 9623 transitions. Word has length 70 [2019-12-07 10:38:10,994 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 10:38:10,994 INFO L462 AbstractCegarLoop]: Abstraction has 3477 states and 9623 transitions. [2019-12-07 10:38:10,994 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 10:38:10,994 INFO L276 IsEmpty]: Start isEmpty. Operand 3477 states and 9623 transitions. [2019-12-07 10:38:10,996 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 10:38:10,996 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 10:38:10,997 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 10:38:10,997 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 10:38:10,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 10:38:10,997 INFO L82 PathProgramCache]: Analyzing trace with hash -1078025367, now seen corresponding path program 2 times [2019-12-07 10:38:10,997 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 10:38:10,997 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [283392691] [2019-12-07 10:38:10,997 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 10:38:11,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 10:38:11,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 10:38:11,076 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 10:38:11,076 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 10:38:11,079 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [876] [876] ULTIMATE.startENTRY-->L833: Formula: (let ((.cse0 (store |v_#valid_73| 0 0))) (and (= v_~x~0_55 0) (= (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t781~0.base_24| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t781~0.base_24|) |v_ULTIMATE.start_main_~#t781~0.offset_18| 0)) |v_#memory_int_27|) (= v_~a~0_26 0) (= 0 v_~y$read_delayed_var~0.offset_7) (= v_~y$r_buff1_thd0~0_273 0) (= v_~y$r_buff0_thd1~0_30 0) (= v_~y$r_buff0_thd4~0_83 0) (= v_~main$tmp_guard0~0_39 0) (= 0 v_~y$r_buff1_thd1~0_94) (= 0 v_~y$r_buff0_thd3~0_170) (= v_~y~0_170 0) (= 0 v_~__unbuffered_p3_EBX~0_25) (= v_~y$read_delayed~0_6 0) (= v_~y$r_buff0_thd0~0_357 0) (= |v_#length_31| (store |v_#length_32| |v_ULTIMATE.start_main_~#t781~0.base_24| 4)) (= v_~y$mem_tmp~0_18 0) (= 0 v_~y$flush_delayed~0_35) (= 0 v_~__unbuffered_p3_EAX~0_21) (= v_~__unbuffered_cnt~0_136 0) (= v_~y$w_buff1_used~0_387 0) (= 0 v_~y$r_buff1_thd2~0_158) (= 0 |v_#NULL.base_4|) (= v_~y$w_buff1~0_158 0) (= 0 v_~y$read_delayed_var~0.base_7) (< 0 |v_#StackHeapBarrier_20|) (= v_~y$r_buff0_thd2~0_97 0) (= |v_ULTIMATE.start_main_~#t781~0.offset_18| 0) (= |v_#valid_71| (store .cse0 |v_ULTIMATE.start_main_~#t781~0.base_24| 1)) (= v_~z~0_109 0) (= 0 v_~__unbuffered_p0_EAX~0_27) (= 0 v_~y$w_buff0~0_171) (= 0 v_~y$r_buff1_thd4~0_149) (= |v_#NULL.offset_4| 0) (= v_~main$tmp_guard1~0_24 0) (= 0 v_~weak$$choice0~0_13) (= 0 v_~y$r_buff1_thd3~0_146) (= v_~weak$$choice2~0_110 0) (< |v_#StackHeapBarrier_20| |v_ULTIMATE.start_main_~#t781~0.base_24|) (= (select .cse0 |v_ULTIMATE.start_main_~#t781~0.base_24|) 0) (= v_~y$w_buff0_used~0_739 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_20|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_28|, #length=|v_#length_32|} OutVars{ULTIMATE.start_main_~#t781~0.offset=|v_ULTIMATE.start_main_~#t781~0.offset_18|, ULTIMATE.start_main_#t~nondet32=|v_ULTIMATE.start_main_#t~nondet32_21|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_33|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_30|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_28|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_33|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_284|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_37|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_41|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ULTIMATE.start_main_~#t784~0.base=|v_ULTIMATE.start_main_~#t784~0.base_20|, ~a~0=v_~a~0_26, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_29|, ~y$mem_tmp~0=v_~y$mem_tmp~0_18, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_27, ULTIMATE.start_main_~#t781~0.base=|v_ULTIMATE.start_main_~#t781~0.base_24|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_146, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_30, ULTIMATE.start_main_~#t784~0.offset=|v_ULTIMATE.start_main_~#t784~0.offset_16|, ~y$flush_delayed~0=v_~y$flush_delayed~0_35, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_21, #length=|v_#length_31|, ULTIMATE.start_main_~#t782~0.base=|v_ULTIMATE.start_main_~#t782~0.base_23|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_54|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_28|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_25|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_55|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_20|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_46|, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_149, ~y$w_buff1~0=v_~y$w_buff1~0_158, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_97, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_136, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_273, ~x~0=v_~x~0_55, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_739, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_27|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_29|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_40|, ULTIMATE.start_main_~#t783~0.base=|v_ULTIMATE.start_main_~#t783~0.base_20|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_24, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_25|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_36|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_158|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_39|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_94, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_33|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_51|, ~y$w_buff0~0=v_~y$w_buff0~0_171, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_170, ~y~0=v_~y~0_170, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_9|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_9|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_46|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_52|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_39, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_25, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_32|, ULTIMATE.start_main_~#t783~0.offset=|v_ULTIMATE.start_main_~#t783~0.offset_17|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_103|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_158, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_83, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_154|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_357, #valid=|v_#valid_71|, #memory_int=|v_#memory_int_27|, ~z~0=v_~z~0_109, ~weak$$choice2~0=v_~weak$$choice2~0_110, ULTIMATE.start_main_~#t782~0.offset=|v_ULTIMATE.start_main_~#t782~0.offset_18|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_387} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t781~0.offset, ULTIMATE.start_main_#t~nondet32, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ~y$read_delayed~0, ULTIMATE.start_main_~#t784~0.base, ~a~0, ULTIMATE.start_main_#t~ite52, ~y$mem_tmp~0, ~__unbuffered_p0_EAX~0, ULTIMATE.start_main_~#t781~0.base, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ULTIMATE.start_main_~#t784~0.offset, ~y$flush_delayed~0, ~__unbuffered_p3_EAX~0, #length, ULTIMATE.start_main_~#t782~0.base, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$r_buff1_thd4~0, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_~#t783~0.base, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite51, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~__unbuffered_p3_EBX~0, ULTIMATE.start_main_#t~ite53, ULTIMATE.start_main_~#t783~0.offset, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ~y$r_buff0_thd4~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ULTIMATE.start_main_~#t782~0.offset, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 10:38:11,079 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L833-1-->L835: Formula: (and (= (select |v_#valid_43| |v_ULTIMATE.start_main_~#t782~0.base_10|) 0) (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t782~0.base_10| 4)) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t782~0.base_10|) (= |v_#valid_42| (store |v_#valid_43| |v_ULTIMATE.start_main_~#t782~0.base_10| 1)) (not (= |v_ULTIMATE.start_main_~#t782~0.base_10| 0)) (= |v_#memory_int_15| (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t782~0.base_10| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t782~0.base_10|) |v_ULTIMATE.start_main_~#t782~0.offset_9| 1))) (= |v_ULTIMATE.start_main_~#t782~0.offset_9| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_43|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, ULTIMATE.start_main_~#t782~0.base=|v_ULTIMATE.start_main_~#t782~0.base_10|, #valid=|v_#valid_42|, #memory_int=|v_#memory_int_15|, #length=|v_#length_19|, ULTIMATE.start_main_~#t782~0.offset=|v_ULTIMATE.start_main_~#t782~0.offset_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t782~0.base, #valid, #memory_int, #length, ULTIMATE.start_main_~#t782~0.offset] because there is no mapped edge [2019-12-07 10:38:11,080 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [835] [835] L835-1-->L837: Formula: (and (= 0 (select |v_#valid_39| |v_ULTIMATE.start_main_~#t783~0.base_11|)) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t783~0.base_11| 4)) (= (store |v_#valid_39| |v_ULTIMATE.start_main_~#t783~0.base_11| 1) |v_#valid_38|) (not (= 0 |v_ULTIMATE.start_main_~#t783~0.base_11|)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t783~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t783~0.base_11|) |v_ULTIMATE.start_main_~#t783~0.offset_10| 2)) |v_#memory_int_13|) (= |v_ULTIMATE.start_main_~#t783~0.offset_10| 0) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t783~0.base_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t783~0.base=|v_ULTIMATE.start_main_~#t783~0.base_11|, #length=|v_#length_17|, ULTIMATE.start_main_~#t783~0.offset=|v_ULTIMATE.start_main_~#t783~0.offset_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, ULTIMATE.start_main_~#t783~0.base, #length, ULTIMATE.start_main_~#t783~0.offset] because there is no mapped edge [2019-12-07 10:38:11,080 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] P2ENTRY-->L4-3: Formula: (and (= (ite (not (and (not (= 0 (mod v_~y$w_buff1_used~0_105 256))) (not (= 0 (mod v_~y$w_buff0_used~0_178 256))))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~y$w_buff0~0_34 v_~y$w_buff1~0_39) (= |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8)) (= 2 v_~y$w_buff0~0_33) (= v_P2Thread1of1ForFork0_~arg.base_6 |v_P2Thread1of1ForFork0_#in~arg.base_8|) (= v_~y$w_buff0_used~0_179 v_~y$w_buff1_used~0_105) (= v_~y$w_buff0_used~0_178 1) (= v_P2Thread1of1ForFork0_~arg.offset_6 |v_P2Thread1of1ForFork0_#in~arg.offset_8|)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_179, ~y$w_buff0~0=v_~y$w_buff0~0_34, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_6, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_178, ~y$w_buff1~0=v_~y$w_buff1~0_39, ~y$w_buff0~0=v_~y$w_buff0~0_33, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_6, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_105} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 10:38:11,080 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L837-1-->L839: Formula: (and (= (store |v_#length_22| |v_ULTIMATE.start_main_~#t784~0.base_11| 4) |v_#length_21|) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t784~0.base_11| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t784~0.base_11|) |v_ULTIMATE.start_main_~#t784~0.offset_9| 3)) |v_#memory_int_17|) (not (= |v_ULTIMATE.start_main_~#t784~0.base_11| 0)) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t784~0.base_11|) (= |v_ULTIMATE.start_main_~#t784~0.offset_9| 0) (= |v_#valid_44| (store |v_#valid_45| |v_ULTIMATE.start_main_~#t784~0.base_11| 1)) (= (select |v_#valid_45| |v_ULTIMATE.start_main_~#t784~0.base_11|) 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_~#t784~0.base=|v_ULTIMATE.start_main_~#t784~0.base_11|, #StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_4|, #valid=|v_#valid_44|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_~#t784~0.offset=|v_ULTIMATE.start_main_~#t784~0.offset_9|, #length=|v_#length_21|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t784~0.base, ULTIMATE.start_main_#t~nondet23, #valid, #memory_int, ULTIMATE.start_main_~#t784~0.offset, #length] because there is no mapped edge [2019-12-07 10:38:11,081 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] P0ENTRY-->P0EXIT: Formula: (and (= v_P0Thread1of1ForFork2_~arg.base_6 |v_P0Thread1of1ForFork2_#in~arg.base_8|) (= v_~a~0_12 1) (= (+ v_~__unbuffered_cnt~0_48 1) v_~__unbuffered_cnt~0_47) (= |v_P0Thread1of1ForFork2_#res.offset_3| 0) (= v_P0Thread1of1ForFork2_~arg.offset_6 |v_P0Thread1of1ForFork2_#in~arg.offset_8|) (= v_~x~0_36 v_~__unbuffered_p0_EAX~0_17) (= 0 |v_P0Thread1of1ForFork2_#res.base_3|)) InVars {P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_48, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_8|, ~x~0=v_~x~0_36} OutVars{~a~0=v_~a~0_12, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_17, P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_8|, P0Thread1of1ForFork2_~arg.offset=v_P0Thread1of1ForFork2_~arg.offset_6, P0Thread1of1ForFork2_#res.offset=|v_P0Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_47, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_8|, P0Thread1of1ForFork2_#res.base=|v_P0Thread1of1ForFork2_#res.base_3|, ~x~0=v_~x~0_36, P0Thread1of1ForFork2_~arg.base=v_P0Thread1of1ForFork2_~arg.base_6} AuxVars[] AssignedVars[~a~0, ~__unbuffered_p0_EAX~0, P0Thread1of1ForFork2_~arg.offset, P0Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0, P0Thread1of1ForFork2_#res.base, P0Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-12-07 10:38:11,082 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L757-2-->L757-5: Formula: (let ((.cse2 (= |P1Thread1of1ForFork3_#t~ite3_Out1699740190| |P1Thread1of1ForFork3_#t~ite4_Out1699740190|)) (.cse1 (= (mod ~y$w_buff1_used~0_In1699740190 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd2~0_In1699740190 256) 0))) (or (and (or .cse0 .cse1) .cse2 (= |P1Thread1of1ForFork3_#t~ite3_Out1699740190| ~y~0_In1699740190)) (and .cse2 (not .cse1) (not .cse0) (= ~y$w_buff1~0_In1699740190 |P1Thread1of1ForFork3_#t~ite3_Out1699740190|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1699740190, ~y$w_buff1~0=~y$w_buff1~0_In1699740190, ~y~0=~y~0_In1699740190, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1699740190} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1699740190, ~y$w_buff1~0=~y$w_buff1~0_In1699740190, P1Thread1of1ForFork3_#t~ite4=|P1Thread1of1ForFork3_#t~ite4_Out1699740190|, P1Thread1of1ForFork3_#t~ite3=|P1Thread1of1ForFork3_#t~ite3_Out1699740190|, ~y~0=~y~0_In1699740190, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1699740190} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite4, P1Thread1of1ForFork3_#t~ite3] because there is no mapped edge [2019-12-07 10:38:11,082 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L758-->L758-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In1414931505 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In1414931505 256)))) (or (and (not .cse0) (= |P1Thread1of1ForFork3_#t~ite5_Out1414931505| 0) (not .cse1)) (and (= ~y$w_buff0_used~0_In1414931505 |P1Thread1of1ForFork3_#t~ite5_Out1414931505|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1414931505, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1414931505} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1414931505, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1414931505, P1Thread1of1ForFork3_#t~ite5=|P1Thread1of1ForFork3_#t~ite5_Out1414931505|} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite5] because there is no mapped edge [2019-12-07 10:38:11,082 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [807] [807] L810-2-->L810-4: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In954344809 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd4~0_In954344809 256) 0))) (or (and (not .cse0) (not .cse1) (= |P3Thread1of1ForFork1_#t~ite15_Out954344809| ~y$w_buff1~0_In954344809)) (and (= |P3Thread1of1ForFork1_#t~ite15_Out954344809| ~y~0_In954344809) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In954344809, ~y$w_buff1~0=~y$w_buff1~0_In954344809, ~y~0=~y~0_In954344809, ~y$w_buff1_used~0=~y$w_buff1_used~0_In954344809} OutVars{~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In954344809, ~y$w_buff1~0=~y$w_buff1~0_In954344809, P3Thread1of1ForFork1_#t~ite15=|P3Thread1of1ForFork1_#t~ite15_Out954344809|, ~y~0=~y~0_In954344809, ~y$w_buff1_used~0=~y$w_buff1_used~0_In954344809} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite15] because there is no mapped edge [2019-12-07 10:38:11,083 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [794] [794] L759-->L759-2: Formula: (let ((.cse2 (= (mod ~y$w_buff1_used~0_In2083305106 256) 0)) (.cse3 (= (mod ~y$r_buff1_thd2~0_In2083305106 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In2083305106 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In2083305106 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P1Thread1of1ForFork3_#t~ite6_Out2083305106| ~y$w_buff1_used~0_In2083305106)) (and (= |P1Thread1of1ForFork3_#t~ite6_Out2083305106| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2083305106, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2083305106, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2083305106, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2083305106} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2083305106, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2083305106, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2083305106, P1Thread1of1ForFork3_#t~ite6=|P1Thread1of1ForFork3_#t~ite6_Out2083305106|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2083305106} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite6] because there is no mapped edge [2019-12-07 10:38:11,083 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [731] [731] L810-4-->L811: Formula: (= v_~y~0_28 |v_P3Thread1of1ForFork1_#t~ite15_8|) InVars {P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_8|} OutVars{P3Thread1of1ForFork1_#t~ite16=|v_P3Thread1of1ForFork1_#t~ite16_13|, P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_7|, ~y~0=v_~y~0_28} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite16, P3Thread1of1ForFork1_#t~ite15, ~y~0] because there is no mapped edge [2019-12-07 10:38:11,083 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L811-->L811-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd4~0_In-1063402688 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1063402688 256)))) (or (and (= |P3Thread1of1ForFork1_#t~ite17_Out-1063402688| 0) (not .cse0) (not .cse1)) (and (= |P3Thread1of1ForFork1_#t~ite17_Out-1063402688| ~y$w_buff0_used~0_In-1063402688) (or .cse0 .cse1)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1063402688, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1063402688} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1063402688, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1063402688, P3Thread1of1ForFork1_#t~ite17=|P3Thread1of1ForFork1_#t~ite17_Out-1063402688|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite17] because there is no mapped edge [2019-12-07 10:38:11,083 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L812-->L812-2: Formula: (let ((.cse3 (= 0 (mod ~y$r_buff1_thd4~0_In-1144763357 256))) (.cse2 (= (mod ~y$w_buff1_used~0_In-1144763357 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1144763357 256))) (.cse1 (= (mod ~y$r_buff0_thd4~0_In-1144763357 256) 0))) (or (and (or .cse0 .cse1) (= ~y$w_buff1_used~0_In-1144763357 |P3Thread1of1ForFork1_#t~ite18_Out-1144763357|) (or .cse2 .cse3)) (and (= 0 |P3Thread1of1ForFork1_#t~ite18_Out-1144763357|) (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1)))))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1144763357, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-1144763357, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1144763357, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1144763357} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1144763357, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-1144763357, P3Thread1of1ForFork1_#t~ite18=|P3Thread1of1ForFork1_#t~ite18_Out-1144763357|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1144763357, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1144763357} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite18] because there is no mapped edge [2019-12-07 10:38:11,084 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L813-->L813-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd4~0_In1020777018 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In1020777018 256)))) (or (and (not .cse0) (= |P3Thread1of1ForFork1_#t~ite19_Out1020777018| 0) (not .cse1)) (and (or .cse0 .cse1) (= |P3Thread1of1ForFork1_#t~ite19_Out1020777018| ~y$r_buff0_thd4~0_In1020777018)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1020777018, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1020777018} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1020777018, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1020777018, P3Thread1of1ForFork1_#t~ite19=|P3Thread1of1ForFork1_#t~ite19_Out1020777018|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite19] because there is no mapped edge [2019-12-07 10:38:11,084 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L760-->L760-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In593259054 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In593259054 256) 0))) (or (and (= |P1Thread1of1ForFork3_#t~ite7_Out593259054| ~y$r_buff0_thd2~0_In593259054) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork3_#t~ite7_Out593259054|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In593259054, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In593259054} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In593259054, P1Thread1of1ForFork3_#t~ite7=|P1Thread1of1ForFork3_#t~ite7_Out593259054|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In593259054} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite7] because there is no mapped edge [2019-12-07 10:38:11,085 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [810] [810] L761-->L761-2: Formula: (let ((.cse3 (= (mod ~y$w_buff1_used~0_In-1993818874 256) 0)) (.cse2 (= (mod ~y$r_buff1_thd2~0_In-1993818874 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-1993818874 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1993818874 256)))) (or (and (= |P1Thread1of1ForFork3_#t~ite8_Out-1993818874| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse1 .cse0) (= |P1Thread1of1ForFork3_#t~ite8_Out-1993818874| ~y$r_buff1_thd2~0_In-1993818874)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1993818874, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1993818874, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1993818874, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1993818874} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1993818874, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1993818874, P1Thread1of1ForFork3_#t~ite8=|P1Thread1of1ForFork3_#t~ite8_Out-1993818874|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1993818874, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1993818874} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite8] because there is no mapped edge [2019-12-07 10:38:11,085 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L761-2-->P1EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_41 1) v_~__unbuffered_cnt~0_40) (= 0 |v_P1Thread1of1ForFork3_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork3_#res.base_3|) (= |v_P1Thread1of1ForFork3_#t~ite8_24| v_~y$r_buff1_thd2~0_111)) InVars {P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_41} OutVars{P1Thread1of1ForFork3_#res.base=|v_P1Thread1of1ForFork3_#res.base_3|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_111, P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_23|, P1Thread1of1ForFork3_#res.offset=|v_P1Thread1of1ForFork3_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#res.base, ~y$r_buff1_thd2~0, P1Thread1of1ForFork3_#t~ite8, P1Thread1of1ForFork3_#res.offset, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 10:38:11,085 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L788-->L788-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1396074371 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In-1396074371 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In-1396074371 |P2Thread1of1ForFork0_#t~ite11_Out-1396074371|)) (and (= 0 |P2Thread1of1ForFork0_#t~ite11_Out-1396074371|) (not .cse1) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1396074371, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1396074371} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1396074371, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-1396074371|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1396074371} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 10:38:11,085 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [813] [813] L789-->L789-2: Formula: (let ((.cse3 (= (mod ~y$w_buff1_used~0_In-1503873405 256) 0)) (.cse2 (= (mod ~y$r_buff1_thd3~0_In-1503873405 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In-1503873405 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In-1503873405 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork0_#t~ite12_Out-1503873405|)) (and (= |P2Thread1of1ForFork0_#t~ite12_Out-1503873405| ~y$w_buff1_used~0_In-1503873405) (or .cse3 .cse2) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1503873405, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1503873405, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1503873405, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1503873405} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1503873405, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1503873405, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-1503873405|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1503873405, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1503873405} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 10:38:11,086 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L790-->L791: Formula: (let ((.cse0 (= ~y$r_buff0_thd3~0_In795151806 ~y$r_buff0_thd3~0_Out795151806)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In795151806 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In795151806 256)))) (or (and .cse0 .cse1) (and .cse0 .cse2) (and (not .cse1) (not .cse2) (= 0 ~y$r_buff0_thd3~0_Out795151806)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In795151806, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In795151806} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In795151806, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out795151806, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out795151806|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 10:38:11,086 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L791-->L791-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff0_used~0_In1312987537 256))) (.cse2 (= (mod ~y$r_buff0_thd3~0_In1312987537 256) 0)) (.cse1 (= (mod ~y$w_buff1_used~0_In1312987537 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd3~0_In1312987537 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite14_Out1312987537| ~y$r_buff1_thd3~0_In1312987537) (or .cse2 .cse3)) (and (= |P2Thread1of1ForFork0_#t~ite14_Out1312987537| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1312987537, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1312987537, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1312987537, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1312987537} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out1312987537|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1312987537, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1312987537, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1312987537, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1312987537} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 10:38:11,086 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [847] [847] L791-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= v_~__unbuffered_cnt~0_59 (+ v_~__unbuffered_cnt~0_60 1)) (= v_~y$r_buff1_thd3~0_114 |v_P2Thread1of1ForFork0_#t~ite14_20|) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_20|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_60} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_19|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_114, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_59, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 10:38:11,086 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [792] [792] L814-->L814-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff0_used~0_In-1402159742 256))) (.cse3 (= 0 (mod ~y$r_buff0_thd4~0_In-1402159742 256))) (.cse1 (= (mod ~y$r_buff1_thd4~0_In-1402159742 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In-1402159742 256) 0))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd4~0_In-1402159742 |P3Thread1of1ForFork1_#t~ite20_Out-1402159742|) (or .cse2 .cse3)) (and (= 0 |P3Thread1of1ForFork1_#t~ite20_Out-1402159742|) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1402159742, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-1402159742, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1402159742, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1402159742} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1402159742, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-1402159742, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1402159742, P3Thread1of1ForFork1_#t~ite20=|P3Thread1of1ForFork1_#t~ite20_Out-1402159742|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1402159742} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 10:38:11,086 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [846] [846] L814-2-->P3EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_54 1) v_~__unbuffered_cnt~0_53) (= |v_P3Thread1of1ForFork1_#t~ite20_28| v_~y$r_buff1_thd4~0_111) (= |v_P3Thread1of1ForFork1_#res.offset_3| 0) (= |v_P3Thread1of1ForFork1_#res.base_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_28|} OutVars{~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_111, P3Thread1of1ForFork1_#res.base=|v_P3Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_53, P3Thread1of1ForFork1_#res.offset=|v_P3Thread1of1ForFork1_#res.offset_3|, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_27|} AuxVars[] AssignedVars[~y$r_buff1_thd4~0, P3Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork1_#res.offset, P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 10:38:11,087 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L843-->L845-2: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (or (= (mod v_~y$w_buff0_used~0_216 256) 0) (= 0 (mod v_~y$r_buff0_thd0~0_104 256)))) InVars {~y$w_buff0_used~0=v_~y$w_buff0_used~0_216, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} OutVars{~y$w_buff0_used~0=v_~y$w_buff0_used~0_216, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 10:38:11,087 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L845-2-->L845-5: Formula: (let ((.cse1 (= |ULTIMATE.start_main_#t~ite26_Out-421721701| |ULTIMATE.start_main_#t~ite25_Out-421721701|)) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-421721701 256))) (.cse2 (= (mod ~y$w_buff1_used~0_In-421721701 256) 0))) (or (and (not .cse0) .cse1 (= |ULTIMATE.start_main_#t~ite25_Out-421721701| ~y$w_buff1~0_In-421721701) (not .cse2)) (and .cse1 (or .cse0 .cse2) (= |ULTIMATE.start_main_#t~ite25_Out-421721701| ~y~0_In-421721701)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-421721701, ~y~0=~y~0_In-421721701, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-421721701, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-421721701} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-421721701, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-421721701|, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-421721701|, ~y~0=~y~0_In-421721701, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-421721701, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-421721701} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 10:38:11,087 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [797] [797] L846-->L846-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1208136471 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-1208136471 256)))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite27_Out-1208136471|) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite27_Out-1208136471| ~y$w_buff0_used~0_In-1208136471) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1208136471, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1208136471} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1208136471, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1208136471, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-1208136471|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 10:38:11,088 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L847-->L847-2: Formula: (let ((.cse2 (= (mod ~y$w_buff0_used~0_In-1259013035 256) 0)) (.cse3 (= 0 (mod ~y$r_buff0_thd0~0_In-1259013035 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In-1259013035 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-1259013035 256)))) (or (and (= ~y$w_buff1_used~0_In-1259013035 |ULTIMATE.start_main_#t~ite28_Out-1259013035|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |ULTIMATE.start_main_#t~ite28_Out-1259013035|) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1259013035, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1259013035, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1259013035, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1259013035} OutVars{ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out-1259013035|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1259013035, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1259013035, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1259013035, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1259013035} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 10:38:11,088 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [812] [812] L848-->L848-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1426510303 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-1426510303 256)))) (or (and (= |ULTIMATE.start_main_#t~ite29_Out-1426510303| ~y$r_buff0_thd0~0_In-1426510303) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite29_Out-1426510303| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1426510303, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1426510303} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1426510303, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-1426510303|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1426510303} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 10:38:11,088 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [790] [790] L849-->L849-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In87595741 256))) (.cse1 (= (mod ~y$w_buff1_used~0_In87595741 256) 0)) (.cse3 (= (mod ~y$w_buff0_used~0_In87595741 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd0~0_In87595741 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite30_Out87595741| ~y$r_buff1_thd0~0_In87595741)) (and (= |ULTIMATE.start_main_#t~ite30_Out87595741| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In87595741, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In87595741, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In87595741, ~y$w_buff1_used~0=~y$w_buff1_used~0_In87595741} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out87595741|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In87595741, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In87595741, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In87595741, ~y$w_buff1_used~0=~y$w_buff1_used~0_In87595741} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30] because there is no mapped edge [2019-12-07 10:38:11,090 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [852] [852] L858-->L858-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-1229006778 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite40_Out-1229006778| ~y$w_buff1~0_In-1229006778) (= |ULTIMATE.start_main_#t~ite39_In-1229006778| |ULTIMATE.start_main_#t~ite39_Out-1229006778|)) (and (= ~y$w_buff1~0_In-1229006778 |ULTIMATE.start_main_#t~ite39_Out-1229006778|) (= |ULTIMATE.start_main_#t~ite40_Out-1229006778| |ULTIMATE.start_main_#t~ite39_Out-1229006778|) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-1229006778 256) 0))) (or (= 0 (mod ~y$w_buff0_used~0_In-1229006778 256)) (and (= 0 (mod ~y$w_buff1_used~0_In-1229006778 256)) .cse1) (and (= 0 (mod ~y$r_buff1_thd0~0_In-1229006778 256)) .cse1))) .cse0))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1229006778, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1229006778, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_In-1229006778|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1229006778, ~weak$$choice2~0=~weak$$choice2~0_In-1229006778, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1229006778, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1229006778} OutVars{ULTIMATE.start_main_#t~ite40=|ULTIMATE.start_main_#t~ite40_Out-1229006778|, ~y$w_buff1~0=~y$w_buff1~0_In-1229006778, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1229006778, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out-1229006778|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1229006778, ~weak$$choice2~0=~weak$$choice2~0_In-1229006778, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1229006778, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1229006778} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 10:38:11,090 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L859-->L859-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In1966669572 256)))) (or (and (= |ULTIMATE.start_main_#t~ite43_Out1966669572| ~y$w_buff0_used~0_In1966669572) (= |ULTIMATE.start_main_#t~ite42_In1966669572| |ULTIMATE.start_main_#t~ite42_Out1966669572|) (not .cse0)) (and (= ~y$w_buff0_used~0_In1966669572 |ULTIMATE.start_main_#t~ite42_Out1966669572|) .cse0 (= |ULTIMATE.start_main_#t~ite43_Out1966669572| |ULTIMATE.start_main_#t~ite42_Out1966669572|) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In1966669572 256)))) (or (and (= 0 (mod ~y$w_buff1_used~0_In1966669572 256)) .cse1) (= 0 (mod ~y$w_buff0_used~0_In1966669572 256)) (and (= (mod ~y$r_buff1_thd0~0_In1966669572 256) 0) .cse1)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1966669572, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1966669572, ~weak$$choice2~0=~weak$$choice2~0_In1966669572, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1966669572, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_In1966669572|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1966669572} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1966669572, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1966669572, ULTIMATE.start_main_#t~ite43=|ULTIMATE.start_main_#t~ite43_Out1966669572|, ~weak$$choice2~0=~weak$$choice2~0_In1966669572, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_Out1966669572|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1966669572, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1966669572} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 10:38:11,091 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [865] [865] L860-->L860-8: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In1738256568 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In1738256568 256))) (.cse5 (= 0 (mod ~y$r_buff1_thd0~0_In1738256568 256))) (.cse6 (= 0 (mod ~y$r_buff0_thd0~0_In1738256568 256))) (.cse4 (= |ULTIMATE.start_main_#t~ite46_Out1738256568| |ULTIMATE.start_main_#t~ite45_Out1738256568|)) (.cse3 (= (mod ~weak$$choice2~0_In1738256568 256) 0))) (or (let ((.cse1 (not .cse6))) (and (or (not .cse0) .cse1) (not .cse2) .cse3 (= |ULTIMATE.start_main_#t~ite44_Out1738256568| 0) .cse4 (or (not .cse5) .cse1) (= |ULTIMATE.start_main_#t~ite44_Out1738256568| |ULTIMATE.start_main_#t~ite45_Out1738256568|))) (and (or (and .cse3 (= ~y$w_buff1_used~0_In1738256568 |ULTIMATE.start_main_#t~ite45_Out1738256568|) (or (and .cse0 .cse6) .cse2 (and .cse5 .cse6)) .cse4) (and (= |ULTIMATE.start_main_#t~ite45_In1738256568| |ULTIMATE.start_main_#t~ite45_Out1738256568|) (= |ULTIMATE.start_main_#t~ite46_Out1738256568| ~y$w_buff1_used~0_In1738256568) (not .cse3))) (= |ULTIMATE.start_main_#t~ite44_In1738256568| |ULTIMATE.start_main_#t~ite44_Out1738256568|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1738256568, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1738256568, ~weak$$choice2~0=~weak$$choice2~0_In1738256568, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1738256568, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In1738256568|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1738256568, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_In1738256568|} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1738256568, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1738256568, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out1738256568|, ~weak$$choice2~0=~weak$$choice2~0_In1738256568, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1738256568, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out1738256568|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1738256568, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_Out1738256568|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-12-07 10:38:11,091 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [868] [868] L860-8-->L862: Formula: (and (not (= (mod v_~weak$$choice2~0_106 256) 0)) (= v_~y$w_buff1_used~0_383 |v_ULTIMATE.start_main_#t~ite46_36|) (= v_~y$r_buff0_thd0~0_352 v_~y$r_buff0_thd0~0_351)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_352, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~weak$$choice2~0=v_~weak$$choice2~0_106} OutVars{~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_351, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_35|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_31|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_34|, ~weak$$choice2~0=v_~weak$$choice2~0_106, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_33|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_383} AuxVars[] AssignedVars[~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 10:38:11,091 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L864-->L4: Formula: (and (= 0 v_~y$flush_delayed~0_25) (= v_~y~0_116 v_~y$mem_tmp~0_11) (not (= (mod v_~y$flush_delayed~0_26 256) 0)) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5| (mod v_~main$tmp_guard1~0_15 256))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_26, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_11, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ~y$flush_delayed~0=v_~y$flush_delayed~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15, ~y~0=v_~y~0_116, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_23|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ~y~0, ULTIMATE.start_main_#t~ite53, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 10:38:11,091 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 10:38:11,150 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 10:38:11 BasicIcfg [2019-12-07 10:38:11,150 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 10:38:11,150 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 10:38:11,150 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 10:38:11,150 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 10:38:11,151 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 10:35:18" (3/4) ... [2019-12-07 10:38:11,152 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 10:38:11,153 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [876] [876] ULTIMATE.startENTRY-->L833: Formula: (let ((.cse0 (store |v_#valid_73| 0 0))) (and (= v_~x~0_55 0) (= (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t781~0.base_24| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t781~0.base_24|) |v_ULTIMATE.start_main_~#t781~0.offset_18| 0)) |v_#memory_int_27|) (= v_~a~0_26 0) (= 0 v_~y$read_delayed_var~0.offset_7) (= v_~y$r_buff1_thd0~0_273 0) (= v_~y$r_buff0_thd1~0_30 0) (= v_~y$r_buff0_thd4~0_83 0) (= v_~main$tmp_guard0~0_39 0) (= 0 v_~y$r_buff1_thd1~0_94) (= 0 v_~y$r_buff0_thd3~0_170) (= v_~y~0_170 0) (= 0 v_~__unbuffered_p3_EBX~0_25) (= v_~y$read_delayed~0_6 0) (= v_~y$r_buff0_thd0~0_357 0) (= |v_#length_31| (store |v_#length_32| |v_ULTIMATE.start_main_~#t781~0.base_24| 4)) (= v_~y$mem_tmp~0_18 0) (= 0 v_~y$flush_delayed~0_35) (= 0 v_~__unbuffered_p3_EAX~0_21) (= v_~__unbuffered_cnt~0_136 0) (= v_~y$w_buff1_used~0_387 0) (= 0 v_~y$r_buff1_thd2~0_158) (= 0 |v_#NULL.base_4|) (= v_~y$w_buff1~0_158 0) (= 0 v_~y$read_delayed_var~0.base_7) (< 0 |v_#StackHeapBarrier_20|) (= v_~y$r_buff0_thd2~0_97 0) (= |v_ULTIMATE.start_main_~#t781~0.offset_18| 0) (= |v_#valid_71| (store .cse0 |v_ULTIMATE.start_main_~#t781~0.base_24| 1)) (= v_~z~0_109 0) (= 0 v_~__unbuffered_p0_EAX~0_27) (= 0 v_~y$w_buff0~0_171) (= 0 v_~y$r_buff1_thd4~0_149) (= |v_#NULL.offset_4| 0) (= v_~main$tmp_guard1~0_24 0) (= 0 v_~weak$$choice0~0_13) (= 0 v_~y$r_buff1_thd3~0_146) (= v_~weak$$choice2~0_110 0) (< |v_#StackHeapBarrier_20| |v_ULTIMATE.start_main_~#t781~0.base_24|) (= (select .cse0 |v_ULTIMATE.start_main_~#t781~0.base_24|) 0) (= v_~y$w_buff0_used~0_739 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_20|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_28|, #length=|v_#length_32|} OutVars{ULTIMATE.start_main_~#t781~0.offset=|v_ULTIMATE.start_main_~#t781~0.offset_18|, ULTIMATE.start_main_#t~nondet32=|v_ULTIMATE.start_main_#t~nondet32_21|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_33|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_30|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_28|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_33|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_284|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_37|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_41|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ULTIMATE.start_main_~#t784~0.base=|v_ULTIMATE.start_main_~#t784~0.base_20|, ~a~0=v_~a~0_26, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_29|, ~y$mem_tmp~0=v_~y$mem_tmp~0_18, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_27, ULTIMATE.start_main_~#t781~0.base=|v_ULTIMATE.start_main_~#t781~0.base_24|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_146, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_30, ULTIMATE.start_main_~#t784~0.offset=|v_ULTIMATE.start_main_~#t784~0.offset_16|, ~y$flush_delayed~0=v_~y$flush_delayed~0_35, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_21, #length=|v_#length_31|, ULTIMATE.start_main_~#t782~0.base=|v_ULTIMATE.start_main_~#t782~0.base_23|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_54|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_28|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_25|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_55|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_20|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_46|, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_149, ~y$w_buff1~0=v_~y$w_buff1~0_158, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_97, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_136, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_273, ~x~0=v_~x~0_55, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_739, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_27|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_29|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_40|, ULTIMATE.start_main_~#t783~0.base=|v_ULTIMATE.start_main_~#t783~0.base_20|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_24, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_25|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_36|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_158|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_39|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_94, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_33|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_51|, ~y$w_buff0~0=v_~y$w_buff0~0_171, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_170, ~y~0=v_~y~0_170, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_9|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_9|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_46|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_52|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_39, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_25, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_32|, ULTIMATE.start_main_~#t783~0.offset=|v_ULTIMATE.start_main_~#t783~0.offset_17|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_103|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_158, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_83, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_154|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_357, #valid=|v_#valid_71|, #memory_int=|v_#memory_int_27|, ~z~0=v_~z~0_109, ~weak$$choice2~0=v_~weak$$choice2~0_110, ULTIMATE.start_main_~#t782~0.offset=|v_ULTIMATE.start_main_~#t782~0.offset_18|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_387} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t781~0.offset, ULTIMATE.start_main_#t~nondet32, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ~y$read_delayed~0, ULTIMATE.start_main_~#t784~0.base, ~a~0, ULTIMATE.start_main_#t~ite52, ~y$mem_tmp~0, ~__unbuffered_p0_EAX~0, ULTIMATE.start_main_~#t781~0.base, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ULTIMATE.start_main_~#t784~0.offset, ~y$flush_delayed~0, ~__unbuffered_p3_EAX~0, #length, ULTIMATE.start_main_~#t782~0.base, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$r_buff1_thd4~0, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_~#t783~0.base, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite51, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~__unbuffered_p3_EBX~0, ULTIMATE.start_main_#t~ite53, ULTIMATE.start_main_~#t783~0.offset, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ~y$r_buff0_thd4~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ULTIMATE.start_main_~#t782~0.offset, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 10:38:11,153 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L833-1-->L835: Formula: (and (= (select |v_#valid_43| |v_ULTIMATE.start_main_~#t782~0.base_10|) 0) (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t782~0.base_10| 4)) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t782~0.base_10|) (= |v_#valid_42| (store |v_#valid_43| |v_ULTIMATE.start_main_~#t782~0.base_10| 1)) (not (= |v_ULTIMATE.start_main_~#t782~0.base_10| 0)) (= |v_#memory_int_15| (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t782~0.base_10| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t782~0.base_10|) |v_ULTIMATE.start_main_~#t782~0.offset_9| 1))) (= |v_ULTIMATE.start_main_~#t782~0.offset_9| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_43|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, ULTIMATE.start_main_~#t782~0.base=|v_ULTIMATE.start_main_~#t782~0.base_10|, #valid=|v_#valid_42|, #memory_int=|v_#memory_int_15|, #length=|v_#length_19|, ULTIMATE.start_main_~#t782~0.offset=|v_ULTIMATE.start_main_~#t782~0.offset_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t782~0.base, #valid, #memory_int, #length, ULTIMATE.start_main_~#t782~0.offset] because there is no mapped edge [2019-12-07 10:38:11,153 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [835] [835] L835-1-->L837: Formula: (and (= 0 (select |v_#valid_39| |v_ULTIMATE.start_main_~#t783~0.base_11|)) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t783~0.base_11| 4)) (= (store |v_#valid_39| |v_ULTIMATE.start_main_~#t783~0.base_11| 1) |v_#valid_38|) (not (= 0 |v_ULTIMATE.start_main_~#t783~0.base_11|)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t783~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t783~0.base_11|) |v_ULTIMATE.start_main_~#t783~0.offset_10| 2)) |v_#memory_int_13|) (= |v_ULTIMATE.start_main_~#t783~0.offset_10| 0) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t783~0.base_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t783~0.base=|v_ULTIMATE.start_main_~#t783~0.base_11|, #length=|v_#length_17|, ULTIMATE.start_main_~#t783~0.offset=|v_ULTIMATE.start_main_~#t783~0.offset_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, ULTIMATE.start_main_~#t783~0.base, #length, ULTIMATE.start_main_~#t783~0.offset] because there is no mapped edge [2019-12-07 10:38:11,154 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] P2ENTRY-->L4-3: Formula: (and (= (ite (not (and (not (= 0 (mod v_~y$w_buff1_used~0_105 256))) (not (= 0 (mod v_~y$w_buff0_used~0_178 256))))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~y$w_buff0~0_34 v_~y$w_buff1~0_39) (= |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8)) (= 2 v_~y$w_buff0~0_33) (= v_P2Thread1of1ForFork0_~arg.base_6 |v_P2Thread1of1ForFork0_#in~arg.base_8|) (= v_~y$w_buff0_used~0_179 v_~y$w_buff1_used~0_105) (= v_~y$w_buff0_used~0_178 1) (= v_P2Thread1of1ForFork0_~arg.offset_6 |v_P2Thread1of1ForFork0_#in~arg.offset_8|)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_179, ~y$w_buff0~0=v_~y$w_buff0~0_34, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_6, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_178, ~y$w_buff1~0=v_~y$w_buff1~0_39, ~y$w_buff0~0=v_~y$w_buff0~0_33, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_6, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_105} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 10:38:11,154 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L837-1-->L839: Formula: (and (= (store |v_#length_22| |v_ULTIMATE.start_main_~#t784~0.base_11| 4) |v_#length_21|) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t784~0.base_11| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t784~0.base_11|) |v_ULTIMATE.start_main_~#t784~0.offset_9| 3)) |v_#memory_int_17|) (not (= |v_ULTIMATE.start_main_~#t784~0.base_11| 0)) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t784~0.base_11|) (= |v_ULTIMATE.start_main_~#t784~0.offset_9| 0) (= |v_#valid_44| (store |v_#valid_45| |v_ULTIMATE.start_main_~#t784~0.base_11| 1)) (= (select |v_#valid_45| |v_ULTIMATE.start_main_~#t784~0.base_11|) 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_~#t784~0.base=|v_ULTIMATE.start_main_~#t784~0.base_11|, #StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_4|, #valid=|v_#valid_44|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_~#t784~0.offset=|v_ULTIMATE.start_main_~#t784~0.offset_9|, #length=|v_#length_21|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t784~0.base, ULTIMATE.start_main_#t~nondet23, #valid, #memory_int, ULTIMATE.start_main_~#t784~0.offset, #length] because there is no mapped edge [2019-12-07 10:38:11,155 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] P0ENTRY-->P0EXIT: Formula: (and (= v_P0Thread1of1ForFork2_~arg.base_6 |v_P0Thread1of1ForFork2_#in~arg.base_8|) (= v_~a~0_12 1) (= (+ v_~__unbuffered_cnt~0_48 1) v_~__unbuffered_cnt~0_47) (= |v_P0Thread1of1ForFork2_#res.offset_3| 0) (= v_P0Thread1of1ForFork2_~arg.offset_6 |v_P0Thread1of1ForFork2_#in~arg.offset_8|) (= v_~x~0_36 v_~__unbuffered_p0_EAX~0_17) (= 0 |v_P0Thread1of1ForFork2_#res.base_3|)) InVars {P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_48, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_8|, ~x~0=v_~x~0_36} OutVars{~a~0=v_~a~0_12, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_17, P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_8|, P0Thread1of1ForFork2_~arg.offset=v_P0Thread1of1ForFork2_~arg.offset_6, P0Thread1of1ForFork2_#res.offset=|v_P0Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_47, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_8|, P0Thread1of1ForFork2_#res.base=|v_P0Thread1of1ForFork2_#res.base_3|, ~x~0=v_~x~0_36, P0Thread1of1ForFork2_~arg.base=v_P0Thread1of1ForFork2_~arg.base_6} AuxVars[] AssignedVars[~a~0, ~__unbuffered_p0_EAX~0, P0Thread1of1ForFork2_~arg.offset, P0Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0, P0Thread1of1ForFork2_#res.base, P0Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-12-07 10:38:11,155 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L757-2-->L757-5: Formula: (let ((.cse2 (= |P1Thread1of1ForFork3_#t~ite3_Out1699740190| |P1Thread1of1ForFork3_#t~ite4_Out1699740190|)) (.cse1 (= (mod ~y$w_buff1_used~0_In1699740190 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd2~0_In1699740190 256) 0))) (or (and (or .cse0 .cse1) .cse2 (= |P1Thread1of1ForFork3_#t~ite3_Out1699740190| ~y~0_In1699740190)) (and .cse2 (not .cse1) (not .cse0) (= ~y$w_buff1~0_In1699740190 |P1Thread1of1ForFork3_#t~ite3_Out1699740190|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1699740190, ~y$w_buff1~0=~y$w_buff1~0_In1699740190, ~y~0=~y~0_In1699740190, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1699740190} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1699740190, ~y$w_buff1~0=~y$w_buff1~0_In1699740190, P1Thread1of1ForFork3_#t~ite4=|P1Thread1of1ForFork3_#t~ite4_Out1699740190|, P1Thread1of1ForFork3_#t~ite3=|P1Thread1of1ForFork3_#t~ite3_Out1699740190|, ~y~0=~y~0_In1699740190, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1699740190} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite4, P1Thread1of1ForFork3_#t~ite3] because there is no mapped edge [2019-12-07 10:38:11,156 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L758-->L758-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In1414931505 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In1414931505 256)))) (or (and (not .cse0) (= |P1Thread1of1ForFork3_#t~ite5_Out1414931505| 0) (not .cse1)) (and (= ~y$w_buff0_used~0_In1414931505 |P1Thread1of1ForFork3_#t~ite5_Out1414931505|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1414931505, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1414931505} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1414931505, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1414931505, P1Thread1of1ForFork3_#t~ite5=|P1Thread1of1ForFork3_#t~ite5_Out1414931505|} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite5] because there is no mapped edge [2019-12-07 10:38:11,156 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [807] [807] L810-2-->L810-4: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In954344809 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd4~0_In954344809 256) 0))) (or (and (not .cse0) (not .cse1) (= |P3Thread1of1ForFork1_#t~ite15_Out954344809| ~y$w_buff1~0_In954344809)) (and (= |P3Thread1of1ForFork1_#t~ite15_Out954344809| ~y~0_In954344809) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In954344809, ~y$w_buff1~0=~y$w_buff1~0_In954344809, ~y~0=~y~0_In954344809, ~y$w_buff1_used~0=~y$w_buff1_used~0_In954344809} OutVars{~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In954344809, ~y$w_buff1~0=~y$w_buff1~0_In954344809, P3Thread1of1ForFork1_#t~ite15=|P3Thread1of1ForFork1_#t~ite15_Out954344809|, ~y~0=~y~0_In954344809, ~y$w_buff1_used~0=~y$w_buff1_used~0_In954344809} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite15] because there is no mapped edge [2019-12-07 10:38:11,156 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [794] [794] L759-->L759-2: Formula: (let ((.cse2 (= (mod ~y$w_buff1_used~0_In2083305106 256) 0)) (.cse3 (= (mod ~y$r_buff1_thd2~0_In2083305106 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In2083305106 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In2083305106 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P1Thread1of1ForFork3_#t~ite6_Out2083305106| ~y$w_buff1_used~0_In2083305106)) (and (= |P1Thread1of1ForFork3_#t~ite6_Out2083305106| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2083305106, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2083305106, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2083305106, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2083305106} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2083305106, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2083305106, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2083305106, P1Thread1of1ForFork3_#t~ite6=|P1Thread1of1ForFork3_#t~ite6_Out2083305106|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2083305106} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite6] because there is no mapped edge [2019-12-07 10:38:11,156 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [731] [731] L810-4-->L811: Formula: (= v_~y~0_28 |v_P3Thread1of1ForFork1_#t~ite15_8|) InVars {P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_8|} OutVars{P3Thread1of1ForFork1_#t~ite16=|v_P3Thread1of1ForFork1_#t~ite16_13|, P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_7|, ~y~0=v_~y~0_28} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite16, P3Thread1of1ForFork1_#t~ite15, ~y~0] because there is no mapped edge [2019-12-07 10:38:11,156 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L811-->L811-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd4~0_In-1063402688 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1063402688 256)))) (or (and (= |P3Thread1of1ForFork1_#t~ite17_Out-1063402688| 0) (not .cse0) (not .cse1)) (and (= |P3Thread1of1ForFork1_#t~ite17_Out-1063402688| ~y$w_buff0_used~0_In-1063402688) (or .cse0 .cse1)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1063402688, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1063402688} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1063402688, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1063402688, P3Thread1of1ForFork1_#t~ite17=|P3Thread1of1ForFork1_#t~ite17_Out-1063402688|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite17] because there is no mapped edge [2019-12-07 10:38:11,157 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L812-->L812-2: Formula: (let ((.cse3 (= 0 (mod ~y$r_buff1_thd4~0_In-1144763357 256))) (.cse2 (= (mod ~y$w_buff1_used~0_In-1144763357 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1144763357 256))) (.cse1 (= (mod ~y$r_buff0_thd4~0_In-1144763357 256) 0))) (or (and (or .cse0 .cse1) (= ~y$w_buff1_used~0_In-1144763357 |P3Thread1of1ForFork1_#t~ite18_Out-1144763357|) (or .cse2 .cse3)) (and (= 0 |P3Thread1of1ForFork1_#t~ite18_Out-1144763357|) (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1)))))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1144763357, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-1144763357, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1144763357, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1144763357} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1144763357, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-1144763357, P3Thread1of1ForFork1_#t~ite18=|P3Thread1of1ForFork1_#t~ite18_Out-1144763357|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1144763357, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1144763357} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite18] because there is no mapped edge [2019-12-07 10:38:11,157 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L813-->L813-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd4~0_In1020777018 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In1020777018 256)))) (or (and (not .cse0) (= |P3Thread1of1ForFork1_#t~ite19_Out1020777018| 0) (not .cse1)) (and (or .cse0 .cse1) (= |P3Thread1of1ForFork1_#t~ite19_Out1020777018| ~y$r_buff0_thd4~0_In1020777018)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1020777018, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1020777018} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1020777018, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1020777018, P3Thread1of1ForFork1_#t~ite19=|P3Thread1of1ForFork1_#t~ite19_Out1020777018|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite19] because there is no mapped edge [2019-12-07 10:38:11,158 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L760-->L760-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In593259054 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In593259054 256) 0))) (or (and (= |P1Thread1of1ForFork3_#t~ite7_Out593259054| ~y$r_buff0_thd2~0_In593259054) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork3_#t~ite7_Out593259054|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In593259054, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In593259054} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In593259054, P1Thread1of1ForFork3_#t~ite7=|P1Thread1of1ForFork3_#t~ite7_Out593259054|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In593259054} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite7] because there is no mapped edge [2019-12-07 10:38:11,158 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [810] [810] L761-->L761-2: Formula: (let ((.cse3 (= (mod ~y$w_buff1_used~0_In-1993818874 256) 0)) (.cse2 (= (mod ~y$r_buff1_thd2~0_In-1993818874 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-1993818874 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1993818874 256)))) (or (and (= |P1Thread1of1ForFork3_#t~ite8_Out-1993818874| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse1 .cse0) (= |P1Thread1of1ForFork3_#t~ite8_Out-1993818874| ~y$r_buff1_thd2~0_In-1993818874)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1993818874, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1993818874, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1993818874, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1993818874} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1993818874, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1993818874, P1Thread1of1ForFork3_#t~ite8=|P1Thread1of1ForFork3_#t~ite8_Out-1993818874|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1993818874, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1993818874} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite8] because there is no mapped edge [2019-12-07 10:38:11,158 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L761-2-->P1EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_41 1) v_~__unbuffered_cnt~0_40) (= 0 |v_P1Thread1of1ForFork3_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork3_#res.base_3|) (= |v_P1Thread1of1ForFork3_#t~ite8_24| v_~y$r_buff1_thd2~0_111)) InVars {P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_41} OutVars{P1Thread1of1ForFork3_#res.base=|v_P1Thread1of1ForFork3_#res.base_3|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_111, P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_23|, P1Thread1of1ForFork3_#res.offset=|v_P1Thread1of1ForFork3_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#res.base, ~y$r_buff1_thd2~0, P1Thread1of1ForFork3_#t~ite8, P1Thread1of1ForFork3_#res.offset, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 10:38:11,158 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L788-->L788-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1396074371 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In-1396074371 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In-1396074371 |P2Thread1of1ForFork0_#t~ite11_Out-1396074371|)) (and (= 0 |P2Thread1of1ForFork0_#t~ite11_Out-1396074371|) (not .cse1) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1396074371, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1396074371} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1396074371, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-1396074371|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1396074371} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 10:38:11,159 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [813] [813] L789-->L789-2: Formula: (let ((.cse3 (= (mod ~y$w_buff1_used~0_In-1503873405 256) 0)) (.cse2 (= (mod ~y$r_buff1_thd3~0_In-1503873405 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In-1503873405 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In-1503873405 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork0_#t~ite12_Out-1503873405|)) (and (= |P2Thread1of1ForFork0_#t~ite12_Out-1503873405| ~y$w_buff1_used~0_In-1503873405) (or .cse3 .cse2) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1503873405, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1503873405, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1503873405, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1503873405} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1503873405, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1503873405, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-1503873405|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1503873405, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1503873405} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 10:38:11,159 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L790-->L791: Formula: (let ((.cse0 (= ~y$r_buff0_thd3~0_In795151806 ~y$r_buff0_thd3~0_Out795151806)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In795151806 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In795151806 256)))) (or (and .cse0 .cse1) (and .cse0 .cse2) (and (not .cse1) (not .cse2) (= 0 ~y$r_buff0_thd3~0_Out795151806)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In795151806, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In795151806} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In795151806, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out795151806, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out795151806|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 10:38:11,159 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L791-->L791-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff0_used~0_In1312987537 256))) (.cse2 (= (mod ~y$r_buff0_thd3~0_In1312987537 256) 0)) (.cse1 (= (mod ~y$w_buff1_used~0_In1312987537 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd3~0_In1312987537 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite14_Out1312987537| ~y$r_buff1_thd3~0_In1312987537) (or .cse2 .cse3)) (and (= |P2Thread1of1ForFork0_#t~ite14_Out1312987537| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1312987537, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1312987537, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1312987537, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1312987537} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out1312987537|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1312987537, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1312987537, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1312987537, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1312987537} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 10:38:11,159 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [847] [847] L791-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= v_~__unbuffered_cnt~0_59 (+ v_~__unbuffered_cnt~0_60 1)) (= v_~y$r_buff1_thd3~0_114 |v_P2Thread1of1ForFork0_#t~ite14_20|) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_20|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_60} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_19|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_114, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_59, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 10:38:11,159 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [792] [792] L814-->L814-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff0_used~0_In-1402159742 256))) (.cse3 (= 0 (mod ~y$r_buff0_thd4~0_In-1402159742 256))) (.cse1 (= (mod ~y$r_buff1_thd4~0_In-1402159742 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In-1402159742 256) 0))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd4~0_In-1402159742 |P3Thread1of1ForFork1_#t~ite20_Out-1402159742|) (or .cse2 .cse3)) (and (= 0 |P3Thread1of1ForFork1_#t~ite20_Out-1402159742|) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1402159742, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-1402159742, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1402159742, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1402159742} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1402159742, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-1402159742, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1402159742, P3Thread1of1ForFork1_#t~ite20=|P3Thread1of1ForFork1_#t~ite20_Out-1402159742|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1402159742} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 10:38:11,160 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [846] [846] L814-2-->P3EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_54 1) v_~__unbuffered_cnt~0_53) (= |v_P3Thread1of1ForFork1_#t~ite20_28| v_~y$r_buff1_thd4~0_111) (= |v_P3Thread1of1ForFork1_#res.offset_3| 0) (= |v_P3Thread1of1ForFork1_#res.base_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_28|} OutVars{~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_111, P3Thread1of1ForFork1_#res.base=|v_P3Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_53, P3Thread1of1ForFork1_#res.offset=|v_P3Thread1of1ForFork1_#res.offset_3|, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_27|} AuxVars[] AssignedVars[~y$r_buff1_thd4~0, P3Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork1_#res.offset, P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 10:38:11,160 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L843-->L845-2: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (or (= (mod v_~y$w_buff0_used~0_216 256) 0) (= 0 (mod v_~y$r_buff0_thd0~0_104 256)))) InVars {~y$w_buff0_used~0=v_~y$w_buff0_used~0_216, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} OutVars{~y$w_buff0_used~0=v_~y$w_buff0_used~0_216, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 10:38:11,160 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L845-2-->L845-5: Formula: (let ((.cse1 (= |ULTIMATE.start_main_#t~ite26_Out-421721701| |ULTIMATE.start_main_#t~ite25_Out-421721701|)) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-421721701 256))) (.cse2 (= (mod ~y$w_buff1_used~0_In-421721701 256) 0))) (or (and (not .cse0) .cse1 (= |ULTIMATE.start_main_#t~ite25_Out-421721701| ~y$w_buff1~0_In-421721701) (not .cse2)) (and .cse1 (or .cse0 .cse2) (= |ULTIMATE.start_main_#t~ite25_Out-421721701| ~y~0_In-421721701)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-421721701, ~y~0=~y~0_In-421721701, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-421721701, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-421721701} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-421721701, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-421721701|, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-421721701|, ~y~0=~y~0_In-421721701, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-421721701, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-421721701} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 10:38:11,160 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [797] [797] L846-->L846-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1208136471 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-1208136471 256)))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite27_Out-1208136471|) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite27_Out-1208136471| ~y$w_buff0_used~0_In-1208136471) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1208136471, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1208136471} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1208136471, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1208136471, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-1208136471|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 10:38:11,161 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L847-->L847-2: Formula: (let ((.cse2 (= (mod ~y$w_buff0_used~0_In-1259013035 256) 0)) (.cse3 (= 0 (mod ~y$r_buff0_thd0~0_In-1259013035 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In-1259013035 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-1259013035 256)))) (or (and (= ~y$w_buff1_used~0_In-1259013035 |ULTIMATE.start_main_#t~ite28_Out-1259013035|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |ULTIMATE.start_main_#t~ite28_Out-1259013035|) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1259013035, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1259013035, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1259013035, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1259013035} OutVars{ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out-1259013035|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1259013035, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1259013035, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1259013035, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1259013035} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 10:38:11,161 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [812] [812] L848-->L848-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1426510303 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-1426510303 256)))) (or (and (= |ULTIMATE.start_main_#t~ite29_Out-1426510303| ~y$r_buff0_thd0~0_In-1426510303) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite29_Out-1426510303| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1426510303, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1426510303} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1426510303, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-1426510303|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1426510303} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 10:38:11,161 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [790] [790] L849-->L849-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In87595741 256))) (.cse1 (= (mod ~y$w_buff1_used~0_In87595741 256) 0)) (.cse3 (= (mod ~y$w_buff0_used~0_In87595741 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd0~0_In87595741 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite30_Out87595741| ~y$r_buff1_thd0~0_In87595741)) (and (= |ULTIMATE.start_main_#t~ite30_Out87595741| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In87595741, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In87595741, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In87595741, ~y$w_buff1_used~0=~y$w_buff1_used~0_In87595741} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out87595741|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In87595741, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In87595741, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In87595741, ~y$w_buff1_used~0=~y$w_buff1_used~0_In87595741} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30] because there is no mapped edge [2019-12-07 10:38:11,163 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [852] [852] L858-->L858-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-1229006778 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite40_Out-1229006778| ~y$w_buff1~0_In-1229006778) (= |ULTIMATE.start_main_#t~ite39_In-1229006778| |ULTIMATE.start_main_#t~ite39_Out-1229006778|)) (and (= ~y$w_buff1~0_In-1229006778 |ULTIMATE.start_main_#t~ite39_Out-1229006778|) (= |ULTIMATE.start_main_#t~ite40_Out-1229006778| |ULTIMATE.start_main_#t~ite39_Out-1229006778|) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-1229006778 256) 0))) (or (= 0 (mod ~y$w_buff0_used~0_In-1229006778 256)) (and (= 0 (mod ~y$w_buff1_used~0_In-1229006778 256)) .cse1) (and (= 0 (mod ~y$r_buff1_thd0~0_In-1229006778 256)) .cse1))) .cse0))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1229006778, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1229006778, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_In-1229006778|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1229006778, ~weak$$choice2~0=~weak$$choice2~0_In-1229006778, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1229006778, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1229006778} OutVars{ULTIMATE.start_main_#t~ite40=|ULTIMATE.start_main_#t~ite40_Out-1229006778|, ~y$w_buff1~0=~y$w_buff1~0_In-1229006778, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1229006778, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out-1229006778|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1229006778, ~weak$$choice2~0=~weak$$choice2~0_In-1229006778, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1229006778, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1229006778} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 10:38:11,163 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L859-->L859-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In1966669572 256)))) (or (and (= |ULTIMATE.start_main_#t~ite43_Out1966669572| ~y$w_buff0_used~0_In1966669572) (= |ULTIMATE.start_main_#t~ite42_In1966669572| |ULTIMATE.start_main_#t~ite42_Out1966669572|) (not .cse0)) (and (= ~y$w_buff0_used~0_In1966669572 |ULTIMATE.start_main_#t~ite42_Out1966669572|) .cse0 (= |ULTIMATE.start_main_#t~ite43_Out1966669572| |ULTIMATE.start_main_#t~ite42_Out1966669572|) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In1966669572 256)))) (or (and (= 0 (mod ~y$w_buff1_used~0_In1966669572 256)) .cse1) (= 0 (mod ~y$w_buff0_used~0_In1966669572 256)) (and (= (mod ~y$r_buff1_thd0~0_In1966669572 256) 0) .cse1)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1966669572, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1966669572, ~weak$$choice2~0=~weak$$choice2~0_In1966669572, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1966669572, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_In1966669572|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1966669572} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1966669572, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1966669572, ULTIMATE.start_main_#t~ite43=|ULTIMATE.start_main_#t~ite43_Out1966669572|, ~weak$$choice2~0=~weak$$choice2~0_In1966669572, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_Out1966669572|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1966669572, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1966669572} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 10:38:11,164 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [865] [865] L860-->L860-8: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In1738256568 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In1738256568 256))) (.cse5 (= 0 (mod ~y$r_buff1_thd0~0_In1738256568 256))) (.cse6 (= 0 (mod ~y$r_buff0_thd0~0_In1738256568 256))) (.cse4 (= |ULTIMATE.start_main_#t~ite46_Out1738256568| |ULTIMATE.start_main_#t~ite45_Out1738256568|)) (.cse3 (= (mod ~weak$$choice2~0_In1738256568 256) 0))) (or (let ((.cse1 (not .cse6))) (and (or (not .cse0) .cse1) (not .cse2) .cse3 (= |ULTIMATE.start_main_#t~ite44_Out1738256568| 0) .cse4 (or (not .cse5) .cse1) (= |ULTIMATE.start_main_#t~ite44_Out1738256568| |ULTIMATE.start_main_#t~ite45_Out1738256568|))) (and (or (and .cse3 (= ~y$w_buff1_used~0_In1738256568 |ULTIMATE.start_main_#t~ite45_Out1738256568|) (or (and .cse0 .cse6) .cse2 (and .cse5 .cse6)) .cse4) (and (= |ULTIMATE.start_main_#t~ite45_In1738256568| |ULTIMATE.start_main_#t~ite45_Out1738256568|) (= |ULTIMATE.start_main_#t~ite46_Out1738256568| ~y$w_buff1_used~0_In1738256568) (not .cse3))) (= |ULTIMATE.start_main_#t~ite44_In1738256568| |ULTIMATE.start_main_#t~ite44_Out1738256568|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1738256568, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1738256568, ~weak$$choice2~0=~weak$$choice2~0_In1738256568, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1738256568, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In1738256568|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1738256568, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_In1738256568|} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1738256568, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1738256568, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out1738256568|, ~weak$$choice2~0=~weak$$choice2~0_In1738256568, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1738256568, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out1738256568|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1738256568, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_Out1738256568|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-12-07 10:38:11,164 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [868] [868] L860-8-->L862: Formula: (and (not (= (mod v_~weak$$choice2~0_106 256) 0)) (= v_~y$w_buff1_used~0_383 |v_ULTIMATE.start_main_#t~ite46_36|) (= v_~y$r_buff0_thd0~0_352 v_~y$r_buff0_thd0~0_351)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_352, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~weak$$choice2~0=v_~weak$$choice2~0_106} OutVars{~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_351, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_35|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_31|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_34|, ~weak$$choice2~0=v_~weak$$choice2~0_106, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_33|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_383} AuxVars[] AssignedVars[~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 10:38:11,164 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L864-->L4: Formula: (and (= 0 v_~y$flush_delayed~0_25) (= v_~y~0_116 v_~y$mem_tmp~0_11) (not (= (mod v_~y$flush_delayed~0_26 256) 0)) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5| (mod v_~main$tmp_guard1~0_15 256))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_26, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_11, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ~y$flush_delayed~0=v_~y$flush_delayed~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15, ~y~0=v_~y~0_116, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_23|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ~y~0, ULTIMATE.start_main_#t~ite53, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 10:38:11,164 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 10:38:11,225 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_b2944d01-8133-423d-a01f-2142f92440a1/bin/uautomizer/witness.graphml [2019-12-07 10:38:11,226 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 10:38:11,227 INFO L168 Benchmark]: Toolchain (without parser) took 173800.84 ms. Allocated memory was 1.0 GB in the beginning and 9.5 GB in the end (delta: 8.5 GB). Free memory was 938.1 MB in the beginning and 5.2 GB in the end (delta: -4.3 GB). Peak memory consumption was 4.2 GB. Max. memory is 11.5 GB. [2019-12-07 10:38:11,227 INFO L168 Benchmark]: CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 10:38:11,227 INFO L168 Benchmark]: CACSL2BoogieTranslator took 439.46 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 161.5 MB). Free memory was 938.1 MB in the beginning and 1.1 GB in the end (delta: -181.7 MB). Peak memory consumption was 18.5 MB. Max. memory is 11.5 GB. [2019-12-07 10:38:11,227 INFO L168 Benchmark]: Boogie Procedure Inliner took 51.24 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 10:38:11,228 INFO L168 Benchmark]: Boogie Preprocessor took 31.75 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 11.5 GB. [2019-12-07 10:38:11,228 INFO L168 Benchmark]: RCFGBuilder took 431.96 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 61.3 MB). Peak memory consumption was 61.3 MB. Max. memory is 11.5 GB. [2019-12-07 10:38:11,228 INFO L168 Benchmark]: TraceAbstraction took 172767.82 ms. Allocated memory was 1.2 GB in the beginning and 9.5 GB in the end (delta: 8.4 GB). Free memory was 1.1 GB in the beginning and 5.3 GB in the end (delta: -4.2 GB). Peak memory consumption was 4.2 GB. Max. memory is 11.5 GB. [2019-12-07 10:38:11,228 INFO L168 Benchmark]: Witness Printer took 75.44 ms. Allocated memory is still 9.5 GB. Free memory was 5.3 GB in the beginning and 5.2 GB in the end (delta: 37.8 MB). Peak memory consumption was 37.8 MB. Max. memory is 11.5 GB. [2019-12-07 10:38:11,230 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 439.46 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 161.5 MB). Free memory was 938.1 MB in the beginning and 1.1 GB in the end (delta: -181.7 MB). Peak memory consumption was 18.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 51.24 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 31.75 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 11.5 GB. * RCFGBuilder took 431.96 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 61.3 MB). Peak memory consumption was 61.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 172767.82 ms. Allocated memory was 1.2 GB in the beginning and 9.5 GB in the end (delta: 8.4 GB). Free memory was 1.1 GB in the beginning and 5.3 GB in the end (delta: -4.2 GB). Peak memory consumption was 4.2 GB. Max. memory is 11.5 GB. * Witness Printer took 75.44 ms. Allocated memory is still 9.5 GB. Free memory was 5.3 GB in the beginning and 5.2 GB in the end (delta: 37.8 MB). Peak memory consumption was 37.8 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.3s, 192 ProgramPointsBefore, 97 ProgramPointsAfterwards, 226 TransitionsBefore, 103 TransitionsAfterwards, 18432 CoEnabledTransitionPairs, 8 FixpointIterations, 36 TrivialSequentialCompositions, 54 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 37 ConcurrentYvCompositions, 33 ChoiceCompositions, 6018 VarBasedMoverChecksPositive, 223 VarBasedMoverChecksNegative, 64 SemBasedMoverChecksPositive, 227 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.7s, 0 MoverChecksTotal, 86545 CheckedPairsTotal, 127 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L833] FCALL, FORK 0 pthread_create(&t781, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L835] FCALL, FORK 0 pthread_create(&t782, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L837] FCALL, FORK 0 pthread_create(&t783, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L776] 3 y$r_buff1_thd0 = y$r_buff0_thd0 [L777] 3 y$r_buff1_thd1 = y$r_buff0_thd1 [L778] 3 y$r_buff1_thd2 = y$r_buff0_thd2 [L779] 3 y$r_buff1_thd3 = y$r_buff0_thd3 [L780] 3 y$r_buff1_thd4 = y$r_buff0_thd4 [L781] 3 y$r_buff0_thd3 = (_Bool)1 [L784] 3 z = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L839] FCALL, FORK 0 pthread_create(&t784, ((void *)0), P3, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L801] 4 z = 2 [L804] 4 __unbuffered_p3_EAX = z [L807] 4 __unbuffered_p3_EBX = a VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L810] 4 y$w_buff0_used && y$r_buff0_thd4 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd4 ? y$w_buff1 : y) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L751] 2 x = 1 [L754] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L757] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L757] 2 y = y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) [L758] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L811] 4 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd4 ? (_Bool)0 : y$w_buff0_used [L812] 4 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd4 || y$w_buff1_used && y$r_buff1_thd4 ? (_Bool)0 : y$w_buff1_used [L787] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L759] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L760] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L787] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L788] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L789] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L813] 4 y$r_buff0_thd4 = y$w_buff0_used && y$r_buff0_thd4 ? (_Bool)0 : y$r_buff0_thd4 [L841] 0 main$tmp_guard0 = __unbuffered_cnt == 4 VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L845] 0 y = y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L846] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L847] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L848] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L849] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L852] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L853] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L854] 0 y$flush_delayed = weak$$choice2 [L855] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L856] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L856] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L857] EXPR 0 weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L857] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L858] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L859] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L862] EXPR 0 weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L862] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L863] 0 main$tmp_guard1 = !(y == 2 && z == 2 && __unbuffered_p0_EAX == 0 && __unbuffered_p3_EAX == 2 && __unbuffered_p3_EBX == 0) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 180 locations, 2 error locations. Result: UNSAFE, OverallTime: 172.6s, OverallIterations: 25, TraceHistogramMax: 1, AutomataDifference: 40.3s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 3842 SDtfs, 3943 SDslu, 7914 SDs, 0 SdLazy, 4932 SolverSat, 247 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 231 GetRequests, 61 SyntacticMatches, 31 SemanticMatches, 139 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 142 ImplicationChecksByTransitivity, 0.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=389200occurred in iteration=5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 90.7s AutomataMinimizationTime, 24 MinimizatonAttempts, 357052 StatesRemovedByMinimization, 19 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.1s InterpolantComputationTime, 1228 NumberOfCodeBlocks, 1228 NumberOfCodeBlocksAsserted, 25 NumberOfCheckSat, 1134 ConstructedInterpolants, 0 QuantifiedInterpolants, 195396 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 24 InterpolantComputations, 24 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...