./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix029_rmo.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_53904900-9218-4a81-b471-d6270c803fb1/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_53904900-9218-4a81-b471-d6270c803fb1/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_53904900-9218-4a81-b471-d6270c803fb1/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_53904900-9218-4a81-b471-d6270c803fb1/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix029_rmo.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_53904900-9218-4a81-b471-d6270c803fb1/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_53904900-9218-4a81-b471-d6270c803fb1/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash fc8913eb63dfe6eed6e7ae85c6e9ebe4b7b9d18c ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 13:23:22,920 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 13:23:22,922 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 13:23:22,931 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 13:23:22,931 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 13:23:22,932 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 13:23:22,933 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 13:23:22,935 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 13:23:22,936 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 13:23:22,937 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 13:23:22,937 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 13:23:22,938 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 13:23:22,938 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 13:23:22,939 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 13:23:22,940 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 13:23:22,940 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 13:23:22,941 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 13:23:22,942 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 13:23:22,943 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 13:23:22,944 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 13:23:22,946 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 13:23:22,946 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 13:23:22,947 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 13:23:22,947 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 13:23:22,949 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 13:23:22,949 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 13:23:22,949 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 13:23:22,950 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 13:23:22,950 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 13:23:22,951 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 13:23:22,951 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 13:23:22,951 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 13:23:22,952 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 13:23:22,953 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 13:23:22,953 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 13:23:22,954 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 13:23:22,954 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 13:23:22,954 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 13:23:22,954 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 13:23:22,955 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 13:23:22,956 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 13:23:22,956 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_53904900-9218-4a81-b471-d6270c803fb1/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 13:23:22,969 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 13:23:22,969 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 13:23:22,970 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 13:23:22,970 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 13:23:22,971 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 13:23:22,971 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 13:23:22,971 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 13:23:22,971 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 13:23:22,971 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 13:23:22,972 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 13:23:22,972 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 13:23:22,972 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 13:23:22,972 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 13:23:22,972 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 13:23:22,973 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 13:23:22,973 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 13:23:22,973 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 13:23:22,973 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 13:23:22,973 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 13:23:22,974 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 13:23:22,974 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 13:23:22,974 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 13:23:22,974 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 13:23:22,974 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 13:23:22,975 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 13:23:22,975 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 13:23:22,975 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 13:23:22,975 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 13:23:22,975 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 13:23:22,976 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_53904900-9218-4a81-b471-d6270c803fb1/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> fc8913eb63dfe6eed6e7ae85c6e9ebe4b7b9d18c [2019-12-07 13:23:23,090 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 13:23:23,098 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 13:23:23,100 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 13:23:23,101 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 13:23:23,101 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 13:23:23,102 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_53904900-9218-4a81-b471-d6270c803fb1/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix029_rmo.opt.i [2019-12-07 13:23:23,139 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_53904900-9218-4a81-b471-d6270c803fb1/bin/uautomizer/data/3778459e2/20b769a48d6c43f980d68b30b759b332/FLAG2fea83ef0 [2019-12-07 13:23:23,513 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 13:23:23,513 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_53904900-9218-4a81-b471-d6270c803fb1/sv-benchmarks/c/pthread-wmm/mix029_rmo.opt.i [2019-12-07 13:23:23,525 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_53904900-9218-4a81-b471-d6270c803fb1/bin/uautomizer/data/3778459e2/20b769a48d6c43f980d68b30b759b332/FLAG2fea83ef0 [2019-12-07 13:23:23,534 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_53904900-9218-4a81-b471-d6270c803fb1/bin/uautomizer/data/3778459e2/20b769a48d6c43f980d68b30b759b332 [2019-12-07 13:23:23,535 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 13:23:23,536 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 13:23:23,537 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 13:23:23,537 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 13:23:23,539 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 13:23:23,540 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 01:23:23" (1/1) ... [2019-12-07 13:23:23,541 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@355b5b5c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:23, skipping insertion in model container [2019-12-07 13:23:23,542 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 01:23:23" (1/1) ... [2019-12-07 13:23:23,546 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 13:23:23,574 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 13:23:23,821 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 13:23:23,829 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 13:23:23,873 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 13:23:23,919 INFO L208 MainTranslator]: Completed translation [2019-12-07 13:23:23,919 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:23 WrapperNode [2019-12-07 13:23:23,919 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 13:23:23,920 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 13:23:23,920 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 13:23:23,920 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 13:23:23,926 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:23" (1/1) ... [2019-12-07 13:23:23,940 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:23" (1/1) ... [2019-12-07 13:23:23,962 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 13:23:23,962 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 13:23:23,962 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 13:23:23,962 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 13:23:23,969 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:23" (1/1) ... [2019-12-07 13:23:23,969 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:23" (1/1) ... [2019-12-07 13:23:23,973 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:23" (1/1) ... [2019-12-07 13:23:23,973 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:23" (1/1) ... [2019-12-07 13:23:23,981 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:23" (1/1) ... [2019-12-07 13:23:23,984 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:23" (1/1) ... [2019-12-07 13:23:23,987 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:23" (1/1) ... [2019-12-07 13:23:23,991 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 13:23:23,991 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 13:23:23,991 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 13:23:23,991 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 13:23:23,992 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:23" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_53904900-9218-4a81-b471-d6270c803fb1/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 13:23:24,036 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 13:23:24,037 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 13:23:24,037 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 13:23:24,037 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 13:23:24,037 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 13:23:24,037 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 13:23:24,037 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 13:23:24,037 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 13:23:24,037 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 13:23:24,037 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 13:23:24,037 INFO L130 BoogieDeclarations]: Found specification of procedure P3 [2019-12-07 13:23:24,037 INFO L138 BoogieDeclarations]: Found implementation of procedure P3 [2019-12-07 13:23:24,037 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 13:23:24,038 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 13:23:24,038 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 13:23:24,039 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 13:23:24,419 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 13:23:24,419 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 13:23:24,420 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 01:23:24 BoogieIcfgContainer [2019-12-07 13:23:24,420 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 13:23:24,421 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 13:23:24,421 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 13:23:24,423 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 13:23:24,423 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 01:23:23" (1/3) ... [2019-12-07 13:23:24,424 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@203fef86 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 01:23:24, skipping insertion in model container [2019-12-07 13:23:24,424 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:23:23" (2/3) ... [2019-12-07 13:23:24,424 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@203fef86 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 01:23:24, skipping insertion in model container [2019-12-07 13:23:24,424 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 01:23:24" (3/3) ... [2019-12-07 13:23:24,425 INFO L109 eAbstractionObserver]: Analyzing ICFG mix029_rmo.opt.i [2019-12-07 13:23:24,432 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 13:23:24,432 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 13:23:24,437 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 13:23:24,438 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 13:23:24,465 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,465 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,466 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,466 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,466 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,466 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,466 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,467 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,467 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork3_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,467 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork3_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,467 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,467 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,467 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,467 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,467 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,468 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,468 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,468 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,468 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,468 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,468 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,468 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,469 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,469 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,469 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,469 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,469 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,470 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,470 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,470 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,470 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,470 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,470 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,471 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,471 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,471 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,472 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,472 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,472 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,472 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,472 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,472 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,473 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,473 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,473 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,473 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,473 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,473 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,473 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,473 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,474 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,474 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,474 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,474 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,474 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,474 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,474 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,475 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,475 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,475 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,475 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,475 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,475 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,476 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,476 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,476 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,476 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,476 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,476 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,476 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,477 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,477 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,477 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,477 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,477 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,477 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,477 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,477 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,478 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,478 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,478 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,478 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,478 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,478 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,478 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,479 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,479 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,479 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,479 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,479 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,479 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,479 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,479 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,480 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,480 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,480 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,480 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,480 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,480 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,481 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:23:24,493 INFO L249 AbstractCegarLoop]: Starting to check reachability of 7 error locations. [2019-12-07 13:23:24,506 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 13:23:24,506 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 13:23:24,506 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 13:23:24,506 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 13:23:24,506 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 13:23:24,506 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 13:23:24,506 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 13:23:24,506 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 13:23:24,519 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 192 places, 226 transitions [2019-12-07 13:23:24,520 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 192 places, 226 transitions [2019-12-07 13:23:24,585 INFO L134 PetriNetUnfolder]: 47/222 cut-off events. [2019-12-07 13:23:24,585 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 13:23:24,596 INFO L76 FinitePrefix]: Finished finitePrefix Result has 235 conditions, 222 events. 47/222 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 586 event pairs. 12/185 useless extension candidates. Maximal degree in co-relation 190. Up to 2 conditions per place. [2019-12-07 13:23:24,613 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 192 places, 226 transitions [2019-12-07 13:23:24,642 INFO L134 PetriNetUnfolder]: 47/222 cut-off events. [2019-12-07 13:23:24,643 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 13:23:24,648 INFO L76 FinitePrefix]: Finished finitePrefix Result has 235 conditions, 222 events. 47/222 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 586 event pairs. 12/185 useless extension candidates. Maximal degree in co-relation 190. Up to 2 conditions per place. [2019-12-07 13:23:24,663 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 18432 [2019-12-07 13:23:24,664 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 13:23:27,791 WARN L192 SmtUtils]: Spent 173.00 ms on a formula simplification. DAG size of input: 97 DAG size of output: 95 [2019-12-07 13:23:27,903 INFO L206 etLargeBlockEncoding]: Checked pairs total: 86545 [2019-12-07 13:23:27,903 INFO L214 etLargeBlockEncoding]: Total number of compositions: 127 [2019-12-07 13:23:27,905 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 97 places, 103 transitions [2019-12-07 13:24:06,056 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 199530 states. [2019-12-07 13:24:06,058 INFO L276 IsEmpty]: Start isEmpty. Operand 199530 states. [2019-12-07 13:24:06,062 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-12-07 13:24:06,062 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:24:06,062 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:24:06,063 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:24:06,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:24:06,066 INFO L82 PathProgramCache]: Analyzing trace with hash 1574015469, now seen corresponding path program 1 times [2019-12-07 13:24:06,072 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:24:06,072 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [601475387] [2019-12-07 13:24:06,072 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:24:06,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:24:06,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:24:06,226 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [601475387] [2019-12-07 13:24:06,226 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:24:06,226 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 13:24:06,227 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1710267386] [2019-12-07 13:24:06,229 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 13:24:06,230 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:24:06,238 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:24:06,239 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:24:06,240 INFO L87 Difference]: Start difference. First operand 199530 states. Second operand 3 states. [2019-12-07 13:24:07,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:24:07,705 INFO L93 Difference]: Finished difference Result 198930 states and 939730 transitions. [2019-12-07 13:24:07,706 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:24:07,707 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-12-07 13:24:07,708 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:24:08,546 INFO L225 Difference]: With dead ends: 198930 [2019-12-07 13:24:08,546 INFO L226 Difference]: Without dead ends: 194562 [2019-12-07 13:24:08,547 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:24:17,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 194562 states. [2019-12-07 13:24:20,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 194562 to 194562. [2019-12-07 13:24:20,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194562 states. [2019-12-07 13:24:21,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194562 states to 194562 states and 919710 transitions. [2019-12-07 13:24:21,409 INFO L78 Accepts]: Start accepts. Automaton has 194562 states and 919710 transitions. Word has length 7 [2019-12-07 13:24:21,409 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:24:21,410 INFO L462 AbstractCegarLoop]: Abstraction has 194562 states and 919710 transitions. [2019-12-07 13:24:21,410 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 13:24:21,410 INFO L276 IsEmpty]: Start isEmpty. Operand 194562 states and 919710 transitions. [2019-12-07 13:24:21,413 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 13:24:21,413 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:24:21,413 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:24:21,414 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:24:21,414 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:24:21,414 INFO L82 PathProgramCache]: Analyzing trace with hash 1968556431, now seen corresponding path program 1 times [2019-12-07 13:24:21,414 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:24:21,414 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1387613613] [2019-12-07 13:24:21,414 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:24:21,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:24:21,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:24:21,482 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1387613613] [2019-12-07 13:24:21,482 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:24:21,482 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:24:21,482 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1001678472] [2019-12-07 13:24:21,483 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 13:24:21,483 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:24:21,483 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 13:24:21,484 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 13:24:21,484 INFO L87 Difference]: Start difference. First operand 194562 states and 919710 transitions. Second operand 4 states. [2019-12-07 13:24:26,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:24:26,327 INFO L93 Difference]: Finished difference Result 312518 states and 1424536 transitions. [2019-12-07 13:24:26,327 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 13:24:26,327 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 13:24:26,328 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:24:27,269 INFO L225 Difference]: With dead ends: 312518 [2019-12-07 13:24:27,269 INFO L226 Difference]: Without dead ends: 312420 [2019-12-07 13:24:27,270 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:24:35,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312420 states. [2019-12-07 13:24:39,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312420 to 280564. [2019-12-07 13:24:39,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280564 states. [2019-12-07 13:24:40,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280564 states to 280564 states and 1291349 transitions. [2019-12-07 13:24:40,849 INFO L78 Accepts]: Start accepts. Automaton has 280564 states and 1291349 transitions. Word has length 13 [2019-12-07 13:24:40,849 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:24:40,849 INFO L462 AbstractCegarLoop]: Abstraction has 280564 states and 1291349 transitions. [2019-12-07 13:24:40,849 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 13:24:40,849 INFO L276 IsEmpty]: Start isEmpty. Operand 280564 states and 1291349 transitions. [2019-12-07 13:24:40,854 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 13:24:40,854 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:24:40,854 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:24:40,854 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:24:40,854 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:24:40,854 INFO L82 PathProgramCache]: Analyzing trace with hash 381664219, now seen corresponding path program 1 times [2019-12-07 13:24:40,855 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:24:40,855 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1495669365] [2019-12-07 13:24:40,855 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:24:40,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:24:40,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:24:40,907 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1495669365] [2019-12-07 13:24:40,907 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:24:40,907 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:24:40,908 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [780457789] [2019-12-07 13:24:40,908 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 13:24:40,908 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:24:40,908 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 13:24:40,908 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 13:24:40,908 INFO L87 Difference]: Start difference. First operand 280564 states and 1291349 transitions. Second operand 4 states. [2019-12-07 13:24:46,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:24:46,399 INFO L93 Difference]: Finished difference Result 400666 states and 1806688 transitions. [2019-12-07 13:24:46,399 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 13:24:46,399 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 13:24:46,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:24:47,937 INFO L225 Difference]: With dead ends: 400666 [2019-12-07 13:24:47,937 INFO L226 Difference]: Without dead ends: 400540 [2019-12-07 13:24:47,937 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:24:57,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 400540 states. [2019-12-07 13:25:02,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 400540 to 335984. [2019-12-07 13:25:02,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 335984 states. [2019-12-07 13:25:03,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 335984 states to 335984 states and 1536425 transitions. [2019-12-07 13:25:03,998 INFO L78 Accepts]: Start accepts. Automaton has 335984 states and 1536425 transitions. Word has length 15 [2019-12-07 13:25:03,998 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:25:03,999 INFO L462 AbstractCegarLoop]: Abstraction has 335984 states and 1536425 transitions. [2019-12-07 13:25:03,999 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 13:25:03,999 INFO L276 IsEmpty]: Start isEmpty. Operand 335984 states and 1536425 transitions. [2019-12-07 13:25:04,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 13:25:04,002 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:25:04,002 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:25:04,002 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:25:04,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:25:04,002 INFO L82 PathProgramCache]: Analyzing trace with hash 1895054000, now seen corresponding path program 1 times [2019-12-07 13:25:04,003 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:25:04,003 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052722338] [2019-12-07 13:25:04,003 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:25:04,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:25:04,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:25:04,663 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2052722338] [2019-12-07 13:25:04,663 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:25:04,663 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:25:04,664 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1438431935] [2019-12-07 13:25:04,664 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 13:25:04,664 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:25:04,664 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 13:25:04,664 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 13:25:04,664 INFO L87 Difference]: Start difference. First operand 335984 states and 1536425 transitions. Second operand 4 states. [2019-12-07 13:25:11,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:25:11,366 INFO L93 Difference]: Finished difference Result 416162 states and 1884830 transitions. [2019-12-07 13:25:11,367 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 13:25:11,367 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 13:25:11,367 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:25:12,679 INFO L225 Difference]: With dead ends: 416162 [2019-12-07 13:25:12,679 INFO L226 Difference]: Without dead ends: 416162 [2019-12-07 13:25:12,680 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:25:22,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 416162 states. [2019-12-07 13:25:28,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 416162 to 354242. [2019-12-07 13:25:28,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 354242 states. [2019-12-07 13:25:29,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 354242 states to 354242 states and 1619952 transitions. [2019-12-07 13:25:29,579 INFO L78 Accepts]: Start accepts. Automaton has 354242 states and 1619952 transitions. Word has length 15 [2019-12-07 13:25:29,579 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:25:29,579 INFO L462 AbstractCegarLoop]: Abstraction has 354242 states and 1619952 transitions. [2019-12-07 13:25:29,579 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 13:25:29,579 INFO L276 IsEmpty]: Start isEmpty. Operand 354242 states and 1619952 transitions. [2019-12-07 13:25:29,606 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 13:25:29,607 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:25:29,607 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:25:29,607 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:25:29,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:25:29,607 INFO L82 PathProgramCache]: Analyzing trace with hash -244633219, now seen corresponding path program 1 times [2019-12-07 13:25:29,607 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:25:29,607 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1078576098] [2019-12-07 13:25:29,608 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:25:29,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:25:29,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:25:29,667 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1078576098] [2019-12-07 13:25:29,667 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:25:29,667 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:25:29,668 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [498773529] [2019-12-07 13:25:29,668 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 13:25:29,668 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:25:29,668 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:25:29,668 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:25:29,669 INFO L87 Difference]: Start difference. First operand 354242 states and 1619952 transitions. Second operand 5 states. [2019-12-07 13:25:37,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:25:37,954 INFO L93 Difference]: Finished difference Result 524522 states and 2349272 transitions. [2019-12-07 13:25:37,955 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 13:25:37,955 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2019-12-07 13:25:37,955 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:25:39,536 INFO L225 Difference]: With dead ends: 524522 [2019-12-07 13:25:39,536 INFO L226 Difference]: Without dead ends: 524242 [2019-12-07 13:25:39,537 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 13:25:50,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 524242 states. [2019-12-07 13:25:57,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 524242 to 389200. [2019-12-07 13:25:57,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 389200 states. [2019-12-07 13:25:59,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389200 states to 389200 states and 1771393 transitions. [2019-12-07 13:25:59,001 INFO L78 Accepts]: Start accepts. Automaton has 389200 states and 1771393 transitions. Word has length 21 [2019-12-07 13:25:59,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:25:59,001 INFO L462 AbstractCegarLoop]: Abstraction has 389200 states and 1771393 transitions. [2019-12-07 13:25:59,001 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 13:25:59,001 INFO L276 IsEmpty]: Start isEmpty. Operand 389200 states and 1771393 transitions. [2019-12-07 13:25:59,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 13:25:59,024 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:25:59,024 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:25:59,024 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:25:59,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:25:59,025 INFO L82 PathProgramCache]: Analyzing trace with hash 1268756562, now seen corresponding path program 1 times [2019-12-07 13:25:59,025 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:25:59,025 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [971326881] [2019-12-07 13:25:59,025 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:25:59,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:25:59,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:25:59,075 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [971326881] [2019-12-07 13:25:59,075 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:25:59,075 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:25:59,075 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2061640827] [2019-12-07 13:25:59,076 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 13:25:59,076 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:25:59,076 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:25:59,076 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:25:59,076 INFO L87 Difference]: Start difference. First operand 389200 states and 1771393 transitions. Second operand 5 states. [2019-12-07 13:26:07,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:26:07,529 INFO L93 Difference]: Finished difference Result 563484 states and 2519221 transitions. [2019-12-07 13:26:07,530 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 13:26:07,530 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2019-12-07 13:26:07,530 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:26:09,235 INFO L225 Difference]: With dead ends: 563484 [2019-12-07 13:26:09,235 INFO L226 Difference]: Without dead ends: 563358 [2019-12-07 13:26:09,236 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 13:26:20,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 563358 states. [2019-12-07 13:26:27,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 563358 to 395636. [2019-12-07 13:26:27,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 395636 states. [2019-12-07 13:26:30,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 395636 states to 395636 states and 1799759 transitions. [2019-12-07 13:26:30,034 INFO L78 Accepts]: Start accepts. Automaton has 395636 states and 1799759 transitions. Word has length 21 [2019-12-07 13:26:30,034 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:26:30,034 INFO L462 AbstractCegarLoop]: Abstraction has 395636 states and 1799759 transitions. [2019-12-07 13:26:30,034 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 13:26:30,034 INFO L276 IsEmpty]: Start isEmpty. Operand 395636 states and 1799759 transitions. [2019-12-07 13:26:30,062 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 13:26:30,062 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:26:30,062 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:26:30,062 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:26:30,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:26:30,062 INFO L82 PathProgramCache]: Analyzing trace with hash -402177574, now seen corresponding path program 1 times [2019-12-07 13:26:30,063 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:26:30,063 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [111079070] [2019-12-07 13:26:30,063 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:26:30,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:26:30,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:26:30,124 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [111079070] [2019-12-07 13:26:30,124 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:26:30,124 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:26:30,124 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1008745587] [2019-12-07 13:26:30,124 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 13:26:30,124 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:26:30,125 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:26:30,125 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:26:30,125 INFO L87 Difference]: Start difference. First operand 395636 states and 1799759 transitions. Second operand 5 states. [2019-12-07 13:26:37,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:26:37,916 INFO L93 Difference]: Finished difference Result 577196 states and 2584233 transitions. [2019-12-07 13:26:37,917 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 13:26:37,917 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2019-12-07 13:26:37,917 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:26:40,070 INFO L225 Difference]: With dead ends: 577196 [2019-12-07 13:26:40,070 INFO L226 Difference]: Without dead ends: 577070 [2019-12-07 13:26:40,070 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 13:26:51,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 577070 states. [2019-12-07 13:26:59,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 577070 to 423132. [2019-12-07 13:26:59,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 423132 states. [2019-12-07 13:27:01,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 423132 states to 423132 states and 1922787 transitions. [2019-12-07 13:27:01,148 INFO L78 Accepts]: Start accepts. Automaton has 423132 states and 1922787 transitions. Word has length 21 [2019-12-07 13:27:01,149 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:01,149 INFO L462 AbstractCegarLoop]: Abstraction has 423132 states and 1922787 transitions. [2019-12-07 13:27:01,149 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 13:27:01,149 INFO L276 IsEmpty]: Start isEmpty. Operand 423132 states and 1922787 transitions. [2019-12-07 13:27:01,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 13:27:01,267 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:01,267 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:01,267 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:01,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:01,267 INFO L82 PathProgramCache]: Analyzing trace with hash -1992788484, now seen corresponding path program 1 times [2019-12-07 13:27:01,268 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:01,268 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [777954465] [2019-12-07 13:27:01,268 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:01,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:01,319 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:01,319 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [777954465] [2019-12-07 13:27:01,319 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:01,319 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:27:01,319 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [501278372] [2019-12-07 13:27:01,319 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 13:27:01,319 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:01,320 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 13:27:01,320 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 13:27:01,320 INFO L87 Difference]: Start difference. First operand 423132 states and 1922787 transitions. Second operand 4 states. [2019-12-07 13:27:03,299 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:03,299 INFO L93 Difference]: Finished difference Result 262865 states and 1064265 transitions. [2019-12-07 13:27:03,300 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 13:27:03,300 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 27 [2019-12-07 13:27:03,300 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:03,994 INFO L225 Difference]: With dead ends: 262865 [2019-12-07 13:27:03,995 INFO L226 Difference]: Without dead ends: 251817 [2019-12-07 13:27:03,995 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:27:12,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 251817 states. [2019-12-07 13:27:16,331 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 251817 to 251817. [2019-12-07 13:27:16,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 251817 states. [2019-12-07 13:27:17,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 251817 states to 251817 states and 1023003 transitions. [2019-12-07 13:27:17,130 INFO L78 Accepts]: Start accepts. Automaton has 251817 states and 1023003 transitions. Word has length 27 [2019-12-07 13:27:17,130 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:17,130 INFO L462 AbstractCegarLoop]: Abstraction has 251817 states and 1023003 transitions. [2019-12-07 13:27:17,130 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 13:27:17,130 INFO L276 IsEmpty]: Start isEmpty. Operand 251817 states and 1023003 transitions. [2019-12-07 13:27:17,179 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 13:27:17,179 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:17,179 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:17,179 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:17,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:17,179 INFO L82 PathProgramCache]: Analyzing trace with hash 1827943700, now seen corresponding path program 1 times [2019-12-07 13:27:17,180 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:17,180 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [679423982] [2019-12-07 13:27:17,180 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:17,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:17,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:17,225 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [679423982] [2019-12-07 13:27:17,226 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:17,226 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 13:27:17,226 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1282150868] [2019-12-07 13:27:17,226 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 13:27:17,226 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:17,226 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:27:17,226 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:27:17,226 INFO L87 Difference]: Start difference. First operand 251817 states and 1023003 transitions. Second operand 5 states. [2019-12-07 13:27:17,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:17,429 INFO L93 Difference]: Finished difference Result 55533 states and 183312 transitions. [2019-12-07 13:27:17,429 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 13:27:17,429 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2019-12-07 13:27:17,429 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:17,504 INFO L225 Difference]: With dead ends: 55533 [2019-12-07 13:27:17,504 INFO L226 Difference]: Without dead ends: 48725 [2019-12-07 13:27:17,505 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 13:27:17,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48725 states. [2019-12-07 13:27:18,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48725 to 48725. [2019-12-07 13:27:18,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48725 states. [2019-12-07 13:27:18,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48725 states to 48725 states and 158325 transitions. [2019-12-07 13:27:18,637 INFO L78 Accepts]: Start accepts. Automaton has 48725 states and 158325 transitions. Word has length 28 [2019-12-07 13:27:18,637 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:18,637 INFO L462 AbstractCegarLoop]: Abstraction has 48725 states and 158325 transitions. [2019-12-07 13:27:18,638 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 13:27:18,638 INFO L276 IsEmpty]: Start isEmpty. Operand 48725 states and 158325 transitions. [2019-12-07 13:27:18,655 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 13:27:18,655 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:18,655 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:18,655 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:18,655 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:18,655 INFO L82 PathProgramCache]: Analyzing trace with hash -1021179047, now seen corresponding path program 1 times [2019-12-07 13:27:18,656 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:18,656 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425533680] [2019-12-07 13:27:18,656 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:18,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:18,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:18,722 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425533680] [2019-12-07 13:27:18,722 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:18,722 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 13:27:18,723 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1591801193] [2019-12-07 13:27:18,723 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 13:27:18,723 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:18,723 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 13:27:18,723 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 13:27:18,723 INFO L87 Difference]: Start difference. First operand 48725 states and 158325 transitions. Second operand 6 states. [2019-12-07 13:27:19,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:19,404 INFO L93 Difference]: Finished difference Result 59256 states and 189513 transitions. [2019-12-07 13:27:19,405 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 13:27:19,405 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 34 [2019-12-07 13:27:19,405 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:19,492 INFO L225 Difference]: With dead ends: 59256 [2019-12-07 13:27:19,492 INFO L226 Difference]: Without dead ends: 59243 [2019-12-07 13:27:19,492 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 0 SyntacticMatches, 3 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2019-12-07 13:27:19,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59243 states. [2019-12-07 13:27:20,242 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59243 to 44441. [2019-12-07 13:27:20,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44441 states. [2019-12-07 13:27:20,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44441 states to 44441 states and 144754 transitions. [2019-12-07 13:27:20,326 INFO L78 Accepts]: Start accepts. Automaton has 44441 states and 144754 transitions. Word has length 34 [2019-12-07 13:27:20,326 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:20,326 INFO L462 AbstractCegarLoop]: Abstraction has 44441 states and 144754 transitions. [2019-12-07 13:27:20,327 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 13:27:20,327 INFO L276 IsEmpty]: Start isEmpty. Operand 44441 states and 144754 transitions. [2019-12-07 13:27:20,348 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-12-07 13:27:20,348 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:20,349 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:20,349 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:20,349 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:20,349 INFO L82 PathProgramCache]: Analyzing trace with hash -1561630541, now seen corresponding path program 1 times [2019-12-07 13:27:20,349 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:20,349 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1823682499] [2019-12-07 13:27:20,349 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:20,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:20,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:20,477 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1823682499] [2019-12-07 13:27:20,477 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:20,477 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 13:27:20,477 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1888797787] [2019-12-07 13:27:20,477 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 13:27:20,478 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:20,478 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 13:27:20,478 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-12-07 13:27:20,478 INFO L87 Difference]: Start difference. First operand 44441 states and 144754 transitions. Second operand 8 states. [2019-12-07 13:27:21,714 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:21,714 INFO L93 Difference]: Finished difference Result 66591 states and 211053 transitions. [2019-12-07 13:27:21,715 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 13:27:21,715 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 42 [2019-12-07 13:27:21,715 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:21,809 INFO L225 Difference]: With dead ends: 66591 [2019-12-07 13:27:21,809 INFO L226 Difference]: Without dead ends: 66561 [2019-12-07 13:27:21,810 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 0 SyntacticMatches, 4 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 36 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=69, Invalid=203, Unknown=0, NotChecked=0, Total=272 [2019-12-07 13:27:22,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66561 states. [2019-12-07 13:27:22,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66561 to 56773. [2019-12-07 13:27:22,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56773 states. [2019-12-07 13:27:22,804 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56773 states to 56773 states and 182014 transitions. [2019-12-07 13:27:22,804 INFO L78 Accepts]: Start accepts. Automaton has 56773 states and 182014 transitions. Word has length 42 [2019-12-07 13:27:22,804 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:22,804 INFO L462 AbstractCegarLoop]: Abstraction has 56773 states and 182014 transitions. [2019-12-07 13:27:22,804 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 13:27:22,805 INFO L276 IsEmpty]: Start isEmpty. Operand 56773 states and 182014 transitions. [2019-12-07 13:27:22,835 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-12-07 13:27:22,836 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:22,836 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:22,836 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:22,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:22,836 INFO L82 PathProgramCache]: Analyzing trace with hash 1398904019, now seen corresponding path program 1 times [2019-12-07 13:27:22,836 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:22,836 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305813146] [2019-12-07 13:27:22,836 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:22,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:22,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:22,928 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1305813146] [2019-12-07 13:27:22,928 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:22,928 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 13:27:22,928 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [263725199] [2019-12-07 13:27:22,928 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 13:27:22,928 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:22,928 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 13:27:22,929 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 13:27:22,929 INFO L87 Difference]: Start difference. First operand 56773 states and 182014 transitions. Second operand 7 states. [2019-12-07 13:27:23,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:23,585 INFO L93 Difference]: Finished difference Result 76148 states and 240088 transitions. [2019-12-07 13:27:23,586 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 13:27:23,586 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 42 [2019-12-07 13:27:23,586 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:23,695 INFO L225 Difference]: With dead ends: 76148 [2019-12-07 13:27:23,695 INFO L226 Difference]: Without dead ends: 76118 [2019-12-07 13:27:23,696 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 0 SyntacticMatches, 3 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2019-12-07 13:27:23,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76118 states. [2019-12-07 13:27:24,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76118 to 60440. [2019-12-07 13:27:24,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60440 states. [2019-12-07 13:27:24,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60440 states to 60440 states and 193402 transitions. [2019-12-07 13:27:24,833 INFO L78 Accepts]: Start accepts. Automaton has 60440 states and 193402 transitions. Word has length 42 [2019-12-07 13:27:24,833 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:24,833 INFO L462 AbstractCegarLoop]: Abstraction has 60440 states and 193402 transitions. [2019-12-07 13:27:24,833 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 13:27:24,833 INFO L276 IsEmpty]: Start isEmpty. Operand 60440 states and 193402 transitions. [2019-12-07 13:27:24,870 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-12-07 13:27:24,870 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:24,870 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:24,870 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:24,870 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:24,870 INFO L82 PathProgramCache]: Analyzing trace with hash -1097796967, now seen corresponding path program 1 times [2019-12-07 13:27:24,870 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:24,871 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [922259949] [2019-12-07 13:27:24,871 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:24,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:24,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:24,899 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [922259949] [2019-12-07 13:27:24,899 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:24,900 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:27:24,900 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1107839449] [2019-12-07 13:27:24,900 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 13:27:24,900 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:24,900 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:27:24,900 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:27:24,900 INFO L87 Difference]: Start difference. First operand 60440 states and 193402 transitions. Second operand 3 states. [2019-12-07 13:27:25,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:25,127 INFO L93 Difference]: Finished difference Result 73033 states and 232942 transitions. [2019-12-07 13:27:25,127 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:27:25,128 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2019-12-07 13:27:25,128 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:25,236 INFO L225 Difference]: With dead ends: 73033 [2019-12-07 13:27:25,236 INFO L226 Difference]: Without dead ends: 73033 [2019-12-07 13:27:25,237 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:27:25,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73033 states. [2019-12-07 13:27:26,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73033 to 63372. [2019-12-07 13:27:26,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63372 states. [2019-12-07 13:27:26,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63372 states to 63372 states and 203470 transitions. [2019-12-07 13:27:26,530 INFO L78 Accepts]: Start accepts. Automaton has 63372 states and 203470 transitions. Word has length 45 [2019-12-07 13:27:26,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:26,530 INFO L462 AbstractCegarLoop]: Abstraction has 63372 states and 203470 transitions. [2019-12-07 13:27:26,530 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 13:27:26,530 INFO L276 IsEmpty]: Start isEmpty. Operand 63372 states and 203470 transitions. [2019-12-07 13:27:26,562 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-12-07 13:27:26,563 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:26,563 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:26,563 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:26,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:26,563 INFO L82 PathProgramCache]: Analyzing trace with hash -1281841630, now seen corresponding path program 1 times [2019-12-07 13:27:26,563 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:26,563 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345475737] [2019-12-07 13:27:26,564 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:26,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:26,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:26,618 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1345475737] [2019-12-07 13:27:26,618 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:26,618 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 13:27:26,618 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1993293600] [2019-12-07 13:27:26,619 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 13:27:26,619 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:26,619 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:27:26,619 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:27:26,619 INFO L87 Difference]: Start difference. First operand 63372 states and 203470 transitions. Second operand 5 states. [2019-12-07 13:27:27,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:27,166 INFO L93 Difference]: Finished difference Result 85105 states and 271230 transitions. [2019-12-07 13:27:27,166 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 13:27:27,166 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 45 [2019-12-07 13:27:27,166 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:27,300 INFO L225 Difference]: With dead ends: 85105 [2019-12-07 13:27:27,300 INFO L226 Difference]: Without dead ends: 85105 [2019-12-07 13:27:27,300 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 13:27:27,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85105 states. [2019-12-07 13:27:28,462 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85105 to 76108. [2019-12-07 13:27:28,462 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76108 states. [2019-12-07 13:27:28,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76108 states to 76108 states and 244522 transitions. [2019-12-07 13:27:28,620 INFO L78 Accepts]: Start accepts. Automaton has 76108 states and 244522 transitions. Word has length 45 [2019-12-07 13:27:28,620 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:28,620 INFO L462 AbstractCegarLoop]: Abstraction has 76108 states and 244522 transitions. [2019-12-07 13:27:28,620 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 13:27:28,620 INFO L276 IsEmpty]: Start isEmpty. Operand 76108 states and 244522 transitions. [2019-12-07 13:27:28,679 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-12-07 13:27:28,679 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:28,679 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:28,679 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:28,679 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:28,679 INFO L82 PathProgramCache]: Analyzing trace with hash 783344372, now seen corresponding path program 1 times [2019-12-07 13:27:28,679 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:28,680 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1338004763] [2019-12-07 13:27:28,680 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:28,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:28,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:28,730 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1338004763] [2019-12-07 13:27:28,730 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:28,730 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 13:27:28,730 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1228395493] [2019-12-07 13:27:28,731 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 13:27:28,731 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:28,731 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:27:28,731 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:27:28,731 INFO L87 Difference]: Start difference. First operand 76108 states and 244522 transitions. Second operand 5 states. [2019-12-07 13:27:29,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:29,531 INFO L93 Difference]: Finished difference Result 105367 states and 334843 transitions. [2019-12-07 13:27:29,532 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 13:27:29,532 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 46 [2019-12-07 13:27:29,532 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:29,699 INFO L225 Difference]: With dead ends: 105367 [2019-12-07 13:27:29,699 INFO L226 Difference]: Without dead ends: 105367 [2019-12-07 13:27:29,699 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 13:27:30,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105367 states. [2019-12-07 13:27:31,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105367 to 83567. [2019-12-07 13:27:31,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83567 states. [2019-12-07 13:27:31,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83567 states to 83567 states and 269447 transitions. [2019-12-07 13:27:31,198 INFO L78 Accepts]: Start accepts. Automaton has 83567 states and 269447 transitions. Word has length 46 [2019-12-07 13:27:31,198 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:31,198 INFO L462 AbstractCegarLoop]: Abstraction has 83567 states and 269447 transitions. [2019-12-07 13:27:31,198 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 13:27:31,198 INFO L276 IsEmpty]: Start isEmpty. Operand 83567 states and 269447 transitions. [2019-12-07 13:27:31,265 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-12-07 13:27:31,266 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:31,266 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:31,266 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:31,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:31,266 INFO L82 PathProgramCache]: Analyzing trace with hash 1745033113, now seen corresponding path program 1 times [2019-12-07 13:27:31,266 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:31,266 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1063296794] [2019-12-07 13:27:31,266 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:31,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:31,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:31,350 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1063296794] [2019-12-07 13:27:31,350 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:31,350 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 13:27:31,350 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2097552042] [2019-12-07 13:27:31,351 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 13:27:31,351 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:31,351 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 13:27:31,351 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 13:27:31,351 INFO L87 Difference]: Start difference. First operand 83567 states and 269447 transitions. Second operand 6 states. [2019-12-07 13:27:32,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:32,068 INFO L93 Difference]: Finished difference Result 154747 states and 501443 transitions. [2019-12-07 13:27:32,068 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 13:27:32,068 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 46 [2019-12-07 13:27:32,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:32,198 INFO L225 Difference]: With dead ends: 154747 [2019-12-07 13:27:32,198 INFO L226 Difference]: Without dead ends: 82261 [2019-12-07 13:27:32,198 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=47, Invalid=85, Unknown=0, NotChecked=0, Total=132 [2019-12-07 13:27:32,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82261 states. [2019-12-07 13:27:33,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82261 to 76161. [2019-12-07 13:27:33,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76161 states. [2019-12-07 13:27:33,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76161 states to 76161 states and 242963 transitions. [2019-12-07 13:27:33,492 INFO L78 Accepts]: Start accepts. Automaton has 76161 states and 242963 transitions. Word has length 46 [2019-12-07 13:27:33,493 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:33,493 INFO L462 AbstractCegarLoop]: Abstraction has 76161 states and 242963 transitions. [2019-12-07 13:27:33,493 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 13:27:33,493 INFO L276 IsEmpty]: Start isEmpty. Operand 76161 states and 242963 transitions. [2019-12-07 13:27:33,553 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-12-07 13:27:33,553 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:33,554 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:33,554 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:33,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:33,554 INFO L82 PathProgramCache]: Analyzing trace with hash 290754849, now seen corresponding path program 1 times [2019-12-07 13:27:33,554 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:33,554 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [327312485] [2019-12-07 13:27:33,554 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:33,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:33,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:33,605 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [327312485] [2019-12-07 13:27:33,605 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:33,605 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 13:27:33,605 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1013750119] [2019-12-07 13:27:33,606 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 13:27:33,606 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:33,606 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:27:33,606 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:27:33,606 INFO L87 Difference]: Start difference. First operand 76161 states and 242963 transitions. Second operand 5 states. [2019-12-07 13:27:34,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:34,364 INFO L93 Difference]: Finished difference Result 98930 states and 312747 transitions. [2019-12-07 13:27:34,364 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 13:27:34,365 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 46 [2019-12-07 13:27:34,365 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:34,518 INFO L225 Difference]: With dead ends: 98930 [2019-12-07 13:27:34,518 INFO L226 Difference]: Without dead ends: 98930 [2019-12-07 13:27:34,519 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 13:27:34,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98930 states. [2019-12-07 13:27:35,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98930 to 84090. [2019-12-07 13:27:35,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84090 states. [2019-12-07 13:27:35,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84090 states to 84090 states and 269025 transitions. [2019-12-07 13:27:35,966 INFO L78 Accepts]: Start accepts. Automaton has 84090 states and 269025 transitions. Word has length 46 [2019-12-07 13:27:35,966 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:35,966 INFO L462 AbstractCegarLoop]: Abstraction has 84090 states and 269025 transitions. [2019-12-07 13:27:35,966 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 13:27:35,966 INFO L276 IsEmpty]: Start isEmpty. Operand 84090 states and 269025 transitions. [2019-12-07 13:27:36,035 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2019-12-07 13:27:36,035 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:36,036 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:36,036 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:36,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:36,036 INFO L82 PathProgramCache]: Analyzing trace with hash -367844597, now seen corresponding path program 1 times [2019-12-07 13:27:36,036 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:36,036 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [987009249] [2019-12-07 13:27:36,036 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:36,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:36,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:36,115 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [987009249] [2019-12-07 13:27:36,115 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:36,115 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 13:27:36,115 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1104576456] [2019-12-07 13:27:36,115 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 13:27:36,116 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:36,116 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 13:27:36,116 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 13:27:36,116 INFO L87 Difference]: Start difference. First operand 84090 states and 269025 transitions. Second operand 6 states. [2019-12-07 13:27:36,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:36,573 INFO L93 Difference]: Finished difference Result 90869 states and 291871 transitions. [2019-12-07 13:27:36,573 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 13:27:36,573 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 47 [2019-12-07 13:27:36,573 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:36,696 INFO L225 Difference]: With dead ends: 90869 [2019-12-07 13:27:36,697 INFO L226 Difference]: Without dead ends: 90029 [2019-12-07 13:27:36,697 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=47, Invalid=85, Unknown=0, NotChecked=0, Total=132 [2019-12-07 13:27:37,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90029 states. [2019-12-07 13:27:38,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90029 to 84032. [2019-12-07 13:27:38,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84032 states. [2019-12-07 13:27:38,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84032 states to 84032 states and 268832 transitions. [2019-12-07 13:27:38,185 INFO L78 Accepts]: Start accepts. Automaton has 84032 states and 268832 transitions. Word has length 47 [2019-12-07 13:27:38,186 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:38,186 INFO L462 AbstractCegarLoop]: Abstraction has 84032 states and 268832 transitions. [2019-12-07 13:27:38,186 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 13:27:38,186 INFO L276 IsEmpty]: Start isEmpty. Operand 84032 states and 268832 transitions. [2019-12-07 13:27:38,258 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2019-12-07 13:27:38,258 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:38,258 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:38,259 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:38,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:38,259 INFO L82 PathProgramCache]: Analyzing trace with hash -1351542591, now seen corresponding path program 1 times [2019-12-07 13:27:38,259 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:38,259 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1613201307] [2019-12-07 13:27:38,259 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:38,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:38,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:38,310 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1613201307] [2019-12-07 13:27:38,310 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:38,310 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 13:27:38,310 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1308305680] [2019-12-07 13:27:38,310 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 13:27:38,311 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:38,311 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 13:27:38,311 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-12-07 13:27:38,311 INFO L87 Difference]: Start difference. First operand 84032 states and 268832 transitions. Second operand 6 states. [2019-12-07 13:27:38,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:38,434 INFO L93 Difference]: Finished difference Result 26591 states and 82208 transitions. [2019-12-07 13:27:38,435 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 13:27:38,435 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 47 [2019-12-07 13:27:38,435 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:38,467 INFO L225 Difference]: With dead ends: 26591 [2019-12-07 13:27:38,467 INFO L226 Difference]: Without dead ends: 24457 [2019-12-07 13:27:38,468 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-12-07 13:27:38,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24457 states. [2019-12-07 13:27:38,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24457 to 22723. [2019-12-07 13:27:38,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22723 states. [2019-12-07 13:27:38,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22723 states to 22723 states and 70617 transitions. [2019-12-07 13:27:38,811 INFO L78 Accepts]: Start accepts. Automaton has 22723 states and 70617 transitions. Word has length 47 [2019-12-07 13:27:38,811 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:38,811 INFO L462 AbstractCegarLoop]: Abstraction has 22723 states and 70617 transitions. [2019-12-07 13:27:38,811 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 13:27:38,811 INFO L276 IsEmpty]: Start isEmpty. Operand 22723 states and 70617 transitions. [2019-12-07 13:27:38,833 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-12-07 13:27:38,833 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:38,833 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:38,834 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:38,834 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:38,834 INFO L82 PathProgramCache]: Analyzing trace with hash -963635776, now seen corresponding path program 1 times [2019-12-07 13:27:38,834 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:38,834 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [257150328] [2019-12-07 13:27:38,834 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:38,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:38,892 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:38,892 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [257150328] [2019-12-07 13:27:38,892 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:38,892 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 13:27:38,892 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [222855913] [2019-12-07 13:27:38,893 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 13:27:38,893 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:38,893 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 13:27:38,893 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 13:27:38,893 INFO L87 Difference]: Start difference. First operand 22723 states and 70617 transitions. Second operand 7 states. [2019-12-07 13:27:39,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:39,003 INFO L93 Difference]: Finished difference Result 19045 states and 62411 transitions. [2019-12-07 13:27:39,003 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 13:27:39,003 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 54 [2019-12-07 13:27:39,003 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:39,026 INFO L225 Difference]: With dead ends: 19045 [2019-12-07 13:27:39,026 INFO L226 Difference]: Without dead ends: 17390 [2019-12-07 13:27:39,027 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2019-12-07 13:27:39,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17390 states. [2019-12-07 13:27:39,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17390 to 14380. [2019-12-07 13:27:39,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14380 states. [2019-12-07 13:27:39,306 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14380 states to 14380 states and 48389 transitions. [2019-12-07 13:27:39,307 INFO L78 Accepts]: Start accepts. Automaton has 14380 states and 48389 transitions. Word has length 54 [2019-12-07 13:27:39,307 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:39,307 INFO L462 AbstractCegarLoop]: Abstraction has 14380 states and 48389 transitions. [2019-12-07 13:27:39,307 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 13:27:39,307 INFO L276 IsEmpty]: Start isEmpty. Operand 14380 states and 48389 transitions. [2019-12-07 13:27:39,321 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 13:27:39,321 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:39,321 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:39,321 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:39,322 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:39,322 INFO L82 PathProgramCache]: Analyzing trace with hash 1157078727, now seen corresponding path program 1 times [2019-12-07 13:27:39,322 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:39,322 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [160419581] [2019-12-07 13:27:39,322 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:39,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:39,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:39,390 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [160419581] [2019-12-07 13:27:39,390 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:39,390 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 13:27:39,390 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [214371328] [2019-12-07 13:27:39,390 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 13:27:39,390 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:39,390 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 13:27:39,391 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 13:27:39,391 INFO L87 Difference]: Start difference. First operand 14380 states and 48389 transitions. Second operand 6 states. [2019-12-07 13:27:39,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:39,669 INFO L93 Difference]: Finished difference Result 18632 states and 61974 transitions. [2019-12-07 13:27:39,669 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 13:27:39,669 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 67 [2019-12-07 13:27:39,670 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:39,693 INFO L225 Difference]: With dead ends: 18632 [2019-12-07 13:27:39,693 INFO L226 Difference]: Without dead ends: 18632 [2019-12-07 13:27:39,693 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 6 SyntacticMatches, 3 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-12-07 13:27:39,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18632 states. [2019-12-07 13:27:39,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18632 to 14660. [2019-12-07 13:27:39,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14660 states. [2019-12-07 13:27:39,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14660 states to 14660 states and 49301 transitions. [2019-12-07 13:27:39,948 INFO L78 Accepts]: Start accepts. Automaton has 14660 states and 49301 transitions. Word has length 67 [2019-12-07 13:27:39,948 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:39,948 INFO L462 AbstractCegarLoop]: Abstraction has 14660 states and 49301 transitions. [2019-12-07 13:27:39,948 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 13:27:39,948 INFO L276 IsEmpty]: Start isEmpty. Operand 14660 states and 49301 transitions. [2019-12-07 13:27:39,963 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 13:27:39,963 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:39,963 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:39,963 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:39,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:39,964 INFO L82 PathProgramCache]: Analyzing trace with hash -153275837, now seen corresponding path program 2 times [2019-12-07 13:27:39,964 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:39,964 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [63898935] [2019-12-07 13:27:39,964 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:39,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:40,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:40,034 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [63898935] [2019-12-07 13:27:40,034 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:40,034 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 13:27:40,034 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [771151866] [2019-12-07 13:27:40,034 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 13:27:40,034 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:40,035 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 13:27:40,035 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 13:27:40,035 INFO L87 Difference]: Start difference. First operand 14660 states and 49301 transitions. Second operand 7 states. [2019-12-07 13:27:40,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:40,434 INFO L93 Difference]: Finished difference Result 19926 states and 66478 transitions. [2019-12-07 13:27:40,434 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 13:27:40,435 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 67 [2019-12-07 13:27:40,435 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:40,460 INFO L225 Difference]: With dead ends: 19926 [2019-12-07 13:27:40,461 INFO L226 Difference]: Without dead ends: 19926 [2019-12-07 13:27:40,461 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 6 SyntacticMatches, 3 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=64, Unknown=0, NotChecked=0, Total=90 [2019-12-07 13:27:40,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19926 states. [2019-12-07 13:27:40,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19926 to 14744. [2019-12-07 13:27:40,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14744 states. [2019-12-07 13:27:40,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14744 states to 14744 states and 49583 transitions. [2019-12-07 13:27:40,737 INFO L78 Accepts]: Start accepts. Automaton has 14744 states and 49583 transitions. Word has length 67 [2019-12-07 13:27:40,737 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:40,737 INFO L462 AbstractCegarLoop]: Abstraction has 14744 states and 49583 transitions. [2019-12-07 13:27:40,737 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 13:27:40,737 INFO L276 IsEmpty]: Start isEmpty. Operand 14744 states and 49583 transitions. [2019-12-07 13:27:40,753 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 13:27:40,753 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:40,754 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:40,754 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:40,754 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:40,754 INFO L82 PathProgramCache]: Analyzing trace with hash -1100636955, now seen corresponding path program 3 times [2019-12-07 13:27:40,754 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:40,754 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1792147931] [2019-12-07 13:27:40,754 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:40,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:40,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:40,820 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1792147931] [2019-12-07 13:27:40,820 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:40,820 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 13:27:40,820 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1050548448] [2019-12-07 13:27:40,821 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 13:27:40,821 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:40,821 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 13:27:40,821 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-12-07 13:27:40,821 INFO L87 Difference]: Start difference. First operand 14744 states and 49583 transitions. Second operand 7 states. [2019-12-07 13:27:41,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:41,209 INFO L93 Difference]: Finished difference Result 19332 states and 64254 transitions. [2019-12-07 13:27:41,209 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 13:27:41,209 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 67 [2019-12-07 13:27:41,209 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:41,234 INFO L225 Difference]: With dead ends: 19332 [2019-12-07 13:27:41,234 INFO L226 Difference]: Without dead ends: 19332 [2019-12-07 13:27:41,234 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 9 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2019-12-07 13:27:41,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19332 states. [2019-12-07 13:27:41,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19332 to 15542. [2019-12-07 13:27:41,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15542 states. [2019-12-07 13:27:41,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15542 states to 15542 states and 52192 transitions. [2019-12-07 13:27:41,501 INFO L78 Accepts]: Start accepts. Automaton has 15542 states and 52192 transitions. Word has length 67 [2019-12-07 13:27:41,501 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:41,501 INFO L462 AbstractCegarLoop]: Abstraction has 15542 states and 52192 transitions. [2019-12-07 13:27:41,501 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 13:27:41,501 INFO L276 IsEmpty]: Start isEmpty. Operand 15542 states and 52192 transitions. [2019-12-07 13:27:41,517 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 13:27:41,517 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:41,517 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:41,517 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:41,517 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:41,517 INFO L82 PathProgramCache]: Analyzing trace with hash -972408575, now seen corresponding path program 4 times [2019-12-07 13:27:41,517 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:41,517 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765441337] [2019-12-07 13:27:41,518 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:41,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:41,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:41,558 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1765441337] [2019-12-07 13:27:41,558 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:41,558 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:27:41,558 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1844538240] [2019-12-07 13:27:41,559 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 13:27:41,559 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:41,559 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:27:41,559 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:27:41,559 INFO L87 Difference]: Start difference. First operand 15542 states and 52192 transitions. Second operand 3 states. [2019-12-07 13:27:41,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:41,643 INFO L93 Difference]: Finished difference Result 15542 states and 52191 transitions. [2019-12-07 13:27:41,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:27:41,644 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 13:27:41,644 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:41,664 INFO L225 Difference]: With dead ends: 15542 [2019-12-07 13:27:41,664 INFO L226 Difference]: Without dead ends: 15542 [2019-12-07 13:27:41,664 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:27:41,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15542 states. [2019-12-07 13:27:41,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15542 to 10863. [2019-12-07 13:27:41,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10863 states. [2019-12-07 13:27:41,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10863 states to 10863 states and 36818 transitions. [2019-12-07 13:27:41,860 INFO L78 Accepts]: Start accepts. Automaton has 10863 states and 36818 transitions. Word has length 67 [2019-12-07 13:27:41,861 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:41,861 INFO L462 AbstractCegarLoop]: Abstraction has 10863 states and 36818 transitions. [2019-12-07 13:27:41,861 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 13:27:41,861 INFO L276 IsEmpty]: Start isEmpty. Operand 10863 states and 36818 transitions. [2019-12-07 13:27:41,871 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 13:27:41,871 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:41,871 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:41,871 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:41,871 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:41,871 INFO L82 PathProgramCache]: Analyzing trace with hash 42152852, now seen corresponding path program 1 times [2019-12-07 13:27:41,872 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:41,872 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [853285066] [2019-12-07 13:27:41,872 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:41,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:41,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:41,908 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [853285066] [2019-12-07 13:27:41,909 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:41,909 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:27:41,909 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1737907708] [2019-12-07 13:27:41,909 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 13:27:41,909 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:41,909 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:27:41,910 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:27:41,910 INFO L87 Difference]: Start difference. First operand 10863 states and 36818 transitions. Second operand 3 states. [2019-12-07 13:27:41,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:41,947 INFO L93 Difference]: Finished difference Result 9929 states and 32957 transitions. [2019-12-07 13:27:41,947 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:27:41,947 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 68 [2019-12-07 13:27:41,947 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:41,959 INFO L225 Difference]: With dead ends: 9929 [2019-12-07 13:27:41,959 INFO L226 Difference]: Without dead ends: 9929 [2019-12-07 13:27:41,960 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:27:42,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9929 states. [2019-12-07 13:27:42,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9929 to 9205. [2019-12-07 13:27:42,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9205 states. [2019-12-07 13:27:42,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9205 states to 9205 states and 30543 transitions. [2019-12-07 13:27:42,128 INFO L78 Accepts]: Start accepts. Automaton has 9205 states and 30543 transitions. Word has length 68 [2019-12-07 13:27:42,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:42,128 INFO L462 AbstractCegarLoop]: Abstraction has 9205 states and 30543 transitions. [2019-12-07 13:27:42,128 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 13:27:42,128 INFO L276 IsEmpty]: Start isEmpty. Operand 9205 states and 30543 transitions. [2019-12-07 13:27:42,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-12-07 13:27:42,137 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:42,137 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:42,137 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:42,137 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:42,137 INFO L82 PathProgramCache]: Analyzing trace with hash -1867313469, now seen corresponding path program 1 times [2019-12-07 13:27:42,137 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:42,137 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225613953] [2019-12-07 13:27:42,138 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:42,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:42,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:42,208 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1225613953] [2019-12-07 13:27:42,208 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:42,208 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 13:27:42,208 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [902179233] [2019-12-07 13:27:42,209 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 13:27:42,209 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:42,209 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 13:27:42,209 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 13:27:42,209 INFO L87 Difference]: Start difference. First operand 9205 states and 30543 transitions. Second operand 7 states. [2019-12-07 13:27:42,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:42,327 INFO L93 Difference]: Finished difference Result 14248 states and 45751 transitions. [2019-12-07 13:27:42,327 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 13:27:42,327 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 69 [2019-12-07 13:27:42,327 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:42,339 INFO L225 Difference]: With dead ends: 14248 [2019-12-07 13:27:42,339 INFO L226 Difference]: Without dead ends: 9201 [2019-12-07 13:27:42,339 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=40, Invalid=70, Unknown=0, NotChecked=0, Total=110 [2019-12-07 13:27:42,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9201 states. [2019-12-07 13:27:42,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9201 to 7983. [2019-12-07 13:27:42,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7983 states. [2019-12-07 13:27:42,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7983 states to 7983 states and 25889 transitions. [2019-12-07 13:27:42,470 INFO L78 Accepts]: Start accepts. Automaton has 7983 states and 25889 transitions. Word has length 69 [2019-12-07 13:27:42,470 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:42,470 INFO L462 AbstractCegarLoop]: Abstraction has 7983 states and 25889 transitions. [2019-12-07 13:27:42,470 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 13:27:42,470 INFO L276 IsEmpty]: Start isEmpty. Operand 7983 states and 25889 transitions. [2019-12-07 13:27:42,477 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-12-07 13:27:42,477 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:42,477 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:42,477 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:42,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:42,478 INFO L82 PathProgramCache]: Analyzing trace with hash 1467003793, now seen corresponding path program 2 times [2019-12-07 13:27:42,478 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:42,478 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1475562225] [2019-12-07 13:27:42,478 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:42,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:42,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:42,512 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1475562225] [2019-12-07 13:27:42,512 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:42,512 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:27:42,512 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1006143775] [2019-12-07 13:27:42,513 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 13:27:42,513 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:42,513 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:27:42,513 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:27:42,513 INFO L87 Difference]: Start difference. First operand 7983 states and 25889 transitions. Second operand 3 states. [2019-12-07 13:27:42,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:42,541 INFO L93 Difference]: Finished difference Result 7339 states and 23253 transitions. [2019-12-07 13:27:42,541 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:27:42,541 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 69 [2019-12-07 13:27:42,541 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:42,549 INFO L225 Difference]: With dead ends: 7339 [2019-12-07 13:27:42,549 INFO L226 Difference]: Without dead ends: 7339 [2019-12-07 13:27:42,550 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:27:42,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7339 states. [2019-12-07 13:27:42,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7339 to 6674. [2019-12-07 13:27:42,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6674 states. [2019-12-07 13:27:42,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6674 states to 6674 states and 21245 transitions. [2019-12-07 13:27:42,658 INFO L78 Accepts]: Start accepts. Automaton has 6674 states and 21245 transitions. Word has length 69 [2019-12-07 13:27:42,658 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:42,658 INFO L462 AbstractCegarLoop]: Abstraction has 6674 states and 21245 transitions. [2019-12-07 13:27:42,658 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 13:27:42,658 INFO L276 IsEmpty]: Start isEmpty. Operand 6674 states and 21245 transitions. [2019-12-07 13:27:42,663 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 13:27:42,663 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:42,663 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:42,664 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:42,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:42,664 INFO L82 PathProgramCache]: Analyzing trace with hash -1196877625, now seen corresponding path program 1 times [2019-12-07 13:27:42,664 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:42,664 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122652542] [2019-12-07 13:27:42,664 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:42,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:27:42,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:27:42,720 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [122652542] [2019-12-07 13:27:42,720 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:27:42,720 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 13:27:42,720 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [966631493] [2019-12-07 13:27:42,720 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 13:27:42,721 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:27:42,721 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 13:27:42,721 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 13:27:42,721 INFO L87 Difference]: Start difference. First operand 6674 states and 21245 transitions. Second operand 6 states. [2019-12-07 13:27:42,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:27:42,775 INFO L93 Difference]: Finished difference Result 8301 states and 25787 transitions. [2019-12-07 13:27:42,775 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 13:27:42,775 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 70 [2019-12-07 13:27:42,775 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:27:42,777 INFO L225 Difference]: With dead ends: 8301 [2019-12-07 13:27:42,777 INFO L226 Difference]: Without dead ends: 1937 [2019-12-07 13:27:42,777 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 13:27:42,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1937 states. [2019-12-07 13:27:42,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1937 to 1937. [2019-12-07 13:27:42,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1937 states. [2019-12-07 13:27:42,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1937 states to 1937 states and 5395 transitions. [2019-12-07 13:27:42,803 INFO L78 Accepts]: Start accepts. Automaton has 1937 states and 5395 transitions. Word has length 70 [2019-12-07 13:27:42,803 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:27:42,803 INFO L462 AbstractCegarLoop]: Abstraction has 1937 states and 5395 transitions. [2019-12-07 13:27:42,803 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 13:27:42,803 INFO L276 IsEmpty]: Start isEmpty. Operand 1937 states and 5395 transitions. [2019-12-07 13:27:42,804 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 13:27:42,804 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:27:42,805 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:27:42,805 INFO L410 AbstractCegarLoop]: === Iteration 29 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:27:42,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:27:42,805 INFO L82 PathProgramCache]: Analyzing trace with hash -1078025367, now seen corresponding path program 2 times [2019-12-07 13:27:42,805 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:27:42,805 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1668986364] [2019-12-07 13:27:42,805 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:27:42,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:27:42,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:27:42,877 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:27:42,878 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 13:27:42,880 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [876] [876] ULTIMATE.startENTRY-->L833: Formula: (let ((.cse0 (store |v_#valid_73| 0 0))) (and (= v_~x~0_55 0) (= v_~a~0_26 0) (= 0 v_~y$read_delayed_var~0.offset_7) (= v_~y$r_buff1_thd0~0_273 0) (= v_~y$r_buff0_thd1~0_30 0) (= v_~y$r_buff0_thd4~0_83 0) (= v_~main$tmp_guard0~0_39 0) (= 0 v_~y$r_buff1_thd1~0_94) (= 0 v_~y$r_buff0_thd3~0_170) (= v_~y~0_170 0) (= 0 v_~__unbuffered_p3_EBX~0_25) (= v_~y$read_delayed~0_6 0) (= v_~y$r_buff0_thd0~0_357 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t789~0.base_24|)) (= v_~y$mem_tmp~0_18 0) (= 0 |v_ULTIMATE.start_main_~#t789~0.offset_18|) (= 0 v_~y$flush_delayed~0_35) (= 0 v_~__unbuffered_p3_EAX~0_21) (= v_~__unbuffered_cnt~0_136 0) (= v_~y$w_buff1_used~0_387 0) (= 0 v_~y$r_buff1_thd2~0_158) (= 0 |v_#NULL.base_4|) (= v_~y$w_buff1~0_158 0) (= (store |v_#length_32| |v_ULTIMATE.start_main_~#t789~0.base_24| 4) |v_#length_31|) (= 0 v_~y$read_delayed_var~0.base_7) (< 0 |v_#StackHeapBarrier_20|) (= v_~y$r_buff0_thd2~0_97 0) (= v_~z~0_109 0) (= 0 v_~__unbuffered_p0_EAX~0_27) (= 0 v_~y$w_buff0~0_171) (= 0 v_~y$r_buff1_thd4~0_149) (< |v_#StackHeapBarrier_20| |v_ULTIMATE.start_main_~#t789~0.base_24|) (= |v_#NULL.offset_4| 0) (= |v_#memory_int_27| (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t789~0.base_24| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t789~0.base_24|) |v_ULTIMATE.start_main_~#t789~0.offset_18| 0))) (= v_~main$tmp_guard1~0_24 0) (= |v_#valid_71| (store .cse0 |v_ULTIMATE.start_main_~#t789~0.base_24| 1)) (= 0 v_~weak$$choice0~0_13) (= 0 v_~y$r_buff1_thd3~0_146) (= v_~weak$$choice2~0_110 0) (= v_~y$w_buff0_used~0_739 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_20|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_28|, #length=|v_#length_32|} OutVars{ULTIMATE.start_main_#t~nondet32=|v_ULTIMATE.start_main_#t~nondet32_21|, ULTIMATE.start_main_~#t791~0.offset=|v_ULTIMATE.start_main_~#t791~0.offset_17|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_33|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_30|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_28|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_33|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_284|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_37|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_41|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~a~0=v_~a~0_26, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_29|, ~y$mem_tmp~0=v_~y$mem_tmp~0_18, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_27, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_146, ULTIMATE.start_main_~#t790~0.base=|v_ULTIMATE.start_main_~#t790~0.base_23|, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_30, ~y$flush_delayed~0=v_~y$flush_delayed~0_35, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_21, #length=|v_#length_31|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_54|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_28|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_25|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_55|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_20|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_46|, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_149, ~y$w_buff1~0=v_~y$w_buff1~0_158, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_97, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_136, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_273, ~x~0=v_~x~0_55, ULTIMATE.start_main_~#t792~0.base=|v_ULTIMATE.start_main_~#t792~0.base_20|, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_739, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_27|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_29|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_40|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_24, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_25|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_36|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_158|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_39|, ULTIMATE.start_main_~#t790~0.offset=|v_ULTIMATE.start_main_~#t790~0.offset_18|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_94, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_33|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_51|, ~y$w_buff0~0=v_~y$w_buff0~0_171, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_170, ~y~0=v_~y~0_170, ULTIMATE.start_main_~#t789~0.base=|v_ULTIMATE.start_main_~#t789~0.base_24|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_9|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_9|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_46|, ULTIMATE.start_main_~#t789~0.offset=|v_ULTIMATE.start_main_~#t789~0.offset_18|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_52|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_39, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_25, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_32|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_103|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_158, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_83, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_154|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_357, #valid=|v_#valid_71|, #memory_int=|v_#memory_int_27|, ULTIMATE.start_main_~#t792~0.offset=|v_ULTIMATE.start_main_~#t792~0.offset_16|, ~z~0=v_~z~0_109, ~weak$$choice2~0=v_~weak$$choice2~0_110, ULTIMATE.start_main_~#t791~0.base=|v_ULTIMATE.start_main_~#t791~0.base_20|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_387} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet32, ULTIMATE.start_main_~#t791~0.offset, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ~y$read_delayed~0, ~a~0, ULTIMATE.start_main_#t~ite52, ~y$mem_tmp~0, ~__unbuffered_p0_EAX~0, ~y$r_buff1_thd3~0, ULTIMATE.start_main_~#t790~0.base, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ~__unbuffered_p3_EAX~0, #length, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$r_buff1_thd4~0, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_~#t792~0.base, ULTIMATE.start_main_#t~nondet31, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t790~0.offset, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite51, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_~#t789~0.base, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_~#t789~0.offset, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~__unbuffered_p3_EBX~0, ULTIMATE.start_main_#t~ite53, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ~y$r_buff0_thd4~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_~#t792~0.offset, ~z~0, ~weak$$choice2~0, ULTIMATE.start_main_~#t791~0.base, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 13:27:42,881 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L833-1-->L835: Formula: (and (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t790~0.base_10|) (= (store |v_#length_20| |v_ULTIMATE.start_main_~#t790~0.base_10| 4) |v_#length_19|) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t790~0.base_10| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t790~0.base_10|) |v_ULTIMATE.start_main_~#t790~0.offset_9| 1)) |v_#memory_int_15|) (= 0 (select |v_#valid_43| |v_ULTIMATE.start_main_~#t790~0.base_10|)) (= |v_#valid_42| (store |v_#valid_43| |v_ULTIMATE.start_main_~#t790~0.base_10| 1)) (= |v_ULTIMATE.start_main_~#t790~0.offset_9| 0) (not (= |v_ULTIMATE.start_main_~#t790~0.base_10| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_43|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{ULTIMATE.start_main_~#t790~0.offset=|v_ULTIMATE.start_main_~#t790~0.offset_9|, #StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, ULTIMATE.start_main_~#t790~0.base=|v_ULTIMATE.start_main_~#t790~0.base_10|, #valid=|v_#valid_42|, #memory_int=|v_#memory_int_15|, #length=|v_#length_19|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t790~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t790~0.base, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 13:27:42,881 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [835] [835] L835-1-->L837: Formula: (and (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t791~0.base_11| 4)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t791~0.base_11|) (= 0 (select |v_#valid_39| |v_ULTIMATE.start_main_~#t791~0.base_11|)) (= |v_ULTIMATE.start_main_~#t791~0.offset_10| 0) (= (store |v_#valid_39| |v_ULTIMATE.start_main_~#t791~0.base_11| 1) |v_#valid_38|) (not (= 0 |v_ULTIMATE.start_main_~#t791~0.base_11|)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t791~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t791~0.base_11|) |v_ULTIMATE.start_main_~#t791~0.offset_10| 2)) |v_#memory_int_13|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t791~0.offset=|v_ULTIMATE.start_main_~#t791~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_13|, #length=|v_#length_17|, ULTIMATE.start_main_~#t791~0.base=|v_ULTIMATE.start_main_~#t791~0.base_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t791~0.offset, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t791~0.base] because there is no mapped edge [2019-12-07 13:27:42,881 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] P2ENTRY-->L4-3: Formula: (and (= (ite (not (and (not (= 0 (mod v_~y$w_buff1_used~0_105 256))) (not (= 0 (mod v_~y$w_buff0_used~0_178 256))))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~y$w_buff0~0_34 v_~y$w_buff1~0_39) (= |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8)) (= 2 v_~y$w_buff0~0_33) (= v_P2Thread1of1ForFork0_~arg.base_6 |v_P2Thread1of1ForFork0_#in~arg.base_8|) (= v_~y$w_buff0_used~0_179 v_~y$w_buff1_used~0_105) (= v_~y$w_buff0_used~0_178 1) (= v_P2Thread1of1ForFork0_~arg.offset_6 |v_P2Thread1of1ForFork0_#in~arg.offset_8|)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_179, ~y$w_buff0~0=v_~y$w_buff0~0_34, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_6, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_178, ~y$w_buff1~0=v_~y$w_buff1~0_39, ~y$w_buff0~0=v_~y$w_buff0~0_33, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_6, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_105} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 13:27:42,882 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L837-1-->L839: Formula: (and (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t792~0.base_11| 4)) (not (= |v_ULTIMATE.start_main_~#t792~0.base_11| 0)) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t792~0.base_11|) (= (select |v_#valid_45| |v_ULTIMATE.start_main_~#t792~0.base_11|) 0) (= |v_#valid_44| (store |v_#valid_45| |v_ULTIMATE.start_main_~#t792~0.base_11| 1)) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t792~0.base_11| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t792~0.base_11|) |v_ULTIMATE.start_main_~#t792~0.offset_9| 3)) |v_#memory_int_17|) (= |v_ULTIMATE.start_main_~#t792~0.offset_9| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_~#t792~0.base=|v_ULTIMATE.start_main_~#t792~0.base_11|, #StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_4|, #valid=|v_#valid_44|, #memory_int=|v_#memory_int_17|, #length=|v_#length_21|, ULTIMATE.start_main_~#t792~0.offset=|v_ULTIMATE.start_main_~#t792~0.offset_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t792~0.base, ULTIMATE.start_main_#t~nondet23, #valid, #memory_int, #length, ULTIMATE.start_main_~#t792~0.offset] because there is no mapped edge [2019-12-07 13:27:42,882 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] P0ENTRY-->P0EXIT: Formula: (and (= v_P0Thread1of1ForFork2_~arg.base_6 |v_P0Thread1of1ForFork2_#in~arg.base_8|) (= v_~a~0_12 1) (= (+ v_~__unbuffered_cnt~0_48 1) v_~__unbuffered_cnt~0_47) (= |v_P0Thread1of1ForFork2_#res.offset_3| 0) (= v_P0Thread1of1ForFork2_~arg.offset_6 |v_P0Thread1of1ForFork2_#in~arg.offset_8|) (= v_~x~0_36 v_~__unbuffered_p0_EAX~0_17) (= 0 |v_P0Thread1of1ForFork2_#res.base_3|)) InVars {P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_48, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_8|, ~x~0=v_~x~0_36} OutVars{~a~0=v_~a~0_12, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_17, P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_8|, P0Thread1of1ForFork2_~arg.offset=v_P0Thread1of1ForFork2_~arg.offset_6, P0Thread1of1ForFork2_#res.offset=|v_P0Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_47, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_8|, P0Thread1of1ForFork2_#res.base=|v_P0Thread1of1ForFork2_#res.base_3|, ~x~0=v_~x~0_36, P0Thread1of1ForFork2_~arg.base=v_P0Thread1of1ForFork2_~arg.base_6} AuxVars[] AssignedVars[~a~0, ~__unbuffered_p0_EAX~0, P0Thread1of1ForFork2_~arg.offset, P0Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0, P0Thread1of1ForFork2_#res.base, P0Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-12-07 13:27:42,883 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L757-2-->L757-5: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In1158677860 256))) (.cse2 (= |P1Thread1of1ForFork3_#t~ite3_Out1158677860| |P1Thread1of1ForFork3_#t~ite4_Out1158677860|)) (.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In1158677860 256)))) (or (and (or .cse0 .cse1) .cse2 (= |P1Thread1of1ForFork3_#t~ite3_Out1158677860| ~y~0_In1158677860)) (and (not .cse1) (= ~y$w_buff1~0_In1158677860 |P1Thread1of1ForFork3_#t~ite3_Out1158677860|) .cse2 (not .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1158677860, ~y$w_buff1~0=~y$w_buff1~0_In1158677860, ~y~0=~y~0_In1158677860, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1158677860} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1158677860, ~y$w_buff1~0=~y$w_buff1~0_In1158677860, P1Thread1of1ForFork3_#t~ite4=|P1Thread1of1ForFork3_#t~ite4_Out1158677860|, P1Thread1of1ForFork3_#t~ite3=|P1Thread1of1ForFork3_#t~ite3_Out1158677860|, ~y~0=~y~0_In1158677860, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1158677860} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite4, P1Thread1of1ForFork3_#t~ite3] because there is no mapped edge [2019-12-07 13:27:42,883 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L758-->L758-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd2~0_In-355609908 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In-355609908 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork3_#t~ite5_Out-355609908|)) (and (= ~y$w_buff0_used~0_In-355609908 |P1Thread1of1ForFork3_#t~ite5_Out-355609908|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-355609908, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-355609908} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-355609908, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-355609908, P1Thread1of1ForFork3_#t~ite5=|P1Thread1of1ForFork3_#t~ite5_Out-355609908|} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite5] because there is no mapped edge [2019-12-07 13:27:42,884 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [807] [807] L810-2-->L810-4: Formula: (let ((.cse1 (= (mod ~y$r_buff1_thd4~0_In1585544267 256) 0)) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In1585544267 256)))) (or (and (= |P3Thread1of1ForFork1_#t~ite15_Out1585544267| ~y~0_In1585544267) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |P3Thread1of1ForFork1_#t~ite15_Out1585544267| ~y$w_buff1~0_In1585544267)))) InVars {~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1585544267, ~y$w_buff1~0=~y$w_buff1~0_In1585544267, ~y~0=~y~0_In1585544267, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1585544267} OutVars{~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1585544267, ~y$w_buff1~0=~y$w_buff1~0_In1585544267, P3Thread1of1ForFork1_#t~ite15=|P3Thread1of1ForFork1_#t~ite15_Out1585544267|, ~y~0=~y~0_In1585544267, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1585544267} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite15] because there is no mapped edge [2019-12-07 13:27:42,884 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [794] [794] L759-->L759-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff0_used~0_In-714486848 256))) (.cse2 (= (mod ~y$r_buff0_thd2~0_In-714486848 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In-714486848 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In-714486848 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork3_#t~ite6_Out-714486848|)) (and (or .cse3 .cse2) (= ~y$w_buff1_used~0_In-714486848 |P1Thread1of1ForFork3_#t~ite6_Out-714486848|) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-714486848, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-714486848, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-714486848, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-714486848} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-714486848, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-714486848, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-714486848, P1Thread1of1ForFork3_#t~ite6=|P1Thread1of1ForFork3_#t~ite6_Out-714486848|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-714486848} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite6] because there is no mapped edge [2019-12-07 13:27:42,884 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [731] [731] L810-4-->L811: Formula: (= v_~y~0_28 |v_P3Thread1of1ForFork1_#t~ite15_8|) InVars {P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_8|} OutVars{P3Thread1of1ForFork1_#t~ite16=|v_P3Thread1of1ForFork1_#t~ite16_13|, P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_7|, ~y~0=v_~y~0_28} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite16, P3Thread1of1ForFork1_#t~ite15, ~y~0] because there is no mapped edge [2019-12-07 13:27:42,884 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L811-->L811-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In1861063033 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd4~0_In1861063033 256)))) (or (and (not .cse0) (not .cse1) (= |P3Thread1of1ForFork1_#t~ite17_Out1861063033| 0)) (and (= |P3Thread1of1ForFork1_#t~ite17_Out1861063033| ~y$w_buff0_used~0_In1861063033) (or .cse0 .cse1)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1861063033, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1861063033} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1861063033, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1861063033, P3Thread1of1ForFork1_#t~ite17=|P3Thread1of1ForFork1_#t~ite17_Out1861063033|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite17] because there is no mapped edge [2019-12-07 13:27:42,884 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L812-->L812-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd4~0_In1085596246 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In1085596246 256))) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1085596246 256))) (.cse3 (= 0 (mod ~y$r_buff1_thd4~0_In1085596246 256)))) (or (and (or .cse0 .cse1) (= |P3Thread1of1ForFork1_#t~ite18_Out1085596246| ~y$w_buff1_used~0_In1085596246) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P3Thread1of1ForFork1_#t~ite18_Out1085596246| 0)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1085596246, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1085596246, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1085596246, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1085596246} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1085596246, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1085596246, P3Thread1of1ForFork1_#t~ite18=|P3Thread1of1ForFork1_#t~ite18_Out1085596246|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1085596246, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1085596246} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite18] because there is no mapped edge [2019-12-07 13:27:42,885 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L813-->L813-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd4~0_In634346640 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In634346640 256)))) (or (and (or .cse0 .cse1) (= |P3Thread1of1ForFork1_#t~ite19_Out634346640| ~y$r_buff0_thd4~0_In634346640)) (and (not .cse0) (not .cse1) (= |P3Thread1of1ForFork1_#t~ite19_Out634346640| 0)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In634346640, ~y$w_buff0_used~0=~y$w_buff0_used~0_In634346640} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In634346640, ~y$w_buff0_used~0=~y$w_buff0_used~0_In634346640, P3Thread1of1ForFork1_#t~ite19=|P3Thread1of1ForFork1_#t~ite19_Out634346640|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite19] because there is no mapped edge [2019-12-07 13:27:42,885 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L760-->L760-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-58177092 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-58177092 256)))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork3_#t~ite7_Out-58177092| 0)) (and (= |P1Thread1of1ForFork3_#t~ite7_Out-58177092| ~y$r_buff0_thd2~0_In-58177092) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-58177092, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-58177092} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-58177092, P1Thread1of1ForFork3_#t~ite7=|P1Thread1of1ForFork3_#t~ite7_Out-58177092|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-58177092} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite7] because there is no mapped edge [2019-12-07 13:27:42,886 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [810] [810] L761-->L761-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In-1005945924 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-1005945924 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In-1005945924 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In-1005945924 256) 0))) (or (and (= ~y$r_buff1_thd2~0_In-1005945924 |P1Thread1of1ForFork3_#t~ite8_Out-1005945924|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P1Thread1of1ForFork3_#t~ite8_Out-1005945924|) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1005945924, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1005945924, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1005945924, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1005945924} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1005945924, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1005945924, P1Thread1of1ForFork3_#t~ite8=|P1Thread1of1ForFork3_#t~ite8_Out-1005945924|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1005945924, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1005945924} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite8] because there is no mapped edge [2019-12-07 13:27:42,886 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L761-2-->P1EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_41 1) v_~__unbuffered_cnt~0_40) (= 0 |v_P1Thread1of1ForFork3_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork3_#res.base_3|) (= |v_P1Thread1of1ForFork3_#t~ite8_24| v_~y$r_buff1_thd2~0_111)) InVars {P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_41} OutVars{P1Thread1of1ForFork3_#res.base=|v_P1Thread1of1ForFork3_#res.base_3|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_111, P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_23|, P1Thread1of1ForFork3_#res.offset=|v_P1Thread1of1ForFork3_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#res.base, ~y$r_buff1_thd2~0, P1Thread1of1ForFork3_#t~ite8, P1Thread1of1ForFork3_#res.offset, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 13:27:42,886 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L788-->L788-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1285811244 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In-1285811244 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In-1285811244 |P2Thread1of1ForFork0_#t~ite11_Out-1285811244|)) (and (not .cse0) (= 0 |P2Thread1of1ForFork0_#t~ite11_Out-1285811244|) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1285811244, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1285811244} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1285811244, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-1285811244|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1285811244} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 13:27:42,886 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [813] [813] L789-->L789-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1736798882 256) 0)) (.cse0 (= (mod ~y$r_buff0_thd3~0_In-1736798882 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd3~0_In-1736798882 256))) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1736798882 256)))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite12_Out-1736798882| ~y$w_buff1_used~0_In-1736798882) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite12_Out-1736798882|) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1736798882, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1736798882, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1736798882, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1736798882} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1736798882, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1736798882, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-1736798882|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1736798882, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1736798882} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 13:27:42,887 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L790-->L791: Formula: (let ((.cse0 (= ~y$r_buff0_thd3~0_In-1855435202 ~y$r_buff0_thd3~0_Out-1855435202)) (.cse1 (= (mod ~y$r_buff0_thd3~0_In-1855435202 256) 0)) (.cse2 (= (mod ~y$w_buff0_used~0_In-1855435202 256) 0))) (or (and .cse0 .cse1) (and .cse0 .cse2) (and (not .cse1) (= 0 ~y$r_buff0_thd3~0_Out-1855435202) (not .cse2)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1855435202, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1855435202} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1855435202, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-1855435202, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-1855435202|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 13:27:42,887 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L791-->L791-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In-2058858830 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In-2058858830 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd3~0_In-2058858830 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-2058858830 256) 0))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd3~0_In-2058858830 |P2Thread1of1ForFork0_#t~ite14_Out-2058858830|) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite14_Out-2058858830|) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-2058858830, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2058858830, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2058858830, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2058858830} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out-2058858830|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-2058858830, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2058858830, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2058858830, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2058858830} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 13:27:42,887 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [847] [847] L791-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= v_~__unbuffered_cnt~0_59 (+ v_~__unbuffered_cnt~0_60 1)) (= v_~y$r_buff1_thd3~0_114 |v_P2Thread1of1ForFork0_#t~ite14_20|) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_20|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_60} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_19|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_114, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_59, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 13:27:42,887 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [792] [792] L814-->L814-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff1_thd4~0_In-2139722762 256))) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In-2139722762 256))) (.cse1 (= (mod ~y$r_buff0_thd4~0_In-2139722762 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-2139722762 256)))) (or (and (= ~y$r_buff1_thd4~0_In-2139722762 |P3Thread1of1ForFork1_#t~ite20_Out-2139722762|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |P3Thread1of1ForFork1_#t~ite20_Out-2139722762|)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-2139722762, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-2139722762, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2139722762, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2139722762} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-2139722762, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-2139722762, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2139722762, P3Thread1of1ForFork1_#t~ite20=|P3Thread1of1ForFork1_#t~ite20_Out-2139722762|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2139722762} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 13:27:42,887 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [846] [846] L814-2-->P3EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_54 1) v_~__unbuffered_cnt~0_53) (= |v_P3Thread1of1ForFork1_#t~ite20_28| v_~y$r_buff1_thd4~0_111) (= |v_P3Thread1of1ForFork1_#res.offset_3| 0) (= |v_P3Thread1of1ForFork1_#res.base_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_28|} OutVars{~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_111, P3Thread1of1ForFork1_#res.base=|v_P3Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_53, P3Thread1of1ForFork1_#res.offset=|v_P3Thread1of1ForFork1_#res.offset_3|, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_27|} AuxVars[] AssignedVars[~y$r_buff1_thd4~0, P3Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork1_#res.offset, P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 13:27:42,888 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L843-->L845-2: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (or (= (mod v_~y$w_buff0_used~0_216 256) 0) (= 0 (mod v_~y$r_buff0_thd0~0_104 256)))) InVars {~y$w_buff0_used~0=v_~y$w_buff0_used~0_216, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} OutVars{~y$w_buff0_used~0=v_~y$w_buff0_used~0_216, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 13:27:42,888 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L845-2-->L845-5: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite25_Out1301867602| |ULTIMATE.start_main_#t~ite26_Out1301867602|)) (.cse2 (= (mod ~y$r_buff1_thd0~0_In1301867602 256) 0)) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In1301867602 256)))) (or (and (= |ULTIMATE.start_main_#t~ite25_Out1301867602| ~y~0_In1301867602) .cse0 (or .cse1 .cse2)) (and (= |ULTIMATE.start_main_#t~ite25_Out1301867602| ~y$w_buff1~0_In1301867602) .cse0 (not .cse2) (not .cse1)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In1301867602, ~y~0=~y~0_In1301867602, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1301867602, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1301867602} OutVars{~y$w_buff1~0=~y$w_buff1~0_In1301867602, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out1301867602|, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out1301867602|, ~y~0=~y~0_In1301867602, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1301867602, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1301867602} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 13:27:42,888 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [797] [797] L846-->L846-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-389003387 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-389003387 256)))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite27_Out-389003387|)) (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In-389003387 |ULTIMATE.start_main_#t~ite27_Out-389003387|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-389003387, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-389003387} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-389003387, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-389003387, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-389003387|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 13:27:42,889 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L847-->L847-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff0_used~0_In-1110307918 256))) (.cse2 (= (mod ~y$r_buff0_thd0~0_In-1110307918 256) 0)) (.cse1 (= (mod ~y$w_buff1_used~0_In-1110307918 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-1110307918 256)))) (or (and (= 0 |ULTIMATE.start_main_#t~ite28_Out-1110307918|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (= ~y$w_buff1_used~0_In-1110307918 |ULTIMATE.start_main_#t~ite28_Out-1110307918|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1110307918, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1110307918, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1110307918, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1110307918} OutVars{ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out-1110307918|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1110307918, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1110307918, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1110307918, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1110307918} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 13:27:42,889 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [812] [812] L848-->L848-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-2079230198 256))) (.cse1 (= (mod ~y$r_buff0_thd0~0_In-2079230198 256) 0))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite29_Out-2079230198| 0) (not .cse1)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite29_Out-2079230198| ~y$r_buff0_thd0~0_In-2079230198)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-2079230198, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-2079230198} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-2079230198, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-2079230198|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-2079230198} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 13:27:42,889 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [790] [790] L849-->L849-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-1887937651 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd0~0_In-1887937651 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1887937651 256))) (.cse3 (= 0 (mod ~y$r_buff1_thd0~0_In-1887937651 256)))) (or (and (= ~y$r_buff1_thd0~0_In-1887937651 |ULTIMATE.start_main_#t~ite30_Out-1887937651|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |ULTIMATE.start_main_#t~ite30_Out-1887937651| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1887937651, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1887937651, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1887937651, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1887937651} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out-1887937651|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1887937651, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1887937651, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1887937651, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1887937651} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30] because there is no mapped edge [2019-12-07 13:27:42,891 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [852] [852] L858-->L858-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-1982313851 256)))) (or (and (= |ULTIMATE.start_main_#t~ite39_In-1982313851| |ULTIMATE.start_main_#t~ite39_Out-1982313851|) (not .cse0) (= |ULTIMATE.start_main_#t~ite40_Out-1982313851| ~y$w_buff1~0_In-1982313851)) (and (= ~y$w_buff1~0_In-1982313851 |ULTIMATE.start_main_#t~ite39_Out-1982313851|) .cse0 (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-1982313851 256)))) (or (= 0 (mod ~y$w_buff0_used~0_In-1982313851 256)) (and (= (mod ~y$r_buff1_thd0~0_In-1982313851 256) 0) .cse1) (and .cse1 (= (mod ~y$w_buff1_used~0_In-1982313851 256) 0)))) (= |ULTIMATE.start_main_#t~ite40_Out-1982313851| |ULTIMATE.start_main_#t~ite39_Out-1982313851|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1982313851, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1982313851, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_In-1982313851|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1982313851, ~weak$$choice2~0=~weak$$choice2~0_In-1982313851, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1982313851, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1982313851} OutVars{ULTIMATE.start_main_#t~ite40=|ULTIMATE.start_main_#t~ite40_Out-1982313851|, ~y$w_buff1~0=~y$w_buff1~0_In-1982313851, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1982313851, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out-1982313851|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1982313851, ~weak$$choice2~0=~weak$$choice2~0_In-1982313851, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1982313851, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1982313851} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 13:27:42,891 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L859-->L859-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-359966343 256) 0))) (or (and (= ~y$w_buff0_used~0_In-359966343 |ULTIMATE.start_main_#t~ite42_Out-359966343|) .cse0 (= |ULTIMATE.start_main_#t~ite43_Out-359966343| |ULTIMATE.start_main_#t~ite42_Out-359966343|) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-359966343 256) 0))) (or (and .cse1 (= (mod ~y$r_buff1_thd0~0_In-359966343 256) 0)) (and (= (mod ~y$w_buff1_used~0_In-359966343 256) 0) .cse1) (= 0 (mod ~y$w_buff0_used~0_In-359966343 256))))) (and (= |ULTIMATE.start_main_#t~ite43_Out-359966343| ~y$w_buff0_used~0_In-359966343) (= |ULTIMATE.start_main_#t~ite42_In-359966343| |ULTIMATE.start_main_#t~ite42_Out-359966343|) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-359966343, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-359966343, ~weak$$choice2~0=~weak$$choice2~0_In-359966343, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-359966343, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_In-359966343|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-359966343} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-359966343, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-359966343, ULTIMATE.start_main_#t~ite43=|ULTIMATE.start_main_#t~ite43_Out-359966343|, ~weak$$choice2~0=~weak$$choice2~0_In-359966343, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_Out-359966343|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-359966343, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-359966343} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 13:27:42,892 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [865] [865] L860-->L860-8: Formula: (let ((.cse4 (= 0 (mod ~weak$$choice2~0_In-1334516335 256))) (.cse3 (= |ULTIMATE.start_main_#t~ite46_Out-1334516335| |ULTIMATE.start_main_#t~ite45_Out-1334516335|)) (.cse5 (= 0 (mod ~y$w_buff1_used~0_In-1334516335 256))) (.cse2 (= (mod ~y$r_buff1_thd0~0_In-1334516335 256) 0)) (.cse6 (= 0 (mod ~y$r_buff0_thd0~0_In-1334516335 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1334516335 256)))) (or (let ((.cse1 (not .cse6))) (and (not .cse0) (= |ULTIMATE.start_main_#t~ite45_Out-1334516335| |ULTIMATE.start_main_#t~ite44_Out-1334516335|) (or .cse1 (not .cse2)) .cse3 .cse4 (or .cse1 (not .cse5)) (= 0 |ULTIMATE.start_main_#t~ite44_Out-1334516335|))) (and (= |ULTIMATE.start_main_#t~ite44_In-1334516335| |ULTIMATE.start_main_#t~ite44_Out-1334516335|) (or (and (= |ULTIMATE.start_main_#t~ite45_Out-1334516335| |ULTIMATE.start_main_#t~ite45_In-1334516335|) (not .cse4) (= ~y$w_buff1_used~0_In-1334516335 |ULTIMATE.start_main_#t~ite46_Out-1334516335|)) (and .cse4 .cse3 (= ~y$w_buff1_used~0_In-1334516335 |ULTIMATE.start_main_#t~ite45_Out-1334516335|) (or (and .cse5 .cse6) (and .cse2 .cse6) .cse0)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1334516335, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1334516335, ~weak$$choice2~0=~weak$$choice2~0_In-1334516335, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1334516335, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In-1334516335|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1334516335, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_In-1334516335|} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1334516335, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1334516335, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out-1334516335|, ~weak$$choice2~0=~weak$$choice2~0_In-1334516335, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1334516335, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out-1334516335|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1334516335, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_Out-1334516335|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-12-07 13:27:42,892 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [868] [868] L860-8-->L862: Formula: (and (not (= (mod v_~weak$$choice2~0_106 256) 0)) (= v_~y$w_buff1_used~0_383 |v_ULTIMATE.start_main_#t~ite46_36|) (= v_~y$r_buff0_thd0~0_352 v_~y$r_buff0_thd0~0_351)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_352, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~weak$$choice2~0=v_~weak$$choice2~0_106} OutVars{~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_351, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_35|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_31|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_34|, ~weak$$choice2~0=v_~weak$$choice2~0_106, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_33|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_383} AuxVars[] AssignedVars[~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 13:27:42,892 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L864-->L4: Formula: (and (= 0 v_~y$flush_delayed~0_25) (= v_~y~0_116 v_~y$mem_tmp~0_11) (not (= (mod v_~y$flush_delayed~0_26 256) 0)) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5| (mod v_~main$tmp_guard1~0_15 256))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_26, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_11, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ~y$flush_delayed~0=v_~y$flush_delayed~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15, ~y~0=v_~y~0_116, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_23|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ~y~0, ULTIMATE.start_main_#t~ite53, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 13:27:42,892 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 13:27:42,954 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 01:27:42 BasicIcfg [2019-12-07 13:27:42,954 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 13:27:42,955 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 13:27:42,955 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 13:27:42,955 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 13:27:42,955 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 01:23:24" (3/4) ... [2019-12-07 13:27:42,957 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 13:27:42,957 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [876] [876] ULTIMATE.startENTRY-->L833: Formula: (let ((.cse0 (store |v_#valid_73| 0 0))) (and (= v_~x~0_55 0) (= v_~a~0_26 0) (= 0 v_~y$read_delayed_var~0.offset_7) (= v_~y$r_buff1_thd0~0_273 0) (= v_~y$r_buff0_thd1~0_30 0) (= v_~y$r_buff0_thd4~0_83 0) (= v_~main$tmp_guard0~0_39 0) (= 0 v_~y$r_buff1_thd1~0_94) (= 0 v_~y$r_buff0_thd3~0_170) (= v_~y~0_170 0) (= 0 v_~__unbuffered_p3_EBX~0_25) (= v_~y$read_delayed~0_6 0) (= v_~y$r_buff0_thd0~0_357 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t789~0.base_24|)) (= v_~y$mem_tmp~0_18 0) (= 0 |v_ULTIMATE.start_main_~#t789~0.offset_18|) (= 0 v_~y$flush_delayed~0_35) (= 0 v_~__unbuffered_p3_EAX~0_21) (= v_~__unbuffered_cnt~0_136 0) (= v_~y$w_buff1_used~0_387 0) (= 0 v_~y$r_buff1_thd2~0_158) (= 0 |v_#NULL.base_4|) (= v_~y$w_buff1~0_158 0) (= (store |v_#length_32| |v_ULTIMATE.start_main_~#t789~0.base_24| 4) |v_#length_31|) (= 0 v_~y$read_delayed_var~0.base_7) (< 0 |v_#StackHeapBarrier_20|) (= v_~y$r_buff0_thd2~0_97 0) (= v_~z~0_109 0) (= 0 v_~__unbuffered_p0_EAX~0_27) (= 0 v_~y$w_buff0~0_171) (= 0 v_~y$r_buff1_thd4~0_149) (< |v_#StackHeapBarrier_20| |v_ULTIMATE.start_main_~#t789~0.base_24|) (= |v_#NULL.offset_4| 0) (= |v_#memory_int_27| (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t789~0.base_24| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t789~0.base_24|) |v_ULTIMATE.start_main_~#t789~0.offset_18| 0))) (= v_~main$tmp_guard1~0_24 0) (= |v_#valid_71| (store .cse0 |v_ULTIMATE.start_main_~#t789~0.base_24| 1)) (= 0 v_~weak$$choice0~0_13) (= 0 v_~y$r_buff1_thd3~0_146) (= v_~weak$$choice2~0_110 0) (= v_~y$w_buff0_used~0_739 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_20|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_28|, #length=|v_#length_32|} OutVars{ULTIMATE.start_main_#t~nondet32=|v_ULTIMATE.start_main_#t~nondet32_21|, ULTIMATE.start_main_~#t791~0.offset=|v_ULTIMATE.start_main_~#t791~0.offset_17|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_33|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_30|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_28|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_33|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_284|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_37|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_41|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~a~0=v_~a~0_26, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_29|, ~y$mem_tmp~0=v_~y$mem_tmp~0_18, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_27, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_146, ULTIMATE.start_main_~#t790~0.base=|v_ULTIMATE.start_main_~#t790~0.base_23|, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_30, ~y$flush_delayed~0=v_~y$flush_delayed~0_35, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_21, #length=|v_#length_31|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_54|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_28|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_25|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_55|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_20|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_46|, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_149, ~y$w_buff1~0=v_~y$w_buff1~0_158, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_97, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_136, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_273, ~x~0=v_~x~0_55, ULTIMATE.start_main_~#t792~0.base=|v_ULTIMATE.start_main_~#t792~0.base_20|, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_739, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_27|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_29|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_40|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_24, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_25|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_36|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_158|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_39|, ULTIMATE.start_main_~#t790~0.offset=|v_ULTIMATE.start_main_~#t790~0.offset_18|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_94, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_33|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_51|, ~y$w_buff0~0=v_~y$w_buff0~0_171, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_170, ~y~0=v_~y~0_170, ULTIMATE.start_main_~#t789~0.base=|v_ULTIMATE.start_main_~#t789~0.base_24|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_9|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_9|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_46|, ULTIMATE.start_main_~#t789~0.offset=|v_ULTIMATE.start_main_~#t789~0.offset_18|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_52|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_39, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_25, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_32|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_103|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_158, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_83, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_154|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_357, #valid=|v_#valid_71|, #memory_int=|v_#memory_int_27|, ULTIMATE.start_main_~#t792~0.offset=|v_ULTIMATE.start_main_~#t792~0.offset_16|, ~z~0=v_~z~0_109, ~weak$$choice2~0=v_~weak$$choice2~0_110, ULTIMATE.start_main_~#t791~0.base=|v_ULTIMATE.start_main_~#t791~0.base_20|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_387} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet32, ULTIMATE.start_main_~#t791~0.offset, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ~y$read_delayed~0, ~a~0, ULTIMATE.start_main_#t~ite52, ~y$mem_tmp~0, ~__unbuffered_p0_EAX~0, ~y$r_buff1_thd3~0, ULTIMATE.start_main_~#t790~0.base, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ~__unbuffered_p3_EAX~0, #length, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$r_buff1_thd4~0, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_~#t792~0.base, ULTIMATE.start_main_#t~nondet31, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t790~0.offset, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite51, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_~#t789~0.base, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_~#t789~0.offset, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~__unbuffered_p3_EBX~0, ULTIMATE.start_main_#t~ite53, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ~y$r_buff0_thd4~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_~#t792~0.offset, ~z~0, ~weak$$choice2~0, ULTIMATE.start_main_~#t791~0.base, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 13:27:42,957 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L833-1-->L835: Formula: (and (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t790~0.base_10|) (= (store |v_#length_20| |v_ULTIMATE.start_main_~#t790~0.base_10| 4) |v_#length_19|) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t790~0.base_10| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t790~0.base_10|) |v_ULTIMATE.start_main_~#t790~0.offset_9| 1)) |v_#memory_int_15|) (= 0 (select |v_#valid_43| |v_ULTIMATE.start_main_~#t790~0.base_10|)) (= |v_#valid_42| (store |v_#valid_43| |v_ULTIMATE.start_main_~#t790~0.base_10| 1)) (= |v_ULTIMATE.start_main_~#t790~0.offset_9| 0) (not (= |v_ULTIMATE.start_main_~#t790~0.base_10| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_43|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{ULTIMATE.start_main_~#t790~0.offset=|v_ULTIMATE.start_main_~#t790~0.offset_9|, #StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, ULTIMATE.start_main_~#t790~0.base=|v_ULTIMATE.start_main_~#t790~0.base_10|, #valid=|v_#valid_42|, #memory_int=|v_#memory_int_15|, #length=|v_#length_19|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t790~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t790~0.base, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 13:27:42,958 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [835] [835] L835-1-->L837: Formula: (and (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t791~0.base_11| 4)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t791~0.base_11|) (= 0 (select |v_#valid_39| |v_ULTIMATE.start_main_~#t791~0.base_11|)) (= |v_ULTIMATE.start_main_~#t791~0.offset_10| 0) (= (store |v_#valid_39| |v_ULTIMATE.start_main_~#t791~0.base_11| 1) |v_#valid_38|) (not (= 0 |v_ULTIMATE.start_main_~#t791~0.base_11|)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t791~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t791~0.base_11|) |v_ULTIMATE.start_main_~#t791~0.offset_10| 2)) |v_#memory_int_13|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t791~0.offset=|v_ULTIMATE.start_main_~#t791~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_13|, #length=|v_#length_17|, ULTIMATE.start_main_~#t791~0.base=|v_ULTIMATE.start_main_~#t791~0.base_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t791~0.offset, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t791~0.base] because there is no mapped edge [2019-12-07 13:27:42,958 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] P2ENTRY-->L4-3: Formula: (and (= (ite (not (and (not (= 0 (mod v_~y$w_buff1_used~0_105 256))) (not (= 0 (mod v_~y$w_buff0_used~0_178 256))))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~y$w_buff0~0_34 v_~y$w_buff1~0_39) (= |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8)) (= 2 v_~y$w_buff0~0_33) (= v_P2Thread1of1ForFork0_~arg.base_6 |v_P2Thread1of1ForFork0_#in~arg.base_8|) (= v_~y$w_buff0_used~0_179 v_~y$w_buff1_used~0_105) (= v_~y$w_buff0_used~0_178 1) (= v_P2Thread1of1ForFork0_~arg.offset_6 |v_P2Thread1of1ForFork0_#in~arg.offset_8|)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_179, ~y$w_buff0~0=v_~y$w_buff0~0_34, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_6, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_178, ~y$w_buff1~0=v_~y$w_buff1~0_39, ~y$w_buff0~0=v_~y$w_buff0~0_33, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_6, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_105} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 13:27:42,958 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L837-1-->L839: Formula: (and (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t792~0.base_11| 4)) (not (= |v_ULTIMATE.start_main_~#t792~0.base_11| 0)) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t792~0.base_11|) (= (select |v_#valid_45| |v_ULTIMATE.start_main_~#t792~0.base_11|) 0) (= |v_#valid_44| (store |v_#valid_45| |v_ULTIMATE.start_main_~#t792~0.base_11| 1)) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t792~0.base_11| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t792~0.base_11|) |v_ULTIMATE.start_main_~#t792~0.offset_9| 3)) |v_#memory_int_17|) (= |v_ULTIMATE.start_main_~#t792~0.offset_9| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_~#t792~0.base=|v_ULTIMATE.start_main_~#t792~0.base_11|, #StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_4|, #valid=|v_#valid_44|, #memory_int=|v_#memory_int_17|, #length=|v_#length_21|, ULTIMATE.start_main_~#t792~0.offset=|v_ULTIMATE.start_main_~#t792~0.offset_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t792~0.base, ULTIMATE.start_main_#t~nondet23, #valid, #memory_int, #length, ULTIMATE.start_main_~#t792~0.offset] because there is no mapped edge [2019-12-07 13:27:42,959 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] P0ENTRY-->P0EXIT: Formula: (and (= v_P0Thread1of1ForFork2_~arg.base_6 |v_P0Thread1of1ForFork2_#in~arg.base_8|) (= v_~a~0_12 1) (= (+ v_~__unbuffered_cnt~0_48 1) v_~__unbuffered_cnt~0_47) (= |v_P0Thread1of1ForFork2_#res.offset_3| 0) (= v_P0Thread1of1ForFork2_~arg.offset_6 |v_P0Thread1of1ForFork2_#in~arg.offset_8|) (= v_~x~0_36 v_~__unbuffered_p0_EAX~0_17) (= 0 |v_P0Thread1of1ForFork2_#res.base_3|)) InVars {P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_48, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_8|, ~x~0=v_~x~0_36} OutVars{~a~0=v_~a~0_12, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_17, P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_8|, P0Thread1of1ForFork2_~arg.offset=v_P0Thread1of1ForFork2_~arg.offset_6, P0Thread1of1ForFork2_#res.offset=|v_P0Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_47, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_8|, P0Thread1of1ForFork2_#res.base=|v_P0Thread1of1ForFork2_#res.base_3|, ~x~0=v_~x~0_36, P0Thread1of1ForFork2_~arg.base=v_P0Thread1of1ForFork2_~arg.base_6} AuxVars[] AssignedVars[~a~0, ~__unbuffered_p0_EAX~0, P0Thread1of1ForFork2_~arg.offset, P0Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0, P0Thread1of1ForFork2_#res.base, P0Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-12-07 13:27:42,960 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L757-2-->L757-5: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In1158677860 256))) (.cse2 (= |P1Thread1of1ForFork3_#t~ite3_Out1158677860| |P1Thread1of1ForFork3_#t~ite4_Out1158677860|)) (.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In1158677860 256)))) (or (and (or .cse0 .cse1) .cse2 (= |P1Thread1of1ForFork3_#t~ite3_Out1158677860| ~y~0_In1158677860)) (and (not .cse1) (= ~y$w_buff1~0_In1158677860 |P1Thread1of1ForFork3_#t~ite3_Out1158677860|) .cse2 (not .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1158677860, ~y$w_buff1~0=~y$w_buff1~0_In1158677860, ~y~0=~y~0_In1158677860, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1158677860} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1158677860, ~y$w_buff1~0=~y$w_buff1~0_In1158677860, P1Thread1of1ForFork3_#t~ite4=|P1Thread1of1ForFork3_#t~ite4_Out1158677860|, P1Thread1of1ForFork3_#t~ite3=|P1Thread1of1ForFork3_#t~ite3_Out1158677860|, ~y~0=~y~0_In1158677860, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1158677860} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite4, P1Thread1of1ForFork3_#t~ite3] because there is no mapped edge [2019-12-07 13:27:42,960 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L758-->L758-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd2~0_In-355609908 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In-355609908 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork3_#t~ite5_Out-355609908|)) (and (= ~y$w_buff0_used~0_In-355609908 |P1Thread1of1ForFork3_#t~ite5_Out-355609908|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-355609908, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-355609908} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-355609908, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-355609908, P1Thread1of1ForFork3_#t~ite5=|P1Thread1of1ForFork3_#t~ite5_Out-355609908|} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite5] because there is no mapped edge [2019-12-07 13:27:42,960 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [807] [807] L810-2-->L810-4: Formula: (let ((.cse1 (= (mod ~y$r_buff1_thd4~0_In1585544267 256) 0)) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In1585544267 256)))) (or (and (= |P3Thread1of1ForFork1_#t~ite15_Out1585544267| ~y~0_In1585544267) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |P3Thread1of1ForFork1_#t~ite15_Out1585544267| ~y$w_buff1~0_In1585544267)))) InVars {~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1585544267, ~y$w_buff1~0=~y$w_buff1~0_In1585544267, ~y~0=~y~0_In1585544267, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1585544267} OutVars{~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1585544267, ~y$w_buff1~0=~y$w_buff1~0_In1585544267, P3Thread1of1ForFork1_#t~ite15=|P3Thread1of1ForFork1_#t~ite15_Out1585544267|, ~y~0=~y~0_In1585544267, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1585544267} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite15] because there is no mapped edge [2019-12-07 13:27:42,960 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [794] [794] L759-->L759-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff0_used~0_In-714486848 256))) (.cse2 (= (mod ~y$r_buff0_thd2~0_In-714486848 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In-714486848 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In-714486848 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork3_#t~ite6_Out-714486848|)) (and (or .cse3 .cse2) (= ~y$w_buff1_used~0_In-714486848 |P1Thread1of1ForFork3_#t~ite6_Out-714486848|) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-714486848, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-714486848, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-714486848, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-714486848} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-714486848, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-714486848, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-714486848, P1Thread1of1ForFork3_#t~ite6=|P1Thread1of1ForFork3_#t~ite6_Out-714486848|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-714486848} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite6] because there is no mapped edge [2019-12-07 13:27:42,960 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [731] [731] L810-4-->L811: Formula: (= v_~y~0_28 |v_P3Thread1of1ForFork1_#t~ite15_8|) InVars {P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_8|} OutVars{P3Thread1of1ForFork1_#t~ite16=|v_P3Thread1of1ForFork1_#t~ite16_13|, P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_7|, ~y~0=v_~y~0_28} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite16, P3Thread1of1ForFork1_#t~ite15, ~y~0] because there is no mapped edge [2019-12-07 13:27:42,960 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L811-->L811-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In1861063033 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd4~0_In1861063033 256)))) (or (and (not .cse0) (not .cse1) (= |P3Thread1of1ForFork1_#t~ite17_Out1861063033| 0)) (and (= |P3Thread1of1ForFork1_#t~ite17_Out1861063033| ~y$w_buff0_used~0_In1861063033) (or .cse0 .cse1)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1861063033, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1861063033} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1861063033, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1861063033, P3Thread1of1ForFork1_#t~ite17=|P3Thread1of1ForFork1_#t~ite17_Out1861063033|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite17] because there is no mapped edge [2019-12-07 13:27:42,961 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L812-->L812-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd4~0_In1085596246 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In1085596246 256))) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1085596246 256))) (.cse3 (= 0 (mod ~y$r_buff1_thd4~0_In1085596246 256)))) (or (and (or .cse0 .cse1) (= |P3Thread1of1ForFork1_#t~ite18_Out1085596246| ~y$w_buff1_used~0_In1085596246) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P3Thread1of1ForFork1_#t~ite18_Out1085596246| 0)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1085596246, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1085596246, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1085596246, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1085596246} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1085596246, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1085596246, P3Thread1of1ForFork1_#t~ite18=|P3Thread1of1ForFork1_#t~ite18_Out1085596246|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1085596246, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1085596246} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite18] because there is no mapped edge [2019-12-07 13:27:42,961 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L813-->L813-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd4~0_In634346640 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In634346640 256)))) (or (and (or .cse0 .cse1) (= |P3Thread1of1ForFork1_#t~ite19_Out634346640| ~y$r_buff0_thd4~0_In634346640)) (and (not .cse0) (not .cse1) (= |P3Thread1of1ForFork1_#t~ite19_Out634346640| 0)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In634346640, ~y$w_buff0_used~0=~y$w_buff0_used~0_In634346640} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In634346640, ~y$w_buff0_used~0=~y$w_buff0_used~0_In634346640, P3Thread1of1ForFork1_#t~ite19=|P3Thread1of1ForFork1_#t~ite19_Out634346640|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite19] because there is no mapped edge [2019-12-07 13:27:42,962 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L760-->L760-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-58177092 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-58177092 256)))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork3_#t~ite7_Out-58177092| 0)) (and (= |P1Thread1of1ForFork3_#t~ite7_Out-58177092| ~y$r_buff0_thd2~0_In-58177092) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-58177092, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-58177092} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-58177092, P1Thread1of1ForFork3_#t~ite7=|P1Thread1of1ForFork3_#t~ite7_Out-58177092|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-58177092} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite7] because there is no mapped edge [2019-12-07 13:27:42,962 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [810] [810] L761-->L761-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In-1005945924 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-1005945924 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In-1005945924 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In-1005945924 256) 0))) (or (and (= ~y$r_buff1_thd2~0_In-1005945924 |P1Thread1of1ForFork3_#t~ite8_Out-1005945924|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P1Thread1of1ForFork3_#t~ite8_Out-1005945924|) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1005945924, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1005945924, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1005945924, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1005945924} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1005945924, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1005945924, P1Thread1of1ForFork3_#t~ite8=|P1Thread1of1ForFork3_#t~ite8_Out-1005945924|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1005945924, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1005945924} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite8] because there is no mapped edge [2019-12-07 13:27:42,962 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L761-2-->P1EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_41 1) v_~__unbuffered_cnt~0_40) (= 0 |v_P1Thread1of1ForFork3_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork3_#res.base_3|) (= |v_P1Thread1of1ForFork3_#t~ite8_24| v_~y$r_buff1_thd2~0_111)) InVars {P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_41} OutVars{P1Thread1of1ForFork3_#res.base=|v_P1Thread1of1ForFork3_#res.base_3|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_111, P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_23|, P1Thread1of1ForFork3_#res.offset=|v_P1Thread1of1ForFork3_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#res.base, ~y$r_buff1_thd2~0, P1Thread1of1ForFork3_#t~ite8, P1Thread1of1ForFork3_#res.offset, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 13:27:42,962 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L788-->L788-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1285811244 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In-1285811244 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In-1285811244 |P2Thread1of1ForFork0_#t~ite11_Out-1285811244|)) (and (not .cse0) (= 0 |P2Thread1of1ForFork0_#t~ite11_Out-1285811244|) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1285811244, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1285811244} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1285811244, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-1285811244|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1285811244} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 13:27:42,963 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [813] [813] L789-->L789-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1736798882 256) 0)) (.cse0 (= (mod ~y$r_buff0_thd3~0_In-1736798882 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd3~0_In-1736798882 256))) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1736798882 256)))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite12_Out-1736798882| ~y$w_buff1_used~0_In-1736798882) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite12_Out-1736798882|) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1736798882, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1736798882, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1736798882, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1736798882} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1736798882, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1736798882, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-1736798882|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1736798882, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1736798882} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 13:27:42,963 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L790-->L791: Formula: (let ((.cse0 (= ~y$r_buff0_thd3~0_In-1855435202 ~y$r_buff0_thd3~0_Out-1855435202)) (.cse1 (= (mod ~y$r_buff0_thd3~0_In-1855435202 256) 0)) (.cse2 (= (mod ~y$w_buff0_used~0_In-1855435202 256) 0))) (or (and .cse0 .cse1) (and .cse0 .cse2) (and (not .cse1) (= 0 ~y$r_buff0_thd3~0_Out-1855435202) (not .cse2)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1855435202, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1855435202} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1855435202, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-1855435202, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-1855435202|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 13:27:42,963 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L791-->L791-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In-2058858830 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In-2058858830 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd3~0_In-2058858830 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-2058858830 256) 0))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd3~0_In-2058858830 |P2Thread1of1ForFork0_#t~ite14_Out-2058858830|) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite14_Out-2058858830|) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-2058858830, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2058858830, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2058858830, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2058858830} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out-2058858830|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-2058858830, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2058858830, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2058858830, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2058858830} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 13:27:42,963 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [847] [847] L791-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= v_~__unbuffered_cnt~0_59 (+ v_~__unbuffered_cnt~0_60 1)) (= v_~y$r_buff1_thd3~0_114 |v_P2Thread1of1ForFork0_#t~ite14_20|) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_20|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_60} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_19|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_114, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_59, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 13:27:42,964 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [792] [792] L814-->L814-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff1_thd4~0_In-2139722762 256))) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In-2139722762 256))) (.cse1 (= (mod ~y$r_buff0_thd4~0_In-2139722762 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-2139722762 256)))) (or (and (= ~y$r_buff1_thd4~0_In-2139722762 |P3Thread1of1ForFork1_#t~ite20_Out-2139722762|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |P3Thread1of1ForFork1_#t~ite20_Out-2139722762|)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-2139722762, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-2139722762, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2139722762, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2139722762} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-2139722762, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-2139722762, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2139722762, P3Thread1of1ForFork1_#t~ite20=|P3Thread1of1ForFork1_#t~ite20_Out-2139722762|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2139722762} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 13:27:42,964 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [846] [846] L814-2-->P3EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_54 1) v_~__unbuffered_cnt~0_53) (= |v_P3Thread1of1ForFork1_#t~ite20_28| v_~y$r_buff1_thd4~0_111) (= |v_P3Thread1of1ForFork1_#res.offset_3| 0) (= |v_P3Thread1of1ForFork1_#res.base_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_28|} OutVars{~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_111, P3Thread1of1ForFork1_#res.base=|v_P3Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_53, P3Thread1of1ForFork1_#res.offset=|v_P3Thread1of1ForFork1_#res.offset_3|, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_27|} AuxVars[] AssignedVars[~y$r_buff1_thd4~0, P3Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork1_#res.offset, P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 13:27:42,964 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L843-->L845-2: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (or (= (mod v_~y$w_buff0_used~0_216 256) 0) (= 0 (mod v_~y$r_buff0_thd0~0_104 256)))) InVars {~y$w_buff0_used~0=v_~y$w_buff0_used~0_216, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} OutVars{~y$w_buff0_used~0=v_~y$w_buff0_used~0_216, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 13:27:42,964 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L845-2-->L845-5: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite25_Out1301867602| |ULTIMATE.start_main_#t~ite26_Out1301867602|)) (.cse2 (= (mod ~y$r_buff1_thd0~0_In1301867602 256) 0)) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In1301867602 256)))) (or (and (= |ULTIMATE.start_main_#t~ite25_Out1301867602| ~y~0_In1301867602) .cse0 (or .cse1 .cse2)) (and (= |ULTIMATE.start_main_#t~ite25_Out1301867602| ~y$w_buff1~0_In1301867602) .cse0 (not .cse2) (not .cse1)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In1301867602, ~y~0=~y~0_In1301867602, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1301867602, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1301867602} OutVars{~y$w_buff1~0=~y$w_buff1~0_In1301867602, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out1301867602|, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out1301867602|, ~y~0=~y~0_In1301867602, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1301867602, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1301867602} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 13:27:42,964 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [797] [797] L846-->L846-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-389003387 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-389003387 256)))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite27_Out-389003387|)) (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In-389003387 |ULTIMATE.start_main_#t~ite27_Out-389003387|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-389003387, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-389003387} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-389003387, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-389003387, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-389003387|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 13:27:42,965 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L847-->L847-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff0_used~0_In-1110307918 256))) (.cse2 (= (mod ~y$r_buff0_thd0~0_In-1110307918 256) 0)) (.cse1 (= (mod ~y$w_buff1_used~0_In-1110307918 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-1110307918 256)))) (or (and (= 0 |ULTIMATE.start_main_#t~ite28_Out-1110307918|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (= ~y$w_buff1_used~0_In-1110307918 |ULTIMATE.start_main_#t~ite28_Out-1110307918|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1110307918, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1110307918, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1110307918, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1110307918} OutVars{ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out-1110307918|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1110307918, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1110307918, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1110307918, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1110307918} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 13:27:42,965 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [812] [812] L848-->L848-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-2079230198 256))) (.cse1 (= (mod ~y$r_buff0_thd0~0_In-2079230198 256) 0))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite29_Out-2079230198| 0) (not .cse1)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite29_Out-2079230198| ~y$r_buff0_thd0~0_In-2079230198)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-2079230198, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-2079230198} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-2079230198, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-2079230198|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-2079230198} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 13:27:42,966 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [790] [790] L849-->L849-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-1887937651 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd0~0_In-1887937651 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1887937651 256))) (.cse3 (= 0 (mod ~y$r_buff1_thd0~0_In-1887937651 256)))) (or (and (= ~y$r_buff1_thd0~0_In-1887937651 |ULTIMATE.start_main_#t~ite30_Out-1887937651|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |ULTIMATE.start_main_#t~ite30_Out-1887937651| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1887937651, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1887937651, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1887937651, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1887937651} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out-1887937651|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1887937651, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1887937651, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1887937651, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1887937651} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30] because there is no mapped edge [2019-12-07 13:27:42,967 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [852] [852] L858-->L858-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-1982313851 256)))) (or (and (= |ULTIMATE.start_main_#t~ite39_In-1982313851| |ULTIMATE.start_main_#t~ite39_Out-1982313851|) (not .cse0) (= |ULTIMATE.start_main_#t~ite40_Out-1982313851| ~y$w_buff1~0_In-1982313851)) (and (= ~y$w_buff1~0_In-1982313851 |ULTIMATE.start_main_#t~ite39_Out-1982313851|) .cse0 (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-1982313851 256)))) (or (= 0 (mod ~y$w_buff0_used~0_In-1982313851 256)) (and (= (mod ~y$r_buff1_thd0~0_In-1982313851 256) 0) .cse1) (and .cse1 (= (mod ~y$w_buff1_used~0_In-1982313851 256) 0)))) (= |ULTIMATE.start_main_#t~ite40_Out-1982313851| |ULTIMATE.start_main_#t~ite39_Out-1982313851|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1982313851, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1982313851, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_In-1982313851|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1982313851, ~weak$$choice2~0=~weak$$choice2~0_In-1982313851, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1982313851, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1982313851} OutVars{ULTIMATE.start_main_#t~ite40=|ULTIMATE.start_main_#t~ite40_Out-1982313851|, ~y$w_buff1~0=~y$w_buff1~0_In-1982313851, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1982313851, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out-1982313851|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1982313851, ~weak$$choice2~0=~weak$$choice2~0_In-1982313851, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1982313851, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1982313851} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 13:27:42,967 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L859-->L859-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-359966343 256) 0))) (or (and (= ~y$w_buff0_used~0_In-359966343 |ULTIMATE.start_main_#t~ite42_Out-359966343|) .cse0 (= |ULTIMATE.start_main_#t~ite43_Out-359966343| |ULTIMATE.start_main_#t~ite42_Out-359966343|) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-359966343 256) 0))) (or (and .cse1 (= (mod ~y$r_buff1_thd0~0_In-359966343 256) 0)) (and (= (mod ~y$w_buff1_used~0_In-359966343 256) 0) .cse1) (= 0 (mod ~y$w_buff0_used~0_In-359966343 256))))) (and (= |ULTIMATE.start_main_#t~ite43_Out-359966343| ~y$w_buff0_used~0_In-359966343) (= |ULTIMATE.start_main_#t~ite42_In-359966343| |ULTIMATE.start_main_#t~ite42_Out-359966343|) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-359966343, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-359966343, ~weak$$choice2~0=~weak$$choice2~0_In-359966343, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-359966343, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_In-359966343|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-359966343} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-359966343, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-359966343, ULTIMATE.start_main_#t~ite43=|ULTIMATE.start_main_#t~ite43_Out-359966343|, ~weak$$choice2~0=~weak$$choice2~0_In-359966343, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_Out-359966343|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-359966343, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-359966343} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 13:27:42,968 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [865] [865] L860-->L860-8: Formula: (let ((.cse4 (= 0 (mod ~weak$$choice2~0_In-1334516335 256))) (.cse3 (= |ULTIMATE.start_main_#t~ite46_Out-1334516335| |ULTIMATE.start_main_#t~ite45_Out-1334516335|)) (.cse5 (= 0 (mod ~y$w_buff1_used~0_In-1334516335 256))) (.cse2 (= (mod ~y$r_buff1_thd0~0_In-1334516335 256) 0)) (.cse6 (= 0 (mod ~y$r_buff0_thd0~0_In-1334516335 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1334516335 256)))) (or (let ((.cse1 (not .cse6))) (and (not .cse0) (= |ULTIMATE.start_main_#t~ite45_Out-1334516335| |ULTIMATE.start_main_#t~ite44_Out-1334516335|) (or .cse1 (not .cse2)) .cse3 .cse4 (or .cse1 (not .cse5)) (= 0 |ULTIMATE.start_main_#t~ite44_Out-1334516335|))) (and (= |ULTIMATE.start_main_#t~ite44_In-1334516335| |ULTIMATE.start_main_#t~ite44_Out-1334516335|) (or (and (= |ULTIMATE.start_main_#t~ite45_Out-1334516335| |ULTIMATE.start_main_#t~ite45_In-1334516335|) (not .cse4) (= ~y$w_buff1_used~0_In-1334516335 |ULTIMATE.start_main_#t~ite46_Out-1334516335|)) (and .cse4 .cse3 (= ~y$w_buff1_used~0_In-1334516335 |ULTIMATE.start_main_#t~ite45_Out-1334516335|) (or (and .cse5 .cse6) (and .cse2 .cse6) .cse0)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1334516335, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1334516335, ~weak$$choice2~0=~weak$$choice2~0_In-1334516335, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1334516335, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In-1334516335|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1334516335, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_In-1334516335|} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1334516335, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1334516335, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out-1334516335|, ~weak$$choice2~0=~weak$$choice2~0_In-1334516335, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1334516335, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out-1334516335|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1334516335, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_Out-1334516335|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-12-07 13:27:42,968 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [868] [868] L860-8-->L862: Formula: (and (not (= (mod v_~weak$$choice2~0_106 256) 0)) (= v_~y$w_buff1_used~0_383 |v_ULTIMATE.start_main_#t~ite46_36|) (= v_~y$r_buff0_thd0~0_352 v_~y$r_buff0_thd0~0_351)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_352, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~weak$$choice2~0=v_~weak$$choice2~0_106} OutVars{~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_351, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_35|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_31|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_34|, ~weak$$choice2~0=v_~weak$$choice2~0_106, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_33|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_383} AuxVars[] AssignedVars[~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 13:27:42,968 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L864-->L4: Formula: (and (= 0 v_~y$flush_delayed~0_25) (= v_~y~0_116 v_~y$mem_tmp~0_11) (not (= (mod v_~y$flush_delayed~0_26 256) 0)) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5| (mod v_~main$tmp_guard1~0_15 256))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_26, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_11, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ~y$flush_delayed~0=v_~y$flush_delayed~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15, ~y~0=v_~y~0_116, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_23|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ~y~0, ULTIMATE.start_main_#t~ite53, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 13:27:42,968 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 13:27:43,031 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_53904900-9218-4a81-b471-d6270c803fb1/bin/uautomizer/witness.graphml [2019-12-07 13:27:43,031 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 13:27:43,032 INFO L168 Benchmark]: Toolchain (without parser) took 259495.77 ms. Allocated memory was 1.0 GB in the beginning and 9.9 GB in the end (delta: 8.9 GB). Free memory was 937.1 MB in the beginning and 4.9 GB in the end (delta: -4.0 GB). Peak memory consumption was 4.9 GB. Max. memory is 11.5 GB. [2019-12-07 13:27:43,032 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 957.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 13:27:43,033 INFO L168 Benchmark]: CACSL2BoogieTranslator took 382.77 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 71.3 MB). Free memory was 937.1 MB in the beginning and 1.0 GB in the end (delta: -99.0 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. [2019-12-07 13:27:43,033 INFO L168 Benchmark]: Boogie Procedure Inliner took 42.17 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 3.0 MB). Peak memory consumption was 3.0 MB. Max. memory is 11.5 GB. [2019-12-07 13:27:43,033 INFO L168 Benchmark]: Boogie Preprocessor took 28.42 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 3.0 MB). Peak memory consumption was 3.0 MB. Max. memory is 11.5 GB. [2019-12-07 13:27:43,033 INFO L168 Benchmark]: RCFGBuilder took 429.28 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 970.0 MB in the end (delta: 60.1 MB). Peak memory consumption was 60.1 MB. Max. memory is 11.5 GB. [2019-12-07 13:27:43,034 INFO L168 Benchmark]: TraceAbstraction took 258533.45 ms. Allocated memory was 1.1 GB in the beginning and 9.9 GB in the end (delta: 8.8 GB). Free memory was 970.0 MB in the beginning and 5.0 GB in the end (delta: -4.0 GB). Peak memory consumption was 4.8 GB. Max. memory is 11.5 GB. [2019-12-07 13:27:43,034 INFO L168 Benchmark]: Witness Printer took 76.36 ms. Allocated memory is still 9.9 GB. Free memory was 5.0 GB in the beginning and 4.9 GB in the end (delta: 41.6 MB). Peak memory consumption was 41.6 MB. Max. memory is 11.5 GB. [2019-12-07 13:27:43,035 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 957.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 382.77 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 71.3 MB). Free memory was 937.1 MB in the beginning and 1.0 GB in the end (delta: -99.0 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 42.17 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 3.0 MB). Peak memory consumption was 3.0 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 28.42 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 3.0 MB). Peak memory consumption was 3.0 MB. Max. memory is 11.5 GB. * RCFGBuilder took 429.28 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 970.0 MB in the end (delta: 60.1 MB). Peak memory consumption was 60.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 258533.45 ms. Allocated memory was 1.1 GB in the beginning and 9.9 GB in the end (delta: 8.8 GB). Free memory was 970.0 MB in the beginning and 5.0 GB in the end (delta: -4.0 GB). Peak memory consumption was 4.8 GB. Max. memory is 11.5 GB. * Witness Printer took 76.36 ms. Allocated memory is still 9.9 GB. Free memory was 5.0 GB in the beginning and 4.9 GB in the end (delta: 41.6 MB). Peak memory consumption was 41.6 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.3s, 192 ProgramPointsBefore, 97 ProgramPointsAfterwards, 226 TransitionsBefore, 103 TransitionsAfterwards, 18432 CoEnabledTransitionPairs, 8 FixpointIterations, 36 TrivialSequentialCompositions, 54 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 37 ConcurrentYvCompositions, 33 ChoiceCompositions, 6018 VarBasedMoverChecksPositive, 223 VarBasedMoverChecksNegative, 64 SemBasedMoverChecksPositive, 227 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.7s, 0 MoverChecksTotal, 86545 CheckedPairsTotal, 127 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L833] FCALL, FORK 0 pthread_create(&t789, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L835] FCALL, FORK 0 pthread_create(&t790, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L837] FCALL, FORK 0 pthread_create(&t791, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L776] 3 y$r_buff1_thd0 = y$r_buff0_thd0 [L777] 3 y$r_buff1_thd1 = y$r_buff0_thd1 [L778] 3 y$r_buff1_thd2 = y$r_buff0_thd2 [L779] 3 y$r_buff1_thd3 = y$r_buff0_thd3 [L780] 3 y$r_buff1_thd4 = y$r_buff0_thd4 [L781] 3 y$r_buff0_thd3 = (_Bool)1 [L784] 3 z = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L839] FCALL, FORK 0 pthread_create(&t792, ((void *)0), P3, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L801] 4 z = 2 [L804] 4 __unbuffered_p3_EAX = z [L807] 4 __unbuffered_p3_EBX = a VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L810] 4 y$w_buff0_used && y$r_buff0_thd4 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd4 ? y$w_buff1 : y) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L751] 2 x = 1 [L754] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L757] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L757] 2 y = y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) [L758] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L811] 4 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd4 ? (_Bool)0 : y$w_buff0_used [L812] 4 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd4 || y$w_buff1_used && y$r_buff1_thd4 ? (_Bool)0 : y$w_buff1_used [L787] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L759] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L760] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L787] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L788] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L789] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L813] 4 y$r_buff0_thd4 = y$w_buff0_used && y$r_buff0_thd4 ? (_Bool)0 : y$r_buff0_thd4 [L841] 0 main$tmp_guard0 = __unbuffered_cnt == 4 VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L845] 0 y = y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L846] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L847] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L848] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L849] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L852] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L853] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L854] 0 y$flush_delayed = weak$$choice2 [L855] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L856] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L856] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L857] EXPR 0 weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L857] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L858] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L859] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L862] EXPR 0 weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L862] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L863] 0 main$tmp_guard1 = !(y == 2 && z == 2 && __unbuffered_p0_EAX == 0 && __unbuffered_p3_EAX == 2 && __unbuffered_p3_EBX == 0) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p0_EAX=0, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 180 locations, 2 error locations. Result: UNSAFE, OverallTime: 258.3s, OverallIterations: 29, TraceHistogramMax: 1, AutomataDifference: 65.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 5507 SDtfs, 5758 SDslu, 11887 SDs, 0 SdLazy, 6641 SolverSat, 290 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 260 GetRequests, 55 SyntacticMatches, 33 SemanticMatches, 172 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 160 ImplicationChecksByTransitivity, 1.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=423132occurred in iteration=7, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 148.3s AutomataMinimizationTime, 28 MinimizatonAttempts, 747671 StatesRemovedByMinimization, 24 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.8s InterpolantComputationTime, 1276 NumberOfCodeBlocks, 1276 NumberOfCodeBlocksAsserted, 29 NumberOfCheckSat, 1178 ConstructedInterpolants, 0 QuantifiedInterpolants, 202219 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 28 InterpolantComputations, 28 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...