./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix030_power.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_574666ef-5228-4dc6-973e-31744f12bb1b/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_574666ef-5228-4dc6-973e-31744f12bb1b/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_574666ef-5228-4dc6-973e-31744f12bb1b/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_574666ef-5228-4dc6-973e-31744f12bb1b/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix030_power.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_574666ef-5228-4dc6-973e-31744f12bb1b/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_574666ef-5228-4dc6-973e-31744f12bb1b/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash cccc56ad4a19fb304e7921abf6a31a993feeb081 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:46:28,023 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:46:28,024 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:46:28,032 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:46:28,032 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:46:28,033 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:46:28,034 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:46:28,035 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:46:28,036 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:46:28,037 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:46:28,037 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:46:28,038 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:46:28,038 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:46:28,039 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:46:28,040 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:46:28,040 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:46:28,041 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:46:28,041 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:46:28,043 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:46:28,044 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:46:28,045 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:46:28,046 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:46:28,047 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:46:28,047 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:46:28,049 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:46:28,049 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:46:28,049 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:46:28,049 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:46:28,050 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:46:28,050 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:46:28,050 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:46:28,051 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:46:28,051 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:46:28,052 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:46:28,052 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:46:28,052 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:46:28,053 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:46:28,053 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:46:28,053 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:46:28,054 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:46:28,054 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:46:28,055 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_574666ef-5228-4dc6-973e-31744f12bb1b/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 18:46:28,064 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:46:28,064 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:46:28,065 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:46:28,065 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:46:28,065 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:46:28,065 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:46:28,065 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:46:28,065 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:46:28,066 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:46:28,066 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:46:28,066 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 18:46:28,066 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 18:46:28,066 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 18:46:28,066 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:46:28,066 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:46:28,066 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:46:28,067 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 18:46:28,067 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:46:28,067 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:46:28,067 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 18:46:28,067 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 18:46:28,067 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:46:28,067 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:46:28,067 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 18:46:28,068 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 18:46:28,068 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:46:28,068 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 18:46:28,068 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 18:46:28,068 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:46:28,068 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_574666ef-5228-4dc6-973e-31744f12bb1b/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> cccc56ad4a19fb304e7921abf6a31a993feeb081 [2019-12-07 18:46:28,167 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:46:28,177 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:46:28,180 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:46:28,182 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:46:28,182 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:46:28,182 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_574666ef-5228-4dc6-973e-31744f12bb1b/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix030_power.opt.i [2019-12-07 18:46:28,221 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_574666ef-5228-4dc6-973e-31744f12bb1b/bin/uautomizer/data/489fb5ad3/7def6816764e411a838a8a8dc28a8e9f/FLAG1223fdd0f [2019-12-07 18:46:28,595 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:46:28,596 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_574666ef-5228-4dc6-973e-31744f12bb1b/sv-benchmarks/c/pthread-wmm/mix030_power.opt.i [2019-12-07 18:46:28,607 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_574666ef-5228-4dc6-973e-31744f12bb1b/bin/uautomizer/data/489fb5ad3/7def6816764e411a838a8a8dc28a8e9f/FLAG1223fdd0f [2019-12-07 18:46:28,616 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_574666ef-5228-4dc6-973e-31744f12bb1b/bin/uautomizer/data/489fb5ad3/7def6816764e411a838a8a8dc28a8e9f [2019-12-07 18:46:28,618 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:46:28,619 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:46:28,620 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:46:28,620 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:46:28,622 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:46:28,622 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:46:28" (1/1) ... [2019-12-07 18:46:28,624 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7d8e373 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:28, skipping insertion in model container [2019-12-07 18:46:28,624 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:46:28" (1/1) ... [2019-12-07 18:46:28,629 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:46:28,658 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:46:28,929 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:46:28,937 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:46:28,979 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:46:29,026 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:46:29,026 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:29 WrapperNode [2019-12-07 18:46:29,026 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:46:29,027 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:46:29,027 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:46:29,027 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:46:29,032 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:29" (1/1) ... [2019-12-07 18:46:29,045 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:29" (1/1) ... [2019-12-07 18:46:29,066 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:46:29,066 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:46:29,066 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:46:29,066 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:46:29,072 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:29" (1/1) ... [2019-12-07 18:46:29,073 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:29" (1/1) ... [2019-12-07 18:46:29,076 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:29" (1/1) ... [2019-12-07 18:46:29,076 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:29" (1/1) ... [2019-12-07 18:46:29,084 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:29" (1/1) ... [2019-12-07 18:46:29,087 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:29" (1/1) ... [2019-12-07 18:46:29,089 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:29" (1/1) ... [2019-12-07 18:46:29,092 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:46:29,093 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:46:29,093 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:46:29,093 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:46:29,093 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:29" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_574666ef-5228-4dc6-973e-31744f12bb1b/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:46:29,133 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 18:46:29,133 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 18:46:29,133 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 18:46:29,134 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 18:46:29,134 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 18:46:29,134 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 18:46:29,134 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 18:46:29,134 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 18:46:29,134 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 18:46:29,134 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 18:46:29,134 INFO L130 BoogieDeclarations]: Found specification of procedure P3 [2019-12-07 18:46:29,134 INFO L138 BoogieDeclarations]: Found implementation of procedure P3 [2019-12-07 18:46:29,134 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 18:46:29,134 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:46:29,135 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:46:29,136 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 18:46:29,510 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:46:29,510 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 18:46:29,511 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:46:29 BoogieIcfgContainer [2019-12-07 18:46:29,511 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:46:29,512 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 18:46:29,512 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 18:46:29,514 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 18:46:29,514 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 06:46:28" (1/3) ... [2019-12-07 18:46:29,514 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2fc35c76 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:46:29, skipping insertion in model container [2019-12-07 18:46:29,514 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:29" (2/3) ... [2019-12-07 18:46:29,515 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2fc35c76 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:46:29, skipping insertion in model container [2019-12-07 18:46:29,515 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:46:29" (3/3) ... [2019-12-07 18:46:29,516 INFO L109 eAbstractionObserver]: Analyzing ICFG mix030_power.opt.i [2019-12-07 18:46:29,522 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 18:46:29,522 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 18:46:29,527 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 18:46:29,527 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 18:46:29,551 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,551 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,551 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,551 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,551 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,552 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,552 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,552 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,552 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork3_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,552 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork3_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,552 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,552 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,553 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,553 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,553 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,553 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,553 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,553 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,553 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,553 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,554 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,554 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,554 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,554 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,554 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,554 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,554 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,554 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,555 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,555 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,555 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,555 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,555 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,555 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,555 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,555 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,556 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,556 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,556 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,556 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,556 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,556 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,556 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,557 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,557 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,557 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,557 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,557 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,557 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,557 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,557 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,558 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,558 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,558 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,558 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,558 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,558 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,558 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,558 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,558 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,559 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,559 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,559 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,559 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,559 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,559 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,559 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,559 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,559 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,559 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,560 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,560 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,560 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,560 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,560 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,560 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,560 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,561 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,561 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,561 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,561 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,561 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,561 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,561 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,561 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,561 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,561 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,562 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,562 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,562 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,562 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,562 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,562 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,562 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,562 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,562 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,563 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,563 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,563 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,563 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:46:29,575 INFO L249 AbstractCegarLoop]: Starting to check reachability of 7 error locations. [2019-12-07 18:46:29,587 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 18:46:29,587 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 18:46:29,587 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 18:46:29,587 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:46:29,587 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:46:29,587 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 18:46:29,588 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:46:29,588 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 18:46:29,598 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 191 places, 225 transitions [2019-12-07 18:46:29,600 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 191 places, 225 transitions [2019-12-07 18:46:29,659 INFO L134 PetriNetUnfolder]: 47/221 cut-off events. [2019-12-07 18:46:29,659 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:46:29,670 INFO L76 FinitePrefix]: Finished finitePrefix Result has 234 conditions, 221 events. 47/221 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 572 event pairs. 12/184 useless extension candidates. Maximal degree in co-relation 190. Up to 2 conditions per place. [2019-12-07 18:46:29,685 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 191 places, 225 transitions [2019-12-07 18:46:29,716 INFO L134 PetriNetUnfolder]: 47/221 cut-off events. [2019-12-07 18:46:29,716 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:46:29,722 INFO L76 FinitePrefix]: Finished finitePrefix Result has 234 conditions, 221 events. 47/221 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 572 event pairs. 12/184 useless extension candidates. Maximal degree in co-relation 190. Up to 2 conditions per place. [2019-12-07 18:46:29,737 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 18432 [2019-12-07 18:46:29,738 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 18:46:32,800 WARN L192 SmtUtils]: Spent 169.00 ms on a formula simplification. DAG size of input: 95 DAG size of output: 93 [2019-12-07 18:46:32,893 INFO L206 etLargeBlockEncoding]: Checked pairs total: 85060 [2019-12-07 18:46:32,893 INFO L214 etLargeBlockEncoding]: Total number of compositions: 120 [2019-12-07 18:46:32,896 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 104 places, 115 transitions [2019-12-07 18:47:35,355 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 247806 states. [2019-12-07 18:47:35,356 INFO L276 IsEmpty]: Start isEmpty. Operand 247806 states. [2019-12-07 18:47:35,361 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-12-07 18:47:35,361 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:35,361 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:35,361 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:35,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:35,366 INFO L82 PathProgramCache]: Analyzing trace with hash 1977456045, now seen corresponding path program 1 times [2019-12-07 18:47:35,371 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:35,372 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475006811] [2019-12-07 18:47:35,372 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:35,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:35,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:35,534 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [475006811] [2019-12-07 18:47:35,535 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:35,535 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:47:35,536 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [648798981] [2019-12-07 18:47:35,540 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:47:35,540 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:35,552 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:47:35,553 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:47:35,555 INFO L87 Difference]: Start difference. First operand 247806 states. Second operand 3 states. [2019-12-07 18:47:39,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:39,049 INFO L93 Difference]: Finished difference Result 246830 states and 1186092 transitions. [2019-12-07 18:47:39,049 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:47:39,050 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-12-07 18:47:39,051 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:40,093 INFO L225 Difference]: With dead ends: 246830 [2019-12-07 18:47:40,093 INFO L226 Difference]: Without dead ends: 242126 [2019-12-07 18:47:40,094 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:47:50,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242126 states. [2019-12-07 18:47:54,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242126 to 242126. [2019-12-07 18:47:54,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 242126 states. [2019-12-07 18:47:55,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 242126 states to 242126 states and 1164532 transitions. [2019-12-07 18:47:55,584 INFO L78 Accepts]: Start accepts. Automaton has 242126 states and 1164532 transitions. Word has length 7 [2019-12-07 18:47:55,585 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:55,585 INFO L462 AbstractCegarLoop]: Abstraction has 242126 states and 1164532 transitions. [2019-12-07 18:47:55,585 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:47:55,585 INFO L276 IsEmpty]: Start isEmpty. Operand 242126 states and 1164532 transitions. [2019-12-07 18:47:55,590 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:47:55,590 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:55,590 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:55,590 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:55,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:55,590 INFO L82 PathProgramCache]: Analyzing trace with hash -1148535013, now seen corresponding path program 1 times [2019-12-07 18:47:55,590 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:55,591 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [61036499] [2019-12-07 18:47:55,591 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:55,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:55,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:55,663 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [61036499] [2019-12-07 18:47:55,663 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:55,664 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:47:55,664 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1603218146] [2019-12-07 18:47:55,665 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:47:55,665 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:55,665 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:47:55,665 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:47:55,665 INFO L87 Difference]: Start difference. First operand 242126 states and 1164532 transitions. Second operand 4 states. [2019-12-07 18:48:01,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:48:01,102 INFO L93 Difference]: Finished difference Result 378478 states and 1756574 transitions. [2019-12-07 18:48:01,102 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:48:01,103 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 18:48:01,103 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:48:02,214 INFO L225 Difference]: With dead ends: 378478 [2019-12-07 18:48:02,215 INFO L226 Difference]: Without dead ends: 378380 [2019-12-07 18:48:02,215 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:48:15,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 378380 states. [2019-12-07 18:48:20,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 378380 to 348970. [2019-12-07 18:48:20,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 348970 states. [2019-12-07 18:48:22,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 348970 states to 348970 states and 1635532 transitions. [2019-12-07 18:48:22,409 INFO L78 Accepts]: Start accepts. Automaton has 348970 states and 1635532 transitions. Word has length 13 [2019-12-07 18:48:22,409 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:48:22,409 INFO L462 AbstractCegarLoop]: Abstraction has 348970 states and 1635532 transitions. [2019-12-07 18:48:22,409 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:48:22,409 INFO L276 IsEmpty]: Start isEmpty. Operand 348970 states and 1635532 transitions. [2019-12-07 18:48:22,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 18:48:22,415 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:48:22,415 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:48:22,415 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:48:22,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:22,416 INFO L82 PathProgramCache]: Analyzing trace with hash -195341508, now seen corresponding path program 1 times [2019-12-07 18:48:22,416 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:22,416 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1325015544] [2019-12-07 18:48:22,416 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:22,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:22,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:48:22,482 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1325015544] [2019-12-07 18:48:22,483 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:48:22,483 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:48:22,483 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [812408067] [2019-12-07 18:48:22,483 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:48:22,483 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:48:22,483 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:48:22,484 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:48:22,484 INFO L87 Difference]: Start difference. First operand 348970 states and 1635532 transitions. Second operand 4 states. [2019-12-07 18:48:28,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:48:28,721 INFO L93 Difference]: Finished difference Result 443358 states and 2051772 transitions. [2019-12-07 18:48:28,722 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:48:28,722 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 18:48:28,722 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:48:30,525 INFO L225 Difference]: With dead ends: 443358 [2019-12-07 18:48:30,525 INFO L226 Difference]: Without dead ends: 443358 [2019-12-07 18:48:30,526 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:48:44,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 443358 states. [2019-12-07 18:48:50,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 443358 to 395566. [2019-12-07 18:48:50,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 395566 states. [2019-12-07 18:48:52,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 395566 states to 395566 states and 1844254 transitions. [2019-12-07 18:48:52,547 INFO L78 Accepts]: Start accepts. Automaton has 395566 states and 1844254 transitions. Word has length 15 [2019-12-07 18:48:52,547 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:48:52,547 INFO L462 AbstractCegarLoop]: Abstraction has 395566 states and 1844254 transitions. [2019-12-07 18:48:52,547 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:48:52,548 INFO L276 IsEmpty]: Start isEmpty. Operand 395566 states and 1844254 transitions. [2019-12-07 18:48:52,552 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 18:48:52,552 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:48:52,552 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:48:52,552 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:48:52,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:52,553 INFO L82 PathProgramCache]: Analyzing trace with hash 1056904453, now seen corresponding path program 1 times [2019-12-07 18:48:52,553 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:52,553 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [441935183] [2019-12-07 18:48:52,553 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:52,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:52,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:48:52,603 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [441935183] [2019-12-07 18:48:52,603 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:48:52,603 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:48:52,603 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [932819304] [2019-12-07 18:48:52,603 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:48:52,604 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:48:52,604 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:48:52,604 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:48:52,604 INFO L87 Difference]: Start difference. First operand 395566 states and 1844254 transitions. Second operand 4 states. [2019-12-07 18:48:59,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:48:59,721 INFO L93 Difference]: Finished difference Result 544758 states and 2498476 transitions. [2019-12-07 18:48:59,721 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:48:59,722 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 18:48:59,722 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:49:01,331 INFO L225 Difference]: With dead ends: 544758 [2019-12-07 18:49:01,332 INFO L226 Difference]: Without dead ends: 544632 [2019-12-07 18:49:01,332 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:49:17,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 544632 states. [2019-12-07 18:49:24,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 544632 to 445950. [2019-12-07 18:49:24,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 445950 states. [2019-12-07 18:49:26,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 445950 states to 445950 states and 2076166 transitions. [2019-12-07 18:49:26,727 INFO L78 Accepts]: Start accepts. Automaton has 445950 states and 2076166 transitions. Word has length 15 [2019-12-07 18:49:26,727 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:49:26,727 INFO L462 AbstractCegarLoop]: Abstraction has 445950 states and 2076166 transitions. [2019-12-07 18:49:26,727 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:49:26,727 INFO L276 IsEmpty]: Start isEmpty. Operand 445950 states and 2076166 transitions. [2019-12-07 18:49:26,768 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 18:49:26,768 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:49:26,768 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:49:26,769 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:49:26,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:26,769 INFO L82 PathProgramCache]: Analyzing trace with hash 897732386, now seen corresponding path program 1 times [2019-12-07 18:49:26,769 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:26,769 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [131506553] [2019-12-07 18:49:26,769 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:26,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:26,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:26,830 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [131506553] [2019-12-07 18:49:26,830 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:49:26,830 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:49:26,830 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [781672685] [2019-12-07 18:49:26,830 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:49:26,830 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:26,831 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:49:26,831 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:49:26,831 INFO L87 Difference]: Start difference. First operand 445950 states and 2076166 transitions. Second operand 5 states. [2019-12-07 18:49:35,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:35,048 INFO L93 Difference]: Finished difference Result 656704 states and 2996335 transitions. [2019-12-07 18:49:35,049 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:49:35,049 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2019-12-07 18:49:35,049 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:49:37,571 INFO L225 Difference]: With dead ends: 656704 [2019-12-07 18:49:37,571 INFO L226 Difference]: Without dead ends: 656578 [2019-12-07 18:49:37,572 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:49:54,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 656578 states. [2019-12-07 18:50:03,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 656578 to 470878. [2019-12-07 18:50:03,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 470878 states. [2019-12-07 18:50:14,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 470878 states to 470878 states and 2182366 transitions. [2019-12-07 18:50:14,965 INFO L78 Accepts]: Start accepts. Automaton has 470878 states and 2182366 transitions. Word has length 21 [2019-12-07 18:50:14,965 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:50:14,965 INFO L462 AbstractCegarLoop]: Abstraction has 470878 states and 2182366 transitions. [2019-12-07 18:50:14,965 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:50:14,965 INFO L276 IsEmpty]: Start isEmpty. Operand 470878 states and 2182366 transitions. [2019-12-07 18:50:14,992 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 18:50:14,992 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:50:14,992 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:14,992 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:50:14,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:14,993 INFO L82 PathProgramCache]: Analyzing trace with hash 782357866, now seen corresponding path program 1 times [2019-12-07 18:50:14,993 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:14,993 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2104543343] [2019-12-07 18:50:14,993 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:15,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:15,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:15,046 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2104543343] [2019-12-07 18:50:15,046 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:15,046 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:50:15,046 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1432263087] [2019-12-07 18:50:15,047 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:50:15,047 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:15,047 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:50:15,047 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:50:15,047 INFO L87 Difference]: Start difference. First operand 470878 states and 2182366 transitions. Second operand 5 states. [2019-12-07 18:50:24,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:24,707 INFO L93 Difference]: Finished difference Result 680728 states and 3098485 transitions. [2019-12-07 18:50:24,707 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:50:24,707 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2019-12-07 18:50:24,707 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:50:26,713 INFO L225 Difference]: With dead ends: 680728 [2019-12-07 18:50:26,713 INFO L226 Difference]: Without dead ends: 680602 [2019-12-07 18:50:26,714 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 0 SyntacticMatches, 3 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:50:44,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 680602 states. [2019-12-07 18:50:53,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 680602 to 486100. [2019-12-07 18:50:53,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 486100 states. [2019-12-07 18:50:56,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486100 states to 486100 states and 2249451 transitions. [2019-12-07 18:50:56,064 INFO L78 Accepts]: Start accepts. Automaton has 486100 states and 2249451 transitions. Word has length 21 [2019-12-07 18:50:56,064 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:50:56,064 INFO L462 AbstractCegarLoop]: Abstraction has 486100 states and 2249451 transitions. [2019-12-07 18:50:56,064 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:50:56,064 INFO L276 IsEmpty]: Start isEmpty. Operand 486100 states and 2249451 transitions. [2019-12-07 18:50:56,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 18:50:56,093 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:50:56,093 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:56,093 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:50:56,093 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:56,093 INFO L82 PathProgramCache]: Analyzing trace with hash -831169421, now seen corresponding path program 1 times [2019-12-07 18:50:56,093 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:56,093 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [547729405] [2019-12-07 18:50:56,094 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:56,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:56,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:56,155 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [547729405] [2019-12-07 18:50:56,155 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:56,155 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:50:56,155 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [275840580] [2019-12-07 18:50:56,156 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:50:56,156 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:56,156 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:50:56,156 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:50:56,156 INFO L87 Difference]: Start difference. First operand 486100 states and 2249451 transitions. Second operand 5 states. [2019-12-07 18:51:06,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:51:06,036 INFO L93 Difference]: Finished difference Result 785524 states and 3579471 transitions. [2019-12-07 18:51:06,037 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:51:06,037 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2019-12-07 18:51:06,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:51:08,908 INFO L225 Difference]: With dead ends: 785524 [2019-12-07 18:51:08,908 INFO L226 Difference]: Without dead ends: 785230 [2019-12-07 18:51:08,909 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:51:28,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 785230 states. [2019-12-07 18:51:38,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 785230 to 541362. [2019-12-07 18:51:38,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 541362 states. [2019-12-07 18:51:41,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 541362 states to 541362 states and 2502846 transitions. [2019-12-07 18:51:41,480 INFO L78 Accepts]: Start accepts. Automaton has 541362 states and 2502846 transitions. Word has length 21 [2019-12-07 18:51:41,480 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:51:41,480 INFO L462 AbstractCegarLoop]: Abstraction has 541362 states and 2502846 transitions. [2019-12-07 18:51:41,480 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:51:41,481 INFO L276 IsEmpty]: Start isEmpty. Operand 541362 states and 2502846 transitions. [2019-12-07 18:51:41,618 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 18:51:41,619 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:51:41,619 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:51:41,619 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:51:41,619 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:51:41,619 INFO L82 PathProgramCache]: Analyzing trace with hash -1103508272, now seen corresponding path program 1 times [2019-12-07 18:51:41,619 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:51:41,620 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [696634338] [2019-12-07 18:51:41,620 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:51:41,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:51:41,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:51:41,664 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [696634338] [2019-12-07 18:51:41,664 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:51:41,665 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:51:41,665 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1283324807] [2019-12-07 18:51:41,665 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:51:41,665 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:51:41,665 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:51:41,665 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:51:41,665 INFO L87 Difference]: Start difference. First operand 541362 states and 2502846 transitions. Second operand 4 states. [2019-12-07 18:51:47,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:51:47,797 INFO L93 Difference]: Finished difference Result 330793 states and 1364785 transitions. [2019-12-07 18:51:47,798 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:51:47,798 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 27 [2019-12-07 18:51:47,798 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:51:48,631 INFO L225 Difference]: With dead ends: 330793 [2019-12-07 18:51:48,631 INFO L226 Difference]: Without dead ends: 319217 [2019-12-07 18:51:48,631 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:51:56,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 319217 states. [2019-12-07 18:52:00,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 319217 to 319217. [2019-12-07 18:52:00,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 319217 states. [2019-12-07 18:52:01,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 319217 states to 319217 states and 1321493 transitions. [2019-12-07 18:52:01,864 INFO L78 Accepts]: Start accepts. Automaton has 319217 states and 1321493 transitions. Word has length 27 [2019-12-07 18:52:01,864 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:01,864 INFO L462 AbstractCegarLoop]: Abstraction has 319217 states and 1321493 transitions. [2019-12-07 18:52:01,864 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:52:01,864 INFO L276 IsEmpty]: Start isEmpty. Operand 319217 states and 1321493 transitions. [2019-12-07 18:52:01,927 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 18:52:01,927 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:01,927 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:01,927 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:01,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:01,927 INFO L82 PathProgramCache]: Analyzing trace with hash 580994948, now seen corresponding path program 1 times [2019-12-07 18:52:01,928 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:01,928 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1306534542] [2019-12-07 18:52:01,928 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:01,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:01,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:01,996 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1306534542] [2019-12-07 18:52:01,996 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:01,996 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:52:01,996 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [791704396] [2019-12-07 18:52:01,996 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:52:01,997 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:01,997 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:52:01,997 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:52:01,997 INFO L87 Difference]: Start difference. First operand 319217 states and 1321493 transitions. Second operand 6 states. [2019-12-07 18:52:04,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:04,929 INFO L93 Difference]: Finished difference Result 379398 states and 1553189 transitions. [2019-12-07 18:52:04,930 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 18:52:04,930 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 28 [2019-12-07 18:52:04,930 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:05,897 INFO L225 Difference]: With dead ends: 379398 [2019-12-07 18:52:05,897 INFO L226 Difference]: Without dead ends: 379238 [2019-12-07 18:52:05,897 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=81, Invalid=191, Unknown=0, NotChecked=0, Total=272 [2019-12-07 18:52:14,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 379238 states. [2019-12-07 18:52:18,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 379238 to 266981. [2019-12-07 18:52:18,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 266981 states. [2019-12-07 18:52:19,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 266981 states to 266981 states and 1111163 transitions. [2019-12-07 18:52:19,488 INFO L78 Accepts]: Start accepts. Automaton has 266981 states and 1111163 transitions. Word has length 28 [2019-12-07 18:52:19,488 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:19,488 INFO L462 AbstractCegarLoop]: Abstraction has 266981 states and 1111163 transitions. [2019-12-07 18:52:19,488 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:52:19,489 INFO L276 IsEmpty]: Start isEmpty. Operand 266981 states and 1111163 transitions. [2019-12-07 18:52:19,570 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2019-12-07 18:52:19,570 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:19,570 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:19,570 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:19,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:19,570 INFO L82 PathProgramCache]: Analyzing trace with hash -1772573408, now seen corresponding path program 1 times [2019-12-07 18:52:19,570 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:19,571 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [265491902] [2019-12-07 18:52:19,571 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:19,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:19,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:19,604 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [265491902] [2019-12-07 18:52:19,604 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:19,604 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:52:19,605 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1725188387] [2019-12-07 18:52:19,605 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:52:19,605 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:19,605 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:52:19,605 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:19,605 INFO L87 Difference]: Start difference. First operand 266981 states and 1111163 transitions. Second operand 3 states. [2019-12-07 18:52:21,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:21,485 INFO L93 Difference]: Finished difference Result 316908 states and 1306760 transitions. [2019-12-07 18:52:21,485 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:52:21,485 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 30 [2019-12-07 18:52:21,486 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:22,291 INFO L225 Difference]: With dead ends: 316908 [2019-12-07 18:52:22,291 INFO L226 Difference]: Without dead ends: 316908 [2019-12-07 18:52:22,291 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:33,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 316908 states. [2019-12-07 18:52:37,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 316908 to 280376. [2019-12-07 18:52:37,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280376 states. [2019-12-07 18:52:38,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280376 states to 280376 states and 1166224 transitions. [2019-12-07 18:52:38,142 INFO L78 Accepts]: Start accepts. Automaton has 280376 states and 1166224 transitions. Word has length 30 [2019-12-07 18:52:38,143 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:38,143 INFO L462 AbstractCegarLoop]: Abstraction has 280376 states and 1166224 transitions. [2019-12-07 18:52:38,143 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:52:38,143 INFO L276 IsEmpty]: Start isEmpty. Operand 280376 states and 1166224 transitions. [2019-12-07 18:52:38,222 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2019-12-07 18:52:38,222 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:38,223 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:38,223 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:38,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:38,223 INFO L82 PathProgramCache]: Analyzing trace with hash -1772884245, now seen corresponding path program 1 times [2019-12-07 18:52:38,223 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:38,223 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798632309] [2019-12-07 18:52:38,223 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:38,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:38,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:38,268 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1798632309] [2019-12-07 18:52:38,268 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:38,268 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:52:38,268 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1978580852] [2019-12-07 18:52:38,268 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:52:38,268 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:38,268 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:52:38,269 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:52:38,269 INFO L87 Difference]: Start difference. First operand 280376 states and 1166224 transitions. Second operand 5 states. [2019-12-07 18:52:38,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:38,488 INFO L93 Difference]: Finished difference Result 61057 states and 204396 transitions. [2019-12-07 18:52:38,489 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:52:38,489 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 30 [2019-12-07 18:52:38,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:38,585 INFO L225 Difference]: With dead ends: 61057 [2019-12-07 18:52:38,586 INFO L226 Difference]: Without dead ends: 55207 [2019-12-07 18:52:38,586 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:52:39,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55207 states. [2019-12-07 18:52:39,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55207 to 55207. [2019-12-07 18:52:39,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55207 states. [2019-12-07 18:52:39,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55207 states to 55207 states and 182675 transitions. [2019-12-07 18:52:39,964 INFO L78 Accepts]: Start accepts. Automaton has 55207 states and 182675 transitions. Word has length 30 [2019-12-07 18:52:39,964 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:39,964 INFO L462 AbstractCegarLoop]: Abstraction has 55207 states and 182675 transitions. [2019-12-07 18:52:39,964 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:52:39,964 INFO L276 IsEmpty]: Start isEmpty. Operand 55207 states and 182675 transitions. [2019-12-07 18:52:39,995 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-12-07 18:52:39,995 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:39,996 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:39,996 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:39,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:39,996 INFO L82 PathProgramCache]: Analyzing trace with hash -458036937, now seen corresponding path program 1 times [2019-12-07 18:52:39,996 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:39,996 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [479804229] [2019-12-07 18:52:39,996 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:40,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:40,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:40,048 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [479804229] [2019-12-07 18:52:40,048 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:40,048 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:52:40,048 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [831579886] [2019-12-07 18:52:40,049 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:52:40,049 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:40,049 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:52:40,049 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:52:40,049 INFO L87 Difference]: Start difference. First operand 55207 states and 182675 transitions. Second operand 6 states. [2019-12-07 18:52:40,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:40,140 INFO L93 Difference]: Finished difference Result 14836 states and 46527 transitions. [2019-12-07 18:52:40,140 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:52:40,140 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 42 [2019-12-07 18:52:40,141 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:40,158 INFO L225 Difference]: With dead ends: 14836 [2019-12-07 18:52:40,158 INFO L226 Difference]: Without dead ends: 13706 [2019-12-07 18:52:40,158 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:52:40,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13706 states. [2019-12-07 18:52:40,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13706 to 13482. [2019-12-07 18:52:40,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13482 states. [2019-12-07 18:52:40,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13482 states to 13482 states and 42469 transitions. [2019-12-07 18:52:40,360 INFO L78 Accepts]: Start accepts. Automaton has 13482 states and 42469 transitions. Word has length 42 [2019-12-07 18:52:40,360 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:40,360 INFO L462 AbstractCegarLoop]: Abstraction has 13482 states and 42469 transitions. [2019-12-07 18:52:40,360 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:52:40,360 INFO L276 IsEmpty]: Start isEmpty. Operand 13482 states and 42469 transitions. [2019-12-07 18:52:40,372 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-12-07 18:52:40,372 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:40,372 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:40,372 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:40,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:40,373 INFO L82 PathProgramCache]: Analyzing trace with hash -878689176, now seen corresponding path program 1 times [2019-12-07 18:52:40,373 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:40,373 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1215317483] [2019-12-07 18:52:40,373 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:40,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:40,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:40,439 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1215317483] [2019-12-07 18:52:40,439 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:40,439 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:52:40,439 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [35645599] [2019-12-07 18:52:40,440 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:52:40,440 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:40,440 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:52:40,440 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:52:40,440 INFO L87 Difference]: Start difference. First operand 13482 states and 42469 transitions. Second operand 7 states. [2019-12-07 18:52:40,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:40,529 INFO L93 Difference]: Finished difference Result 10693 states and 35943 transitions. [2019-12-07 18:52:40,529 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:52:40,529 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 54 [2019-12-07 18:52:40,529 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:40,543 INFO L225 Difference]: With dead ends: 10693 [2019-12-07 18:52:40,543 INFO L226 Difference]: Without dead ends: 10610 [2019-12-07 18:52:40,543 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:52:40,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10610 states. [2019-12-07 18:52:40,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10610 to 9882. [2019-12-07 18:52:40,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9882 states. [2019-12-07 18:52:40,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9882 states to 9882 states and 33446 transitions. [2019-12-07 18:52:40,711 INFO L78 Accepts]: Start accepts. Automaton has 9882 states and 33446 transitions. Word has length 54 [2019-12-07 18:52:40,711 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:40,712 INFO L462 AbstractCegarLoop]: Abstraction has 9882 states and 33446 transitions. [2019-12-07 18:52:40,712 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:52:40,712 INFO L276 IsEmpty]: Start isEmpty. Operand 9882 states and 33446 transitions. [2019-12-07 18:52:40,722 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:52:40,722 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:40,722 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:40,722 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:40,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:40,722 INFO L82 PathProgramCache]: Analyzing trace with hash 1525014862, now seen corresponding path program 1 times [2019-12-07 18:52:40,722 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:40,722 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1532691622] [2019-12-07 18:52:40,722 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:40,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:40,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:40,792 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1532691622] [2019-12-07 18:52:40,792 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:40,792 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:52:40,792 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [407722360] [2019-12-07 18:52:40,793 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:52:40,793 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:40,793 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:52:40,793 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:52:40,793 INFO L87 Difference]: Start difference. First operand 9882 states and 33446 transitions. Second operand 5 states. [2019-12-07 18:52:41,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:41,014 INFO L93 Difference]: Finished difference Result 15023 states and 50470 transitions. [2019-12-07 18:52:41,014 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:52:41,014 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 68 [2019-12-07 18:52:41,014 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:41,034 INFO L225 Difference]: With dead ends: 15023 [2019-12-07 18:52:41,034 INFO L226 Difference]: Without dead ends: 15023 [2019-12-07 18:52:41,034 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:52:41,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15023 states. [2019-12-07 18:52:41,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15023 to 13229. [2019-12-07 18:52:41,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13229 states. [2019-12-07 18:52:41,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13229 states to 13229 states and 44621 transitions. [2019-12-07 18:52:41,266 INFO L78 Accepts]: Start accepts. Automaton has 13229 states and 44621 transitions. Word has length 68 [2019-12-07 18:52:41,266 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:41,266 INFO L462 AbstractCegarLoop]: Abstraction has 13229 states and 44621 transitions. [2019-12-07 18:52:41,266 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:52:41,266 INFO L276 IsEmpty]: Start isEmpty. Operand 13229 states and 44621 transitions. [2019-12-07 18:52:41,280 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:52:41,281 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:41,281 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:41,281 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:41,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:41,281 INFO L82 PathProgramCache]: Analyzing trace with hash 938890640, now seen corresponding path program 2 times [2019-12-07 18:52:41,281 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:41,281 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081843034] [2019-12-07 18:52:41,281 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:41,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:41,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:41,341 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2081843034] [2019-12-07 18:52:41,341 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:41,341 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:52:41,341 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1565729855] [2019-12-07 18:52:41,341 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:52:41,341 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:41,341 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:52:41,341 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:41,341 INFO L87 Difference]: Start difference. First operand 13229 states and 44621 transitions. Second operand 3 states. [2019-12-07 18:52:41,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:41,385 INFO L93 Difference]: Finished difference Result 12489 states and 41569 transitions. [2019-12-07 18:52:41,385 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:52:41,385 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 68 [2019-12-07 18:52:41,385 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:41,402 INFO L225 Difference]: With dead ends: 12489 [2019-12-07 18:52:41,402 INFO L226 Difference]: Without dead ends: 12489 [2019-12-07 18:52:41,403 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:41,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12489 states. [2019-12-07 18:52:41,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12489 to 12177. [2019-12-07 18:52:41,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12177 states. [2019-12-07 18:52:41,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12177 states to 12177 states and 40553 transitions. [2019-12-07 18:52:41,842 INFO L78 Accepts]: Start accepts. Automaton has 12177 states and 40553 transitions. Word has length 68 [2019-12-07 18:52:41,842 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:41,843 INFO L462 AbstractCegarLoop]: Abstraction has 12177 states and 40553 transitions. [2019-12-07 18:52:41,843 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:52:41,843 INFO L276 IsEmpty]: Start isEmpty. Operand 12177 states and 40553 transitions. [2019-12-07 18:52:41,854 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-12-07 18:52:41,854 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:41,854 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:41,855 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:41,855 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:41,855 INFO L82 PathProgramCache]: Analyzing trace with hash 1809822351, now seen corresponding path program 1 times [2019-12-07 18:52:41,855 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:41,855 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1063243411] [2019-12-07 18:52:41,855 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:41,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:41,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:41,917 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1063243411] [2019-12-07 18:52:41,917 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:41,917 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:52:41,917 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1376131907] [2019-12-07 18:52:41,918 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:52:41,918 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:41,918 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:52:41,918 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:41,918 INFO L87 Difference]: Start difference. First operand 12177 states and 40553 transitions. Second operand 3 states. [2019-12-07 18:52:41,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:41,971 INFO L93 Difference]: Finished difference Result 11575 states and 38096 transitions. [2019-12-07 18:52:41,971 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:52:41,971 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 69 [2019-12-07 18:52:41,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:41,986 INFO L225 Difference]: With dead ends: 11575 [2019-12-07 18:52:41,986 INFO L226 Difference]: Without dead ends: 11575 [2019-12-07 18:52:41,986 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:42,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11575 states. [2019-12-07 18:52:42,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11575 to 10903. [2019-12-07 18:52:42,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10903 states. [2019-12-07 18:52:42,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10903 states to 10903 states and 35904 transitions. [2019-12-07 18:52:42,156 INFO L78 Accepts]: Start accepts. Automaton has 10903 states and 35904 transitions. Word has length 69 [2019-12-07 18:52:42,156 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:42,156 INFO L462 AbstractCegarLoop]: Abstraction has 10903 states and 35904 transitions. [2019-12-07 18:52:42,156 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:52:42,156 INFO L276 IsEmpty]: Start isEmpty. Operand 10903 states and 35904 transitions. [2019-12-07 18:52:42,166 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 18:52:42,166 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:42,166 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:42,166 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:42,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:42,166 INFO L82 PathProgramCache]: Analyzing trace with hash -396393043, now seen corresponding path program 1 times [2019-12-07 18:52:42,167 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:42,167 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2063696424] [2019-12-07 18:52:42,167 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:42,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:42,239 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:42,239 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2063696424] [2019-12-07 18:52:42,239 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:42,239 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 18:52:42,240 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [933665598] [2019-12-07 18:52:42,240 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:52:42,240 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:42,240 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:52:42,240 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:52:42,240 INFO L87 Difference]: Start difference. First operand 10903 states and 35904 transitions. Second operand 7 states. [2019-12-07 18:52:42,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:42,796 INFO L93 Difference]: Finished difference Result 15648 states and 51226 transitions. [2019-12-07 18:52:42,796 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 18:52:42,796 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 70 [2019-12-07 18:52:42,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:42,815 INFO L225 Difference]: With dead ends: 15648 [2019-12-07 18:52:42,816 INFO L226 Difference]: Without dead ends: 15648 [2019-12-07 18:52:42,816 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 20 SyntacticMatches, 3 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 101 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=110, Invalid=396, Unknown=0, NotChecked=0, Total=506 [2019-12-07 18:52:42,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15648 states. [2019-12-07 18:52:43,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15648 to 13145. [2019-12-07 18:52:43,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13145 states. [2019-12-07 18:52:43,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13145 states to 13145 states and 43199 transitions. [2019-12-07 18:52:43,044 INFO L78 Accepts]: Start accepts. Automaton has 13145 states and 43199 transitions. Word has length 70 [2019-12-07 18:52:43,044 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:43,044 INFO L462 AbstractCegarLoop]: Abstraction has 13145 states and 43199 transitions. [2019-12-07 18:52:43,044 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:52:43,045 INFO L276 IsEmpty]: Start isEmpty. Operand 13145 states and 43199 transitions. [2019-12-07 18:52:43,059 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 18:52:43,059 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:43,059 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:43,059 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:43,059 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:43,059 INFO L82 PathProgramCache]: Analyzing trace with hash -18539293, now seen corresponding path program 2 times [2019-12-07 18:52:43,059 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:43,059 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1409878246] [2019-12-07 18:52:43,060 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:43,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:43,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:43,100 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1409878246] [2019-12-07 18:52:43,100 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:43,100 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:52:43,100 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [93418206] [2019-12-07 18:52:43,101 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:52:43,101 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:43,101 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:52:43,101 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:43,101 INFO L87 Difference]: Start difference. First operand 13145 states and 43199 transitions. Second operand 3 states. [2019-12-07 18:52:43,165 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:43,166 INFO L93 Difference]: Finished difference Result 13144 states and 43197 transitions. [2019-12-07 18:52:43,166 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:52:43,166 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2019-12-07 18:52:43,166 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:43,184 INFO L225 Difference]: With dead ends: 13144 [2019-12-07 18:52:43,184 INFO L226 Difference]: Without dead ends: 13144 [2019-12-07 18:52:43,185 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:43,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13144 states. [2019-12-07 18:52:43,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13144 to 8801. [2019-12-07 18:52:43,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8801 states. [2019-12-07 18:52:43,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8801 states to 8801 states and 29020 transitions. [2019-12-07 18:52:43,354 INFO L78 Accepts]: Start accepts. Automaton has 8801 states and 29020 transitions. Word has length 70 [2019-12-07 18:52:43,354 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:43,354 INFO L462 AbstractCegarLoop]: Abstraction has 8801 states and 29020 transitions. [2019-12-07 18:52:43,354 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:52:43,355 INFO L276 IsEmpty]: Start isEmpty. Operand 8801 states and 29020 transitions. [2019-12-07 18:52:43,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-12-07 18:52:43,363 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:43,363 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:43,363 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:43,363 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:43,363 INFO L82 PathProgramCache]: Analyzing trace with hash 335729332, now seen corresponding path program 1 times [2019-12-07 18:52:43,363 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:43,364 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1827122833] [2019-12-07 18:52:43,364 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:43,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:43,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:43,553 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1827122833] [2019-12-07 18:52:43,553 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:43,553 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 18:52:43,553 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [76646733] [2019-12-07 18:52:43,553 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 18:52:43,553 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:43,553 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 18:52:43,553 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=122, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:52:43,554 INFO L87 Difference]: Start difference. First operand 8801 states and 29020 transitions. Second operand 13 states. [2019-12-07 18:52:44,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:44,607 INFO L93 Difference]: Finished difference Result 30058 states and 89974 transitions. [2019-12-07 18:52:44,608 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 18:52:44,608 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 71 [2019-12-07 18:52:44,608 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:44,628 INFO L225 Difference]: With dead ends: 30058 [2019-12-07 18:52:44,628 INFO L226 Difference]: Without dead ends: 19158 [2019-12-07 18:52:44,628 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 156 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=239, Invalid=753, Unknown=0, NotChecked=0, Total=992 [2019-12-07 18:52:44,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19158 states. [2019-12-07 18:52:44,819 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19158 to 7978. [2019-12-07 18:52:44,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7978 states. [2019-12-07 18:52:44,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7978 states to 7978 states and 25856 transitions. [2019-12-07 18:52:44,834 INFO L78 Accepts]: Start accepts. Automaton has 7978 states and 25856 transitions. Word has length 71 [2019-12-07 18:52:44,834 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:44,834 INFO L462 AbstractCegarLoop]: Abstraction has 7978 states and 25856 transitions. [2019-12-07 18:52:44,834 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 18:52:44,834 INFO L276 IsEmpty]: Start isEmpty. Operand 7978 states and 25856 transitions. [2019-12-07 18:52:44,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-12-07 18:52:44,841 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:44,841 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:44,842 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:44,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:44,842 INFO L82 PathProgramCache]: Analyzing trace with hash 734943428, now seen corresponding path program 2 times [2019-12-07 18:52:44,842 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:44,842 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [401519011] [2019-12-07 18:52:44,842 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:44,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:45,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:45,005 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [401519011] [2019-12-07 18:52:45,006 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:45,006 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 18:52:45,006 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [383903433] [2019-12-07 18:52:45,006 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 18:52:45,006 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:45,006 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 18:52:45,006 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=105, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:52:45,007 INFO L87 Difference]: Start difference. First operand 7978 states and 25856 transitions. Second operand 12 states. [2019-12-07 18:52:45,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:45,256 INFO L93 Difference]: Finished difference Result 14316 states and 46402 transitions. [2019-12-07 18:52:45,257 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 18:52:45,257 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 71 [2019-12-07 18:52:45,257 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:45,273 INFO L225 Difference]: With dead ends: 14316 [2019-12-07 18:52:45,273 INFO L226 Difference]: Without dead ends: 13006 [2019-12-07 18:52:45,274 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=93, Invalid=369, Unknown=0, NotChecked=0, Total=462 [2019-12-07 18:52:45,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13006 states. [2019-12-07 18:52:45,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13006 to 10560. [2019-12-07 18:52:45,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10560 states. [2019-12-07 18:52:45,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10560 states to 10560 states and 34147 transitions. [2019-12-07 18:52:45,460 INFO L78 Accepts]: Start accepts. Automaton has 10560 states and 34147 transitions. Word has length 71 [2019-12-07 18:52:45,460 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:45,460 INFO L462 AbstractCegarLoop]: Abstraction has 10560 states and 34147 transitions. [2019-12-07 18:52:45,460 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 18:52:45,461 INFO L276 IsEmpty]: Start isEmpty. Operand 10560 states and 34147 transitions. [2019-12-07 18:52:45,471 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-12-07 18:52:45,471 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:45,471 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:45,471 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:45,471 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:45,472 INFO L82 PathProgramCache]: Analyzing trace with hash 1013832808, now seen corresponding path program 3 times [2019-12-07 18:52:45,472 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:45,472 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1731482218] [2019-12-07 18:52:45,472 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:45,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:52:45,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:52:45,556 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:52:45,556 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 18:52:45,559 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [862] [862] ULTIMATE.startENTRY-->L831: Formula: (let ((.cse0 (store |v_#valid_76| 0 0))) (and (= 0 v_~y$read_delayed_var~0.offset_7) (= 0 v_~weak$$choice0~0_14) (= 0 v_~y$r_buff1_thd2~0_173) (= |v_#NULL.offset_6| 0) (= |v_#length_29| (store |v_#length_30| |v_ULTIMATE.start_main_~#t805~0.base_24| 4)) (= 0 v_~__unbuffered_cnt~0_81) (= v_~y$r_buff0_thd1~0_40 0) (= v_~y$w_buff1~0_309 0) (< |v_#StackHeapBarrier_20| |v_ULTIMATE.start_main_~#t805~0.base_24|) (= 0 v_~y$r_buff0_thd3~0_201) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t805~0.base_24|)) (= v_~y$read_delayed~0_6 0) (= v_~y~0_210 0) (= 0 v_~__unbuffered_p3_EAX~0_26) (= |v_ULTIMATE.start_main_~#t805~0.offset_19| 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t805~0.base_24| 1) |v_#valid_74|) (= v_~y$r_buff0_thd0~0_436 0) (= v_~y$r_buff1_thd0~0_339 0) (= 0 v_~__unbuffered_p3_EBX~0_26) (= 0 |v_#NULL.base_6|) (= (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t805~0.base_24| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t805~0.base_24|) |v_ULTIMATE.start_main_~#t805~0.offset_19| 0)) |v_#memory_int_27|) (= v_~x~0_31 0) (= 0 v_~y$read_delayed_var~0.base_7) (= v_~y$mem_tmp~0_17 0) (= 0 v_~y$r_buff0_thd4~0_118) (< 0 |v_#StackHeapBarrier_20|) (= v_~y$w_buff0_used~0_961 0) (= v_~z~0_132 0) (= v_~a~0_21 0) (= v_~main$tmp_guard1~0_24 0) (= 0 v_~y$flush_delayed~0_38) (= 0 v_~y$r_buff1_thd3~0_154) (= v_~main$tmp_guard0~0_48 0) (= v_~weak$$choice2~0_131 0) (= 0 v_~y$r_buff1_thd4~0_167) (= 0 v_~y$w_buff0~0_462) (= v_~y$r_buff1_thd1~0_115 0) (= v_~y$w_buff1_used~0_595 0) (= 0 v_~y$r_buff0_thd2~0_133))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_20|, #valid=|v_#valid_76|, #memory_int=|v_#memory_int_28|, #length=|v_#length_30|} OutVars{ULTIMATE.start_main_#t~nondet32=|v_ULTIMATE.start_main_#t~nondet32_21|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_141|, ULTIMATE.start_main_~#t806~0.base=|v_ULTIMATE.start_main_~#t806~0.base_24|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_29|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_36|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_17|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_23|, ULTIMATE.start_main_~#t805~0.offset=|v_ULTIMATE.start_main_~#t805~0.offset_19|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_50|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_44|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~a~0=v_~a~0_21, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_36|, ~y$mem_tmp~0=v_~y$mem_tmp~0_17, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_154, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_40, ~y$flush_delayed~0=v_~y$flush_delayed~0_38, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_26, #length=|v_#length_29|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_62|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_30|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_46|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_39|, ULTIMATE.start_main_~#t807~0.base=|v_ULTIMATE.start_main_~#t807~0.base_19|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_31|, ULTIMATE.start_main_~#t807~0.offset=|v_ULTIMATE.start_main_~#t807~0.offset_16|, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_20|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_49|, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_167, ~y$w_buff1~0=v_~y$w_buff1~0_309, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_133, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_81, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_339, ~x~0=v_~x~0_31, ULTIMATE.start_main_~#t808~0.offset=|v_ULTIMATE.start_main_~#t808~0.offset_17|, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_961, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_35|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_39|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_24, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_27|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_35|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_36|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_42|, ULTIMATE.start_main_~#t805~0.base=|v_ULTIMATE.start_main_~#t805~0.base_24|, ULTIMATE.start_main_~#t808~0.base=|v_ULTIMATE.start_main_~#t808~0.base_21|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_115, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_37|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_48|, ~y$w_buff0~0=v_~y$w_buff0~0_462, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_201, ULTIMATE.start_main_~#t806~0.offset=|v_ULTIMATE.start_main_~#t806~0.offset_18|, ~y~0=v_~y~0_210, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_9|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_10|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_48|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_54|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_48, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_26, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_44|, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_73|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_173, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_118, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_34|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_436, #valid=|v_#valid_74|, #memory_int=|v_#memory_int_27|, ~z~0=v_~z~0_132, ~weak$$choice2~0=v_~weak$$choice2~0_131, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_595} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet32, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t806~0.base, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_~#t805~0.offset, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ~y$read_delayed~0, ~a~0, ULTIMATE.start_main_#t~ite52, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ~__unbuffered_p3_EAX~0, #length, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_~#t807~0.base, ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_~#t807~0.offset, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$r_buff1_thd4~0, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_~#t808~0.offset, ULTIMATE.start_main_#t~nondet31, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t805~0.base, ULTIMATE.start_main_~#t808~0.base, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite51, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ULTIMATE.start_main_~#t806~0.offset, ~y~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~__unbuffered_p3_EBX~0, ULTIMATE.start_main_#t~ite53, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ~y$r_buff0_thd4~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 18:52:45,559 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L831-1-->L833: Formula: (and (= |v_#valid_45| (store |v_#valid_46| |v_ULTIMATE.start_main_~#t806~0.base_12| 1)) (not (= |v_ULTIMATE.start_main_~#t806~0.base_12| 0)) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t806~0.base_12| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t806~0.base_12|) |v_ULTIMATE.start_main_~#t806~0.offset_10| 1)) |v_#memory_int_19|) (= |v_ULTIMATE.start_main_~#t806~0.offset_10| 0) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t806~0.base_12| 4)) (= (select |v_#valid_46| |v_ULTIMATE.start_main_~#t806~0.base_12|) 0) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t806~0.base_12|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_20|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_5|, ULTIMATE.start_main_~#t806~0.base=|v_ULTIMATE.start_main_~#t806~0.base_12|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_19|, #length=|v_#length_21|, ULTIMATE.start_main_~#t806~0.offset=|v_ULTIMATE.start_main_~#t806~0.offset_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t806~0.base, #valid, #memory_int, #length, ULTIMATE.start_main_~#t806~0.offset] because there is no mapped edge [2019-12-07 18:52:45,560 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [819] [819] L833-1-->L835: Formula: (and (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t807~0.base_10| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t807~0.base_10|) |v_ULTIMATE.start_main_~#t807~0.offset_9| 2)) |v_#memory_int_15|) (= 0 |v_ULTIMATE.start_main_~#t807~0.offset_9|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t807~0.base_10| 4)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t807~0.base_10|) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t807~0.base_10|)) (= |v_#valid_35| (store |v_#valid_36| |v_ULTIMATE.start_main_~#t807~0.base_10| 1)) (not (= 0 |v_ULTIMATE.start_main_~#t807~0.base_10|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_4|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_15|, #length=|v_#length_17|, ULTIMATE.start_main_~#t807~0.base=|v_ULTIMATE.start_main_~#t807~0.base_10|, ULTIMATE.start_main_~#t807~0.offset=|v_ULTIMATE.start_main_~#t807~0.offset_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t807~0.base, ULTIMATE.start_main_~#t807~0.offset] because there is no mapped edge [2019-12-07 18:52:45,560 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [739] [739] L4-->L785: Formula: (and (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10)) (= v_~y$r_buff0_thd2~0_30 v_~y$r_buff1_thd2~0_21) (= 1 v_~z~0_9) (= v_~y$r_buff1_thd1~0_6 v_~y$r_buff0_thd1~0_6) (= v_~y$r_buff0_thd3~0_27 1) (= v_~y$r_buff0_thd4~0_17 v_~y$r_buff1_thd4~0_14) (= v_~y$r_buff0_thd0~0_88 v_~y$r_buff1_thd0~0_47) (= v_~y$r_buff0_thd3~0_28 v_~y$r_buff1_thd3~0_19)) InVars {~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_17, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_28, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_88, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_30, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_6, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_21, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_17, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_6, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_14, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_19, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_27, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_88, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_30, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_6, ~z~0=v_~z~0_9, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_47, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, ~y$r_buff1_thd1~0, ~y$r_buff1_thd4~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd3~0, ~z~0, ~y$r_buff1_thd0~0] because there is no mapped edge [2019-12-07 18:52:45,561 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [824] [824] L835-1-->L837: Formula: (and (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t808~0.base_10| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t808~0.base_10|) |v_ULTIMATE.start_main_~#t808~0.offset_9| 3)) |v_#memory_int_17|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t808~0.base_10|) (= (store |v_#valid_38| |v_ULTIMATE.start_main_~#t808~0.base_10| 1) |v_#valid_37|) (not (= |v_ULTIMATE.start_main_~#t808~0.base_10| 0)) (= (store |v_#length_20| |v_ULTIMATE.start_main_~#t808~0.base_10| 4) |v_#length_19|) (= 0 |v_ULTIMATE.start_main_~#t808~0.offset_9|) (= 0 (select |v_#valid_38| |v_ULTIMATE.start_main_~#t808~0.base_10|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_18|, #length=|v_#length_20|} OutVars{ULTIMATE.start_main_~#t808~0.base=|v_ULTIMATE.start_main_~#t808~0.base_10|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, #valid=|v_#valid_37|, #memory_int=|v_#memory_int_17|, #length=|v_#length_19|, ULTIMATE.start_main_~#t808~0.offset=|v_ULTIMATE.start_main_~#t808~0.offset_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t808~0.base, ULTIMATE.start_main_#t~nondet23, #valid, #memory_int, #length, ULTIMATE.start_main_~#t808~0.offset] because there is no mapped edge [2019-12-07 18:52:45,562 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L786-->L786-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-708390329 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In-708390329 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P2Thread1of1ForFork0_#t~ite11_Out-708390329|)) (and (or .cse1 .cse0) (= ~y$w_buff0_used~0_In-708390329 |P2Thread1of1ForFork0_#t~ite11_Out-708390329|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-708390329, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-708390329} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-708390329, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-708390329|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-708390329} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 18:52:45,562 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [811] [811] L787-->L787-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-698535395 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd3~0_In-698535395 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd3~0_In-698535395 256))) (.cse2 (= (mod ~y$w_buff1_used~0_In-698535395 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite12_Out-698535395| ~y$w_buff1_used~0_In-698535395) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P2Thread1of1ForFork0_#t~ite12_Out-698535395| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-698535395, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-698535395, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-698535395, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-698535395} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-698535395, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-698535395, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-698535395|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-698535395, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-698535395} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 18:52:45,562 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [814] [814] L788-->L789: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-336767602 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd3~0_In-336767602 256) 0)) (.cse2 (= ~y$r_buff0_thd3~0_In-336767602 ~y$r_buff0_thd3~0_Out-336767602))) (or (and (= 0 ~y$r_buff0_thd3~0_Out-336767602) (not .cse0) (not .cse1)) (and .cse0 .cse2) (and .cse1 .cse2))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-336767602, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-336767602} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-336767602, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-336767602, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-336767602|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 18:52:45,562 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L789-->L789-2: Formula: (let ((.cse2 (= (mod ~y$r_buff1_thd3~0_In-1981019750 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In-1981019750 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1981019750 256))) (.cse1 (= (mod ~y$r_buff0_thd3~0_In-1981019750 256) 0))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd3~0_In-1981019750 |P2Thread1of1ForFork0_#t~ite14_Out-1981019750|) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite14_Out-1981019750|) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1981019750, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1981019750, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1981019750, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1981019750} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out-1981019750|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1981019750, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1981019750, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1981019750, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1981019750} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 18:52:45,562 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L789-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_18| v_~y$r_buff1_thd3~0_49) (= (+ v_~__unbuffered_cnt~0_45 1) v_~__unbuffered_cnt~0_44) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_18|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_45} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_17|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_49, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_44, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 18:52:45,563 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [834] [834] P0ENTRY-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork2_#res.offset_5| 0) (= v_~__unbuffered_cnt~0_50 (+ v_~__unbuffered_cnt~0_51 1)) (= v_P0Thread1of1ForFork2_~arg.offset_9 |v_P0Thread1of1ForFork2_#in~arg.offset_11|) (= 0 |v_P0Thread1of1ForFork2_#res.base_5|) (= v_~a~0_14 1) (= v_~x~0_21 1) (= v_P0Thread1of1ForFork2_~arg.base_9 |v_P0Thread1of1ForFork2_#in~arg.base_11|)) InVars {P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_11|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_51, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_11|} OutVars{~a~0=v_~a~0_14, P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_11|, P0Thread1of1ForFork2_~arg.offset=v_P0Thread1of1ForFork2_~arg.offset_9, P0Thread1of1ForFork2_#res.offset=|v_P0Thread1of1ForFork2_#res.offset_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_50, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_11|, P0Thread1of1ForFork2_#res.base=|v_P0Thread1of1ForFork2_#res.base_5|, ~x~0=v_~x~0_21, P0Thread1of1ForFork2_~arg.base=v_P0Thread1of1ForFork2_~arg.base_9} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork2_~arg.offset, P0Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0, P0Thread1of1ForFork2_#res.base, ~x~0, P0Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-12-07 18:52:45,563 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [807] [807] L808-2-->L808-4: Formula: (let ((.cse1 (= (mod ~y$r_buff1_thd4~0_In451998044 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In451998044 256) 0))) (or (and (not .cse0) (not .cse1) (= ~y$w_buff1~0_In451998044 |P3Thread1of1ForFork1_#t~ite15_Out451998044|)) (and (= ~y~0_In451998044 |P3Thread1of1ForFork1_#t~ite15_Out451998044|) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In451998044, ~y$w_buff1~0=~y$w_buff1~0_In451998044, ~y~0=~y~0_In451998044, ~y$w_buff1_used~0=~y$w_buff1_used~0_In451998044} OutVars{~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In451998044, ~y$w_buff1~0=~y$w_buff1~0_In451998044, P3Thread1of1ForFork1_#t~ite15=|P3Thread1of1ForFork1_#t~ite15_Out451998044|, ~y~0=~y~0_In451998044, ~y$w_buff1_used~0=~y$w_buff1_used~0_In451998044} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite15] because there is no mapped edge [2019-12-07 18:52:45,564 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [753] [753] L808-4-->L809: Formula: (= v_~y~0_56 |v_P3Thread1of1ForFork1_#t~ite15_8|) InVars {P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_8|} OutVars{P3Thread1of1ForFork1_#t~ite16=|v_P3Thread1of1ForFork1_#t~ite16_11|, P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_7|, ~y~0=v_~y~0_56} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite16, P3Thread1of1ForFork1_#t~ite15, ~y~0] because there is no mapped edge [2019-12-07 18:52:45,564 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [809] [809] L809-->L809-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In1538343199 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd4~0_In1538343199 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P3Thread1of1ForFork1_#t~ite17_Out1538343199|)) (and (= ~y$w_buff0_used~0_In1538343199 |P3Thread1of1ForFork1_#t~ite17_Out1538343199|) (or .cse1 .cse0)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1538343199, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1538343199} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1538343199, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1538343199, P3Thread1of1ForFork1_#t~ite17=|P3Thread1of1ForFork1_#t~ite17_Out1538343199|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite17] because there is no mapped edge [2019-12-07 18:52:45,564 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L810-->L810-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In582088541 256))) (.cse3 (= (mod ~y$r_buff1_thd4~0_In582088541 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In582088541 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd4~0_In582088541 256)))) (or (and (or .cse0 .cse1) (= |P3Thread1of1ForFork1_#t~ite18_Out582088541| ~y$w_buff1_used~0_In582088541) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1))) (= |P3Thread1of1ForFork1_#t~ite18_Out582088541| 0)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In582088541, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In582088541, ~y$w_buff0_used~0=~y$w_buff0_used~0_In582088541, ~y$w_buff1_used~0=~y$w_buff1_used~0_In582088541} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In582088541, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In582088541, P3Thread1of1ForFork1_#t~ite18=|P3Thread1of1ForFork1_#t~ite18_Out582088541|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In582088541, ~y$w_buff1_used~0=~y$w_buff1_used~0_In582088541} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite18] because there is no mapped edge [2019-12-07 18:52:45,565 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [792] [792] L811-->L811-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-516425222 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd4~0_In-516425222 256)))) (or (and (not .cse0) (not .cse1) (= |P3Thread1of1ForFork1_#t~ite19_Out-516425222| 0)) (and (= |P3Thread1of1ForFork1_#t~ite19_Out-516425222| ~y$r_buff0_thd4~0_In-516425222) (or .cse0 .cse1)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-516425222, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-516425222} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-516425222, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-516425222, P3Thread1of1ForFork1_#t~ite19=|P3Thread1of1ForFork1_#t~ite19_Out-516425222|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite19] because there is no mapped edge [2019-12-07 18:52:45,565 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L812-->L812-2: Formula: (let ((.cse0 (= (mod ~y$r_buff1_thd4~0_In181965624 256) 0)) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In181965624 256))) (.cse3 (= 0 (mod ~y$r_buff0_thd4~0_In181965624 256))) (.cse2 (= (mod ~y$w_buff0_used~0_In181965624 256) 0))) (or (and (= ~y$r_buff1_thd4~0_In181965624 |P3Thread1of1ForFork1_#t~ite20_Out181965624|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2))) (= |P3Thread1of1ForFork1_#t~ite20_Out181965624| 0)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In181965624, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In181965624, ~y$w_buff0_used~0=~y$w_buff0_used~0_In181965624, ~y$w_buff1_used~0=~y$w_buff1_used~0_In181965624} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In181965624, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In181965624, ~y$w_buff0_used~0=~y$w_buff0_used~0_In181965624, P3Thread1of1ForFork1_#t~ite20=|P3Thread1of1ForFork1_#t~ite20_Out181965624|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In181965624} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 18:52:45,565 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [835] [835] L812-2-->P3EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_57 1) v_~__unbuffered_cnt~0_56) (= |v_P3Thread1of1ForFork1_#t~ite20_18| v_~y$r_buff1_thd4~0_61) (= |v_P3Thread1of1ForFork1_#res.offset_3| 0) (= |v_P3Thread1of1ForFork1_#res.base_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_57, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_18|} OutVars{~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_61, P3Thread1of1ForFork1_#res.base=|v_P3Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56, P3Thread1of1ForFork1_#res.offset=|v_P3Thread1of1ForFork1_#res.offset_3|, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_17|} AuxVars[] AssignedVars[~y$r_buff1_thd4~0, P3Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork1_#res.offset, P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 18:52:45,565 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L755-2-->L755-4: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In-186759071 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-186759071 256) 0))) (or (and (= ~y$w_buff1~0_In-186759071 |P1Thread1of1ForFork3_#t~ite3_Out-186759071|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |P1Thread1of1ForFork3_#t~ite3_Out-186759071| ~y~0_In-186759071)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-186759071, ~y$w_buff1~0=~y$w_buff1~0_In-186759071, ~y~0=~y~0_In-186759071, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-186759071} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-186759071, ~y$w_buff1~0=~y$w_buff1~0_In-186759071, P1Thread1of1ForFork3_#t~ite3=|P1Thread1of1ForFork3_#t~ite3_Out-186759071|, ~y~0=~y~0_In-186759071, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-186759071} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite3] because there is no mapped edge [2019-12-07 18:52:45,565 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L755-4-->L756: Formula: (= |v_P1Thread1of1ForFork3_#t~ite3_24| v_~y~0_66) InVars {P1Thread1of1ForFork3_#t~ite3=|v_P1Thread1of1ForFork3_#t~ite3_24|} OutVars{P1Thread1of1ForFork3_#t~ite4=|v_P1Thread1of1ForFork3_#t~ite4_33|, P1Thread1of1ForFork3_#t~ite3=|v_P1Thread1of1ForFork3_#t~ite3_23|, ~y~0=v_~y~0_66} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite4, P1Thread1of1ForFork3_#t~ite3, ~y~0] because there is no mapped edge [2019-12-07 18:52:45,566 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L756-->L756-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd2~0_In411439057 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In411439057 256)))) (or (and (= 0 |P1Thread1of1ForFork3_#t~ite5_Out411439057|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~y$w_buff0_used~0_In411439057 |P1Thread1of1ForFork3_#t~ite5_Out411439057|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In411439057, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In411439057} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In411439057, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In411439057, P1Thread1of1ForFork3_#t~ite5=|P1Thread1of1ForFork3_#t~ite5_Out411439057|} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite5] because there is no mapped edge [2019-12-07 18:52:45,566 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [817] [817] L757-->L757-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In1726943671 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In1726943671 256))) (.cse3 (= (mod ~y$r_buff0_thd2~0_In1726943671 256) 0)) (.cse2 (= (mod ~y$w_buff0_used~0_In1726943671 256) 0))) (or (and (= |P1Thread1of1ForFork3_#t~ite6_Out1726943671| ~y$w_buff1_used~0_In1726943671) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P1Thread1of1ForFork3_#t~ite6_Out1726943671| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1726943671, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1726943671, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1726943671, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1726943671} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1726943671, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1726943671, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1726943671, P1Thread1of1ForFork3_#t~ite6=|P1Thread1of1ForFork3_#t~ite6_Out1726943671|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1726943671} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite6] because there is no mapped edge [2019-12-07 18:52:45,566 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L758-->L758-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In838614178 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd2~0_In838614178 256) 0))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork3_#t~ite7_Out838614178| ~y$r_buff0_thd2~0_In838614178)) (and (= |P1Thread1of1ForFork3_#t~ite7_Out838614178| 0) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In838614178, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In838614178} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In838614178, P1Thread1of1ForFork3_#t~ite7=|P1Thread1of1ForFork3_#t~ite7_Out838614178|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In838614178} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite7] because there is no mapped edge [2019-12-07 18:52:45,567 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L759-->L759-2: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In1324008106 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd2~0_In1324008106 256) 0)) (.cse3 (= (mod ~y$w_buff0_used~0_In1324008106 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd2~0_In1324008106 256) 0))) (or (and (= |P1Thread1of1ForFork3_#t~ite8_Out1324008106| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (= ~y$r_buff1_thd2~0_In1324008106 |P1Thread1of1ForFork3_#t~ite8_Out1324008106|) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1324008106, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1324008106, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1324008106, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1324008106} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1324008106, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1324008106, P1Thread1of1ForFork3_#t~ite8=|P1Thread1of1ForFork3_#t~ite8_Out1324008106|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1324008106, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1324008106} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite8] because there is no mapped edge [2019-12-07 18:52:45,567 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [820] [820] L759-2-->P1EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_39 1) v_~__unbuffered_cnt~0_38) (= 0 |v_P1Thread1of1ForFork3_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork3_#res.base_3|) (= |v_P1Thread1of1ForFork3_#t~ite8_18| v_~y$r_buff1_thd2~0_43)) InVars {P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_18|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_39} OutVars{P1Thread1of1ForFork3_#res.base=|v_P1Thread1of1ForFork3_#res.base_3|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_43, P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_17|, P1Thread1of1ForFork3_#res.offset=|v_P1Thread1of1ForFork3_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#res.base, ~y$r_buff1_thd2~0, P1Thread1of1ForFork3_#t~ite8, P1Thread1of1ForFork3_#res.offset, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 18:52:45,567 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [737] [737] L841-->L843-2: Formula: (and (or (= 0 (mod v_~y$w_buff0_used~0_154 256)) (= 0 (mod v_~y$r_buff0_thd0~0_84 256))) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~y$w_buff0_used~0=v_~y$w_buff0_used~0_154, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_84, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} OutVars{~y$w_buff0_used~0=v_~y$w_buff0_used~0_154, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_84, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 18:52:45,567 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L843-2-->L843-4: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In-1124982874 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-1124982874 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite25_Out-1124982874| ~y$w_buff1~0_In-1124982874) (not .cse1)) (and (or .cse1 .cse0) (= ~y~0_In-1124982874 |ULTIMATE.start_main_#t~ite25_Out-1124982874|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1124982874, ~y~0=~y~0_In-1124982874, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1124982874, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1124982874} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1124982874, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-1124982874|, ~y~0=~y~0_In-1124982874, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1124982874, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1124982874} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 18:52:45,567 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [725] [725] L843-4-->L844: Formula: (= v_~y~0_29 |v_ULTIMATE.start_main_#t~ite25_10|) InVars {ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_10|} OutVars{ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_9|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_13|, ~y~0=v_~y~0_29} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite26, ~y~0] because there is no mapped edge [2019-12-07 18:52:45,567 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [813] [813] L844-->L844-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In1875658174 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In1875658174 256)))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite27_Out1875658174| 0)) (and (= ~y$w_buff0_used~0_In1875658174 |ULTIMATE.start_main_#t~ite27_Out1875658174|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1875658174, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1875658174} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1875658174, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1875658174, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out1875658174|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 18:52:45,568 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L845-->L845-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In1208279635 256))) (.cse0 (= (mod ~y$r_buff1_thd0~0_In1208279635 256) 0)) (.cse3 (= 0 (mod ~y$r_buff0_thd0~0_In1208279635 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In1208279635 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite28_Out1208279635|)) (and (or .cse1 .cse0) (= ~y$w_buff1_used~0_In1208279635 |ULTIMATE.start_main_#t~ite28_Out1208279635|) (or .cse3 .cse2)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1208279635, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1208279635, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1208279635, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1208279635} OutVars{ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out1208279635|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1208279635, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1208279635, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1208279635, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1208279635} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 18:52:45,568 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [818] [818] L846-->L846-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-815906408 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In-815906408 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite29_Out-815906408|)) (and (= ~y$r_buff0_thd0~0_In-815906408 |ULTIMATE.start_main_#t~ite29_Out-815906408|) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-815906408, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-815906408} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-815906408, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-815906408|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-815906408} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 18:52:45,569 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [797] [797] L847-->L847-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-869671256 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In-869671256 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In-869671256 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In-869671256 256)))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd0~0_In-869671256 |ULTIMATE.start_main_#t~ite30_Out-869671256|) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2))) (= |ULTIMATE.start_main_#t~ite30_Out-869671256| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-869671256, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-869671256, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-869671256, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-869671256} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out-869671256|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-869671256, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-869671256, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-869671256, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-869671256} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30] because there is no mapped edge [2019-12-07 18:52:45,572 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L859-->L860: Formula: (and (= v_~y$r_buff0_thd0~0_48 v_~y$r_buff0_thd0~0_47) (not (= 0 (mod v_~weak$$choice2~0_17 256)))) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_48, ~weak$$choice2~0=v_~weak$$choice2~0_17} OutVars{~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_47, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_7|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_8|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_8|, ~weak$$choice2~0=v_~weak$$choice2~0_17} AuxVars[] AssignedVars[~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 18:52:45,572 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L862-->L865-1: Formula: (and (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7| (mod v_~main$tmp_guard1~0_16 256)) (not (= (mod v_~y$flush_delayed~0_30 256) 0)) (= v_~y~0_172 v_~y$mem_tmp~0_14) (= 0 v_~y$flush_delayed~0_29)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_14, ~y$flush_delayed~0=v_~y$flush_delayed~0_30, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_16} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_14, ~y$flush_delayed~0=v_~y$flush_delayed~0_29, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_16, ~y~0=v_~y~0_172, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_30|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[~y$flush_delayed~0, ~y~0, ULTIMATE.start_main_#t~ite53, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:52:45,572 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [828] [828] L865-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:52:45,635 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 06:52:45 BasicIcfg [2019-12-07 18:52:45,636 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 18:52:45,636 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:52:45,636 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:52:45,636 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:52:45,636 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:46:29" (3/4) ... [2019-12-07 18:52:45,638 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 18:52:45,638 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [862] [862] ULTIMATE.startENTRY-->L831: Formula: (let ((.cse0 (store |v_#valid_76| 0 0))) (and (= 0 v_~y$read_delayed_var~0.offset_7) (= 0 v_~weak$$choice0~0_14) (= 0 v_~y$r_buff1_thd2~0_173) (= |v_#NULL.offset_6| 0) (= |v_#length_29| (store |v_#length_30| |v_ULTIMATE.start_main_~#t805~0.base_24| 4)) (= 0 v_~__unbuffered_cnt~0_81) (= v_~y$r_buff0_thd1~0_40 0) (= v_~y$w_buff1~0_309 0) (< |v_#StackHeapBarrier_20| |v_ULTIMATE.start_main_~#t805~0.base_24|) (= 0 v_~y$r_buff0_thd3~0_201) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t805~0.base_24|)) (= v_~y$read_delayed~0_6 0) (= v_~y~0_210 0) (= 0 v_~__unbuffered_p3_EAX~0_26) (= |v_ULTIMATE.start_main_~#t805~0.offset_19| 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t805~0.base_24| 1) |v_#valid_74|) (= v_~y$r_buff0_thd0~0_436 0) (= v_~y$r_buff1_thd0~0_339 0) (= 0 v_~__unbuffered_p3_EBX~0_26) (= 0 |v_#NULL.base_6|) (= (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t805~0.base_24| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t805~0.base_24|) |v_ULTIMATE.start_main_~#t805~0.offset_19| 0)) |v_#memory_int_27|) (= v_~x~0_31 0) (= 0 v_~y$read_delayed_var~0.base_7) (= v_~y$mem_tmp~0_17 0) (= 0 v_~y$r_buff0_thd4~0_118) (< 0 |v_#StackHeapBarrier_20|) (= v_~y$w_buff0_used~0_961 0) (= v_~z~0_132 0) (= v_~a~0_21 0) (= v_~main$tmp_guard1~0_24 0) (= 0 v_~y$flush_delayed~0_38) (= 0 v_~y$r_buff1_thd3~0_154) (= v_~main$tmp_guard0~0_48 0) (= v_~weak$$choice2~0_131 0) (= 0 v_~y$r_buff1_thd4~0_167) (= 0 v_~y$w_buff0~0_462) (= v_~y$r_buff1_thd1~0_115 0) (= v_~y$w_buff1_used~0_595 0) (= 0 v_~y$r_buff0_thd2~0_133))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_20|, #valid=|v_#valid_76|, #memory_int=|v_#memory_int_28|, #length=|v_#length_30|} OutVars{ULTIMATE.start_main_#t~nondet32=|v_ULTIMATE.start_main_#t~nondet32_21|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_141|, ULTIMATE.start_main_~#t806~0.base=|v_ULTIMATE.start_main_~#t806~0.base_24|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_29|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_36|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_17|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_23|, ULTIMATE.start_main_~#t805~0.offset=|v_ULTIMATE.start_main_~#t805~0.offset_19|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_50|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_44|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~a~0=v_~a~0_21, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_36|, ~y$mem_tmp~0=v_~y$mem_tmp~0_17, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_154, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_40, ~y$flush_delayed~0=v_~y$flush_delayed~0_38, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_26, #length=|v_#length_29|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_62|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_30|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_46|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_39|, ULTIMATE.start_main_~#t807~0.base=|v_ULTIMATE.start_main_~#t807~0.base_19|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_31|, ULTIMATE.start_main_~#t807~0.offset=|v_ULTIMATE.start_main_~#t807~0.offset_16|, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_20|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_49|, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_167, ~y$w_buff1~0=v_~y$w_buff1~0_309, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_133, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_81, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_339, ~x~0=v_~x~0_31, ULTIMATE.start_main_~#t808~0.offset=|v_ULTIMATE.start_main_~#t808~0.offset_17|, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_961, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_35|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_39|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_24, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_27|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_35|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_36|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_42|, ULTIMATE.start_main_~#t805~0.base=|v_ULTIMATE.start_main_~#t805~0.base_24|, ULTIMATE.start_main_~#t808~0.base=|v_ULTIMATE.start_main_~#t808~0.base_21|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_115, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_37|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_48|, ~y$w_buff0~0=v_~y$w_buff0~0_462, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_201, ULTIMATE.start_main_~#t806~0.offset=|v_ULTIMATE.start_main_~#t806~0.offset_18|, ~y~0=v_~y~0_210, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_9|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_10|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_48|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_54|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_48, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_26, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_44|, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_73|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_173, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_118, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_34|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_436, #valid=|v_#valid_74|, #memory_int=|v_#memory_int_27|, ~z~0=v_~z~0_132, ~weak$$choice2~0=v_~weak$$choice2~0_131, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_595} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet32, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t806~0.base, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_~#t805~0.offset, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ~y$read_delayed~0, ~a~0, ULTIMATE.start_main_#t~ite52, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ~__unbuffered_p3_EAX~0, #length, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_~#t807~0.base, ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_~#t807~0.offset, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$r_buff1_thd4~0, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_~#t808~0.offset, ULTIMATE.start_main_#t~nondet31, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t805~0.base, ULTIMATE.start_main_~#t808~0.base, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite51, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ULTIMATE.start_main_~#t806~0.offset, ~y~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~__unbuffered_p3_EBX~0, ULTIMATE.start_main_#t~ite53, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ~y$r_buff0_thd4~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 18:52:45,639 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L831-1-->L833: Formula: (and (= |v_#valid_45| (store |v_#valid_46| |v_ULTIMATE.start_main_~#t806~0.base_12| 1)) (not (= |v_ULTIMATE.start_main_~#t806~0.base_12| 0)) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t806~0.base_12| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t806~0.base_12|) |v_ULTIMATE.start_main_~#t806~0.offset_10| 1)) |v_#memory_int_19|) (= |v_ULTIMATE.start_main_~#t806~0.offset_10| 0) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t806~0.base_12| 4)) (= (select |v_#valid_46| |v_ULTIMATE.start_main_~#t806~0.base_12|) 0) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t806~0.base_12|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_20|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_5|, ULTIMATE.start_main_~#t806~0.base=|v_ULTIMATE.start_main_~#t806~0.base_12|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_19|, #length=|v_#length_21|, ULTIMATE.start_main_~#t806~0.offset=|v_ULTIMATE.start_main_~#t806~0.offset_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t806~0.base, #valid, #memory_int, #length, ULTIMATE.start_main_~#t806~0.offset] because there is no mapped edge [2019-12-07 18:52:45,639 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [819] [819] L833-1-->L835: Formula: (and (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t807~0.base_10| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t807~0.base_10|) |v_ULTIMATE.start_main_~#t807~0.offset_9| 2)) |v_#memory_int_15|) (= 0 |v_ULTIMATE.start_main_~#t807~0.offset_9|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t807~0.base_10| 4)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t807~0.base_10|) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t807~0.base_10|)) (= |v_#valid_35| (store |v_#valid_36| |v_ULTIMATE.start_main_~#t807~0.base_10| 1)) (not (= 0 |v_ULTIMATE.start_main_~#t807~0.base_10|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_4|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_15|, #length=|v_#length_17|, ULTIMATE.start_main_~#t807~0.base=|v_ULTIMATE.start_main_~#t807~0.base_10|, ULTIMATE.start_main_~#t807~0.offset=|v_ULTIMATE.start_main_~#t807~0.offset_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t807~0.base, ULTIMATE.start_main_~#t807~0.offset] because there is no mapped edge [2019-12-07 18:52:45,640 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [739] [739] L4-->L785: Formula: (and (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10)) (= v_~y$r_buff0_thd2~0_30 v_~y$r_buff1_thd2~0_21) (= 1 v_~z~0_9) (= v_~y$r_buff1_thd1~0_6 v_~y$r_buff0_thd1~0_6) (= v_~y$r_buff0_thd3~0_27 1) (= v_~y$r_buff0_thd4~0_17 v_~y$r_buff1_thd4~0_14) (= v_~y$r_buff0_thd0~0_88 v_~y$r_buff1_thd0~0_47) (= v_~y$r_buff0_thd3~0_28 v_~y$r_buff1_thd3~0_19)) InVars {~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_17, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_28, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_88, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_30, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_6, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_21, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_17, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_6, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_14, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_19, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_27, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_88, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_30, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_6, ~z~0=v_~z~0_9, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_47, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, ~y$r_buff1_thd1~0, ~y$r_buff1_thd4~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd3~0, ~z~0, ~y$r_buff1_thd0~0] because there is no mapped edge [2019-12-07 18:52:45,640 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [824] [824] L835-1-->L837: Formula: (and (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t808~0.base_10| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t808~0.base_10|) |v_ULTIMATE.start_main_~#t808~0.offset_9| 3)) |v_#memory_int_17|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t808~0.base_10|) (= (store |v_#valid_38| |v_ULTIMATE.start_main_~#t808~0.base_10| 1) |v_#valid_37|) (not (= |v_ULTIMATE.start_main_~#t808~0.base_10| 0)) (= (store |v_#length_20| |v_ULTIMATE.start_main_~#t808~0.base_10| 4) |v_#length_19|) (= 0 |v_ULTIMATE.start_main_~#t808~0.offset_9|) (= 0 (select |v_#valid_38| |v_ULTIMATE.start_main_~#t808~0.base_10|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_18|, #length=|v_#length_20|} OutVars{ULTIMATE.start_main_~#t808~0.base=|v_ULTIMATE.start_main_~#t808~0.base_10|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, #valid=|v_#valid_37|, #memory_int=|v_#memory_int_17|, #length=|v_#length_19|, ULTIMATE.start_main_~#t808~0.offset=|v_ULTIMATE.start_main_~#t808~0.offset_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t808~0.base, ULTIMATE.start_main_#t~nondet23, #valid, #memory_int, #length, ULTIMATE.start_main_~#t808~0.offset] because there is no mapped edge [2019-12-07 18:52:45,641 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L786-->L786-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-708390329 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In-708390329 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P2Thread1of1ForFork0_#t~ite11_Out-708390329|)) (and (or .cse1 .cse0) (= ~y$w_buff0_used~0_In-708390329 |P2Thread1of1ForFork0_#t~ite11_Out-708390329|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-708390329, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-708390329} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-708390329, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-708390329|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-708390329} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 18:52:45,641 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [811] [811] L787-->L787-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-698535395 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd3~0_In-698535395 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd3~0_In-698535395 256))) (.cse2 (= (mod ~y$w_buff1_used~0_In-698535395 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite12_Out-698535395| ~y$w_buff1_used~0_In-698535395) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P2Thread1of1ForFork0_#t~ite12_Out-698535395| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-698535395, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-698535395, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-698535395, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-698535395} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-698535395, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-698535395, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-698535395|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-698535395, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-698535395} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 18:52:45,641 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [814] [814] L788-->L789: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-336767602 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd3~0_In-336767602 256) 0)) (.cse2 (= ~y$r_buff0_thd3~0_In-336767602 ~y$r_buff0_thd3~0_Out-336767602))) (or (and (= 0 ~y$r_buff0_thd3~0_Out-336767602) (not .cse0) (not .cse1)) (and .cse0 .cse2) (and .cse1 .cse2))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-336767602, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-336767602} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-336767602, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-336767602, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-336767602|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 18:52:45,641 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L789-->L789-2: Formula: (let ((.cse2 (= (mod ~y$r_buff1_thd3~0_In-1981019750 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In-1981019750 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1981019750 256))) (.cse1 (= (mod ~y$r_buff0_thd3~0_In-1981019750 256) 0))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd3~0_In-1981019750 |P2Thread1of1ForFork0_#t~ite14_Out-1981019750|) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite14_Out-1981019750|) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1981019750, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1981019750, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1981019750, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1981019750} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out-1981019750|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1981019750, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1981019750, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1981019750, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1981019750} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 18:52:45,641 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L789-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_18| v_~y$r_buff1_thd3~0_49) (= (+ v_~__unbuffered_cnt~0_45 1) v_~__unbuffered_cnt~0_44) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_18|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_45} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_17|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_49, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_44, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 18:52:45,642 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [834] [834] P0ENTRY-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork2_#res.offset_5| 0) (= v_~__unbuffered_cnt~0_50 (+ v_~__unbuffered_cnt~0_51 1)) (= v_P0Thread1of1ForFork2_~arg.offset_9 |v_P0Thread1of1ForFork2_#in~arg.offset_11|) (= 0 |v_P0Thread1of1ForFork2_#res.base_5|) (= v_~a~0_14 1) (= v_~x~0_21 1) (= v_P0Thread1of1ForFork2_~arg.base_9 |v_P0Thread1of1ForFork2_#in~arg.base_11|)) InVars {P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_11|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_51, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_11|} OutVars{~a~0=v_~a~0_14, P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_11|, P0Thread1of1ForFork2_~arg.offset=v_P0Thread1of1ForFork2_~arg.offset_9, P0Thread1of1ForFork2_#res.offset=|v_P0Thread1of1ForFork2_#res.offset_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_50, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_11|, P0Thread1of1ForFork2_#res.base=|v_P0Thread1of1ForFork2_#res.base_5|, ~x~0=v_~x~0_21, P0Thread1of1ForFork2_~arg.base=v_P0Thread1of1ForFork2_~arg.base_9} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork2_~arg.offset, P0Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0, P0Thread1of1ForFork2_#res.base, ~x~0, P0Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-12-07 18:52:45,642 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [807] [807] L808-2-->L808-4: Formula: (let ((.cse1 (= (mod ~y$r_buff1_thd4~0_In451998044 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In451998044 256) 0))) (or (and (not .cse0) (not .cse1) (= ~y$w_buff1~0_In451998044 |P3Thread1of1ForFork1_#t~ite15_Out451998044|)) (and (= ~y~0_In451998044 |P3Thread1of1ForFork1_#t~ite15_Out451998044|) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In451998044, ~y$w_buff1~0=~y$w_buff1~0_In451998044, ~y~0=~y~0_In451998044, ~y$w_buff1_used~0=~y$w_buff1_used~0_In451998044} OutVars{~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In451998044, ~y$w_buff1~0=~y$w_buff1~0_In451998044, P3Thread1of1ForFork1_#t~ite15=|P3Thread1of1ForFork1_#t~ite15_Out451998044|, ~y~0=~y~0_In451998044, ~y$w_buff1_used~0=~y$w_buff1_used~0_In451998044} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite15] because there is no mapped edge [2019-12-07 18:52:45,642 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [753] [753] L808-4-->L809: Formula: (= v_~y~0_56 |v_P3Thread1of1ForFork1_#t~ite15_8|) InVars {P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_8|} OutVars{P3Thread1of1ForFork1_#t~ite16=|v_P3Thread1of1ForFork1_#t~ite16_11|, P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_7|, ~y~0=v_~y~0_56} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite16, P3Thread1of1ForFork1_#t~ite15, ~y~0] because there is no mapped edge [2019-12-07 18:52:45,643 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [809] [809] L809-->L809-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In1538343199 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd4~0_In1538343199 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P3Thread1of1ForFork1_#t~ite17_Out1538343199|)) (and (= ~y$w_buff0_used~0_In1538343199 |P3Thread1of1ForFork1_#t~ite17_Out1538343199|) (or .cse1 .cse0)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1538343199, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1538343199} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1538343199, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1538343199, P3Thread1of1ForFork1_#t~ite17=|P3Thread1of1ForFork1_#t~ite17_Out1538343199|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite17] because there is no mapped edge [2019-12-07 18:52:45,643 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L810-->L810-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In582088541 256))) (.cse3 (= (mod ~y$r_buff1_thd4~0_In582088541 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In582088541 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd4~0_In582088541 256)))) (or (and (or .cse0 .cse1) (= |P3Thread1of1ForFork1_#t~ite18_Out582088541| ~y$w_buff1_used~0_In582088541) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1))) (= |P3Thread1of1ForFork1_#t~ite18_Out582088541| 0)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In582088541, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In582088541, ~y$w_buff0_used~0=~y$w_buff0_used~0_In582088541, ~y$w_buff1_used~0=~y$w_buff1_used~0_In582088541} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In582088541, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In582088541, P3Thread1of1ForFork1_#t~ite18=|P3Thread1of1ForFork1_#t~ite18_Out582088541|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In582088541, ~y$w_buff1_used~0=~y$w_buff1_used~0_In582088541} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite18] because there is no mapped edge [2019-12-07 18:52:45,643 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [792] [792] L811-->L811-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-516425222 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd4~0_In-516425222 256)))) (or (and (not .cse0) (not .cse1) (= |P3Thread1of1ForFork1_#t~ite19_Out-516425222| 0)) (and (= |P3Thread1of1ForFork1_#t~ite19_Out-516425222| ~y$r_buff0_thd4~0_In-516425222) (or .cse0 .cse1)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-516425222, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-516425222} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-516425222, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-516425222, P3Thread1of1ForFork1_#t~ite19=|P3Thread1of1ForFork1_#t~ite19_Out-516425222|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite19] because there is no mapped edge [2019-12-07 18:52:45,644 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L812-->L812-2: Formula: (let ((.cse0 (= (mod ~y$r_buff1_thd4~0_In181965624 256) 0)) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In181965624 256))) (.cse3 (= 0 (mod ~y$r_buff0_thd4~0_In181965624 256))) (.cse2 (= (mod ~y$w_buff0_used~0_In181965624 256) 0))) (or (and (= ~y$r_buff1_thd4~0_In181965624 |P3Thread1of1ForFork1_#t~ite20_Out181965624|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2))) (= |P3Thread1of1ForFork1_#t~ite20_Out181965624| 0)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In181965624, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In181965624, ~y$w_buff0_used~0=~y$w_buff0_used~0_In181965624, ~y$w_buff1_used~0=~y$w_buff1_used~0_In181965624} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In181965624, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In181965624, ~y$w_buff0_used~0=~y$w_buff0_used~0_In181965624, P3Thread1of1ForFork1_#t~ite20=|P3Thread1of1ForFork1_#t~ite20_Out181965624|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In181965624} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 18:52:45,644 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [835] [835] L812-2-->P3EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_57 1) v_~__unbuffered_cnt~0_56) (= |v_P3Thread1of1ForFork1_#t~ite20_18| v_~y$r_buff1_thd4~0_61) (= |v_P3Thread1of1ForFork1_#res.offset_3| 0) (= |v_P3Thread1of1ForFork1_#res.base_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_57, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_18|} OutVars{~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_61, P3Thread1of1ForFork1_#res.base=|v_P3Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56, P3Thread1of1ForFork1_#res.offset=|v_P3Thread1of1ForFork1_#res.offset_3|, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_17|} AuxVars[] AssignedVars[~y$r_buff1_thd4~0, P3Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork1_#res.offset, P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 18:52:45,644 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L755-2-->L755-4: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In-186759071 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-186759071 256) 0))) (or (and (= ~y$w_buff1~0_In-186759071 |P1Thread1of1ForFork3_#t~ite3_Out-186759071|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |P1Thread1of1ForFork3_#t~ite3_Out-186759071| ~y~0_In-186759071)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-186759071, ~y$w_buff1~0=~y$w_buff1~0_In-186759071, ~y~0=~y~0_In-186759071, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-186759071} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-186759071, ~y$w_buff1~0=~y$w_buff1~0_In-186759071, P1Thread1of1ForFork3_#t~ite3=|P1Thread1of1ForFork3_#t~ite3_Out-186759071|, ~y~0=~y~0_In-186759071, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-186759071} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite3] because there is no mapped edge [2019-12-07 18:52:45,644 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L755-4-->L756: Formula: (= |v_P1Thread1of1ForFork3_#t~ite3_24| v_~y~0_66) InVars {P1Thread1of1ForFork3_#t~ite3=|v_P1Thread1of1ForFork3_#t~ite3_24|} OutVars{P1Thread1of1ForFork3_#t~ite4=|v_P1Thread1of1ForFork3_#t~ite4_33|, P1Thread1of1ForFork3_#t~ite3=|v_P1Thread1of1ForFork3_#t~ite3_23|, ~y~0=v_~y~0_66} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite4, P1Thread1of1ForFork3_#t~ite3, ~y~0] because there is no mapped edge [2019-12-07 18:52:45,644 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L756-->L756-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd2~0_In411439057 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In411439057 256)))) (or (and (= 0 |P1Thread1of1ForFork3_#t~ite5_Out411439057|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~y$w_buff0_used~0_In411439057 |P1Thread1of1ForFork3_#t~ite5_Out411439057|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In411439057, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In411439057} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In411439057, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In411439057, P1Thread1of1ForFork3_#t~ite5=|P1Thread1of1ForFork3_#t~ite5_Out411439057|} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite5] because there is no mapped edge [2019-12-07 18:52:45,645 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [817] [817] L757-->L757-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In1726943671 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In1726943671 256))) (.cse3 (= (mod ~y$r_buff0_thd2~0_In1726943671 256) 0)) (.cse2 (= (mod ~y$w_buff0_used~0_In1726943671 256) 0))) (or (and (= |P1Thread1of1ForFork3_#t~ite6_Out1726943671| ~y$w_buff1_used~0_In1726943671) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P1Thread1of1ForFork3_#t~ite6_Out1726943671| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1726943671, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1726943671, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1726943671, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1726943671} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1726943671, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1726943671, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1726943671, P1Thread1of1ForFork3_#t~ite6=|P1Thread1of1ForFork3_#t~ite6_Out1726943671|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1726943671} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite6] because there is no mapped edge [2019-12-07 18:52:45,645 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L758-->L758-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In838614178 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd2~0_In838614178 256) 0))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork3_#t~ite7_Out838614178| ~y$r_buff0_thd2~0_In838614178)) (and (= |P1Thread1of1ForFork3_#t~ite7_Out838614178| 0) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In838614178, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In838614178} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In838614178, P1Thread1of1ForFork3_#t~ite7=|P1Thread1of1ForFork3_#t~ite7_Out838614178|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In838614178} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite7] because there is no mapped edge [2019-12-07 18:52:45,645 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L759-->L759-2: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In1324008106 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd2~0_In1324008106 256) 0)) (.cse3 (= (mod ~y$w_buff0_used~0_In1324008106 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd2~0_In1324008106 256) 0))) (or (and (= |P1Thread1of1ForFork3_#t~ite8_Out1324008106| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (= ~y$r_buff1_thd2~0_In1324008106 |P1Thread1of1ForFork3_#t~ite8_Out1324008106|) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1324008106, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1324008106, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1324008106, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1324008106} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1324008106, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1324008106, P1Thread1of1ForFork3_#t~ite8=|P1Thread1of1ForFork3_#t~ite8_Out1324008106|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1324008106, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1324008106} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite8] because there is no mapped edge [2019-12-07 18:52:45,645 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [820] [820] L759-2-->P1EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_39 1) v_~__unbuffered_cnt~0_38) (= 0 |v_P1Thread1of1ForFork3_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork3_#res.base_3|) (= |v_P1Thread1of1ForFork3_#t~ite8_18| v_~y$r_buff1_thd2~0_43)) InVars {P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_18|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_39} OutVars{P1Thread1of1ForFork3_#res.base=|v_P1Thread1of1ForFork3_#res.base_3|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_43, P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_17|, P1Thread1of1ForFork3_#res.offset=|v_P1Thread1of1ForFork3_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#res.base, ~y$r_buff1_thd2~0, P1Thread1of1ForFork3_#t~ite8, P1Thread1of1ForFork3_#res.offset, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 18:52:45,646 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [737] [737] L841-->L843-2: Formula: (and (or (= 0 (mod v_~y$w_buff0_used~0_154 256)) (= 0 (mod v_~y$r_buff0_thd0~0_84 256))) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~y$w_buff0_used~0=v_~y$w_buff0_used~0_154, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_84, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} OutVars{~y$w_buff0_used~0=v_~y$w_buff0_used~0_154, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_84, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 18:52:45,646 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L843-2-->L843-4: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In-1124982874 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-1124982874 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite25_Out-1124982874| ~y$w_buff1~0_In-1124982874) (not .cse1)) (and (or .cse1 .cse0) (= ~y~0_In-1124982874 |ULTIMATE.start_main_#t~ite25_Out-1124982874|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1124982874, ~y~0=~y~0_In-1124982874, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1124982874, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1124982874} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1124982874, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-1124982874|, ~y~0=~y~0_In-1124982874, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1124982874, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1124982874} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 18:52:45,646 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [725] [725] L843-4-->L844: Formula: (= v_~y~0_29 |v_ULTIMATE.start_main_#t~ite25_10|) InVars {ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_10|} OutVars{ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_9|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_13|, ~y~0=v_~y~0_29} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite26, ~y~0] because there is no mapped edge [2019-12-07 18:52:45,646 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [813] [813] L844-->L844-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In1875658174 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In1875658174 256)))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite27_Out1875658174| 0)) (and (= ~y$w_buff0_used~0_In1875658174 |ULTIMATE.start_main_#t~ite27_Out1875658174|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1875658174, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1875658174} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1875658174, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1875658174, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out1875658174|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 18:52:45,646 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L845-->L845-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In1208279635 256))) (.cse0 (= (mod ~y$r_buff1_thd0~0_In1208279635 256) 0)) (.cse3 (= 0 (mod ~y$r_buff0_thd0~0_In1208279635 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In1208279635 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite28_Out1208279635|)) (and (or .cse1 .cse0) (= ~y$w_buff1_used~0_In1208279635 |ULTIMATE.start_main_#t~ite28_Out1208279635|) (or .cse3 .cse2)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1208279635, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1208279635, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1208279635, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1208279635} OutVars{ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out1208279635|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1208279635, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1208279635, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1208279635, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1208279635} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 18:52:45,647 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [818] [818] L846-->L846-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-815906408 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In-815906408 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite29_Out-815906408|)) (and (= ~y$r_buff0_thd0~0_In-815906408 |ULTIMATE.start_main_#t~ite29_Out-815906408|) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-815906408, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-815906408} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-815906408, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-815906408|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-815906408} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 18:52:45,647 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [797] [797] L847-->L847-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-869671256 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In-869671256 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In-869671256 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In-869671256 256)))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd0~0_In-869671256 |ULTIMATE.start_main_#t~ite30_Out-869671256|) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2))) (= |ULTIMATE.start_main_#t~ite30_Out-869671256| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-869671256, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-869671256, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-869671256, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-869671256} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out-869671256|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-869671256, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-869671256, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-869671256, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-869671256} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30] because there is no mapped edge [2019-12-07 18:52:45,650 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L859-->L860: Formula: (and (= v_~y$r_buff0_thd0~0_48 v_~y$r_buff0_thd0~0_47) (not (= 0 (mod v_~weak$$choice2~0_17 256)))) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_48, ~weak$$choice2~0=v_~weak$$choice2~0_17} OutVars{~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_47, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_7|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_8|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_8|, ~weak$$choice2~0=v_~weak$$choice2~0_17} AuxVars[] AssignedVars[~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 18:52:45,651 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L862-->L865-1: Formula: (and (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7| (mod v_~main$tmp_guard1~0_16 256)) (not (= (mod v_~y$flush_delayed~0_30 256) 0)) (= v_~y~0_172 v_~y$mem_tmp~0_14) (= 0 v_~y$flush_delayed~0_29)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_14, ~y$flush_delayed~0=v_~y$flush_delayed~0_30, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_16} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_14, ~y$flush_delayed~0=v_~y$flush_delayed~0_29, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_16, ~y~0=v_~y~0_172, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_30|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[~y$flush_delayed~0, ~y~0, ULTIMATE.start_main_#t~ite53, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:52:45,651 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [828] [828] L865-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:52:45,710 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_574666ef-5228-4dc6-973e-31744f12bb1b/bin/uautomizer/witness.graphml [2019-12-07 18:52:45,710 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:52:45,711 INFO L168 Benchmark]: Toolchain (without parser) took 377092.11 ms. Allocated memory was 1.0 GB in the beginning and 9.9 GB in the end (delta: 8.9 GB). Free memory was 934.4 MB in the beginning and 5.6 GB in the end (delta: -4.7 GB). Peak memory consumption was 4.2 GB. Max. memory is 11.5 GB. [2019-12-07 18:52:45,711 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 955.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:52:45,711 INFO L168 Benchmark]: CACSL2BoogieTranslator took 407.10 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 118.5 MB). Free memory was 934.4 MB in the beginning and 1.1 GB in the end (delta: -146.3 MB). Peak memory consumption was 18.5 MB. Max. memory is 11.5 GB. [2019-12-07 18:52:45,712 INFO L168 Benchmark]: Boogie Procedure Inliner took 39.05 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:52:45,712 INFO L168 Benchmark]: Boogie Preprocessor took 26.27 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:52:45,712 INFO L168 Benchmark]: RCFGBuilder took 418.59 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.2 MB). Peak memory consumption was 55.2 MB. Max. memory is 11.5 GB. [2019-12-07 18:52:45,712 INFO L168 Benchmark]: TraceAbstraction took 376123.81 ms. Allocated memory was 1.1 GB in the beginning and 9.9 GB in the end (delta: 8.8 GB). Free memory was 1.0 GB in the beginning and 5.6 GB in the end (delta: -4.6 GB). Peak memory consumption was 4.2 GB. Max. memory is 11.5 GB. [2019-12-07 18:52:45,713 INFO L168 Benchmark]: Witness Printer took 73.99 ms. Allocated memory is still 9.9 GB. Free memory was 5.6 GB in the beginning and 5.6 GB in the end (delta: 37.9 MB). Peak memory consumption was 37.9 MB. Max. memory is 11.5 GB. [2019-12-07 18:52:45,714 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 955.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 407.10 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 118.5 MB). Free memory was 934.4 MB in the beginning and 1.1 GB in the end (delta: -146.3 MB). Peak memory consumption was 18.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 39.05 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.27 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 418.59 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.2 MB). Peak memory consumption was 55.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 376123.81 ms. Allocated memory was 1.1 GB in the beginning and 9.9 GB in the end (delta: 8.8 GB). Free memory was 1.0 GB in the beginning and 5.6 GB in the end (delta: -4.6 GB). Peak memory consumption was 4.2 GB. Max. memory is 11.5 GB. * Witness Printer took 73.99 ms. Allocated memory is still 9.9 GB. Free memory was 5.6 GB in the beginning and 5.6 GB in the end (delta: 37.9 MB). Peak memory consumption was 37.9 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.2s, 191 ProgramPointsBefore, 104 ProgramPointsAfterwards, 225 TransitionsBefore, 115 TransitionsAfterwards, 18432 CoEnabledTransitionPairs, 7 FixpointIterations, 35 TrivialSequentialCompositions, 48 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 37 ConcurrentYvCompositions, 28 ChoiceCompositions, 6687 VarBasedMoverChecksPositive, 264 VarBasedMoverChecksNegative, 76 SemBasedMoverChecksPositive, 273 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.0s, 0 MoverChecksTotal, 85060 CheckedPairsTotal, 120 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L831] FCALL, FORK 0 pthread_create(&t805, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L833] FCALL, FORK 0 pthread_create(&t806, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L835] FCALL, FORK 0 pthread_create(&t807, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L769] 3 y$w_buff1 = y$w_buff0 [L770] 3 y$w_buff0 = 2 [L771] 3 y$w_buff1_used = y$w_buff0_used [L772] 3 y$w_buff0_used = (_Bool)1 [L837] FCALL, FORK 0 pthread_create(&t808, ((void *)0), P3, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L785] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L785] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L786] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L787] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L799] 4 z = 2 [L802] 4 __unbuffered_p3_EAX = z [L805] 4 __unbuffered_p3_EBX = a VAL [__unbuffered_cnt=1, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L808] 4 y$w_buff0_used && y$r_buff0_thd4 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd4 ? y$w_buff1 : y) VAL [__unbuffered_cnt=1, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L749] 2 x = 2 [L752] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, y$w_buff1_used && y$r_buff1_thd4 ? y$w_buff1 : y=2, z=2] [L755] 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L809] 4 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd4 ? (_Bool)0 : y$w_buff0_used [L810] 4 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd4 || y$w_buff1_used && y$r_buff1_thd4 ? (_Bool)0 : y$w_buff1_used [L811] 4 y$r_buff0_thd4 = y$w_buff0_used && y$r_buff0_thd4 ? (_Bool)0 : y$r_buff0_thd4 [L756] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L757] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L758] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L839] 0 main$tmp_guard0 = __unbuffered_cnt == 4 VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L844] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L845] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L846] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L847] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L850] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L851] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L852] 0 y$flush_delayed = weak$$choice2 [L853] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L854] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L854] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L855] EXPR 0 weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L855] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L856] EXPR 0 weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L856] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L857] EXPR 0 weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L857] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L858] EXPR 0 weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L858] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L860] EXPR 0 weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L860] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L861] 0 main$tmp_guard1 = !(x == 2 && y == 2 && z == 2 && __unbuffered_p3_EAX == 2 && __unbuffered_p3_EBX == 0) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=2, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 179 locations, 2 error locations. Result: UNSAFE, OverallTime: 375.9s, OverallIterations: 21, TraceHistogramMax: 1, AutomataDifference: 79.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 4060 SDtfs, 4547 SDslu, 9340 SDs, 0 SdLazy, 5002 SolverSat, 263 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 11.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 214 GetRequests, 42 SyntacticMatches, 23 SemanticMatches, 149 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 396 ImplicationChecksByTransitivity, 1.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=541362occurred in iteration=7, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 228.4s AutomataMinimizationTime, 20 MinimizatonAttempts, 972945 StatesRemovedByMinimization, 17 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.0s InterpolantComputationTime, 882 NumberOfCodeBlocks, 882 NumberOfCodeBlocksAsserted, 21 NumberOfCheckSat, 791 ConstructedInterpolants, 0 QuantifiedInterpolants, 168883 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 20 InterpolantComputations, 20 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...