./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix033_power.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_dde28f07-fd16-4804-8edb-05c660702a75/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_dde28f07-fd16-4804-8edb-05c660702a75/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_dde28f07-fd16-4804-8edb-05c660702a75/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_dde28f07-fd16-4804-8edb-05c660702a75/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix033_power.oepc.i -s /tmp/vcloud-vcloud-master/worker/run_dir_dde28f07-fd16-4804-8edb-05c660702a75/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_dde28f07-fd16-4804-8edb-05c660702a75/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 26c00609450d0c6b51da4247483bad4298e13733 .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 17:04:50,198 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 17:04:50,200 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 17:04:50,207 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 17:04:50,207 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 17:04:50,208 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 17:04:50,209 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 17:04:50,210 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 17:04:50,211 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 17:04:50,212 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 17:04:50,212 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 17:04:50,213 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 17:04:50,213 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 17:04:50,214 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 17:04:50,215 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 17:04:50,215 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 17:04:50,216 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 17:04:50,217 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 17:04:50,218 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 17:04:50,219 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 17:04:50,220 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 17:04:50,221 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 17:04:50,222 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 17:04:50,222 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 17:04:50,224 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 17:04:50,224 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 17:04:50,224 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 17:04:50,224 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 17:04:50,225 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 17:04:50,225 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 17:04:50,225 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 17:04:50,226 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 17:04:50,226 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 17:04:50,227 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 17:04:50,227 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 17:04:50,227 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 17:04:50,228 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 17:04:50,228 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 17:04:50,228 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 17:04:50,228 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 17:04:50,229 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 17:04:50,229 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_dde28f07-fd16-4804-8edb-05c660702a75/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 17:04:50,239 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 17:04:50,239 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 17:04:50,240 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 17:04:50,240 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 17:04:50,240 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 17:04:50,240 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 17:04:50,240 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 17:04:50,240 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 17:04:50,240 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 17:04:50,241 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 17:04:50,241 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 17:04:50,241 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 17:04:50,241 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 17:04:50,241 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 17:04:50,241 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 17:04:50,241 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 17:04:50,241 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 17:04:50,242 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 17:04:50,242 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 17:04:50,242 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 17:04:50,242 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 17:04:50,242 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:04:50,242 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 17:04:50,242 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 17:04:50,242 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 17:04:50,243 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 17:04:50,243 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 17:04:50,243 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 17:04:50,243 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 17:04:50,243 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_dde28f07-fd16-4804-8edb-05c660702a75/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 26c00609450d0c6b51da4247483bad4298e13733 [2019-12-07 17:04:50,343 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 17:04:50,353 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 17:04:50,356 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 17:04:50,357 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 17:04:50,358 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 17:04:50,358 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_dde28f07-fd16-4804-8edb-05c660702a75/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix033_power.oepc.i [2019-12-07 17:04:50,402 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_dde28f07-fd16-4804-8edb-05c660702a75/bin/uautomizer/data/51d616a8d/c78937b8d9564ffc97d23fdca4e4f6fc/FLAGb3c3d9a0a [2019-12-07 17:04:50,759 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 17:04:50,760 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_dde28f07-fd16-4804-8edb-05c660702a75/sv-benchmarks/c/pthread-wmm/mix033_power.oepc.i [2019-12-07 17:04:50,769 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_dde28f07-fd16-4804-8edb-05c660702a75/bin/uautomizer/data/51d616a8d/c78937b8d9564ffc97d23fdca4e4f6fc/FLAGb3c3d9a0a [2019-12-07 17:04:50,778 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_dde28f07-fd16-4804-8edb-05c660702a75/bin/uautomizer/data/51d616a8d/c78937b8d9564ffc97d23fdca4e4f6fc [2019-12-07 17:04:50,780 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 17:04:50,780 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 17:04:50,781 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 17:04:50,781 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 17:04:50,783 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 17:04:50,784 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:04:50" (1/1) ... [2019-12-07 17:04:50,785 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1c8002ab and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:04:50, skipping insertion in model container [2019-12-07 17:04:50,785 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:04:50" (1/1) ... [2019-12-07 17:04:50,790 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 17:04:50,817 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 17:04:51,059 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:04:51,067 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 17:04:51,111 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:04:51,156 INFO L208 MainTranslator]: Completed translation [2019-12-07 17:04:51,157 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:04:51 WrapperNode [2019-12-07 17:04:51,157 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 17:04:51,157 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 17:04:51,157 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 17:04:51,158 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 17:04:51,163 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:04:51" (1/1) ... [2019-12-07 17:04:51,177 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:04:51" (1/1) ... [2019-12-07 17:04:51,196 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 17:04:51,196 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 17:04:51,196 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 17:04:51,196 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 17:04:51,203 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:04:51" (1/1) ... [2019-12-07 17:04:51,203 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:04:51" (1/1) ... [2019-12-07 17:04:51,206 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:04:51" (1/1) ... [2019-12-07 17:04:51,207 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:04:51" (1/1) ... [2019-12-07 17:04:51,214 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:04:51" (1/1) ... [2019-12-07 17:04:51,217 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:04:51" (1/1) ... [2019-12-07 17:04:51,219 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:04:51" (1/1) ... [2019-12-07 17:04:51,223 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 17:04:51,223 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 17:04:51,223 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 17:04:51,223 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 17:04:51,224 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:04:51" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_dde28f07-fd16-4804-8edb-05c660702a75/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:04:51,263 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 17:04:51,264 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 17:04:51,264 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 17:04:51,264 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 17:04:51,264 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 17:04:51,264 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 17:04:51,264 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 17:04:51,264 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 17:04:51,264 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 17:04:51,264 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 17:04:51,264 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 17:04:51,264 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 17:04:51,265 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 17:04:51,266 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 17:04:51,627 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 17:04:51,627 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 17:04:51,628 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:04:51 BoogieIcfgContainer [2019-12-07 17:04:51,628 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 17:04:51,628 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 17:04:51,628 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 17:04:51,630 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 17:04:51,630 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 05:04:50" (1/3) ... [2019-12-07 17:04:51,631 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@e03a26a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:04:51, skipping insertion in model container [2019-12-07 17:04:51,631 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:04:51" (2/3) ... [2019-12-07 17:04:51,631 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@e03a26a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:04:51, skipping insertion in model container [2019-12-07 17:04:51,631 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:04:51" (3/3) ... [2019-12-07 17:04:51,632 INFO L109 eAbstractionObserver]: Analyzing ICFG mix033_power.oepc.i [2019-12-07 17:04:51,639 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 17:04:51,639 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 17:04:51,644 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 17:04:51,644 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 17:04:51,670 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,670 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,670 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,670 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,670 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,670 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,671 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,671 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,671 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,671 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,671 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,671 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,672 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,672 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,672 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,672 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,672 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,672 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,672 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,672 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,672 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,673 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,673 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,673 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,673 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,673 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,673 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,673 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,673 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,674 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,674 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,674 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,674 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,674 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,674 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,674 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,675 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,675 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,675 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,675 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,675 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,675 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,675 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,675 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,676 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,676 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,676 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,676 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,676 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,676 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,676 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,676 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,677 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,677 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,677 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,677 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,677 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,677 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,677 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,677 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,677 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,678 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,678 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,678 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,678 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,679 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,679 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,679 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,679 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,679 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,679 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,679 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,679 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,679 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,679 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,679 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,682 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,682 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,682 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,682 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,682 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,682 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,682 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,682 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,683 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,683 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,683 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,683 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,683 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,683 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,683 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,683 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,683 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,683 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,684 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,684 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,684 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,684 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,684 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,684 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,684 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,684 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,684 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,684 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,685 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,685 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,685 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,685 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,685 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,685 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,685 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,685 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,685 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,685 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,686 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,686 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,686 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,686 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,686 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,686 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,686 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,686 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,686 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,686 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,687 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,687 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,687 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,687 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,687 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,687 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,687 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,687 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,687 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,687 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,688 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,688 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,688 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,688 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,688 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,688 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,688 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,688 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,688 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,688 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,688 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,689 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,689 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,689 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,689 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,689 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,689 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,689 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,689 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,689 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,689 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,690 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,690 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,690 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,690 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,690 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,690 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,690 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,690 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:04:51,703 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 17:04:51,715 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 17:04:51,715 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 17:04:51,715 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 17:04:51,715 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 17:04:51,715 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 17:04:51,716 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 17:04:51,716 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 17:04:51,716 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 17:04:51,726 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 179 places, 216 transitions [2019-12-07 17:04:51,728 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 179 places, 216 transitions [2019-12-07 17:04:51,782 INFO L134 PetriNetUnfolder]: 47/213 cut-off events. [2019-12-07 17:04:51,782 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 17:04:51,792 INFO L76 FinitePrefix]: Finished finitePrefix Result has 223 conditions, 213 events. 47/213 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 694 event pairs. 9/173 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 17:04:51,808 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 179 places, 216 transitions [2019-12-07 17:04:51,841 INFO L134 PetriNetUnfolder]: 47/213 cut-off events. [2019-12-07 17:04:51,842 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 17:04:51,847 INFO L76 FinitePrefix]: Finished finitePrefix Result has 223 conditions, 213 events. 47/213 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 694 event pairs. 9/173 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 17:04:51,862 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 19004 [2019-12-07 17:04:51,863 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 17:04:54,934 WARN L192 SmtUtils]: Spent 180.00 ms on a formula simplification. DAG size of input: 97 DAG size of output: 95 [2019-12-07 17:04:55,190 WARN L192 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 48 [2019-12-07 17:04:55,214 INFO L206 etLargeBlockEncoding]: Checked pairs total: 80691 [2019-12-07 17:04:55,214 INFO L214 etLargeBlockEncoding]: Total number of compositions: 120 [2019-12-07 17:04:55,216 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 93 places, 102 transitions [2019-12-07 17:05:07,837 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 109594 states. [2019-12-07 17:05:07,838 INFO L276 IsEmpty]: Start isEmpty. Operand 109594 states. [2019-12-07 17:05:07,842 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-12-07 17:05:07,842 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:05:07,842 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-12-07 17:05:07,843 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:05:07,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:05:07,846 INFO L82 PathProgramCache]: Analyzing trace with hash 925663, now seen corresponding path program 1 times [2019-12-07 17:05:07,852 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:05:07,852 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1408806191] [2019-12-07 17:05:07,852 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:05:07,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:05:07,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:05:07,981 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1408806191] [2019-12-07 17:05:07,981 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:05:07,981 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 17:05:07,982 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1210850112] [2019-12-07 17:05:07,985 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:05:07,985 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:05:07,994 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:05:07,995 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:05:07,996 INFO L87 Difference]: Start difference. First operand 109594 states. Second operand 3 states. [2019-12-07 17:05:08,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:05:08,850 INFO L93 Difference]: Finished difference Result 108584 states and 463030 transitions. [2019-12-07 17:05:08,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:05:08,851 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-12-07 17:05:08,851 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:05:09,280 INFO L225 Difference]: With dead ends: 108584 [2019-12-07 17:05:09,280 INFO L226 Difference]: Without dead ends: 102344 [2019-12-07 17:05:09,281 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:05:13,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102344 states. [2019-12-07 17:05:14,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102344 to 102344. [2019-12-07 17:05:14,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102344 states. [2019-12-07 17:05:14,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102344 states to 102344 states and 435834 transitions. [2019-12-07 17:05:14,988 INFO L78 Accepts]: Start accepts. Automaton has 102344 states and 435834 transitions. Word has length 3 [2019-12-07 17:05:14,988 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:05:14,988 INFO L462 AbstractCegarLoop]: Abstraction has 102344 states and 435834 transitions. [2019-12-07 17:05:14,988 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:05:14,988 INFO L276 IsEmpty]: Start isEmpty. Operand 102344 states and 435834 transitions. [2019-12-07 17:05:14,990 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 17:05:14,990 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:05:14,991 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:05:14,991 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:05:14,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:05:14,991 INFO L82 PathProgramCache]: Analyzing trace with hash 295188242, now seen corresponding path program 1 times [2019-12-07 17:05:14,991 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:05:14,991 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [101530432] [2019-12-07 17:05:14,991 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:05:15,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:05:16,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:05:16,447 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [101530432] [2019-12-07 17:05:16,448 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:05:16,448 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:05:16,448 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1229361321] [2019-12-07 17:05:16,449 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:05:16,449 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:05:16,450 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:05:16,450 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:05:16,450 INFO L87 Difference]: Start difference. First operand 102344 states and 435834 transitions. Second operand 4 states. [2019-12-07 17:05:17,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:05:17,278 INFO L93 Difference]: Finished difference Result 162816 states and 664963 transitions. [2019-12-07 17:05:17,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:05:17,278 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 17:05:17,279 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:05:17,688 INFO L225 Difference]: With dead ends: 162816 [2019-12-07 17:05:17,688 INFO L226 Difference]: Without dead ends: 162767 [2019-12-07 17:05:17,689 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:05:22,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162767 states. [2019-12-07 17:05:24,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162767 to 148375. [2019-12-07 17:05:24,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148375 states. [2019-12-07 17:05:25,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148375 states to 148375 states and 613985 transitions. [2019-12-07 17:05:25,086 INFO L78 Accepts]: Start accepts. Automaton has 148375 states and 613985 transitions. Word has length 11 [2019-12-07 17:05:25,086 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:05:25,086 INFO L462 AbstractCegarLoop]: Abstraction has 148375 states and 613985 transitions. [2019-12-07 17:05:25,086 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:05:25,086 INFO L276 IsEmpty]: Start isEmpty. Operand 148375 states and 613985 transitions. [2019-12-07 17:05:25,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 17:05:25,093 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:05:25,093 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:05:25,093 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:05:25,093 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:05:25,093 INFO L82 PathProgramCache]: Analyzing trace with hash 1979345710, now seen corresponding path program 1 times [2019-12-07 17:05:25,093 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:05:25,093 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1303664748] [2019-12-07 17:05:25,094 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:05:25,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:05:25,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:05:25,144 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1303664748] [2019-12-07 17:05:25,145 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:05:25,145 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:05:25,145 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [413597308] [2019-12-07 17:05:25,145 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:05:25,145 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:05:25,145 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:05:25,146 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:05:25,146 INFO L87 Difference]: Start difference. First operand 148375 states and 613985 transitions. Second operand 4 states. [2019-12-07 17:05:26,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:05:26,164 INFO L93 Difference]: Finished difference Result 208037 states and 841937 transitions. [2019-12-07 17:05:26,165 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:05:26,165 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 17:05:26,165 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:05:26,675 INFO L225 Difference]: With dead ends: 208037 [2019-12-07 17:05:26,675 INFO L226 Difference]: Without dead ends: 207981 [2019-12-07 17:05:26,675 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:05:33,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207981 states. [2019-12-07 17:05:36,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207981 to 175449. [2019-12-07 17:05:36,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 175449 states. [2019-12-07 17:05:36,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175449 states to 175449 states and 722246 transitions. [2019-12-07 17:05:36,652 INFO L78 Accepts]: Start accepts. Automaton has 175449 states and 722246 transitions. Word has length 13 [2019-12-07 17:05:36,653 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:05:36,653 INFO L462 AbstractCegarLoop]: Abstraction has 175449 states and 722246 transitions. [2019-12-07 17:05:36,653 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:05:36,653 INFO L276 IsEmpty]: Start isEmpty. Operand 175449 states and 722246 transitions. [2019-12-07 17:05:36,660 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 17:05:36,660 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:05:36,660 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:05:36,660 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:05:36,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:05:36,660 INFO L82 PathProgramCache]: Analyzing trace with hash -1850281775, now seen corresponding path program 1 times [2019-12-07 17:05:36,661 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:05:36,661 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1735252600] [2019-12-07 17:05:36,661 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:05:36,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:05:36,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:05:36,690 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1735252600] [2019-12-07 17:05:36,691 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:05:36,691 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:05:36,691 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1828462469] [2019-12-07 17:05:36,691 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:05:36,691 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:05:36,692 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:05:36,692 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:05:36,692 INFO L87 Difference]: Start difference. First operand 175449 states and 722246 transitions. Second operand 3 states. [2019-12-07 17:05:38,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:05:38,236 INFO L93 Difference]: Finished difference Result 259190 states and 1053818 transitions. [2019-12-07 17:05:38,237 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:05:38,237 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 16 [2019-12-07 17:05:38,237 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:05:38,858 INFO L225 Difference]: With dead ends: 259190 [2019-12-07 17:05:38,858 INFO L226 Difference]: Without dead ends: 259190 [2019-12-07 17:05:38,859 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:05:47,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 259190 states. [2019-12-07 17:05:49,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 259190 to 195219. [2019-12-07 17:05:49,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 195219 states. [2019-12-07 17:05:50,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195219 states to 195219 states and 799392 transitions. [2019-12-07 17:05:50,422 INFO L78 Accepts]: Start accepts. Automaton has 195219 states and 799392 transitions. Word has length 16 [2019-12-07 17:05:50,422 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:05:50,422 INFO L462 AbstractCegarLoop]: Abstraction has 195219 states and 799392 transitions. [2019-12-07 17:05:50,422 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:05:50,422 INFO L276 IsEmpty]: Start isEmpty. Operand 195219 states and 799392 transitions. [2019-12-07 17:05:50,428 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 17:05:50,428 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:05:50,428 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:05:50,428 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:05:50,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:05:50,429 INFO L82 PathProgramCache]: Analyzing trace with hash -1985443542, now seen corresponding path program 1 times [2019-12-07 17:05:50,429 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:05:50,429 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [538410960] [2019-12-07 17:05:50,429 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:05:50,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:05:50,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:05:50,466 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [538410960] [2019-12-07 17:05:50,466 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:05:50,466 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:05:50,466 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [10476189] [2019-12-07 17:05:50,466 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:05:50,466 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:05:50,467 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:05:50,467 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:05:50,467 INFO L87 Difference]: Start difference. First operand 195219 states and 799392 transitions. Second operand 4 states. [2019-12-07 17:05:51,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:05:51,564 INFO L93 Difference]: Finished difference Result 227593 states and 924546 transitions. [2019-12-07 17:05:51,565 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:05:51,565 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2019-12-07 17:05:51,565 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:05:52,136 INFO L225 Difference]: With dead ends: 227593 [2019-12-07 17:05:52,136 INFO L226 Difference]: Without dead ends: 227593 [2019-12-07 17:05:52,137 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:05:57,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 227593 states. [2019-12-07 17:06:03,115 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 227593 to 204638. [2019-12-07 17:06:03,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 204638 states. [2019-12-07 17:06:03,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204638 states to 204638 states and 837381 transitions. [2019-12-07 17:06:03,736 INFO L78 Accepts]: Start accepts. Automaton has 204638 states and 837381 transitions. Word has length 16 [2019-12-07 17:06:03,737 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:06:03,737 INFO L462 AbstractCegarLoop]: Abstraction has 204638 states and 837381 transitions. [2019-12-07 17:06:03,737 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:06:03,737 INFO L276 IsEmpty]: Start isEmpty. Operand 204638 states and 837381 transitions. [2019-12-07 17:06:03,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 17:06:03,744 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:06:03,744 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:06:03,744 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:06:03,744 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:06:03,745 INFO L82 PathProgramCache]: Analyzing trace with hash -32753983, now seen corresponding path program 1 times [2019-12-07 17:06:03,745 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:06:03,745 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [853859742] [2019-12-07 17:06:03,745 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:06:03,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:06:03,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:06:03,779 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [853859742] [2019-12-07 17:06:03,779 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:06:03,779 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:06:03,780 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [44700710] [2019-12-07 17:06:03,780 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:06:03,780 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:06:03,780 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:06:03,780 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:06:03,780 INFO L87 Difference]: Start difference. First operand 204638 states and 837381 transitions. Second operand 4 states. [2019-12-07 17:06:05,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:06:05,322 INFO L93 Difference]: Finished difference Result 239634 states and 974592 transitions. [2019-12-07 17:06:05,323 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:06:05,323 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2019-12-07 17:06:05,323 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:06:05,939 INFO L225 Difference]: With dead ends: 239634 [2019-12-07 17:06:05,939 INFO L226 Difference]: Without dead ends: 239634 [2019-12-07 17:06:05,940 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:06:11,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239634 states. [2019-12-07 17:06:14,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239634 to 207981. [2019-12-07 17:06:14,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207981 states. [2019-12-07 17:06:15,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207981 states to 207981 states and 851409 transitions. [2019-12-07 17:06:15,758 INFO L78 Accepts]: Start accepts. Automaton has 207981 states and 851409 transitions. Word has length 16 [2019-12-07 17:06:15,758 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:06:15,758 INFO L462 AbstractCegarLoop]: Abstraction has 207981 states and 851409 transitions. [2019-12-07 17:06:15,758 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:06:15,758 INFO L276 IsEmpty]: Start isEmpty. Operand 207981 states and 851409 transitions. [2019-12-07 17:06:15,770 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2019-12-07 17:06:15,770 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:06:15,771 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:06:15,771 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:06:15,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:06:15,771 INFO L82 PathProgramCache]: Analyzing trace with hash -486126770, now seen corresponding path program 1 times [2019-12-07 17:06:15,771 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:06:15,771 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184166755] [2019-12-07 17:06:15,771 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:06:15,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:06:15,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:06:15,824 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [184166755] [2019-12-07 17:06:15,824 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:06:15,824 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 17:06:15,824 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1876544835] [2019-12-07 17:06:15,824 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:06:15,825 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:06:15,825 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:06:15,825 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:06:15,825 INFO L87 Difference]: Start difference. First operand 207981 states and 851409 transitions. Second operand 3 states. [2019-12-07 17:06:19,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:06:19,995 INFO L93 Difference]: Finished difference Result 372280 states and 1515056 transitions. [2019-12-07 17:06:19,995 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:06:19,995 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 18 [2019-12-07 17:06:19,996 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:06:20,805 INFO L225 Difference]: With dead ends: 372280 [2019-12-07 17:06:20,805 INFO L226 Difference]: Without dead ends: 337486 [2019-12-07 17:06:20,806 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:06:27,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 337486 states. [2019-12-07 17:06:32,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 337486 to 324440. [2019-12-07 17:06:32,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 324440 states. [2019-12-07 17:06:33,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 324440 states to 324440 states and 1329299 transitions. [2019-12-07 17:06:33,088 INFO L78 Accepts]: Start accepts. Automaton has 324440 states and 1329299 transitions. Word has length 18 [2019-12-07 17:06:33,088 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:06:33,088 INFO L462 AbstractCegarLoop]: Abstraction has 324440 states and 1329299 transitions. [2019-12-07 17:06:33,088 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:06:33,088 INFO L276 IsEmpty]: Start isEmpty. Operand 324440 states and 1329299 transitions. [2019-12-07 17:06:33,107 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 17:06:33,108 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:06:33,108 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:06:33,108 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:06:33,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:06:33,108 INFO L82 PathProgramCache]: Analyzing trace with hash -1539660278, now seen corresponding path program 1 times [2019-12-07 17:06:33,108 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:06:33,108 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894327352] [2019-12-07 17:06:33,108 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:06:33,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:06:33,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:06:33,166 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [894327352] [2019-12-07 17:06:33,167 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:06:33,167 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:06:33,167 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [644995701] [2019-12-07 17:06:33,167 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:06:33,167 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:06:33,168 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:06:33,168 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:06:33,168 INFO L87 Difference]: Start difference. First operand 324440 states and 1329299 transitions. Second operand 5 states. [2019-12-07 17:06:35,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:06:35,965 INFO L93 Difference]: Finished difference Result 458907 states and 1837584 transitions. [2019-12-07 17:06:35,965 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:06:35,965 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 17:06:35,965 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:06:37,647 INFO L225 Difference]: With dead ends: 458907 [2019-12-07 17:06:37,647 INFO L226 Difference]: Without dead ends: 458816 [2019-12-07 17:06:37,648 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:06:49,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 458816 states. [2019-12-07 17:06:55,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 458816 to 349791. [2019-12-07 17:06:55,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 349791 states. [2019-12-07 17:06:56,650 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 349791 states to 349791 states and 1426231 transitions. [2019-12-07 17:06:56,650 INFO L78 Accepts]: Start accepts. Automaton has 349791 states and 1426231 transitions. Word has length 19 [2019-12-07 17:06:56,650 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:06:56,650 INFO L462 AbstractCegarLoop]: Abstraction has 349791 states and 1426231 transitions. [2019-12-07 17:06:56,650 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:06:56,650 INFO L276 IsEmpty]: Start isEmpty. Operand 349791 states and 1426231 transitions. [2019-12-07 17:06:56,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 17:06:56,675 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:06:56,675 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:06:56,675 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:06:56,675 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:06:56,675 INFO L82 PathProgramCache]: Analyzing trace with hash 1882855134, now seen corresponding path program 1 times [2019-12-07 17:06:56,675 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:06:56,675 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1163415632] [2019-12-07 17:06:56,676 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:06:56,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:06:56,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:06:56,702 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1163415632] [2019-12-07 17:06:56,703 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:06:56,703 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 17:06:56,703 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503261479] [2019-12-07 17:06:56,703 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:06:56,703 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:06:56,703 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:06:56,704 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:06:56,704 INFO L87 Difference]: Start difference. First operand 349791 states and 1426231 transitions. Second operand 3 states. [2019-12-07 17:06:58,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:06:58,792 INFO L93 Difference]: Finished difference Result 349467 states and 1424966 transitions. [2019-12-07 17:06:58,792 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:06:58,792 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2019-12-07 17:06:58,793 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:06:59,691 INFO L225 Difference]: With dead ends: 349467 [2019-12-07 17:06:59,691 INFO L226 Difference]: Without dead ends: 349467 [2019-12-07 17:06:59,691 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:07:10,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 349467 states. [2019-12-07 17:07:14,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 349467 to 346461. [2019-12-07 17:07:14,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 346461 states. [2019-12-07 17:07:16,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 346461 states to 346461 states and 1413505 transitions. [2019-12-07 17:07:16,391 INFO L78 Accepts]: Start accepts. Automaton has 346461 states and 1413505 transitions. Word has length 19 [2019-12-07 17:07:16,391 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:07:16,391 INFO L462 AbstractCegarLoop]: Abstraction has 346461 states and 1413505 transitions. [2019-12-07 17:07:16,391 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:07:16,391 INFO L276 IsEmpty]: Start isEmpty. Operand 346461 states and 1413505 transitions. [2019-12-07 17:07:16,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 17:07:16,418 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:07:16,418 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:07:16,418 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:07:16,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:07:16,418 INFO L82 PathProgramCache]: Analyzing trace with hash -434257907, now seen corresponding path program 1 times [2019-12-07 17:07:16,418 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:07:16,418 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1108729864] [2019-12-07 17:07:16,418 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:07:16,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:07:16,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:07:16,453 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1108729864] [2019-12-07 17:07:16,453 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:07:16,453 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:07:16,453 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [568734856] [2019-12-07 17:07:16,453 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:07:16,453 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:07:16,453 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:07:16,454 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:07:16,454 INFO L87 Difference]: Start difference. First operand 346461 states and 1413505 transitions. Second operand 3 states. [2019-12-07 17:07:17,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:07:17,807 INFO L93 Difference]: Finished difference Result 324262 states and 1308808 transitions. [2019-12-07 17:07:17,808 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:07:17,808 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2019-12-07 17:07:17,808 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:07:19,148 INFO L225 Difference]: With dead ends: 324262 [2019-12-07 17:07:19,148 INFO L226 Difference]: Without dead ends: 324262 [2019-12-07 17:07:19,148 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:07:25,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 324262 states. [2019-12-07 17:07:29,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 324262 to 321894. [2019-12-07 17:07:29,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 321894 states. [2019-12-07 17:07:30,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 321894 states to 321894 states and 1300178 transitions. [2019-12-07 17:07:30,605 INFO L78 Accepts]: Start accepts. Automaton has 321894 states and 1300178 transitions. Word has length 19 [2019-12-07 17:07:30,605 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:07:30,605 INFO L462 AbstractCegarLoop]: Abstraction has 321894 states and 1300178 transitions. [2019-12-07 17:07:30,605 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:07:30,605 INFO L276 IsEmpty]: Start isEmpty. Operand 321894 states and 1300178 transitions. [2019-12-07 17:07:30,625 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 17:07:30,626 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:07:30,626 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:07:30,626 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:07:30,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:07:30,626 INFO L82 PathProgramCache]: Analyzing trace with hash -1804312711, now seen corresponding path program 1 times [2019-12-07 17:07:30,626 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:07:30,626 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911361501] [2019-12-07 17:07:30,626 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:07:30,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:07:30,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:07:30,670 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1911361501] [2019-12-07 17:07:30,671 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:07:30,671 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:07:30,671 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [121690941] [2019-12-07 17:07:30,671 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:07:30,671 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:07:30,672 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:07:30,672 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:07:30,672 INFO L87 Difference]: Start difference. First operand 321894 states and 1300178 transitions. Second operand 4 states. [2019-12-07 17:07:32,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:07:32,070 INFO L93 Difference]: Finished difference Result 334949 states and 1340993 transitions. [2019-12-07 17:07:32,070 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 17:07:32,070 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 19 [2019-12-07 17:07:32,070 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:07:36,501 INFO L225 Difference]: With dead ends: 334949 [2019-12-07 17:07:36,502 INFO L226 Difference]: Without dead ends: 334949 [2019-12-07 17:07:36,502 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:07:42,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 334949 states. [2019-12-07 17:07:46,592 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 334949 to 310982. [2019-12-07 17:07:46,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 310982 states. [2019-12-07 17:07:47,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 310982 states to 310982 states and 1255856 transitions. [2019-12-07 17:07:47,856 INFO L78 Accepts]: Start accepts. Automaton has 310982 states and 1255856 transitions. Word has length 19 [2019-12-07 17:07:47,856 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:07:47,856 INFO L462 AbstractCegarLoop]: Abstraction has 310982 states and 1255856 transitions. [2019-12-07 17:07:47,856 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:07:47,856 INFO L276 IsEmpty]: Start isEmpty. Operand 310982 states and 1255856 transitions. [2019-12-07 17:07:47,877 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2019-12-07 17:07:47,877 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:07:47,877 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:07:47,877 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:07:47,877 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:07:47,877 INFO L82 PathProgramCache]: Analyzing trace with hash -1380317719, now seen corresponding path program 1 times [2019-12-07 17:07:47,878 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:07:47,878 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1320034893] [2019-12-07 17:07:47,878 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:07:47,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:07:47,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:07:47,912 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1320034893] [2019-12-07 17:07:47,912 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:07:47,912 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:07:47,913 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [551322161] [2019-12-07 17:07:47,913 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:07:47,913 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:07:47,913 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:07:47,913 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:07:47,913 INFO L87 Difference]: Start difference. First operand 310982 states and 1255856 transitions. Second operand 4 states. [2019-12-07 17:07:48,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:07:48,210 INFO L93 Difference]: Finished difference Result 86910 states and 292872 transitions. [2019-12-07 17:07:48,210 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 17:07:48,211 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 20 [2019-12-07 17:07:48,211 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:07:48,316 INFO L225 Difference]: With dead ends: 86910 [2019-12-07 17:07:48,316 INFO L226 Difference]: Without dead ends: 65685 [2019-12-07 17:07:48,316 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:07:48,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65685 states. [2019-12-07 17:07:49,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65685 to 65573. [2019-12-07 17:07:49,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65573 states. [2019-12-07 17:07:49,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65573 states to 65573 states and 208360 transitions. [2019-12-07 17:07:49,792 INFO L78 Accepts]: Start accepts. Automaton has 65573 states and 208360 transitions. Word has length 20 [2019-12-07 17:07:49,792 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:07:49,792 INFO L462 AbstractCegarLoop]: Abstraction has 65573 states and 208360 transitions. [2019-12-07 17:07:49,792 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:07:49,792 INFO L276 IsEmpty]: Start isEmpty. Operand 65573 states and 208360 transitions. [2019-12-07 17:07:49,797 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 17:07:49,797 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:07:49,797 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:07:49,797 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:07:49,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:07:49,798 INFO L82 PathProgramCache]: Analyzing trace with hash 1141389468, now seen corresponding path program 1 times [2019-12-07 17:07:49,798 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:07:49,798 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203666982] [2019-12-07 17:07:49,798 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:07:49,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:07:49,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:07:49,832 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1203666982] [2019-12-07 17:07:49,832 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:07:49,832 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:07:49,833 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [224345055] [2019-12-07 17:07:49,833 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:07:49,833 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:07:49,833 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:07:49,833 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:07:49,833 INFO L87 Difference]: Start difference. First operand 65573 states and 208360 transitions. Second operand 5 states. [2019-12-07 17:07:50,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:07:50,291 INFO L93 Difference]: Finished difference Result 82355 states and 256944 transitions. [2019-12-07 17:07:50,291 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:07:50,291 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 22 [2019-12-07 17:07:50,291 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:07:50,404 INFO L225 Difference]: With dead ends: 82355 [2019-12-07 17:07:50,404 INFO L226 Difference]: Without dead ends: 82299 [2019-12-07 17:07:50,405 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:07:50,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82299 states. [2019-12-07 17:07:51,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82299 to 68425. [2019-12-07 17:07:51,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68425 states. [2019-12-07 17:07:51,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68425 states to 68425 states and 216910 transitions. [2019-12-07 17:07:51,592 INFO L78 Accepts]: Start accepts. Automaton has 68425 states and 216910 transitions. Word has length 22 [2019-12-07 17:07:51,592 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:07:51,592 INFO L462 AbstractCegarLoop]: Abstraction has 68425 states and 216910 transitions. [2019-12-07 17:07:51,592 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:07:51,592 INFO L276 IsEmpty]: Start isEmpty. Operand 68425 states and 216910 transitions. [2019-12-07 17:07:51,598 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 17:07:51,598 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:07:51,598 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:07:51,598 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:07:51,598 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:07:51,598 INFO L82 PathProgramCache]: Analyzing trace with hash 1541375313, now seen corresponding path program 1 times [2019-12-07 17:07:51,599 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:07:51,599 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1217078931] [2019-12-07 17:07:51,599 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:07:51,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:07:51,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:07:51,640 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1217078931] [2019-12-07 17:07:51,640 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:07:51,640 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:07:51,640 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2119155310] [2019-12-07 17:07:51,641 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:07:51,641 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:07:51,641 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:07:51,641 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:07:51,641 INFO L87 Difference]: Start difference. First operand 68425 states and 216910 transitions. Second operand 5 states. [2019-12-07 17:07:52,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:07:52,133 INFO L93 Difference]: Finished difference Result 85549 states and 267008 transitions. [2019-12-07 17:07:52,133 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:07:52,133 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 22 [2019-12-07 17:07:52,133 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:07:52,250 INFO L225 Difference]: With dead ends: 85549 [2019-12-07 17:07:52,250 INFO L226 Difference]: Without dead ends: 85493 [2019-12-07 17:07:52,251 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:07:52,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85493 states. [2019-12-07 17:07:53,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85493 to 68439. [2019-12-07 17:07:53,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68439 states. [2019-12-07 17:07:53,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68439 states to 68439 states and 216766 transitions. [2019-12-07 17:07:53,578 INFO L78 Accepts]: Start accepts. Automaton has 68439 states and 216766 transitions. Word has length 22 [2019-12-07 17:07:53,579 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:07:53,579 INFO L462 AbstractCegarLoop]: Abstraction has 68439 states and 216766 transitions. [2019-12-07 17:07:53,579 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:07:53,579 INFO L276 IsEmpty]: Start isEmpty. Operand 68439 states and 216766 transitions. [2019-12-07 17:07:53,592 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2019-12-07 17:07:53,592 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:07:53,592 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:07:53,592 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:07:53,592 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:07:53,592 INFO L82 PathProgramCache]: Analyzing trace with hash 2020314615, now seen corresponding path program 1 times [2019-12-07 17:07:53,593 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:07:53,593 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [717900888] [2019-12-07 17:07:53,593 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:07:53,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:07:53,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:07:53,626 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [717900888] [2019-12-07 17:07:53,626 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:07:53,626 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:07:53,626 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1810370073] [2019-12-07 17:07:53,627 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:07:53,627 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:07:53,627 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:07:53,627 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:07:53,627 INFO L87 Difference]: Start difference. First operand 68439 states and 216766 transitions. Second operand 5 states. [2019-12-07 17:07:54,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:07:54,029 INFO L93 Difference]: Finished difference Result 80305 states and 251119 transitions. [2019-12-07 17:07:54,030 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 17:07:54,030 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 26 [2019-12-07 17:07:54,030 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:07:54,138 INFO L225 Difference]: With dead ends: 80305 [2019-12-07 17:07:54,138 INFO L226 Difference]: Without dead ends: 80137 [2019-12-07 17:07:54,138 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:07:54,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80137 states. [2019-12-07 17:07:55,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80137 to 70638. [2019-12-07 17:07:55,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70638 states. [2019-12-07 17:07:55,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70638 states to 70638 states and 223242 transitions. [2019-12-07 17:07:55,366 INFO L78 Accepts]: Start accepts. Automaton has 70638 states and 223242 transitions. Word has length 26 [2019-12-07 17:07:55,367 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:07:55,367 INFO L462 AbstractCegarLoop]: Abstraction has 70638 states and 223242 transitions. [2019-12-07 17:07:55,367 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:07:55,367 INFO L276 IsEmpty]: Start isEmpty. Operand 70638 states and 223242 transitions. [2019-12-07 17:07:55,381 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2019-12-07 17:07:55,381 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:07:55,381 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:07:55,381 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:07:55,381 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:07:55,381 INFO L82 PathProgramCache]: Analyzing trace with hash 1824549582, now seen corresponding path program 1 times [2019-12-07 17:07:55,381 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:07:55,382 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [978908855] [2019-12-07 17:07:55,382 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:07:55,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:07:55,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:07:55,400 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [978908855] [2019-12-07 17:07:55,400 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:07:55,400 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:07:55,401 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1208346112] [2019-12-07 17:07:55,401 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:07:55,401 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:07:55,401 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:07:55,401 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:07:55,401 INFO L87 Difference]: Start difference. First operand 70638 states and 223242 transitions. Second operand 3 states. [2019-12-07 17:07:55,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:07:55,628 INFO L93 Difference]: Finished difference Result 84647 states and 260398 transitions. [2019-12-07 17:07:55,628 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:07:55,629 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 26 [2019-12-07 17:07:55,629 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:07:55,741 INFO L225 Difference]: With dead ends: 84647 [2019-12-07 17:07:55,741 INFO L226 Difference]: Without dead ends: 84647 [2019-12-07 17:07:55,742 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:07:56,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84647 states. [2019-12-07 17:07:56,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84647 to 70638. [2019-12-07 17:07:56,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70638 states. [2019-12-07 17:07:57,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70638 states to 70638 states and 217847 transitions. [2019-12-07 17:07:57,043 INFO L78 Accepts]: Start accepts. Automaton has 70638 states and 217847 transitions. Word has length 26 [2019-12-07 17:07:57,044 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:07:57,044 INFO L462 AbstractCegarLoop]: Abstraction has 70638 states and 217847 transitions. [2019-12-07 17:07:57,044 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:07:57,044 INFO L276 IsEmpty]: Start isEmpty. Operand 70638 states and 217847 transitions. [2019-12-07 17:07:57,065 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 17:07:57,065 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:07:57,065 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:07:57,065 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:07:57,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:07:57,065 INFO L82 PathProgramCache]: Analyzing trace with hash -77744514, now seen corresponding path program 1 times [2019-12-07 17:07:57,066 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:07:57,066 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1683109604] [2019-12-07 17:07:57,066 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:07:57,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:07:57,096 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:07:57,096 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1683109604] [2019-12-07 17:07:57,097 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:07:57,097 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:07:57,097 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1425049968] [2019-12-07 17:07:57,097 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:07:57,097 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:07:57,097 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:07:57,097 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:07:57,097 INFO L87 Difference]: Start difference. First operand 70638 states and 217847 transitions. Second operand 5 states. [2019-12-07 17:07:57,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:07:57,485 INFO L93 Difference]: Finished difference Result 82875 states and 253074 transitions. [2019-12-07 17:07:57,485 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 17:07:57,485 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2019-12-07 17:07:57,486 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:07:57,597 INFO L225 Difference]: With dead ends: 82875 [2019-12-07 17:07:57,597 INFO L226 Difference]: Without dead ends: 82691 [2019-12-07 17:07:57,597 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:07:57,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82691 states. [2019-12-07 17:07:58,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82691 to 70276. [2019-12-07 17:07:58,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70276 states. [2019-12-07 17:07:58,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70276 states to 70276 states and 216644 transitions. [2019-12-07 17:07:58,765 INFO L78 Accepts]: Start accepts. Automaton has 70276 states and 216644 transitions. Word has length 28 [2019-12-07 17:07:58,765 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:07:58,765 INFO L462 AbstractCegarLoop]: Abstraction has 70276 states and 216644 transitions. [2019-12-07 17:07:58,765 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:07:58,765 INFO L276 IsEmpty]: Start isEmpty. Operand 70276 states and 216644 transitions. [2019-12-07 17:07:58,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 17:07:58,791 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:07:58,791 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:07:58,791 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:07:58,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:07:58,791 INFO L82 PathProgramCache]: Analyzing trace with hash -604665634, now seen corresponding path program 1 times [2019-12-07 17:07:58,791 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:07:58,791 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635500490] [2019-12-07 17:07:58,792 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:07:58,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:07:58,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:07:58,838 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1635500490] [2019-12-07 17:07:58,839 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:07:58,839 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:07:58,839 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1538704302] [2019-12-07 17:07:58,839 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:07:58,839 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:07:58,840 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:07:58,840 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:07:58,840 INFO L87 Difference]: Start difference. First operand 70276 states and 216644 transitions. Second operand 5 states. [2019-12-07 17:07:58,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:07:58,945 INFO L93 Difference]: Finished difference Result 31139 states and 92090 transitions. [2019-12-07 17:07:58,946 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:07:58,946 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 31 [2019-12-07 17:07:58,946 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:07:58,978 INFO L225 Difference]: With dead ends: 31139 [2019-12-07 17:07:58,978 INFO L226 Difference]: Without dead ends: 27075 [2019-12-07 17:07:58,978 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:07:59,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27075 states. [2019-12-07 17:07:59,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27075 to 25552. [2019-12-07 17:07:59,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25552 states. [2019-12-07 17:07:59,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25552 states to 25552 states and 75390 transitions. [2019-12-07 17:07:59,424 INFO L78 Accepts]: Start accepts. Automaton has 25552 states and 75390 transitions. Word has length 31 [2019-12-07 17:07:59,424 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:07:59,424 INFO L462 AbstractCegarLoop]: Abstraction has 25552 states and 75390 transitions. [2019-12-07 17:07:59,424 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:07:59,425 INFO L276 IsEmpty]: Start isEmpty. Operand 25552 states and 75390 transitions. [2019-12-07 17:07:59,440 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-12-07 17:07:59,440 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:07:59,440 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:07:59,440 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:07:59,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:07:59,440 INFO L82 PathProgramCache]: Analyzing trace with hash 147507175, now seen corresponding path program 1 times [2019-12-07 17:07:59,441 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:07:59,441 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430128452] [2019-12-07 17:07:59,441 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:07:59,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:07:59,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:07:59,486 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [430128452] [2019-12-07 17:07:59,486 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:07:59,487 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:07:59,487 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [702032206] [2019-12-07 17:07:59,487 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:07:59,487 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:07:59,487 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:07:59,487 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:07:59,487 INFO L87 Difference]: Start difference. First operand 25552 states and 75390 transitions. Second operand 6 states. [2019-12-07 17:07:59,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:07:59,861 INFO L93 Difference]: Finished difference Result 30385 states and 88582 transitions. [2019-12-07 17:07:59,862 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:07:59,862 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 32 [2019-12-07 17:07:59,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:07:59,894 INFO L225 Difference]: With dead ends: 30385 [2019-12-07 17:07:59,894 INFO L226 Difference]: Without dead ends: 30129 [2019-12-07 17:07:59,894 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:07:59,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30129 states. [2019-12-07 17:08:00,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30129 to 25617. [2019-12-07 17:08:00,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25617 states. [2019-12-07 17:08:00,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25617 states to 25617 states and 75584 transitions. [2019-12-07 17:08:00,288 INFO L78 Accepts]: Start accepts. Automaton has 25617 states and 75584 transitions. Word has length 32 [2019-12-07 17:08:00,288 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:00,288 INFO L462 AbstractCegarLoop]: Abstraction has 25617 states and 75584 transitions. [2019-12-07 17:08:00,288 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:08:00,289 INFO L276 IsEmpty]: Start isEmpty. Operand 25617 states and 75584 transitions. [2019-12-07 17:08:00,305 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-12-07 17:08:00,305 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:00,305 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:00,305 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:00,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:00,305 INFO L82 PathProgramCache]: Analyzing trace with hash -1407969559, now seen corresponding path program 2 times [2019-12-07 17:08:00,305 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:00,305 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1171401026] [2019-12-07 17:08:00,306 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:00,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:00,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:00,340 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1171401026] [2019-12-07 17:08:00,340 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:00,340 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:08:00,340 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [780585389] [2019-12-07 17:08:00,341 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:08:00,341 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:00,341 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:08:00,341 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:08:00,341 INFO L87 Difference]: Start difference. First operand 25617 states and 75584 transitions. Second operand 6 states. [2019-12-07 17:08:00,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:00,753 INFO L93 Difference]: Finished difference Result 30678 states and 89487 transitions. [2019-12-07 17:08:00,754 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 17:08:00,754 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 32 [2019-12-07 17:08:00,754 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:00,785 INFO L225 Difference]: With dead ends: 30678 [2019-12-07 17:08:00,785 INFO L226 Difference]: Without dead ends: 30361 [2019-12-07 17:08:00,786 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=111, Unknown=0, NotChecked=0, Total=156 [2019-12-07 17:08:00,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30361 states. [2019-12-07 17:08:01,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30361 to 25584. [2019-12-07 17:08:01,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25584 states. [2019-12-07 17:08:01,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25584 states to 25584 states and 75501 transitions. [2019-12-07 17:08:01,179 INFO L78 Accepts]: Start accepts. Automaton has 25584 states and 75501 transitions. Word has length 32 [2019-12-07 17:08:01,179 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:01,179 INFO L462 AbstractCegarLoop]: Abstraction has 25584 states and 75501 transitions. [2019-12-07 17:08:01,179 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:08:01,179 INFO L276 IsEmpty]: Start isEmpty. Operand 25584 states and 75501 transitions. [2019-12-07 17:08:01,197 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 17:08:01,197 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:01,197 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:01,197 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:01,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:01,197 INFO L82 PathProgramCache]: Analyzing trace with hash 1247784206, now seen corresponding path program 1 times [2019-12-07 17:08:01,198 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:01,198 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1331227555] [2019-12-07 17:08:01,198 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:01,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:01,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:01,233 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1331227555] [2019-12-07 17:08:01,233 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:01,233 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:08:01,233 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [841325345] [2019-12-07 17:08:01,234 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:08:01,234 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:01,234 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:08:01,234 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:08:01,234 INFO L87 Difference]: Start difference. First operand 25584 states and 75501 transitions. Second operand 6 states. [2019-12-07 17:08:01,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:01,633 INFO L93 Difference]: Finished difference Result 29652 states and 86454 transitions. [2019-12-07 17:08:01,633 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 17:08:01,633 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 34 [2019-12-07 17:08:01,633 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:01,664 INFO L225 Difference]: With dead ends: 29652 [2019-12-07 17:08:01,664 INFO L226 Difference]: Without dead ends: 29277 [2019-12-07 17:08:01,664 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=111, Unknown=0, NotChecked=0, Total=156 [2019-12-07 17:08:01,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29277 states. [2019-12-07 17:08:02,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29277 to 24506. [2019-12-07 17:08:02,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24506 states. [2019-12-07 17:08:02,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24506 states to 24506 states and 72314 transitions. [2019-12-07 17:08:02,035 INFO L78 Accepts]: Start accepts. Automaton has 24506 states and 72314 transitions. Word has length 34 [2019-12-07 17:08:02,035 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:02,035 INFO L462 AbstractCegarLoop]: Abstraction has 24506 states and 72314 transitions. [2019-12-07 17:08:02,035 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:08:02,036 INFO L276 IsEmpty]: Start isEmpty. Operand 24506 states and 72314 transitions. [2019-12-07 17:08:02,055 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-12-07 17:08:02,055 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:02,055 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:02,055 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:02,056 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:02,056 INFO L82 PathProgramCache]: Analyzing trace with hash 280000667, now seen corresponding path program 1 times [2019-12-07 17:08:02,056 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:02,056 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1790365207] [2019-12-07 17:08:02,056 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:02,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:02,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:02,172 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1790365207] [2019-12-07 17:08:02,172 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:02,172 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:08:02,172 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [823024994] [2019-12-07 17:08:02,173 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:08:02,173 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:02,173 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:08:02,173 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:08:02,173 INFO L87 Difference]: Start difference. First operand 24506 states and 72314 transitions. Second operand 4 states. [2019-12-07 17:08:02,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:02,253 INFO L93 Difference]: Finished difference Result 33143 states and 98354 transitions. [2019-12-07 17:08:02,253 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 17:08:02,253 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 41 [2019-12-07 17:08:02,253 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:02,265 INFO L225 Difference]: With dead ends: 33143 [2019-12-07 17:08:02,265 INFO L226 Difference]: Without dead ends: 12296 [2019-12-07 17:08:02,266 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:08:02,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12296 states. [2019-12-07 17:08:02,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12296 to 12252. [2019-12-07 17:08:02,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12252 states. [2019-12-07 17:08:02,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12252 states to 12252 states and 35721 transitions. [2019-12-07 17:08:02,425 INFO L78 Accepts]: Start accepts. Automaton has 12252 states and 35721 transitions. Word has length 41 [2019-12-07 17:08:02,425 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:02,425 INFO L462 AbstractCegarLoop]: Abstraction has 12252 states and 35721 transitions. [2019-12-07 17:08:02,426 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:08:02,426 INFO L276 IsEmpty]: Start isEmpty. Operand 12252 states and 35721 transitions. [2019-12-07 17:08:02,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-12-07 17:08:02,434 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:02,434 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:02,435 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:02,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:02,435 INFO L82 PathProgramCache]: Analyzing trace with hash -2063356405, now seen corresponding path program 2 times [2019-12-07 17:08:02,435 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:02,435 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [824891288] [2019-12-07 17:08:02,435 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:02,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:02,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:02,470 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [824891288] [2019-12-07 17:08:02,470 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:02,470 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:08:02,471 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1121980306] [2019-12-07 17:08:02,471 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:08:02,471 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:02,471 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:08:02,471 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:08:02,471 INFO L87 Difference]: Start difference. First operand 12252 states and 35721 transitions. Second operand 3 states. [2019-12-07 17:08:02,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:02,513 INFO L93 Difference]: Finished difference Result 12252 states and 35109 transitions. [2019-12-07 17:08:02,513 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:08:02,514 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 41 [2019-12-07 17:08:02,514 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:02,526 INFO L225 Difference]: With dead ends: 12252 [2019-12-07 17:08:02,526 INFO L226 Difference]: Without dead ends: 12252 [2019-12-07 17:08:02,526 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:08:02,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12252 states. [2019-12-07 17:08:02,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12252 to 11990. [2019-12-07 17:08:02,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11990 states. [2019-12-07 17:08:02,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11990 states to 11990 states and 34388 transitions. [2019-12-07 17:08:02,690 INFO L78 Accepts]: Start accepts. Automaton has 11990 states and 34388 transitions. Word has length 41 [2019-12-07 17:08:02,690 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:02,690 INFO L462 AbstractCegarLoop]: Abstraction has 11990 states and 34388 transitions. [2019-12-07 17:08:02,690 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:08:02,690 INFO L276 IsEmpty]: Start isEmpty. Operand 11990 states and 34388 transitions. [2019-12-07 17:08:02,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-12-07 17:08:02,699 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:02,699 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:02,699 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:02,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:02,700 INFO L82 PathProgramCache]: Analyzing trace with hash 1498841336, now seen corresponding path program 1 times [2019-12-07 17:08:02,700 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:02,700 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1235171593] [2019-12-07 17:08:02,700 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:02,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:02,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:02,746 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1235171593] [2019-12-07 17:08:02,747 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:02,747 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:08:02,747 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1684410645] [2019-12-07 17:08:02,747 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:08:02,747 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:02,747 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:08:02,747 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:08:02,747 INFO L87 Difference]: Start difference. First operand 11990 states and 34388 transitions. Second operand 6 states. [2019-12-07 17:08:02,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:02,816 INFO L93 Difference]: Finished difference Result 11043 states and 32390 transitions. [2019-12-07 17:08:02,816 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:08:02,816 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 42 [2019-12-07 17:08:02,816 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:02,826 INFO L225 Difference]: With dead ends: 11043 [2019-12-07 17:08:02,826 INFO L226 Difference]: Without dead ends: 9390 [2019-12-07 17:08:02,826 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:08:02,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9390 states. [2019-12-07 17:08:02,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9390 to 9390. [2019-12-07 17:08:02,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9390 states. [2019-12-07 17:08:02,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9390 states to 9390 states and 28429 transitions. [2019-12-07 17:08:02,963 INFO L78 Accepts]: Start accepts. Automaton has 9390 states and 28429 transitions. Word has length 42 [2019-12-07 17:08:02,963 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:02,963 INFO L462 AbstractCegarLoop]: Abstraction has 9390 states and 28429 transitions. [2019-12-07 17:08:02,964 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:08:02,964 INFO L276 IsEmpty]: Start isEmpty. Operand 9390 states and 28429 transitions. [2019-12-07 17:08:02,971 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 17:08:02,971 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:02,971 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:02,971 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:02,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:02,971 INFO L82 PathProgramCache]: Analyzing trace with hash -224937897, now seen corresponding path program 1 times [2019-12-07 17:08:02,971 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:02,971 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1891869613] [2019-12-07 17:08:02,971 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:02,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:03,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:03,025 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1891869613] [2019-12-07 17:08:03,025 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:03,025 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:08:03,025 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [512817677] [2019-12-07 17:08:03,026 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:08:03,026 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:03,026 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:08:03,026 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:08:03,026 INFO L87 Difference]: Start difference. First operand 9390 states and 28429 transitions. Second operand 6 states. [2019-12-07 17:08:03,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:03,504 INFO L93 Difference]: Finished difference Result 17261 states and 51283 transitions. [2019-12-07 17:08:03,504 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 17:08:03,504 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 65 [2019-12-07 17:08:03,504 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:03,521 INFO L225 Difference]: With dead ends: 17261 [2019-12-07 17:08:03,522 INFO L226 Difference]: Without dead ends: 17261 [2019-12-07 17:08:03,522 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2019-12-07 17:08:03,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17261 states. [2019-12-07 17:08:03,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17261 to 13272. [2019-12-07 17:08:03,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13272 states. [2019-12-07 17:08:03,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13272 states to 13272 states and 40002 transitions. [2019-12-07 17:08:03,740 INFO L78 Accepts]: Start accepts. Automaton has 13272 states and 40002 transitions. Word has length 65 [2019-12-07 17:08:03,741 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:03,741 INFO L462 AbstractCegarLoop]: Abstraction has 13272 states and 40002 transitions. [2019-12-07 17:08:03,741 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:08:03,741 INFO L276 IsEmpty]: Start isEmpty. Operand 13272 states and 40002 transitions. [2019-12-07 17:08:03,752 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 17:08:03,752 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:03,753 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:03,753 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:03,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:03,753 INFO L82 PathProgramCache]: Analyzing trace with hash 1636974987, now seen corresponding path program 2 times [2019-12-07 17:08:03,753 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:03,753 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1693863887] [2019-12-07 17:08:03,753 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:03,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:03,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:03,830 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1693863887] [2019-12-07 17:08:03,830 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:03,830 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 17:08:03,830 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1881068568] [2019-12-07 17:08:03,830 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 17:08:03,830 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:03,831 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 17:08:03,831 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2019-12-07 17:08:03,831 INFO L87 Difference]: Start difference. First operand 13272 states and 40002 transitions. Second operand 8 states. [2019-12-07 17:08:05,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:05,365 INFO L93 Difference]: Finished difference Result 23530 states and 69197 transitions. [2019-12-07 17:08:05,366 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 17:08:05,366 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 65 [2019-12-07 17:08:05,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:05,388 INFO L225 Difference]: With dead ends: 23530 [2019-12-07 17:08:05,388 INFO L226 Difference]: Without dead ends: 23530 [2019-12-07 17:08:05,389 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=117, Unknown=0, NotChecked=0, Total=156 [2019-12-07 17:08:05,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23530 states. [2019-12-07 17:08:05,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23530 to 14184. [2019-12-07 17:08:05,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14184 states. [2019-12-07 17:08:05,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14184 states to 14184 states and 42654 transitions. [2019-12-07 17:08:05,648 INFO L78 Accepts]: Start accepts. Automaton has 14184 states and 42654 transitions. Word has length 65 [2019-12-07 17:08:05,648 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:05,648 INFO L462 AbstractCegarLoop]: Abstraction has 14184 states and 42654 transitions. [2019-12-07 17:08:05,648 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 17:08:05,648 INFO L276 IsEmpty]: Start isEmpty. Operand 14184 states and 42654 transitions. [2019-12-07 17:08:05,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 17:08:05,659 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:05,659 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:05,659 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:05,659 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:05,660 INFO L82 PathProgramCache]: Analyzing trace with hash -338575261, now seen corresponding path program 3 times [2019-12-07 17:08:05,660 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:05,660 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1439343664] [2019-12-07 17:08:05,660 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:05,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:05,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:05,741 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1439343664] [2019-12-07 17:08:05,741 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:05,741 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 17:08:05,741 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [421126493] [2019-12-07 17:08:05,741 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 17:08:05,742 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:05,742 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 17:08:05,742 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:08:05,742 INFO L87 Difference]: Start difference. First operand 14184 states and 42654 transitions. Second operand 9 states. [2019-12-07 17:08:07,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:07,621 INFO L93 Difference]: Finished difference Result 23893 states and 70438 transitions. [2019-12-07 17:08:07,622 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-12-07 17:08:07,622 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 65 [2019-12-07 17:08:07,622 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:07,656 INFO L225 Difference]: With dead ends: 23893 [2019-12-07 17:08:07,656 INFO L226 Difference]: Without dead ends: 23893 [2019-12-07 17:08:07,656 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 108 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=115, Invalid=485, Unknown=0, NotChecked=0, Total=600 [2019-12-07 17:08:07,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23893 states. [2019-12-07 17:08:07,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23893 to 13818. [2019-12-07 17:08:07,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13818 states. [2019-12-07 17:08:07,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13818 states to 13818 states and 41623 transitions. [2019-12-07 17:08:07,946 INFO L78 Accepts]: Start accepts. Automaton has 13818 states and 41623 transitions. Word has length 65 [2019-12-07 17:08:07,946 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:07,946 INFO L462 AbstractCegarLoop]: Abstraction has 13818 states and 41623 transitions. [2019-12-07 17:08:07,946 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 17:08:07,946 INFO L276 IsEmpty]: Start isEmpty. Operand 13818 states and 41623 transitions. [2019-12-07 17:08:07,958 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 17:08:07,958 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:07,958 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:07,958 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:07,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:07,958 INFO L82 PathProgramCache]: Analyzing trace with hash 1110190313, now seen corresponding path program 4 times [2019-12-07 17:08:07,958 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:07,959 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [319048405] [2019-12-07 17:08:07,959 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:07,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:07,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:07,995 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [319048405] [2019-12-07 17:08:07,995 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:07,995 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:08:07,995 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [282686923] [2019-12-07 17:08:07,995 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:08:07,996 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:07,996 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:08:07,996 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:08:07,996 INFO L87 Difference]: Start difference. First operand 13818 states and 41623 transitions. Second operand 3 states. [2019-12-07 17:08:08,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:08,063 INFO L93 Difference]: Finished difference Result 16584 states and 49988 transitions. [2019-12-07 17:08:08,064 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:08:08,064 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 17:08:08,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:08,080 INFO L225 Difference]: With dead ends: 16584 [2019-12-07 17:08:08,080 INFO L226 Difference]: Without dead ends: 16584 [2019-12-07 17:08:08,081 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:08:08,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16584 states. [2019-12-07 17:08:08,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16584 to 12289. [2019-12-07 17:08:08,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12289 states. [2019-12-07 17:08:08,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12289 states to 12289 states and 37337 transitions. [2019-12-07 17:08:08,282 INFO L78 Accepts]: Start accepts. Automaton has 12289 states and 37337 transitions. Word has length 65 [2019-12-07 17:08:08,282 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:08,282 INFO L462 AbstractCegarLoop]: Abstraction has 12289 states and 37337 transitions. [2019-12-07 17:08:08,282 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:08:08,282 INFO L276 IsEmpty]: Start isEmpty. Operand 12289 states and 37337 transitions. [2019-12-07 17:08:08,292 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:08:08,292 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:08,293 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:08,293 INFO L410 AbstractCegarLoop]: === Iteration 29 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:08,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:08,293 INFO L82 PathProgramCache]: Analyzing trace with hash -623699513, now seen corresponding path program 1 times [2019-12-07 17:08:08,293 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:08,293 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1477444641] [2019-12-07 17:08:08,293 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:08,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:08,424 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:08,425 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1477444641] [2019-12-07 17:08:08,425 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:08,425 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 17:08:08,425 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1655811888] [2019-12-07 17:08:08,425 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 17:08:08,425 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:08,425 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 17:08:08,425 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2019-12-07 17:08:08,426 INFO L87 Difference]: Start difference. First operand 12289 states and 37337 transitions. Second operand 10 states. [2019-12-07 17:08:10,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:10,635 INFO L93 Difference]: Finished difference Result 33044 states and 100385 transitions. [2019-12-07 17:08:10,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-12-07 17:08:10,636 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 66 [2019-12-07 17:08:10,636 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:10,667 INFO L225 Difference]: With dead ends: 33044 [2019-12-07 17:08:10,667 INFO L226 Difference]: Without dead ends: 22878 [2019-12-07 17:08:10,668 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 218 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=179, Invalid=813, Unknown=0, NotChecked=0, Total=992 [2019-12-07 17:08:10,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22878 states. [2019-12-07 17:08:10,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22878 to 15187. [2019-12-07 17:08:10,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15187 states. [2019-12-07 17:08:10,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15187 states to 15187 states and 45454 transitions. [2019-12-07 17:08:10,935 INFO L78 Accepts]: Start accepts. Automaton has 15187 states and 45454 transitions. Word has length 66 [2019-12-07 17:08:10,935 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:10,935 INFO L462 AbstractCegarLoop]: Abstraction has 15187 states and 45454 transitions. [2019-12-07 17:08:10,935 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 17:08:10,935 INFO L276 IsEmpty]: Start isEmpty. Operand 15187 states and 45454 transitions. [2019-12-07 17:08:10,948 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:08:10,948 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:10,948 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:10,948 INFO L410 AbstractCegarLoop]: === Iteration 30 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:10,948 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:10,949 INFO L82 PathProgramCache]: Analyzing trace with hash -1795841111, now seen corresponding path program 2 times [2019-12-07 17:08:10,949 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:10,949 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [443927041] [2019-12-07 17:08:10,949 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:10,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:11,070 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:11,070 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [443927041] [2019-12-07 17:08:11,070 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:11,070 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 17:08:11,070 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1394437607] [2019-12-07 17:08:11,071 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 17:08:11,071 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:11,071 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 17:08:11,071 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 17:08:11,071 INFO L87 Difference]: Start difference. First operand 15187 states and 45454 transitions. Second operand 11 states. [2019-12-07 17:08:12,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:12,682 INFO L93 Difference]: Finished difference Result 28215 states and 84250 transitions. [2019-12-07 17:08:12,682 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-12-07 17:08:12,683 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 66 [2019-12-07 17:08:12,683 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:12,705 INFO L225 Difference]: With dead ends: 28215 [2019-12-07 17:08:12,705 INFO L226 Difference]: Without dead ends: 23375 [2019-12-07 17:08:12,706 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 165 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=154, Invalid=716, Unknown=0, NotChecked=0, Total=870 [2019-12-07 17:08:12,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23375 states. [2019-12-07 17:08:12,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23375 to 15183. [2019-12-07 17:08:12,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15183 states. [2019-12-07 17:08:13,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15183 states to 15183 states and 45197 transitions. [2019-12-07 17:08:13,021 INFO L78 Accepts]: Start accepts. Automaton has 15183 states and 45197 transitions. Word has length 66 [2019-12-07 17:08:13,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:13,021 INFO L462 AbstractCegarLoop]: Abstraction has 15183 states and 45197 transitions. [2019-12-07 17:08:13,021 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 17:08:13,021 INFO L276 IsEmpty]: Start isEmpty. Operand 15183 states and 45197 transitions. [2019-12-07 17:08:13,032 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:08:13,032 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:13,032 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:13,033 INFO L410 AbstractCegarLoop]: === Iteration 31 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:13,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:13,033 INFO L82 PathProgramCache]: Analyzing trace with hash -131673981, now seen corresponding path program 3 times [2019-12-07 17:08:13,033 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:13,033 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1360995439] [2019-12-07 17:08:13,033 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:13,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:13,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:13,448 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1360995439] [2019-12-07 17:08:13,448 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:13,448 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 17:08:13,448 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [779217378] [2019-12-07 17:08:13,449 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 17:08:13,449 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:13,449 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 17:08:13,449 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=225, Unknown=0, NotChecked=0, Total=272 [2019-12-07 17:08:13,449 INFO L87 Difference]: Start difference. First operand 15183 states and 45197 transitions. Second operand 17 states. [2019-12-07 17:08:15,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:15,693 INFO L93 Difference]: Finished difference Result 23205 states and 67824 transitions. [2019-12-07 17:08:15,693 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-12-07 17:08:15,693 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 66 [2019-12-07 17:08:15,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:15,712 INFO L225 Difference]: With dead ends: 23205 [2019-12-07 17:08:15,712 INFO L226 Difference]: Without dead ends: 19207 [2019-12-07 17:08:15,712 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 0 SyntacticMatches, 3 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 312 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=311, Invalid=1329, Unknown=0, NotChecked=0, Total=1640 [2019-12-07 17:08:15,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19207 states. [2019-12-07 17:08:15,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19207 to 15945. [2019-12-07 17:08:15,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15945 states. [2019-12-07 17:08:15,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15945 states to 15945 states and 47256 transitions. [2019-12-07 17:08:15,944 INFO L78 Accepts]: Start accepts. Automaton has 15945 states and 47256 transitions. Word has length 66 [2019-12-07 17:08:15,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:15,944 INFO L462 AbstractCegarLoop]: Abstraction has 15945 states and 47256 transitions. [2019-12-07 17:08:15,944 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 17:08:15,944 INFO L276 IsEmpty]: Start isEmpty. Operand 15945 states and 47256 transitions. [2019-12-07 17:08:15,957 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:08:15,957 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:15,957 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:15,957 INFO L410 AbstractCegarLoop]: === Iteration 32 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:15,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:15,957 INFO L82 PathProgramCache]: Analyzing trace with hash 461520025, now seen corresponding path program 4 times [2019-12-07 17:08:15,957 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:15,958 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1153782752] [2019-12-07 17:08:15,958 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:15,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:16,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:16,290 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1153782752] [2019-12-07 17:08:16,290 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:16,291 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 17:08:16,291 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [469835089] [2019-12-07 17:08:16,291 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 17:08:16,291 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:16,291 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 17:08:16,291 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=199, Unknown=0, NotChecked=0, Total=240 [2019-12-07 17:08:16,292 INFO L87 Difference]: Start difference. First operand 15945 states and 47256 transitions. Second operand 16 states. [2019-12-07 17:08:26,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:26,366 INFO L93 Difference]: Finished difference Result 38327 states and 111104 transitions. [2019-12-07 17:08:26,367 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2019-12-07 17:08:26,367 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 66 [2019-12-07 17:08:26,367 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:26,412 INFO L225 Difference]: With dead ends: 38327 [2019-12-07 17:08:26,412 INFO L226 Difference]: Without dead ends: 33955 [2019-12-07 17:08:26,413 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 0 SyntacticMatches, 3 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1699 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=794, Invalid=4318, Unknown=0, NotChecked=0, Total=5112 [2019-12-07 17:08:26,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33955 states. [2019-12-07 17:08:26,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33955 to 16228. [2019-12-07 17:08:26,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16228 states. [2019-12-07 17:08:26,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16228 states to 16228 states and 47896 transitions. [2019-12-07 17:08:26,750 INFO L78 Accepts]: Start accepts. Automaton has 16228 states and 47896 transitions. Word has length 66 [2019-12-07 17:08:26,750 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:26,750 INFO L462 AbstractCegarLoop]: Abstraction has 16228 states and 47896 transitions. [2019-12-07 17:08:26,750 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 17:08:26,750 INFO L276 IsEmpty]: Start isEmpty. Operand 16228 states and 47896 transitions. [2019-12-07 17:08:26,763 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:08:26,763 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:26,763 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:26,763 INFO L410 AbstractCegarLoop]: === Iteration 33 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:26,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:26,764 INFO L82 PathProgramCache]: Analyzing trace with hash -2041557437, now seen corresponding path program 5 times [2019-12-07 17:08:26,764 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:26,764 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1349669738] [2019-12-07 17:08:26,764 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:26,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:27,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:27,060 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1349669738] [2019-12-07 17:08:27,060 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:27,060 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 17:08:27,060 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2118456634] [2019-12-07 17:08:27,061 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 17:08:27,061 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:27,061 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 17:08:27,061 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=197, Unknown=0, NotChecked=0, Total=240 [2019-12-07 17:08:27,061 INFO L87 Difference]: Start difference. First operand 16228 states and 47896 transitions. Second operand 16 states. [2019-12-07 17:08:31,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:31,404 INFO L93 Difference]: Finished difference Result 38742 states and 112566 transitions. [2019-12-07 17:08:31,405 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 80 states. [2019-12-07 17:08:31,405 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 66 [2019-12-07 17:08:31,405 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:31,446 INFO L225 Difference]: With dead ends: 38742 [2019-12-07 17:08:31,446 INFO L226 Difference]: Without dead ends: 31017 [2019-12-07 17:08:31,448 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 81 GetRequests, 0 SyntacticMatches, 3 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2141 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=984, Invalid=5336, Unknown=0, NotChecked=0, Total=6320 [2019-12-07 17:08:31,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31017 states. [2019-12-07 17:08:31,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31017 to 16364. [2019-12-07 17:08:31,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16364 states. [2019-12-07 17:08:31,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16364 states to 16364 states and 48278 transitions. [2019-12-07 17:08:31,819 INFO L78 Accepts]: Start accepts. Automaton has 16364 states and 48278 transitions. Word has length 66 [2019-12-07 17:08:31,819 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:31,819 INFO L462 AbstractCegarLoop]: Abstraction has 16364 states and 48278 transitions. [2019-12-07 17:08:31,819 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 17:08:31,819 INFO L276 IsEmpty]: Start isEmpty. Operand 16364 states and 48278 transitions. [2019-12-07 17:08:31,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:08:31,831 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:31,831 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:31,832 INFO L410 AbstractCegarLoop]: === Iteration 34 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:31,832 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:31,832 INFO L82 PathProgramCache]: Analyzing trace with hash -1958849865, now seen corresponding path program 6 times [2019-12-07 17:08:31,832 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:31,832 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781570858] [2019-12-07 17:08:31,832 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:31,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:32,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:32,235 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [781570858] [2019-12-07 17:08:32,235 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:32,235 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 17:08:32,235 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [265916417] [2019-12-07 17:08:32,236 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 17:08:32,236 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:32,236 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 17:08:32,236 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=231, Unknown=0, NotChecked=0, Total=272 [2019-12-07 17:08:32,236 INFO L87 Difference]: Start difference. First operand 16364 states and 48278 transitions. Second operand 17 states. [2019-12-07 17:08:36,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:36,615 INFO L93 Difference]: Finished difference Result 22344 states and 64835 transitions. [2019-12-07 17:08:36,616 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2019-12-07 17:08:36,616 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 66 [2019-12-07 17:08:36,616 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:36,646 INFO L225 Difference]: With dead ends: 22344 [2019-12-07 17:08:36,646 INFO L226 Difference]: Without dead ends: 21133 [2019-12-07 17:08:36,647 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 0 SyntacticMatches, 3 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 339 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=297, Invalid=1425, Unknown=0, NotChecked=0, Total=1722 [2019-12-07 17:08:36,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21133 states. [2019-12-07 17:08:36,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21133 to 16432. [2019-12-07 17:08:36,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16432 states. [2019-12-07 17:08:36,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16432 states to 16432 states and 48440 transitions. [2019-12-07 17:08:36,903 INFO L78 Accepts]: Start accepts. Automaton has 16432 states and 48440 transitions. Word has length 66 [2019-12-07 17:08:36,903 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:36,903 INFO L462 AbstractCegarLoop]: Abstraction has 16432 states and 48440 transitions. [2019-12-07 17:08:36,903 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 17:08:36,903 INFO L276 IsEmpty]: Start isEmpty. Operand 16432 states and 48440 transitions. [2019-12-07 17:08:36,916 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:08:36,917 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:36,917 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:36,917 INFO L410 AbstractCegarLoop]: === Iteration 35 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:36,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:36,917 INFO L82 PathProgramCache]: Analyzing trace with hash -458699383, now seen corresponding path program 7 times [2019-12-07 17:08:36,917 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:36,917 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280551870] [2019-12-07 17:08:36,917 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:36,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:37,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:37,258 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1280551870] [2019-12-07 17:08:37,258 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:37,258 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 17:08:37,258 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1881661053] [2019-12-07 17:08:37,258 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 17:08:37,258 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:37,259 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 17:08:37,259 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=224, Unknown=0, NotChecked=0, Total=272 [2019-12-07 17:08:37,259 INFO L87 Difference]: Start difference. First operand 16432 states and 48440 transitions. Second operand 17 states. [2019-12-07 17:08:45,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:45,162 INFO L93 Difference]: Finished difference Result 35180 states and 102219 transitions. [2019-12-07 17:08:45,162 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 75 states. [2019-12-07 17:08:45,162 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 66 [2019-12-07 17:08:45,163 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:45,192 INFO L225 Difference]: With dead ends: 35180 [2019-12-07 17:08:45,192 INFO L226 Difference]: Without dead ends: 33693 [2019-12-07 17:08:45,194 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 0 SyntacticMatches, 3 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1891 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=824, Invalid=4876, Unknown=0, NotChecked=0, Total=5700 [2019-12-07 17:08:45,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33693 states. [2019-12-07 17:08:45,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33693 to 16056. [2019-12-07 17:08:45,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16056 states. [2019-12-07 17:08:45,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16056 states to 16056 states and 47449 transitions. [2019-12-07 17:08:45,516 INFO L78 Accepts]: Start accepts. Automaton has 16056 states and 47449 transitions. Word has length 66 [2019-12-07 17:08:45,516 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:45,516 INFO L462 AbstractCegarLoop]: Abstraction has 16056 states and 47449 transitions. [2019-12-07 17:08:45,516 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 17:08:45,516 INFO L276 IsEmpty]: Start isEmpty. Operand 16056 states and 47449 transitions. [2019-12-07 17:08:45,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:08:45,529 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:45,529 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:45,529 INFO L410 AbstractCegarLoop]: === Iteration 36 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:45,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:45,529 INFO L82 PathProgramCache]: Analyzing trace with hash -1233581485, now seen corresponding path program 8 times [2019-12-07 17:08:45,529 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:45,529 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1650089694] [2019-12-07 17:08:45,529 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:45,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:45,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:45,783 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1650089694] [2019-12-07 17:08:45,783 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:45,783 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 17:08:45,783 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2039646985] [2019-12-07 17:08:45,783 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 17:08:45,783 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:45,784 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 17:08:45,784 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=176, Unknown=0, NotChecked=0, Total=210 [2019-12-07 17:08:45,784 INFO L87 Difference]: Start difference. First operand 16056 states and 47449 transitions. Second operand 15 states. [2019-12-07 17:08:50,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:50,778 INFO L93 Difference]: Finished difference Result 46809 states and 137475 transitions. [2019-12-07 17:08:50,778 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2019-12-07 17:08:50,778 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 66 [2019-12-07 17:08:50,778 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:50,821 INFO L225 Difference]: With dead ends: 46809 [2019-12-07 17:08:50,821 INFO L226 Difference]: Without dead ends: 41385 [2019-12-07 17:08:50,823 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 0 SyntacticMatches, 4 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2486 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1068, Invalid=6242, Unknown=0, NotChecked=0, Total=7310 [2019-12-07 17:08:50,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41385 states. [2019-12-07 17:08:51,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41385 to 19528. [2019-12-07 17:08:51,202 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19528 states. [2019-12-07 17:08:51,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19528 states to 19528 states and 57721 transitions. [2019-12-07 17:08:51,233 INFO L78 Accepts]: Start accepts. Automaton has 19528 states and 57721 transitions. Word has length 66 [2019-12-07 17:08:51,233 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:51,233 INFO L462 AbstractCegarLoop]: Abstraction has 19528 states and 57721 transitions. [2019-12-07 17:08:51,233 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 17:08:51,233 INFO L276 IsEmpty]: Start isEmpty. Operand 19528 states and 57721 transitions. [2019-12-07 17:08:51,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:08:51,249 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:51,250 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:51,250 INFO L410 AbstractCegarLoop]: === Iteration 37 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:51,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:51,250 INFO L82 PathProgramCache]: Analyzing trace with hash 1547917427, now seen corresponding path program 9 times [2019-12-07 17:08:51,250 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:51,250 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2113987275] [2019-12-07 17:08:51,250 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:51,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:51,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:51,496 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2113987275] [2019-12-07 17:08:51,496 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:51,496 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 17:08:51,496 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [673760693] [2019-12-07 17:08:51,496 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 17:08:51,496 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:51,496 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 17:08:51,497 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=172, Unknown=0, NotChecked=0, Total=210 [2019-12-07 17:08:51,497 INFO L87 Difference]: Start difference. First operand 19528 states and 57721 transitions. Second operand 15 states. [2019-12-07 17:08:56,601 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:56,602 INFO L93 Difference]: Finished difference Result 43790 states and 127458 transitions. [2019-12-07 17:08:56,602 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 74 states. [2019-12-07 17:08:56,603 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 66 [2019-12-07 17:08:56,603 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:56,649 INFO L225 Difference]: With dead ends: 43790 [2019-12-07 17:08:56,649 INFO L226 Difference]: Without dead ends: 33116 [2019-12-07 17:08:56,651 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 0 SyntacticMatches, 4 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1837 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=874, Invalid=4826, Unknown=0, NotChecked=0, Total=5700 [2019-12-07 17:08:56,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33116 states. [2019-12-07 17:08:56,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33116 to 15521. [2019-12-07 17:08:56,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15521 states. [2019-12-07 17:08:56,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15521 states to 15521 states and 46105 transitions. [2019-12-07 17:08:56,982 INFO L78 Accepts]: Start accepts. Automaton has 15521 states and 46105 transitions. Word has length 66 [2019-12-07 17:08:56,982 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:56,983 INFO L462 AbstractCegarLoop]: Abstraction has 15521 states and 46105 transitions. [2019-12-07 17:08:56,983 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 17:08:56,983 INFO L276 IsEmpty]: Start isEmpty. Operand 15521 states and 46105 transitions. [2019-12-07 17:08:56,996 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:08:56,996 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:56,996 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:56,996 INFO L410 AbstractCegarLoop]: === Iteration 38 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:56,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:56,996 INFO L82 PathProgramCache]: Analyzing trace with hash 1816995703, now seen corresponding path program 10 times [2019-12-07 17:08:56,996 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:56,996 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1762919880] [2019-12-07 17:08:56,997 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:57,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:57,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:57,120 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1762919880] [2019-12-07 17:08:57,120 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:57,120 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 17:08:57,120 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1058469246] [2019-12-07 17:08:57,120 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 17:08:57,120 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:57,120 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 17:08:57,121 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 17:08:57,121 INFO L87 Difference]: Start difference. First operand 15521 states and 46105 transitions. Second operand 11 states. [2019-12-07 17:08:58,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:58,549 INFO L93 Difference]: Finished difference Result 39051 states and 116875 transitions. [2019-12-07 17:08:58,550 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-12-07 17:08:58,550 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 66 [2019-12-07 17:08:58,550 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:58,584 INFO L225 Difference]: With dead ends: 39051 [2019-12-07 17:08:58,584 INFO L226 Difference]: Without dead ends: 32765 [2019-12-07 17:08:58,585 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 267 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=236, Invalid=954, Unknown=0, NotChecked=0, Total=1190 [2019-12-07 17:08:58,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32765 states. [2019-12-07 17:08:58,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32765 to 18330. [2019-12-07 17:08:58,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18330 states. [2019-12-07 17:08:58,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18330 states to 18330 states and 54466 transitions. [2019-12-07 17:08:58,939 INFO L78 Accepts]: Start accepts. Automaton has 18330 states and 54466 transitions. Word has length 66 [2019-12-07 17:08:58,939 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:08:58,939 INFO L462 AbstractCegarLoop]: Abstraction has 18330 states and 54466 transitions. [2019-12-07 17:08:58,939 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 17:08:58,939 INFO L276 IsEmpty]: Start isEmpty. Operand 18330 states and 54466 transitions. [2019-12-07 17:08:58,954 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:08:58,954 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:08:58,954 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:08:58,954 INFO L410 AbstractCegarLoop]: === Iteration 39 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:08:58,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:08:58,955 INFO L82 PathProgramCache]: Analyzing trace with hash -1224589181, now seen corresponding path program 11 times [2019-12-07 17:08:58,955 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:08:58,955 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [350801646] [2019-12-07 17:08:58,955 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:08:58,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:08:59,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:08:59,056 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [350801646] [2019-12-07 17:08:59,056 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:08:59,056 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 17:08:59,056 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [972297080] [2019-12-07 17:08:59,056 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 17:08:59,056 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:08:59,056 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 17:08:59,056 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 17:08:59,056 INFO L87 Difference]: Start difference. First operand 18330 states and 54466 transitions. Second operand 11 states. [2019-12-07 17:08:59,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:08:59,887 INFO L93 Difference]: Finished difference Result 32600 states and 96662 transitions. [2019-12-07 17:08:59,887 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 17:08:59,887 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 66 [2019-12-07 17:08:59,887 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:08:59,917 INFO L225 Difference]: With dead ends: 32600 [2019-12-07 17:08:59,917 INFO L226 Difference]: Without dead ends: 26628 [2019-12-07 17:08:59,918 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=122, Invalid=478, Unknown=0, NotChecked=0, Total=600 [2019-12-07 17:09:00,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26628 states. [2019-12-07 17:09:00,197 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26628 to 14360. [2019-12-07 17:09:00,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14360 states. [2019-12-07 17:09:00,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14360 states to 14360 states and 42825 transitions. [2019-12-07 17:09:00,219 INFO L78 Accepts]: Start accepts. Automaton has 14360 states and 42825 transitions. Word has length 66 [2019-12-07 17:09:00,219 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:09:00,219 INFO L462 AbstractCegarLoop]: Abstraction has 14360 states and 42825 transitions. [2019-12-07 17:09:00,219 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 17:09:00,219 INFO L276 IsEmpty]: Start isEmpty. Operand 14360 states and 42825 transitions. [2019-12-07 17:09:00,231 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:09:00,231 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:09:00,231 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:09:00,232 INFO L410 AbstractCegarLoop]: === Iteration 40 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:09:00,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:09:00,232 INFO L82 PathProgramCache]: Analyzing trace with hash -663530261, now seen corresponding path program 12 times [2019-12-07 17:09:00,232 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:09:00,232 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434240734] [2019-12-07 17:09:00,232 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:09:00,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:09:00,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:09:00,293 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:09:00,293 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 17:09:00,295 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [907] [907] ULTIMATE.startENTRY-->L840: Formula: (let ((.cse0 (store |v_#valid_71| 0 0))) (and (= v_~main$tmp_guard0~0_40 0) (= 0 v_~b$r_buff1_thd1~0_173) (= (store |v_#memory_int_26| |v_ULTIMATE.start_main_~#t873~0.base_30| (store (select |v_#memory_int_26| |v_ULTIMATE.start_main_~#t873~0.base_30|) |v_ULTIMATE.start_main_~#t873~0.offset_22| 0)) |v_#memory_int_25|) (= 0 v_~__unbuffered_p1_EAX~0_44) (= 0 v_~x~0_134) (= v_~z~0_33 0) (= 0 v_~weak$$choice0~0_14) (= |v_#NULL.offset_6| 0) (= 0 v_~b$r_buff0_thd2~0_158) (= v_~__unbuffered_p2_EBX~0_34 0) (= 0 v_~b$read_delayed~0_7) (= v_~a~0_13 0) (= v_~b$w_buff1~0_227 0) (< 0 |v_#StackHeapBarrier_19|) (= v_~weak$$choice2~0_143 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t873~0.base_30|)) (= 0 v_~b$r_buff0_thd3~0_397) (= v_~b$r_buff1_thd0~0_151 0) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t873~0.base_30| 4)) (= 0 v_~b$r_buff1_thd3~0_304) (= 0 v_~b$r_buff0_thd1~0_258) (= v_~__unbuffered_p1_EBX~0_44 0) (= v_~__unbuffered_cnt~0_127 0) (= v_~b$read_delayed_var~0.offset_7 0) (= v_~b~0_156 0) (= v_~y~0_27 0) (= v_~main$tmp_guard1~0_28 0) (= 0 |v_#NULL.base_6|) (= 0 v_~__unbuffered_p2_EAX~0_34) (= v_~b$mem_tmp~0_17 0) (= 0 v_~b$r_buff1_thd2~0_163) (= v_~b$flush_delayed~0_32 0) (= 0 v_~b$w_buff1_used~0_458) (= 0 v_~b$w_buff0_used~0_811) (< |v_#StackHeapBarrier_19| |v_ULTIMATE.start_main_~#t873~0.base_30|) (= 0 |v_ULTIMATE.start_main_~#t873~0.offset_22|) (= v_~b$r_buff0_thd0~0_167 0) (= 0 v_~b$w_buff0~0_363) (= 0 v_~b$read_delayed_var~0.base_7) (= |v_#valid_69| (store .cse0 |v_ULTIMATE.start_main_~#t873~0.base_30| 1)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_19|, #valid=|v_#valid_71|, #memory_int=|v_#memory_int_26|, #length=|v_#length_26|} OutVars{~b$r_buff0_thd3~0=v_~b$r_buff0_thd3~0_397, ~b$r_buff1_thd1~0=v_~b$r_buff1_thd1~0_173, ~b$read_delayed_var~0.offset=v_~b$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_64|, ULTIMATE.start_main_~#t875~0.offset=|v_ULTIMATE.start_main_~#t875~0.offset_15|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_38|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_38|, ~b$w_buff0_used~0=v_~b$w_buff0_used~0_811, ~a~0=v_~a~0_13, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_58|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_44, ULTIMATE.start_main_~#t873~0.base=|v_ULTIMATE.start_main_~#t873~0.base_30|, #length=|v_#length_25|, ~b$w_buff0~0=v_~b$w_buff0~0_363, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_34, ~b$r_buff0_thd0~0=v_~b$r_buff0_thd0~0_167, ~b$r_buff0_thd2~0=v_~b$r_buff0_thd2~0_158, ~b$mem_tmp~0=v_~b$mem_tmp~0_17, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_34, ~b$flush_delayed~0=v_~b$flush_delayed~0_32, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_8|, ~b$read_delayed~0=v_~b$read_delayed~0_7, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_19|, ~b$w_buff1~0=v_~b$w_buff1~0_227, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_127, ~x~0=v_~x~0_134, ~b$r_buff0_thd1~0=v_~b$r_buff0_thd1~0_258, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_28, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_105|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_42|, ULTIMATE.start_main_~#t874~0.offset=|v_ULTIMATE.start_main_~#t874~0.offset_15|, ~b$w_buff1_used~0=v_~b$w_buff1_used~0_458, ULTIMATE.start_main_~#t875~0.base=|v_ULTIMATE.start_main_~#t875~0.base_18|, ~y~0=v_~y~0_27, ~b$r_buff1_thd2~0=v_~b$r_buff1_thd2~0_163, ULTIMATE.start_main_~#t874~0.base=|v_ULTIMATE.start_main_~#t874~0.base_24|, ~b$r_buff1_thd0~0=v_~b$r_buff1_thd0~0_151, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_44, ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_19|, ULTIMATE.start_main_~#t873~0.offset=|v_ULTIMATE.start_main_~#t873~0.offset_22|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_8|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_40, #NULL.base=|v_#NULL.base_6|, ~b$read_delayed_var~0.base=v_~b$read_delayed_var~0.base_7, ~b~0=v_~b~0_156, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_22|, #valid=|v_#valid_69|, #memory_int=|v_#memory_int_25|, ~z~0=v_~z~0_33, ~weak$$choice2~0=v_~weak$$choice2~0_143, ~b$r_buff1_thd3~0=v_~b$r_buff1_thd3~0_304} AuxVars[] AssignedVars[~b$r_buff0_thd3~0, ~b$r_buff1_thd1~0, ~b$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_~#t875~0.offset, #NULL.offset, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite50, ~b$w_buff0_used~0, ~a~0, ULTIMATE.start_main_#t~ite52, ~__unbuffered_p1_EAX~0, ULTIMATE.start_main_~#t873~0.base, #length, ~b$w_buff0~0, ~__unbuffered_p2_EAX~0, ~b$r_buff0_thd0~0, ~b$r_buff0_thd2~0, ~b$mem_tmp~0, ~__unbuffered_p2_EBX~0, ~b$flush_delayed~0, ULTIMATE.start_main_#t~nondet45, ~b$read_delayed~0, ~weak$$choice0~0, ~b$w_buff1~0, ~__unbuffered_cnt~0, ~x~0, ~b$r_buff0_thd1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite51, ULTIMATE.start_main_~#t874~0.offset, ~b$w_buff1_used~0, ULTIMATE.start_main_~#t875~0.base, ~y~0, ~b$r_buff1_thd2~0, ULTIMATE.start_main_~#t874~0.base, ~b$r_buff1_thd0~0, ~__unbuffered_p1_EBX~0, ULTIMATE.start_main_#t~nondet46, ULTIMATE.start_main_~#t873~0.offset, ULTIMATE.start_main_#t~nondet44, ~main$tmp_guard0~0, #NULL.base, ~b$read_delayed_var~0.base, ~b~0, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~b$r_buff1_thd3~0] because there is no mapped edge [2019-12-07 17:09:00,296 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [881] [881] L840-1-->L842: Formula: (and (= 0 |v_ULTIMATE.start_main_~#t874~0.offset_10|) (= (store |v_#valid_39| |v_ULTIMATE.start_main_~#t874~0.base_12| 1) |v_#valid_38|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t874~0.base_12|) (not (= |v_ULTIMATE.start_main_~#t874~0.base_12| 0)) (= (store |v_#length_18| |v_ULTIMATE.start_main_~#t874~0.base_12| 4) |v_#length_17|) (= 0 (select |v_#valid_39| |v_ULTIMATE.start_main_~#t874~0.base_12|)) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t874~0.base_12| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t874~0.base_12|) |v_ULTIMATE.start_main_~#t874~0.offset_10| 1)) |v_#memory_int_17|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_18|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t874~0.base=|v_ULTIMATE.start_main_~#t874~0.base_12|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_~#t874~0.offset=|v_ULTIMATE.start_main_~#t874~0.offset_10|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_4|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_17|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t874~0.base, ULTIMATE.start_main_~#t874~0.offset, ULTIMATE.start_main_#t~nondet44, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 17:09:00,297 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [882] [882] L4-->L752: Formula: (and (= ~b$r_buff0_thd1~0_In-1817262039 ~b$r_buff1_thd1~0_Out-1817262039) (= ~b$r_buff1_thd3~0_Out-1817262039 ~b$r_buff0_thd3~0_In-1817262039) (= ~x~0_Out-1817262039 1) (not (= P0Thread1of1ForFork1___VERIFIER_assert_~expression_In-1817262039 0)) (= ~b$r_buff0_thd1~0_Out-1817262039 1) (= ~b$r_buff0_thd2~0_In-1817262039 ~b$r_buff1_thd2~0_Out-1817262039) (= ~b$r_buff0_thd0~0_In-1817262039 ~b$r_buff1_thd0~0_Out-1817262039)) InVars {~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_In-1817262039, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In-1817262039, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In-1817262039, P0Thread1of1ForFork1___VERIFIER_assert_~expression=P0Thread1of1ForFork1___VERIFIER_assert_~expression_In-1817262039, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In-1817262039} OutVars{~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_Out-1817262039, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In-1817262039, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In-1817262039, ~b$r_buff1_thd1~0=~b$r_buff1_thd1~0_Out-1817262039, ~b$r_buff1_thd0~0=~b$r_buff1_thd0~0_Out-1817262039, P0Thread1of1ForFork1___VERIFIER_assert_~expression=P0Thread1of1ForFork1___VERIFIER_assert_~expression_In-1817262039, ~b$r_buff1_thd2~0=~b$r_buff1_thd2~0_Out-1817262039, ~x~0=~x~0_Out-1817262039, ~b$r_buff1_thd3~0=~b$r_buff1_thd3~0_Out-1817262039, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In-1817262039} AuxVars[] AssignedVars[~b$r_buff0_thd1~0, ~b$r_buff1_thd1~0, ~b$r_buff1_thd0~0, ~b$r_buff1_thd2~0, ~x~0, ~b$r_buff1_thd3~0] because there is no mapped edge [2019-12-07 17:09:00,298 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [852] [852] L778-2-->L778-5: Formula: (let ((.cse0 (= (mod ~b$r_buff1_thd2~0_In-773681727 256) 0)) (.cse2 (= |P1Thread1of1ForFork2_#t~ite9_Out-773681727| |P1Thread1of1ForFork2_#t~ite10_Out-773681727|)) (.cse1 (= (mod ~b$w_buff1_used~0_In-773681727 256) 0))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite9_Out-773681727| ~b~0_In-773681727) .cse2) (and (= ~b$w_buff1~0_In-773681727 |P1Thread1of1ForFork2_#t~ite9_Out-773681727|) (not .cse0) .cse2 (not .cse1)))) InVars {~b$w_buff1_used~0=~b$w_buff1_used~0_In-773681727, ~b~0=~b~0_In-773681727, ~b$w_buff1~0=~b$w_buff1~0_In-773681727, ~b$r_buff1_thd2~0=~b$r_buff1_thd2~0_In-773681727} OutVars{P1Thread1of1ForFork2_#t~ite9=|P1Thread1of1ForFork2_#t~ite9_Out-773681727|, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-773681727, ~b~0=~b~0_In-773681727, P1Thread1of1ForFork2_#t~ite10=|P1Thread1of1ForFork2_#t~ite10_Out-773681727|, ~b$w_buff1~0=~b$w_buff1~0_In-773681727, ~b$r_buff1_thd2~0=~b$r_buff1_thd2~0_In-773681727} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite10] because there is no mapped edge [2019-12-07 17:09:00,298 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [839] [839] L753-->L753-2: Formula: (let ((.cse0 (= (mod ~b$r_buff0_thd1~0_In819873431 256) 0)) (.cse1 (= (mod ~b$w_buff0_used~0_In819873431 256) 0))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork1_#t~ite5_Out819873431| 0)) (and (or .cse0 .cse1) (= |P0Thread1of1ForFork1_#t~ite5_Out819873431| ~b$w_buff0_used~0_In819873431)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In819873431, ~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_In819873431} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In819873431, P0Thread1of1ForFork1_#t~ite5=|P0Thread1of1ForFork1_#t~ite5_Out819873431|, ~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_In819873431} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite5] because there is no mapped edge [2019-12-07 17:09:00,299 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [827] [827] L754-->L754-2: Formula: (let ((.cse0 (= (mod ~b$r_buff1_thd1~0_In-355899940 256) 0)) (.cse1 (= 0 (mod ~b$w_buff1_used~0_In-355899940 256))) (.cse3 (= 0 (mod ~b$r_buff0_thd1~0_In-355899940 256))) (.cse2 (= 0 (mod ~b$w_buff0_used~0_In-355899940 256)))) (or (and (= |P0Thread1of1ForFork1_#t~ite6_Out-355899940| ~b$w_buff1_used~0_In-355899940) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P0Thread1of1ForFork1_#t~ite6_Out-355899940| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In-355899940, ~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_In-355899940, ~b$r_buff1_thd1~0=~b$r_buff1_thd1~0_In-355899940, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-355899940} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In-355899940, ~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_In-355899940, ~b$r_buff1_thd1~0=~b$r_buff1_thd1~0_In-355899940, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-355899940, P0Thread1of1ForFork1_#t~ite6=|P0Thread1of1ForFork1_#t~ite6_Out-355899940|} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite6] because there is no mapped edge [2019-12-07 17:09:00,299 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [828] [828] L779-->L779-2: Formula: (let ((.cse0 (= (mod ~b$w_buff0_used~0_In-459326923 256) 0)) (.cse1 (= 0 (mod ~b$r_buff0_thd2~0_In-459326923 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite11_Out-459326923| 0) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite11_Out-459326923| ~b$w_buff0_used~0_In-459326923)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In-459326923, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In-459326923} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In-459326923, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In-459326923, P1Thread1of1ForFork2_#t~ite11=|P1Thread1of1ForFork2_#t~ite11_Out-459326923|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-12-07 17:09:00,299 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [850] [850] L755-->L756: Formula: (let ((.cse0 (= 0 (mod ~b$r_buff0_thd1~0_In862586898 256))) (.cse2 (= (mod ~b$w_buff0_used~0_In862586898 256) 0)) (.cse1 (= ~b$r_buff0_thd1~0_In862586898 ~b$r_buff0_thd1~0_Out862586898))) (or (and .cse0 .cse1) (and (= 0 ~b$r_buff0_thd1~0_Out862586898) (not .cse2) (not .cse0)) (and .cse2 .cse1))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In862586898, ~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_In862586898} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In862586898, ~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_Out862586898, P0Thread1of1ForFork1_#t~ite7=|P0Thread1of1ForFork1_#t~ite7_Out862586898|} AuxVars[] AssignedVars[~b$r_buff0_thd1~0, P0Thread1of1ForFork1_#t~ite7] because there is no mapped edge [2019-12-07 17:09:00,299 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [835] [835] L756-->L756-2: Formula: (let ((.cse3 (= 0 (mod ~b$r_buff0_thd1~0_In1069875815 256))) (.cse2 (= 0 (mod ~b$w_buff0_used~0_In1069875815 256))) (.cse0 (= (mod ~b$w_buff1_used~0_In1069875815 256) 0)) (.cse1 (= (mod ~b$r_buff1_thd1~0_In1069875815 256) 0))) (or (and (= |P0Thread1of1ForFork1_#t~ite8_Out1069875815| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse0 .cse1) (= |P0Thread1of1ForFork1_#t~ite8_Out1069875815| ~b$r_buff1_thd1~0_In1069875815)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In1069875815, ~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_In1069875815, ~b$r_buff1_thd1~0=~b$r_buff1_thd1~0_In1069875815, ~b$w_buff1_used~0=~b$w_buff1_used~0_In1069875815} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In1069875815, ~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_In1069875815, ~b$r_buff1_thd1~0=~b$r_buff1_thd1~0_In1069875815, P0Thread1of1ForFork1_#t~ite8=|P0Thread1of1ForFork1_#t~ite8_Out1069875815|, ~b$w_buff1_used~0=~b$w_buff1_used~0_In1069875815} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 17:09:00,299 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [880] [880] L756-2-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork1_#res.base_3|) (= v_~b$r_buff1_thd1~0_107 |v_P0Thread1of1ForFork1_#t~ite8_46|) (= 0 |v_P0Thread1of1ForFork1_#res.offset_3|) (= (+ v_~__unbuffered_cnt~0_87 1) v_~__unbuffered_cnt~0_86)) InVars {P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_46|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_87} OutVars{~b$r_buff1_thd1~0=v_~b$r_buff1_thd1~0_107, P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_45|, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_3|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_86} AuxVars[] AssignedVars[~b$r_buff1_thd1~0, P0Thread1of1ForFork1_#t~ite8, P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 17:09:00,299 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [878] [878] L842-1-->L844: Formula: (and (= (store |v_#length_16| |v_ULTIMATE.start_main_~#t875~0.base_12| 4) |v_#length_15|) (= 0 |v_ULTIMATE.start_main_~#t875~0.offset_10|) (not (= 0 |v_ULTIMATE.start_main_~#t875~0.base_12|)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t875~0.base_12|) (= 0 (select |v_#valid_37| |v_ULTIMATE.start_main_~#t875~0.base_12|)) (= |v_#valid_36| (store |v_#valid_37| |v_ULTIMATE.start_main_~#t875~0.base_12| 1)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t875~0.base_12| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t875~0.base_12|) |v_ULTIMATE.start_main_~#t875~0.offset_10| 2)) |v_#memory_int_15|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_37|, #memory_int=|v_#memory_int_16|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t875~0.base=|v_ULTIMATE.start_main_~#t875~0.base_12|, #valid=|v_#valid_36|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_4|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_~#t875~0.offset=|v_ULTIMATE.start_main_~#t875~0.offset_10|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t875~0.base, #valid, ULTIMATE.start_main_#t~nondet45, #memory_int, ULTIMATE.start_main_~#t875~0.offset, #length] because there is no mapped edge [2019-12-07 17:09:00,303 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [883] [883] L809-->L809-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-631029246 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite29_In-631029246| |P2Thread1of1ForFork0_#t~ite29_Out-631029246|) (= ~b$w_buff1_used~0_In-631029246 |P2Thread1of1ForFork0_#t~ite30_Out-631029246|) (not .cse0)) (and (= ~b$w_buff1_used~0_In-631029246 |P2Thread1of1ForFork0_#t~ite29_Out-631029246|) (let ((.cse1 (= (mod ~b$r_buff0_thd3~0_In-631029246 256) 0))) (or (and (= (mod ~b$w_buff1_used~0_In-631029246 256) 0) .cse1) (and (= (mod ~b$r_buff1_thd3~0_In-631029246 256) 0) .cse1) (= (mod ~b$w_buff0_used~0_In-631029246 256) 0))) (= |P2Thread1of1ForFork0_#t~ite30_Out-631029246| |P2Thread1of1ForFork0_#t~ite29_Out-631029246|) .cse0))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In-631029246, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In-631029246, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-631029246, ~weak$$choice2~0=~weak$$choice2~0_In-631029246, P2Thread1of1ForFork0_#t~ite29=|P2Thread1of1ForFork0_#t~ite29_In-631029246|, ~b$r_buff1_thd3~0=~b$r_buff1_thd3~0_In-631029246} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In-631029246, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In-631029246, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-631029246, P2Thread1of1ForFork0_#t~ite30=|P2Thread1of1ForFork0_#t~ite30_Out-631029246|, P2Thread1of1ForFork0_#t~ite29=|P2Thread1of1ForFork0_#t~ite29_Out-631029246|, ~weak$$choice2~0=~weak$$choice2~0_In-631029246, ~b$r_buff1_thd3~0=~b$r_buff1_thd3~0_In-631029246} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite30, P2Thread1of1ForFork0_#t~ite29] because there is no mapped edge [2019-12-07 17:09:00,303 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [897] [897] L810-->L811-8: Formula: (and (= |v_P2Thread1of1ForFork0_#t~ite36_36| v_~b$r_buff1_thd3~0_279) (= v_~b$r_buff0_thd3~0_376 v_~b$r_buff0_thd3~0_375) (not (= 0 (mod v_~weak$$choice2~0_126 256))) (= |v_P2Thread1of1ForFork0_#t~ite34_29| |v_P2Thread1of1ForFork0_#t~ite34_28|) (= |v_P2Thread1of1ForFork0_#t~ite35_33| |v_P2Thread1of1ForFork0_#t~ite35_32|)) InVars {~b$r_buff0_thd3~0=v_~b$r_buff0_thd3~0_376, P2Thread1of1ForFork0_#t~ite35=|v_P2Thread1of1ForFork0_#t~ite35_33|, P2Thread1of1ForFork0_#t~ite34=|v_P2Thread1of1ForFork0_#t~ite34_29|, ~weak$$choice2~0=v_~weak$$choice2~0_126, ~b$r_buff1_thd3~0=v_~b$r_buff1_thd3~0_279} OutVars{P2Thread1of1ForFork0_#t~ite36=|v_P2Thread1of1ForFork0_#t~ite36_36|, ~b$r_buff0_thd3~0=v_~b$r_buff0_thd3~0_375, P2Thread1of1ForFork0_#t~ite33=|v_P2Thread1of1ForFork0_#t~ite33_23|, P2Thread1of1ForFork0_#t~ite32=|v_P2Thread1of1ForFork0_#t~ite32_32|, P2Thread1of1ForFork0_#t~ite35=|v_P2Thread1of1ForFork0_#t~ite35_32|, P2Thread1of1ForFork0_#t~ite34=|v_P2Thread1of1ForFork0_#t~ite34_28|, P2Thread1of1ForFork0_#t~ite31=|v_P2Thread1of1ForFork0_#t~ite31_25|, ~weak$$choice2~0=v_~weak$$choice2~0_126, ~b$r_buff1_thd3~0=v_~b$r_buff1_thd3~0_279} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite36, ~b$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite33, P2Thread1of1ForFork0_#t~ite32, P2Thread1of1ForFork0_#t~ite35, P2Thread1of1ForFork0_#t~ite34, P2Thread1of1ForFork0_#t~ite31] because there is no mapped edge [2019-12-07 17:09:00,303 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L813-->L817: Formula: (and (= v_~b$flush_delayed~0_6 0) (not (= (mod v_~b$flush_delayed~0_7 256) 0)) (= v_~b~0_16 v_~b$mem_tmp~0_4)) InVars {~b$mem_tmp~0=v_~b$mem_tmp~0_4, ~b$flush_delayed~0=v_~b$flush_delayed~0_7} OutVars{P2Thread1of1ForFork0_#t~ite37=|v_P2Thread1of1ForFork0_#t~ite37_5|, ~b$mem_tmp~0=v_~b$mem_tmp~0_4, ~b~0=v_~b~0_16, ~b$flush_delayed~0=v_~b$flush_delayed~0_6} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite37, ~b~0, ~b$flush_delayed~0] because there is no mapped edge [2019-12-07 17:09:00,304 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [847] [847] L817-2-->L817-5: Formula: (let ((.cse0 (= |P2Thread1of1ForFork0_#t~ite38_Out-358957499| |P2Thread1of1ForFork0_#t~ite39_Out-358957499|)) (.cse1 (= 0 (mod ~b$w_buff1_used~0_In-358957499 256))) (.cse2 (= 0 (mod ~b$r_buff1_thd3~0_In-358957499 256)))) (or (and .cse0 (= ~b$w_buff1~0_In-358957499 |P2Thread1of1ForFork0_#t~ite38_Out-358957499|) (not .cse1) (not .cse2)) (and .cse0 (= |P2Thread1of1ForFork0_#t~ite38_Out-358957499| ~b~0_In-358957499) (or .cse1 .cse2)))) InVars {~b$w_buff1_used~0=~b$w_buff1_used~0_In-358957499, ~b~0=~b~0_In-358957499, ~b$w_buff1~0=~b$w_buff1~0_In-358957499, ~b$r_buff1_thd3~0=~b$r_buff1_thd3~0_In-358957499} OutVars{P2Thread1of1ForFork0_#t~ite39=|P2Thread1of1ForFork0_#t~ite39_Out-358957499|, P2Thread1of1ForFork0_#t~ite38=|P2Thread1of1ForFork0_#t~ite38_Out-358957499|, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-358957499, ~b~0=~b~0_In-358957499, ~b$w_buff1~0=~b$w_buff1~0_In-358957499, ~b$r_buff1_thd3~0=~b$r_buff1_thd3~0_In-358957499} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite39, P2Thread1of1ForFork0_#t~ite38] because there is no mapped edge [2019-12-07 17:09:00,304 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L818-->L818-2: Formula: (let ((.cse1 (= 0 (mod ~b$w_buff0_used~0_In683024697 256))) (.cse0 (= 0 (mod ~b$r_buff0_thd3~0_In683024697 256)))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite40_Out683024697| ~b$w_buff0_used~0_In683024697)) (and (not .cse1) (not .cse0) (= |P2Thread1of1ForFork0_#t~ite40_Out683024697| 0)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In683024697, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In683024697} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In683024697, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In683024697, P2Thread1of1ForFork0_#t~ite40=|P2Thread1of1ForFork0_#t~ite40_Out683024697|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite40] because there is no mapped edge [2019-12-07 17:09:00,305 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [831] [831] L819-->L819-2: Formula: (let ((.cse2 (= 0 (mod ~b$w_buff1_used~0_In1314199592 256))) (.cse3 (= (mod ~b$r_buff1_thd3~0_In1314199592 256) 0)) (.cse1 (= (mod ~b$r_buff0_thd3~0_In1314199592 256) 0)) (.cse0 (= 0 (mod ~b$w_buff0_used~0_In1314199592 256)))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite41_Out1314199592| ~b$w_buff1_used~0_In1314199592) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |P2Thread1of1ForFork0_#t~ite41_Out1314199592| 0)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In1314199592, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In1314199592, ~b$w_buff1_used~0=~b$w_buff1_used~0_In1314199592, ~b$r_buff1_thd3~0=~b$r_buff1_thd3~0_In1314199592} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In1314199592, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In1314199592, ~b$w_buff1_used~0=~b$w_buff1_used~0_In1314199592, P2Thread1of1ForFork0_#t~ite41=|P2Thread1of1ForFork0_#t~ite41_Out1314199592|, ~b$r_buff1_thd3~0=~b$r_buff1_thd3~0_In1314199592} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite41] because there is no mapped edge [2019-12-07 17:09:00,305 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [842] [842] L820-->L820-2: Formula: (let ((.cse1 (= (mod ~b$r_buff0_thd3~0_In-959911550 256) 0)) (.cse0 (= 0 (mod ~b$w_buff0_used~0_In-959911550 256)))) (or (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite42_Out-959911550| 0) (not .cse1)) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork0_#t~ite42_Out-959911550| ~b$r_buff0_thd3~0_In-959911550)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In-959911550, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In-959911550} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In-959911550, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In-959911550, P2Thread1of1ForFork0_#t~ite42=|P2Thread1of1ForFork0_#t~ite42_Out-959911550|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite42] because there is no mapped edge [2019-12-07 17:09:00,305 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L821-->L821-2: Formula: (let ((.cse0 (= (mod ~b$r_buff0_thd3~0_In-316149769 256) 0)) (.cse1 (= (mod ~b$w_buff0_used~0_In-316149769 256) 0)) (.cse3 (= (mod ~b$w_buff1_used~0_In-316149769 256) 0)) (.cse2 (= (mod ~b$r_buff1_thd3~0_In-316149769 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite43_Out-316149769| ~b$r_buff1_thd3~0_In-316149769) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite43_Out-316149769|) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In-316149769, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In-316149769, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-316149769, ~b$r_buff1_thd3~0=~b$r_buff1_thd3~0_In-316149769} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In-316149769, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In-316149769, P2Thread1of1ForFork0_#t~ite43=|P2Thread1of1ForFork0_#t~ite43_Out-316149769|, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-316149769, ~b$r_buff1_thd3~0=~b$r_buff1_thd3~0_In-316149769} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite43] because there is no mapped edge [2019-12-07 17:09:00,306 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L821-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= (+ v_~__unbuffered_cnt~0_56 1) v_~__unbuffered_cnt~0_55) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite43_34| v_~b$r_buff1_thd3~0_101)) InVars {P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56} OutVars{P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_33|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55, ~b$r_buff1_thd3~0=v_~b$r_buff1_thd3~0_101, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#res.base, P2Thread1of1ForFork0_#t~ite43, ~__unbuffered_cnt~0, ~b$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 17:09:00,306 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [840] [840] L780-->L780-2: Formula: (let ((.cse2 (= 0 (mod ~b$r_buff1_thd2~0_In1478108249 256))) (.cse3 (= (mod ~b$w_buff1_used~0_In1478108249 256) 0)) (.cse1 (= (mod ~b$r_buff0_thd2~0_In1478108249 256) 0)) (.cse0 (= 0 (mod ~b$w_buff0_used~0_In1478108249 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite12_Out1478108249|)) (and (= ~b$w_buff1_used~0_In1478108249 |P1Thread1of1ForFork2_#t~ite12_Out1478108249|) (or .cse2 .cse3) (or .cse1 .cse0)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In1478108249, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In1478108249, ~b$w_buff1_used~0=~b$w_buff1_used~0_In1478108249, ~b$r_buff1_thd2~0=~b$r_buff1_thd2~0_In1478108249} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In1478108249, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In1478108249, ~b$w_buff1_used~0=~b$w_buff1_used~0_In1478108249, P1Thread1of1ForFork2_#t~ite12=|P1Thread1of1ForFork2_#t~ite12_Out1478108249|, ~b$r_buff1_thd2~0=~b$r_buff1_thd2~0_In1478108249} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite12] because there is no mapped edge [2019-12-07 17:09:00,306 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [836] [836] L781-->L781-2: Formula: (let ((.cse1 (= 0 (mod ~b$w_buff0_used~0_In-887798388 256))) (.cse0 (= (mod ~b$r_buff0_thd2~0_In-887798388 256) 0))) (or (and (= ~b$r_buff0_thd2~0_In-887798388 |P1Thread1of1ForFork2_#t~ite13_Out-887798388|) (or .cse0 .cse1)) (and (not .cse1) (= 0 |P1Thread1of1ForFork2_#t~ite13_Out-887798388|) (not .cse0)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In-887798388, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In-887798388} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In-887798388, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In-887798388, P1Thread1of1ForFork2_#t~ite13=|P1Thread1of1ForFork2_#t~ite13_Out-887798388|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite13] because there is no mapped edge [2019-12-07 17:09:00,307 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L782-->L782-2: Formula: (let ((.cse1 (= (mod ~b$w_buff0_used~0_In888541559 256) 0)) (.cse0 (= (mod ~b$r_buff0_thd2~0_In888541559 256) 0)) (.cse2 (= 0 (mod ~b$w_buff1_used~0_In888541559 256))) (.cse3 (= (mod ~b$r_buff1_thd2~0_In888541559 256) 0))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite14_Out888541559| ~b$r_buff1_thd2~0_In888541559) (or .cse2 .cse3)) (and (= |P1Thread1of1ForFork2_#t~ite14_Out888541559| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In888541559, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In888541559, ~b$w_buff1_used~0=~b$w_buff1_used~0_In888541559, ~b$r_buff1_thd2~0=~b$r_buff1_thd2~0_In888541559} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In888541559, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In888541559, ~b$w_buff1_used~0=~b$w_buff1_used~0_In888541559, P1Thread1of1ForFork2_#t~ite14=|P1Thread1of1ForFork2_#t~ite14_Out888541559|, ~b$r_buff1_thd2~0=~b$r_buff1_thd2~0_In888541559} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite14] because there is no mapped edge [2019-12-07 17:09:00,307 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [872] [872] L782-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= v_~b$r_buff1_thd2~0_91 |v_P1Thread1of1ForFork2_#t~ite14_50|) (= (+ v_~__unbuffered_cnt~0_81 1) v_~__unbuffered_cnt~0_80)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_81, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_50|} OutVars{P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_80, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_49|, ~b$r_buff1_thd2~0=v_~b$r_buff1_thd2~0_91, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#t~ite14, ~b$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 17:09:00,307 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L848-->L850-2: Formula: (and (or (= 0 (mod v_~b$w_buff0_used~0_159 256)) (= 0 (mod v_~b$r_buff0_thd0~0_23 256))) (not (= 0 (mod v_~main$tmp_guard0~0_5 256)))) InVars {~b$w_buff0_used~0=v_~b$w_buff0_used~0_159, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_5, ~b$r_buff0_thd0~0=v_~b$r_buff0_thd0~0_23} OutVars{~b$w_buff0_used~0=v_~b$w_buff0_used~0_159, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_5, ~b$r_buff0_thd0~0=v_~b$r_buff0_thd0~0_23} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 17:09:00,307 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [848] [848] L850-2-->L850-4: Formula: (let ((.cse1 (= (mod ~b$w_buff1_used~0_In-2089564303 256) 0)) (.cse0 (= 0 (mod ~b$r_buff1_thd0~0_In-2089564303 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite47_Out-2089564303| ~b$w_buff1~0_In-2089564303) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite47_Out-2089564303| ~b~0_In-2089564303) (or .cse1 .cse0)))) InVars {~b$r_buff1_thd0~0=~b$r_buff1_thd0~0_In-2089564303, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-2089564303, ~b~0=~b~0_In-2089564303, ~b$w_buff1~0=~b$w_buff1~0_In-2089564303} OutVars{~b$r_buff1_thd0~0=~b$r_buff1_thd0~0_In-2089564303, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-2089564303, ~b~0=~b~0_In-2089564303, ULTIMATE.start_main_#t~ite47=|ULTIMATE.start_main_#t~ite47_Out-2089564303|, ~b$w_buff1~0=~b$w_buff1~0_In-2089564303} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] because there is no mapped edge [2019-12-07 17:09:00,307 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L850-4-->L851: Formula: (= v_~b~0_28 |v_ULTIMATE.start_main_#t~ite47_9|) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_9|} OutVars{~b~0=v_~b~0_28, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_8|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_12|} AuxVars[] AssignedVars[~b~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 17:09:00,307 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [849] [849] L851-->L851-2: Formula: (let ((.cse0 (= (mod ~b$w_buff0_used~0_In-1695741204 256) 0)) (.cse1 (= 0 (mod ~b$r_buff0_thd0~0_In-1695741204 256)))) (or (and (= |ULTIMATE.start_main_#t~ite49_Out-1695741204| 0) (not .cse0) (not .cse1)) (and (= ~b$w_buff0_used~0_In-1695741204 |ULTIMATE.start_main_#t~ite49_Out-1695741204|) (or .cse0 .cse1)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In-1695741204, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In-1695741204} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In-1695741204, ULTIMATE.start_main_#t~ite49=|ULTIMATE.start_main_#t~ite49_Out-1695741204|, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In-1695741204} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite49] because there is no mapped edge [2019-12-07 17:09:00,308 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L852-->L852-2: Formula: (let ((.cse0 (= 0 (mod ~b$w_buff0_used~0_In-1685809702 256))) (.cse1 (= (mod ~b$r_buff0_thd0~0_In-1685809702 256) 0)) (.cse2 (= 0 (mod ~b$r_buff1_thd0~0_In-1685809702 256))) (.cse3 (= 0 (mod ~b$w_buff1_used~0_In-1685809702 256)))) (or (and (or .cse0 .cse1) (= ~b$w_buff1_used~0_In-1685809702 |ULTIMATE.start_main_#t~ite50_Out-1685809702|) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite50_Out-1685809702| 0)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In-1685809702, ~b$r_buff1_thd0~0=~b$r_buff1_thd0~0_In-1685809702, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-1685809702, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In-1685809702} OutVars{ULTIMATE.start_main_#t~ite50=|ULTIMATE.start_main_#t~ite50_Out-1685809702|, ~b$w_buff0_used~0=~b$w_buff0_used~0_In-1685809702, ~b$r_buff1_thd0~0=~b$r_buff1_thd0~0_In-1685809702, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-1685809702, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In-1685809702} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite50] because there is no mapped edge [2019-12-07 17:09:00,308 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [837] [837] L853-->L853-2: Formula: (let ((.cse0 (= 0 (mod ~b$r_buff0_thd0~0_In-1379275990 256))) (.cse1 (= (mod ~b$w_buff0_used~0_In-1379275990 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite51_Out-1379275990|) (not .cse0) (not .cse1)) (and (= ~b$r_buff0_thd0~0_In-1379275990 |ULTIMATE.start_main_#t~ite51_Out-1379275990|) (or .cse0 .cse1)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In-1379275990, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In-1379275990} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In-1379275990, ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_Out-1379275990|, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In-1379275990} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite51] because there is no mapped edge [2019-12-07 17:09:00,309 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] L854-->L854-2: Formula: (let ((.cse2 (= (mod ~b$w_buff0_used~0_In1858099339 256) 0)) (.cse3 (= (mod ~b$r_buff0_thd0~0_In1858099339 256) 0)) (.cse1 (= (mod ~b$r_buff1_thd0~0_In1858099339 256) 0)) (.cse0 (= (mod ~b$w_buff1_used~0_In1858099339 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite52_Out1858099339| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite52_Out1858099339| ~b$r_buff1_thd0~0_In1858099339) (or .cse1 .cse0)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In1858099339, ~b$r_buff1_thd0~0=~b$r_buff1_thd0~0_In1858099339, ~b$w_buff1_used~0=~b$w_buff1_used~0_In1858099339, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In1858099339} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In1858099339, ULTIMATE.start_main_#t~ite52=|ULTIMATE.start_main_#t~ite52_Out1858099339|, ~b$r_buff1_thd0~0=~b$r_buff1_thd0~0_In1858099339, ~b$w_buff1_used~0=~b$w_buff1_used~0_In1858099339, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In1858099339} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52] because there is no mapped edge [2019-12-07 17:09:00,309 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [895] [895] L854-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_19 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_14|) (= v_~main$tmp_guard1~0_17 (ite (= 0 (ite (not (and (= 1 v_~__unbuffered_p1_EAX~0_30) (= v_~__unbuffered_p2_EBX~0_21 0) (= v_~x~0_96 2) (= v_~__unbuffered_p1_EBX~0_30 0) (= 1 v_~__unbuffered_p2_EAX~0_23))) 1 0)) 0 1)) (= (mod v_~main$tmp_guard1~0_17 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_14|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_19 0) (= v_~b$r_buff1_thd0~0_116 |v_ULTIMATE.start_main_#t~ite52_39|)) InVars {ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_39|, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_30, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_21, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_30, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_23, ~x~0=v_~x~0_96} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_38|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_19, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_30, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_21, ~b$r_buff1_thd0~0=v_~b$r_buff1_thd0~0_116, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_30, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_17, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_23, ~x~0=v_~x~0_96, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_14|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~b$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 17:09:00,360 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 05:09:00 BasicIcfg [2019-12-07 17:09:00,361 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 17:09:00,361 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 17:09:00,361 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 17:09:00,361 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 17:09:00,361 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:04:51" (3/4) ... [2019-12-07 17:09:00,363 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 17:09:00,363 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [907] [907] ULTIMATE.startENTRY-->L840: Formula: (let ((.cse0 (store |v_#valid_71| 0 0))) (and (= v_~main$tmp_guard0~0_40 0) (= 0 v_~b$r_buff1_thd1~0_173) (= (store |v_#memory_int_26| |v_ULTIMATE.start_main_~#t873~0.base_30| (store (select |v_#memory_int_26| |v_ULTIMATE.start_main_~#t873~0.base_30|) |v_ULTIMATE.start_main_~#t873~0.offset_22| 0)) |v_#memory_int_25|) (= 0 v_~__unbuffered_p1_EAX~0_44) (= 0 v_~x~0_134) (= v_~z~0_33 0) (= 0 v_~weak$$choice0~0_14) (= |v_#NULL.offset_6| 0) (= 0 v_~b$r_buff0_thd2~0_158) (= v_~__unbuffered_p2_EBX~0_34 0) (= 0 v_~b$read_delayed~0_7) (= v_~a~0_13 0) (= v_~b$w_buff1~0_227 0) (< 0 |v_#StackHeapBarrier_19|) (= v_~weak$$choice2~0_143 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t873~0.base_30|)) (= 0 v_~b$r_buff0_thd3~0_397) (= v_~b$r_buff1_thd0~0_151 0) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t873~0.base_30| 4)) (= 0 v_~b$r_buff1_thd3~0_304) (= 0 v_~b$r_buff0_thd1~0_258) (= v_~__unbuffered_p1_EBX~0_44 0) (= v_~__unbuffered_cnt~0_127 0) (= v_~b$read_delayed_var~0.offset_7 0) (= v_~b~0_156 0) (= v_~y~0_27 0) (= v_~main$tmp_guard1~0_28 0) (= 0 |v_#NULL.base_6|) (= 0 v_~__unbuffered_p2_EAX~0_34) (= v_~b$mem_tmp~0_17 0) (= 0 v_~b$r_buff1_thd2~0_163) (= v_~b$flush_delayed~0_32 0) (= 0 v_~b$w_buff1_used~0_458) (= 0 v_~b$w_buff0_used~0_811) (< |v_#StackHeapBarrier_19| |v_ULTIMATE.start_main_~#t873~0.base_30|) (= 0 |v_ULTIMATE.start_main_~#t873~0.offset_22|) (= v_~b$r_buff0_thd0~0_167 0) (= 0 v_~b$w_buff0~0_363) (= 0 v_~b$read_delayed_var~0.base_7) (= |v_#valid_69| (store .cse0 |v_ULTIMATE.start_main_~#t873~0.base_30| 1)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_19|, #valid=|v_#valid_71|, #memory_int=|v_#memory_int_26|, #length=|v_#length_26|} OutVars{~b$r_buff0_thd3~0=v_~b$r_buff0_thd3~0_397, ~b$r_buff1_thd1~0=v_~b$r_buff1_thd1~0_173, ~b$read_delayed_var~0.offset=v_~b$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_64|, ULTIMATE.start_main_~#t875~0.offset=|v_ULTIMATE.start_main_~#t875~0.offset_15|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_38|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_38|, ~b$w_buff0_used~0=v_~b$w_buff0_used~0_811, ~a~0=v_~a~0_13, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_58|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_44, ULTIMATE.start_main_~#t873~0.base=|v_ULTIMATE.start_main_~#t873~0.base_30|, #length=|v_#length_25|, ~b$w_buff0~0=v_~b$w_buff0~0_363, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_34, ~b$r_buff0_thd0~0=v_~b$r_buff0_thd0~0_167, ~b$r_buff0_thd2~0=v_~b$r_buff0_thd2~0_158, ~b$mem_tmp~0=v_~b$mem_tmp~0_17, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_34, ~b$flush_delayed~0=v_~b$flush_delayed~0_32, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_8|, ~b$read_delayed~0=v_~b$read_delayed~0_7, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_19|, ~b$w_buff1~0=v_~b$w_buff1~0_227, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_127, ~x~0=v_~x~0_134, ~b$r_buff0_thd1~0=v_~b$r_buff0_thd1~0_258, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_28, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_105|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_42|, ULTIMATE.start_main_~#t874~0.offset=|v_ULTIMATE.start_main_~#t874~0.offset_15|, ~b$w_buff1_used~0=v_~b$w_buff1_used~0_458, ULTIMATE.start_main_~#t875~0.base=|v_ULTIMATE.start_main_~#t875~0.base_18|, ~y~0=v_~y~0_27, ~b$r_buff1_thd2~0=v_~b$r_buff1_thd2~0_163, ULTIMATE.start_main_~#t874~0.base=|v_ULTIMATE.start_main_~#t874~0.base_24|, ~b$r_buff1_thd0~0=v_~b$r_buff1_thd0~0_151, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_44, ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_19|, ULTIMATE.start_main_~#t873~0.offset=|v_ULTIMATE.start_main_~#t873~0.offset_22|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_8|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_40, #NULL.base=|v_#NULL.base_6|, ~b$read_delayed_var~0.base=v_~b$read_delayed_var~0.base_7, ~b~0=v_~b~0_156, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_22|, #valid=|v_#valid_69|, #memory_int=|v_#memory_int_25|, ~z~0=v_~z~0_33, ~weak$$choice2~0=v_~weak$$choice2~0_143, ~b$r_buff1_thd3~0=v_~b$r_buff1_thd3~0_304} AuxVars[] AssignedVars[~b$r_buff0_thd3~0, ~b$r_buff1_thd1~0, ~b$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_~#t875~0.offset, #NULL.offset, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite50, ~b$w_buff0_used~0, ~a~0, ULTIMATE.start_main_#t~ite52, ~__unbuffered_p1_EAX~0, ULTIMATE.start_main_~#t873~0.base, #length, ~b$w_buff0~0, ~__unbuffered_p2_EAX~0, ~b$r_buff0_thd0~0, ~b$r_buff0_thd2~0, ~b$mem_tmp~0, ~__unbuffered_p2_EBX~0, ~b$flush_delayed~0, ULTIMATE.start_main_#t~nondet45, ~b$read_delayed~0, ~weak$$choice0~0, ~b$w_buff1~0, ~__unbuffered_cnt~0, ~x~0, ~b$r_buff0_thd1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite51, ULTIMATE.start_main_~#t874~0.offset, ~b$w_buff1_used~0, ULTIMATE.start_main_~#t875~0.base, ~y~0, ~b$r_buff1_thd2~0, ULTIMATE.start_main_~#t874~0.base, ~b$r_buff1_thd0~0, ~__unbuffered_p1_EBX~0, ULTIMATE.start_main_#t~nondet46, ULTIMATE.start_main_~#t873~0.offset, ULTIMATE.start_main_#t~nondet44, ~main$tmp_guard0~0, #NULL.base, ~b$read_delayed_var~0.base, ~b~0, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~b$r_buff1_thd3~0] because there is no mapped edge [2019-12-07 17:09:00,364 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [881] [881] L840-1-->L842: Formula: (and (= 0 |v_ULTIMATE.start_main_~#t874~0.offset_10|) (= (store |v_#valid_39| |v_ULTIMATE.start_main_~#t874~0.base_12| 1) |v_#valid_38|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t874~0.base_12|) (not (= |v_ULTIMATE.start_main_~#t874~0.base_12| 0)) (= (store |v_#length_18| |v_ULTIMATE.start_main_~#t874~0.base_12| 4) |v_#length_17|) (= 0 (select |v_#valid_39| |v_ULTIMATE.start_main_~#t874~0.base_12|)) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t874~0.base_12| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t874~0.base_12|) |v_ULTIMATE.start_main_~#t874~0.offset_10| 1)) |v_#memory_int_17|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_18|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t874~0.base=|v_ULTIMATE.start_main_~#t874~0.base_12|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_~#t874~0.offset=|v_ULTIMATE.start_main_~#t874~0.offset_10|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_4|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_17|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t874~0.base, ULTIMATE.start_main_~#t874~0.offset, ULTIMATE.start_main_#t~nondet44, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 17:09:00,364 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [882] [882] L4-->L752: Formula: (and (= ~b$r_buff0_thd1~0_In-1817262039 ~b$r_buff1_thd1~0_Out-1817262039) (= ~b$r_buff1_thd3~0_Out-1817262039 ~b$r_buff0_thd3~0_In-1817262039) (= ~x~0_Out-1817262039 1) (not (= P0Thread1of1ForFork1___VERIFIER_assert_~expression_In-1817262039 0)) (= ~b$r_buff0_thd1~0_Out-1817262039 1) (= ~b$r_buff0_thd2~0_In-1817262039 ~b$r_buff1_thd2~0_Out-1817262039) (= ~b$r_buff0_thd0~0_In-1817262039 ~b$r_buff1_thd0~0_Out-1817262039)) InVars {~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_In-1817262039, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In-1817262039, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In-1817262039, P0Thread1of1ForFork1___VERIFIER_assert_~expression=P0Thread1of1ForFork1___VERIFIER_assert_~expression_In-1817262039, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In-1817262039} OutVars{~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_Out-1817262039, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In-1817262039, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In-1817262039, ~b$r_buff1_thd1~0=~b$r_buff1_thd1~0_Out-1817262039, ~b$r_buff1_thd0~0=~b$r_buff1_thd0~0_Out-1817262039, P0Thread1of1ForFork1___VERIFIER_assert_~expression=P0Thread1of1ForFork1___VERIFIER_assert_~expression_In-1817262039, ~b$r_buff1_thd2~0=~b$r_buff1_thd2~0_Out-1817262039, ~x~0=~x~0_Out-1817262039, ~b$r_buff1_thd3~0=~b$r_buff1_thd3~0_Out-1817262039, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In-1817262039} AuxVars[] AssignedVars[~b$r_buff0_thd1~0, ~b$r_buff1_thd1~0, ~b$r_buff1_thd0~0, ~b$r_buff1_thd2~0, ~x~0, ~b$r_buff1_thd3~0] because there is no mapped edge [2019-12-07 17:09:00,365 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [852] [852] L778-2-->L778-5: Formula: (let ((.cse0 (= (mod ~b$r_buff1_thd2~0_In-773681727 256) 0)) (.cse2 (= |P1Thread1of1ForFork2_#t~ite9_Out-773681727| |P1Thread1of1ForFork2_#t~ite10_Out-773681727|)) (.cse1 (= (mod ~b$w_buff1_used~0_In-773681727 256) 0))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite9_Out-773681727| ~b~0_In-773681727) .cse2) (and (= ~b$w_buff1~0_In-773681727 |P1Thread1of1ForFork2_#t~ite9_Out-773681727|) (not .cse0) .cse2 (not .cse1)))) InVars {~b$w_buff1_used~0=~b$w_buff1_used~0_In-773681727, ~b~0=~b~0_In-773681727, ~b$w_buff1~0=~b$w_buff1~0_In-773681727, ~b$r_buff1_thd2~0=~b$r_buff1_thd2~0_In-773681727} OutVars{P1Thread1of1ForFork2_#t~ite9=|P1Thread1of1ForFork2_#t~ite9_Out-773681727|, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-773681727, ~b~0=~b~0_In-773681727, P1Thread1of1ForFork2_#t~ite10=|P1Thread1of1ForFork2_#t~ite10_Out-773681727|, ~b$w_buff1~0=~b$w_buff1~0_In-773681727, ~b$r_buff1_thd2~0=~b$r_buff1_thd2~0_In-773681727} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite10] because there is no mapped edge [2019-12-07 17:09:00,365 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [839] [839] L753-->L753-2: Formula: (let ((.cse0 (= (mod ~b$r_buff0_thd1~0_In819873431 256) 0)) (.cse1 (= (mod ~b$w_buff0_used~0_In819873431 256) 0))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork1_#t~ite5_Out819873431| 0)) (and (or .cse0 .cse1) (= |P0Thread1of1ForFork1_#t~ite5_Out819873431| ~b$w_buff0_used~0_In819873431)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In819873431, ~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_In819873431} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In819873431, P0Thread1of1ForFork1_#t~ite5=|P0Thread1of1ForFork1_#t~ite5_Out819873431|, ~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_In819873431} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite5] because there is no mapped edge [2019-12-07 17:09:00,366 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [827] [827] L754-->L754-2: Formula: (let ((.cse0 (= (mod ~b$r_buff1_thd1~0_In-355899940 256) 0)) (.cse1 (= 0 (mod ~b$w_buff1_used~0_In-355899940 256))) (.cse3 (= 0 (mod ~b$r_buff0_thd1~0_In-355899940 256))) (.cse2 (= 0 (mod ~b$w_buff0_used~0_In-355899940 256)))) (or (and (= |P0Thread1of1ForFork1_#t~ite6_Out-355899940| ~b$w_buff1_used~0_In-355899940) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P0Thread1of1ForFork1_#t~ite6_Out-355899940| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In-355899940, ~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_In-355899940, ~b$r_buff1_thd1~0=~b$r_buff1_thd1~0_In-355899940, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-355899940} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In-355899940, ~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_In-355899940, ~b$r_buff1_thd1~0=~b$r_buff1_thd1~0_In-355899940, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-355899940, P0Thread1of1ForFork1_#t~ite6=|P0Thread1of1ForFork1_#t~ite6_Out-355899940|} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite6] because there is no mapped edge [2019-12-07 17:09:00,366 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [828] [828] L779-->L779-2: Formula: (let ((.cse0 (= (mod ~b$w_buff0_used~0_In-459326923 256) 0)) (.cse1 (= 0 (mod ~b$r_buff0_thd2~0_In-459326923 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite11_Out-459326923| 0) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite11_Out-459326923| ~b$w_buff0_used~0_In-459326923)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In-459326923, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In-459326923} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In-459326923, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In-459326923, P1Thread1of1ForFork2_#t~ite11=|P1Thread1of1ForFork2_#t~ite11_Out-459326923|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-12-07 17:09:00,367 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [850] [850] L755-->L756: Formula: (let ((.cse0 (= 0 (mod ~b$r_buff0_thd1~0_In862586898 256))) (.cse2 (= (mod ~b$w_buff0_used~0_In862586898 256) 0)) (.cse1 (= ~b$r_buff0_thd1~0_In862586898 ~b$r_buff0_thd1~0_Out862586898))) (or (and .cse0 .cse1) (and (= 0 ~b$r_buff0_thd1~0_Out862586898) (not .cse2) (not .cse0)) (and .cse2 .cse1))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In862586898, ~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_In862586898} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In862586898, ~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_Out862586898, P0Thread1of1ForFork1_#t~ite7=|P0Thread1of1ForFork1_#t~ite7_Out862586898|} AuxVars[] AssignedVars[~b$r_buff0_thd1~0, P0Thread1of1ForFork1_#t~ite7] because there is no mapped edge [2019-12-07 17:09:00,367 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [835] [835] L756-->L756-2: Formula: (let ((.cse3 (= 0 (mod ~b$r_buff0_thd1~0_In1069875815 256))) (.cse2 (= 0 (mod ~b$w_buff0_used~0_In1069875815 256))) (.cse0 (= (mod ~b$w_buff1_used~0_In1069875815 256) 0)) (.cse1 (= (mod ~b$r_buff1_thd1~0_In1069875815 256) 0))) (or (and (= |P0Thread1of1ForFork1_#t~ite8_Out1069875815| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse0 .cse1) (= |P0Thread1of1ForFork1_#t~ite8_Out1069875815| ~b$r_buff1_thd1~0_In1069875815)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In1069875815, ~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_In1069875815, ~b$r_buff1_thd1~0=~b$r_buff1_thd1~0_In1069875815, ~b$w_buff1_used~0=~b$w_buff1_used~0_In1069875815} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In1069875815, ~b$r_buff0_thd1~0=~b$r_buff0_thd1~0_In1069875815, ~b$r_buff1_thd1~0=~b$r_buff1_thd1~0_In1069875815, P0Thread1of1ForFork1_#t~ite8=|P0Thread1of1ForFork1_#t~ite8_Out1069875815|, ~b$w_buff1_used~0=~b$w_buff1_used~0_In1069875815} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 17:09:00,367 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [880] [880] L756-2-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork1_#res.base_3|) (= v_~b$r_buff1_thd1~0_107 |v_P0Thread1of1ForFork1_#t~ite8_46|) (= 0 |v_P0Thread1of1ForFork1_#res.offset_3|) (= (+ v_~__unbuffered_cnt~0_87 1) v_~__unbuffered_cnt~0_86)) InVars {P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_46|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_87} OutVars{~b$r_buff1_thd1~0=v_~b$r_buff1_thd1~0_107, P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_45|, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_3|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_86} AuxVars[] AssignedVars[~b$r_buff1_thd1~0, P0Thread1of1ForFork1_#t~ite8, P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 17:09:00,367 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [878] [878] L842-1-->L844: Formula: (and (= (store |v_#length_16| |v_ULTIMATE.start_main_~#t875~0.base_12| 4) |v_#length_15|) (= 0 |v_ULTIMATE.start_main_~#t875~0.offset_10|) (not (= 0 |v_ULTIMATE.start_main_~#t875~0.base_12|)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t875~0.base_12|) (= 0 (select |v_#valid_37| |v_ULTIMATE.start_main_~#t875~0.base_12|)) (= |v_#valid_36| (store |v_#valid_37| |v_ULTIMATE.start_main_~#t875~0.base_12| 1)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t875~0.base_12| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t875~0.base_12|) |v_ULTIMATE.start_main_~#t875~0.offset_10| 2)) |v_#memory_int_15|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_37|, #memory_int=|v_#memory_int_16|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t875~0.base=|v_ULTIMATE.start_main_~#t875~0.base_12|, #valid=|v_#valid_36|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_4|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_~#t875~0.offset=|v_ULTIMATE.start_main_~#t875~0.offset_10|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t875~0.base, #valid, ULTIMATE.start_main_#t~nondet45, #memory_int, ULTIMATE.start_main_~#t875~0.offset, #length] because there is no mapped edge [2019-12-07 17:09:00,370 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [883] [883] L809-->L809-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-631029246 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite29_In-631029246| |P2Thread1of1ForFork0_#t~ite29_Out-631029246|) (= ~b$w_buff1_used~0_In-631029246 |P2Thread1of1ForFork0_#t~ite30_Out-631029246|) (not .cse0)) (and (= ~b$w_buff1_used~0_In-631029246 |P2Thread1of1ForFork0_#t~ite29_Out-631029246|) (let ((.cse1 (= (mod ~b$r_buff0_thd3~0_In-631029246 256) 0))) (or (and (= (mod ~b$w_buff1_used~0_In-631029246 256) 0) .cse1) (and (= (mod ~b$r_buff1_thd3~0_In-631029246 256) 0) .cse1) (= (mod ~b$w_buff0_used~0_In-631029246 256) 0))) (= |P2Thread1of1ForFork0_#t~ite30_Out-631029246| |P2Thread1of1ForFork0_#t~ite29_Out-631029246|) .cse0))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In-631029246, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In-631029246, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-631029246, ~weak$$choice2~0=~weak$$choice2~0_In-631029246, P2Thread1of1ForFork0_#t~ite29=|P2Thread1of1ForFork0_#t~ite29_In-631029246|, ~b$r_buff1_thd3~0=~b$r_buff1_thd3~0_In-631029246} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In-631029246, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In-631029246, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-631029246, P2Thread1of1ForFork0_#t~ite30=|P2Thread1of1ForFork0_#t~ite30_Out-631029246|, P2Thread1of1ForFork0_#t~ite29=|P2Thread1of1ForFork0_#t~ite29_Out-631029246|, ~weak$$choice2~0=~weak$$choice2~0_In-631029246, ~b$r_buff1_thd3~0=~b$r_buff1_thd3~0_In-631029246} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite30, P2Thread1of1ForFork0_#t~ite29] because there is no mapped edge [2019-12-07 17:09:00,371 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [897] [897] L810-->L811-8: Formula: (and (= |v_P2Thread1of1ForFork0_#t~ite36_36| v_~b$r_buff1_thd3~0_279) (= v_~b$r_buff0_thd3~0_376 v_~b$r_buff0_thd3~0_375) (not (= 0 (mod v_~weak$$choice2~0_126 256))) (= |v_P2Thread1of1ForFork0_#t~ite34_29| |v_P2Thread1of1ForFork0_#t~ite34_28|) (= |v_P2Thread1of1ForFork0_#t~ite35_33| |v_P2Thread1of1ForFork0_#t~ite35_32|)) InVars {~b$r_buff0_thd3~0=v_~b$r_buff0_thd3~0_376, P2Thread1of1ForFork0_#t~ite35=|v_P2Thread1of1ForFork0_#t~ite35_33|, P2Thread1of1ForFork0_#t~ite34=|v_P2Thread1of1ForFork0_#t~ite34_29|, ~weak$$choice2~0=v_~weak$$choice2~0_126, ~b$r_buff1_thd3~0=v_~b$r_buff1_thd3~0_279} OutVars{P2Thread1of1ForFork0_#t~ite36=|v_P2Thread1of1ForFork0_#t~ite36_36|, ~b$r_buff0_thd3~0=v_~b$r_buff0_thd3~0_375, P2Thread1of1ForFork0_#t~ite33=|v_P2Thread1of1ForFork0_#t~ite33_23|, P2Thread1of1ForFork0_#t~ite32=|v_P2Thread1of1ForFork0_#t~ite32_32|, P2Thread1of1ForFork0_#t~ite35=|v_P2Thread1of1ForFork0_#t~ite35_32|, P2Thread1of1ForFork0_#t~ite34=|v_P2Thread1of1ForFork0_#t~ite34_28|, P2Thread1of1ForFork0_#t~ite31=|v_P2Thread1of1ForFork0_#t~ite31_25|, ~weak$$choice2~0=v_~weak$$choice2~0_126, ~b$r_buff1_thd3~0=v_~b$r_buff1_thd3~0_279} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite36, ~b$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite33, P2Thread1of1ForFork0_#t~ite32, P2Thread1of1ForFork0_#t~ite35, P2Thread1of1ForFork0_#t~ite34, P2Thread1of1ForFork0_#t~ite31] because there is no mapped edge [2019-12-07 17:09:00,371 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L813-->L817: Formula: (and (= v_~b$flush_delayed~0_6 0) (not (= (mod v_~b$flush_delayed~0_7 256) 0)) (= v_~b~0_16 v_~b$mem_tmp~0_4)) InVars {~b$mem_tmp~0=v_~b$mem_tmp~0_4, ~b$flush_delayed~0=v_~b$flush_delayed~0_7} OutVars{P2Thread1of1ForFork0_#t~ite37=|v_P2Thread1of1ForFork0_#t~ite37_5|, ~b$mem_tmp~0=v_~b$mem_tmp~0_4, ~b~0=v_~b~0_16, ~b$flush_delayed~0=v_~b$flush_delayed~0_6} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite37, ~b~0, ~b$flush_delayed~0] because there is no mapped edge [2019-12-07 17:09:00,371 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [847] [847] L817-2-->L817-5: Formula: (let ((.cse0 (= |P2Thread1of1ForFork0_#t~ite38_Out-358957499| |P2Thread1of1ForFork0_#t~ite39_Out-358957499|)) (.cse1 (= 0 (mod ~b$w_buff1_used~0_In-358957499 256))) (.cse2 (= 0 (mod ~b$r_buff1_thd3~0_In-358957499 256)))) (or (and .cse0 (= ~b$w_buff1~0_In-358957499 |P2Thread1of1ForFork0_#t~ite38_Out-358957499|) (not .cse1) (not .cse2)) (and .cse0 (= |P2Thread1of1ForFork0_#t~ite38_Out-358957499| ~b~0_In-358957499) (or .cse1 .cse2)))) InVars {~b$w_buff1_used~0=~b$w_buff1_used~0_In-358957499, ~b~0=~b~0_In-358957499, ~b$w_buff1~0=~b$w_buff1~0_In-358957499, ~b$r_buff1_thd3~0=~b$r_buff1_thd3~0_In-358957499} OutVars{P2Thread1of1ForFork0_#t~ite39=|P2Thread1of1ForFork0_#t~ite39_Out-358957499|, P2Thread1of1ForFork0_#t~ite38=|P2Thread1of1ForFork0_#t~ite38_Out-358957499|, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-358957499, ~b~0=~b~0_In-358957499, ~b$w_buff1~0=~b$w_buff1~0_In-358957499, ~b$r_buff1_thd3~0=~b$r_buff1_thd3~0_In-358957499} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite39, P2Thread1of1ForFork0_#t~ite38] because there is no mapped edge [2019-12-07 17:09:00,372 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L818-->L818-2: Formula: (let ((.cse1 (= 0 (mod ~b$w_buff0_used~0_In683024697 256))) (.cse0 (= 0 (mod ~b$r_buff0_thd3~0_In683024697 256)))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite40_Out683024697| ~b$w_buff0_used~0_In683024697)) (and (not .cse1) (not .cse0) (= |P2Thread1of1ForFork0_#t~ite40_Out683024697| 0)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In683024697, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In683024697} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In683024697, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In683024697, P2Thread1of1ForFork0_#t~ite40=|P2Thread1of1ForFork0_#t~ite40_Out683024697|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite40] because there is no mapped edge [2019-12-07 17:09:00,372 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [831] [831] L819-->L819-2: Formula: (let ((.cse2 (= 0 (mod ~b$w_buff1_used~0_In1314199592 256))) (.cse3 (= (mod ~b$r_buff1_thd3~0_In1314199592 256) 0)) (.cse1 (= (mod ~b$r_buff0_thd3~0_In1314199592 256) 0)) (.cse0 (= 0 (mod ~b$w_buff0_used~0_In1314199592 256)))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite41_Out1314199592| ~b$w_buff1_used~0_In1314199592) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |P2Thread1of1ForFork0_#t~ite41_Out1314199592| 0)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In1314199592, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In1314199592, ~b$w_buff1_used~0=~b$w_buff1_used~0_In1314199592, ~b$r_buff1_thd3~0=~b$r_buff1_thd3~0_In1314199592} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In1314199592, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In1314199592, ~b$w_buff1_used~0=~b$w_buff1_used~0_In1314199592, P2Thread1of1ForFork0_#t~ite41=|P2Thread1of1ForFork0_#t~ite41_Out1314199592|, ~b$r_buff1_thd3~0=~b$r_buff1_thd3~0_In1314199592} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite41] because there is no mapped edge [2019-12-07 17:09:00,373 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [842] [842] L820-->L820-2: Formula: (let ((.cse1 (= (mod ~b$r_buff0_thd3~0_In-959911550 256) 0)) (.cse0 (= 0 (mod ~b$w_buff0_used~0_In-959911550 256)))) (or (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite42_Out-959911550| 0) (not .cse1)) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork0_#t~ite42_Out-959911550| ~b$r_buff0_thd3~0_In-959911550)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In-959911550, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In-959911550} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In-959911550, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In-959911550, P2Thread1of1ForFork0_#t~ite42=|P2Thread1of1ForFork0_#t~ite42_Out-959911550|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite42] because there is no mapped edge [2019-12-07 17:09:00,373 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L821-->L821-2: Formula: (let ((.cse0 (= (mod ~b$r_buff0_thd3~0_In-316149769 256) 0)) (.cse1 (= (mod ~b$w_buff0_used~0_In-316149769 256) 0)) (.cse3 (= (mod ~b$w_buff1_used~0_In-316149769 256) 0)) (.cse2 (= (mod ~b$r_buff1_thd3~0_In-316149769 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite43_Out-316149769| ~b$r_buff1_thd3~0_In-316149769) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite43_Out-316149769|) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In-316149769, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In-316149769, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-316149769, ~b$r_buff1_thd3~0=~b$r_buff1_thd3~0_In-316149769} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In-316149769, ~b$r_buff0_thd3~0=~b$r_buff0_thd3~0_In-316149769, P2Thread1of1ForFork0_#t~ite43=|P2Thread1of1ForFork0_#t~ite43_Out-316149769|, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-316149769, ~b$r_buff1_thd3~0=~b$r_buff1_thd3~0_In-316149769} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite43] because there is no mapped edge [2019-12-07 17:09:00,373 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L821-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= (+ v_~__unbuffered_cnt~0_56 1) v_~__unbuffered_cnt~0_55) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite43_34| v_~b$r_buff1_thd3~0_101)) InVars {P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56} OutVars{P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_33|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55, ~b$r_buff1_thd3~0=v_~b$r_buff1_thd3~0_101, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#res.base, P2Thread1of1ForFork0_#t~ite43, ~__unbuffered_cnt~0, ~b$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 17:09:00,374 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [840] [840] L780-->L780-2: Formula: (let ((.cse2 (= 0 (mod ~b$r_buff1_thd2~0_In1478108249 256))) (.cse3 (= (mod ~b$w_buff1_used~0_In1478108249 256) 0)) (.cse1 (= (mod ~b$r_buff0_thd2~0_In1478108249 256) 0)) (.cse0 (= 0 (mod ~b$w_buff0_used~0_In1478108249 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite12_Out1478108249|)) (and (= ~b$w_buff1_used~0_In1478108249 |P1Thread1of1ForFork2_#t~ite12_Out1478108249|) (or .cse2 .cse3) (or .cse1 .cse0)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In1478108249, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In1478108249, ~b$w_buff1_used~0=~b$w_buff1_used~0_In1478108249, ~b$r_buff1_thd2~0=~b$r_buff1_thd2~0_In1478108249} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In1478108249, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In1478108249, ~b$w_buff1_used~0=~b$w_buff1_used~0_In1478108249, P1Thread1of1ForFork2_#t~ite12=|P1Thread1of1ForFork2_#t~ite12_Out1478108249|, ~b$r_buff1_thd2~0=~b$r_buff1_thd2~0_In1478108249} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite12] because there is no mapped edge [2019-12-07 17:09:00,374 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [836] [836] L781-->L781-2: Formula: (let ((.cse1 (= 0 (mod ~b$w_buff0_used~0_In-887798388 256))) (.cse0 (= (mod ~b$r_buff0_thd2~0_In-887798388 256) 0))) (or (and (= ~b$r_buff0_thd2~0_In-887798388 |P1Thread1of1ForFork2_#t~ite13_Out-887798388|) (or .cse0 .cse1)) (and (not .cse1) (= 0 |P1Thread1of1ForFork2_#t~ite13_Out-887798388|) (not .cse0)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In-887798388, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In-887798388} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In-887798388, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In-887798388, P1Thread1of1ForFork2_#t~ite13=|P1Thread1of1ForFork2_#t~ite13_Out-887798388|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite13] because there is no mapped edge [2019-12-07 17:09:00,374 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L782-->L782-2: Formula: (let ((.cse1 (= (mod ~b$w_buff0_used~0_In888541559 256) 0)) (.cse0 (= (mod ~b$r_buff0_thd2~0_In888541559 256) 0)) (.cse2 (= 0 (mod ~b$w_buff1_used~0_In888541559 256))) (.cse3 (= (mod ~b$r_buff1_thd2~0_In888541559 256) 0))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite14_Out888541559| ~b$r_buff1_thd2~0_In888541559) (or .cse2 .cse3)) (and (= |P1Thread1of1ForFork2_#t~ite14_Out888541559| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In888541559, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In888541559, ~b$w_buff1_used~0=~b$w_buff1_used~0_In888541559, ~b$r_buff1_thd2~0=~b$r_buff1_thd2~0_In888541559} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In888541559, ~b$r_buff0_thd2~0=~b$r_buff0_thd2~0_In888541559, ~b$w_buff1_used~0=~b$w_buff1_used~0_In888541559, P1Thread1of1ForFork2_#t~ite14=|P1Thread1of1ForFork2_#t~ite14_Out888541559|, ~b$r_buff1_thd2~0=~b$r_buff1_thd2~0_In888541559} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite14] because there is no mapped edge [2019-12-07 17:09:00,374 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [872] [872] L782-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= v_~b$r_buff1_thd2~0_91 |v_P1Thread1of1ForFork2_#t~ite14_50|) (= (+ v_~__unbuffered_cnt~0_81 1) v_~__unbuffered_cnt~0_80)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_81, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_50|} OutVars{P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_80, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_49|, ~b$r_buff1_thd2~0=v_~b$r_buff1_thd2~0_91, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#t~ite14, ~b$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 17:09:00,375 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L848-->L850-2: Formula: (and (or (= 0 (mod v_~b$w_buff0_used~0_159 256)) (= 0 (mod v_~b$r_buff0_thd0~0_23 256))) (not (= 0 (mod v_~main$tmp_guard0~0_5 256)))) InVars {~b$w_buff0_used~0=v_~b$w_buff0_used~0_159, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_5, ~b$r_buff0_thd0~0=v_~b$r_buff0_thd0~0_23} OutVars{~b$w_buff0_used~0=v_~b$w_buff0_used~0_159, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_5, ~b$r_buff0_thd0~0=v_~b$r_buff0_thd0~0_23} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 17:09:00,375 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [848] [848] L850-2-->L850-4: Formula: (let ((.cse1 (= (mod ~b$w_buff1_used~0_In-2089564303 256) 0)) (.cse0 (= 0 (mod ~b$r_buff1_thd0~0_In-2089564303 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite47_Out-2089564303| ~b$w_buff1~0_In-2089564303) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite47_Out-2089564303| ~b~0_In-2089564303) (or .cse1 .cse0)))) InVars {~b$r_buff1_thd0~0=~b$r_buff1_thd0~0_In-2089564303, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-2089564303, ~b~0=~b~0_In-2089564303, ~b$w_buff1~0=~b$w_buff1~0_In-2089564303} OutVars{~b$r_buff1_thd0~0=~b$r_buff1_thd0~0_In-2089564303, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-2089564303, ~b~0=~b~0_In-2089564303, ULTIMATE.start_main_#t~ite47=|ULTIMATE.start_main_#t~ite47_Out-2089564303|, ~b$w_buff1~0=~b$w_buff1~0_In-2089564303} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] because there is no mapped edge [2019-12-07 17:09:00,375 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L850-4-->L851: Formula: (= v_~b~0_28 |v_ULTIMATE.start_main_#t~ite47_9|) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_9|} OutVars{~b~0=v_~b~0_28, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_8|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_12|} AuxVars[] AssignedVars[~b~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 17:09:00,375 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [849] [849] L851-->L851-2: Formula: (let ((.cse0 (= (mod ~b$w_buff0_used~0_In-1695741204 256) 0)) (.cse1 (= 0 (mod ~b$r_buff0_thd0~0_In-1695741204 256)))) (or (and (= |ULTIMATE.start_main_#t~ite49_Out-1695741204| 0) (not .cse0) (not .cse1)) (and (= ~b$w_buff0_used~0_In-1695741204 |ULTIMATE.start_main_#t~ite49_Out-1695741204|) (or .cse0 .cse1)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In-1695741204, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In-1695741204} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In-1695741204, ULTIMATE.start_main_#t~ite49=|ULTIMATE.start_main_#t~ite49_Out-1695741204|, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In-1695741204} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite49] because there is no mapped edge [2019-12-07 17:09:00,376 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L852-->L852-2: Formula: (let ((.cse0 (= 0 (mod ~b$w_buff0_used~0_In-1685809702 256))) (.cse1 (= (mod ~b$r_buff0_thd0~0_In-1685809702 256) 0)) (.cse2 (= 0 (mod ~b$r_buff1_thd0~0_In-1685809702 256))) (.cse3 (= 0 (mod ~b$w_buff1_used~0_In-1685809702 256)))) (or (and (or .cse0 .cse1) (= ~b$w_buff1_used~0_In-1685809702 |ULTIMATE.start_main_#t~ite50_Out-1685809702|) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite50_Out-1685809702| 0)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In-1685809702, ~b$r_buff1_thd0~0=~b$r_buff1_thd0~0_In-1685809702, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-1685809702, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In-1685809702} OutVars{ULTIMATE.start_main_#t~ite50=|ULTIMATE.start_main_#t~ite50_Out-1685809702|, ~b$w_buff0_used~0=~b$w_buff0_used~0_In-1685809702, ~b$r_buff1_thd0~0=~b$r_buff1_thd0~0_In-1685809702, ~b$w_buff1_used~0=~b$w_buff1_used~0_In-1685809702, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In-1685809702} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite50] because there is no mapped edge [2019-12-07 17:09:00,376 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [837] [837] L853-->L853-2: Formula: (let ((.cse0 (= 0 (mod ~b$r_buff0_thd0~0_In-1379275990 256))) (.cse1 (= (mod ~b$w_buff0_used~0_In-1379275990 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite51_Out-1379275990|) (not .cse0) (not .cse1)) (and (= ~b$r_buff0_thd0~0_In-1379275990 |ULTIMATE.start_main_#t~ite51_Out-1379275990|) (or .cse0 .cse1)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In-1379275990, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In-1379275990} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In-1379275990, ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_Out-1379275990|, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In-1379275990} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite51] because there is no mapped edge [2019-12-07 17:09:00,376 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] L854-->L854-2: Formula: (let ((.cse2 (= (mod ~b$w_buff0_used~0_In1858099339 256) 0)) (.cse3 (= (mod ~b$r_buff0_thd0~0_In1858099339 256) 0)) (.cse1 (= (mod ~b$r_buff1_thd0~0_In1858099339 256) 0)) (.cse0 (= (mod ~b$w_buff1_used~0_In1858099339 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite52_Out1858099339| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite52_Out1858099339| ~b$r_buff1_thd0~0_In1858099339) (or .cse1 .cse0)))) InVars {~b$w_buff0_used~0=~b$w_buff0_used~0_In1858099339, ~b$r_buff1_thd0~0=~b$r_buff1_thd0~0_In1858099339, ~b$w_buff1_used~0=~b$w_buff1_used~0_In1858099339, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In1858099339} OutVars{~b$w_buff0_used~0=~b$w_buff0_used~0_In1858099339, ULTIMATE.start_main_#t~ite52=|ULTIMATE.start_main_#t~ite52_Out1858099339|, ~b$r_buff1_thd0~0=~b$r_buff1_thd0~0_In1858099339, ~b$w_buff1_used~0=~b$w_buff1_used~0_In1858099339, ~b$r_buff0_thd0~0=~b$r_buff0_thd0~0_In1858099339} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52] because there is no mapped edge [2019-12-07 17:09:00,377 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [895] [895] L854-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_19 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_14|) (= v_~main$tmp_guard1~0_17 (ite (= 0 (ite (not (and (= 1 v_~__unbuffered_p1_EAX~0_30) (= v_~__unbuffered_p2_EBX~0_21 0) (= v_~x~0_96 2) (= v_~__unbuffered_p1_EBX~0_30 0) (= 1 v_~__unbuffered_p2_EAX~0_23))) 1 0)) 0 1)) (= (mod v_~main$tmp_guard1~0_17 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_14|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_19 0) (= v_~b$r_buff1_thd0~0_116 |v_ULTIMATE.start_main_#t~ite52_39|)) InVars {ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_39|, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_30, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_21, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_30, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_23, ~x~0=v_~x~0_96} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_38|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_19, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_30, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_21, ~b$r_buff1_thd0~0=v_~b$r_buff1_thd0~0_116, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_30, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_17, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_23, ~x~0=v_~x~0_96, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_14|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~b$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 17:09:00,429 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_dde28f07-fd16-4804-8edb-05c660702a75/bin/uautomizer/witness.graphml [2019-12-07 17:09:00,429 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 17:09:00,430 INFO L168 Benchmark]: Toolchain (without parser) took 249649.63 ms. Allocated memory was 1.0 GB in the beginning and 8.4 GB in the end (delta: 7.4 GB). Free memory was 943.5 MB in the beginning and 4.4 GB in the end (delta: -3.4 GB). Peak memory consumption was 4.0 GB. Max. memory is 11.5 GB. [2019-12-07 17:09:00,430 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 963.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 17:09:00,431 INFO L168 Benchmark]: CACSL2BoogieTranslator took 376.12 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 102.2 MB). Free memory was 943.5 MB in the beginning and 1.1 GB in the end (delta: -120.0 MB). Peak memory consumption was 18.2 MB. Max. memory is 11.5 GB. [2019-12-07 17:09:00,431 INFO L168 Benchmark]: Boogie Procedure Inliner took 38.36 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 17:09:00,431 INFO L168 Benchmark]: Boogie Preprocessor took 26.77 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 17:09:00,431 INFO L168 Benchmark]: RCFGBuilder took 404.86 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 61.1 MB). Peak memory consumption was 61.1 MB. Max. memory is 11.5 GB. [2019-12-07 17:09:00,431 INFO L168 Benchmark]: TraceAbstraction took 248732.30 ms. Allocated memory was 1.1 GB in the beginning and 8.4 GB in the end (delta: 7.3 GB). Free memory was 1.0 GB in the beginning and 4.4 GB in the end (delta: -3.4 GB). Peak memory consumption was 3.9 GB. Max. memory is 11.5 GB. [2019-12-07 17:09:00,432 INFO L168 Benchmark]: Witness Printer took 68.19 ms. Allocated memory is still 8.4 GB. Free memory was 4.4 GB in the beginning and 4.4 GB in the end (delta: 48.9 MB). Peak memory consumption was 48.9 MB. Max. memory is 11.5 GB. [2019-12-07 17:09:00,433 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 963.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 376.12 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 102.2 MB). Free memory was 943.5 MB in the beginning and 1.1 GB in the end (delta: -120.0 MB). Peak memory consumption was 18.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 38.36 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.77 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 404.86 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 61.1 MB). Peak memory consumption was 61.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 248732.30 ms. Allocated memory was 1.1 GB in the beginning and 8.4 GB in the end (delta: 7.3 GB). Free memory was 1.0 GB in the beginning and 4.4 GB in the end (delta: -3.4 GB). Peak memory consumption was 3.9 GB. Max. memory is 11.5 GB. * Witness Printer took 68.19 ms. Allocated memory is still 8.4 GB. Free memory was 4.4 GB in the beginning and 4.4 GB in the end (delta: 48.9 MB). Peak memory consumption was 48.9 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.4s, 179 ProgramPointsBefore, 93 ProgramPointsAfterwards, 216 TransitionsBefore, 102 TransitionsAfterwards, 19004 CoEnabledTransitionPairs, 7 FixpointIterations, 36 TrivialSequentialCompositions, 49 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 35 ConcurrentYvCompositions, 32 ChoiceCompositions, 7364 VarBasedMoverChecksPositive, 244 VarBasedMoverChecksNegative, 47 SemBasedMoverChecksPositive, 271 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.0s, 0 MoverChecksTotal, 80691 CheckedPairsTotal, 120 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L840] FCALL, FORK 0 pthread_create(&t873, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, b$flush_delayed=0, b$mem_tmp=0, b$r_buff0_thd0=0, b$r_buff0_thd1=0, b$r_buff0_thd2=0, b$r_buff0_thd3=0, b$r_buff1_thd0=0, b$r_buff1_thd1=0, b$r_buff1_thd2=0, b$r_buff1_thd3=0, b$read_delayed=0, b$read_delayed_var={0:0}, b$w_buff0=0, b$w_buff0_used=0, b$w_buff1=0, b$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L842] FCALL, FORK 0 pthread_create(&t874, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, b=0, b$flush_delayed=0, b$mem_tmp=0, b$r_buff0_thd0=0, b$r_buff0_thd1=0, b$r_buff0_thd2=0, b$r_buff0_thd3=0, b$r_buff1_thd0=0, b$r_buff1_thd1=0, b$r_buff1_thd2=0, b$r_buff1_thd3=0, b$read_delayed=0, b$read_delayed_var={0:0}, b$w_buff0=0, b$w_buff0_used=0, b$w_buff1=0, b$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L737] 1 b$w_buff1 = b$w_buff0 [L738] 1 b$w_buff0 = 1 [L739] 1 b$w_buff1_used = b$w_buff0_used [L740] 1 b$w_buff0_used = (_Bool)1 [L752] EXPR 1 b$w_buff0_used && b$r_buff0_thd1 ? b$w_buff0 : (b$w_buff1_used && b$r_buff1_thd1 ? b$w_buff1 : b) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, b=0, b$flush_delayed=0, b$mem_tmp=0, b$r_buff0_thd0=0, b$r_buff0_thd1=1, b$r_buff0_thd2=0, b$r_buff0_thd3=0, b$r_buff1_thd0=0, b$r_buff1_thd1=0, b$r_buff1_thd2=0, b$r_buff1_thd3=0, b$read_delayed=0, b$read_delayed_var={0:0}, b$w_buff0=1, b$w_buff0_used=1, b$w_buff1=0, b$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0] [L766] 2 x = 2 [L769] 2 y = 1 [L772] 2 __unbuffered_p1_EAX = y [L775] 2 __unbuffered_p1_EBX = z VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, b$flush_delayed=0, b$mem_tmp=0, b$r_buff0_thd0=0, b$r_buff0_thd1=1, b$r_buff0_thd2=0, b$r_buff0_thd3=0, b$r_buff1_thd0=0, b$r_buff1_thd1=0, b$r_buff1_thd2=0, b$r_buff1_thd3=0, b$read_delayed=0, b$read_delayed_var={0:0}, b$w_buff0=1, b$w_buff0_used=1, b$w_buff1=0, b$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=0] [L778] EXPR 2 b$w_buff0_used && b$r_buff0_thd2 ? b$w_buff0 : (b$w_buff1_used && b$r_buff1_thd2 ? b$w_buff1 : b) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, b$flush_delayed=0, b$mem_tmp=0, b$r_buff0_thd0=0, b$r_buff0_thd1=1, b$r_buff0_thd2=0, b$r_buff0_thd3=0, b$r_buff1_thd0=0, b$r_buff1_thd1=0, b$r_buff1_thd2=0, b$r_buff1_thd3=0, b$read_delayed=0, b$read_delayed_var={0:0}, b$w_buff0=1, b$w_buff0_used=1, b$w_buff1=0, b$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=0] [L752] 1 b = b$w_buff0_used && b$r_buff0_thd1 ? b$w_buff0 : (b$w_buff1_used && b$r_buff1_thd1 ? b$w_buff1 : b) [L778] 2 b = b$w_buff0_used && b$r_buff0_thd2 ? b$w_buff0 : (b$w_buff1_used && b$r_buff1_thd2 ? b$w_buff1 : b) [L753] 1 b$w_buff0_used = b$w_buff0_used && b$r_buff0_thd1 ? (_Bool)0 : b$w_buff0_used [L754] 1 b$w_buff1_used = b$w_buff0_used && b$r_buff0_thd1 || b$w_buff1_used && b$r_buff1_thd1 ? (_Bool)0 : b$w_buff1_used [L844] FCALL, FORK 0 pthread_create(&t875, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, b=0, b$flush_delayed=0, b$mem_tmp=0, b$r_buff0_thd0=0, b$r_buff0_thd1=1, b$r_buff0_thd2=0, b$r_buff0_thd3=0, b$r_buff1_thd0=0, b$r_buff1_thd1=0, b$r_buff1_thd2=0, b$r_buff1_thd3=0, b$read_delayed=0, b$read_delayed_var={0:0}, b$w_buff0=1, b$w_buff0_used=0, b$w_buff0_used && b$r_buff0_thd2 ? (_Bool)0 : b$w_buff0_used=0, b$w_buff1=0, b$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=0] [L792] 3 z = 1 [L795] 3 a = 1 [L798] 3 __unbuffered_p2_EAX = a [L801] 3 weak$$choice0 = __VERIFIER_nondet_bool() [L802] 3 weak$$choice2 = __VERIFIER_nondet_bool() [L803] 3 b$flush_delayed = weak$$choice2 [L804] 3 b$mem_tmp = b VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=0, b$flush_delayed=1, b$mem_tmp=0, b$r_buff0_thd0=0, b$r_buff0_thd1=1, b$r_buff0_thd2=0, b$r_buff0_thd3=0, b$r_buff1_thd0=0, b$r_buff1_thd1=0, b$r_buff1_thd2=0, b$r_buff1_thd3=0, b$read_delayed=0, b$read_delayed_var={0:0}, b$w_buff0=1, b$w_buff0_used=0, b$w_buff0_used && b$r_buff0_thd2 ? (_Bool)0 : b$w_buff0_used=0, b$w_buff1=0, b$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=2, y=1, z=1] [L805] EXPR 3 !b$w_buff0_used || !b$r_buff0_thd3 && !b$w_buff1_used || !b$r_buff0_thd3 && !b$r_buff1_thd3 ? b : (b$w_buff0_used && b$r_buff0_thd3 ? b$w_buff0 : b$w_buff1) VAL [!b$w_buff0_used || !b$r_buff0_thd3 && !b$w_buff1_used || !b$r_buff0_thd3 && !b$r_buff1_thd3 ? b : (b$w_buff0_used && b$r_buff0_thd3 ? b$w_buff0 : b$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=0, b$flush_delayed=1, b$mem_tmp=0, b$r_buff0_thd0=0, b$r_buff0_thd1=1, b$r_buff0_thd2=0, b$r_buff0_thd3=0, b$r_buff1_thd0=0, b$r_buff1_thd1=0, b$r_buff1_thd2=0, b$r_buff1_thd3=0, b$read_delayed=0, b$read_delayed_var={0:0}, b$w_buff0=1, b$w_buff0_used=0, b$w_buff0_used && b$r_buff0_thd2 ? (_Bool)0 : b$w_buff0_used=0, b$w_buff1=0, b$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=2, y=1, z=1] [L805] 3 b = !b$w_buff0_used || !b$r_buff0_thd3 && !b$w_buff1_used || !b$r_buff0_thd3 && !b$r_buff1_thd3 ? b : (b$w_buff0_used && b$r_buff0_thd3 ? b$w_buff0 : b$w_buff1) [L806] EXPR 3 weak$$choice2 ? b$w_buff0 : (!b$w_buff0_used || !b$r_buff0_thd3 && !b$w_buff1_used || !b$r_buff0_thd3 && !b$r_buff1_thd3 ? b$w_buff0 : (b$w_buff0_used && b$r_buff0_thd3 ? b$w_buff0 : b$w_buff0)) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=0, b$flush_delayed=1, b$mem_tmp=0, b$r_buff0_thd0=0, b$r_buff0_thd1=1, b$r_buff0_thd2=0, b$r_buff0_thd3=0, b$r_buff1_thd0=0, b$r_buff1_thd1=0, b$r_buff1_thd2=0, b$r_buff1_thd3=0, b$read_delayed=0, b$read_delayed_var={0:0}, b$w_buff0=1, b$w_buff0_used=0, b$w_buff0_used && b$r_buff0_thd2 ? (_Bool)0 : b$w_buff0_used=0, b$w_buff1=0, b$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, weak$$choice2 ? b$w_buff0 : (!b$w_buff0_used || !b$r_buff0_thd3 && !b$w_buff1_used || !b$r_buff0_thd3 && !b$r_buff1_thd3 ? b$w_buff0 : (b$w_buff0_used && b$r_buff0_thd3 ? b$w_buff0 : b$w_buff0))=1, x=2, y=1, z=1] [L806] 3 b$w_buff0 = weak$$choice2 ? b$w_buff0 : (!b$w_buff0_used || !b$r_buff0_thd3 && !b$w_buff1_used || !b$r_buff0_thd3 && !b$r_buff1_thd3 ? b$w_buff0 : (b$w_buff0_used && b$r_buff0_thd3 ? b$w_buff0 : b$w_buff0)) [L807] EXPR 3 weak$$choice2 ? b$w_buff1 : (!b$w_buff0_used || !b$r_buff0_thd3 && !b$w_buff1_used || !b$r_buff0_thd3 && !b$r_buff1_thd3 ? b$w_buff1 : (b$w_buff0_used && b$r_buff0_thd3 ? b$w_buff1 : b$w_buff1)) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=0, b$flush_delayed=1, b$mem_tmp=0, b$r_buff0_thd0=0, b$r_buff0_thd1=1, b$r_buff0_thd2=0, b$r_buff0_thd3=0, b$r_buff1_thd0=0, b$r_buff1_thd1=0, b$r_buff1_thd2=0, b$r_buff1_thd3=0, b$read_delayed=0, b$read_delayed_var={0:0}, b$w_buff0=1, b$w_buff0_used=0, b$w_buff0_used && b$r_buff0_thd2 ? (_Bool)0 : b$w_buff0_used=0, b$w_buff1=0, b$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, weak$$choice2 ? b$w_buff1 : (!b$w_buff0_used || !b$r_buff0_thd3 && !b$w_buff1_used || !b$r_buff0_thd3 && !b$r_buff1_thd3 ? b$w_buff1 : (b$w_buff0_used && b$r_buff0_thd3 ? b$w_buff1 : b$w_buff1))=0, x=2, y=1, z=1] [L807] 3 b$w_buff1 = weak$$choice2 ? b$w_buff1 : (!b$w_buff0_used || !b$r_buff0_thd3 && !b$w_buff1_used || !b$r_buff0_thd3 && !b$r_buff1_thd3 ? b$w_buff1 : (b$w_buff0_used && b$r_buff0_thd3 ? b$w_buff1 : b$w_buff1)) [L808] EXPR 3 weak$$choice2 ? b$w_buff0_used : (!b$w_buff0_used || !b$r_buff0_thd3 && !b$w_buff1_used || !b$r_buff0_thd3 && !b$r_buff1_thd3 ? b$w_buff0_used : (b$w_buff0_used && b$r_buff0_thd3 ? (_Bool)0 : b$w_buff0_used)) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=0, b$flush_delayed=1, b$mem_tmp=0, b$r_buff0_thd0=0, b$r_buff0_thd1=1, b$r_buff0_thd2=0, b$r_buff0_thd3=0, b$r_buff1_thd0=0, b$r_buff1_thd1=0, b$r_buff1_thd2=0, b$r_buff1_thd3=0, b$read_delayed=0, b$read_delayed_var={0:0}, b$w_buff0=1, b$w_buff0_used=0, b$w_buff0_used && b$r_buff0_thd2 ? (_Bool)0 : b$w_buff0_used=0, b$w_buff1=0, b$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, weak$$choice2 ? b$w_buff0_used : (!b$w_buff0_used || !b$r_buff0_thd3 && !b$w_buff1_used || !b$r_buff0_thd3 && !b$r_buff1_thd3 ? b$w_buff0_used : (b$w_buff0_used && b$r_buff0_thd3 ? (_Bool)0 : b$w_buff0_used))=0, x=2, y=1, z=1] [L808] 3 b$w_buff0_used = weak$$choice2 ? b$w_buff0_used : (!b$w_buff0_used || !b$r_buff0_thd3 && !b$w_buff1_used || !b$r_buff0_thd3 && !b$r_buff1_thd3 ? b$w_buff0_used : (b$w_buff0_used && b$r_buff0_thd3 ? (_Bool)0 : b$w_buff0_used)) [L809] 3 b$w_buff1_used = weak$$choice2 ? b$w_buff1_used : (!b$w_buff0_used || !b$r_buff0_thd3 && !b$w_buff1_used || !b$r_buff0_thd3 && !b$r_buff1_thd3 ? b$w_buff1_used : (b$w_buff0_used && b$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L811] 3 b$r_buff1_thd3 = weak$$choice2 ? b$r_buff1_thd3 : (!b$w_buff0_used || !b$r_buff0_thd3 && !b$w_buff1_used || !b$r_buff0_thd3 && !b$r_buff1_thd3 ? b$r_buff1_thd3 : (b$w_buff0_used && b$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L812] 3 __unbuffered_p2_EBX = b VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=0, b$flush_delayed=1, b$mem_tmp=0, b$r_buff0_thd0=0, b$r_buff0_thd1=1, b$r_buff0_thd2=0, b$r_buff0_thd3=0, b$r_buff1_thd0=0, b$r_buff1_thd1=0, b$r_buff1_thd2=0, b$r_buff1_thd3=0, b$read_delayed=0, b$read_delayed_var={0:0}, b$w_buff0=1, b$w_buff0_used=0, b$w_buff0_used && b$r_buff0_thd2 ? (_Bool)0 : b$w_buff0_used=0, b$w_buff1=0, b$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=2, y=1, z=1] [L817] EXPR 3 b$w_buff0_used && b$r_buff0_thd3 ? b$w_buff0 : (b$w_buff1_used && b$r_buff1_thd3 ? b$w_buff1 : b) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=0, b$flush_delayed=0, b$mem_tmp=0, b$r_buff0_thd0=0, b$r_buff0_thd1=1, b$r_buff0_thd2=0, b$r_buff0_thd3=0, b$r_buff1_thd0=0, b$r_buff1_thd1=0, b$r_buff1_thd2=0, b$r_buff1_thd3=0, b$read_delayed=0, b$read_delayed_var={0:0}, b$w_buff0=1, b$w_buff0_used=0, b$w_buff0_used && b$r_buff0_thd2 ? (_Bool)0 : b$w_buff0_used=0, b$w_buff1=0, b$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=2, y=1, z=1] [L817] 3 b = b$w_buff0_used && b$r_buff0_thd3 ? b$w_buff0 : (b$w_buff1_used && b$r_buff1_thd3 ? b$w_buff1 : b) [L818] 3 b$w_buff0_used = b$w_buff0_used && b$r_buff0_thd3 ? (_Bool)0 : b$w_buff0_used [L819] 3 b$w_buff1_used = b$w_buff0_used && b$r_buff0_thd3 || b$w_buff1_used && b$r_buff1_thd3 ? (_Bool)0 : b$w_buff1_used [L820] 3 b$r_buff0_thd3 = b$w_buff0_used && b$r_buff0_thd3 ? (_Bool)0 : b$r_buff0_thd3 [L779] 2 b$w_buff0_used = b$w_buff0_used && b$r_buff0_thd2 ? (_Bool)0 : b$w_buff0_used [L780] 2 b$w_buff1_used = b$w_buff0_used && b$r_buff0_thd2 || b$w_buff1_used && b$r_buff1_thd2 ? (_Bool)0 : b$w_buff1_used [L781] 2 b$r_buff0_thd2 = b$w_buff0_used && b$r_buff0_thd2 ? (_Bool)0 : b$r_buff0_thd2 [L846] 0 main$tmp_guard0 = __unbuffered_cnt == 3 VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=0, b$flush_delayed=0, b$mem_tmp=0, b$r_buff0_thd0=0, b$r_buff0_thd1=1, b$r_buff0_thd2=0, b$r_buff0_thd3=0, b$r_buff1_thd0=0, b$r_buff1_thd1=0, b$r_buff1_thd2=0, b$r_buff1_thd3=0, b$read_delayed=0, b$read_delayed_var={0:0}, b$w_buff0=1, b$w_buff0_used=0, b$w_buff1=0, b$w_buff1_used=0, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=2, y=1, z=1] [L851] 0 b$w_buff0_used = b$w_buff0_used && b$r_buff0_thd0 ? (_Bool)0 : b$w_buff0_used [L852] 0 b$w_buff1_used = b$w_buff0_used && b$r_buff0_thd0 || b$w_buff1_used && b$r_buff1_thd0 ? (_Bool)0 : b$w_buff1_used [L853] 0 b$r_buff0_thd0 = b$w_buff0_used && b$r_buff0_thd0 ? (_Bool)0 : b$r_buff0_thd0 - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 170 locations, 2 error locations. Result: UNSAFE, OverallTime: 248.5s, OverallIterations: 40, TraceHistogramMax: 1, AutomataDifference: 85.1s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 10929 SDtfs, 15553 SDslu, 46197 SDs, 0 SdLazy, 49533 SolverSat, 808 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 35.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 804 GetRequests, 46 SyntacticMatches, 42 SemanticMatches, 716 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11641 ImplicationChecksByTransitivity, 10.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=349791occurred in iteration=8, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 141.0s AutomataMinimizationTime, 39 MinimizatonAttempts, 567490 StatesRemovedByMinimization, 37 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 4.9s InterpolantComputationTime, 1618 NumberOfCodeBlocks, 1618 NumberOfCodeBlocksAsserted, 40 NumberOfCheckSat, 1513 ConstructedInterpolants, 0 QuantifiedInterpolants, 571712 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 39 InterpolantComputations, 39 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...