./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix036_power.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_aa315b34-122a-4185-9e3e-d45e078a5220/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_aa315b34-122a-4185-9e3e-d45e078a5220/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_aa315b34-122a-4185-9e3e-d45e078a5220/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_aa315b34-122a-4185-9e3e-d45e078a5220/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix036_power.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_aa315b34-122a-4185-9e3e-d45e078a5220/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_aa315b34-122a-4185-9e3e-d45e078a5220/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash aaadaa430afe319284ad2cc35ebb4ad15d10acd1 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:53:11,685 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:53:11,687 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:53:11,694 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:53:11,694 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:53:11,695 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:53:11,696 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:53:11,697 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:53:11,698 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:53:11,699 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:53:11,700 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:53:11,701 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:53:11,701 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:53:11,701 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:53:11,702 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:53:11,703 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:53:11,703 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:53:11,704 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:53:11,706 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:53:11,707 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:53:11,709 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:53:11,709 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:53:11,710 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:53:11,710 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:53:11,712 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:53:11,713 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:53:11,713 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:53:11,713 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:53:11,713 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:53:11,714 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:53:11,714 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:53:11,715 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:53:11,715 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:53:11,715 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:53:11,716 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:53:11,716 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:53:11,716 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:53:11,717 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:53:11,717 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:53:11,717 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:53:11,718 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:53:11,718 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_aa315b34-122a-4185-9e3e-d45e078a5220/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 18:53:11,727 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:53:11,727 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:53:11,728 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:53:11,728 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:53:11,728 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:53:11,728 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:53:11,728 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:53:11,728 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:53:11,729 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:53:11,729 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:53:11,729 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 18:53:11,729 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 18:53:11,729 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 18:53:11,729 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:53:11,729 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:53:11,729 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:53:11,729 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 18:53:11,729 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:53:11,730 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:53:11,730 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 18:53:11,730 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 18:53:11,730 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:53:11,730 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:53:11,730 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 18:53:11,730 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 18:53:11,730 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:53:11,730 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 18:53:11,731 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 18:53:11,731 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:53:11,731 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_aa315b34-122a-4185-9e3e-d45e078a5220/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> aaadaa430afe319284ad2cc35ebb4ad15d10acd1 [2019-12-07 18:53:11,830 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:53:11,839 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:53:11,842 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:53:11,843 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:53:11,844 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:53:11,844 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_aa315b34-122a-4185-9e3e-d45e078a5220/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix036_power.opt.i [2019-12-07 18:53:11,884 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_aa315b34-122a-4185-9e3e-d45e078a5220/bin/uautomizer/data/2105f28a2/f9e7d38a8c354fa2b1ff0e86a12859c7/FLAGe5f1cf676 [2019-12-07 18:53:12,350 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:53:12,350 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_aa315b34-122a-4185-9e3e-d45e078a5220/sv-benchmarks/c/pthread-wmm/mix036_power.opt.i [2019-12-07 18:53:12,363 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_aa315b34-122a-4185-9e3e-d45e078a5220/bin/uautomizer/data/2105f28a2/f9e7d38a8c354fa2b1ff0e86a12859c7/FLAGe5f1cf676 [2019-12-07 18:53:12,374 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_aa315b34-122a-4185-9e3e-d45e078a5220/bin/uautomizer/data/2105f28a2/f9e7d38a8c354fa2b1ff0e86a12859c7 [2019-12-07 18:53:12,376 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:53:12,377 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:53:12,378 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:53:12,378 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:53:12,380 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:53:12,380 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:53:12" (1/1) ... [2019-12-07 18:53:12,382 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5a2ff042 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:53:12, skipping insertion in model container [2019-12-07 18:53:12,382 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:53:12" (1/1) ... [2019-12-07 18:53:12,387 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:53:12,420 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:53:12,667 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:53:12,675 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:53:12,718 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:53:12,764 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:53:12,764 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:53:12 WrapperNode [2019-12-07 18:53:12,765 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:53:12,765 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:53:12,765 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:53:12,765 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:53:12,771 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:53:12" (1/1) ... [2019-12-07 18:53:12,785 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:53:12" (1/1) ... [2019-12-07 18:53:12,804 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:53:12,804 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:53:12,804 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:53:12,805 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:53:12,811 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:53:12" (1/1) ... [2019-12-07 18:53:12,811 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:53:12" (1/1) ... [2019-12-07 18:53:12,815 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:53:12" (1/1) ... [2019-12-07 18:53:12,815 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:53:12" (1/1) ... [2019-12-07 18:53:12,822 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:53:12" (1/1) ... [2019-12-07 18:53:12,826 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:53:12" (1/1) ... [2019-12-07 18:53:12,829 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:53:12" (1/1) ... [2019-12-07 18:53:12,832 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:53:12,832 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:53:12,832 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:53:12,833 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:53:12,833 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:53:12" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_aa315b34-122a-4185-9e3e-d45e078a5220/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:53:12,872 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 18:53:12,872 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 18:53:12,872 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 18:53:12,872 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 18:53:12,873 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 18:53:12,873 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 18:53:12,873 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 18:53:12,873 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 18:53:12,873 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 18:53:12,873 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 18:53:12,873 INFO L130 BoogieDeclarations]: Found specification of procedure P3 [2019-12-07 18:53:12,873 INFO L138 BoogieDeclarations]: Found implementation of procedure P3 [2019-12-07 18:53:12,873 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 18:53:12,873 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:53:12,873 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:53:12,874 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 18:53:13,222 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:53:13,222 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 18:53:13,223 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:53:13 BoogieIcfgContainer [2019-12-07 18:53:13,223 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:53:13,223 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 18:53:13,224 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 18:53:13,225 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 18:53:13,225 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 06:53:12" (1/3) ... [2019-12-07 18:53:13,226 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@16660a3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:53:13, skipping insertion in model container [2019-12-07 18:53:13,226 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:53:12" (2/3) ... [2019-12-07 18:53:13,226 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@16660a3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:53:13, skipping insertion in model container [2019-12-07 18:53:13,226 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:53:13" (3/3) ... [2019-12-07 18:53:13,227 INFO L109 eAbstractionObserver]: Analyzing ICFG mix036_power.opt.i [2019-12-07 18:53:13,234 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 18:53:13,234 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 18:53:13,239 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 18:53:13,239 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 18:53:13,264 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,265 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,265 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,265 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,265 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,265 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,266 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,266 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~nondet3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,266 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~nondet4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,266 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,266 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,266 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~nondet3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,266 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,266 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~nondet4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,267 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,267 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,267 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,267 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,267 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,267 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,267 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,267 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,268 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,268 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,268 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,268 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,268 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,268 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,268 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,268 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,268 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,269 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,269 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,269 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,269 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,269 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,269 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,269 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,269 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,270 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,270 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,270 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,270 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,270 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,270 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,270 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,270 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,270 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,271 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,271 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,271 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,271 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,271 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,271 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,271 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,271 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,271 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,272 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,272 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,272 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,272 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,272 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,272 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,272 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,272 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,272 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,273 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,273 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,273 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,273 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,273 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,273 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,273 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,273 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,273 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,274 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,274 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,274 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,274 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,274 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,274 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,274 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,274 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,274 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,274 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,275 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,275 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,275 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,275 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,275 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,275 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,275 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,275 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,275 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,276 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,276 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,276 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,276 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,276 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,276 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,277 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,277 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,277 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork3___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,277 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork3_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,277 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,277 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork3_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,277 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork3___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,277 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork3___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,277 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,278 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,278 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,278 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,278 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,278 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,278 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,278 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,278 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,278 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,279 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,279 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,279 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,279 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,279 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,279 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,279 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,279 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,279 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,280 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,280 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,280 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,280 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,280 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,280 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,280 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork3_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,280 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,281 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,281 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,281 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,281 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,281 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,281 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,281 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,281 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,281 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,282 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,282 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,282 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,282 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,282 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,282 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,282 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,282 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,282 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,282 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,283 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,283 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,283 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,283 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,283 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,283 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,283 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,283 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,283 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,283 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:53:13,298 INFO L249 AbstractCegarLoop]: Starting to check reachability of 7 error locations. [2019-12-07 18:53:13,313 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 18:53:13,313 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 18:53:13,313 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 18:53:13,313 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:53:13,313 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:53:13,313 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 18:53:13,313 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:53:13,314 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 18:53:13,324 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 183 places, 211 transitions [2019-12-07 18:53:13,325 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 183 places, 211 transitions [2019-12-07 18:53:13,385 INFO L134 PetriNetUnfolder]: 41/207 cut-off events. [2019-12-07 18:53:13,386 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:53:13,397 INFO L76 FinitePrefix]: Finished finitePrefix Result has 220 conditions, 207 events. 41/207 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 13. Compared 704 event pairs. 12/176 useless extension candidates. Maximal degree in co-relation 172. Up to 2 conditions per place. [2019-12-07 18:53:13,411 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 183 places, 211 transitions [2019-12-07 18:53:13,442 INFO L134 PetriNetUnfolder]: 41/207 cut-off events. [2019-12-07 18:53:13,443 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:53:13,448 INFO L76 FinitePrefix]: Finished finitePrefix Result has 220 conditions, 207 events. 41/207 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 13. Compared 704 event pairs. 12/176 useless extension candidates. Maximal degree in co-relation 172. Up to 2 conditions per place. [2019-12-07 18:53:13,463 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 18126 [2019-12-07 18:53:13,463 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 18:53:16,862 WARN L192 SmtUtils]: Spent 184.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 49 [2019-12-07 18:53:17,058 WARN L192 SmtUtils]: Spent 181.00 ms on a formula simplification. DAG size of input: 103 DAG size of output: 101 [2019-12-07 18:53:17,174 INFO L206 etLargeBlockEncoding]: Checked pairs total: 74129 [2019-12-07 18:53:17,174 INFO L214 etLargeBlockEncoding]: Total number of compositions: 127 [2019-12-07 18:53:17,176 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 88 places, 95 transitions [2019-12-07 18:53:43,096 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 160086 states. [2019-12-07 18:53:43,098 INFO L276 IsEmpty]: Start isEmpty. Operand 160086 states. [2019-12-07 18:53:43,102 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-12-07 18:53:43,102 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:53:43,102 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:53:43,103 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:53:43,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:53:43,106 INFO L82 PathProgramCache]: Analyzing trace with hash -74872892, now seen corresponding path program 1 times [2019-12-07 18:53:43,112 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:53:43,112 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1692209166] [2019-12-07 18:53:43,112 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:53:43,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:53:43,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:53:43,261 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1692209166] [2019-12-07 18:53:43,262 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:53:43,262 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:53:43,263 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [946122843] [2019-12-07 18:53:43,265 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:53:43,266 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:53:43,274 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:53:43,275 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:53:43,276 INFO L87 Difference]: Start difference. First operand 160086 states. Second operand 3 states. [2019-12-07 18:53:44,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:53:44,423 INFO L93 Difference]: Finished difference Result 158186 states and 763682 transitions. [2019-12-07 18:53:44,424 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:53:44,424 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-12-07 18:53:44,425 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:53:45,171 INFO L225 Difference]: With dead ends: 158186 [2019-12-07 18:53:45,171 INFO L226 Difference]: Without dead ends: 149138 [2019-12-07 18:53:45,172 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:53:52,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149138 states. [2019-12-07 18:53:54,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149138 to 149138. [2019-12-07 18:53:54,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149138 states. [2019-12-07 18:53:54,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149138 states to 149138 states and 719092 transitions. [2019-12-07 18:53:54,979 INFO L78 Accepts]: Start accepts. Automaton has 149138 states and 719092 transitions. Word has length 7 [2019-12-07 18:53:54,980 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:53:54,980 INFO L462 AbstractCegarLoop]: Abstraction has 149138 states and 719092 transitions. [2019-12-07 18:53:54,980 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:53:54,980 INFO L276 IsEmpty]: Start isEmpty. Operand 149138 states and 719092 transitions. [2019-12-07 18:53:54,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 18:53:54,988 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:53:54,988 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:53:54,988 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:53:54,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:53:54,988 INFO L82 PathProgramCache]: Analyzing trace with hash 117436716, now seen corresponding path program 1 times [2019-12-07 18:53:54,989 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:53:54,989 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1241929751] [2019-12-07 18:53:54,989 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:53:55,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:53:55,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:53:55,051 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1241929751] [2019-12-07 18:53:55,051 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:53:55,051 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:53:55,052 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1449901129] [2019-12-07 18:53:55,053 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:53:55,053 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:53:55,053 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:53:55,053 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:53:55,053 INFO L87 Difference]: Start difference. First operand 149138 states and 719092 transitions. Second operand 4 states. [2019-12-07 18:53:56,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:53:56,399 INFO L93 Difference]: Finished difference Result 229934 states and 1066258 transitions. [2019-12-07 18:53:56,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:53:56,400 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 18:53:56,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:53:59,758 INFO L225 Difference]: With dead ends: 229934 [2019-12-07 18:53:59,758 INFO L226 Difference]: Without dead ends: 229738 [2019-12-07 18:53:59,759 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:54:05,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 229738 states. [2019-12-07 18:54:08,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 229738 to 213034. [2019-12-07 18:54:08,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 213034 states. [2019-12-07 18:54:09,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 213034 states to 213034 states and 997136 transitions. [2019-12-07 18:54:09,391 INFO L78 Accepts]: Start accepts. Automaton has 213034 states and 997136 transitions. Word has length 15 [2019-12-07 18:54:09,391 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:54:09,391 INFO L462 AbstractCegarLoop]: Abstraction has 213034 states and 997136 transitions. [2019-12-07 18:54:09,391 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:54:09,391 INFO L276 IsEmpty]: Start isEmpty. Operand 213034 states and 997136 transitions. [2019-12-07 18:54:09,395 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 18:54:09,395 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:54:09,395 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:54:09,395 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:54:09,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:54:09,396 INFO L82 PathProgramCache]: Analyzing trace with hash 860387736, now seen corresponding path program 1 times [2019-12-07 18:54:09,396 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:54:09,396 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1614846384] [2019-12-07 18:54:09,396 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:54:09,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:54:09,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:54:09,458 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1614846384] [2019-12-07 18:54:09,458 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:54:09,458 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:54:09,458 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [582744473] [2019-12-07 18:54:09,458 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:54:09,459 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:54:09,459 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:54:09,459 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:54:09,459 INFO L87 Difference]: Start difference. First operand 213034 states and 997136 transitions. Second operand 4 states. [2019-12-07 18:54:11,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:54:11,531 INFO L93 Difference]: Finished difference Result 303626 states and 1391380 transitions. [2019-12-07 18:54:11,532 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:54:11,532 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 18:54:11,532 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:54:12,421 INFO L225 Difference]: With dead ends: 303626 [2019-12-07 18:54:12,421 INFO L226 Difference]: Without dead ends: 303402 [2019-12-07 18:54:12,421 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:54:19,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 303402 states. [2019-12-07 18:54:26,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 303402 to 256502. [2019-12-07 18:54:26,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 256502 states. [2019-12-07 18:54:27,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 256502 states to 256502 states and 1193404 transitions. [2019-12-07 18:54:27,977 INFO L78 Accepts]: Start accepts. Automaton has 256502 states and 1193404 transitions. Word has length 15 [2019-12-07 18:54:27,977 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:54:27,977 INFO L462 AbstractCegarLoop]: Abstraction has 256502 states and 1193404 transitions. [2019-12-07 18:54:27,977 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:54:27,977 INFO L276 IsEmpty]: Start isEmpty. Operand 256502 states and 1193404 transitions. [2019-12-07 18:54:27,982 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 18:54:27,982 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:54:27,982 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:54:27,983 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:54:27,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:54:27,983 INFO L82 PathProgramCache]: Analyzing trace with hash -293201311, now seen corresponding path program 1 times [2019-12-07 18:54:27,983 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:54:27,983 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [912476618] [2019-12-07 18:54:27,983 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:54:27,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:54:28,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:54:28,022 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [912476618] [2019-12-07 18:54:28,022 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:54:28,023 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:54:28,023 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [139784748] [2019-12-07 18:54:28,023 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:54:28,023 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:54:28,023 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:54:28,024 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:54:28,024 INFO L87 Difference]: Start difference. First operand 256502 states and 1193404 transitions. Second operand 4 states. [2019-12-07 18:54:30,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:54:30,236 INFO L93 Difference]: Finished difference Result 322820 states and 1487561 transitions. [2019-12-07 18:54:30,237 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:54:30,237 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2019-12-07 18:54:30,237 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:54:31,146 INFO L225 Difference]: With dead ends: 322820 [2019-12-07 18:54:31,146 INFO L226 Difference]: Without dead ends: 322628 [2019-12-07 18:54:31,146 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:54:41,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322628 states. [2019-12-07 18:54:45,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322628 to 276774. [2019-12-07 18:54:45,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 276774 states. [2019-12-07 18:54:46,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 276774 states to 276774 states and 1285532 transitions. [2019-12-07 18:54:46,757 INFO L78 Accepts]: Start accepts. Automaton has 276774 states and 1285532 transitions. Word has length 16 [2019-12-07 18:54:46,757 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:54:46,757 INFO L462 AbstractCegarLoop]: Abstraction has 276774 states and 1285532 transitions. [2019-12-07 18:54:46,757 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:54:46,757 INFO L276 IsEmpty]: Start isEmpty. Operand 276774 states and 1285532 transitions. [2019-12-07 18:54:46,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 18:54:46,761 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:54:46,762 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:54:46,762 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:54:46,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:54:46,762 INFO L82 PathProgramCache]: Analyzing trace with hash -293081279, now seen corresponding path program 1 times [2019-12-07 18:54:46,762 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:54:46,762 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [49187639] [2019-12-07 18:54:46,762 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:54:46,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:54:46,803 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:54:46,804 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [49187639] [2019-12-07 18:54:46,804 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:54:46,804 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:54:46,804 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [951028561] [2019-12-07 18:54:46,804 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:54:46,805 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:54:46,805 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:54:46,805 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:54:46,805 INFO L87 Difference]: Start difference. First operand 276774 states and 1285532 transitions. Second operand 4 states. [2019-12-07 18:54:49,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:54:49,128 INFO L93 Difference]: Finished difference Result 336936 states and 1552183 transitions. [2019-12-07 18:54:49,128 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:54:49,128 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2019-12-07 18:54:49,128 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:54:50,113 INFO L225 Difference]: With dead ends: 336936 [2019-12-07 18:54:50,113 INFO L226 Difference]: Without dead ends: 336744 [2019-12-07 18:54:50,113 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:55:01,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 336744 states. [2019-12-07 18:55:05,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 336744 to 277412. [2019-12-07 18:55:05,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 277412 states. [2019-12-07 18:55:07,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277412 states to 277412 states and 1288143 transitions. [2019-12-07 18:55:07,131 INFO L78 Accepts]: Start accepts. Automaton has 277412 states and 1288143 transitions. Word has length 16 [2019-12-07 18:55:07,131 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:07,131 INFO L462 AbstractCegarLoop]: Abstraction has 277412 states and 1288143 transitions. [2019-12-07 18:55:07,131 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:55:07,131 INFO L276 IsEmpty]: Start isEmpty. Operand 277412 states and 1288143 transitions. [2019-12-07 18:55:07,149 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2019-12-07 18:55:07,149 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:07,149 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:07,149 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:07,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:07,149 INFO L82 PathProgramCache]: Analyzing trace with hash -236448520, now seen corresponding path program 1 times [2019-12-07 18:55:07,149 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:07,149 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2000510343] [2019-12-07 18:55:07,149 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:07,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:07,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:07,206 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2000510343] [2019-12-07 18:55:07,206 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:07,207 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:55:07,207 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1240121677] [2019-12-07 18:55:07,207 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:55:07,207 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:07,207 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:55:07,208 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:55:07,208 INFO L87 Difference]: Start difference. First operand 277412 states and 1288143 transitions. Second operand 3 states. [2019-12-07 18:55:08,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:08,586 INFO L93 Difference]: Finished difference Result 278964 states and 1292630 transitions. [2019-12-07 18:55:08,587 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:55:08,587 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 20 [2019-12-07 18:55:08,587 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:09,915 INFO L225 Difference]: With dead ends: 278964 [2019-12-07 18:55:09,915 INFO L226 Difference]: Without dead ends: 278964 [2019-12-07 18:55:09,915 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:55:19,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 278964 states. [2019-12-07 18:55:23,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 278964 to 277319. [2019-12-07 18:55:23,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 277319 states. [2019-12-07 18:55:24,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277319 states to 277319 states and 1287652 transitions. [2019-12-07 18:55:24,944 INFO L78 Accepts]: Start accepts. Automaton has 277319 states and 1287652 transitions. Word has length 20 [2019-12-07 18:55:24,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:24,944 INFO L462 AbstractCegarLoop]: Abstraction has 277319 states and 1287652 transitions. [2019-12-07 18:55:24,944 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:55:24,944 INFO L276 IsEmpty]: Start isEmpty. Operand 277319 states and 1287652 transitions. [2019-12-07 18:55:24,965 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 18:55:24,966 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:24,966 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:24,966 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:24,966 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:24,966 INFO L82 PathProgramCache]: Analyzing trace with hash 318179554, now seen corresponding path program 1 times [2019-12-07 18:55:24,966 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:24,966 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1810822176] [2019-12-07 18:55:24,966 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:24,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:24,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:24,999 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1810822176] [2019-12-07 18:55:24,999 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:24,999 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:55:25,000 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2032020799] [2019-12-07 18:55:25,000 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:55:25,000 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:25,000 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:55:25,000 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:55:25,001 INFO L87 Difference]: Start difference. First operand 277319 states and 1287652 transitions. Second operand 3 states. [2019-12-07 18:55:26,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:26,905 INFO L93 Difference]: Finished difference Result 275822 states and 1280712 transitions. [2019-12-07 18:55:26,906 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:55:26,906 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 21 [2019-12-07 18:55:26,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:27,688 INFO L225 Difference]: With dead ends: 275822 [2019-12-07 18:55:27,688 INFO L226 Difference]: Without dead ends: 275822 [2019-12-07 18:55:27,688 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:55:34,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 275822 states. [2019-12-07 18:55:38,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 275822 to 275822. [2019-12-07 18:55:38,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 275822 states. [2019-12-07 18:55:39,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 275822 states to 275822 states and 1280712 transitions. [2019-12-07 18:55:39,689 INFO L78 Accepts]: Start accepts. Automaton has 275822 states and 1280712 transitions. Word has length 21 [2019-12-07 18:55:39,690 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:39,690 INFO L462 AbstractCegarLoop]: Abstraction has 275822 states and 1280712 transitions. [2019-12-07 18:55:39,690 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:55:39,690 INFO L276 IsEmpty]: Start isEmpty. Operand 275822 states and 1280712 transitions. [2019-12-07 18:55:39,716 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 18:55:39,716 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:39,716 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:39,716 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:39,716 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:39,717 INFO L82 PathProgramCache]: Analyzing trace with hash 559574299, now seen corresponding path program 1 times [2019-12-07 18:55:39,717 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:39,717 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [659511046] [2019-12-07 18:55:39,717 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:39,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:39,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:39,753 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [659511046] [2019-12-07 18:55:39,753 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:39,753 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:55:39,753 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2128128956] [2019-12-07 18:55:39,753 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:55:39,753 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:39,754 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:55:39,754 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:55:39,754 INFO L87 Difference]: Start difference. First operand 275822 states and 1280712 transitions. Second operand 5 states. [2019-12-07 18:55:45,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:45,353 INFO L93 Difference]: Finished difference Result 385174 states and 1757400 transitions. [2019-12-07 18:55:45,354 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:55:45,354 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2019-12-07 18:55:45,354 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:46,464 INFO L225 Difference]: With dead ends: 385174 [2019-12-07 18:55:46,464 INFO L226 Difference]: Without dead ends: 384792 [2019-12-07 18:55:46,464 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:55:54,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384792 states. [2019-12-07 18:55:59,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384792 to 290536. [2019-12-07 18:55:59,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 290536 states. [2019-12-07 18:56:00,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 290536 states to 290536 states and 1346927 transitions. [2019-12-07 18:56:00,474 INFO L78 Accepts]: Start accepts. Automaton has 290536 states and 1346927 transitions. Word has length 21 [2019-12-07 18:56:00,474 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:00,474 INFO L462 AbstractCegarLoop]: Abstraction has 290536 states and 1346927 transitions. [2019-12-07 18:56:00,474 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:56:00,474 INFO L276 IsEmpty]: Start isEmpty. Operand 290536 states and 1346927 transitions. [2019-12-07 18:56:00,499 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 18:56:00,500 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:00,500 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:00,500 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:00,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:00,500 INFO L82 PathProgramCache]: Analyzing trace with hash 357663375, now seen corresponding path program 1 times [2019-12-07 18:56:00,500 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:00,500 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [631856155] [2019-12-07 18:56:00,500 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:00,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:00,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:00,529 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [631856155] [2019-12-07 18:56:00,529 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:00,529 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:56:00,529 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2123944862] [2019-12-07 18:56:00,529 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:56:00,530 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:00,530 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:56:00,530 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:56:00,530 INFO L87 Difference]: Start difference. First operand 290536 states and 1346927 transitions. Second operand 3 states. [2019-12-07 18:56:01,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:01,283 INFO L93 Difference]: Finished difference Result 179389 states and 748773 transitions. [2019-12-07 18:56:01,284 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:56:01,284 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 21 [2019-12-07 18:56:01,284 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:02,276 INFO L225 Difference]: With dead ends: 179389 [2019-12-07 18:56:02,276 INFO L226 Difference]: Without dead ends: 179389 [2019-12-07 18:56:02,277 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:56:05,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179389 states. [2019-12-07 18:56:08,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179389 to 179389. [2019-12-07 18:56:08,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 179389 states. [2019-12-07 18:56:09,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179389 states to 179389 states and 748773 transitions. [2019-12-07 18:56:09,001 INFO L78 Accepts]: Start accepts. Automaton has 179389 states and 748773 transitions. Word has length 21 [2019-12-07 18:56:09,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:09,001 INFO L462 AbstractCegarLoop]: Abstraction has 179389 states and 748773 transitions. [2019-12-07 18:56:09,001 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:56:09,001 INFO L276 IsEmpty]: Start isEmpty. Operand 179389 states and 748773 transitions. [2019-12-07 18:56:09,018 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 18:56:09,018 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:09,018 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:09,018 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:09,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:09,018 INFO L82 PathProgramCache]: Analyzing trace with hash 371264485, now seen corresponding path program 1 times [2019-12-07 18:56:09,019 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:09,019 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1571137975] [2019-12-07 18:56:09,019 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:09,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:09,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:09,059 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1571137975] [2019-12-07 18:56:09,059 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:09,060 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:56:09,060 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [685239195] [2019-12-07 18:56:09,060 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:56:09,060 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:09,060 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:56:09,060 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:56:09,060 INFO L87 Difference]: Start difference. First operand 179389 states and 748773 transitions. Second operand 4 states. [2019-12-07 18:56:12,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:12,758 INFO L93 Difference]: Finished difference Result 284843 states and 1188989 transitions. [2019-12-07 18:56:12,759 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:56:12,759 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 22 [2019-12-07 18:56:12,759 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:13,469 INFO L225 Difference]: With dead ends: 284843 [2019-12-07 18:56:13,469 INFO L226 Difference]: Without dead ends: 275011 [2019-12-07 18:56:13,470 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:56:18,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 275011 states. [2019-12-07 18:56:22,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 275011 to 274789. [2019-12-07 18:56:22,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 274789 states. [2019-12-07 18:56:22,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 274789 states to 274789 states and 1148100 transitions. [2019-12-07 18:56:22,809 INFO L78 Accepts]: Start accepts. Automaton has 274789 states and 1148100 transitions. Word has length 22 [2019-12-07 18:56:22,810 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:22,810 INFO L462 AbstractCegarLoop]: Abstraction has 274789 states and 1148100 transitions. [2019-12-07 18:56:22,810 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:56:22,810 INFO L276 IsEmpty]: Start isEmpty. Operand 274789 states and 1148100 transitions. [2019-12-07 18:56:22,833 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 18:56:22,833 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:22,833 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:22,833 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:22,833 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:22,833 INFO L82 PathProgramCache]: Analyzing trace with hash 1724335203, now seen corresponding path program 2 times [2019-12-07 18:56:22,833 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:22,833 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1849911390] [2019-12-07 18:56:22,833 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:22,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:22,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:22,867 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1849911390] [2019-12-07 18:56:22,867 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:22,867 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:56:22,867 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1505657940] [2019-12-07 18:56:22,867 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:56:22,867 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:22,868 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:56:22,868 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:56:22,868 INFO L87 Difference]: Start difference. First operand 274789 states and 1148100 transitions. Second operand 4 states. [2019-12-07 18:56:23,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:23,080 INFO L93 Difference]: Finished difference Result 62542 states and 218525 transitions. [2019-12-07 18:56:23,081 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:56:23,081 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 22 [2019-12-07 18:56:23,081 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:23,195 INFO L225 Difference]: With dead ends: 62542 [2019-12-07 18:56:23,195 INFO L226 Difference]: Without dead ends: 62542 [2019-12-07 18:56:23,195 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:56:23,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62542 states. [2019-12-07 18:56:24,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62542 to 62542. [2019-12-07 18:56:24,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 62542 states. [2019-12-07 18:56:24,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62542 states to 62542 states and 218525 transitions. [2019-12-07 18:56:24,576 INFO L78 Accepts]: Start accepts. Automaton has 62542 states and 218525 transitions. Word has length 22 [2019-12-07 18:56:24,576 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:24,577 INFO L462 AbstractCegarLoop]: Abstraction has 62542 states and 218525 transitions. [2019-12-07 18:56:24,577 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:56:24,577 INFO L276 IsEmpty]: Start isEmpty. Operand 62542 states and 218525 transitions. [2019-12-07 18:56:24,585 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-12-07 18:56:24,586 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:24,586 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:24,586 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:24,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:24,586 INFO L82 PathProgramCache]: Analyzing trace with hash 127408811, now seen corresponding path program 1 times [2019-12-07 18:56:24,586 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:24,586 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1728191058] [2019-12-07 18:56:24,586 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:24,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:24,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:24,636 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1728191058] [2019-12-07 18:56:24,636 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:24,636 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:56:24,636 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [150669941] [2019-12-07 18:56:24,637 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:56:24,637 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:24,637 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:56:24,637 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:56:24,637 INFO L87 Difference]: Start difference. First operand 62542 states and 218525 transitions. Second operand 5 states. [2019-12-07 18:56:25,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:25,153 INFO L93 Difference]: Finished difference Result 88931 states and 306134 transitions. [2019-12-07 18:56:25,153 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:56:25,154 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 24 [2019-12-07 18:56:25,154 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:25,303 INFO L225 Difference]: With dead ends: 88931 [2019-12-07 18:56:25,303 INFO L226 Difference]: Without dead ends: 88907 [2019-12-07 18:56:25,304 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:56:25,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88907 states. [2019-12-07 18:56:26,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88907 to 68768. [2019-12-07 18:56:26,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68768 states. [2019-12-07 18:56:27,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68768 states to 68768 states and 239569 transitions. [2019-12-07 18:56:27,091 INFO L78 Accepts]: Start accepts. Automaton has 68768 states and 239569 transitions. Word has length 24 [2019-12-07 18:56:27,091 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:27,091 INFO L462 AbstractCegarLoop]: Abstraction has 68768 states and 239569 transitions. [2019-12-07 18:56:27,091 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:56:27,091 INFO L276 IsEmpty]: Start isEmpty. Operand 68768 states and 239569 transitions. [2019-12-07 18:56:27,101 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-12-07 18:56:27,101 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:27,101 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:27,101 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:27,101 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:27,101 INFO L82 PathProgramCache]: Analyzing trace with hash 127528843, now seen corresponding path program 1 times [2019-12-07 18:56:27,101 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:27,102 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140621913] [2019-12-07 18:56:27,102 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:27,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:27,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:27,139 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [140621913] [2019-12-07 18:56:27,139 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:27,139 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:56:27,139 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [328942952] [2019-12-07 18:56:27,140 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:56:27,140 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:27,140 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:56:27,140 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:56:27,140 INFO L87 Difference]: Start difference. First operand 68768 states and 239569 transitions. Second operand 5 states. [2019-12-07 18:56:27,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:27,668 INFO L93 Difference]: Finished difference Result 90953 states and 312676 transitions. [2019-12-07 18:56:27,669 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:56:27,669 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 24 [2019-12-07 18:56:27,669 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:27,830 INFO L225 Difference]: With dead ends: 90953 [2019-12-07 18:56:27,830 INFO L226 Difference]: Without dead ends: 90929 [2019-12-07 18:56:27,830 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:56:28,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90929 states. [2019-12-07 18:56:28,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90929 to 63934. [2019-12-07 18:56:28,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63934 states. [2019-12-07 18:56:29,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63934 states to 63934 states and 222658 transitions. [2019-12-07 18:56:29,463 INFO L78 Accepts]: Start accepts. Automaton has 63934 states and 222658 transitions. Word has length 24 [2019-12-07 18:56:29,463 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:29,463 INFO L462 AbstractCegarLoop]: Abstraction has 63934 states and 222658 transitions. [2019-12-07 18:56:29,463 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:56:29,463 INFO L276 IsEmpty]: Start isEmpty. Operand 63934 states and 222658 transitions. [2019-12-07 18:56:29,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 18:56:29,487 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:29,488 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:29,488 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:29,488 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:29,488 INFO L82 PathProgramCache]: Analyzing trace with hash 459682268, now seen corresponding path program 1 times [2019-12-07 18:56:29,488 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:29,488 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [569788613] [2019-12-07 18:56:29,488 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:29,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:29,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:29,521 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [569788613] [2019-12-07 18:56:29,521 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:29,521 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:56:29,521 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [614724277] [2019-12-07 18:56:29,521 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:56:29,522 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:29,522 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:56:29,522 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:56:29,522 INFO L87 Difference]: Start difference. First operand 63934 states and 222658 transitions. Second operand 5 states. [2019-12-07 18:56:29,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:29,916 INFO L93 Difference]: Finished difference Result 85044 states and 292494 transitions. [2019-12-07 18:56:29,916 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:56:29,916 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 31 [2019-12-07 18:56:29,916 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:30,057 INFO L225 Difference]: With dead ends: 85044 [2019-12-07 18:56:30,057 INFO L226 Difference]: Without dead ends: 85017 [2019-12-07 18:56:30,057 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:56:30,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85017 states. [2019-12-07 18:56:31,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85017 to 70109. [2019-12-07 18:56:31,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70109 states. [2019-12-07 18:56:31,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70109 states to 70109 states and 243720 transitions. [2019-12-07 18:56:31,349 INFO L78 Accepts]: Start accepts. Automaton has 70109 states and 243720 transitions. Word has length 31 [2019-12-07 18:56:31,349 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:31,349 INFO L462 AbstractCegarLoop]: Abstraction has 70109 states and 243720 transitions. [2019-12-07 18:56:31,349 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:56:31,349 INFO L276 IsEmpty]: Start isEmpty. Operand 70109 states and 243720 transitions. [2019-12-07 18:56:31,381 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 18:56:31,381 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:31,381 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:31,382 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:31,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:31,382 INFO L82 PathProgramCache]: Analyzing trace with hash 1441773244, now seen corresponding path program 1 times [2019-12-07 18:56:31,382 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:31,382 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1299162734] [2019-12-07 18:56:31,382 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:31,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:31,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:31,406 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1299162734] [2019-12-07 18:56:31,406 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:31,406 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:56:31,406 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [672046992] [2019-12-07 18:56:31,406 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:56:31,407 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:31,407 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:56:31,407 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:56:31,407 INFO L87 Difference]: Start difference. First operand 70109 states and 243720 transitions. Second operand 3 states. [2019-12-07 18:56:31,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:31,839 INFO L93 Difference]: Finished difference Result 99408 states and 345793 transitions. [2019-12-07 18:56:31,840 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:56:31,840 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 31 [2019-12-07 18:56:31,840 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:32,025 INFO L225 Difference]: With dead ends: 99408 [2019-12-07 18:56:32,025 INFO L226 Difference]: Without dead ends: 99408 [2019-12-07 18:56:32,025 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:56:32,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99408 states. [2019-12-07 18:56:33,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99408 to 82230. [2019-12-07 18:56:33,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82230 states. [2019-12-07 18:56:33,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82230 states to 82230 states and 286116 transitions. [2019-12-07 18:56:33,510 INFO L78 Accepts]: Start accepts. Automaton has 82230 states and 286116 transitions. Word has length 31 [2019-12-07 18:56:33,510 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:33,510 INFO L462 AbstractCegarLoop]: Abstraction has 82230 states and 286116 transitions. [2019-12-07 18:56:33,510 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:56:33,510 INFO L276 IsEmpty]: Start isEmpty. Operand 82230 states and 286116 transitions. [2019-12-07 18:56:33,552 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-12-07 18:56:33,553 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:33,553 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:33,553 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:33,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:33,553 INFO L82 PathProgramCache]: Analyzing trace with hash -1101412888, now seen corresponding path program 1 times [2019-12-07 18:56:33,553 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:33,553 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1691978436] [2019-12-07 18:56:33,554 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:33,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:33,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:33,595 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1691978436] [2019-12-07 18:56:33,595 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:33,595 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:56:33,596 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2015052223] [2019-12-07 18:56:33,596 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:56:33,596 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:33,596 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:56:33,596 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:56:33,596 INFO L87 Difference]: Start difference. First operand 82230 states and 286116 transitions. Second operand 5 states. [2019-12-07 18:56:34,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:34,130 INFO L93 Difference]: Finished difference Result 98184 states and 335926 transitions. [2019-12-07 18:56:34,131 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:56:34,131 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 32 [2019-12-07 18:56:34,131 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:34,293 INFO L225 Difference]: With dead ends: 98184 [2019-12-07 18:56:34,293 INFO L226 Difference]: Without dead ends: 98158 [2019-12-07 18:56:34,293 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:56:34,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98158 states. [2019-12-07 18:56:35,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98158 to 80206. [2019-12-07 18:56:35,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80206 states. [2019-12-07 18:56:35,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80206 states to 80206 states and 279221 transitions. [2019-12-07 18:56:35,805 INFO L78 Accepts]: Start accepts. Automaton has 80206 states and 279221 transitions. Word has length 32 [2019-12-07 18:56:35,806 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:35,806 INFO L462 AbstractCegarLoop]: Abstraction has 80206 states and 279221 transitions. [2019-12-07 18:56:35,806 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:56:35,806 INFO L276 IsEmpty]: Start isEmpty. Operand 80206 states and 279221 transitions. [2019-12-07 18:56:35,844 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-12-07 18:56:35,844 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:35,844 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:35,844 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:35,844 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:35,845 INFO L82 PathProgramCache]: Analyzing trace with hash -917563487, now seen corresponding path program 1 times [2019-12-07 18:56:35,845 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:35,845 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039619210] [2019-12-07 18:56:35,845 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:35,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:36,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:36,065 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1039619210] [2019-12-07 18:56:36,065 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:36,065 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:56:36,065 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [181403249] [2019-12-07 18:56:36,065 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:56:36,065 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:36,065 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:56:36,065 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:56:36,065 INFO L87 Difference]: Start difference. First operand 80206 states and 279221 transitions. Second operand 5 states. [2019-12-07 18:56:36,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:36,682 INFO L93 Difference]: Finished difference Result 114657 states and 394025 transitions. [2019-12-07 18:56:36,682 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:56:36,682 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 32 [2019-12-07 18:56:36,683 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:36,893 INFO L225 Difference]: With dead ends: 114657 [2019-12-07 18:56:36,893 INFO L226 Difference]: Without dead ends: 114657 [2019-12-07 18:56:36,893 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:56:37,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114657 states. [2019-12-07 18:56:38,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114657 to 102063. [2019-12-07 18:56:38,709 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102063 states. [2019-12-07 18:56:38,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102063 states to 102063 states and 353591 transitions. [2019-12-07 18:56:38,932 INFO L78 Accepts]: Start accepts. Automaton has 102063 states and 353591 transitions. Word has length 32 [2019-12-07 18:56:38,932 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:38,932 INFO L462 AbstractCegarLoop]: Abstraction has 102063 states and 353591 transitions. [2019-12-07 18:56:38,932 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:56:38,932 INFO L276 IsEmpty]: Start isEmpty. Operand 102063 states and 353591 transitions. [2019-12-07 18:56:38,990 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-12-07 18:56:38,990 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:38,991 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:38,991 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:38,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:38,991 INFO L82 PathProgramCache]: Analyzing trace with hash 592862499, now seen corresponding path program 1 times [2019-12-07 18:56:38,991 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:38,991 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [548339274] [2019-12-07 18:56:38,991 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:39,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:39,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:39,037 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [548339274] [2019-12-07 18:56:39,038 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:39,038 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:56:39,038 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1855879418] [2019-12-07 18:56:39,038 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:56:39,038 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:39,038 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:56:39,039 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:56:39,039 INFO L87 Difference]: Start difference. First operand 102063 states and 353591 transitions. Second operand 5 states. [2019-12-07 18:56:39,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:39,781 INFO L93 Difference]: Finished difference Result 143120 states and 490601 transitions. [2019-12-07 18:56:39,781 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:56:39,781 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 32 [2019-12-07 18:56:39,781 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:40,047 INFO L225 Difference]: With dead ends: 143120 [2019-12-07 18:56:40,047 INFO L226 Difference]: Without dead ends: 143120 [2019-12-07 18:56:40,048 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:56:40,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143120 states. [2019-12-07 18:56:42,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143120 to 114391. [2019-12-07 18:56:42,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114391 states. [2019-12-07 18:56:42,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114391 states to 114391 states and 396191 transitions. [2019-12-07 18:56:42,280 INFO L78 Accepts]: Start accepts. Automaton has 114391 states and 396191 transitions. Word has length 32 [2019-12-07 18:56:42,280 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:42,280 INFO L462 AbstractCegarLoop]: Abstraction has 114391 states and 396191 transitions. [2019-12-07 18:56:42,280 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:56:42,280 INFO L276 IsEmpty]: Start isEmpty. Operand 114391 states and 396191 transitions. [2019-12-07 18:56:42,362 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 18:56:42,362 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:42,362 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:42,362 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:42,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:42,362 INFO L82 PathProgramCache]: Analyzing trace with hash -181451484, now seen corresponding path program 1 times [2019-12-07 18:56:42,363 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:42,363 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [663738130] [2019-12-07 18:56:42,363 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:42,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:42,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:42,561 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [663738130] [2019-12-07 18:56:42,561 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:42,561 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 18:56:42,561 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [977688566] [2019-12-07 18:56:42,561 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 18:56:42,561 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:42,561 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 18:56:42,562 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:56:42,562 INFO L87 Difference]: Start difference. First operand 114391 states and 396191 transitions. Second operand 8 states. [2019-12-07 18:56:44,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:44,007 INFO L93 Difference]: Finished difference Result 187703 states and 648418 transitions. [2019-12-07 18:56:44,007 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 18:56:44,007 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 33 [2019-12-07 18:56:44,008 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:44,321 INFO L225 Difference]: With dead ends: 187703 [2019-12-07 18:56:44,321 INFO L226 Difference]: Without dead ends: 177069 [2019-12-07 18:56:44,321 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=50, Invalid=106, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:56:44,863 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177069 states. [2019-12-07 18:56:46,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177069 to 136541. [2019-12-07 18:56:46,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136541 states. [2019-12-07 18:56:47,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136541 states to 136541 states and 478115 transitions. [2019-12-07 18:56:47,052 INFO L78 Accepts]: Start accepts. Automaton has 136541 states and 478115 transitions. Word has length 33 [2019-12-07 18:56:47,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:47,053 INFO L462 AbstractCegarLoop]: Abstraction has 136541 states and 478115 transitions. [2019-12-07 18:56:47,053 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 18:56:47,053 INFO L276 IsEmpty]: Start isEmpty. Operand 136541 states and 478115 transitions. [2019-12-07 18:56:47,157 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 18:56:47,157 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:47,157 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:47,157 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:47,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:47,158 INFO L82 PathProgramCache]: Analyzing trace with hash -1932693659, now seen corresponding path program 1 times [2019-12-07 18:56:47,158 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:47,158 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1111616036] [2019-12-07 18:56:47,158 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:47,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:47,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:47,205 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1111616036] [2019-12-07 18:56:47,206 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:47,206 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:56:47,206 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1171212935] [2019-12-07 18:56:47,206 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:56:47,206 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:47,206 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:56:47,207 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:56:47,207 INFO L87 Difference]: Start difference. First operand 136541 states and 478115 transitions. Second operand 3 states. [2019-12-07 18:56:47,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:47,677 INFO L93 Difference]: Finished difference Result 132328 states and 461391 transitions. [2019-12-07 18:56:47,677 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:56:47,678 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 33 [2019-12-07 18:56:47,678 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:47,933 INFO L225 Difference]: With dead ends: 132328 [2019-12-07 18:56:47,933 INFO L226 Difference]: Without dead ends: 132328 [2019-12-07 18:56:47,933 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:56:48,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132328 states. [2019-12-07 18:56:49,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132328 to 123941. [2019-12-07 18:56:49,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 123941 states. [2019-12-07 18:56:50,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123941 states to 123941 states and 432292 transitions. [2019-12-07 18:56:50,208 INFO L78 Accepts]: Start accepts. Automaton has 123941 states and 432292 transitions. Word has length 33 [2019-12-07 18:56:50,208 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:50,208 INFO L462 AbstractCegarLoop]: Abstraction has 123941 states and 432292 transitions. [2019-12-07 18:56:50,208 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:56:50,208 INFO L276 IsEmpty]: Start isEmpty. Operand 123941 states and 432292 transitions. [2019-12-07 18:56:50,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 18:56:50,304 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:50,304 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:50,304 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:50,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:50,304 INFO L82 PathProgramCache]: Analyzing trace with hash 1080944817, now seen corresponding path program 1 times [2019-12-07 18:56:50,304 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:50,304 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635084824] [2019-12-07 18:56:50,305 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:50,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:50,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:50,341 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1635084824] [2019-12-07 18:56:50,341 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:50,341 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:56:50,341 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [405738966] [2019-12-07 18:56:50,341 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:56:50,341 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:50,341 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:56:50,342 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:56:50,342 INFO L87 Difference]: Start difference. First operand 123941 states and 432292 transitions. Second operand 5 states. [2019-12-07 18:56:50,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:50,588 INFO L93 Difference]: Finished difference Result 68809 states and 247678 transitions. [2019-12-07 18:56:50,588 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:56:50,588 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 33 [2019-12-07 18:56:50,588 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:50,708 INFO L225 Difference]: With dead ends: 68809 [2019-12-07 18:56:50,708 INFO L226 Difference]: Without dead ends: 68809 [2019-12-07 18:56:50,709 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:56:50,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68809 states. [2019-12-07 18:56:51,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68809 to 53817. [2019-12-07 18:56:51,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53817 states. [2019-12-07 18:56:51,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53817 states to 53817 states and 187789 transitions. [2019-12-07 18:56:51,863 INFO L78 Accepts]: Start accepts. Automaton has 53817 states and 187789 transitions. Word has length 33 [2019-12-07 18:56:51,864 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:51,864 INFO L462 AbstractCegarLoop]: Abstraction has 53817 states and 187789 transitions. [2019-12-07 18:56:51,864 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:56:51,864 INFO L276 IsEmpty]: Start isEmpty. Operand 53817 states and 187789 transitions. [2019-12-07 18:56:51,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2019-12-07 18:56:51,933 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:51,933 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:51,933 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:51,933 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:51,933 INFO L82 PathProgramCache]: Analyzing trace with hash 301569509, now seen corresponding path program 1 times [2019-12-07 18:56:51,933 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:51,934 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1595829273] [2019-12-07 18:56:51,934 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:51,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:51,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:51,994 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1595829273] [2019-12-07 18:56:51,995 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:51,995 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:56:51,995 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1747374034] [2019-12-07 18:56:51,995 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:56:51,995 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:51,995 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:56:51,995 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:56:51,995 INFO L87 Difference]: Start difference. First operand 53817 states and 187789 transitions. Second operand 6 states. [2019-12-07 18:56:52,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:52,569 INFO L93 Difference]: Finished difference Result 65494 states and 225148 transitions. [2019-12-07 18:56:52,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 18:56:52,569 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 43 [2019-12-07 18:56:52,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:52,679 INFO L225 Difference]: With dead ends: 65494 [2019-12-07 18:56:52,679 INFO L226 Difference]: Without dead ends: 65402 [2019-12-07 18:56:52,680 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=47, Invalid=109, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:56:52,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65402 states. [2019-12-07 18:56:53,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65402 to 54481. [2019-12-07 18:56:53,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54481 states. [2019-12-07 18:56:53,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54481 states to 54481 states and 190010 transitions. [2019-12-07 18:56:53,685 INFO L78 Accepts]: Start accepts. Automaton has 54481 states and 190010 transitions. Word has length 43 [2019-12-07 18:56:53,685 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:53,685 INFO L462 AbstractCegarLoop]: Abstraction has 54481 states and 190010 transitions. [2019-12-07 18:56:53,685 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:56:53,685 INFO L276 IsEmpty]: Start isEmpty. Operand 54481 states and 190010 transitions. [2019-12-07 18:56:53,755 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2019-12-07 18:56:53,755 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:53,755 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:53,755 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:53,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:53,756 INFO L82 PathProgramCache]: Analyzing trace with hash 1643904346, now seen corresponding path program 1 times [2019-12-07 18:56:53,756 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:53,756 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [406673626] [2019-12-07 18:56:53,756 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:53,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:53,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:53,794 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [406673626] [2019-12-07 18:56:53,794 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:53,794 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:56:53,794 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1381370837] [2019-12-07 18:56:53,794 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:56:53,795 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:53,795 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:56:53,795 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:56:53,795 INFO L87 Difference]: Start difference. First operand 54481 states and 190010 transitions. Second operand 4 states. [2019-12-07 18:56:54,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:54,129 INFO L93 Difference]: Finished difference Result 91331 states and 319682 transitions. [2019-12-07 18:56:54,129 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:56:54,129 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 43 [2019-12-07 18:56:54,129 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:54,198 INFO L225 Difference]: With dead ends: 91331 [2019-12-07 18:56:54,198 INFO L226 Difference]: Without dead ends: 46260 [2019-12-07 18:56:54,199 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:56:54,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46260 states. [2019-12-07 18:56:54,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46260 to 46022. [2019-12-07 18:56:54,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46022 states. [2019-12-07 18:56:54,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46022 states to 46022 states and 160392 transitions. [2019-12-07 18:56:54,954 INFO L78 Accepts]: Start accepts. Automaton has 46022 states and 160392 transitions. Word has length 43 [2019-12-07 18:56:54,954 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:54,954 INFO L462 AbstractCegarLoop]: Abstraction has 46022 states and 160392 transitions. [2019-12-07 18:56:54,954 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:56:54,954 INFO L276 IsEmpty]: Start isEmpty. Operand 46022 states and 160392 transitions. [2019-12-07 18:56:55,018 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2019-12-07 18:56:55,018 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:55,018 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:55,018 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:55,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:55,018 INFO L82 PathProgramCache]: Analyzing trace with hash -1477031722, now seen corresponding path program 2 times [2019-12-07 18:56:55,018 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:55,019 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1329884927] [2019-12-07 18:56:55,019 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:55,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:55,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:55,046 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1329884927] [2019-12-07 18:56:55,046 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:55,047 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:56:55,047 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [137678899] [2019-12-07 18:56:55,047 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:56:55,047 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:55,047 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:56:55,047 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:56:55,047 INFO L87 Difference]: Start difference. First operand 46022 states and 160392 transitions. Second operand 3 states. [2019-12-07 18:56:55,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:55,172 INFO L93 Difference]: Finished difference Result 39004 states and 134034 transitions. [2019-12-07 18:56:55,173 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:56:55,173 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 43 [2019-12-07 18:56:55,173 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:55,233 INFO L225 Difference]: With dead ends: 39004 [2019-12-07 18:56:55,234 INFO L226 Difference]: Without dead ends: 39004 [2019-12-07 18:56:55,234 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:56:55,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39004 states. [2019-12-07 18:56:55,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39004 to 37975. [2019-12-07 18:56:55,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37975 states. [2019-12-07 18:56:55,827 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37975 states to 37975 states and 130835 transitions. [2019-12-07 18:56:55,827 INFO L78 Accepts]: Start accepts. Automaton has 37975 states and 130835 transitions. Word has length 43 [2019-12-07 18:56:55,827 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:55,827 INFO L462 AbstractCegarLoop]: Abstraction has 37975 states and 130835 transitions. [2019-12-07 18:56:55,827 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:56:55,827 INFO L276 IsEmpty]: Start isEmpty. Operand 37975 states and 130835 transitions. [2019-12-07 18:56:55,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2019-12-07 18:56:55,867 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:55,868 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:55,868 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:55,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:55,868 INFO L82 PathProgramCache]: Analyzing trace with hash -925128929, now seen corresponding path program 1 times [2019-12-07 18:56:55,868 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:55,868 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1690003226] [2019-12-07 18:56:55,868 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:55,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:55,916 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:55,917 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1690003226] [2019-12-07 18:56:55,917 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:55,917 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:56:55,917 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489548897] [2019-12-07 18:56:55,917 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:56:55,917 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:55,917 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:56:55,917 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:56:55,917 INFO L87 Difference]: Start difference. First operand 37975 states and 130835 transitions. Second operand 6 states. [2019-12-07 18:56:56,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:56,320 INFO L93 Difference]: Finished difference Result 43806 states and 148028 transitions. [2019-12-07 18:56:56,320 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 18:56:56,320 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 44 [2019-12-07 18:56:56,320 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:56,456 INFO L225 Difference]: With dead ends: 43806 [2019-12-07 18:56:56,456 INFO L226 Difference]: Without dead ends: 43714 [2019-12-07 18:56:56,457 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=40, Invalid=92, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:56:56,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43714 states. [2019-12-07 18:56:56,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43714 to 35924. [2019-12-07 18:56:56,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35924 states. [2019-12-07 18:56:57,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35924 states to 35924 states and 124360 transitions. [2019-12-07 18:56:57,031 INFO L78 Accepts]: Start accepts. Automaton has 35924 states and 124360 transitions. Word has length 44 [2019-12-07 18:56:57,031 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:57,031 INFO L462 AbstractCegarLoop]: Abstraction has 35924 states and 124360 transitions. [2019-12-07 18:56:57,031 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:56:57,032 INFO L276 IsEmpty]: Start isEmpty. Operand 35924 states and 124360 transitions. [2019-12-07 18:56:57,069 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2019-12-07 18:56:57,069 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:57,070 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:57,070 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:57,070 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:57,070 INFO L82 PathProgramCache]: Analyzing trace with hash -45425920, now seen corresponding path program 1 times [2019-12-07 18:56:57,070 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:57,070 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1090854398] [2019-12-07 18:56:57,070 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:57,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:57,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:57,112 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1090854398] [2019-12-07 18:56:57,112 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:57,112 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:56:57,112 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1155621212] [2019-12-07 18:56:57,113 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:56:57,113 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:57,113 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:56:57,113 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:56:57,113 INFO L87 Difference]: Start difference. First operand 35924 states and 124360 transitions. Second operand 6 states. [2019-12-07 18:56:57,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:57,249 INFO L93 Difference]: Finished difference Result 34037 states and 119834 transitions. [2019-12-07 18:56:57,249 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:56:57,249 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 44 [2019-12-07 18:56:57,249 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:57,304 INFO L225 Difference]: With dead ends: 34037 [2019-12-07 18:56:57,304 INFO L226 Difference]: Without dead ends: 31925 [2019-12-07 18:56:57,304 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:56:57,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31925 states. [2019-12-07 18:56:57,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31925 to 22456. [2019-12-07 18:56:57,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22456 states. [2019-12-07 18:56:57,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22456 states to 22456 states and 83042 transitions. [2019-12-07 18:56:57,737 INFO L78 Accepts]: Start accepts. Automaton has 22456 states and 83042 transitions. Word has length 44 [2019-12-07 18:56:57,737 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:57,737 INFO L462 AbstractCegarLoop]: Abstraction has 22456 states and 83042 transitions. [2019-12-07 18:56:57,737 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:56:57,737 INFO L276 IsEmpty]: Start isEmpty. Operand 22456 states and 83042 transitions. [2019-12-07 18:56:57,762 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 18:56:57,762 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:57,762 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:57,763 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:57,763 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:57,763 INFO L82 PathProgramCache]: Analyzing trace with hash 755425574, now seen corresponding path program 1 times [2019-12-07 18:56:57,763 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:57,763 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1616786394] [2019-12-07 18:56:57,763 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:57,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:57,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:57,813 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1616786394] [2019-12-07 18:56:57,814 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:57,814 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:56:57,814 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [990515623] [2019-12-07 18:56:57,814 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:56:57,814 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:57,814 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:56:57,814 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:56:57,814 INFO L87 Difference]: Start difference. First operand 22456 states and 83042 transitions. Second operand 5 states. [2019-12-07 18:56:57,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:57,918 INFO L93 Difference]: Finished difference Result 31267 states and 111215 transitions. [2019-12-07 18:56:57,919 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:56:57,919 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 59 [2019-12-07 18:56:57,919 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:57,952 INFO L225 Difference]: With dead ends: 31267 [2019-12-07 18:56:57,952 INFO L226 Difference]: Without dead ends: 20124 [2019-12-07 18:56:57,953 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:56:58,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20124 states. [2019-12-07 18:56:58,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20124 to 20124. [2019-12-07 18:56:58,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20124 states. [2019-12-07 18:56:58,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20124 states to 20124 states and 73222 transitions. [2019-12-07 18:56:58,279 INFO L78 Accepts]: Start accepts. Automaton has 20124 states and 73222 transitions. Word has length 59 [2019-12-07 18:56:58,279 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:58,279 INFO L462 AbstractCegarLoop]: Abstraction has 20124 states and 73222 transitions. [2019-12-07 18:56:58,279 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:56:58,279 INFO L276 IsEmpty]: Start isEmpty. Operand 20124 states and 73222 transitions. [2019-12-07 18:56:58,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 18:56:58,301 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:58,301 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:58,301 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:58,301 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:58,301 INFO L82 PathProgramCache]: Analyzing trace with hash 696293578, now seen corresponding path program 2 times [2019-12-07 18:56:58,301 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:58,301 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1264801622] [2019-12-07 18:56:58,302 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:58,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:58,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:58,365 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1264801622] [2019-12-07 18:56:58,365 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:58,365 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:56:58,365 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [154144808] [2019-12-07 18:56:58,366 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:56:58,366 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:58,366 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:56:58,366 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:56:58,366 INFO L87 Difference]: Start difference. First operand 20124 states and 73222 transitions. Second operand 5 states. [2019-12-07 18:56:58,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:58,467 INFO L93 Difference]: Finished difference Result 27370 states and 96605 transitions. [2019-12-07 18:56:58,467 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:56:58,467 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 59 [2019-12-07 18:56:58,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:58,475 INFO L225 Difference]: With dead ends: 27370 [2019-12-07 18:56:58,476 INFO L226 Difference]: Without dead ends: 7800 [2019-12-07 18:56:58,476 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:56:58,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7800 states. [2019-12-07 18:56:58,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7800 to 7800. [2019-12-07 18:56:58,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7800 states. [2019-12-07 18:56:58,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7800 states to 7800 states and 24895 transitions. [2019-12-07 18:56:58,583 INFO L78 Accepts]: Start accepts. Automaton has 7800 states and 24895 transitions. Word has length 59 [2019-12-07 18:56:58,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:58,583 INFO L462 AbstractCegarLoop]: Abstraction has 7800 states and 24895 transitions. [2019-12-07 18:56:58,583 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:56:58,583 INFO L276 IsEmpty]: Start isEmpty. Operand 7800 states and 24895 transitions. [2019-12-07 18:56:58,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 18:56:58,589 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:58,589 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:58,590 INFO L410 AbstractCegarLoop]: === Iteration 29 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:58,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:58,590 INFO L82 PathProgramCache]: Analyzing trace with hash 1949196794, now seen corresponding path program 3 times [2019-12-07 18:56:58,590 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:58,590 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [470708840] [2019-12-07 18:56:58,590 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:58,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:58,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:58,699 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [470708840] [2019-12-07 18:56:58,699 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:58,699 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:56:58,699 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1903908675] [2019-12-07 18:56:58,700 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 18:56:58,700 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:58,700 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 18:56:58,700 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:56:58,700 INFO L87 Difference]: Start difference. First operand 7800 states and 24895 transitions. Second operand 10 states. [2019-12-07 18:56:59,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:59,487 INFO L93 Difference]: Finished difference Result 15593 states and 48625 transitions. [2019-12-07 18:56:59,487 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 18:56:59,487 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 59 [2019-12-07 18:56:59,487 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:59,497 INFO L225 Difference]: With dead ends: 15593 [2019-12-07 18:56:59,497 INFO L226 Difference]: Without dead ends: 10260 [2019-12-07 18:56:59,498 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 75 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=100, Invalid=406, Unknown=0, NotChecked=0, Total=506 [2019-12-07 18:56:59,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10260 states. [2019-12-07 18:56:59,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10260 to 9486. [2019-12-07 18:56:59,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9486 states. [2019-12-07 18:56:59,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9486 states to 9486 states and 29718 transitions. [2019-12-07 18:56:59,628 INFO L78 Accepts]: Start accepts. Automaton has 9486 states and 29718 transitions. Word has length 59 [2019-12-07 18:56:59,628 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:59,628 INFO L462 AbstractCegarLoop]: Abstraction has 9486 states and 29718 transitions. [2019-12-07 18:56:59,628 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 18:56:59,628 INFO L276 IsEmpty]: Start isEmpty. Operand 9486 states and 29718 transitions. [2019-12-07 18:56:59,636 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 18:56:59,636 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:59,636 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:59,636 INFO L410 AbstractCegarLoop]: === Iteration 30 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:59,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:59,636 INFO L82 PathProgramCache]: Analyzing trace with hash -1854145516, now seen corresponding path program 4 times [2019-12-07 18:56:59,637 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:59,637 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1626724935] [2019-12-07 18:56:59,637 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:59,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:59,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:59,968 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1626724935] [2019-12-07 18:56:59,968 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:59,968 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 18:56:59,968 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8571311] [2019-12-07 18:56:59,968 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 18:56:59,969 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:59,969 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 18:56:59,969 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=178, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:56:59,969 INFO L87 Difference]: Start difference. First operand 9486 states and 29718 transitions. Second operand 15 states. [2019-12-07 18:57:04,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:04,062 INFO L93 Difference]: Finished difference Result 14959 states and 45959 transitions. [2019-12-07 18:57:04,063 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-12-07 18:57:04,063 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 59 [2019-12-07 18:57:04,063 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:04,089 INFO L225 Difference]: With dead ends: 14959 [2019-12-07 18:57:04,089 INFO L226 Difference]: Without dead ends: 14637 [2019-12-07 18:57:04,090 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 562 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=339, Invalid=2013, Unknown=0, NotChecked=0, Total=2352 [2019-12-07 18:57:04,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14637 states. [2019-12-07 18:57:04,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14637 to 12007. [2019-12-07 18:57:04,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12007 states. [2019-12-07 18:57:04,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12007 states to 12007 states and 37378 transitions. [2019-12-07 18:57:04,278 INFO L78 Accepts]: Start accepts. Automaton has 12007 states and 37378 transitions. Word has length 59 [2019-12-07 18:57:04,278 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:04,278 INFO L462 AbstractCegarLoop]: Abstraction has 12007 states and 37378 transitions. [2019-12-07 18:57:04,278 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 18:57:04,279 INFO L276 IsEmpty]: Start isEmpty. Operand 12007 states and 37378 transitions. [2019-12-07 18:57:04,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 18:57:04,289 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:04,290 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:04,290 INFO L410 AbstractCegarLoop]: === Iteration 31 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:04,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:04,290 INFO L82 PathProgramCache]: Analyzing trace with hash -1037039724, now seen corresponding path program 5 times [2019-12-07 18:57:04,290 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:04,290 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472237352] [2019-12-07 18:57:04,291 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:04,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:04,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:04,628 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1472237352] [2019-12-07 18:57:04,628 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:04,628 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 18:57:04,628 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1894313028] [2019-12-07 18:57:04,629 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 18:57:04,629 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:04,629 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 18:57:04,629 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=173, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:57:04,629 INFO L87 Difference]: Start difference. First operand 12007 states and 37378 transitions. Second operand 15 states. [2019-12-07 18:57:06,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:06,691 INFO L93 Difference]: Finished difference Result 15178 states and 46324 transitions. [2019-12-07 18:57:06,691 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-12-07 18:57:06,691 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 59 [2019-12-07 18:57:06,691 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:06,706 INFO L225 Difference]: With dead ends: 15178 [2019-12-07 18:57:06,706 INFO L226 Difference]: Without dead ends: 13740 [2019-12-07 18:57:06,707 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 249 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=185, Invalid=937, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 18:57:06,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13740 states. [2019-12-07 18:57:06,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13740 to 11412. [2019-12-07 18:57:06,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11412 states. [2019-12-07 18:57:06,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11412 states to 11412 states and 35352 transitions. [2019-12-07 18:57:06,874 INFO L78 Accepts]: Start accepts. Automaton has 11412 states and 35352 transitions. Word has length 59 [2019-12-07 18:57:06,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:06,875 INFO L462 AbstractCegarLoop]: Abstraction has 11412 states and 35352 transitions. [2019-12-07 18:57:06,875 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 18:57:06,875 INFO L276 IsEmpty]: Start isEmpty. Operand 11412 states and 35352 transitions. [2019-12-07 18:57:06,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 18:57:06,884 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:06,884 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:06,884 INFO L410 AbstractCegarLoop]: === Iteration 32 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:06,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:06,884 INFO L82 PathProgramCache]: Analyzing trace with hash -448038556, now seen corresponding path program 6 times [2019-12-07 18:57:06,884 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:06,884 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797661933] [2019-12-07 18:57:06,885 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:06,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:07,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:07,175 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1797661933] [2019-12-07 18:57:07,175 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:07,175 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 18:57:07,175 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1936806127] [2019-12-07 18:57:07,176 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 18:57:07,176 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:07,176 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 18:57:07,176 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=170, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:57:07,176 INFO L87 Difference]: Start difference. First operand 11412 states and 35352 transitions. Second operand 15 states. [2019-12-07 18:57:09,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:09,492 INFO L93 Difference]: Finished difference Result 16800 states and 51097 transitions. [2019-12-07 18:57:09,493 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2019-12-07 18:57:09,493 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 59 [2019-12-07 18:57:09,494 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:09,517 INFO L225 Difference]: With dead ends: 16800 [2019-12-07 18:57:09,518 INFO L226 Difference]: Without dead ends: 13364 [2019-12-07 18:57:09,518 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 0 SyntacticMatches, 3 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 307 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=230, Invalid=1102, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 18:57:09,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13364 states. [2019-12-07 18:57:09,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13364 to 10921. [2019-12-07 18:57:09,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10921 states. [2019-12-07 18:57:09,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10921 states to 10921 states and 34036 transitions. [2019-12-07 18:57:09,687 INFO L78 Accepts]: Start accepts. Automaton has 10921 states and 34036 transitions. Word has length 59 [2019-12-07 18:57:09,687 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:09,687 INFO L462 AbstractCegarLoop]: Abstraction has 10921 states and 34036 transitions. [2019-12-07 18:57:09,687 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 18:57:09,687 INFO L276 IsEmpty]: Start isEmpty. Operand 10921 states and 34036 transitions. [2019-12-07 18:57:09,697 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 18:57:09,697 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:09,697 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:09,697 INFO L410 AbstractCegarLoop]: === Iteration 33 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:09,697 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:09,697 INFO L82 PathProgramCache]: Analyzing trace with hash -1277650624, now seen corresponding path program 7 times [2019-12-07 18:57:09,697 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:09,697 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [955625231] [2019-12-07 18:57:09,698 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:09,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:09,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:09,804 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [955625231] [2019-12-07 18:57:09,804 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:09,804 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:57:09,804 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [446809980] [2019-12-07 18:57:09,804 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:57:09,804 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:09,804 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:57:09,805 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:57:09,805 INFO L87 Difference]: Start difference. First operand 10921 states and 34036 transitions. Second operand 11 states. [2019-12-07 18:57:11,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:11,020 INFO L93 Difference]: Finished difference Result 14531 states and 44691 transitions. [2019-12-07 18:57:11,020 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 18:57:11,020 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 59 [2019-12-07 18:57:11,020 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:11,032 INFO L225 Difference]: With dead ends: 14531 [2019-12-07 18:57:11,032 INFO L226 Difference]: Without dead ends: 11936 [2019-12-07 18:57:11,033 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 67 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=87, Invalid=419, Unknown=0, NotChecked=0, Total=506 [2019-12-07 18:57:11,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11936 states. [2019-12-07 18:57:11,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11936 to 10714. [2019-12-07 18:57:11,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10714 states. [2019-12-07 18:57:11,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10714 states to 10714 states and 33396 transitions. [2019-12-07 18:57:11,189 INFO L78 Accepts]: Start accepts. Automaton has 10714 states and 33396 transitions. Word has length 59 [2019-12-07 18:57:11,189 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:11,189 INFO L462 AbstractCegarLoop]: Abstraction has 10714 states and 33396 transitions. [2019-12-07 18:57:11,189 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:57:11,189 INFO L276 IsEmpty]: Start isEmpty. Operand 10714 states and 33396 transitions. [2019-12-07 18:57:11,198 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 18:57:11,198 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:11,198 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:11,198 INFO L410 AbstractCegarLoop]: === Iteration 34 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:11,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:11,199 INFO L82 PathProgramCache]: Analyzing trace with hash -794252350, now seen corresponding path program 8 times [2019-12-07 18:57:11,199 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:11,199 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745710041] [2019-12-07 18:57:11,199 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:11,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:11,291 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:11,291 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1745710041] [2019-12-07 18:57:11,292 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:11,292 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:57:11,292 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [674466642] [2019-12-07 18:57:11,292 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 18:57:11,292 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:11,292 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 18:57:11,292 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:57:11,292 INFO L87 Difference]: Start difference. First operand 10714 states and 33396 transitions. Second operand 10 states. [2019-12-07 18:57:11,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:11,687 INFO L93 Difference]: Finished difference Result 15734 states and 48883 transitions. [2019-12-07 18:57:11,687 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-12-07 18:57:11,687 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 59 [2019-12-07 18:57:11,687 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:11,704 INFO L225 Difference]: With dead ends: 15734 [2019-12-07 18:57:11,704 INFO L226 Difference]: Without dead ends: 15040 [2019-12-07 18:57:11,704 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 119 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=132, Invalid=518, Unknown=0, NotChecked=0, Total=650 [2019-12-07 18:57:11,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15040 states. [2019-12-07 18:57:11,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15040 to 12934. [2019-12-07 18:57:11,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12934 states. [2019-12-07 18:57:11,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12934 states to 12934 states and 40315 transitions. [2019-12-07 18:57:11,902 INFO L78 Accepts]: Start accepts. Automaton has 12934 states and 40315 transitions. Word has length 59 [2019-12-07 18:57:11,903 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:11,903 INFO L462 AbstractCegarLoop]: Abstraction has 12934 states and 40315 transitions. [2019-12-07 18:57:11,903 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 18:57:11,903 INFO L276 IsEmpty]: Start isEmpty. Operand 12934 states and 40315 transitions. [2019-12-07 18:57:11,915 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 18:57:11,915 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:11,915 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:11,915 INFO L410 AbstractCegarLoop]: === Iteration 35 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:11,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:11,915 INFO L82 PathProgramCache]: Analyzing trace with hash 22853442, now seen corresponding path program 9 times [2019-12-07 18:57:11,915 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:11,915 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1181942728] [2019-12-07 18:57:11,915 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:11,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:12,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:12,012 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1181942728] [2019-12-07 18:57:12,012 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:12,013 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:57:12,013 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2038460843] [2019-12-07 18:57:12,013 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 18:57:12,013 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:12,013 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 18:57:12,013 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:57:12,013 INFO L87 Difference]: Start difference. First operand 12934 states and 40315 transitions. Second operand 10 states. [2019-12-07 18:57:12,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:12,588 INFO L93 Difference]: Finished difference Result 14750 states and 45255 transitions. [2019-12-07 18:57:12,589 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-12-07 18:57:12,589 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 59 [2019-12-07 18:57:12,589 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:12,603 INFO L225 Difference]: With dead ends: 14750 [2019-12-07 18:57:12,603 INFO L226 Difference]: Without dead ends: 11147 [2019-12-07 18:57:12,603 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 96 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=110, Invalid=442, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:57:12,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11147 states. [2019-12-07 18:57:12,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11147 to 9717. [2019-12-07 18:57:12,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9717 states. [2019-12-07 18:57:12,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9717 states to 9717 states and 30078 transitions. [2019-12-07 18:57:12,742 INFO L78 Accepts]: Start accepts. Automaton has 9717 states and 30078 transitions. Word has length 59 [2019-12-07 18:57:12,742 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:12,742 INFO L462 AbstractCegarLoop]: Abstraction has 9717 states and 30078 transitions. [2019-12-07 18:57:12,742 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 18:57:12,742 INFO L276 IsEmpty]: Start isEmpty. Operand 9717 states and 30078 transitions. [2019-12-07 18:57:12,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 18:57:12,750 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:12,750 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:12,750 INFO L410 AbstractCegarLoop]: === Iteration 36 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:12,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:12,750 INFO L82 PathProgramCache]: Analyzing trace with hash 1656101628, now seen corresponding path program 10 times [2019-12-07 18:57:12,751 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:12,751 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094134202] [2019-12-07 18:57:12,751 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:12,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:12,902 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:12,902 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1094134202] [2019-12-07 18:57:12,902 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:12,902 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 18:57:12,902 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1493034436] [2019-12-07 18:57:12,902 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 18:57:12,902 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:12,903 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 18:57:12,903 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=109, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:57:12,903 INFO L87 Difference]: Start difference. First operand 9717 states and 30078 transitions. Second operand 12 states. [2019-12-07 18:57:13,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:13,431 INFO L93 Difference]: Finished difference Result 13492 states and 41800 transitions. [2019-12-07 18:57:13,431 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 18:57:13,431 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 59 [2019-12-07 18:57:13,431 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:13,445 INFO L225 Difference]: With dead ends: 13492 [2019-12-07 18:57:13,445 INFO L226 Difference]: Without dead ends: 13182 [2019-12-07 18:57:13,445 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 87 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=115, Invalid=535, Unknown=0, NotChecked=0, Total=650 [2019-12-07 18:57:13,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13182 states. [2019-12-07 18:57:13,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13182 to 12468. [2019-12-07 18:57:13,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12468 states. [2019-12-07 18:57:13,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12468 states to 12468 states and 38722 transitions. [2019-12-07 18:57:13,632 INFO L78 Accepts]: Start accepts. Automaton has 12468 states and 38722 transitions. Word has length 59 [2019-12-07 18:57:13,632 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:13,632 INFO L462 AbstractCegarLoop]: Abstraction has 12468 states and 38722 transitions. [2019-12-07 18:57:13,632 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 18:57:13,632 INFO L276 IsEmpty]: Start isEmpty. Operand 12468 states and 38722 transitions. [2019-12-07 18:57:13,644 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 18:57:13,644 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:13,644 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:13,644 INFO L410 AbstractCegarLoop]: === Iteration 37 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:13,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:13,644 INFO L82 PathProgramCache]: Analyzing trace with hash -1821759876, now seen corresponding path program 11 times [2019-12-07 18:57:13,644 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:13,644 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1452143729] [2019-12-07 18:57:13,644 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:13,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:14,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:14,183 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1452143729] [2019-12-07 18:57:14,183 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:14,183 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 18:57:14,184 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [815456344] [2019-12-07 18:57:14,184 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 18:57:14,184 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:14,184 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 18:57:14,184 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2019-12-07 18:57:14,184 INFO L87 Difference]: Start difference. First operand 12468 states and 38722 transitions. Second operand 17 states. [2019-12-07 18:57:16,460 WARN L192 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 35 DAG size of output: 29 [2019-12-07 18:57:17,307 WARN L192 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 38 DAG size of output: 33 [2019-12-07 18:57:17,782 WARN L192 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 36 [2019-12-07 18:57:19,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:19,336 INFO L93 Difference]: Finished difference Result 32993 states and 100046 transitions. [2019-12-07 18:57:19,337 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2019-12-07 18:57:19,337 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 59 [2019-12-07 18:57:19,337 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:19,382 INFO L225 Difference]: With dead ends: 32993 [2019-12-07 18:57:19,382 INFO L226 Difference]: Without dead ends: 30222 [2019-12-07 18:57:19,384 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 977 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=556, Invalid=3104, Unknown=0, NotChecked=0, Total=3660 [2019-12-07 18:57:19,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30222 states. [2019-12-07 18:57:19,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30222 to 13192. [2019-12-07 18:57:19,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13192 states. [2019-12-07 18:57:19,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13192 states to 13192 states and 40959 transitions. [2019-12-07 18:57:19,685 INFO L78 Accepts]: Start accepts. Automaton has 13192 states and 40959 transitions. Word has length 59 [2019-12-07 18:57:19,685 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:19,685 INFO L462 AbstractCegarLoop]: Abstraction has 13192 states and 40959 transitions. [2019-12-07 18:57:19,685 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 18:57:19,686 INFO L276 IsEmpty]: Start isEmpty. Operand 13192 states and 40959 transitions. [2019-12-07 18:57:19,698 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 18:57:19,698 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:19,698 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:19,698 INFO L410 AbstractCegarLoop]: === Iteration 38 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:19,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:19,699 INFO L82 PathProgramCache]: Analyzing trace with hash -1659862276, now seen corresponding path program 12 times [2019-12-07 18:57:19,699 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:19,699 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1525993633] [2019-12-07 18:57:19,699 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:19,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:19,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:19,792 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1525993633] [2019-12-07 18:57:19,792 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:19,792 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:57:19,792 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1545227619] [2019-12-07 18:57:19,792 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:57:19,792 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:19,792 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:57:19,793 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:57:19,793 INFO L87 Difference]: Start difference. First operand 13192 states and 40959 transitions. Second operand 11 states. [2019-12-07 18:57:20,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:20,176 INFO L93 Difference]: Finished difference Result 14418 states and 44076 transitions. [2019-12-07 18:57:20,177 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 18:57:20,177 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 59 [2019-12-07 18:57:20,177 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:20,187 INFO L225 Difference]: With dead ends: 14418 [2019-12-07 18:57:20,187 INFO L226 Difference]: Without dead ends: 10367 [2019-12-07 18:57:20,188 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=122, Invalid=478, Unknown=0, NotChecked=0, Total=600 [2019-12-07 18:57:20,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10367 states. [2019-12-07 18:57:20,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10367 to 9365. [2019-12-07 18:57:20,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9365 states. [2019-12-07 18:57:20,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9365 states to 9365 states and 28995 transitions. [2019-12-07 18:57:20,317 INFO L78 Accepts]: Start accepts. Automaton has 9365 states and 28995 transitions. Word has length 59 [2019-12-07 18:57:20,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:20,317 INFO L462 AbstractCegarLoop]: Abstraction has 9365 states and 28995 transitions. [2019-12-07 18:57:20,318 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:57:20,318 INFO L276 IsEmpty]: Start isEmpty. Operand 9365 states and 28995 transitions. [2019-12-07 18:57:20,325 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 18:57:20,325 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:20,325 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:20,325 INFO L410 AbstractCegarLoop]: === Iteration 39 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:20,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:20,326 INFO L82 PathProgramCache]: Analyzing trace with hash 1556260520, now seen corresponding path program 13 times [2019-12-07 18:57:20,326 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:20,326 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079600694] [2019-12-07 18:57:20,326 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:20,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:20,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:20,584 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2079600694] [2019-12-07 18:57:20,585 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:20,585 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 18:57:20,585 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [232799361] [2019-12-07 18:57:20,585 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 18:57:20,585 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:20,585 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 18:57:20,585 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=199, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:57:20,585 INFO L87 Difference]: Start difference. First operand 9365 states and 28995 transitions. Second operand 16 states. [2019-12-07 18:57:22,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:22,284 INFO L93 Difference]: Finished difference Result 11360 states and 34217 transitions. [2019-12-07 18:57:22,284 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2019-12-07 18:57:22,284 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 59 [2019-12-07 18:57:22,284 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:22,295 INFO L225 Difference]: With dead ends: 11360 [2019-12-07 18:57:22,295 INFO L226 Difference]: Without dead ends: 10792 [2019-12-07 18:57:22,296 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 57 GetRequests, 0 SyntacticMatches, 3 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 815 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=497, Invalid=2583, Unknown=0, NotChecked=0, Total=3080 [2019-12-07 18:57:22,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10792 states. [2019-12-07 18:57:22,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10792 to 9161. [2019-12-07 18:57:22,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9161 states. [2019-12-07 18:57:22,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9161 states to 9161 states and 28454 transitions. [2019-12-07 18:57:22,422 INFO L78 Accepts]: Start accepts. Automaton has 9161 states and 28454 transitions. Word has length 59 [2019-12-07 18:57:22,422 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:22,423 INFO L462 AbstractCegarLoop]: Abstraction has 9161 states and 28454 transitions. [2019-12-07 18:57:22,423 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 18:57:22,423 INFO L276 IsEmpty]: Start isEmpty. Operand 9161 states and 28454 transitions. [2019-12-07 18:57:22,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 18:57:22,430 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:22,430 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:22,430 INFO L410 AbstractCegarLoop]: === Iteration 40 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:22,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:22,430 INFO L82 PathProgramCache]: Analyzing trace with hash -765256248, now seen corresponding path program 14 times [2019-12-07 18:57:22,430 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:22,430 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2064351062] [2019-12-07 18:57:22,431 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:22,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:57:22,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:57:22,496 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:57:22,497 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 18:57:22,499 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [860] [860] ULTIMATE.startENTRY-->L850: Formula: (let ((.cse0 (store |v_#valid_82| 0 0))) (and (= v_~main$tmp_guard0~0_31 0) (= 0 v_~y$r_buff1_thd4~0_204) (= 0 v_~y$read_delayed_var~0.offset_8) (= v_~main$tmp_guard1~0_50 0) (= v_~a~0_15 0) (= 0 v_~y$w_buff0~0_524) (= |v_#valid_80| (store .cse0 |v_ULTIMATE.start_main_~#t941~0.base_26| 1)) (= 0 v_~y$r_buff0_thd3~0_184) (= v_~y$read_delayed~0_7 0) (= 0 v_~y$r_buff0_thd4~0_132) (= (store |v_#length_30| |v_ULTIMATE.start_main_~#t941~0.base_26| 4) |v_#length_29|) (= v_~y$w_buff0_used~0_906 0) (= |v_#NULL.offset_3| 0) (= v_~weak$$choice2~0_152 0) (= v_~y$r_buff1_thd0~0_180 0) (= (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t941~0.base_26| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t941~0.base_26|) |v_ULTIMATE.start_main_~#t941~0.offset_17| 0)) |v_#memory_int_27|) (= 0 v_~__unbuffered_p0_EAX~0_69) (= 0 v_~y$r_buff0_thd2~0_313) (= v_~y~0_171 0) (= v_~x~0_48 0) (= v_~y$mem_tmp~0_33 0) (= 0 v_~__unbuffered_p1_EAX~0_59) (= 0 v_~__unbuffered_p3_EAX~0_47) (= 0 v_~__unbuffered_p3_EBX~0_47) (= 0 |v_ULTIMATE.start_main_~#t941~0.offset_17|) (< |v_#StackHeapBarrier_20| |v_ULTIMATE.start_main_~#t941~0.base_26|) (= 0 v_~weak$$choice0~0_21) (= (select .cse0 |v_ULTIMATE.start_main_~#t941~0.base_26|) 0) (= 0 v_~__unbuffered_p2_EAX~0_124) (= 0 v_~y$flush_delayed~0_62) (= 0 v_~y$r_buff1_thd1~0_92) (< 0 |v_#StackHeapBarrier_20|) (= v_~y$w_buff1~0_331 0) (= v_~z~0_40 0) (= 0 |v_#NULL.base_3|) (= v_~y$r_buff0_thd0~0_125 0) (= 0 v_~y$read_delayed_var~0.base_8) (= 0 v_~y$r_buff1_thd2~0_274) (= v_~__unbuffered_cnt~0_218 0) (= v_~y$r_buff0_thd1~0_33 0) (= v_~b~0_43 0) (= 0 v_~y$r_buff1_thd3~0_153) (= v_~y$w_buff1_used~0_620 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_20|, #valid=|v_#valid_82|, #memory_int=|v_#memory_int_28|, #length=|v_#length_30|} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_97|, #NULL.offset=|v_#NULL.offset_3|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_38|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_200|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ~a~0=v_~a~0_15, ~y$mem_tmp~0=v_~y$mem_tmp~0_33, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_69, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_153, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_59, ULTIMATE.start_main_~#t941~0.offset=|v_ULTIMATE.start_main_~#t941~0.offset_17|, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_33, ULTIMATE.start_main_~#t941~0.base=|v_ULTIMATE.start_main_~#t941~0.base_26|, ~y$flush_delayed~0=v_~y$flush_delayed~0_62, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_47, #length=|v_#length_29|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_124, ULTIMATE.start_main_~#t944~0.base=|v_ULTIMATE.start_main_~#t944~0.base_24|, ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_28|, ULTIMATE.start_main_~#t943~0.base=|v_ULTIMATE.start_main_~#t943~0.base_26|, ~weak$$choice0~0=v_~weak$$choice0~0_21, #StackHeapBarrier=|v_#StackHeapBarrier_20|, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_204, ~y$w_buff1~0=v_~y$w_buff1~0_331, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_8, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_313, ULTIMATE.start_main_#t~nondet38=|v_ULTIMATE.start_main_#t~nondet38_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_218, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_180, ~x~0=v_~x~0_48, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_8, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_906, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_38|, ULTIMATE.start_main_~#t942~0.offset=|v_ULTIMATE.start_main_~#t942~0.offset_19|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_50, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_40|, ULTIMATE.start_main_~#t942~0.base=|v_ULTIMATE.start_main_~#t942~0.base_25|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_62|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_92, ~y$w_buff0~0=v_~y$w_buff0~0_524, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_184, ~y~0=v_~y~0_171, ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_8|, ULTIMATE.start_main_~#t943~0.offset=|v_ULTIMATE.start_main_~#t943~0.offset_19|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_31, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_47, #NULL.base=|v_#NULL.base_3|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_274, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_132, ULTIMATE.start_main_~#t944~0.offset=|v_ULTIMATE.start_main_~#t944~0.offset_17|, ~b~0=v_~b~0_43, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_34|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_125, #valid=|v_#valid_80|, #memory_int=|v_#memory_int_27|, ULTIMATE.start_main_#t~nondet39=|v_ULTIMATE.start_main_#t~nondet39_8|, ~z~0=v_~z~0_40, ~weak$$choice2~0=v_~weak$$choice2~0_152, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_620} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~a~0, ~y$mem_tmp~0, ~__unbuffered_p0_EAX~0, ~y$r_buff1_thd3~0, ~__unbuffered_p1_EAX~0, ULTIMATE.start_main_~#t941~0.offset, ~y$r_buff0_thd1~0, ULTIMATE.start_main_~#t941~0.base, ~y$flush_delayed~0, ~__unbuffered_p3_EAX~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t944~0.base, ULTIMATE.start_main_#t~nondet41, ULTIMATE.start_main_~#t943~0.base, ~weak$$choice0~0, ~y$r_buff1_thd4~0, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet38, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_~#t942~0.offset, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_~#t942~0.base, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~nondet40, ULTIMATE.start_main_~#t943~0.offset, ~main$tmp_guard0~0, ~__unbuffered_p3_EBX~0, #NULL.base, ~y$r_buff1_thd2~0, ~y$r_buff0_thd4~0, ULTIMATE.start_main_~#t944~0.offset, ~b~0, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet39, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 18:57:22,499 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] L850-1-->L852: Formula: (and (= |v_ULTIMATE.start_main_~#t942~0.offset_11| 0) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t942~0.base_12|) (= |v_#memory_int_19| (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t942~0.base_12| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t942~0.base_12|) |v_ULTIMATE.start_main_~#t942~0.offset_11| 1))) (= (select |v_#valid_43| |v_ULTIMATE.start_main_~#t942~0.base_12|) 0) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t942~0.base_12| 4)) (= (store |v_#valid_43| |v_ULTIMATE.start_main_~#t942~0.base_12| 1) |v_#valid_42|) (not (= 0 |v_ULTIMATE.start_main_~#t942~0.base_12|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_43|, #memory_int=|v_#memory_int_20|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_42|, #memory_int=|v_#memory_int_19|, ULTIMATE.start_main_#t~nondet38=|v_ULTIMATE.start_main_#t~nondet38_5|, ULTIMATE.start_main_~#t942~0.offset=|v_ULTIMATE.start_main_~#t942~0.offset_11|, #length=|v_#length_21|, ULTIMATE.start_main_~#t942~0.base=|v_ULTIMATE.start_main_~#t942~0.base_12|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet38, ULTIMATE.start_main_~#t942~0.offset, #length, ULTIMATE.start_main_~#t942~0.base] because there is no mapped edge [2019-12-07 18:57:22,500 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [822] [822] L852-1-->L854: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t943~0.base_13|)) (= |v_ULTIMATE.start_main_~#t943~0.offset_11| 0) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t943~0.base_13| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t943~0.base_13|) |v_ULTIMATE.start_main_~#t943~0.offset_11| 2)) |v_#memory_int_17|) (= (store |v_#length_20| |v_ULTIMATE.start_main_~#t943~0.base_13| 4) |v_#length_19|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t943~0.base_13|) (= (select |v_#valid_41| |v_ULTIMATE.start_main_~#t943~0.base_13|) 0) (= |v_#valid_40| (store |v_#valid_41| |v_ULTIMATE.start_main_~#t943~0.base_13| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_18|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_~#t943~0.offset=|v_ULTIMATE.start_main_~#t943~0.offset_11|, ULTIMATE.start_main_~#t943~0.base=|v_ULTIMATE.start_main_~#t943~0.base_13|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_17|, #length=|v_#length_19|, ULTIMATE.start_main_#t~nondet39=|v_ULTIMATE.start_main_#t~nondet39_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t943~0.offset, ULTIMATE.start_main_~#t943~0.base, #valid, #memory_int, #length, ULTIMATE.start_main_#t~nondet39] because there is no mapped edge [2019-12-07 18:57:22,500 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [834] [834] L854-1-->L856: Formula: (and (= |v_ULTIMATE.start_main_~#t944~0.offset_10| 0) (= |v_#length_23| (store |v_#length_24| |v_ULTIMATE.start_main_~#t944~0.base_12| 4)) (< |v_#StackHeapBarrier_15| |v_ULTIMATE.start_main_~#t944~0.base_12|) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t944~0.base_12| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t944~0.base_12|) |v_ULTIMATE.start_main_~#t944~0.offset_10| 3)) |v_#memory_int_21|) (= (store |v_#valid_47| |v_ULTIMATE.start_main_~#t944~0.base_12| 1) |v_#valid_46|) (= (select |v_#valid_47| |v_ULTIMATE.start_main_~#t944~0.base_12|) 0) (not (= |v_ULTIMATE.start_main_~#t944~0.base_12| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_22|, #length=|v_#length_24|} OutVars{ULTIMATE.start_main_~#t944~0.offset=|v_ULTIMATE.start_main_~#t944~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_15|, ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_5|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_21|, #length=|v_#length_23|, ULTIMATE.start_main_~#t944~0.base=|v_ULTIMATE.start_main_~#t944~0.base_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t944~0.offset, ULTIMATE.start_main_#t~nondet40, #valid, #memory_int, #length, ULTIMATE.start_main_~#t944~0.base] because there is no mapped edge [2019-12-07 18:57:22,501 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L4-->L801: Formula: (and (= v_~z~0_12 v_~__unbuffered_p2_EAX~0_13) (= v_~y$r_buff0_thd0~0_41 v_~y$r_buff1_thd0~0_36) (= v_~y$r_buff0_thd3~0_35 v_~y$r_buff1_thd3~0_31) (= v_~y$r_buff0_thd4~0_32 v_~y$r_buff1_thd4~0_28) (= v_~y$r_buff1_thd1~0_9 v_~y$r_buff0_thd1~0_9) (not (= v_P2Thread1of1ForFork3___VERIFIER_assert_~expression_46 0)) (= v_~y$r_buff0_thd2~0_103 v_~y$r_buff1_thd2~0_52) (= v_~y$r_buff0_thd3~0_34 1)) InVars {~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_32, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_35, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_41, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_103, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_9, P2Thread1of1ForFork3___VERIFIER_assert_~expression=v_P2Thread1of1ForFork3___VERIFIER_assert_~expression_46, ~z~0=v_~z~0_12} OutVars{P2Thread1of1ForFork3___VERIFIER_assert_~expression=v_P2Thread1of1ForFork3___VERIFIER_assert_~expression_46, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_52, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_32, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_9, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_28, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_31, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_34, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_41, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_103, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_9, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_13, ~z~0=v_~z~0_12, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_36} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, ~y$r_buff1_thd1~0, ~y$r_buff1_thd4~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd3~0, ~__unbuffered_p2_EAX~0, ~y$r_buff1_thd0~0] because there is no mapped edge [2019-12-07 18:57:22,502 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [818] [818] P0ENTRY-->P0EXIT: Formula: (and (= v_P0Thread1of1ForFork1_~arg.offset_16 |v_P0Thread1of1ForFork1_#in~arg.offset_18|) (= 0 |v_P0Thread1of1ForFork1_#res.base_3|) (= v_~b~0_20 1) (= v_~x~0_26 v_~__unbuffered_p0_EAX~0_24) (= (+ v_~__unbuffered_cnt~0_86 1) v_~__unbuffered_cnt~0_85) (= |v_P0Thread1of1ForFork1_#in~arg.base_18| v_P0Thread1of1ForFork1_~arg.base_16) (= 0 |v_P0Thread1of1ForFork1_#res.offset_3|)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_18|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_86, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_18|, ~x~0=v_~x~0_26} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_24, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_3|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_18|, ~b~0=v_~b~0_20, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_3|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_16, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_85, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_18|, ~x~0=v_~x~0_26, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_16} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, P0Thread1of1ForFork1_#res.offset, ~b~0, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-12-07 18:57:22,502 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L827-2-->L827-5: Formula: (let ((.cse2 (= (mod ~y$r_buff1_thd4~0_In1566783785 256) 0)) (.cse0 (= |P3Thread1of1ForFork0_#t~ite32_Out1566783785| |P3Thread1of1ForFork0_#t~ite33_Out1566783785|)) (.cse1 (= (mod ~y$w_buff1_used~0_In1566783785 256) 0))) (or (and (= |P3Thread1of1ForFork0_#t~ite32_Out1566783785| ~y~0_In1566783785) .cse0 (or .cse1 .cse2)) (and (not .cse2) .cse0 (not .cse1) (= |P3Thread1of1ForFork0_#t~ite32_Out1566783785| ~y$w_buff1~0_In1566783785)))) InVars {~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1566783785, ~y$w_buff1~0=~y$w_buff1~0_In1566783785, ~y~0=~y~0_In1566783785, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1566783785} OutVars{~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1566783785, ~y$w_buff1~0=~y$w_buff1~0_In1566783785, ~y~0=~y~0_In1566783785, P3Thread1of1ForFork0_#t~ite33=|P3Thread1of1ForFork0_#t~ite33_Out1566783785|, P3Thread1of1ForFork0_#t~ite32=|P3Thread1of1ForFork0_#t~ite32_Out1566783785|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1566783785} AuxVars[] AssignedVars[P3Thread1of1ForFork0_#t~ite33, P3Thread1of1ForFork0_#t~ite32] because there is no mapped edge [2019-12-07 18:57:22,503 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [790] [790] L828-->L828-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd4~0_In-913321069 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-913321069 256)))) (or (and (= 0 |P3Thread1of1ForFork0_#t~ite34_Out-913321069|) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In-913321069 |P3Thread1of1ForFork0_#t~ite34_Out-913321069|)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-913321069, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-913321069} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-913321069, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-913321069, P3Thread1of1ForFork0_#t~ite34=|P3Thread1of1ForFork0_#t~ite34_Out-913321069|} AuxVars[] AssignedVars[P3Thread1of1ForFork0_#t~ite34] because there is no mapped edge [2019-12-07 18:57:22,504 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L802-->L802-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In1540550293 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In1540550293 256)))) (or (and (= ~y$w_buff0_used~0_In1540550293 |P2Thread1of1ForFork3_#t~ite28_Out1540550293|) (or .cse0 .cse1)) (and (not .cse1) (= 0 |P2Thread1of1ForFork3_#t~ite28_Out1540550293|) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1540550293, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1540550293} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1540550293, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1540550293, P2Thread1of1ForFork3_#t~ite28=|P2Thread1of1ForFork3_#t~ite28_Out1540550293|} AuxVars[] AssignedVars[P2Thread1of1ForFork3_#t~ite28] because there is no mapped edge [2019-12-07 18:57:22,504 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L829-->L829-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd4~0_In876211489 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In876211489 256))) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In876211489 256))) (.cse3 (= 0 (mod ~y$r_buff1_thd4~0_In876211489 256)))) (or (and (= |P3Thread1of1ForFork0_#t~ite35_Out876211489| ~y$w_buff1_used~0_In876211489) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P3Thread1of1ForFork0_#t~ite35_Out876211489| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In876211489, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In876211489, ~y$w_buff0_used~0=~y$w_buff0_used~0_In876211489, ~y$w_buff1_used~0=~y$w_buff1_used~0_In876211489} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In876211489, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In876211489, ~y$w_buff0_used~0=~y$w_buff0_used~0_In876211489, P3Thread1of1ForFork0_#t~ite35=|P3Thread1of1ForFork0_#t~ite35_Out876211489|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In876211489} AuxVars[] AssignedVars[P3Thread1of1ForFork0_#t~ite35] because there is no mapped edge [2019-12-07 18:57:22,505 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L803-->L803-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In-1572570503 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd3~0_In-1572570503 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In-1572570503 256))) (.cse3 (= 0 (mod ~y$r_buff0_thd3~0_In-1572570503 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork3_#t~ite29_Out-1572570503| 0)) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork3_#t~ite29_Out-1572570503| ~y$w_buff1_used~0_In-1572570503) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1572570503, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1572570503, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1572570503, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1572570503} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1572570503, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1572570503, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1572570503, P2Thread1of1ForFork3_#t~ite29=|P2Thread1of1ForFork3_#t~ite29_Out-1572570503|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1572570503} AuxVars[] AssignedVars[P2Thread1of1ForFork3_#t~ite29] because there is no mapped edge [2019-12-07 18:57:22,506 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [785] [785] L804-->L805: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd3~0_In1102816513 256) 0)) (.cse1 (= ~y$r_buff0_thd3~0_Out1102816513 ~y$r_buff0_thd3~0_In1102816513)) (.cse2 (= (mod ~y$w_buff0_used~0_In1102816513 256) 0))) (or (and .cse0 .cse1) (and (not .cse0) (= ~y$r_buff0_thd3~0_Out1102816513 0) (not .cse2)) (and .cse1 .cse2))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1102816513, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1102816513} OutVars{P2Thread1of1ForFork3_#t~ite30=|P2Thread1of1ForFork3_#t~ite30_Out1102816513|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1102816513, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out1102816513} AuxVars[] AssignedVars[P2Thread1of1ForFork3_#t~ite30, ~y$r_buff0_thd3~0] because there is no mapped edge [2019-12-07 18:57:22,506 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [794] [794] L805-->L805-2: Formula: (let ((.cse0 (= (mod ~y$r_buff1_thd3~0_In-292692101 256) 0)) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In-292692101 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In-292692101 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In-292692101 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork3_#t~ite31_Out-292692101|)) (and (= ~y$r_buff1_thd3~0_In-292692101 |P2Thread1of1ForFork3_#t~ite31_Out-292692101|) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-292692101, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-292692101, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-292692101, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-292692101} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-292692101, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-292692101, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-292692101, P2Thread1of1ForFork3_#t~ite31=|P2Thread1of1ForFork3_#t~ite31_Out-292692101|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-292692101} AuxVars[] AssignedVars[P2Thread1of1ForFork3_#t~ite31] because there is no mapped edge [2019-12-07 18:57:22,506 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L805-2-->P2EXIT: Formula: (and (= v_~__unbuffered_cnt~0_71 (+ v_~__unbuffered_cnt~0_72 1)) (= |v_P2Thread1of1ForFork3_#t~ite31_34| v_~y$r_buff1_thd3~0_46) (= 0 |v_P2Thread1of1ForFork3_#res.base_3|) (= |v_P2Thread1of1ForFork3_#res.offset_3| 0)) InVars {P2Thread1of1ForFork3_#t~ite31=|v_P2Thread1of1ForFork3_#t~ite31_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72} OutVars{~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_46, P2Thread1of1ForFork3_#t~ite31=|v_P2Thread1of1ForFork3_#t~ite31_33|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_71, P2Thread1of1ForFork3_#res.base=|v_P2Thread1of1ForFork3_#res.base_3|, P2Thread1of1ForFork3_#res.offset=|v_P2Thread1of1ForFork3_#res.offset_3|} AuxVars[] AssignedVars[~y$r_buff1_thd3~0, P2Thread1of1ForFork3_#t~ite31, ~__unbuffered_cnt~0, P2Thread1of1ForFork3_#res.base, P2Thread1of1ForFork3_#res.offset] because there is no mapped edge [2019-12-07 18:57:22,506 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [837] [837] L765-->L765-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In2112425768 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite9_Out2112425768| ~y$w_buff0~0_In2112425768) (not .cse0) (= |P1Thread1of1ForFork2_#t~ite8_In2112425768| |P1Thread1of1ForFork2_#t~ite8_Out2112425768|)) (and (= |P1Thread1of1ForFork2_#t~ite8_Out2112425768| |P1Thread1of1ForFork2_#t~ite9_Out2112425768|) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In2112425768 256)))) (or (and .cse1 (= (mod ~y$r_buff1_thd2~0_In2112425768 256) 0)) (and .cse1 (= 0 (mod ~y$w_buff1_used~0_In2112425768 256))) (= (mod ~y$w_buff0_used~0_In2112425768 256) 0))) (= |P1Thread1of1ForFork2_#t~ite8_Out2112425768| ~y$w_buff0~0_In2112425768) .cse0))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2112425768, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2112425768, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_In2112425768|, ~y$w_buff0~0=~y$w_buff0~0_In2112425768, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2112425768, ~weak$$choice2~0=~weak$$choice2~0_In2112425768, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2112425768} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2112425768, P1Thread1of1ForFork2_#t~ite9=|P1Thread1of1ForFork2_#t~ite9_Out2112425768|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2112425768, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out2112425768|, ~y$w_buff0~0=~y$w_buff0~0_In2112425768, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2112425768, ~weak$$choice2~0=~weak$$choice2~0_In2112425768, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2112425768} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 18:57:22,507 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [836] [836] L766-->L766-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In-925856461 256) 0))) (or (and (= |P1Thread1of1ForFork2_#t~ite12_Out-925856461| |P1Thread1of1ForFork2_#t~ite11_Out-925856461|) (= ~y$w_buff1~0_In-925856461 |P1Thread1of1ForFork2_#t~ite11_Out-925856461|) (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In-925856461 256) 0))) (or (and (= (mod ~y$r_buff1_thd2~0_In-925856461 256) 0) .cse0) (and (= 0 (mod ~y$w_buff1_used~0_In-925856461 256)) .cse0) (= 0 (mod ~y$w_buff0_used~0_In-925856461 256)))) .cse1) (and (not .cse1) (= |P1Thread1of1ForFork2_#t~ite11_In-925856461| |P1Thread1of1ForFork2_#t~ite11_Out-925856461|) (= |P1Thread1of1ForFork2_#t~ite12_Out-925856461| ~y$w_buff1~0_In-925856461)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-925856461, ~y$w_buff1~0=~y$w_buff1~0_In-925856461, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-925856461, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-925856461, P1Thread1of1ForFork2_#t~ite11=|P1Thread1of1ForFork2_#t~ite11_In-925856461|, ~weak$$choice2~0=~weak$$choice2~0_In-925856461, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-925856461} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-925856461, ~y$w_buff1~0=~y$w_buff1~0_In-925856461, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-925856461, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-925856461, P1Thread1of1ForFork2_#t~ite12=|P1Thread1of1ForFork2_#t~ite12_Out-925856461|, P1Thread1of1ForFork2_#t~ite11=|P1Thread1of1ForFork2_#t~ite11_Out-925856461|, ~weak$$choice2~0=~weak$$choice2~0_In-925856461, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-925856461} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite12, P1Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-12-07 18:57:22,509 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L769-->L770: Formula: (and (= v_~y$r_buff0_thd2~0_106 v_~y$r_buff0_thd2~0_105) (not (= (mod v_~weak$$choice2~0_28 256) 0))) InVars {~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_106, ~weak$$choice2~0=v_~weak$$choice2~0_28} OutVars{P1Thread1of1ForFork2_#t~ite19=|v_P1Thread1of1ForFork2_#t~ite19_6|, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_105, P1Thread1of1ForFork2_#t~ite20=|v_P1Thread1of1ForFork2_#t~ite20_9|, P1Thread1of1ForFork2_#t~ite21=|v_P1Thread1of1ForFork2_#t~ite21_7|, ~weak$$choice2~0=v_~weak$$choice2~0_28} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite19, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite20, P1Thread1of1ForFork2_#t~ite21] because there is no mapped edge [2019-12-07 18:57:22,509 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] L770-->L770-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In454174320 256)))) (or (and (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In454174320 256) 0))) (or (and (= 0 (mod ~y$r_buff1_thd2~0_In454174320 256)) .cse0) (= (mod ~y$w_buff0_used~0_In454174320 256) 0) (and .cse0 (= (mod ~y$w_buff1_used~0_In454174320 256) 0)))) (= |P1Thread1of1ForFork2_#t~ite23_Out454174320| ~y$r_buff1_thd2~0_In454174320) .cse1 (= |P1Thread1of1ForFork2_#t~ite24_Out454174320| |P1Thread1of1ForFork2_#t~ite23_Out454174320|)) (and (= |P1Thread1of1ForFork2_#t~ite24_Out454174320| ~y$r_buff1_thd2~0_In454174320) (= |P1Thread1of1ForFork2_#t~ite23_In454174320| |P1Thread1of1ForFork2_#t~ite23_Out454174320|) (not .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In454174320, ~y$w_buff0_used~0=~y$w_buff0_used~0_In454174320, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In454174320, P1Thread1of1ForFork2_#t~ite23=|P1Thread1of1ForFork2_#t~ite23_In454174320|, ~weak$$choice2~0=~weak$$choice2~0_In454174320, ~y$w_buff1_used~0=~y$w_buff1_used~0_In454174320} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In454174320, ~y$w_buff0_used~0=~y$w_buff0_used~0_In454174320, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In454174320, P1Thread1of1ForFork2_#t~ite23=|P1Thread1of1ForFork2_#t~ite23_Out454174320|, ~weak$$choice2~0=~weak$$choice2~0_In454174320, P1Thread1of1ForFork2_#t~ite24=|P1Thread1of1ForFork2_#t~ite24_Out454174320|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In454174320} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite23, P1Thread1of1ForFork2_#t~ite24] because there is no mapped edge [2019-12-07 18:57:22,509 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [735] [735] L772-->L780: Formula: (and (= (+ v_~__unbuffered_cnt~0_17 1) v_~__unbuffered_cnt~0_16) (not (= 0 (mod v_~y$flush_delayed~0_10 256))) (= v_~y~0_26 v_~y$mem_tmp~0_7) (= 0 v_~y$flush_delayed~0_9)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_7, ~y$flush_delayed~0=v_~y$flush_delayed~0_10, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_17} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_7, ~y$flush_delayed~0=v_~y$flush_delayed~0_9, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_16, ~y~0=v_~y~0_26, P1Thread1of1ForFork2_#t~ite25=|v_P1Thread1of1ForFork2_#t~ite25_5|} AuxVars[] AssignedVars[~y$flush_delayed~0, ~__unbuffered_cnt~0, ~y~0, P1Thread1of1ForFork2_#t~ite25] because there is no mapped edge [2019-12-07 18:57:22,509 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [783] [783] L830-->L830-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd4~0_In1515198035 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In1515198035 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P3Thread1of1ForFork0_#t~ite36_Out1515198035|)) (and (or .cse1 .cse0) (= |P3Thread1of1ForFork0_#t~ite36_Out1515198035| ~y$r_buff0_thd4~0_In1515198035)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1515198035, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1515198035} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1515198035, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1515198035, P3Thread1of1ForFork0_#t~ite36=|P3Thread1of1ForFork0_#t~ite36_Out1515198035|} AuxVars[] AssignedVars[P3Thread1of1ForFork0_#t~ite36] because there is no mapped edge [2019-12-07 18:57:22,510 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [792] [792] L831-->L831-2: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In926361585 256) 0)) (.cse1 (= 0 (mod ~y$r_buff1_thd4~0_In926361585 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In926361585 256))) (.cse3 (= 0 (mod ~y$r_buff0_thd4~0_In926361585 256)))) (or (and (= ~y$r_buff1_thd4~0_In926361585 |P3Thread1of1ForFork0_#t~ite37_Out926361585|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P3Thread1of1ForFork0_#t~ite37_Out926361585|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In926361585, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In926361585, ~y$w_buff0_used~0=~y$w_buff0_used~0_In926361585, ~y$w_buff1_used~0=~y$w_buff1_used~0_In926361585} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In926361585, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In926361585, ~y$w_buff0_used~0=~y$w_buff0_used~0_In926361585, P3Thread1of1ForFork0_#t~ite37=|P3Thread1of1ForFork0_#t~ite37_Out926361585|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In926361585} AuxVars[] AssignedVars[P3Thread1of1ForFork0_#t~ite37] because there is no mapped edge [2019-12-07 18:57:22,510 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [833] [833] L831-2-->P3EXIT: Formula: (and (= |v_P3Thread1of1ForFork0_#res.base_3| 0) (= v_~__unbuffered_cnt~0_146 (+ v_~__unbuffered_cnt~0_147 1)) (= |v_P3Thread1of1ForFork0_#t~ite37_64| v_~y$r_buff1_thd4~0_141) (= 0 |v_P3Thread1of1ForFork0_#res.offset_3|)) InVars {P3Thread1of1ForFork0_#t~ite37=|v_P3Thread1of1ForFork0_#t~ite37_64|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_147} OutVars{~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_141, P3Thread1of1ForFork0_#res.offset=|v_P3Thread1of1ForFork0_#res.offset_3|, P3Thread1of1ForFork0_#t~ite37=|v_P3Thread1of1ForFork0_#t~ite37_63|, P3Thread1of1ForFork0_#res.base=|v_P3Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_146} AuxVars[] AssignedVars[~y$r_buff1_thd4~0, P3Thread1of1ForFork0_#res.offset, P3Thread1of1ForFork0_#t~ite37, P3Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 18:57:22,510 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L856-1-->L862: Formula: (and (= v_~main$tmp_guard0~0_12 (ite (= 0 (ite (= 4 v_~__unbuffered_cnt~0_38) 1 0)) 0 1)) (not (= 0 (mod v_~main$tmp_guard0~0_12 256)))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38} OutVars{ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_12|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_12} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet41, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:57:22,510 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L862-2-->L862-4: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In951771507 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In951771507 256)))) (or (and (or .cse0 .cse1) (= ~y~0_In951771507 |ULTIMATE.start_main_#t~ite42_Out951771507|)) (and (not .cse1) (not .cse0) (= ~y$w_buff1~0_In951771507 |ULTIMATE.start_main_#t~ite42_Out951771507|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In951771507, ~y~0=~y~0_In951771507, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In951771507, ~y$w_buff1_used~0=~y$w_buff1_used~0_In951771507} OutVars{~y$w_buff1~0=~y$w_buff1~0_In951771507, ~y~0=~y~0_In951771507, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_Out951771507|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In951771507, ~y$w_buff1_used~0=~y$w_buff1_used~0_In951771507} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 18:57:22,510 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L862-4-->L863: Formula: (= v_~y~0_20 |v_ULTIMATE.start_main_#t~ite42_7|) InVars {ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_7|} OutVars{ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_6|, ~y~0=v_~y~0_20, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43, ~y~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 18:57:22,511 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L863-->L863-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In1862333176 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In1862333176 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite44_Out1862333176| ~y$w_buff0_used~0_In1862333176)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite44_Out1862333176| 0) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1862333176, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1862333176} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1862333176, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1862333176, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_Out1862333176|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-12-07 18:57:22,511 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L864-->L864-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1660019355 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In1660019355 256))) (.cse2 (= (mod ~y$r_buff1_thd0~0_In1660019355 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In1660019355 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite45_Out1660019355|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~y$w_buff1_used~0_In1660019355 |ULTIMATE.start_main_#t~ite45_Out1660019355|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1660019355, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1660019355, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1660019355, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1660019355} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1660019355, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1660019355, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1660019355, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out1660019355|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1660019355} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite45] because there is no mapped edge [2019-12-07 18:57:22,511 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [791] [791] L865-->L865-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1651619703 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd0~0_In1651619703 256) 0))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite46_Out1651619703|) (not .cse1)) (and (= ~y$r_buff0_thd0~0_In1651619703 |ULTIMATE.start_main_#t~ite46_Out1651619703|) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1651619703, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1651619703} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1651619703, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1651619703, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out1651619703|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46] because there is no mapped edge [2019-12-07 18:57:22,512 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L866-->L866-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In1903582197 256))) (.cse1 (= (mod ~y$r_buff0_thd0~0_In1903582197 256) 0)) (.cse2 (= (mod ~y$w_buff1_used~0_In1903582197 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd0~0_In1903582197 256)))) (or (and (= |ULTIMATE.start_main_#t~ite47_Out1903582197| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~y$r_buff1_thd0~0_In1903582197 |ULTIMATE.start_main_#t~ite47_Out1903582197|) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1903582197, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1903582197, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1903582197, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1903582197} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1903582197, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1903582197, ULTIMATE.start_main_#t~ite47=|ULTIMATE.start_main_#t~ite47_Out1903582197|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1903582197, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1903582197} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] because there is no mapped edge [2019-12-07 18:57:22,512 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L866-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_~y$r_buff1_thd0~0_137 |v_ULTIMATE.start_main_#t~ite47_48|) (= v_~main$tmp_guard1~0_20 (ite (= 0 (ite (not (and (= 0 v_~__unbuffered_p3_EBX~0_23) (= 0 v_~__unbuffered_p1_EAX~0_25) (= 0 v_~__unbuffered_p2_EAX~0_92) (= 0 v_~__unbuffered_p0_EAX~0_41) (= 1 v_~__unbuffered_p3_EAX~0_23))) 1 0)) 0 1)) (= v_ULTIMATE.start___VERIFIER_assert_~expression_17 0) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_12| (mod v_~main$tmp_guard1~0_20 256)) (= v_ULTIMATE.start___VERIFIER_assert_~expression_17 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_12|)) InVars {~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_41, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_25, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_23, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_48|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_92, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_23} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_41, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_17, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_25, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_23, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_47|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_20, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_92, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_23, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_137, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_12|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ULTIMATE.start_main_#t~ite47, ~main$tmp_guard1~0, ~y$r_buff1_thd0~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:57:22,565 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 06:57:22 BasicIcfg [2019-12-07 18:57:22,565 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 18:57:22,565 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:57:22,565 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:57:22,565 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:57:22,566 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:53:13" (3/4) ... [2019-12-07 18:57:22,567 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 18:57:22,568 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [860] [860] ULTIMATE.startENTRY-->L850: Formula: (let ((.cse0 (store |v_#valid_82| 0 0))) (and (= v_~main$tmp_guard0~0_31 0) (= 0 v_~y$r_buff1_thd4~0_204) (= 0 v_~y$read_delayed_var~0.offset_8) (= v_~main$tmp_guard1~0_50 0) (= v_~a~0_15 0) (= 0 v_~y$w_buff0~0_524) (= |v_#valid_80| (store .cse0 |v_ULTIMATE.start_main_~#t941~0.base_26| 1)) (= 0 v_~y$r_buff0_thd3~0_184) (= v_~y$read_delayed~0_7 0) (= 0 v_~y$r_buff0_thd4~0_132) (= (store |v_#length_30| |v_ULTIMATE.start_main_~#t941~0.base_26| 4) |v_#length_29|) (= v_~y$w_buff0_used~0_906 0) (= |v_#NULL.offset_3| 0) (= v_~weak$$choice2~0_152 0) (= v_~y$r_buff1_thd0~0_180 0) (= (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t941~0.base_26| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t941~0.base_26|) |v_ULTIMATE.start_main_~#t941~0.offset_17| 0)) |v_#memory_int_27|) (= 0 v_~__unbuffered_p0_EAX~0_69) (= 0 v_~y$r_buff0_thd2~0_313) (= v_~y~0_171 0) (= v_~x~0_48 0) (= v_~y$mem_tmp~0_33 0) (= 0 v_~__unbuffered_p1_EAX~0_59) (= 0 v_~__unbuffered_p3_EAX~0_47) (= 0 v_~__unbuffered_p3_EBX~0_47) (= 0 |v_ULTIMATE.start_main_~#t941~0.offset_17|) (< |v_#StackHeapBarrier_20| |v_ULTIMATE.start_main_~#t941~0.base_26|) (= 0 v_~weak$$choice0~0_21) (= (select .cse0 |v_ULTIMATE.start_main_~#t941~0.base_26|) 0) (= 0 v_~__unbuffered_p2_EAX~0_124) (= 0 v_~y$flush_delayed~0_62) (= 0 v_~y$r_buff1_thd1~0_92) (< 0 |v_#StackHeapBarrier_20|) (= v_~y$w_buff1~0_331 0) (= v_~z~0_40 0) (= 0 |v_#NULL.base_3|) (= v_~y$r_buff0_thd0~0_125 0) (= 0 v_~y$read_delayed_var~0.base_8) (= 0 v_~y$r_buff1_thd2~0_274) (= v_~__unbuffered_cnt~0_218 0) (= v_~y$r_buff0_thd1~0_33 0) (= v_~b~0_43 0) (= 0 v_~y$r_buff1_thd3~0_153) (= v_~y$w_buff1_used~0_620 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_20|, #valid=|v_#valid_82|, #memory_int=|v_#memory_int_28|, #length=|v_#length_30|} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_97|, #NULL.offset=|v_#NULL.offset_3|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_38|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_200|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ~a~0=v_~a~0_15, ~y$mem_tmp~0=v_~y$mem_tmp~0_33, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_69, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_153, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_59, ULTIMATE.start_main_~#t941~0.offset=|v_ULTIMATE.start_main_~#t941~0.offset_17|, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_33, ULTIMATE.start_main_~#t941~0.base=|v_ULTIMATE.start_main_~#t941~0.base_26|, ~y$flush_delayed~0=v_~y$flush_delayed~0_62, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_47, #length=|v_#length_29|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_124, ULTIMATE.start_main_~#t944~0.base=|v_ULTIMATE.start_main_~#t944~0.base_24|, ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_28|, ULTIMATE.start_main_~#t943~0.base=|v_ULTIMATE.start_main_~#t943~0.base_26|, ~weak$$choice0~0=v_~weak$$choice0~0_21, #StackHeapBarrier=|v_#StackHeapBarrier_20|, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_204, ~y$w_buff1~0=v_~y$w_buff1~0_331, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_8, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_313, ULTIMATE.start_main_#t~nondet38=|v_ULTIMATE.start_main_#t~nondet38_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_218, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_180, ~x~0=v_~x~0_48, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_8, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_906, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_38|, ULTIMATE.start_main_~#t942~0.offset=|v_ULTIMATE.start_main_~#t942~0.offset_19|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_50, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_40|, ULTIMATE.start_main_~#t942~0.base=|v_ULTIMATE.start_main_~#t942~0.base_25|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_62|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_92, ~y$w_buff0~0=v_~y$w_buff0~0_524, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_184, ~y~0=v_~y~0_171, ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_8|, ULTIMATE.start_main_~#t943~0.offset=|v_ULTIMATE.start_main_~#t943~0.offset_19|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_31, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_47, #NULL.base=|v_#NULL.base_3|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_274, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_132, ULTIMATE.start_main_~#t944~0.offset=|v_ULTIMATE.start_main_~#t944~0.offset_17|, ~b~0=v_~b~0_43, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_34|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_125, #valid=|v_#valid_80|, #memory_int=|v_#memory_int_27|, ULTIMATE.start_main_#t~nondet39=|v_ULTIMATE.start_main_#t~nondet39_8|, ~z~0=v_~z~0_40, ~weak$$choice2~0=v_~weak$$choice2~0_152, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_620} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~a~0, ~y$mem_tmp~0, ~__unbuffered_p0_EAX~0, ~y$r_buff1_thd3~0, ~__unbuffered_p1_EAX~0, ULTIMATE.start_main_~#t941~0.offset, ~y$r_buff0_thd1~0, ULTIMATE.start_main_~#t941~0.base, ~y$flush_delayed~0, ~__unbuffered_p3_EAX~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t944~0.base, ULTIMATE.start_main_#t~nondet41, ULTIMATE.start_main_~#t943~0.base, ~weak$$choice0~0, ~y$r_buff1_thd4~0, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet38, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_~#t942~0.offset, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_~#t942~0.base, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~nondet40, ULTIMATE.start_main_~#t943~0.offset, ~main$tmp_guard0~0, ~__unbuffered_p3_EBX~0, #NULL.base, ~y$r_buff1_thd2~0, ~y$r_buff0_thd4~0, ULTIMATE.start_main_~#t944~0.offset, ~b~0, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet39, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 18:57:22,568 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] L850-1-->L852: Formula: (and (= |v_ULTIMATE.start_main_~#t942~0.offset_11| 0) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t942~0.base_12|) (= |v_#memory_int_19| (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t942~0.base_12| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t942~0.base_12|) |v_ULTIMATE.start_main_~#t942~0.offset_11| 1))) (= (select |v_#valid_43| |v_ULTIMATE.start_main_~#t942~0.base_12|) 0) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t942~0.base_12| 4)) (= (store |v_#valid_43| |v_ULTIMATE.start_main_~#t942~0.base_12| 1) |v_#valid_42|) (not (= 0 |v_ULTIMATE.start_main_~#t942~0.base_12|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_43|, #memory_int=|v_#memory_int_20|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_42|, #memory_int=|v_#memory_int_19|, ULTIMATE.start_main_#t~nondet38=|v_ULTIMATE.start_main_#t~nondet38_5|, ULTIMATE.start_main_~#t942~0.offset=|v_ULTIMATE.start_main_~#t942~0.offset_11|, #length=|v_#length_21|, ULTIMATE.start_main_~#t942~0.base=|v_ULTIMATE.start_main_~#t942~0.base_12|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet38, ULTIMATE.start_main_~#t942~0.offset, #length, ULTIMATE.start_main_~#t942~0.base] because there is no mapped edge [2019-12-07 18:57:22,568 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [822] [822] L852-1-->L854: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t943~0.base_13|)) (= |v_ULTIMATE.start_main_~#t943~0.offset_11| 0) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t943~0.base_13| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t943~0.base_13|) |v_ULTIMATE.start_main_~#t943~0.offset_11| 2)) |v_#memory_int_17|) (= (store |v_#length_20| |v_ULTIMATE.start_main_~#t943~0.base_13| 4) |v_#length_19|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t943~0.base_13|) (= (select |v_#valid_41| |v_ULTIMATE.start_main_~#t943~0.base_13|) 0) (= |v_#valid_40| (store |v_#valid_41| |v_ULTIMATE.start_main_~#t943~0.base_13| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_18|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_~#t943~0.offset=|v_ULTIMATE.start_main_~#t943~0.offset_11|, ULTIMATE.start_main_~#t943~0.base=|v_ULTIMATE.start_main_~#t943~0.base_13|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_17|, #length=|v_#length_19|, ULTIMATE.start_main_#t~nondet39=|v_ULTIMATE.start_main_#t~nondet39_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t943~0.offset, ULTIMATE.start_main_~#t943~0.base, #valid, #memory_int, #length, ULTIMATE.start_main_#t~nondet39] because there is no mapped edge [2019-12-07 18:57:22,569 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [834] [834] L854-1-->L856: Formula: (and (= |v_ULTIMATE.start_main_~#t944~0.offset_10| 0) (= |v_#length_23| (store |v_#length_24| |v_ULTIMATE.start_main_~#t944~0.base_12| 4)) (< |v_#StackHeapBarrier_15| |v_ULTIMATE.start_main_~#t944~0.base_12|) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t944~0.base_12| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t944~0.base_12|) |v_ULTIMATE.start_main_~#t944~0.offset_10| 3)) |v_#memory_int_21|) (= (store |v_#valid_47| |v_ULTIMATE.start_main_~#t944~0.base_12| 1) |v_#valid_46|) (= (select |v_#valid_47| |v_ULTIMATE.start_main_~#t944~0.base_12|) 0) (not (= |v_ULTIMATE.start_main_~#t944~0.base_12| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_22|, #length=|v_#length_24|} OutVars{ULTIMATE.start_main_~#t944~0.offset=|v_ULTIMATE.start_main_~#t944~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_15|, ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_5|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_21|, #length=|v_#length_23|, ULTIMATE.start_main_~#t944~0.base=|v_ULTIMATE.start_main_~#t944~0.base_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t944~0.offset, ULTIMATE.start_main_#t~nondet40, #valid, #memory_int, #length, ULTIMATE.start_main_~#t944~0.base] because there is no mapped edge [2019-12-07 18:57:22,569 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L4-->L801: Formula: (and (= v_~z~0_12 v_~__unbuffered_p2_EAX~0_13) (= v_~y$r_buff0_thd0~0_41 v_~y$r_buff1_thd0~0_36) (= v_~y$r_buff0_thd3~0_35 v_~y$r_buff1_thd3~0_31) (= v_~y$r_buff0_thd4~0_32 v_~y$r_buff1_thd4~0_28) (= v_~y$r_buff1_thd1~0_9 v_~y$r_buff0_thd1~0_9) (not (= v_P2Thread1of1ForFork3___VERIFIER_assert_~expression_46 0)) (= v_~y$r_buff0_thd2~0_103 v_~y$r_buff1_thd2~0_52) (= v_~y$r_buff0_thd3~0_34 1)) InVars {~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_32, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_35, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_41, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_103, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_9, P2Thread1of1ForFork3___VERIFIER_assert_~expression=v_P2Thread1of1ForFork3___VERIFIER_assert_~expression_46, ~z~0=v_~z~0_12} OutVars{P2Thread1of1ForFork3___VERIFIER_assert_~expression=v_P2Thread1of1ForFork3___VERIFIER_assert_~expression_46, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_52, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_32, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_9, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_28, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_31, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_34, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_41, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_103, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_9, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_13, ~z~0=v_~z~0_12, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_36} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, ~y$r_buff1_thd1~0, ~y$r_buff1_thd4~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd3~0, ~__unbuffered_p2_EAX~0, ~y$r_buff1_thd0~0] because there is no mapped edge [2019-12-07 18:57:22,570 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [818] [818] P0ENTRY-->P0EXIT: Formula: (and (= v_P0Thread1of1ForFork1_~arg.offset_16 |v_P0Thread1of1ForFork1_#in~arg.offset_18|) (= 0 |v_P0Thread1of1ForFork1_#res.base_3|) (= v_~b~0_20 1) (= v_~x~0_26 v_~__unbuffered_p0_EAX~0_24) (= (+ v_~__unbuffered_cnt~0_86 1) v_~__unbuffered_cnt~0_85) (= |v_P0Thread1of1ForFork1_#in~arg.base_18| v_P0Thread1of1ForFork1_~arg.base_16) (= 0 |v_P0Thread1of1ForFork1_#res.offset_3|)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_18|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_86, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_18|, ~x~0=v_~x~0_26} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_24, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_3|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_18|, ~b~0=v_~b~0_20, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_3|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_16, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_85, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_18|, ~x~0=v_~x~0_26, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_16} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, P0Thread1of1ForFork1_#res.offset, ~b~0, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-12-07 18:57:22,571 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L827-2-->L827-5: Formula: (let ((.cse2 (= (mod ~y$r_buff1_thd4~0_In1566783785 256) 0)) (.cse0 (= |P3Thread1of1ForFork0_#t~ite32_Out1566783785| |P3Thread1of1ForFork0_#t~ite33_Out1566783785|)) (.cse1 (= (mod ~y$w_buff1_used~0_In1566783785 256) 0))) (or (and (= |P3Thread1of1ForFork0_#t~ite32_Out1566783785| ~y~0_In1566783785) .cse0 (or .cse1 .cse2)) (and (not .cse2) .cse0 (not .cse1) (= |P3Thread1of1ForFork0_#t~ite32_Out1566783785| ~y$w_buff1~0_In1566783785)))) InVars {~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1566783785, ~y$w_buff1~0=~y$w_buff1~0_In1566783785, ~y~0=~y~0_In1566783785, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1566783785} OutVars{~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1566783785, ~y$w_buff1~0=~y$w_buff1~0_In1566783785, ~y~0=~y~0_In1566783785, P3Thread1of1ForFork0_#t~ite33=|P3Thread1of1ForFork0_#t~ite33_Out1566783785|, P3Thread1of1ForFork0_#t~ite32=|P3Thread1of1ForFork0_#t~ite32_Out1566783785|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1566783785} AuxVars[] AssignedVars[P3Thread1of1ForFork0_#t~ite33, P3Thread1of1ForFork0_#t~ite32] because there is no mapped edge [2019-12-07 18:57:22,571 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [790] [790] L828-->L828-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd4~0_In-913321069 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-913321069 256)))) (or (and (= 0 |P3Thread1of1ForFork0_#t~ite34_Out-913321069|) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In-913321069 |P3Thread1of1ForFork0_#t~ite34_Out-913321069|)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-913321069, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-913321069} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-913321069, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-913321069, P3Thread1of1ForFork0_#t~ite34=|P3Thread1of1ForFork0_#t~ite34_Out-913321069|} AuxVars[] AssignedVars[P3Thread1of1ForFork0_#t~ite34] because there is no mapped edge [2019-12-07 18:57:22,572 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L802-->L802-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In1540550293 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In1540550293 256)))) (or (and (= ~y$w_buff0_used~0_In1540550293 |P2Thread1of1ForFork3_#t~ite28_Out1540550293|) (or .cse0 .cse1)) (and (not .cse1) (= 0 |P2Thread1of1ForFork3_#t~ite28_Out1540550293|) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1540550293, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1540550293} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1540550293, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1540550293, P2Thread1of1ForFork3_#t~ite28=|P2Thread1of1ForFork3_#t~ite28_Out1540550293|} AuxVars[] AssignedVars[P2Thread1of1ForFork3_#t~ite28] because there is no mapped edge [2019-12-07 18:57:22,572 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L829-->L829-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd4~0_In876211489 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In876211489 256))) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In876211489 256))) (.cse3 (= 0 (mod ~y$r_buff1_thd4~0_In876211489 256)))) (or (and (= |P3Thread1of1ForFork0_#t~ite35_Out876211489| ~y$w_buff1_used~0_In876211489) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P3Thread1of1ForFork0_#t~ite35_Out876211489| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In876211489, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In876211489, ~y$w_buff0_used~0=~y$w_buff0_used~0_In876211489, ~y$w_buff1_used~0=~y$w_buff1_used~0_In876211489} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In876211489, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In876211489, ~y$w_buff0_used~0=~y$w_buff0_used~0_In876211489, P3Thread1of1ForFork0_#t~ite35=|P3Thread1of1ForFork0_#t~ite35_Out876211489|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In876211489} AuxVars[] AssignedVars[P3Thread1of1ForFork0_#t~ite35] because there is no mapped edge [2019-12-07 18:57:22,573 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L803-->L803-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In-1572570503 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd3~0_In-1572570503 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In-1572570503 256))) (.cse3 (= 0 (mod ~y$r_buff0_thd3~0_In-1572570503 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork3_#t~ite29_Out-1572570503| 0)) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork3_#t~ite29_Out-1572570503| ~y$w_buff1_used~0_In-1572570503) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1572570503, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1572570503, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1572570503, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1572570503} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1572570503, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1572570503, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1572570503, P2Thread1of1ForFork3_#t~ite29=|P2Thread1of1ForFork3_#t~ite29_Out-1572570503|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1572570503} AuxVars[] AssignedVars[P2Thread1of1ForFork3_#t~ite29] because there is no mapped edge [2019-12-07 18:57:22,574 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [785] [785] L804-->L805: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd3~0_In1102816513 256) 0)) (.cse1 (= ~y$r_buff0_thd3~0_Out1102816513 ~y$r_buff0_thd3~0_In1102816513)) (.cse2 (= (mod ~y$w_buff0_used~0_In1102816513 256) 0))) (or (and .cse0 .cse1) (and (not .cse0) (= ~y$r_buff0_thd3~0_Out1102816513 0) (not .cse2)) (and .cse1 .cse2))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1102816513, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1102816513} OutVars{P2Thread1of1ForFork3_#t~ite30=|P2Thread1of1ForFork3_#t~ite30_Out1102816513|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1102816513, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out1102816513} AuxVars[] AssignedVars[P2Thread1of1ForFork3_#t~ite30, ~y$r_buff0_thd3~0] because there is no mapped edge [2019-12-07 18:57:22,574 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [794] [794] L805-->L805-2: Formula: (let ((.cse0 (= (mod ~y$r_buff1_thd3~0_In-292692101 256) 0)) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In-292692101 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In-292692101 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In-292692101 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork3_#t~ite31_Out-292692101|)) (and (= ~y$r_buff1_thd3~0_In-292692101 |P2Thread1of1ForFork3_#t~ite31_Out-292692101|) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-292692101, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-292692101, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-292692101, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-292692101} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-292692101, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-292692101, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-292692101, P2Thread1of1ForFork3_#t~ite31=|P2Thread1of1ForFork3_#t~ite31_Out-292692101|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-292692101} AuxVars[] AssignedVars[P2Thread1of1ForFork3_#t~ite31] because there is no mapped edge [2019-12-07 18:57:22,574 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L805-2-->P2EXIT: Formula: (and (= v_~__unbuffered_cnt~0_71 (+ v_~__unbuffered_cnt~0_72 1)) (= |v_P2Thread1of1ForFork3_#t~ite31_34| v_~y$r_buff1_thd3~0_46) (= 0 |v_P2Thread1of1ForFork3_#res.base_3|) (= |v_P2Thread1of1ForFork3_#res.offset_3| 0)) InVars {P2Thread1of1ForFork3_#t~ite31=|v_P2Thread1of1ForFork3_#t~ite31_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72} OutVars{~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_46, P2Thread1of1ForFork3_#t~ite31=|v_P2Thread1of1ForFork3_#t~ite31_33|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_71, P2Thread1of1ForFork3_#res.base=|v_P2Thread1of1ForFork3_#res.base_3|, P2Thread1of1ForFork3_#res.offset=|v_P2Thread1of1ForFork3_#res.offset_3|} AuxVars[] AssignedVars[~y$r_buff1_thd3~0, P2Thread1of1ForFork3_#t~ite31, ~__unbuffered_cnt~0, P2Thread1of1ForFork3_#res.base, P2Thread1of1ForFork3_#res.offset] because there is no mapped edge [2019-12-07 18:57:22,574 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [837] [837] L765-->L765-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In2112425768 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite9_Out2112425768| ~y$w_buff0~0_In2112425768) (not .cse0) (= |P1Thread1of1ForFork2_#t~ite8_In2112425768| |P1Thread1of1ForFork2_#t~ite8_Out2112425768|)) (and (= |P1Thread1of1ForFork2_#t~ite8_Out2112425768| |P1Thread1of1ForFork2_#t~ite9_Out2112425768|) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In2112425768 256)))) (or (and .cse1 (= (mod ~y$r_buff1_thd2~0_In2112425768 256) 0)) (and .cse1 (= 0 (mod ~y$w_buff1_used~0_In2112425768 256))) (= (mod ~y$w_buff0_used~0_In2112425768 256) 0))) (= |P1Thread1of1ForFork2_#t~ite8_Out2112425768| ~y$w_buff0~0_In2112425768) .cse0))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2112425768, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2112425768, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_In2112425768|, ~y$w_buff0~0=~y$w_buff0~0_In2112425768, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2112425768, ~weak$$choice2~0=~weak$$choice2~0_In2112425768, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2112425768} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2112425768, P1Thread1of1ForFork2_#t~ite9=|P1Thread1of1ForFork2_#t~ite9_Out2112425768|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2112425768, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out2112425768|, ~y$w_buff0~0=~y$w_buff0~0_In2112425768, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2112425768, ~weak$$choice2~0=~weak$$choice2~0_In2112425768, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2112425768} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 18:57:22,575 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [836] [836] L766-->L766-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In-925856461 256) 0))) (or (and (= |P1Thread1of1ForFork2_#t~ite12_Out-925856461| |P1Thread1of1ForFork2_#t~ite11_Out-925856461|) (= ~y$w_buff1~0_In-925856461 |P1Thread1of1ForFork2_#t~ite11_Out-925856461|) (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In-925856461 256) 0))) (or (and (= (mod ~y$r_buff1_thd2~0_In-925856461 256) 0) .cse0) (and (= 0 (mod ~y$w_buff1_used~0_In-925856461 256)) .cse0) (= 0 (mod ~y$w_buff0_used~0_In-925856461 256)))) .cse1) (and (not .cse1) (= |P1Thread1of1ForFork2_#t~ite11_In-925856461| |P1Thread1of1ForFork2_#t~ite11_Out-925856461|) (= |P1Thread1of1ForFork2_#t~ite12_Out-925856461| ~y$w_buff1~0_In-925856461)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-925856461, ~y$w_buff1~0=~y$w_buff1~0_In-925856461, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-925856461, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-925856461, P1Thread1of1ForFork2_#t~ite11=|P1Thread1of1ForFork2_#t~ite11_In-925856461|, ~weak$$choice2~0=~weak$$choice2~0_In-925856461, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-925856461} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-925856461, ~y$w_buff1~0=~y$w_buff1~0_In-925856461, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-925856461, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-925856461, P1Thread1of1ForFork2_#t~ite12=|P1Thread1of1ForFork2_#t~ite12_Out-925856461|, P1Thread1of1ForFork2_#t~ite11=|P1Thread1of1ForFork2_#t~ite11_Out-925856461|, ~weak$$choice2~0=~weak$$choice2~0_In-925856461, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-925856461} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite12, P1Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-12-07 18:57:22,577 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L769-->L770: Formula: (and (= v_~y$r_buff0_thd2~0_106 v_~y$r_buff0_thd2~0_105) (not (= (mod v_~weak$$choice2~0_28 256) 0))) InVars {~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_106, ~weak$$choice2~0=v_~weak$$choice2~0_28} OutVars{P1Thread1of1ForFork2_#t~ite19=|v_P1Thread1of1ForFork2_#t~ite19_6|, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_105, P1Thread1of1ForFork2_#t~ite20=|v_P1Thread1of1ForFork2_#t~ite20_9|, P1Thread1of1ForFork2_#t~ite21=|v_P1Thread1of1ForFork2_#t~ite21_7|, ~weak$$choice2~0=v_~weak$$choice2~0_28} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite19, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite20, P1Thread1of1ForFork2_#t~ite21] because there is no mapped edge [2019-12-07 18:57:22,577 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] L770-->L770-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In454174320 256)))) (or (and (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In454174320 256) 0))) (or (and (= 0 (mod ~y$r_buff1_thd2~0_In454174320 256)) .cse0) (= (mod ~y$w_buff0_used~0_In454174320 256) 0) (and .cse0 (= (mod ~y$w_buff1_used~0_In454174320 256) 0)))) (= |P1Thread1of1ForFork2_#t~ite23_Out454174320| ~y$r_buff1_thd2~0_In454174320) .cse1 (= |P1Thread1of1ForFork2_#t~ite24_Out454174320| |P1Thread1of1ForFork2_#t~ite23_Out454174320|)) (and (= |P1Thread1of1ForFork2_#t~ite24_Out454174320| ~y$r_buff1_thd2~0_In454174320) (= |P1Thread1of1ForFork2_#t~ite23_In454174320| |P1Thread1of1ForFork2_#t~ite23_Out454174320|) (not .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In454174320, ~y$w_buff0_used~0=~y$w_buff0_used~0_In454174320, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In454174320, P1Thread1of1ForFork2_#t~ite23=|P1Thread1of1ForFork2_#t~ite23_In454174320|, ~weak$$choice2~0=~weak$$choice2~0_In454174320, ~y$w_buff1_used~0=~y$w_buff1_used~0_In454174320} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In454174320, ~y$w_buff0_used~0=~y$w_buff0_used~0_In454174320, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In454174320, P1Thread1of1ForFork2_#t~ite23=|P1Thread1of1ForFork2_#t~ite23_Out454174320|, ~weak$$choice2~0=~weak$$choice2~0_In454174320, P1Thread1of1ForFork2_#t~ite24=|P1Thread1of1ForFork2_#t~ite24_Out454174320|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In454174320} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite23, P1Thread1of1ForFork2_#t~ite24] because there is no mapped edge [2019-12-07 18:57:22,577 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [735] [735] L772-->L780: Formula: (and (= (+ v_~__unbuffered_cnt~0_17 1) v_~__unbuffered_cnt~0_16) (not (= 0 (mod v_~y$flush_delayed~0_10 256))) (= v_~y~0_26 v_~y$mem_tmp~0_7) (= 0 v_~y$flush_delayed~0_9)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_7, ~y$flush_delayed~0=v_~y$flush_delayed~0_10, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_17} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_7, ~y$flush_delayed~0=v_~y$flush_delayed~0_9, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_16, ~y~0=v_~y~0_26, P1Thread1of1ForFork2_#t~ite25=|v_P1Thread1of1ForFork2_#t~ite25_5|} AuxVars[] AssignedVars[~y$flush_delayed~0, ~__unbuffered_cnt~0, ~y~0, P1Thread1of1ForFork2_#t~ite25] because there is no mapped edge [2019-12-07 18:57:22,577 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [783] [783] L830-->L830-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd4~0_In1515198035 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In1515198035 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P3Thread1of1ForFork0_#t~ite36_Out1515198035|)) (and (or .cse1 .cse0) (= |P3Thread1of1ForFork0_#t~ite36_Out1515198035| ~y$r_buff0_thd4~0_In1515198035)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1515198035, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1515198035} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1515198035, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1515198035, P3Thread1of1ForFork0_#t~ite36=|P3Thread1of1ForFork0_#t~ite36_Out1515198035|} AuxVars[] AssignedVars[P3Thread1of1ForFork0_#t~ite36] because there is no mapped edge [2019-12-07 18:57:22,578 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [792] [792] L831-->L831-2: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In926361585 256) 0)) (.cse1 (= 0 (mod ~y$r_buff1_thd4~0_In926361585 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In926361585 256))) (.cse3 (= 0 (mod ~y$r_buff0_thd4~0_In926361585 256)))) (or (and (= ~y$r_buff1_thd4~0_In926361585 |P3Thread1of1ForFork0_#t~ite37_Out926361585|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P3Thread1of1ForFork0_#t~ite37_Out926361585|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In926361585, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In926361585, ~y$w_buff0_used~0=~y$w_buff0_used~0_In926361585, ~y$w_buff1_used~0=~y$w_buff1_used~0_In926361585} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In926361585, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In926361585, ~y$w_buff0_used~0=~y$w_buff0_used~0_In926361585, P3Thread1of1ForFork0_#t~ite37=|P3Thread1of1ForFork0_#t~ite37_Out926361585|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In926361585} AuxVars[] AssignedVars[P3Thread1of1ForFork0_#t~ite37] because there is no mapped edge [2019-12-07 18:57:22,578 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [833] [833] L831-2-->P3EXIT: Formula: (and (= |v_P3Thread1of1ForFork0_#res.base_3| 0) (= v_~__unbuffered_cnt~0_146 (+ v_~__unbuffered_cnt~0_147 1)) (= |v_P3Thread1of1ForFork0_#t~ite37_64| v_~y$r_buff1_thd4~0_141) (= 0 |v_P3Thread1of1ForFork0_#res.offset_3|)) InVars {P3Thread1of1ForFork0_#t~ite37=|v_P3Thread1of1ForFork0_#t~ite37_64|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_147} OutVars{~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_141, P3Thread1of1ForFork0_#res.offset=|v_P3Thread1of1ForFork0_#res.offset_3|, P3Thread1of1ForFork0_#t~ite37=|v_P3Thread1of1ForFork0_#t~ite37_63|, P3Thread1of1ForFork0_#res.base=|v_P3Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_146} AuxVars[] AssignedVars[~y$r_buff1_thd4~0, P3Thread1of1ForFork0_#res.offset, P3Thread1of1ForFork0_#t~ite37, P3Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 18:57:22,578 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L856-1-->L862: Formula: (and (= v_~main$tmp_guard0~0_12 (ite (= 0 (ite (= 4 v_~__unbuffered_cnt~0_38) 1 0)) 0 1)) (not (= 0 (mod v_~main$tmp_guard0~0_12 256)))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38} OutVars{ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_12|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_12} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet41, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:57:22,578 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L862-2-->L862-4: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In951771507 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In951771507 256)))) (or (and (or .cse0 .cse1) (= ~y~0_In951771507 |ULTIMATE.start_main_#t~ite42_Out951771507|)) (and (not .cse1) (not .cse0) (= ~y$w_buff1~0_In951771507 |ULTIMATE.start_main_#t~ite42_Out951771507|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In951771507, ~y~0=~y~0_In951771507, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In951771507, ~y$w_buff1_used~0=~y$w_buff1_used~0_In951771507} OutVars{~y$w_buff1~0=~y$w_buff1~0_In951771507, ~y~0=~y~0_In951771507, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_Out951771507|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In951771507, ~y$w_buff1_used~0=~y$w_buff1_used~0_In951771507} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 18:57:22,578 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L862-4-->L863: Formula: (= v_~y~0_20 |v_ULTIMATE.start_main_#t~ite42_7|) InVars {ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_7|} OutVars{ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_6|, ~y~0=v_~y~0_20, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43, ~y~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 18:57:22,578 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L863-->L863-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In1862333176 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In1862333176 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite44_Out1862333176| ~y$w_buff0_used~0_In1862333176)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite44_Out1862333176| 0) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1862333176, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1862333176} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1862333176, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1862333176, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_Out1862333176|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-12-07 18:57:22,579 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L864-->L864-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1660019355 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In1660019355 256))) (.cse2 (= (mod ~y$r_buff1_thd0~0_In1660019355 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In1660019355 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite45_Out1660019355|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~y$w_buff1_used~0_In1660019355 |ULTIMATE.start_main_#t~ite45_Out1660019355|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1660019355, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1660019355, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1660019355, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1660019355} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1660019355, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1660019355, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1660019355, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out1660019355|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1660019355} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite45] because there is no mapped edge [2019-12-07 18:57:22,579 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [791] [791] L865-->L865-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1651619703 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd0~0_In1651619703 256) 0))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite46_Out1651619703|) (not .cse1)) (and (= ~y$r_buff0_thd0~0_In1651619703 |ULTIMATE.start_main_#t~ite46_Out1651619703|) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1651619703, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1651619703} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1651619703, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1651619703, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out1651619703|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46] because there is no mapped edge [2019-12-07 18:57:22,580 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L866-->L866-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In1903582197 256))) (.cse1 (= (mod ~y$r_buff0_thd0~0_In1903582197 256) 0)) (.cse2 (= (mod ~y$w_buff1_used~0_In1903582197 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd0~0_In1903582197 256)))) (or (and (= |ULTIMATE.start_main_#t~ite47_Out1903582197| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~y$r_buff1_thd0~0_In1903582197 |ULTIMATE.start_main_#t~ite47_Out1903582197|) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1903582197, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1903582197, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1903582197, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1903582197} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1903582197, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1903582197, ULTIMATE.start_main_#t~ite47=|ULTIMATE.start_main_#t~ite47_Out1903582197|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1903582197, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1903582197} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] because there is no mapped edge [2019-12-07 18:57:22,580 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L866-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_~y$r_buff1_thd0~0_137 |v_ULTIMATE.start_main_#t~ite47_48|) (= v_~main$tmp_guard1~0_20 (ite (= 0 (ite (not (and (= 0 v_~__unbuffered_p3_EBX~0_23) (= 0 v_~__unbuffered_p1_EAX~0_25) (= 0 v_~__unbuffered_p2_EAX~0_92) (= 0 v_~__unbuffered_p0_EAX~0_41) (= 1 v_~__unbuffered_p3_EAX~0_23))) 1 0)) 0 1)) (= v_ULTIMATE.start___VERIFIER_assert_~expression_17 0) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_12| (mod v_~main$tmp_guard1~0_20 256)) (= v_ULTIMATE.start___VERIFIER_assert_~expression_17 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_12|)) InVars {~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_41, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_25, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_23, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_48|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_92, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_23} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_41, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_17, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_25, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_23, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_47|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_20, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_92, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_23, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_137, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_12|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ULTIMATE.start_main_#t~ite47, ~main$tmp_guard1~0, ~y$r_buff1_thd0~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:57:22,635 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_aa315b34-122a-4185-9e3e-d45e078a5220/bin/uautomizer/witness.graphml [2019-12-07 18:57:22,635 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:57:22,636 INFO L168 Benchmark]: Toolchain (without parser) took 250259.32 ms. Allocated memory was 1.0 GB in the beginning and 9.1 GB in the end (delta: 8.1 GB). Free memory was 934.5 MB in the beginning and 3.5 GB in the end (delta: -2.6 GB). Peak memory consumption was 5.5 GB. Max. memory is 11.5 GB. [2019-12-07 18:57:22,636 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 956.0 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:57:22,636 INFO L168 Benchmark]: CACSL2BoogieTranslator took 387.18 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 79.7 MB). Free memory was 934.5 MB in the beginning and 1.0 GB in the end (delta: -110.3 MB). Peak memory consumption was 18.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:57:22,637 INFO L168 Benchmark]: Boogie Procedure Inliner took 39.24 ms. Allocated memory is still 1.1 GB. Free memory is still 1.0 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:57:22,637 INFO L168 Benchmark]: Boogie Preprocessor took 27.70 ms. Allocated memory is still 1.1 GB. Free memory is still 1.0 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:57:22,637 INFO L168 Benchmark]: RCFGBuilder took 390.58 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 988.5 MB in the end (delta: 50.9 MB). Peak memory consumption was 50.9 MB. Max. memory is 11.5 GB. [2019-12-07 18:57:22,637 INFO L168 Benchmark]: TraceAbstraction took 249341.63 ms. Allocated memory was 1.1 GB in the beginning and 9.1 GB in the end (delta: 8.0 GB). Free memory was 988.5 MB in the beginning and 3.6 GB in the end (delta: -2.6 GB). Peak memory consumption was 5.4 GB. Max. memory is 11.5 GB. [2019-12-07 18:57:22,637 INFO L168 Benchmark]: Witness Printer took 69.90 ms. Allocated memory is still 9.1 GB. Free memory was 3.6 GB in the beginning and 3.5 GB in the end (delta: 49.3 MB). Peak memory consumption was 49.3 MB. Max. memory is 11.5 GB. [2019-12-07 18:57:22,639 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 956.0 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 387.18 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 79.7 MB). Free memory was 934.5 MB in the beginning and 1.0 GB in the end (delta: -110.3 MB). Peak memory consumption was 18.4 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 39.24 ms. Allocated memory is still 1.1 GB. Free memory is still 1.0 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 27.70 ms. Allocated memory is still 1.1 GB. Free memory is still 1.0 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 390.58 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 988.5 MB in the end (delta: 50.9 MB). Peak memory consumption was 50.9 MB. Max. memory is 11.5 GB. * TraceAbstraction took 249341.63 ms. Allocated memory was 1.1 GB in the beginning and 9.1 GB in the end (delta: 8.0 GB). Free memory was 988.5 MB in the beginning and 3.6 GB in the end (delta: -2.6 GB). Peak memory consumption was 5.4 GB. Max. memory is 11.5 GB. * Witness Printer took 69.90 ms. Allocated memory is still 9.1 GB. Free memory was 3.6 GB in the beginning and 3.5 GB in the end (delta: 49.3 MB). Peak memory consumption was 49.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.8s, 183 ProgramPointsBefore, 88 ProgramPointsAfterwards, 211 TransitionsBefore, 95 TransitionsAfterwards, 18126 CoEnabledTransitionPairs, 8 FixpointIterations, 39 TrivialSequentialCompositions, 53 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 35 ConcurrentYvCompositions, 26 ChoiceCompositions, 7374 VarBasedMoverChecksPositive, 271 VarBasedMoverChecksNegative, 80 SemBasedMoverChecksPositive, 263 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.1s, 0 MoverChecksTotal, 74129 CheckedPairsTotal, 127 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L850] FCALL, FORK 0 pthread_create(&t941, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L852] FCALL, FORK 0 pthread_create(&t942, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L854] FCALL, FORK 0 pthread_create(&t943, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L856] FCALL, FORK 0 pthread_create(&t944, ((void *)0), P3, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L785] 3 y$w_buff1 = y$w_buff0 [L786] 3 y$w_buff0 = 1 [L787] 3 y$w_buff1_used = y$w_buff0_used [L788] 3 y$w_buff0_used = (_Bool)1 [L801] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=1, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=0] [L815] 4 z = 1 [L818] 4 a = 1 [L821] 4 __unbuffered_p3_EAX = a [L824] 4 __unbuffered_p3_EBX = b VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=1, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L827] EXPR 4 y$w_buff0_used && y$r_buff0_thd4 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd4 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=1, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L801] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L827] 4 y = y$w_buff0_used && y$r_buff0_thd4 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd4 ? y$w_buff1 : y) [L828] 4 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd4 ? (_Bool)0 : y$w_buff0_used [L757] 2 x = 1 [L760] 2 weak$$choice0 = __VERIFIER_nondet_bool() [L761] 2 weak$$choice2 = __VERIFIER_nondet_bool() [L762] 2 y$flush_delayed = weak$$choice2 [L763] 2 y$mem_tmp = y VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=1, y=0, y$flush_delayed=1, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=1, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L802] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L829] 4 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd4 || y$w_buff1_used && y$r_buff1_thd4 ? (_Bool)0 : y$w_buff1_used [L764] EXPR 2 !y$w_buff0_used || !y$r_buff0_thd2 && !y$w_buff1_used || !y$r_buff0_thd2 && !y$r_buff1_thd2 ? y : (y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : y$w_buff1) VAL [!y$w_buff0_used || !y$r_buff0_thd2 && !y$w_buff1_used || !y$r_buff0_thd2 && !y$r_buff1_thd2 ? y : (y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : y$w_buff1)=0, \result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=1, y=0, y$flush_delayed=1, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=1, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L803] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L764] 2 y = !y$w_buff0_used || !y$r_buff0_thd2 && !y$w_buff1_used || !y$r_buff0_thd2 && !y$r_buff1_thd2 ? y : (y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : y$w_buff1) [L765] 2 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd2 && !y$w_buff1_used || !y$r_buff0_thd2 && !y$r_buff1_thd2 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : y$w_buff0)) [L766] 2 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd2 && !y$w_buff1_used || !y$r_buff0_thd2 && !y$r_buff1_thd2 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff1 : y$w_buff1)) [L767] EXPR 2 weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd2 && !y$w_buff1_used || !y$r_buff0_thd2 && !y$r_buff1_thd2 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used)) VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd2 && !y$w_buff1_used || !y$r_buff0_thd2 && !y$r_buff1_thd2 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used))=0, x=1, y=0, y$flush_delayed=1, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=1, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L767] 2 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd2 && !y$w_buff1_used || !y$r_buff0_thd2 && !y$r_buff1_thd2 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used)) [L768] EXPR 2 weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd2 && !y$w_buff1_used || !y$r_buff0_thd2 && !y$r_buff1_thd2 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd2 && !y$w_buff1_used || !y$r_buff0_thd2 && !y$r_buff1_thd2 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=1, y=0, y$flush_delayed=1, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=1, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L768] 2 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd2 && !y$w_buff1_used || !y$r_buff0_thd2 && !y$r_buff1_thd2 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L770] 2 y$r_buff1_thd2 = weak$$choice2 ? y$r_buff1_thd2 : (!y$w_buff0_used || !y$r_buff0_thd2 && !y$w_buff1_used || !y$r_buff0_thd2 && !y$r_buff1_thd2 ? y$r_buff1_thd2 : (y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L771] 2 __unbuffered_p1_EAX = y VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=1, y=0, y$flush_delayed=1, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=1, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L830] 4 y$r_buff0_thd4 = y$w_buff0_used && y$r_buff0_thd4 ? (_Bool)0 : y$r_buff0_thd4 [L862] 0 y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=1, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=1, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L863] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L864] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L865] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 171 locations, 2 error locations. Result: UNSAFE, OverallTime: 249.1s, OverallIterations: 40, TraceHistogramMax: 1, AutomataDifference: 64.1s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 7240 SDtfs, 11186 SDslu, 24736 SDs, 0 SdLazy, 19170 SolverSat, 641 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 14.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 548 GetRequests, 43 SyntacticMatches, 28 SemanticMatches, 477 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3498 ImplicationChecksByTransitivity, 7.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=290536occurred in iteration=8, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 149.9s AutomataMinimizationTime, 39 MinimizatonAttempts, 530072 StatesRemovedByMinimization, 33 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 3.4s InterpolantComputationTime, 1544 NumberOfCodeBlocks, 1544 NumberOfCodeBlocksAsserted, 40 NumberOfCheckSat, 1446 ConstructedInterpolants, 0 QuantifiedInterpolants, 503202 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 39 InterpolantComputations, 39 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...