./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix040_tso.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_fd09fa57-94d0-4642-b045-576cc7a10020/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_fd09fa57-94d0-4642-b045-576cc7a10020/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_fd09fa57-94d0-4642-b045-576cc7a10020/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_fd09fa57-94d0-4642-b045-576cc7a10020/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix040_tso.oepc.i -s /tmp/vcloud-vcloud-master/worker/run_dir_fd09fa57-94d0-4642-b045-576cc7a10020/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_fd09fa57-94d0-4642-b045-576cc7a10020/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ed88644fb34bfc87c0dddcdfd3be21ef107de97e .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:14:48,423 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:14:48,424 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:14:48,432 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:14:48,432 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:14:48,433 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:14:48,434 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:14:48,435 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:14:48,436 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:14:48,437 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:14:48,438 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:14:48,438 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:14:48,439 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:14:48,439 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:14:48,440 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:14:48,441 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:14:48,441 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:14:48,442 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:14:48,443 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:14:48,445 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:14:48,446 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:14:48,447 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:14:48,448 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:14:48,448 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:14:48,450 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:14:48,450 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:14:48,450 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:14:48,451 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:14:48,451 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:14:48,451 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:14:48,451 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:14:48,452 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:14:48,452 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:14:48,453 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:14:48,453 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:14:48,453 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:14:48,454 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:14:48,454 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:14:48,454 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:14:48,455 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:14:48,455 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:14:48,455 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_fd09fa57-94d0-4642-b045-576cc7a10020/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 18:14:48,465 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:14:48,465 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:14:48,466 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:14:48,466 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:14:48,466 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:14:48,466 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:14:48,466 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:14:48,466 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:14:48,466 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:14:48,466 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:14:48,466 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 18:14:48,467 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 18:14:48,467 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 18:14:48,467 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:14:48,467 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:14:48,467 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:14:48,467 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 18:14:48,467 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:14:48,467 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:14:48,467 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 18:14:48,467 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 18:14:48,468 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:14:48,468 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:14:48,468 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 18:14:48,468 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 18:14:48,468 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:14:48,468 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 18:14:48,468 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 18:14:48,468 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:14:48,469 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_fd09fa57-94d0-4642-b045-576cc7a10020/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ed88644fb34bfc87c0dddcdfd3be21ef107de97e [2019-12-07 18:14:48,572 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:14:48,580 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:14:48,583 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:14:48,584 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:14:48,585 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:14:48,585 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_fd09fa57-94d0-4642-b045-576cc7a10020/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix040_tso.oepc.i [2019-12-07 18:14:48,632 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_fd09fa57-94d0-4642-b045-576cc7a10020/bin/uautomizer/data/4dd6a7d40/329009567f754c809b027d1446f5e334/FLAGc8299066f [2019-12-07 18:14:49,027 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:14:49,027 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_fd09fa57-94d0-4642-b045-576cc7a10020/sv-benchmarks/c/pthread-wmm/mix040_tso.oepc.i [2019-12-07 18:14:49,038 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_fd09fa57-94d0-4642-b045-576cc7a10020/bin/uautomizer/data/4dd6a7d40/329009567f754c809b027d1446f5e334/FLAGc8299066f [2019-12-07 18:14:49,046 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_fd09fa57-94d0-4642-b045-576cc7a10020/bin/uautomizer/data/4dd6a7d40/329009567f754c809b027d1446f5e334 [2019-12-07 18:14:49,048 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:14:49,049 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:14:49,050 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:14:49,050 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:14:49,052 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:14:49,052 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:14:49" (1/1) ... [2019-12-07 18:14:49,054 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7d8e373 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:14:49, skipping insertion in model container [2019-12-07 18:14:49,054 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:14:49" (1/1) ... [2019-12-07 18:14:49,059 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:14:49,087 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:14:49,328 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:14:49,336 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:14:49,382 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:14:49,430 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:14:49,430 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:14:49 WrapperNode [2019-12-07 18:14:49,430 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:14:49,431 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:14:49,431 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:14:49,431 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:14:49,437 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:14:49" (1/1) ... [2019-12-07 18:14:49,451 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:14:49" (1/1) ... [2019-12-07 18:14:49,474 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:14:49,474 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:14:49,474 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:14:49,474 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:14:49,481 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:14:49" (1/1) ... [2019-12-07 18:14:49,481 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:14:49" (1/1) ... [2019-12-07 18:14:49,485 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:14:49" (1/1) ... [2019-12-07 18:14:49,485 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:14:49" (1/1) ... [2019-12-07 18:14:49,493 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:14:49" (1/1) ... [2019-12-07 18:14:49,496 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:14:49" (1/1) ... [2019-12-07 18:14:49,499 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:14:49" (1/1) ... [2019-12-07 18:14:49,502 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:14:49,503 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:14:49,503 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:14:49,503 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:14:49,503 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:14:49" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_fd09fa57-94d0-4642-b045-576cc7a10020/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:14:49,545 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 18:14:49,546 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 18:14:49,546 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 18:14:49,546 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 18:14:49,546 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 18:14:49,546 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 18:14:49,546 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 18:14:49,546 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 18:14:49,547 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 18:14:49,547 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 18:14:49,547 INFO L130 BoogieDeclarations]: Found specification of procedure P3 [2019-12-07 18:14:49,547 INFO L138 BoogieDeclarations]: Found implementation of procedure P3 [2019-12-07 18:14:49,547 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 18:14:49,547 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:14:49,547 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:14:49,549 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 18:14:49,920 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:14:49,920 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 18:14:49,921 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:14:49 BoogieIcfgContainer [2019-12-07 18:14:49,921 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:14:49,922 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 18:14:49,922 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 18:14:49,924 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 18:14:49,924 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 06:14:49" (1/3) ... [2019-12-07 18:14:49,924 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6615366b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:14:49, skipping insertion in model container [2019-12-07 18:14:49,925 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:14:49" (2/3) ... [2019-12-07 18:14:49,925 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6615366b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:14:49, skipping insertion in model container [2019-12-07 18:14:49,925 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:14:49" (3/3) ... [2019-12-07 18:14:49,926 INFO L109 eAbstractionObserver]: Analyzing ICFG mix040_tso.oepc.i [2019-12-07 18:14:49,932 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 18:14:49,932 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 18:14:49,937 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 18:14:49,938 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 18:14:49,962 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork3_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,962 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork3_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,962 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork3_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,963 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork3_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,963 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork3_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,963 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork3_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,963 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,963 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,963 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,964 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,964 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,964 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,964 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,964 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,964 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,964 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,964 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,965 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,965 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,965 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,965 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,965 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,965 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,965 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,965 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,965 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,966 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,966 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,966 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,966 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,966 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,966 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,966 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,966 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,966 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,967 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,967 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,967 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,967 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,967 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,967 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,968 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,968 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,968 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,968 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,968 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,968 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,968 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,969 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,969 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,969 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,969 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,969 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,969 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,969 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,969 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,969 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,970 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,970 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,970 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,970 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,970 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,970 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,970 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,970 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,970 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,971 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,971 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,971 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,971 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,971 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,971 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,971 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,971 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,972 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,972 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,972 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,972 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,972 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,972 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,972 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,972 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,972 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,973 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,973 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,973 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,973 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,973 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,973 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,973 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,973 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,973 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,974 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,974 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,974 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,974 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,974 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,974 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,974 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,974 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:14:49,988 INFO L249 AbstractCegarLoop]: Starting to check reachability of 7 error locations. [2019-12-07 18:14:50,001 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 18:14:50,001 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 18:14:50,001 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 18:14:50,001 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:14:50,001 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:14:50,001 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 18:14:50,001 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:14:50,001 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 18:14:50,012 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 193 places, 227 transitions [2019-12-07 18:14:50,013 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 193 places, 227 transitions [2019-12-07 18:14:50,070 INFO L134 PetriNetUnfolder]: 47/223 cut-off events. [2019-12-07 18:14:50,070 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:14:50,081 INFO L76 FinitePrefix]: Finished finitePrefix Result has 236 conditions, 223 events. 47/223 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 585 event pairs. 12/186 useless extension candidates. Maximal degree in co-relation 190. Up to 2 conditions per place. [2019-12-07 18:14:50,096 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 193 places, 227 transitions [2019-12-07 18:14:50,125 INFO L134 PetriNetUnfolder]: 47/223 cut-off events. [2019-12-07 18:14:50,125 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:14:50,130 INFO L76 FinitePrefix]: Finished finitePrefix Result has 236 conditions, 223 events. 47/223 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 585 event pairs. 12/186 useless extension candidates. Maximal degree in co-relation 190. Up to 2 conditions per place. [2019-12-07 18:14:50,147 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 18432 [2019-12-07 18:14:50,147 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 18:14:53,407 WARN L192 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 97 [2019-12-07 18:14:53,508 INFO L206 etLargeBlockEncoding]: Checked pairs total: 89209 [2019-12-07 18:14:53,509 INFO L214 etLargeBlockEncoding]: Total number of compositions: 126 [2019-12-07 18:14:53,511 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 101 places, 110 transitions [2019-12-07 18:15:43,223 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 219914 states. [2019-12-07 18:15:43,224 INFO L276 IsEmpty]: Start isEmpty. Operand 219914 states. [2019-12-07 18:15:43,229 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-12-07 18:15:43,229 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:15:43,230 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:15:43,230 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:15:43,234 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:15:43,234 INFO L82 PathProgramCache]: Analyzing trace with hash -82893504, now seen corresponding path program 1 times [2019-12-07 18:15:43,239 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:15:43,240 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [433560365] [2019-12-07 18:15:43,240 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:15:43,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:15:43,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:15:43,401 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [433560365] [2019-12-07 18:15:43,401 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:15:43,401 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:15:43,402 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [300566109] [2019-12-07 18:15:43,405 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:15:43,405 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:15:43,413 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:15:43,414 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:15:43,415 INFO L87 Difference]: Start difference. First operand 219914 states. Second operand 3 states. [2019-12-07 18:15:46,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:15:46,484 INFO L93 Difference]: Finished difference Result 219314 states and 1046746 transitions. [2019-12-07 18:15:46,485 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:15:46,486 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-12-07 18:15:46,486 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:15:47,440 INFO L225 Difference]: With dead ends: 219314 [2019-12-07 18:15:47,440 INFO L226 Difference]: Without dead ends: 214946 [2019-12-07 18:15:47,441 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:15:54,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214946 states. [2019-12-07 18:15:57,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214946 to 214946. [2019-12-07 18:15:57,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 214946 states. [2019-12-07 18:15:58,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214946 states to 214946 states and 1026726 transitions. [2019-12-07 18:15:58,126 INFO L78 Accepts]: Start accepts. Automaton has 214946 states and 1026726 transitions. Word has length 7 [2019-12-07 18:15:58,127 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:15:58,127 INFO L462 AbstractCegarLoop]: Abstraction has 214946 states and 1026726 transitions. [2019-12-07 18:15:58,127 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:15:58,127 INFO L276 IsEmpty]: Start isEmpty. Operand 214946 states and 1026726 transitions. [2019-12-07 18:15:58,131 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:15:58,131 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:15:58,131 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:15:58,131 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:15:58,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:15:58,132 INFO L82 PathProgramCache]: Analyzing trace with hash -570286936, now seen corresponding path program 1 times [2019-12-07 18:15:58,132 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:15:58,132 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [158867325] [2019-12-07 18:15:58,132 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:15:58,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:15:58,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:15:58,186 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [158867325] [2019-12-07 18:15:58,186 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:15:58,186 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:15:58,187 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1296576874] [2019-12-07 18:15:58,187 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:15:58,188 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:15:58,188 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:15:58,188 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:15:58,188 INFO L87 Difference]: Start difference. First operand 214946 states and 1026726 transitions. Second operand 4 states. [2019-12-07 18:16:02,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:16:02,385 INFO L93 Difference]: Finished difference Result 345446 states and 1588000 transitions. [2019-12-07 18:16:02,386 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:16:02,386 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 18:16:02,386 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:16:03,457 INFO L225 Difference]: With dead ends: 345446 [2019-12-07 18:16:03,458 INFO L226 Difference]: Without dead ends: 345348 [2019-12-07 18:16:03,458 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:16:12,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 345348 states. [2019-12-07 18:16:18,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 345348 to 319828. [2019-12-07 18:16:18,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 319828 states. [2019-12-07 18:16:19,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 319828 states to 319828 states and 1482965 transitions. [2019-12-07 18:16:19,155 INFO L78 Accepts]: Start accepts. Automaton has 319828 states and 1482965 transitions. Word has length 13 [2019-12-07 18:16:19,155 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:16:19,155 INFO L462 AbstractCegarLoop]: Abstraction has 319828 states and 1482965 transitions. [2019-12-07 18:16:19,155 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:16:19,155 INFO L276 IsEmpty]: Start isEmpty. Operand 319828 states and 1482965 transitions. [2019-12-07 18:16:19,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 18:16:19,162 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:16:19,162 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:16:19,162 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:16:19,162 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:16:19,163 INFO L82 PathProgramCache]: Analyzing trace with hash -272405391, now seen corresponding path program 1 times [2019-12-07 18:16:19,163 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:16:19,163 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [397452753] [2019-12-07 18:16:19,163 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:16:19,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:16:19,215 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:16:19,215 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [397452753] [2019-12-07 18:16:19,215 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:16:19,215 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:16:19,216 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [635701734] [2019-12-07 18:16:19,216 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:16:19,216 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:16:19,216 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:16:19,216 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:16:19,216 INFO L87 Difference]: Start difference. First operand 319828 states and 1482965 transitions. Second operand 4 states. [2019-12-07 18:16:25,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:16:25,826 INFO L93 Difference]: Finished difference Result 454248 states and 2062725 transitions. [2019-12-07 18:16:25,827 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:16:25,827 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 18:16:25,827 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:16:27,273 INFO L225 Difference]: With dead ends: 454248 [2019-12-07 18:16:27,273 INFO L226 Difference]: Without dead ends: 454122 [2019-12-07 18:16:27,274 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:16:37,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454122 states. [2019-12-07 18:16:44,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454122 to 386652. [2019-12-07 18:16:44,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 386652 states. [2019-12-07 18:16:45,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386652 states to 386652 states and 1780389 transitions. [2019-12-07 18:16:45,931 INFO L78 Accepts]: Start accepts. Automaton has 386652 states and 1780389 transitions. Word has length 15 [2019-12-07 18:16:45,932 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:16:45,932 INFO L462 AbstractCegarLoop]: Abstraction has 386652 states and 1780389 transitions. [2019-12-07 18:16:45,932 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:16:45,932 INFO L276 IsEmpty]: Start isEmpty. Operand 386652 states and 1780389 transitions. [2019-12-07 18:16:45,935 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 18:16:45,935 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:16:45,935 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:16:45,936 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:16:45,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:16:45,936 INFO L82 PathProgramCache]: Analyzing trace with hash -1499283929, now seen corresponding path program 1 times [2019-12-07 18:16:45,936 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:16:45,936 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1624342925] [2019-12-07 18:16:45,936 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:16:45,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:16:45,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:16:45,977 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1624342925] [2019-12-07 18:16:45,978 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:16:45,978 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:16:45,978 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [141912909] [2019-12-07 18:16:45,978 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:16:45,978 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:16:45,978 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:16:45,978 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:16:45,978 INFO L87 Difference]: Start difference. First operand 386652 states and 1780389 transitions. Second operand 4 states. [2019-12-07 18:16:52,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:16:52,466 INFO L93 Difference]: Finished difference Result 471268 states and 2152941 transitions. [2019-12-07 18:16:52,467 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:16:52,467 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 18:16:52,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:16:54,165 INFO L225 Difference]: With dead ends: 471268 [2019-12-07 18:16:54,166 INFO L226 Difference]: Without dead ends: 471268 [2019-12-07 18:16:54,166 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:17:05,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 471268 states. [2019-12-07 18:17:11,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 471268 to 404660. [2019-12-07 18:17:11,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 404660 states. [2019-12-07 18:17:13,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 404660 states to 404660 states and 1864125 transitions. [2019-12-07 18:17:13,592 INFO L78 Accepts]: Start accepts. Automaton has 404660 states and 1864125 transitions. Word has length 15 [2019-12-07 18:17:13,592 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:17:13,592 INFO L462 AbstractCegarLoop]: Abstraction has 404660 states and 1864125 transitions. [2019-12-07 18:17:13,592 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:17:13,593 INFO L276 IsEmpty]: Start isEmpty. Operand 404660 states and 1864125 transitions. [2019-12-07 18:17:13,624 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 18:17:13,624 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:17:13,624 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:17:13,625 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:17:13,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:17:13,625 INFO L82 PathProgramCache]: Analyzing trace with hash -420686203, now seen corresponding path program 1 times [2019-12-07 18:17:13,625 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:17:13,625 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1916028153] [2019-12-07 18:17:13,625 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:17:13,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:17:13,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:17:13,675 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1916028153] [2019-12-07 18:17:13,675 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:17:13,675 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:17:13,675 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [204330323] [2019-12-07 18:17:13,676 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:17:13,676 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:17:13,676 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:17:13,676 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:17:13,676 INFO L87 Difference]: Start difference. First operand 404660 states and 1864125 transitions. Second operand 5 states. [2019-12-07 18:17:21,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:17:21,789 INFO L93 Difference]: Finished difference Result 580216 states and 2621041 transitions. [2019-12-07 18:17:21,790 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:17:21,790 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2019-12-07 18:17:21,790 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:17:23,504 INFO L225 Difference]: With dead ends: 580216 [2019-12-07 18:17:23,504 INFO L226 Difference]: Without dead ends: 579936 [2019-12-07 18:17:23,505 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:17:35,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 579936 states. [2019-12-07 18:17:43,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 579936 to 440626. [2019-12-07 18:17:43,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 440626 states. [2019-12-07 18:17:45,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 440626 states to 440626 states and 2021890 transitions. [2019-12-07 18:17:45,403 INFO L78 Accepts]: Start accepts. Automaton has 440626 states and 2021890 transitions. Word has length 21 [2019-12-07 18:17:45,403 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:17:45,403 INFO L462 AbstractCegarLoop]: Abstraction has 440626 states and 2021890 transitions. [2019-12-07 18:17:45,403 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:17:45,403 INFO L276 IsEmpty]: Start isEmpty. Operand 440626 states and 2021890 transitions. [2019-12-07 18:17:45,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 18:17:45,425 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:17:45,425 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:17:45,425 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:17:45,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:17:45,426 INFO L82 PathProgramCache]: Analyzing trace with hash -1647564741, now seen corresponding path program 1 times [2019-12-07 18:17:45,426 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:17:45,426 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1149522289] [2019-12-07 18:17:45,426 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:17:45,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:17:45,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:17:45,474 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1149522289] [2019-12-07 18:17:45,474 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:17:45,474 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:17:45,474 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [669693142] [2019-12-07 18:17:45,474 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:17:45,474 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:17:45,475 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:17:45,475 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:17:45,475 INFO L87 Difference]: Start difference. First operand 440626 states and 2021890 transitions. Second operand 5 states. [2019-12-07 18:17:53,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:17:53,302 INFO L93 Difference]: Finished difference Result 642304 states and 2892569 transitions. [2019-12-07 18:17:53,303 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:17:53,303 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2019-12-07 18:17:53,303 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:17:55,757 INFO L225 Difference]: With dead ends: 642304 [2019-12-07 18:17:55,757 INFO L226 Difference]: Without dead ends: 642178 [2019-12-07 18:17:55,758 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:18:08,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 642178 states. [2019-12-07 18:18:16,896 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 642178 to 454242. [2019-12-07 18:18:16,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454242 states. [2019-12-07 18:18:24,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454242 states to 454242 states and 2081324 transitions. [2019-12-07 18:18:24,408 INFO L78 Accepts]: Start accepts. Automaton has 454242 states and 2081324 transitions. Word has length 21 [2019-12-07 18:18:24,408 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:18:24,409 INFO L462 AbstractCegarLoop]: Abstraction has 454242 states and 2081324 transitions. [2019-12-07 18:18:24,409 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:18:24,409 INFO L276 IsEmpty]: Start isEmpty. Operand 454242 states and 2081324 transitions. [2019-12-07 18:18:24,433 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 18:18:24,433 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:18:24,433 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:18:24,433 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:18:24,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:18:24,434 INFO L82 PathProgramCache]: Analyzing trace with hash -873927282, now seen corresponding path program 1 times [2019-12-07 18:18:24,434 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:18:24,434 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [614408644] [2019-12-07 18:18:24,434 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:18:24,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:18:24,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:18:24,471 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [614408644] [2019-12-07 18:18:24,471 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:18:24,471 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:18:24,472 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1729037608] [2019-12-07 18:18:24,472 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:18:24,472 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:18:24,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:18:24,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:18:24,472 INFO L87 Difference]: Start difference. First operand 454242 states and 2081324 transitions. Second operand 5 states. [2019-12-07 18:18:28,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:18:28,996 INFO L93 Difference]: Finished difference Result 661794 states and 2983766 transitions. [2019-12-07 18:18:28,997 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:18:28,997 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2019-12-07 18:18:28,997 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:18:30,923 INFO L225 Difference]: With dead ends: 661794 [2019-12-07 18:18:30,923 INFO L226 Difference]: Without dead ends: 661668 [2019-12-07 18:18:30,924 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:18:49,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 661668 states. [2019-12-07 18:18:57,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 661668 to 488294. [2019-12-07 18:18:57,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 488294 states. [2019-12-07 18:19:00,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 488294 states to 488294 states and 2234536 transitions. [2019-12-07 18:19:00,176 INFO L78 Accepts]: Start accepts. Automaton has 488294 states and 2234536 transitions. Word has length 21 [2019-12-07 18:19:00,176 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:00,176 INFO L462 AbstractCegarLoop]: Abstraction has 488294 states and 2234536 transitions. [2019-12-07 18:19:00,176 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:19:00,176 INFO L276 IsEmpty]: Start isEmpty. Operand 488294 states and 2234536 transitions. [2019-12-07 18:19:00,296 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 18:19:00,296 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:00,296 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:00,296 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:00,297 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:00,297 INFO L82 PathProgramCache]: Analyzing trace with hash 1993832610, now seen corresponding path program 1 times [2019-12-07 18:19:00,297 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:00,297 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [912662353] [2019-12-07 18:19:00,297 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:00,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:00,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:00,357 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [912662353] [2019-12-07 18:19:00,357 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:00,357 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:19:00,357 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1523512864] [2019-12-07 18:19:00,357 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:19:00,358 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:00,358 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:19:00,358 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:19:00,358 INFO L87 Difference]: Start difference. First operand 488294 states and 2234536 transitions. Second operand 4 states. [2019-12-07 18:19:02,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:02,475 INFO L93 Difference]: Finished difference Result 299943 states and 1224200 transitions. [2019-12-07 18:19:02,476 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:19:02,476 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 27 [2019-12-07 18:19:02,476 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:03,223 INFO L225 Difference]: With dead ends: 299943 [2019-12-07 18:19:03,224 INFO L226 Difference]: Without dead ends: 288895 [2019-12-07 18:19:03,224 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:09,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288895 states. [2019-12-07 18:19:17,780 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288895 to 288895. [2019-12-07 18:19:17,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 288895 states. [2019-12-07 18:19:18,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288895 states to 288895 states and 1182938 transitions. [2019-12-07 18:19:18,991 INFO L78 Accepts]: Start accepts. Automaton has 288895 states and 1182938 transitions. Word has length 27 [2019-12-07 18:19:18,991 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:18,991 INFO L462 AbstractCegarLoop]: Abstraction has 288895 states and 1182938 transitions. [2019-12-07 18:19:18,991 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:19:18,991 INFO L276 IsEmpty]: Start isEmpty. Operand 288895 states and 1182938 transitions. [2019-12-07 18:19:19,049 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 18:19:19,049 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:19,049 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:19,049 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:19,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:19,049 INFO L82 PathProgramCache]: Analyzing trace with hash -512001639, now seen corresponding path program 1 times [2019-12-07 18:19:19,050 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:19,050 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1686784247] [2019-12-07 18:19:19,050 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:19,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:19,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:19,094 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1686784247] [2019-12-07 18:19:19,094 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:19,094 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:19:19,094 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [524808901] [2019-12-07 18:19:19,094 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:19:19,094 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:19,094 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:19:19,095 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:19,095 INFO L87 Difference]: Start difference. First operand 288895 states and 1182938 transitions. Second operand 5 states. [2019-12-07 18:19:19,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:19,312 INFO L93 Difference]: Finished difference Result 60298 states and 200149 transitions. [2019-12-07 18:19:19,313 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:19:19,313 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2019-12-07 18:19:19,313 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:19,401 INFO L225 Difference]: With dead ends: 60298 [2019-12-07 18:19:19,401 INFO L226 Difference]: Without dead ends: 53490 [2019-12-07 18:19:19,402 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:19:19,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53490 states. [2019-12-07 18:19:20,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53490 to 53490. [2019-12-07 18:19:20,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53490 states. [2019-12-07 18:19:20,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53490 states to 53490 states and 175162 transitions. [2019-12-07 18:19:20,313 INFO L78 Accepts]: Start accepts. Automaton has 53490 states and 175162 transitions. Word has length 28 [2019-12-07 18:19:20,313 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:20,313 INFO L462 AbstractCegarLoop]: Abstraction has 53490 states and 175162 transitions. [2019-12-07 18:19:20,313 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:19:20,313 INFO L276 IsEmpty]: Start isEmpty. Operand 53490 states and 175162 transitions. [2019-12-07 18:19:20,333 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 18:19:20,333 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:20,333 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:20,333 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:20,333 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:20,333 INFO L82 PathProgramCache]: Analyzing trace with hash -1168161855, now seen corresponding path program 1 times [2019-12-07 18:19:20,333 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:20,334 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [65598065] [2019-12-07 18:19:20,334 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:20,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:20,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:20,385 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [65598065] [2019-12-07 18:19:20,385 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:20,385 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:19:20,385 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [55658816] [2019-12-07 18:19:20,385 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:19:20,386 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:20,386 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:19:20,386 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:19:20,386 INFO L87 Difference]: Start difference. First operand 53490 states and 175162 transitions. Second operand 6 states. [2019-12-07 18:19:21,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:21,481 INFO L93 Difference]: Finished difference Result 64832 states and 208939 transitions. [2019-12-07 18:19:21,482 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 18:19:21,482 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 34 [2019-12-07 18:19:21,482 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:21,575 INFO L225 Difference]: With dead ends: 64832 [2019-12-07 18:19:21,575 INFO L226 Difference]: Without dead ends: 64819 [2019-12-07 18:19:21,575 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:19:21,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64819 states. [2019-12-07 18:19:22,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64819 to 49190. [2019-12-07 18:19:22,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49190 states. [2019-12-07 18:19:22,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49190 states to 49190 states and 161444 transitions. [2019-12-07 18:19:22,516 INFO L78 Accepts]: Start accepts. Automaton has 49190 states and 161444 transitions. Word has length 34 [2019-12-07 18:19:22,516 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:22,516 INFO L462 AbstractCegarLoop]: Abstraction has 49190 states and 161444 transitions. [2019-12-07 18:19:22,516 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:19:22,516 INFO L276 IsEmpty]: Start isEmpty. Operand 49190 states and 161444 transitions. [2019-12-07 18:19:22,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-12-07 18:19:22,544 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:22,544 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:22,544 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:22,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:22,545 INFO L82 PathProgramCache]: Analyzing trace with hash 461831120, now seen corresponding path program 1 times [2019-12-07 18:19:22,545 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:22,545 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [82540002] [2019-12-07 18:19:22,545 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:22,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:22,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:22,601 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [82540002] [2019-12-07 18:19:22,601 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:22,601 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:19:22,601 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2024579060] [2019-12-07 18:19:22,602 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:19:22,602 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:22,602 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:19:22,602 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:19:22,602 INFO L87 Difference]: Start difference. First operand 49190 states and 161444 transitions. Second operand 6 states. [2019-12-07 18:19:22,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:22,681 INFO L93 Difference]: Finished difference Result 13912 states and 43638 transitions. [2019-12-07 18:19:22,681 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:19:22,681 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 42 [2019-12-07 18:19:22,681 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:22,696 INFO L225 Difference]: With dead ends: 13912 [2019-12-07 18:19:22,697 INFO L226 Difference]: Without dead ends: 12828 [2019-12-07 18:19:22,697 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:19:22,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12828 states. [2019-12-07 18:19:22,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12828 to 12604. [2019-12-07 18:19:22,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12604 states. [2019-12-07 18:19:22,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12604 states to 12604 states and 39716 transitions. [2019-12-07 18:19:22,873 INFO L78 Accepts]: Start accepts. Automaton has 12604 states and 39716 transitions. Word has length 42 [2019-12-07 18:19:22,873 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:22,873 INFO L462 AbstractCegarLoop]: Abstraction has 12604 states and 39716 transitions. [2019-12-07 18:19:22,873 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:19:22,873 INFO L276 IsEmpty]: Start isEmpty. Operand 12604 states and 39716 transitions. [2019-12-07 18:19:22,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-12-07 18:19:22,884 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:22,884 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:22,884 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:22,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:22,884 INFO L82 PathProgramCache]: Analyzing trace with hash -720663879, now seen corresponding path program 1 times [2019-12-07 18:19:22,884 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:22,884 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1766049476] [2019-12-07 18:19:22,884 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:22,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:22,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:22,965 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1766049476] [2019-12-07 18:19:22,965 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:22,965 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:19:22,965 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1693380680] [2019-12-07 18:19:22,966 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:19:22,966 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:22,966 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:19:22,966 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:19:22,966 INFO L87 Difference]: Start difference. First operand 12604 states and 39716 transitions. Second operand 7 states. [2019-12-07 18:19:23,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:23,073 INFO L93 Difference]: Finished difference Result 10109 states and 33952 transitions. [2019-12-07 18:19:23,073 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:19:23,073 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 54 [2019-12-07 18:19:23,073 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:23,091 INFO L225 Difference]: With dead ends: 10109 [2019-12-07 18:19:23,091 INFO L226 Difference]: Without dead ends: 10028 [2019-12-07 18:19:23,092 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:19:23,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10028 states. [2019-12-07 18:19:23,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10028 to 9300. [2019-12-07 18:19:23,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9300 states. [2019-12-07 18:19:23,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9300 states to 9300 states and 31459 transitions. [2019-12-07 18:19:23,262 INFO L78 Accepts]: Start accepts. Automaton has 9300 states and 31459 transitions. Word has length 54 [2019-12-07 18:19:23,262 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:23,262 INFO L462 AbstractCegarLoop]: Abstraction has 9300 states and 31459 transitions. [2019-12-07 18:19:23,262 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:19:23,262 INFO L276 IsEmpty]: Start isEmpty. Operand 9300 states and 31459 transitions. [2019-12-07 18:19:23,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:19:23,272 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:23,272 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:23,272 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:23,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:23,272 INFO L82 PathProgramCache]: Analyzing trace with hash -1512196867, now seen corresponding path program 1 times [2019-12-07 18:19:23,272 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:23,272 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1406163326] [2019-12-07 18:19:23,272 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:23,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:23,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:23,309 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1406163326] [2019-12-07 18:19:23,309 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:23,309 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:19:23,309 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1106233889] [2019-12-07 18:19:23,309 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:19:23,310 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:23,310 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:19:23,310 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:23,310 INFO L87 Difference]: Start difference. First operand 9300 states and 31459 transitions. Second operand 3 states. [2019-12-07 18:19:23,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:23,361 INFO L93 Difference]: Finished difference Result 9314 states and 31473 transitions. [2019-12-07 18:19:23,361 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:19:23,361 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 68 [2019-12-07 18:19:23,361 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:23,373 INFO L225 Difference]: With dead ends: 9314 [2019-12-07 18:19:23,373 INFO L226 Difference]: Without dead ends: 9314 [2019-12-07 18:19:23,373 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:23,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9314 states. [2019-12-07 18:19:23,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9314 to 9305. [2019-12-07 18:19:23,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9305 states. [2019-12-07 18:19:23,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9305 states to 9305 states and 31464 transitions. [2019-12-07 18:19:23,507 INFO L78 Accepts]: Start accepts. Automaton has 9305 states and 31464 transitions. Word has length 68 [2019-12-07 18:19:23,507 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:23,507 INFO L462 AbstractCegarLoop]: Abstraction has 9305 states and 31464 transitions. [2019-12-07 18:19:23,507 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:19:23,507 INFO L276 IsEmpty]: Start isEmpty. Operand 9305 states and 31464 transitions. [2019-12-07 18:19:23,518 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:19:23,518 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:23,518 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:23,518 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:23,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:23,518 INFO L82 PathProgramCache]: Analyzing trace with hash -160766453, now seen corresponding path program 1 times [2019-12-07 18:19:23,519 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:23,519 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1244112193] [2019-12-07 18:19:23,519 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:23,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:23,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:23,709 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1244112193] [2019-12-07 18:19:23,709 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:23,709 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:19:23,710 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [719788967] [2019-12-07 18:19:23,710 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:19:23,710 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:23,710 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:19:23,710 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:23,710 INFO L87 Difference]: Start difference. First operand 9305 states and 31464 transitions. Second operand 5 states. [2019-12-07 18:19:23,966 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:23,966 INFO L93 Difference]: Finished difference Result 14803 states and 49454 transitions. [2019-12-07 18:19:23,966 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:19:23,966 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 68 [2019-12-07 18:19:23,966 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:23,985 INFO L225 Difference]: With dead ends: 14803 [2019-12-07 18:19:23,985 INFO L226 Difference]: Without dead ends: 14803 [2019-12-07 18:19:23,986 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:19:24,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14803 states. [2019-12-07 18:19:24,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14803 to 11930. [2019-12-07 18:19:24,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11930 states. [2019-12-07 18:19:24,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11930 states to 11930 states and 40212 transitions. [2019-12-07 18:19:24,180 INFO L78 Accepts]: Start accepts. Automaton has 11930 states and 40212 transitions. Word has length 68 [2019-12-07 18:19:24,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:24,180 INFO L462 AbstractCegarLoop]: Abstraction has 11930 states and 40212 transitions. [2019-12-07 18:19:24,181 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:19:24,181 INFO L276 IsEmpty]: Start isEmpty. Operand 11930 states and 40212 transitions. [2019-12-07 18:19:24,192 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:19:24,193 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:24,193 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:24,193 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:24,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:24,193 INFO L82 PathProgramCache]: Analyzing trace with hash -1743593589, now seen corresponding path program 2 times [2019-12-07 18:19:24,193 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:24,193 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1104677439] [2019-12-07 18:19:24,193 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:24,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:24,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:24,251 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1104677439] [2019-12-07 18:19:24,251 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:24,251 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:19:24,251 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1168576406] [2019-12-07 18:19:24,252 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:19:24,252 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:24,252 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:19:24,252 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:24,252 INFO L87 Difference]: Start difference. First operand 11930 states and 40212 transitions. Second operand 5 states. [2019-12-07 18:19:24,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:24,498 INFO L93 Difference]: Finished difference Result 17345 states and 58185 transitions. [2019-12-07 18:19:24,498 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:19:24,498 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 68 [2019-12-07 18:19:24,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:24,527 INFO L225 Difference]: With dead ends: 17345 [2019-12-07 18:19:24,527 INFO L226 Difference]: Without dead ends: 17345 [2019-12-07 18:19:24,528 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:19:24,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17345 states. [2019-12-07 18:19:24,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17345 to 14598. [2019-12-07 18:19:24,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14598 states. [2019-12-07 18:19:24,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14598 states to 14598 states and 49376 transitions. [2019-12-07 18:19:24,767 INFO L78 Accepts]: Start accepts. Automaton has 14598 states and 49376 transitions. Word has length 68 [2019-12-07 18:19:24,767 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:24,767 INFO L462 AbstractCegarLoop]: Abstraction has 14598 states and 49376 transitions. [2019-12-07 18:19:24,767 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:19:24,767 INFO L276 IsEmpty]: Start isEmpty. Operand 14598 states and 49376 transitions. [2019-12-07 18:19:24,782 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:19:24,782 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:24,782 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:24,782 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:24,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:24,782 INFO L82 PathProgramCache]: Analyzing trace with hash 1372327229, now seen corresponding path program 3 times [2019-12-07 18:19:24,783 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:24,783 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [903165797] [2019-12-07 18:19:24,783 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:24,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:24,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:24,832 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [903165797] [2019-12-07 18:19:24,832 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:24,832 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:19:24,833 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [289241963] [2019-12-07 18:19:24,833 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:19:24,833 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:24,833 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:19:24,833 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:19:24,833 INFO L87 Difference]: Start difference. First operand 14598 states and 49376 transitions. Second operand 6 states. [2019-12-07 18:19:25,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:25,152 INFO L93 Difference]: Finished difference Result 22893 states and 77132 transitions. [2019-12-07 18:19:25,153 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:19:25,153 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 68 [2019-12-07 18:19:25,153 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:25,182 INFO L225 Difference]: With dead ends: 22893 [2019-12-07 18:19:25,183 INFO L226 Difference]: Without dead ends: 22893 [2019-12-07 18:19:25,183 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:19:25,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22893 states. [2019-12-07 18:19:25,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22893 to 16280. [2019-12-07 18:19:25,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16280 states. [2019-12-07 18:19:25,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16280 states to 16280 states and 55177 transitions. [2019-12-07 18:19:25,503 INFO L78 Accepts]: Start accepts. Automaton has 16280 states and 55177 transitions. Word has length 68 [2019-12-07 18:19:25,503 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:25,503 INFO L462 AbstractCegarLoop]: Abstraction has 16280 states and 55177 transitions. [2019-12-07 18:19:25,503 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:19:25,503 INFO L276 IsEmpty]: Start isEmpty. Operand 16280 states and 55177 transitions. [2019-12-07 18:19:25,520 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:19:25,520 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:25,520 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:25,520 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:25,520 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:25,520 INFO L82 PathProgramCache]: Analyzing trace with hash 1276689339, now seen corresponding path program 4 times [2019-12-07 18:19:25,520 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:25,521 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192431746] [2019-12-07 18:19:25,521 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:25,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:25,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:25,601 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192431746] [2019-12-07 18:19:25,601 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:25,601 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:19:25,601 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [654254142] [2019-12-07 18:19:25,601 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 18:19:25,601 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:25,602 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 18:19:25,602 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:19:25,602 INFO L87 Difference]: Start difference. First operand 16280 states and 55177 transitions. Second operand 8 states. [2019-12-07 18:19:26,053 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:26,054 INFO L93 Difference]: Finished difference Result 23748 states and 79791 transitions. [2019-12-07 18:19:26,054 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 18:19:26,054 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 68 [2019-12-07 18:19:26,054 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:26,086 INFO L225 Difference]: With dead ends: 23748 [2019-12-07 18:19:26,086 INFO L226 Difference]: Without dead ends: 23748 [2019-12-07 18:19:26,086 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 7 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=35, Invalid=97, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:19:26,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23748 states. [2019-12-07 18:19:26,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23748 to 16798. [2019-12-07 18:19:26,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16798 states. [2019-12-07 18:19:26,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16798 states to 16798 states and 56888 transitions. [2019-12-07 18:19:26,400 INFO L78 Accepts]: Start accepts. Automaton has 16798 states and 56888 transitions. Word has length 68 [2019-12-07 18:19:26,400 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:26,400 INFO L462 AbstractCegarLoop]: Abstraction has 16798 states and 56888 transitions. [2019-12-07 18:19:26,400 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 18:19:26,400 INFO L276 IsEmpty]: Start isEmpty. Operand 16798 states and 56888 transitions. [2019-12-07 18:19:26,418 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:19:26,418 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:26,418 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:26,418 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:26,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:26,418 INFO L82 PathProgramCache]: Analyzing trace with hash 459730185, now seen corresponding path program 5 times [2019-12-07 18:19:26,418 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:26,418 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [810497895] [2019-12-07 18:19:26,419 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:26,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:26,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:26,537 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [810497895] [2019-12-07 18:19:26,537 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:26,537 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:19:26,537 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [613021243] [2019-12-07 18:19:26,538 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:19:26,538 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:26,538 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:19:26,538 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:19:26,538 INFO L87 Difference]: Start difference. First operand 16798 states and 56888 transitions. Second operand 6 states. [2019-12-07 18:19:26,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:26,840 INFO L93 Difference]: Finished difference Result 22243 states and 74257 transitions. [2019-12-07 18:19:26,840 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:19:26,840 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 68 [2019-12-07 18:19:26,840 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:26,868 INFO L225 Difference]: With dead ends: 22243 [2019-12-07 18:19:26,868 INFO L226 Difference]: Without dead ends: 22243 [2019-12-07 18:19:26,868 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 6 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:19:26,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22243 states. [2019-12-07 18:19:27,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22243 to 17064. [2019-12-07 18:19:27,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17064 states. [2019-12-07 18:19:27,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17064 states to 17064 states and 57795 transitions. [2019-12-07 18:19:27,161 INFO L78 Accepts]: Start accepts. Automaton has 17064 states and 57795 transitions. Word has length 68 [2019-12-07 18:19:27,162 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:27,162 INFO L462 AbstractCegarLoop]: Abstraction has 17064 states and 57795 transitions. [2019-12-07 18:19:27,162 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:19:27,162 INFO L276 IsEmpty]: Start isEmpty. Operand 17064 states and 57795 transitions. [2019-12-07 18:19:27,181 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:19:27,181 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:27,181 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:27,181 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:27,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:27,182 INFO L82 PathProgramCache]: Analyzing trace with hash -1482095379, now seen corresponding path program 6 times [2019-12-07 18:19:27,182 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:27,182 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [155082110] [2019-12-07 18:19:27,182 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:27,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:27,255 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:27,255 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [155082110] [2019-12-07 18:19:27,255 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:27,255 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:19:27,255 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [850952360] [2019-12-07 18:19:27,255 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:19:27,256 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:27,256 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:19:27,256 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:19:27,256 INFO L87 Difference]: Start difference. First operand 17064 states and 57795 transitions. Second operand 6 states. [2019-12-07 18:19:27,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:27,698 INFO L93 Difference]: Finished difference Result 21972 states and 73512 transitions. [2019-12-07 18:19:27,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 18:19:27,698 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 68 [2019-12-07 18:19:27,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:27,735 INFO L225 Difference]: With dead ends: 21972 [2019-12-07 18:19:27,735 INFO L226 Difference]: Without dead ends: 21972 [2019-12-07 18:19:27,735 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 10 SyntacticMatches, 3 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=111, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:19:27,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21972 states. [2019-12-07 18:19:28,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21972 to 17806. [2019-12-07 18:19:28,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17806 states. [2019-12-07 18:19:28,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17806 states to 17806 states and 60202 transitions. [2019-12-07 18:19:28,037 INFO L78 Accepts]: Start accepts. Automaton has 17806 states and 60202 transitions. Word has length 68 [2019-12-07 18:19:28,037 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:28,037 INFO L462 AbstractCegarLoop]: Abstraction has 17806 states and 60202 transitions. [2019-12-07 18:19:28,037 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:19:28,037 INFO L276 IsEmpty]: Start isEmpty. Operand 17806 states and 60202 transitions. [2019-12-07 18:19:28,056 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:19:28,056 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:28,056 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:28,057 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:28,057 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:28,057 INFO L82 PathProgramCache]: Analyzing trace with hash 562041919, now seen corresponding path program 7 times [2019-12-07 18:19:28,057 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:28,057 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [516761546] [2019-12-07 18:19:28,057 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:28,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:28,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:28,128 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [516761546] [2019-12-07 18:19:28,128 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:28,128 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 18:19:28,129 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [300530339] [2019-12-07 18:19:28,129 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:19:28,129 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:28,129 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:19:28,129 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:19:28,129 INFO L87 Difference]: Start difference. First operand 17806 states and 60202 transitions. Second operand 7 states. [2019-12-07 18:19:28,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:28,642 INFO L93 Difference]: Finished difference Result 23270 states and 76592 transitions. [2019-12-07 18:19:28,642 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 18:19:28,643 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 68 [2019-12-07 18:19:28,643 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:28,671 INFO L225 Difference]: With dead ends: 23270 [2019-12-07 18:19:28,672 INFO L226 Difference]: Without dead ends: 23270 [2019-12-07 18:19:28,672 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 11 SyntacticMatches, 3 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=55, Invalid=155, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:19:28,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23270 states. [2019-12-07 18:19:28,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23270 to 16392. [2019-12-07 18:19:28,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16392 states. [2019-12-07 18:19:28,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16392 states to 16392 states and 54651 transitions. [2019-12-07 18:19:28,981 INFO L78 Accepts]: Start accepts. Automaton has 16392 states and 54651 transitions. Word has length 68 [2019-12-07 18:19:28,981 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:28,981 INFO L462 AbstractCegarLoop]: Abstraction has 16392 states and 54651 transitions. [2019-12-07 18:19:28,981 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:19:28,981 INFO L276 IsEmpty]: Start isEmpty. Operand 16392 states and 54651 transitions. [2019-12-07 18:19:28,997 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:19:28,997 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:28,997 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:28,997 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:28,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:28,997 INFO L82 PathProgramCache]: Analyzing trace with hash 587209037, now seen corresponding path program 8 times [2019-12-07 18:19:28,998 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:28,998 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [910073730] [2019-12-07 18:19:28,998 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:29,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:29,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:29,084 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [910073730] [2019-12-07 18:19:29,084 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:29,084 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:19:29,084 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2068374255] [2019-12-07 18:19:29,084 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 18:19:29,085 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:29,085 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 18:19:29,085 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:19:29,085 INFO L87 Difference]: Start difference. First operand 16392 states and 54651 transitions. Second operand 9 states. [2019-12-07 18:19:29,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:29,635 INFO L93 Difference]: Finished difference Result 21956 states and 72394 transitions. [2019-12-07 18:19:29,635 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 18:19:29,635 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 68 [2019-12-07 18:19:29,635 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:29,664 INFO L225 Difference]: With dead ends: 21956 [2019-12-07 18:19:29,664 INFO L226 Difference]: Without dead ends: 21956 [2019-12-07 18:19:29,664 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 13 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=84, Invalid=258, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:19:29,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21956 states. [2019-12-07 18:19:29,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21956 to 15608. [2019-12-07 18:19:29,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15608 states. [2019-12-07 18:19:29,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15608 states to 15608 states and 52061 transitions. [2019-12-07 18:19:29,958 INFO L78 Accepts]: Start accepts. Automaton has 15608 states and 52061 transitions. Word has length 68 [2019-12-07 18:19:29,959 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:29,959 INFO L462 AbstractCegarLoop]: Abstraction has 15608 states and 52061 transitions. [2019-12-07 18:19:29,959 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 18:19:29,959 INFO L276 IsEmpty]: Start isEmpty. Operand 15608 states and 52061 transitions. [2019-12-07 18:19:29,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:19:29,975 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:29,975 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:29,975 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:29,975 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:29,976 INFO L82 PathProgramCache]: Analyzing trace with hash 831592679, now seen corresponding path program 9 times [2019-12-07 18:19:29,976 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:29,976 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1702612800] [2019-12-07 18:19:29,976 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:29,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:30,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:30,042 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1702612800] [2019-12-07 18:19:30,043 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:30,043 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:19:30,043 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [903257021] [2019-12-07 18:19:30,043 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 18:19:30,043 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:30,043 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 18:19:30,043 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:19:30,043 INFO L87 Difference]: Start difference. First operand 15608 states and 52061 transitions. Second operand 8 states. [2019-12-07 18:19:30,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:30,566 INFO L93 Difference]: Finished difference Result 23446 states and 77112 transitions. [2019-12-07 18:19:30,566 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 18:19:30,566 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 68 [2019-12-07 18:19:30,566 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:30,596 INFO L225 Difference]: With dead ends: 23446 [2019-12-07 18:19:30,596 INFO L226 Difference]: Without dead ends: 23446 [2019-12-07 18:19:30,596 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 11 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=60, Invalid=180, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:19:30,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23446 states. [2019-12-07 18:19:30,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23446 to 16124. [2019-12-07 18:19:30,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16124 states. [2019-12-07 18:19:30,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16124 states to 16124 states and 53735 transitions. [2019-12-07 18:19:30,911 INFO L78 Accepts]: Start accepts. Automaton has 16124 states and 53735 transitions. Word has length 68 [2019-12-07 18:19:30,912 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:30,912 INFO L462 AbstractCegarLoop]: Abstraction has 16124 states and 53735 transitions. [2019-12-07 18:19:30,912 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 18:19:30,912 INFO L276 IsEmpty]: Start isEmpty. Operand 16124 states and 53735 transitions. [2019-12-07 18:19:30,929 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:19:30,929 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:30,929 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:30,929 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:30,929 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:30,929 INFO L82 PathProgramCache]: Analyzing trace with hash 131320479, now seen corresponding path program 10 times [2019-12-07 18:19:30,930 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:30,930 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [288508367] [2019-12-07 18:19:30,930 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:30,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:30,995 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:30,995 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [288508367] [2019-12-07 18:19:30,996 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:30,996 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 18:19:30,996 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1252832732] [2019-12-07 18:19:30,996 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:19:30,996 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:30,996 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:19:30,996 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:19:30,996 INFO L87 Difference]: Start difference. First operand 16124 states and 53735 transitions. Second operand 7 states. [2019-12-07 18:19:31,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:31,469 INFO L93 Difference]: Finished difference Result 21863 states and 72129 transitions. [2019-12-07 18:19:31,470 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 18:19:31,470 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 68 [2019-12-07 18:19:31,470 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:31,497 INFO L225 Difference]: With dead ends: 21863 [2019-12-07 18:19:31,497 INFO L226 Difference]: Without dead ends: 21863 [2019-12-07 18:19:31,497 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 13 SyntacticMatches, 2 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=72, Invalid=200, Unknown=0, NotChecked=0, Total=272 [2019-12-07 18:19:31,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21863 states. [2019-12-07 18:19:31,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21863 to 16464. [2019-12-07 18:19:31,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16464 states. [2019-12-07 18:19:31,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16464 states to 16464 states and 54847 transitions. [2019-12-07 18:19:31,788 INFO L78 Accepts]: Start accepts. Automaton has 16464 states and 54847 transitions. Word has length 68 [2019-12-07 18:19:31,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:31,788 INFO L462 AbstractCegarLoop]: Abstraction has 16464 states and 54847 transitions. [2019-12-07 18:19:31,788 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:19:31,788 INFO L276 IsEmpty]: Start isEmpty. Operand 16464 states and 54847 transitions. [2019-12-07 18:19:31,805 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:19:31,805 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:31,805 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:31,805 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:31,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:31,805 INFO L82 PathProgramCache]: Analyzing trace with hash -222773889, now seen corresponding path program 11 times [2019-12-07 18:19:31,805 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:31,806 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948270236] [2019-12-07 18:19:31,806 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:31,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:31,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:31,837 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1948270236] [2019-12-07 18:19:31,837 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:31,837 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:19:31,837 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1395420644] [2019-12-07 18:19:31,837 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:19:31,837 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:31,837 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:19:31,837 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:31,837 INFO L87 Difference]: Start difference. First operand 16464 states and 54847 transitions. Second operand 3 states. [2019-12-07 18:19:31,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:31,904 INFO L93 Difference]: Finished difference Result 16464 states and 54846 transitions. [2019-12-07 18:19:31,904 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:19:31,904 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 68 [2019-12-07 18:19:31,905 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:31,925 INFO L225 Difference]: With dead ends: 16464 [2019-12-07 18:19:31,926 INFO L226 Difference]: Without dead ends: 16464 [2019-12-07 18:19:31,926 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:31,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16464 states. [2019-12-07 18:19:32,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16464 to 11969. [2019-12-07 18:19:32,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11969 states. [2019-12-07 18:19:32,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11969 states to 11969 states and 40211 transitions. [2019-12-07 18:19:32,134 INFO L78 Accepts]: Start accepts. Automaton has 11969 states and 40211 transitions. Word has length 68 [2019-12-07 18:19:32,135 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:32,135 INFO L462 AbstractCegarLoop]: Abstraction has 11969 states and 40211 transitions. [2019-12-07 18:19:32,135 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:19:32,135 INFO L276 IsEmpty]: Start isEmpty. Operand 11969 states and 40211 transitions. [2019-12-07 18:19:32,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-12-07 18:19:32,147 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:32,147 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:32,147 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:32,148 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:32,148 INFO L82 PathProgramCache]: Analyzing trace with hash 557294139, now seen corresponding path program 1 times [2019-12-07 18:19:32,148 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:32,148 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2035105094] [2019-12-07 18:19:32,148 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:32,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:32,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:32,308 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2035105094] [2019-12-07 18:19:32,308 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:32,308 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 18:19:32,308 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1869048769] [2019-12-07 18:19:32,308 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 18:19:32,308 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:32,308 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 18:19:32,309 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:19:32,309 INFO L87 Difference]: Start difference. First operand 11969 states and 40211 transitions. Second operand 13 states. [2019-12-07 18:19:33,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:33,244 INFO L93 Difference]: Finished difference Result 33482 states and 103540 transitions. [2019-12-07 18:19:33,244 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-12-07 18:19:33,244 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 69 [2019-12-07 18:19:33,244 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:33,267 INFO L225 Difference]: With dead ends: 33482 [2019-12-07 18:19:33,268 INFO L226 Difference]: Without dead ends: 20158 [2019-12-07 18:19:33,268 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 124 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=215, Invalid=655, Unknown=0, NotChecked=0, Total=870 [2019-12-07 18:19:33,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20158 states. [2019-12-07 18:19:33,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20158 to 10771. [2019-12-07 18:19:33,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10771 states. [2019-12-07 18:19:33,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10771 states to 10771 states and 35630 transitions. [2019-12-07 18:19:33,487 INFO L78 Accepts]: Start accepts. Automaton has 10771 states and 35630 transitions. Word has length 69 [2019-12-07 18:19:33,487 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:33,487 INFO L462 AbstractCegarLoop]: Abstraction has 10771 states and 35630 transitions. [2019-12-07 18:19:33,487 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 18:19:33,487 INFO L276 IsEmpty]: Start isEmpty. Operand 10771 states and 35630 transitions. [2019-12-07 18:19:33,498 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-12-07 18:19:33,498 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:33,498 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:33,498 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:33,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:33,498 INFO L82 PathProgramCache]: Analyzing trace with hash 1993135547, now seen corresponding path program 2 times [2019-12-07 18:19:33,498 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:33,499 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1753229620] [2019-12-07 18:19:33,499 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:33,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:33,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:33,549 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1753229620] [2019-12-07 18:19:33,550 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:33,550 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:19:33,550 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [456808969] [2019-12-07 18:19:33,550 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:19:33,550 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:33,550 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:19:33,550 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:33,550 INFO L87 Difference]: Start difference. First operand 10771 states and 35630 transitions. Second operand 5 states. [2019-12-07 18:19:33,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:33,609 INFO L93 Difference]: Finished difference Result 15184 states and 48279 transitions. [2019-12-07 18:19:33,609 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:19:33,609 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 69 [2019-12-07 18:19:33,609 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:33,613 INFO L225 Difference]: With dead ends: 15184 [2019-12-07 18:19:33,613 INFO L226 Difference]: Without dead ends: 5252 [2019-12-07 18:19:33,614 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:19:33,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5252 states. [2019-12-07 18:19:33,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5252 to 5252. [2019-12-07 18:19:33,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5252 states. [2019-12-07 18:19:33,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5252 states to 5252 states and 15002 transitions. [2019-12-07 18:19:33,675 INFO L78 Accepts]: Start accepts. Automaton has 5252 states and 15002 transitions. Word has length 69 [2019-12-07 18:19:33,675 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:33,675 INFO L462 AbstractCegarLoop]: Abstraction has 5252 states and 15002 transitions. [2019-12-07 18:19:33,675 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:19:33,675 INFO L276 IsEmpty]: Start isEmpty. Operand 5252 states and 15002 transitions. [2019-12-07 18:19:33,678 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-12-07 18:19:33,678 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:33,678 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:33,678 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:33,678 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:33,679 INFO L82 PathProgramCache]: Analyzing trace with hash -745066921, now seen corresponding path program 3 times [2019-12-07 18:19:33,679 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:33,679 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1803291669] [2019-12-07 18:19:33,679 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:33,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:33,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:33,710 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1803291669] [2019-12-07 18:19:33,710 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:33,711 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:19:33,711 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [531131297] [2019-12-07 18:19:33,711 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:19:33,711 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:33,711 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:19:33,711 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:33,711 INFO L87 Difference]: Start difference. First operand 5252 states and 15002 transitions. Second operand 3 states. [2019-12-07 18:19:33,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:33,727 INFO L93 Difference]: Finished difference Result 5021 states and 14121 transitions. [2019-12-07 18:19:33,727 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:19:33,727 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 69 [2019-12-07 18:19:33,727 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:33,731 INFO L225 Difference]: With dead ends: 5021 [2019-12-07 18:19:33,731 INFO L226 Difference]: Without dead ends: 5021 [2019-12-07 18:19:33,731 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:33,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5021 states. [2019-12-07 18:19:33,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5021 to 4688. [2019-12-07 18:19:33,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4688 states. [2019-12-07 18:19:33,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4688 states to 4688 states and 13171 transitions. [2019-12-07 18:19:33,784 INFO L78 Accepts]: Start accepts. Automaton has 4688 states and 13171 transitions. Word has length 69 [2019-12-07 18:19:33,784 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:33,784 INFO L462 AbstractCegarLoop]: Abstraction has 4688 states and 13171 transitions. [2019-12-07 18:19:33,784 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:19:33,784 INFO L276 IsEmpty]: Start isEmpty. Operand 4688 states and 13171 transitions. [2019-12-07 18:19:33,787 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 18:19:33,787 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:33,787 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:33,787 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:33,787 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:33,787 INFO L82 PathProgramCache]: Analyzing trace with hash 337806488, now seen corresponding path program 1 times [2019-12-07 18:19:33,787 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:33,788 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1041243908] [2019-12-07 18:19:33,788 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:33,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:33,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:33,874 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1041243908] [2019-12-07 18:19:33,875 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:33,875 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:19:33,875 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [41446516] [2019-12-07 18:19:33,875 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 18:19:33,875 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:33,875 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 18:19:33,875 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:19:33,875 INFO L87 Difference]: Start difference. First operand 4688 states and 13171 transitions. Second operand 8 states. [2019-12-07 18:19:34,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:34,315 INFO L93 Difference]: Finished difference Result 7102 states and 20006 transitions. [2019-12-07 18:19:34,315 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 18:19:34,315 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 70 [2019-12-07 18:19:34,315 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:34,321 INFO L225 Difference]: With dead ends: 7102 [2019-12-07 18:19:34,321 INFO L226 Difference]: Without dead ends: 7102 [2019-12-07 18:19:34,321 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 2 SyntacticMatches, 4 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=53, Invalid=129, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:19:34,343 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7102 states. [2019-12-07 18:19:34,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7102 to 4802. [2019-12-07 18:19:34,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4802 states. [2019-12-07 18:19:34,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4802 states to 4802 states and 13520 transitions. [2019-12-07 18:19:34,388 INFO L78 Accepts]: Start accepts. Automaton has 4802 states and 13520 transitions. Word has length 70 [2019-12-07 18:19:34,388 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:34,388 INFO L462 AbstractCegarLoop]: Abstraction has 4802 states and 13520 transitions. [2019-12-07 18:19:34,388 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 18:19:34,388 INFO L276 IsEmpty]: Start isEmpty. Operand 4802 states and 13520 transitions. [2019-12-07 18:19:34,391 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 18:19:34,391 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:34,391 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:34,391 INFO L410 AbstractCegarLoop]: === Iteration 29 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:34,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:34,391 INFO L82 PathProgramCache]: Analyzing trace with hash 601391150, now seen corresponding path program 2 times [2019-12-07 18:19:34,391 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:34,391 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1263675134] [2019-12-07 18:19:34,391 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:34,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:34,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:34,465 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1263675134] [2019-12-07 18:19:34,465 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:34,465 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:19:34,465 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1306092088] [2019-12-07 18:19:34,465 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 18:19:34,465 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:34,465 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 18:19:34,466 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:19:34,466 INFO L87 Difference]: Start difference. First operand 4802 states and 13520 transitions. Second operand 8 states. [2019-12-07 18:19:34,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:34,916 INFO L93 Difference]: Finished difference Result 8099 states and 22542 transitions. [2019-12-07 18:19:34,916 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-12-07 18:19:34,916 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 70 [2019-12-07 18:19:34,916 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:34,922 INFO L225 Difference]: With dead ends: 8099 [2019-12-07 18:19:34,922 INFO L226 Difference]: Without dead ends: 8099 [2019-12-07 18:19:34,923 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=64, Invalid=176, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:19:34,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8099 states. [2019-12-07 18:19:34,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8099 to 4718. [2019-12-07 18:19:34,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4718 states. [2019-12-07 18:19:34,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4718 states to 4718 states and 13259 transitions. [2019-12-07 18:19:34,999 INFO L78 Accepts]: Start accepts. Automaton has 4718 states and 13259 transitions. Word has length 70 [2019-12-07 18:19:34,999 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:35,000 INFO L462 AbstractCegarLoop]: Abstraction has 4718 states and 13259 transitions. [2019-12-07 18:19:35,000 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 18:19:35,000 INFO L276 IsEmpty]: Start isEmpty. Operand 4718 states and 13259 transitions. [2019-12-07 18:19:35,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 18:19:35,003 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:35,003 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:35,003 INFO L410 AbstractCegarLoop]: === Iteration 30 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:35,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:35,003 INFO L82 PathProgramCache]: Analyzing trace with hash -244293942, now seen corresponding path program 3 times [2019-12-07 18:19:35,003 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:35,003 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [756558981] [2019-12-07 18:19:35,003 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:35,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:35,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:35,034 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [756558981] [2019-12-07 18:19:35,034 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:35,034 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:19:35,035 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1812269560] [2019-12-07 18:19:35,035 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:19:35,035 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:35,035 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:19:35,035 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:35,035 INFO L87 Difference]: Start difference. First operand 4718 states and 13259 transitions. Second operand 3 states. [2019-12-07 18:19:35,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:35,049 INFO L93 Difference]: Finished difference Result 4218 states and 11646 transitions. [2019-12-07 18:19:35,049 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:19:35,049 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2019-12-07 18:19:35,049 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:35,052 INFO L225 Difference]: With dead ends: 4218 [2019-12-07 18:19:35,052 INFO L226 Difference]: Without dead ends: 4218 [2019-12-07 18:19:35,052 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:35,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4218 states. [2019-12-07 18:19:35,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4218 to 4149. [2019-12-07 18:19:35,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4149 states. [2019-12-07 18:19:35,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4149 states to 4149 states and 11456 transitions. [2019-12-07 18:19:35,101 INFO L78 Accepts]: Start accepts. Automaton has 4149 states and 11456 transitions. Word has length 70 [2019-12-07 18:19:35,101 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:35,101 INFO L462 AbstractCegarLoop]: Abstraction has 4149 states and 11456 transitions. [2019-12-07 18:19:35,101 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:19:35,102 INFO L276 IsEmpty]: Start isEmpty. Operand 4149 states and 11456 transitions. [2019-12-07 18:19:35,104 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-12-07 18:19:35,104 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:35,104 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:35,104 INFO L410 AbstractCegarLoop]: === Iteration 31 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:35,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:35,104 INFO L82 PathProgramCache]: Analyzing trace with hash 8405892, now seen corresponding path program 1 times [2019-12-07 18:19:35,105 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:35,105 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1110774855] [2019-12-07 18:19:35,105 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:35,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:35,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:35,325 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1110774855] [2019-12-07 18:19:35,326 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:35,326 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 18:19:35,326 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1187557006] [2019-12-07 18:19:35,326 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 18:19:35,326 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:35,326 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 18:19:35,326 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=202, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:19:35,326 INFO L87 Difference]: Start difference. First operand 4149 states and 11456 transitions. Second operand 16 states. [2019-12-07 18:19:36,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:36,762 INFO L93 Difference]: Finished difference Result 8794 states and 24378 transitions. [2019-12-07 18:19:36,763 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-12-07 18:19:36,763 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 71 [2019-12-07 18:19:36,763 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:36,774 INFO L225 Difference]: With dead ends: 8794 [2019-12-07 18:19:36,775 INFO L226 Difference]: Without dead ends: 8240 [2019-12-07 18:19:36,776 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 276 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=265, Invalid=1141, Unknown=0, NotChecked=0, Total=1406 [2019-12-07 18:19:36,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8240 states. [2019-12-07 18:19:36,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8240 to 5371. [2019-12-07 18:19:36,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5371 states. [2019-12-07 18:19:36,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5371 states to 5371 states and 14796 transitions. [2019-12-07 18:19:36,863 INFO L78 Accepts]: Start accepts. Automaton has 5371 states and 14796 transitions. Word has length 71 [2019-12-07 18:19:36,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:36,863 INFO L462 AbstractCegarLoop]: Abstraction has 5371 states and 14796 transitions. [2019-12-07 18:19:36,863 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 18:19:36,863 INFO L276 IsEmpty]: Start isEmpty. Operand 5371 states and 14796 transitions. [2019-12-07 18:19:36,866 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-12-07 18:19:36,867 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:36,867 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:36,867 INFO L410 AbstractCegarLoop]: === Iteration 32 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:36,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:36,867 INFO L82 PathProgramCache]: Analyzing trace with hash 1910816578, now seen corresponding path program 2 times [2019-12-07 18:19:36,867 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:36,867 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [394901318] [2019-12-07 18:19:36,867 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:36,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:19:36,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:19:36,965 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:19:36,965 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 18:19:36,968 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [874] [874] ULTIMATE.startENTRY-->L838: Formula: (let ((.cse0 (store |v_#valid_74| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= 0 v_~y$r_buff0_thd3~0_200) (= 0 v_~__unbuffered_p3_EAX~0_35) (= v_~main$tmp_guard0~0_40 0) (= 0 v_~a~0_9) (= v_~y$w_buff1~0_279 0) (= 0 v_~y$r_buff1_thd2~0_191) (= v_~y$read_delayed~0_7 0) (< 0 |v_#StackHeapBarrier_21|) (= v_~y$r_buff0_thd0~0_427 0) (= 0 v_~y$r_buff0_thd4~0_117) (= v_~y$r_buff1_thd0~0_334 0) (= v_~y$r_buff1_thd1~0_106 0) (= 0 v_~y$r_buff1_thd4~0_188) (= 0 v_~__unbuffered_p3_EBX~0_34) (= v_~b~0_35 0) (= 0 v_~y$flush_delayed~0_35) (= 0 v_~__unbuffered_p2_EAX~0_131) (= 0 |v_ULTIMATE.start_main_~#t1081~0.offset_20|) (= |v_#length_29| (store |v_#length_30| |v_ULTIMATE.start_main_~#t1081~0.base_27| 4)) (= |v_#valid_72| (store .cse0 |v_ULTIMATE.start_main_~#t1081~0.base_27| 1)) (= v_~main$tmp_guard1~0_38 0) (= v_~y$r_buff0_thd1~0_47 0) (< |v_#StackHeapBarrier_21| |v_ULTIMATE.start_main_~#t1081~0.base_27|) (= v_~y$w_buff0_used~0_967 0) (= v_~y$mem_tmp~0_20 0) (= v_~x~0_90 0) (= v_~z~0_48 0) (= v_~weak$$choice2~0_128 0) (= |v_#NULL.offset_5| 0) (= 0 v_~y$r_buff1_thd3~0_168) (= |v_#memory_int_27| (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t1081~0.base_27| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t1081~0.base_27|) |v_ULTIMATE.start_main_~#t1081~0.offset_20| 0))) (= 0 v_~y$w_buff0~0_417) (= 0 v_~y$r_buff0_thd2~0_122) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1081~0.base_27|)) (= 0 v_~y$read_delayed_var~0.offset_6) (= 0 v_~weak$$choice0~0_13) (= v_~y~0_175 0) (= v_~__unbuffered_cnt~0_214 0) (= v_~y$w_buff1_used~0_549 0) (= 0 |v_#NULL.base_5|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_21|, #valid=|v_#valid_74|, #memory_int=|v_#memory_int_28|, #length=|v_#length_30|} OutVars{ULTIMATE.start_main_~#t1081~0.base=|v_ULTIMATE.start_main_~#t1081~0.base_27|, ULTIMATE.start_main_#t~nondet32=|v_ULTIMATE.start_main_#t~nondet32_20|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_44|, ULTIMATE.start_main_~#t1083~0.offset=|v_ULTIMATE.start_main_~#t1083~0.offset_16|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_32|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_35|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_16|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_28|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_87|, ULTIMATE.start_main_~#t1084~0.base=|v_ULTIMATE.start_main_~#t1084~0.base_20|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_54|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ~a~0=v_~a~0_9, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_70|, ~y$mem_tmp~0=v_~y$mem_tmp~0_20, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_168, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_47, ~y$flush_delayed~0=v_~y$flush_delayed~0_35, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_35, #length=|v_#length_29|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_131, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_8|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_46|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_19|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_41|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_32|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_36|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_21|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_38|, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_188, ~y$w_buff1~0=v_~y$w_buff1~0_279, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ULTIMATE.start_main_~#t1084~0.offset=|v_ULTIMATE.start_main_~#t1084~0.offset_16|, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_122, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_214, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_334, ~x~0=v_~x~0_90, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_20|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_967, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_34|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_47|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_38, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_266|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_34|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_41|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_53|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_106, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_36|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_63|, ULTIMATE.start_main_~#t1082~0.offset=|v_ULTIMATE.start_main_~#t1082~0.offset_16|, ~y$w_buff0~0=v_~y$w_buff0~0_417, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_200, ~y~0=v_~y~0_175, ULTIMATE.start_main_~#t1082~0.base=|v_ULTIMATE.start_main_~#t1082~0.base_20|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_8|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_9|, ULTIMATE.start_main_~#t1081~0.offset=|v_ULTIMATE.start_main_~#t1081~0.offset_20|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_45|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_39|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_40, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_34, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_31|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_52|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_191, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_117, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_37|, ~b~0=v_~b~0_35, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_427, #valid=|v_#valid_72|, ULTIMATE.start_main_~#t1083~0.base=|v_ULTIMATE.start_main_~#t1083~0.base_20|, #memory_int=|v_#memory_int_27|, ~z~0=v_~z~0_48, ~weak$$choice2~0=v_~weak$$choice2~0_128, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_549} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1081~0.base, ULTIMATE.start_main_#t~nondet32, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1083~0.offset, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_~#t1084~0.base, ULTIMATE.start_main_#t~ite50, ~y$read_delayed~0, ~a~0, ULTIMATE.start_main_#t~ite52, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ~__unbuffered_p3_EAX~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$r_buff1_thd4~0, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ULTIMATE.start_main_~#t1084~0.offset, ~y$r_buff0_thd2~0, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite51, ULTIMATE.start_main_~#t1082~0.offset, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_~#t1082~0.base, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_~#t1081~0.offset, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~__unbuffered_p3_EBX~0, ULTIMATE.start_main_#t~ite53, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ~y$r_buff0_thd4~0, ULTIMATE.start_main_#t~ite41, ~b~0, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, ULTIMATE.start_main_~#t1083~0.base, #memory_int, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 18:19:36,969 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [847] [847] L838-1-->L840: Formula: (and (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t1082~0.base_11| 4)) (= 0 |v_ULTIMATE.start_main_~#t1082~0.offset_11|) (= 0 (select |v_#valid_47| |v_ULTIMATE.start_main_~#t1082~0.base_11|)) (= (store |v_#valid_47| |v_ULTIMATE.start_main_~#t1082~0.base_11| 1) |v_#valid_46|) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t1082~0.base_11|) (not (= 0 |v_ULTIMATE.start_main_~#t1082~0.base_11|)) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1082~0.base_11| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1082~0.base_11|) |v_ULTIMATE.start_main_~#t1082~0.offset_11| 1)) |v_#memory_int_19|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_20|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_5|, ULTIMATE.start_main_~#t1082~0.offset=|v_ULTIMATE.start_main_~#t1082~0.offset_11|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_19|, #length=|v_#length_21|, ULTIMATE.start_main_~#t1082~0.base=|v_ULTIMATE.start_main_~#t1082~0.base_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t1082~0.offset, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1082~0.base] because there is no mapped edge [2019-12-07 18:19:36,969 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [842] [842] L840-1-->L842: Formula: (and (= 0 (select |v_#valid_43| |v_ULTIMATE.start_main_~#t1083~0.base_12|)) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1083~0.base_12| 4)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1083~0.base_12| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1083~0.base_12|) |v_ULTIMATE.start_main_~#t1083~0.offset_10| 2)) |v_#memory_int_15|) (not (= |v_ULTIMATE.start_main_~#t1083~0.base_12| 0)) (= |v_ULTIMATE.start_main_~#t1083~0.offset_10| 0) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1083~0.base_12|) (= (store |v_#valid_43| |v_ULTIMATE.start_main_~#t1083~0.base_12| 1) |v_#valid_42|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_43|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_4|, ULTIMATE.start_main_~#t1083~0.base=|v_ULTIMATE.start_main_~#t1083~0.base_12|, ULTIMATE.start_main_~#t1083~0.offset=|v_ULTIMATE.start_main_~#t1083~0.offset_10|, #valid=|v_#valid_42|, #memory_int=|v_#memory_int_15|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_~#t1083~0.base, ULTIMATE.start_main_~#t1083~0.offset, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 18:19:36,970 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [850] [850] L842-1-->L844: Formula: (and (= |v_ULTIMATE.start_main_~#t1084~0.offset_11| 0) (= (store |v_#valid_49| |v_ULTIMATE.start_main_~#t1084~0.base_13| 1) |v_#valid_48|) (< |v_#StackHeapBarrier_15| |v_ULTIMATE.start_main_~#t1084~0.base_13|) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1084~0.base_13| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1084~0.base_13|) |v_ULTIMATE.start_main_~#t1084~0.offset_11| 3)) |v_#memory_int_21|) (not (= 0 |v_ULTIMATE.start_main_~#t1084~0.base_13|)) (= 0 (select |v_#valid_49| |v_ULTIMATE.start_main_~#t1084~0.base_13|)) (= (store |v_#length_24| |v_ULTIMATE.start_main_~#t1084~0.base_13| 4) |v_#length_23|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_49|, #memory_int=|v_#memory_int_22|, #length=|v_#length_24|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_15|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_6|, ULTIMATE.start_main_~#t1084~0.offset=|v_ULTIMATE.start_main_~#t1084~0.offset_11|, #valid=|v_#valid_48|, #memory_int=|v_#memory_int_21|, #length=|v_#length_23|, ULTIMATE.start_main_~#t1084~0.base=|v_ULTIMATE.start_main_~#t1084~0.base_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_~#t1084~0.offset, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1084~0.base] because there is no mapped edge [2019-12-07 18:19:36,970 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L4-->L789: Formula: (and (= v_~y$r_buff0_thd2~0_35 v_~y$r_buff1_thd2~0_34) (not (= v_P2Thread1of1ForFork1___VERIFIER_assert_~expression_8 0)) (= v_~__unbuffered_p2_EAX~0_10 v_~z~0_8) (= v_~y$r_buff0_thd4~0_25 v_~y$r_buff1_thd4~0_15) (= v_~y$r_buff0_thd0~0_94 v_~y$r_buff1_thd0~0_61) (= v_~y$r_buff1_thd1~0_7 v_~y$r_buff0_thd1~0_7) (= v_~y$r_buff0_thd3~0_32 1) (= v_~y$r_buff0_thd3~0_33 v_~y$r_buff1_thd3~0_20)) InVars {~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_25, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_33, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_94, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_35, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_7, ~z~0=v_~z~0_8, P2Thread1of1ForFork1___VERIFIER_assert_~expression=v_P2Thread1of1ForFork1___VERIFIER_assert_~expression_8} OutVars{P2Thread1of1ForFork1___VERIFIER_assert_~expression=v_P2Thread1of1ForFork1___VERIFIER_assert_~expression_8, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_34, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_25, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_7, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_15, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_20, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_32, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_94, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_35, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_7, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_10, ~z~0=v_~z~0_8, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_61} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, ~y$r_buff1_thd1~0, ~y$r_buff1_thd4~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd3~0, ~__unbuffered_p2_EAX~0, ~y$r_buff1_thd0~0] because there is no mapped edge [2019-12-07 18:19:36,971 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [851] [851] P0ENTRY-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork3_#res.base_3|) (= |v_P0Thread1of1ForFork3_#in~arg.offset_20| v_P0Thread1of1ForFork3_~arg.offset_18) (= v_P0Thread1of1ForFork3_~arg.base_18 |v_P0Thread1of1ForFork3_#in~arg.base_20|) (= v_~b~0_24 1) (= |v_P0Thread1of1ForFork3_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_135 (+ v_~__unbuffered_cnt~0_136 1)) (= v_~x~0_64 1)) InVars {P0Thread1of1ForFork3_#in~arg.offset=|v_P0Thread1of1ForFork3_#in~arg.offset_20|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_136, P0Thread1of1ForFork3_#in~arg.base=|v_P0Thread1of1ForFork3_#in~arg.base_20|} OutVars{~b~0=v_~b~0_24, P0Thread1of1ForFork3_#in~arg.offset=|v_P0Thread1of1ForFork3_#in~arg.offset_20|, P0Thread1of1ForFork3_~arg.base=v_P0Thread1of1ForFork3_~arg.base_18, P0Thread1of1ForFork3_#res.base=|v_P0Thread1of1ForFork3_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_135, P0Thread1of1ForFork3_#res.offset=|v_P0Thread1of1ForFork3_#res.offset_3|, P0Thread1of1ForFork3_~arg.offset=v_P0Thread1of1ForFork3_~arg.offset_18, P0Thread1of1ForFork3_#in~arg.base=|v_P0Thread1of1ForFork3_#in~arg.base_20|, ~x~0=v_~x~0_64} AuxVars[] AssignedVars[~b~0, P0Thread1of1ForFork3_~arg.base, P0Thread1of1ForFork3_#res.base, ~__unbuffered_cnt~0, P0Thread1of1ForFork3_#res.offset, P0Thread1of1ForFork3_~arg.offset, ~x~0] because there is no mapped edge [2019-12-07 18:19:36,972 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [810] [810] L759-2-->L759-5: Formula: (let ((.cse1 (= |P1Thread1of1ForFork0_#t~ite3_Out1278500084| |P1Thread1of1ForFork0_#t~ite4_Out1278500084|)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1278500084 256))) (.cse0 (= (mod ~y$r_buff1_thd2~0_In1278500084 256) 0))) (or (and (not .cse0) (= |P1Thread1of1ForFork0_#t~ite3_Out1278500084| ~y$w_buff1~0_In1278500084) .cse1 (not .cse2)) (and (= |P1Thread1of1ForFork0_#t~ite3_Out1278500084| ~y~0_In1278500084) .cse1 (or .cse2 .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1278500084, ~y$w_buff1~0=~y$w_buff1~0_In1278500084, ~y~0=~y~0_In1278500084, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1278500084} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1278500084, ~y$w_buff1~0=~y$w_buff1~0_In1278500084, P1Thread1of1ForFork0_#t~ite3=|P1Thread1of1ForFork0_#t~ite3_Out1278500084|, ~y~0=~y~0_In1278500084, P1Thread1of1ForFork0_#t~ite4=|P1Thread1of1ForFork0_#t~ite4_Out1278500084|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1278500084} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite3, P1Thread1of1ForFork0_#t~ite4] because there is no mapped edge [2019-12-07 18:19:36,973 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [818] [818] L760-->L760-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In2137458220 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In2137458220 256)))) (or (and (not .cse0) (= |P1Thread1of1ForFork0_#t~ite5_Out2137458220| 0) (not .cse1)) (and (or .cse1 .cse0) (= |P1Thread1of1ForFork0_#t~ite5_Out2137458220| ~y$w_buff0_used~0_In2137458220)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In2137458220, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2137458220} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In2137458220, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2137458220, P1Thread1of1ForFork0_#t~ite5=|P1Thread1of1ForFork0_#t~ite5_Out2137458220|} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 18:19:36,973 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [811] [811] L815-2-->L815-4: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In729305017 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd4~0_In729305017 256)))) (or (and (= |P3Thread1of1ForFork2_#t~ite15_Out729305017| ~y~0_In729305017) (or .cse0 .cse1)) (and (not .cse1) (= |P3Thread1of1ForFork2_#t~ite15_Out729305017| ~y$w_buff1~0_In729305017) (not .cse0)))) InVars {~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In729305017, ~y$w_buff1~0=~y$w_buff1~0_In729305017, ~y~0=~y~0_In729305017, ~y$w_buff1_used~0=~y$w_buff1_used~0_In729305017} OutVars{~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In729305017, ~y$w_buff1~0=~y$w_buff1~0_In729305017, P3Thread1of1ForFork2_#t~ite15=|P3Thread1of1ForFork2_#t~ite15_Out729305017|, ~y~0=~y~0_In729305017, ~y$w_buff1_used~0=~y$w_buff1_used~0_In729305017} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 18:19:36,973 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [819] [819] L761-->L761-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd2~0_In1865640336 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1865640336 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In1865640336 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In1865640336 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P1Thread1of1ForFork0_#t~ite6_Out1865640336| ~y$w_buff1_used~0_In1865640336)) (and (= 0 |P1Thread1of1ForFork0_#t~ite6_Out1865640336|) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1865640336, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1865640336, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1865640336, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1865640336} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1865640336, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1865640336, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1865640336, P1Thread1of1ForFork0_#t~ite6=|P1Thread1of1ForFork0_#t~ite6_Out1865640336|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1865640336} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 18:19:36,974 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [820] [820] L762-->L762-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In1561350495 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In1561350495 256)))) (or (and (not .cse0) (= |P1Thread1of1ForFork0_#t~ite7_Out1561350495| 0) (not .cse1)) (and (= |P1Thread1of1ForFork0_#t~ite7_Out1561350495| ~y$r_buff0_thd2~0_In1561350495) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1561350495, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1561350495} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1561350495, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1561350495, P1Thread1of1ForFork0_#t~ite7=|P1Thread1of1ForFork0_#t~ite7_Out1561350495|} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-12-07 18:19:36,974 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L763-->L763-2: Formula: (let ((.cse3 (= (mod ~y$w_buff1_used~0_In273026256 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd2~0_In273026256 256))) (.cse1 (= (mod ~y$r_buff0_thd2~0_In273026256 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In273026256 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork0_#t~ite8_Out273026256| 0)) (and (= ~y$r_buff1_thd2~0_In273026256 |P1Thread1of1ForFork0_#t~ite8_Out273026256|) (or .cse3 .cse2) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In273026256, ~y$w_buff0_used~0=~y$w_buff0_used~0_In273026256, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In273026256, ~y$w_buff1_used~0=~y$w_buff1_used~0_In273026256} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In273026256, ~y$w_buff0_used~0=~y$w_buff0_used~0_In273026256, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In273026256, P1Thread1of1ForFork0_#t~ite8=|P1Thread1of1ForFork0_#t~ite8_Out273026256|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In273026256} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 18:19:36,974 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [839] [839] L763-2-->P1EXIT: Formula: (and (= v_~y$r_buff1_thd2~0_135 |v_P1Thread1of1ForFork0_#t~ite8_46|) (= v_~__unbuffered_cnt~0_111 (+ v_~__unbuffered_cnt~0_112 1)) (= 0 |v_P1Thread1of1ForFork0_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork0_#res.base_3|)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_112, P1Thread1of1ForFork0_#t~ite8=|v_P1Thread1of1ForFork0_#t~ite8_46|} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_135, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_111, P1Thread1of1ForFork0_#res.offset=|v_P1Thread1of1ForFork0_#res.offset_3|, P1Thread1of1ForFork0_#t~ite8=|v_P1Thread1of1ForFork0_#t~ite8_45|, P1Thread1of1ForFork0_#res.base=|v_P1Thread1of1ForFork0_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork0_#res.offset, P1Thread1of1ForFork0_#t~ite8, P1Thread1of1ForFork0_#res.base] because there is no mapped edge [2019-12-07 18:19:36,974 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [751] [751] L815-4-->L816: Formula: (= |v_P3Thread1of1ForFork2_#t~ite15_8| v_~y~0_44) InVars {P3Thread1of1ForFork2_#t~ite15=|v_P3Thread1of1ForFork2_#t~ite15_8|} OutVars{P3Thread1of1ForFork2_#t~ite15=|v_P3Thread1of1ForFork2_#t~ite15_7|, P3Thread1of1ForFork2_#t~ite16=|v_P3Thread1of1ForFork2_#t~ite16_11|, ~y~0=v_~y~0_44} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite15, P3Thread1of1ForFork2_#t~ite16, ~y~0] because there is no mapped edge [2019-12-07 18:19:36,975 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L790-->L790-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd3~0_In-1151992128 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1151992128 256)))) (or (and (= 0 |P2Thread1of1ForFork1_#t~ite11_Out-1151992128|) (not .cse0) (not .cse1)) (and (= |P2Thread1of1ForFork1_#t~ite11_Out-1151992128| ~y$w_buff0_used~0_In-1151992128) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1151992128, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1151992128} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1151992128, P2Thread1of1ForFork1_#t~ite11=|P2Thread1of1ForFork1_#t~ite11_Out-1151992128|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1151992128} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 18:19:36,975 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L791-->L791-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In863110034 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In863110034 256))) (.cse1 (= (mod ~y$w_buff1_used~0_In863110034 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd3~0_In863110034 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork1_#t~ite12_Out863110034| ~y$w_buff1_used~0_In863110034)) (and (= 0 |P2Thread1of1ForFork1_#t~ite12_Out863110034|) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In863110034, ~y$w_buff0_used~0=~y$w_buff0_used~0_In863110034, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In863110034, ~y$w_buff1_used~0=~y$w_buff1_used~0_In863110034} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In863110034, ~y$w_buff0_used~0=~y$w_buff0_used~0_In863110034, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In863110034, P2Thread1of1ForFork1_#t~ite12=|P2Thread1of1ForFork1_#t~ite12_Out863110034|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In863110034} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 18:19:36,975 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [812] [812] L816-->L816-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd4~0_In1191164529 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In1191164529 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In1191164529 |P3Thread1of1ForFork2_#t~ite17_Out1191164529|)) (and (not .cse0) (= |P3Thread1of1ForFork2_#t~ite17_Out1191164529| 0) (not .cse1)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1191164529, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1191164529} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1191164529, P3Thread1of1ForFork2_#t~ite17=|P3Thread1of1ForFork2_#t~ite17_Out1191164529|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1191164529} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 18:19:36,976 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [813] [813] L792-->L793: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-1534088874 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd3~0_In-1534088874 256) 0)) (.cse1 (= ~y$r_buff0_thd3~0_In-1534088874 ~y$r_buff0_thd3~0_Out-1534088874))) (or (and .cse0 .cse1) (and (not .cse2) (= ~y$r_buff0_thd3~0_Out-1534088874 0) (not .cse0)) (and .cse2 .cse1))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1534088874, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1534088874} OutVars{P2Thread1of1ForFork1_#t~ite13=|P2Thread1of1ForFork1_#t~ite13_Out-1534088874|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1534088874, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-1534088874} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite13, ~y$r_buff0_thd3~0] because there is no mapped edge [2019-12-07 18:19:36,976 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L793-->L793-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd3~0_In2039985828 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In2039985828 256) 0)) (.cse2 (= (mod ~y$w_buff0_used~0_In2039985828 256) 0)) (.cse3 (= 0 (mod ~y$r_buff0_thd3~0_In2039985828 256)))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork1_#t~ite14_Out2039985828| ~y$r_buff1_thd3~0_In2039985828) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork1_#t~ite14_Out2039985828|)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In2039985828, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2039985828, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In2039985828, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2039985828} OutVars{P2Thread1of1ForFork1_#t~ite14=|P2Thread1of1ForFork1_#t~ite14_Out2039985828|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In2039985828, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2039985828, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In2039985828, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2039985828} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 18:19:36,976 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [848] [848] L793-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork1_#res.offset_3|) (= |v_P2Thread1of1ForFork1_#t~ite14_44| v_~y$r_buff1_thd3~0_136) (= 0 |v_P2Thread1of1ForFork1_#res.base_3|) (= v_~__unbuffered_cnt~0_133 (+ v_~__unbuffered_cnt~0_134 1))) InVars {P2Thread1of1ForFork1_#t~ite14=|v_P2Thread1of1ForFork1_#t~ite14_44|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_134} OutVars{P2Thread1of1ForFork1_#t~ite14=|v_P2Thread1of1ForFork1_#t~ite14_43|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_136, P2Thread1of1ForFork1_#res.base=|v_P2Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_133, P2Thread1of1ForFork1_#res.offset=|v_P2Thread1of1ForFork1_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork1_#res.offset] because there is no mapped edge [2019-12-07 18:19:36,976 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [814] [814] L817-->L817-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In-605650022 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd4~0_In-605650022 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd4~0_In-605650022 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In-605650022 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P3Thread1of1ForFork2_#t~ite18_Out-605650022|)) (and (or .cse3 .cse2) (= ~y$w_buff1_used~0_In-605650022 |P3Thread1of1ForFork2_#t~ite18_Out-605650022|) (or .cse1 .cse0)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-605650022, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-605650022, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-605650022, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-605650022} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-605650022, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-605650022, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-605650022, P3Thread1of1ForFork2_#t~ite18=|P3Thread1of1ForFork2_#t~ite18_Out-605650022|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-605650022} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 18:19:36,976 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [815] [815] L818-->L818-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In433204238 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd4~0_In433204238 256)))) (or (and (= |P3Thread1of1ForFork2_#t~ite19_Out433204238| ~y$r_buff0_thd4~0_In433204238) (or .cse0 .cse1)) (and (not .cse1) (= |P3Thread1of1ForFork2_#t~ite19_Out433204238| 0) (not .cse0)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In433204238, ~y$w_buff0_used~0=~y$w_buff0_used~0_In433204238} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In433204238, P3Thread1of1ForFork2_#t~ite19=|P3Thread1of1ForFork2_#t~ite19_Out433204238|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In433204238} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 18:19:36,977 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [816] [816] L819-->L819-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In640587695 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd4~0_In640587695 256) 0)) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In640587695 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd4~0_In640587695 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P3Thread1of1ForFork2_#t~ite20_Out640587695|)) (and (or .cse3 .cse2) (or .cse0 .cse1) (= ~y$r_buff1_thd4~0_In640587695 |P3Thread1of1ForFork2_#t~ite20_Out640587695|)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In640587695, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In640587695, ~y$w_buff0_used~0=~y$w_buff0_used~0_In640587695, ~y$w_buff1_used~0=~y$w_buff1_used~0_In640587695} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In640587695, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In640587695, ~y$w_buff0_used~0=~y$w_buff0_used~0_In640587695, P3Thread1of1ForFork2_#t~ite20=|P3Thread1of1ForFork2_#t~ite20_Out640587695|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In640587695} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 18:19:36,977 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [836] [836] L819-2-->P3EXIT: Formula: (and (= |v_P3Thread1of1ForFork2_#t~ite20_54| v_~y$r_buff1_thd4~0_130) (= (+ v_~__unbuffered_cnt~0_100 1) v_~__unbuffered_cnt~0_99) (= 0 |v_P3Thread1of1ForFork2_#res.base_3|) (= 0 |v_P3Thread1of1ForFork2_#res.offset_3|)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_100, P3Thread1of1ForFork2_#t~ite20=|v_P3Thread1of1ForFork2_#t~ite20_54|} OutVars{~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_130, P3Thread1of1ForFork2_#res.base=|v_P3Thread1of1ForFork2_#res.base_3|, P3Thread1of1ForFork2_#res.offset=|v_P3Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_99, P3Thread1of1ForFork2_#t~ite20=|v_P3Thread1of1ForFork2_#t~ite20_53|} AuxVars[] AssignedVars[~y$r_buff1_thd4~0, P3Thread1of1ForFork2_#res.base, P3Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0, P3Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 18:19:36,977 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [732] [732] L848-->L850-2: Formula: (and (not (= (mod v_~main$tmp_guard0~0_4 256) 0)) (or (= 0 (mod v_~y$r_buff0_thd0~0_51 256)) (= (mod v_~y$w_buff0_used~0_107 256) 0))) InVars {~y$w_buff0_used~0=v_~y$w_buff0_used~0_107, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_51, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_4} OutVars{~y$w_buff0_used~0=v_~y$w_buff0_used~0_107, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_51, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_4} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 18:19:36,977 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [817] [817] L850-2-->L850-5: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In1807420044 256))) (.cse0 (= (mod ~y$r_buff1_thd0~0_In1807420044 256) 0)) (.cse2 (= |ULTIMATE.start_main_#t~ite25_Out1807420044| |ULTIMATE.start_main_#t~ite26_Out1807420044|))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite25_Out1807420044| ~y~0_In1807420044) .cse2) (and (= |ULTIMATE.start_main_#t~ite25_Out1807420044| ~y$w_buff1~0_In1807420044) (not .cse1) (not .cse0) .cse2))) InVars {~y$w_buff1~0=~y$w_buff1~0_In1807420044, ~y~0=~y~0_In1807420044, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1807420044, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1807420044} OutVars{~y$w_buff1~0=~y$w_buff1~0_In1807420044, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out1807420044|, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out1807420044|, ~y~0=~y~0_In1807420044, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1807420044, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1807420044} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 18:19:36,978 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L851-->L851-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In640075485 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In640075485 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite27_Out640075485| 0) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite27_Out640075485| ~y$w_buff0_used~0_In640075485) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In640075485, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In640075485} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In640075485, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In640075485, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out640075485|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 18:19:36,978 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L852-->L852-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In661125972 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In661125972 256))) (.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In661125972 256))) (.cse3 (= (mod ~y$w_buff1_used~0_In661125972 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite28_Out661125972| 0)) (and (or .cse1 .cse0) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite28_Out661125972| ~y$w_buff1_used~0_In661125972)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In661125972, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In661125972, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In661125972, ~y$w_buff1_used~0=~y$w_buff1_used~0_In661125972} OutVars{ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out661125972|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In661125972, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In661125972, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In661125972, ~y$w_buff1_used~0=~y$w_buff1_used~0_In661125972} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 18:19:36,978 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [797] [797] L853-->L853-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-1569878414 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1569878414 256)))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite29_Out-1569878414|)) (and (or .cse0 .cse1) (= ~y$r_buff0_thd0~0_In-1569878414 |ULTIMATE.start_main_#t~ite29_Out-1569878414|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1569878414, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1569878414} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1569878414, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-1569878414|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1569878414} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 18:19:36,979 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [807] [807] L854-->L854-2: Formula: (let ((.cse3 (= (mod ~y$w_buff1_used~0_In598351424 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In598351424 256))) (.cse0 (= (mod ~y$r_buff0_thd0~0_In598351424 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In598351424 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite30_Out598351424| ~y$r_buff1_thd0~0_In598351424) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= |ULTIMATE.start_main_#t~ite30_Out598351424| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In598351424, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In598351424, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In598351424, ~y$w_buff1_used~0=~y$w_buff1_used~0_In598351424} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out598351424|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In598351424, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In598351424, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In598351424, ~y$w_buff1_used~0=~y$w_buff1_used~0_In598351424} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30] because there is no mapped edge [2019-12-07 18:19:36,980 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [855] [855] L863-->L863-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-730923790 256)))) (or (and (= |ULTIMATE.start_main_#t~ite39_In-730923790| |ULTIMATE.start_main_#t~ite39_Out-730923790|) (not .cse0) (= |ULTIMATE.start_main_#t~ite40_Out-730923790| ~y$w_buff1~0_In-730923790)) (and (= |ULTIMATE.start_main_#t~ite40_Out-730923790| |ULTIMATE.start_main_#t~ite39_Out-730923790|) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-730923790 256) 0))) (or (and (= (mod ~y$r_buff1_thd0~0_In-730923790 256) 0) .cse1) (= 0 (mod ~y$w_buff0_used~0_In-730923790 256)) (and (= 0 (mod ~y$w_buff1_used~0_In-730923790 256)) .cse1))) (= ~y$w_buff1~0_In-730923790 |ULTIMATE.start_main_#t~ite39_Out-730923790|) .cse0))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-730923790, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-730923790, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_In-730923790|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-730923790, ~weak$$choice2~0=~weak$$choice2~0_In-730923790, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-730923790, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-730923790} OutVars{ULTIMATE.start_main_#t~ite40=|ULTIMATE.start_main_#t~ite40_Out-730923790|, ~y$w_buff1~0=~y$w_buff1~0_In-730923790, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-730923790, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out-730923790|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-730923790, ~weak$$choice2~0=~weak$$choice2~0_In-730923790, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-730923790, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-730923790} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 18:19:36,982 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [726] [726] L866-->L867: Formula: (and (= v_~y$r_buff0_thd0~0_49 v_~y$r_buff0_thd0~0_48) (not (= 0 (mod v_~weak$$choice2~0_17 256)))) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_49, ~weak$$choice2~0=v_~weak$$choice2~0_17} OutVars{~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_48, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_6|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_6|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_6|, ~weak$$choice2~0=v_~weak$$choice2~0_17} AuxVars[] AssignedVars[~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 18:19:36,982 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [854] [854] L867-->L867-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-420210138 256) 0))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite51_In-420210138| |ULTIMATE.start_main_#t~ite51_Out-420210138|) (= |ULTIMATE.start_main_#t~ite52_Out-420210138| ~y$r_buff1_thd0~0_In-420210138)) (and (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-420210138 256) 0))) (or (= 0 (mod ~y$w_buff0_used~0_In-420210138 256)) (and (= 0 (mod ~y$w_buff1_used~0_In-420210138 256)) .cse1) (and .cse1 (= (mod ~y$r_buff1_thd0~0_In-420210138 256) 0)))) (= ~y$r_buff1_thd0~0_In-420210138 |ULTIMATE.start_main_#t~ite51_Out-420210138|) .cse0 (= |ULTIMATE.start_main_#t~ite52_Out-420210138| |ULTIMATE.start_main_#t~ite51_Out-420210138|)))) InVars {ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_In-420210138|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-420210138, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-420210138, ~weak$$choice2~0=~weak$$choice2~0_In-420210138, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-420210138, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-420210138} OutVars{ULTIMATE.start_main_#t~ite52=|ULTIMATE.start_main_#t~ite52_Out-420210138|, ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_Out-420210138|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-420210138, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-420210138, ~weak$$choice2~0=~weak$$choice2~0_In-420210138, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-420210138, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-420210138} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start_main_#t~ite51] because there is no mapped edge [2019-12-07 18:19:36,982 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [834] [834] L869-->L872-1: Formula: (and (= (mod v_~main$tmp_guard1~0_19 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (= v_~y~0_96 v_~y$mem_tmp~0_13) (= 0 v_~y$flush_delayed~0_22) (not (= (mod v_~y$flush_delayed~0_23 256) 0))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_13, ~y$flush_delayed~0=v_~y$flush_delayed~0_23, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_19} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_13, ~y$flush_delayed~0=v_~y$flush_delayed~0_22, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_19, ~y~0=v_~y~0_96, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_17|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[~y$flush_delayed~0, ~y~0, ULTIMATE.start_main_#t~ite53, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:19:36,982 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L872-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_12 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_12 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_12, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:19:37,042 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 06:19:37 BasicIcfg [2019-12-07 18:19:37,042 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 18:19:37,042 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:19:37,042 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:19:37,042 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:19:37,042 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:14:49" (3/4) ... [2019-12-07 18:19:37,044 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 18:19:37,044 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [874] [874] ULTIMATE.startENTRY-->L838: Formula: (let ((.cse0 (store |v_#valid_74| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= 0 v_~y$r_buff0_thd3~0_200) (= 0 v_~__unbuffered_p3_EAX~0_35) (= v_~main$tmp_guard0~0_40 0) (= 0 v_~a~0_9) (= v_~y$w_buff1~0_279 0) (= 0 v_~y$r_buff1_thd2~0_191) (= v_~y$read_delayed~0_7 0) (< 0 |v_#StackHeapBarrier_21|) (= v_~y$r_buff0_thd0~0_427 0) (= 0 v_~y$r_buff0_thd4~0_117) (= v_~y$r_buff1_thd0~0_334 0) (= v_~y$r_buff1_thd1~0_106 0) (= 0 v_~y$r_buff1_thd4~0_188) (= 0 v_~__unbuffered_p3_EBX~0_34) (= v_~b~0_35 0) (= 0 v_~y$flush_delayed~0_35) (= 0 v_~__unbuffered_p2_EAX~0_131) (= 0 |v_ULTIMATE.start_main_~#t1081~0.offset_20|) (= |v_#length_29| (store |v_#length_30| |v_ULTIMATE.start_main_~#t1081~0.base_27| 4)) (= |v_#valid_72| (store .cse0 |v_ULTIMATE.start_main_~#t1081~0.base_27| 1)) (= v_~main$tmp_guard1~0_38 0) (= v_~y$r_buff0_thd1~0_47 0) (< |v_#StackHeapBarrier_21| |v_ULTIMATE.start_main_~#t1081~0.base_27|) (= v_~y$w_buff0_used~0_967 0) (= v_~y$mem_tmp~0_20 0) (= v_~x~0_90 0) (= v_~z~0_48 0) (= v_~weak$$choice2~0_128 0) (= |v_#NULL.offset_5| 0) (= 0 v_~y$r_buff1_thd3~0_168) (= |v_#memory_int_27| (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t1081~0.base_27| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t1081~0.base_27|) |v_ULTIMATE.start_main_~#t1081~0.offset_20| 0))) (= 0 v_~y$w_buff0~0_417) (= 0 v_~y$r_buff0_thd2~0_122) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1081~0.base_27|)) (= 0 v_~y$read_delayed_var~0.offset_6) (= 0 v_~weak$$choice0~0_13) (= v_~y~0_175 0) (= v_~__unbuffered_cnt~0_214 0) (= v_~y$w_buff1_used~0_549 0) (= 0 |v_#NULL.base_5|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_21|, #valid=|v_#valid_74|, #memory_int=|v_#memory_int_28|, #length=|v_#length_30|} OutVars{ULTIMATE.start_main_~#t1081~0.base=|v_ULTIMATE.start_main_~#t1081~0.base_27|, ULTIMATE.start_main_#t~nondet32=|v_ULTIMATE.start_main_#t~nondet32_20|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_44|, ULTIMATE.start_main_~#t1083~0.offset=|v_ULTIMATE.start_main_~#t1083~0.offset_16|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_32|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_35|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_16|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_28|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_87|, ULTIMATE.start_main_~#t1084~0.base=|v_ULTIMATE.start_main_~#t1084~0.base_20|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_54|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ~a~0=v_~a~0_9, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_70|, ~y$mem_tmp~0=v_~y$mem_tmp~0_20, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_168, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_47, ~y$flush_delayed~0=v_~y$flush_delayed~0_35, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_35, #length=|v_#length_29|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_131, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_8|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_46|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_19|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_41|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_32|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_36|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_21|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_38|, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_188, ~y$w_buff1~0=v_~y$w_buff1~0_279, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ULTIMATE.start_main_~#t1084~0.offset=|v_ULTIMATE.start_main_~#t1084~0.offset_16|, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_122, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_214, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_334, ~x~0=v_~x~0_90, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_20|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_967, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_34|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_47|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_38, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_266|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_34|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_41|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_53|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_106, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_36|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_63|, ULTIMATE.start_main_~#t1082~0.offset=|v_ULTIMATE.start_main_~#t1082~0.offset_16|, ~y$w_buff0~0=v_~y$w_buff0~0_417, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_200, ~y~0=v_~y~0_175, ULTIMATE.start_main_~#t1082~0.base=|v_ULTIMATE.start_main_~#t1082~0.base_20|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_8|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_9|, ULTIMATE.start_main_~#t1081~0.offset=|v_ULTIMATE.start_main_~#t1081~0.offset_20|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_45|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_39|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_40, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_34, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_31|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_52|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_191, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_117, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_37|, ~b~0=v_~b~0_35, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_427, #valid=|v_#valid_72|, ULTIMATE.start_main_~#t1083~0.base=|v_ULTIMATE.start_main_~#t1083~0.base_20|, #memory_int=|v_#memory_int_27|, ~z~0=v_~z~0_48, ~weak$$choice2~0=v_~weak$$choice2~0_128, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_549} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1081~0.base, ULTIMATE.start_main_#t~nondet32, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1083~0.offset, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_~#t1084~0.base, ULTIMATE.start_main_#t~ite50, ~y$read_delayed~0, ~a~0, ULTIMATE.start_main_#t~ite52, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ~__unbuffered_p3_EAX~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$r_buff1_thd4~0, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ULTIMATE.start_main_~#t1084~0.offset, ~y$r_buff0_thd2~0, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite51, ULTIMATE.start_main_~#t1082~0.offset, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_~#t1082~0.base, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_~#t1081~0.offset, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~__unbuffered_p3_EBX~0, ULTIMATE.start_main_#t~ite53, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ~y$r_buff0_thd4~0, ULTIMATE.start_main_#t~ite41, ~b~0, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, ULTIMATE.start_main_~#t1083~0.base, #memory_int, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 18:19:37,045 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [847] [847] L838-1-->L840: Formula: (and (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t1082~0.base_11| 4)) (= 0 |v_ULTIMATE.start_main_~#t1082~0.offset_11|) (= 0 (select |v_#valid_47| |v_ULTIMATE.start_main_~#t1082~0.base_11|)) (= (store |v_#valid_47| |v_ULTIMATE.start_main_~#t1082~0.base_11| 1) |v_#valid_46|) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t1082~0.base_11|) (not (= 0 |v_ULTIMATE.start_main_~#t1082~0.base_11|)) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1082~0.base_11| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1082~0.base_11|) |v_ULTIMATE.start_main_~#t1082~0.offset_11| 1)) |v_#memory_int_19|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_20|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_5|, ULTIMATE.start_main_~#t1082~0.offset=|v_ULTIMATE.start_main_~#t1082~0.offset_11|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_19|, #length=|v_#length_21|, ULTIMATE.start_main_~#t1082~0.base=|v_ULTIMATE.start_main_~#t1082~0.base_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t1082~0.offset, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1082~0.base] because there is no mapped edge [2019-12-07 18:19:37,045 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [842] [842] L840-1-->L842: Formula: (and (= 0 (select |v_#valid_43| |v_ULTIMATE.start_main_~#t1083~0.base_12|)) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1083~0.base_12| 4)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1083~0.base_12| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1083~0.base_12|) |v_ULTIMATE.start_main_~#t1083~0.offset_10| 2)) |v_#memory_int_15|) (not (= |v_ULTIMATE.start_main_~#t1083~0.base_12| 0)) (= |v_ULTIMATE.start_main_~#t1083~0.offset_10| 0) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1083~0.base_12|) (= (store |v_#valid_43| |v_ULTIMATE.start_main_~#t1083~0.base_12| 1) |v_#valid_42|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_43|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_4|, ULTIMATE.start_main_~#t1083~0.base=|v_ULTIMATE.start_main_~#t1083~0.base_12|, ULTIMATE.start_main_~#t1083~0.offset=|v_ULTIMATE.start_main_~#t1083~0.offset_10|, #valid=|v_#valid_42|, #memory_int=|v_#memory_int_15|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_~#t1083~0.base, ULTIMATE.start_main_~#t1083~0.offset, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 18:19:37,045 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [850] [850] L842-1-->L844: Formula: (and (= |v_ULTIMATE.start_main_~#t1084~0.offset_11| 0) (= (store |v_#valid_49| |v_ULTIMATE.start_main_~#t1084~0.base_13| 1) |v_#valid_48|) (< |v_#StackHeapBarrier_15| |v_ULTIMATE.start_main_~#t1084~0.base_13|) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1084~0.base_13| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1084~0.base_13|) |v_ULTIMATE.start_main_~#t1084~0.offset_11| 3)) |v_#memory_int_21|) (not (= 0 |v_ULTIMATE.start_main_~#t1084~0.base_13|)) (= 0 (select |v_#valid_49| |v_ULTIMATE.start_main_~#t1084~0.base_13|)) (= (store |v_#length_24| |v_ULTIMATE.start_main_~#t1084~0.base_13| 4) |v_#length_23|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_49|, #memory_int=|v_#memory_int_22|, #length=|v_#length_24|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_15|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_6|, ULTIMATE.start_main_~#t1084~0.offset=|v_ULTIMATE.start_main_~#t1084~0.offset_11|, #valid=|v_#valid_48|, #memory_int=|v_#memory_int_21|, #length=|v_#length_23|, ULTIMATE.start_main_~#t1084~0.base=|v_ULTIMATE.start_main_~#t1084~0.base_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_~#t1084~0.offset, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1084~0.base] because there is no mapped edge [2019-12-07 18:19:37,046 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L4-->L789: Formula: (and (= v_~y$r_buff0_thd2~0_35 v_~y$r_buff1_thd2~0_34) (not (= v_P2Thread1of1ForFork1___VERIFIER_assert_~expression_8 0)) (= v_~__unbuffered_p2_EAX~0_10 v_~z~0_8) (= v_~y$r_buff0_thd4~0_25 v_~y$r_buff1_thd4~0_15) (= v_~y$r_buff0_thd0~0_94 v_~y$r_buff1_thd0~0_61) (= v_~y$r_buff1_thd1~0_7 v_~y$r_buff0_thd1~0_7) (= v_~y$r_buff0_thd3~0_32 1) (= v_~y$r_buff0_thd3~0_33 v_~y$r_buff1_thd3~0_20)) InVars {~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_25, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_33, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_94, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_35, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_7, ~z~0=v_~z~0_8, P2Thread1of1ForFork1___VERIFIER_assert_~expression=v_P2Thread1of1ForFork1___VERIFIER_assert_~expression_8} OutVars{P2Thread1of1ForFork1___VERIFIER_assert_~expression=v_P2Thread1of1ForFork1___VERIFIER_assert_~expression_8, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_34, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_25, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_7, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_15, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_20, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_32, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_94, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_35, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_7, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_10, ~z~0=v_~z~0_8, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_61} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, ~y$r_buff1_thd1~0, ~y$r_buff1_thd4~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd3~0, ~__unbuffered_p2_EAX~0, ~y$r_buff1_thd0~0] because there is no mapped edge [2019-12-07 18:19:37,046 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [851] [851] P0ENTRY-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork3_#res.base_3|) (= |v_P0Thread1of1ForFork3_#in~arg.offset_20| v_P0Thread1of1ForFork3_~arg.offset_18) (= v_P0Thread1of1ForFork3_~arg.base_18 |v_P0Thread1of1ForFork3_#in~arg.base_20|) (= v_~b~0_24 1) (= |v_P0Thread1of1ForFork3_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_135 (+ v_~__unbuffered_cnt~0_136 1)) (= v_~x~0_64 1)) InVars {P0Thread1of1ForFork3_#in~arg.offset=|v_P0Thread1of1ForFork3_#in~arg.offset_20|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_136, P0Thread1of1ForFork3_#in~arg.base=|v_P0Thread1of1ForFork3_#in~arg.base_20|} OutVars{~b~0=v_~b~0_24, P0Thread1of1ForFork3_#in~arg.offset=|v_P0Thread1of1ForFork3_#in~arg.offset_20|, P0Thread1of1ForFork3_~arg.base=v_P0Thread1of1ForFork3_~arg.base_18, P0Thread1of1ForFork3_#res.base=|v_P0Thread1of1ForFork3_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_135, P0Thread1of1ForFork3_#res.offset=|v_P0Thread1of1ForFork3_#res.offset_3|, P0Thread1of1ForFork3_~arg.offset=v_P0Thread1of1ForFork3_~arg.offset_18, P0Thread1of1ForFork3_#in~arg.base=|v_P0Thread1of1ForFork3_#in~arg.base_20|, ~x~0=v_~x~0_64} AuxVars[] AssignedVars[~b~0, P0Thread1of1ForFork3_~arg.base, P0Thread1of1ForFork3_#res.base, ~__unbuffered_cnt~0, P0Thread1of1ForFork3_#res.offset, P0Thread1of1ForFork3_~arg.offset, ~x~0] because there is no mapped edge [2019-12-07 18:19:37,047 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [810] [810] L759-2-->L759-5: Formula: (let ((.cse1 (= |P1Thread1of1ForFork0_#t~ite3_Out1278500084| |P1Thread1of1ForFork0_#t~ite4_Out1278500084|)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1278500084 256))) (.cse0 (= (mod ~y$r_buff1_thd2~0_In1278500084 256) 0))) (or (and (not .cse0) (= |P1Thread1of1ForFork0_#t~ite3_Out1278500084| ~y$w_buff1~0_In1278500084) .cse1 (not .cse2)) (and (= |P1Thread1of1ForFork0_#t~ite3_Out1278500084| ~y~0_In1278500084) .cse1 (or .cse2 .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1278500084, ~y$w_buff1~0=~y$w_buff1~0_In1278500084, ~y~0=~y~0_In1278500084, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1278500084} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1278500084, ~y$w_buff1~0=~y$w_buff1~0_In1278500084, P1Thread1of1ForFork0_#t~ite3=|P1Thread1of1ForFork0_#t~ite3_Out1278500084|, ~y~0=~y~0_In1278500084, P1Thread1of1ForFork0_#t~ite4=|P1Thread1of1ForFork0_#t~ite4_Out1278500084|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1278500084} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite3, P1Thread1of1ForFork0_#t~ite4] because there is no mapped edge [2019-12-07 18:19:37,047 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [818] [818] L760-->L760-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In2137458220 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In2137458220 256)))) (or (and (not .cse0) (= |P1Thread1of1ForFork0_#t~ite5_Out2137458220| 0) (not .cse1)) (and (or .cse1 .cse0) (= |P1Thread1of1ForFork0_#t~ite5_Out2137458220| ~y$w_buff0_used~0_In2137458220)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In2137458220, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2137458220} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In2137458220, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2137458220, P1Thread1of1ForFork0_#t~ite5=|P1Thread1of1ForFork0_#t~ite5_Out2137458220|} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 18:19:37,048 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [811] [811] L815-2-->L815-4: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In729305017 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd4~0_In729305017 256)))) (or (and (= |P3Thread1of1ForFork2_#t~ite15_Out729305017| ~y~0_In729305017) (or .cse0 .cse1)) (and (not .cse1) (= |P3Thread1of1ForFork2_#t~ite15_Out729305017| ~y$w_buff1~0_In729305017) (not .cse0)))) InVars {~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In729305017, ~y$w_buff1~0=~y$w_buff1~0_In729305017, ~y~0=~y~0_In729305017, ~y$w_buff1_used~0=~y$w_buff1_used~0_In729305017} OutVars{~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In729305017, ~y$w_buff1~0=~y$w_buff1~0_In729305017, P3Thread1of1ForFork2_#t~ite15=|P3Thread1of1ForFork2_#t~ite15_Out729305017|, ~y~0=~y~0_In729305017, ~y$w_buff1_used~0=~y$w_buff1_used~0_In729305017} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 18:19:37,048 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [819] [819] L761-->L761-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd2~0_In1865640336 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1865640336 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In1865640336 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In1865640336 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P1Thread1of1ForFork0_#t~ite6_Out1865640336| ~y$w_buff1_used~0_In1865640336)) (and (= 0 |P1Thread1of1ForFork0_#t~ite6_Out1865640336|) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1865640336, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1865640336, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1865640336, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1865640336} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1865640336, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1865640336, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1865640336, P1Thread1of1ForFork0_#t~ite6=|P1Thread1of1ForFork0_#t~ite6_Out1865640336|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1865640336} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 18:19:37,049 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [820] [820] L762-->L762-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In1561350495 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In1561350495 256)))) (or (and (not .cse0) (= |P1Thread1of1ForFork0_#t~ite7_Out1561350495| 0) (not .cse1)) (and (= |P1Thread1of1ForFork0_#t~ite7_Out1561350495| ~y$r_buff0_thd2~0_In1561350495) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1561350495, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1561350495} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1561350495, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1561350495, P1Thread1of1ForFork0_#t~ite7=|P1Thread1of1ForFork0_#t~ite7_Out1561350495|} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-12-07 18:19:37,049 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L763-->L763-2: Formula: (let ((.cse3 (= (mod ~y$w_buff1_used~0_In273026256 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd2~0_In273026256 256))) (.cse1 (= (mod ~y$r_buff0_thd2~0_In273026256 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In273026256 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork0_#t~ite8_Out273026256| 0)) (and (= ~y$r_buff1_thd2~0_In273026256 |P1Thread1of1ForFork0_#t~ite8_Out273026256|) (or .cse3 .cse2) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In273026256, ~y$w_buff0_used~0=~y$w_buff0_used~0_In273026256, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In273026256, ~y$w_buff1_used~0=~y$w_buff1_used~0_In273026256} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In273026256, ~y$w_buff0_used~0=~y$w_buff0_used~0_In273026256, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In273026256, P1Thread1of1ForFork0_#t~ite8=|P1Thread1of1ForFork0_#t~ite8_Out273026256|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In273026256} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 18:19:37,049 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [839] [839] L763-2-->P1EXIT: Formula: (and (= v_~y$r_buff1_thd2~0_135 |v_P1Thread1of1ForFork0_#t~ite8_46|) (= v_~__unbuffered_cnt~0_111 (+ v_~__unbuffered_cnt~0_112 1)) (= 0 |v_P1Thread1of1ForFork0_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork0_#res.base_3|)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_112, P1Thread1of1ForFork0_#t~ite8=|v_P1Thread1of1ForFork0_#t~ite8_46|} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_135, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_111, P1Thread1of1ForFork0_#res.offset=|v_P1Thread1of1ForFork0_#res.offset_3|, P1Thread1of1ForFork0_#t~ite8=|v_P1Thread1of1ForFork0_#t~ite8_45|, P1Thread1of1ForFork0_#res.base=|v_P1Thread1of1ForFork0_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork0_#res.offset, P1Thread1of1ForFork0_#t~ite8, P1Thread1of1ForFork0_#res.base] because there is no mapped edge [2019-12-07 18:19:37,049 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [751] [751] L815-4-->L816: Formula: (= |v_P3Thread1of1ForFork2_#t~ite15_8| v_~y~0_44) InVars {P3Thread1of1ForFork2_#t~ite15=|v_P3Thread1of1ForFork2_#t~ite15_8|} OutVars{P3Thread1of1ForFork2_#t~ite15=|v_P3Thread1of1ForFork2_#t~ite15_7|, P3Thread1of1ForFork2_#t~ite16=|v_P3Thread1of1ForFork2_#t~ite16_11|, ~y~0=v_~y~0_44} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite15, P3Thread1of1ForFork2_#t~ite16, ~y~0] because there is no mapped edge [2019-12-07 18:19:37,049 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L790-->L790-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd3~0_In-1151992128 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1151992128 256)))) (or (and (= 0 |P2Thread1of1ForFork1_#t~ite11_Out-1151992128|) (not .cse0) (not .cse1)) (and (= |P2Thread1of1ForFork1_#t~ite11_Out-1151992128| ~y$w_buff0_used~0_In-1151992128) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1151992128, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1151992128} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1151992128, P2Thread1of1ForFork1_#t~ite11=|P2Thread1of1ForFork1_#t~ite11_Out-1151992128|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1151992128} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 18:19:37,050 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L791-->L791-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In863110034 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In863110034 256))) (.cse1 (= (mod ~y$w_buff1_used~0_In863110034 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd3~0_In863110034 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork1_#t~ite12_Out863110034| ~y$w_buff1_used~0_In863110034)) (and (= 0 |P2Thread1of1ForFork1_#t~ite12_Out863110034|) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In863110034, ~y$w_buff0_used~0=~y$w_buff0_used~0_In863110034, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In863110034, ~y$w_buff1_used~0=~y$w_buff1_used~0_In863110034} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In863110034, ~y$w_buff0_used~0=~y$w_buff0_used~0_In863110034, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In863110034, P2Thread1of1ForFork1_#t~ite12=|P2Thread1of1ForFork1_#t~ite12_Out863110034|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In863110034} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 18:19:37,050 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [812] [812] L816-->L816-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd4~0_In1191164529 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In1191164529 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In1191164529 |P3Thread1of1ForFork2_#t~ite17_Out1191164529|)) (and (not .cse0) (= |P3Thread1of1ForFork2_#t~ite17_Out1191164529| 0) (not .cse1)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1191164529, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1191164529} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1191164529, P3Thread1of1ForFork2_#t~ite17=|P3Thread1of1ForFork2_#t~ite17_Out1191164529|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1191164529} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 18:19:37,050 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [813] [813] L792-->L793: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-1534088874 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd3~0_In-1534088874 256) 0)) (.cse1 (= ~y$r_buff0_thd3~0_In-1534088874 ~y$r_buff0_thd3~0_Out-1534088874))) (or (and .cse0 .cse1) (and (not .cse2) (= ~y$r_buff0_thd3~0_Out-1534088874 0) (not .cse0)) (and .cse2 .cse1))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1534088874, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1534088874} OutVars{P2Thread1of1ForFork1_#t~ite13=|P2Thread1of1ForFork1_#t~ite13_Out-1534088874|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1534088874, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-1534088874} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite13, ~y$r_buff0_thd3~0] because there is no mapped edge [2019-12-07 18:19:37,051 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L793-->L793-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd3~0_In2039985828 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In2039985828 256) 0)) (.cse2 (= (mod ~y$w_buff0_used~0_In2039985828 256) 0)) (.cse3 (= 0 (mod ~y$r_buff0_thd3~0_In2039985828 256)))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork1_#t~ite14_Out2039985828| ~y$r_buff1_thd3~0_In2039985828) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork1_#t~ite14_Out2039985828|)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In2039985828, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2039985828, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In2039985828, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2039985828} OutVars{P2Thread1of1ForFork1_#t~ite14=|P2Thread1of1ForFork1_#t~ite14_Out2039985828|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In2039985828, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2039985828, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In2039985828, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2039985828} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 18:19:37,051 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [848] [848] L793-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork1_#res.offset_3|) (= |v_P2Thread1of1ForFork1_#t~ite14_44| v_~y$r_buff1_thd3~0_136) (= 0 |v_P2Thread1of1ForFork1_#res.base_3|) (= v_~__unbuffered_cnt~0_133 (+ v_~__unbuffered_cnt~0_134 1))) InVars {P2Thread1of1ForFork1_#t~ite14=|v_P2Thread1of1ForFork1_#t~ite14_44|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_134} OutVars{P2Thread1of1ForFork1_#t~ite14=|v_P2Thread1of1ForFork1_#t~ite14_43|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_136, P2Thread1of1ForFork1_#res.base=|v_P2Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_133, P2Thread1of1ForFork1_#res.offset=|v_P2Thread1of1ForFork1_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork1_#res.offset] because there is no mapped edge [2019-12-07 18:19:37,051 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [814] [814] L817-->L817-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In-605650022 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd4~0_In-605650022 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd4~0_In-605650022 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In-605650022 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P3Thread1of1ForFork2_#t~ite18_Out-605650022|)) (and (or .cse3 .cse2) (= ~y$w_buff1_used~0_In-605650022 |P3Thread1of1ForFork2_#t~ite18_Out-605650022|) (or .cse1 .cse0)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-605650022, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-605650022, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-605650022, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-605650022} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-605650022, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-605650022, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-605650022, P3Thread1of1ForFork2_#t~ite18=|P3Thread1of1ForFork2_#t~ite18_Out-605650022|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-605650022} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 18:19:37,051 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [815] [815] L818-->L818-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In433204238 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd4~0_In433204238 256)))) (or (and (= |P3Thread1of1ForFork2_#t~ite19_Out433204238| ~y$r_buff0_thd4~0_In433204238) (or .cse0 .cse1)) (and (not .cse1) (= |P3Thread1of1ForFork2_#t~ite19_Out433204238| 0) (not .cse0)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In433204238, ~y$w_buff0_used~0=~y$w_buff0_used~0_In433204238} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In433204238, P3Thread1of1ForFork2_#t~ite19=|P3Thread1of1ForFork2_#t~ite19_Out433204238|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In433204238} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 18:19:37,051 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [816] [816] L819-->L819-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In640587695 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd4~0_In640587695 256) 0)) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In640587695 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd4~0_In640587695 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P3Thread1of1ForFork2_#t~ite20_Out640587695|)) (and (or .cse3 .cse2) (or .cse0 .cse1) (= ~y$r_buff1_thd4~0_In640587695 |P3Thread1of1ForFork2_#t~ite20_Out640587695|)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In640587695, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In640587695, ~y$w_buff0_used~0=~y$w_buff0_used~0_In640587695, ~y$w_buff1_used~0=~y$w_buff1_used~0_In640587695} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In640587695, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In640587695, ~y$w_buff0_used~0=~y$w_buff0_used~0_In640587695, P3Thread1of1ForFork2_#t~ite20=|P3Thread1of1ForFork2_#t~ite20_Out640587695|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In640587695} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 18:19:37,052 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [836] [836] L819-2-->P3EXIT: Formula: (and (= |v_P3Thread1of1ForFork2_#t~ite20_54| v_~y$r_buff1_thd4~0_130) (= (+ v_~__unbuffered_cnt~0_100 1) v_~__unbuffered_cnt~0_99) (= 0 |v_P3Thread1of1ForFork2_#res.base_3|) (= 0 |v_P3Thread1of1ForFork2_#res.offset_3|)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_100, P3Thread1of1ForFork2_#t~ite20=|v_P3Thread1of1ForFork2_#t~ite20_54|} OutVars{~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_130, P3Thread1of1ForFork2_#res.base=|v_P3Thread1of1ForFork2_#res.base_3|, P3Thread1of1ForFork2_#res.offset=|v_P3Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_99, P3Thread1of1ForFork2_#t~ite20=|v_P3Thread1of1ForFork2_#t~ite20_53|} AuxVars[] AssignedVars[~y$r_buff1_thd4~0, P3Thread1of1ForFork2_#res.base, P3Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0, P3Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 18:19:37,052 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [732] [732] L848-->L850-2: Formula: (and (not (= (mod v_~main$tmp_guard0~0_4 256) 0)) (or (= 0 (mod v_~y$r_buff0_thd0~0_51 256)) (= (mod v_~y$w_buff0_used~0_107 256) 0))) InVars {~y$w_buff0_used~0=v_~y$w_buff0_used~0_107, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_51, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_4} OutVars{~y$w_buff0_used~0=v_~y$w_buff0_used~0_107, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_51, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_4} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 18:19:37,052 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [817] [817] L850-2-->L850-5: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In1807420044 256))) (.cse0 (= (mod ~y$r_buff1_thd0~0_In1807420044 256) 0)) (.cse2 (= |ULTIMATE.start_main_#t~ite25_Out1807420044| |ULTIMATE.start_main_#t~ite26_Out1807420044|))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite25_Out1807420044| ~y~0_In1807420044) .cse2) (and (= |ULTIMATE.start_main_#t~ite25_Out1807420044| ~y$w_buff1~0_In1807420044) (not .cse1) (not .cse0) .cse2))) InVars {~y$w_buff1~0=~y$w_buff1~0_In1807420044, ~y~0=~y~0_In1807420044, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1807420044, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1807420044} OutVars{~y$w_buff1~0=~y$w_buff1~0_In1807420044, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out1807420044|, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out1807420044|, ~y~0=~y~0_In1807420044, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1807420044, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1807420044} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 18:19:37,052 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L851-->L851-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In640075485 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In640075485 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite27_Out640075485| 0) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite27_Out640075485| ~y$w_buff0_used~0_In640075485) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In640075485, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In640075485} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In640075485, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In640075485, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out640075485|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 18:19:37,053 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L852-->L852-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In661125972 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In661125972 256))) (.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In661125972 256))) (.cse3 (= (mod ~y$w_buff1_used~0_In661125972 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite28_Out661125972| 0)) (and (or .cse1 .cse0) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite28_Out661125972| ~y$w_buff1_used~0_In661125972)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In661125972, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In661125972, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In661125972, ~y$w_buff1_used~0=~y$w_buff1_used~0_In661125972} OutVars{ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out661125972|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In661125972, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In661125972, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In661125972, ~y$w_buff1_used~0=~y$w_buff1_used~0_In661125972} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 18:19:37,053 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [797] [797] L853-->L853-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-1569878414 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1569878414 256)))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite29_Out-1569878414|)) (and (or .cse0 .cse1) (= ~y$r_buff0_thd0~0_In-1569878414 |ULTIMATE.start_main_#t~ite29_Out-1569878414|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1569878414, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1569878414} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1569878414, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-1569878414|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1569878414} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 18:19:37,053 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [807] [807] L854-->L854-2: Formula: (let ((.cse3 (= (mod ~y$w_buff1_used~0_In598351424 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In598351424 256))) (.cse0 (= (mod ~y$r_buff0_thd0~0_In598351424 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In598351424 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite30_Out598351424| ~y$r_buff1_thd0~0_In598351424) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= |ULTIMATE.start_main_#t~ite30_Out598351424| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In598351424, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In598351424, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In598351424, ~y$w_buff1_used~0=~y$w_buff1_used~0_In598351424} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out598351424|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In598351424, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In598351424, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In598351424, ~y$w_buff1_used~0=~y$w_buff1_used~0_In598351424} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30] because there is no mapped edge [2019-12-07 18:19:37,055 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [855] [855] L863-->L863-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-730923790 256)))) (or (and (= |ULTIMATE.start_main_#t~ite39_In-730923790| |ULTIMATE.start_main_#t~ite39_Out-730923790|) (not .cse0) (= |ULTIMATE.start_main_#t~ite40_Out-730923790| ~y$w_buff1~0_In-730923790)) (and (= |ULTIMATE.start_main_#t~ite40_Out-730923790| |ULTIMATE.start_main_#t~ite39_Out-730923790|) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-730923790 256) 0))) (or (and (= (mod ~y$r_buff1_thd0~0_In-730923790 256) 0) .cse1) (= 0 (mod ~y$w_buff0_used~0_In-730923790 256)) (and (= 0 (mod ~y$w_buff1_used~0_In-730923790 256)) .cse1))) (= ~y$w_buff1~0_In-730923790 |ULTIMATE.start_main_#t~ite39_Out-730923790|) .cse0))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-730923790, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-730923790, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_In-730923790|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-730923790, ~weak$$choice2~0=~weak$$choice2~0_In-730923790, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-730923790, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-730923790} OutVars{ULTIMATE.start_main_#t~ite40=|ULTIMATE.start_main_#t~ite40_Out-730923790|, ~y$w_buff1~0=~y$w_buff1~0_In-730923790, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-730923790, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out-730923790|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-730923790, ~weak$$choice2~0=~weak$$choice2~0_In-730923790, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-730923790, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-730923790} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 18:19:37,056 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [726] [726] L866-->L867: Formula: (and (= v_~y$r_buff0_thd0~0_49 v_~y$r_buff0_thd0~0_48) (not (= 0 (mod v_~weak$$choice2~0_17 256)))) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_49, ~weak$$choice2~0=v_~weak$$choice2~0_17} OutVars{~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_48, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_6|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_6|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_6|, ~weak$$choice2~0=v_~weak$$choice2~0_17} AuxVars[] AssignedVars[~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 18:19:37,057 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [854] [854] L867-->L867-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-420210138 256) 0))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite51_In-420210138| |ULTIMATE.start_main_#t~ite51_Out-420210138|) (= |ULTIMATE.start_main_#t~ite52_Out-420210138| ~y$r_buff1_thd0~0_In-420210138)) (and (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-420210138 256) 0))) (or (= 0 (mod ~y$w_buff0_used~0_In-420210138 256)) (and (= 0 (mod ~y$w_buff1_used~0_In-420210138 256)) .cse1) (and .cse1 (= (mod ~y$r_buff1_thd0~0_In-420210138 256) 0)))) (= ~y$r_buff1_thd0~0_In-420210138 |ULTIMATE.start_main_#t~ite51_Out-420210138|) .cse0 (= |ULTIMATE.start_main_#t~ite52_Out-420210138| |ULTIMATE.start_main_#t~ite51_Out-420210138|)))) InVars {ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_In-420210138|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-420210138, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-420210138, ~weak$$choice2~0=~weak$$choice2~0_In-420210138, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-420210138, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-420210138} OutVars{ULTIMATE.start_main_#t~ite52=|ULTIMATE.start_main_#t~ite52_Out-420210138|, ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_Out-420210138|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-420210138, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-420210138, ~weak$$choice2~0=~weak$$choice2~0_In-420210138, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-420210138, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-420210138} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start_main_#t~ite51] because there is no mapped edge [2019-12-07 18:19:37,057 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [834] [834] L869-->L872-1: Formula: (and (= (mod v_~main$tmp_guard1~0_19 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (= v_~y~0_96 v_~y$mem_tmp~0_13) (= 0 v_~y$flush_delayed~0_22) (not (= (mod v_~y$flush_delayed~0_23 256) 0))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_13, ~y$flush_delayed~0=v_~y$flush_delayed~0_23, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_19} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_13, ~y$flush_delayed~0=v_~y$flush_delayed~0_22, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_19, ~y~0=v_~y~0_96, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_17|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[~y$flush_delayed~0, ~y~0, ULTIMATE.start_main_#t~ite53, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:19:37,057 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L872-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_12 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_12 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_12, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:19:37,113 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_fd09fa57-94d0-4642-b045-576cc7a10020/bin/uautomizer/witness.graphml [2019-12-07 18:19:37,113 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:19:37,114 INFO L168 Benchmark]: Toolchain (without parser) took 288065.20 ms. Allocated memory was 1.0 GB in the beginning and 11.0 GB in the end (delta: 10.0 GB). Free memory was 940.6 MB in the beginning and 6.0 GB in the end (delta: -5.1 GB). Peak memory consumption was 4.9 GB. Max. memory is 11.5 GB. [2019-12-07 18:19:37,114 INFO L168 Benchmark]: CDTParser took 0.20 ms. Allocated memory is still 1.0 GB. Free memory is still 960.8 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:19:37,115 INFO L168 Benchmark]: CACSL2BoogieTranslator took 380.85 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 102.2 MB). Free memory was 940.6 MB in the beginning and 1.1 GB in the end (delta: -124.0 MB). Peak memory consumption was 18.2 MB. Max. memory is 11.5 GB. [2019-12-07 18:19:37,115 INFO L168 Benchmark]: Boogie Procedure Inliner took 43.46 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:19:37,115 INFO L168 Benchmark]: Boogie Preprocessor took 28.13 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. [2019-12-07 18:19:37,115 INFO L168 Benchmark]: RCFGBuilder took 418.76 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 998.0 MB in the end (delta: 56.0 MB). Peak memory consumption was 56.0 MB. Max. memory is 11.5 GB. [2019-12-07 18:19:37,115 INFO L168 Benchmark]: TraceAbstraction took 287119.81 ms. Allocated memory was 1.1 GB in the beginning and 11.0 GB in the end (delta: 9.9 GB). Free memory was 998.0 MB in the beginning and 6.1 GB in the end (delta: -5.1 GB). Peak memory consumption was 6.2 GB. Max. memory is 11.5 GB. [2019-12-07 18:19:37,116 INFO L168 Benchmark]: Witness Printer took 71.17 ms. Allocated memory is still 11.0 GB. Free memory was 6.1 GB in the beginning and 6.0 GB in the end (delta: 37.8 MB). Peak memory consumption was 37.8 MB. Max. memory is 11.5 GB. [2019-12-07 18:19:37,117 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20 ms. Allocated memory is still 1.0 GB. Free memory is still 960.8 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 380.85 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 102.2 MB). Free memory was 940.6 MB in the beginning and 1.1 GB in the end (delta: -124.0 MB). Peak memory consumption was 18.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 43.46 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 28.13 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 418.76 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 998.0 MB in the end (delta: 56.0 MB). Peak memory consumption was 56.0 MB. Max. memory is 11.5 GB. * TraceAbstraction took 287119.81 ms. Allocated memory was 1.1 GB in the beginning and 11.0 GB in the end (delta: 9.9 GB). Free memory was 998.0 MB in the beginning and 6.1 GB in the end (delta: -5.1 GB). Peak memory consumption was 6.2 GB. Max. memory is 11.5 GB. * Witness Printer took 71.17 ms. Allocated memory is still 11.0 GB. Free memory was 6.1 GB in the beginning and 6.0 GB in the end (delta: 37.8 MB). Peak memory consumption was 37.8 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.4s, 193 ProgramPointsBefore, 101 ProgramPointsAfterwards, 227 TransitionsBefore, 110 TransitionsAfterwards, 18432 CoEnabledTransitionPairs, 8 FixpointIterations, 37 TrivialSequentialCompositions, 48 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 41 ConcurrentYvCompositions, 30 ChoiceCompositions, 6323 VarBasedMoverChecksPositive, 274 VarBasedMoverChecksNegative, 82 SemBasedMoverChecksPositive, 278 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.0s, 0 MoverChecksTotal, 89209 CheckedPairsTotal, 126 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L838] FCALL, FORK 0 pthread_create(&t1081, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L840] FCALL, FORK 0 pthread_create(&t1082, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L842] FCALL, FORK 0 pthread_create(&t1083, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L773] 3 y$w_buff1 = y$w_buff0 [L774] 3 y$w_buff0 = 2 [L775] 3 y$w_buff1_used = y$w_buff0_used [L776] 3 y$w_buff0_used = (_Bool)1 [L844] FCALL, FORK 0 pthread_create(&t1084, ((void *)0), P3, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=0] [L803] 4 z = 1 [L806] 4 a = 1 [L809] 4 __unbuffered_p3_EAX = a [L812] 4 __unbuffered_p3_EBX = b VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L753] 2 x = 2 [L756] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L815] 4 y$w_buff0_used && y$r_buff0_thd4 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd4 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L759] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L759] 2 y = y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) [L760] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L789] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used=0, y$w_buff1=0, y$w_buff1_used=0, y$w_buff1_used && y$r_buff1_thd4 ? y$w_buff1 : y=1, z=1] [L761] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L762] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L789] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L790] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L791] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L816] 4 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd4 ? (_Bool)0 : y$w_buff0_used [L817] 4 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd4 || y$w_buff1_used && y$r_buff1_thd4 ? (_Bool)0 : y$w_buff1_used [L818] 4 y$r_buff0_thd4 = y$w_buff0_used && y$r_buff0_thd4 ? (_Bool)0 : y$r_buff0_thd4 [L846] 0 main$tmp_guard0 = __unbuffered_cnt == 4 VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L850] 0 y = y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L851] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L852] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L853] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L854] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L857] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L858] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L859] 0 y$flush_delayed = weak$$choice2 [L860] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L861] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L861] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L862] EXPR 0 weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L862] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L863] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L864] EXPR 0 weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L864] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L865] EXPR 0 weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L865] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L867] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L868] 0 main$tmp_guard1 = !(x == 2 && y == 2 && __unbuffered_p2_EAX == 0 && __unbuffered_p3_EAX == 1 && __unbuffered_p3_EBX == 0) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 181 locations, 2 error locations. Result: UNSAFE, OverallTime: 286.9s, OverallIterations: 32, TraceHistogramMax: 1, AutomataDifference: 64.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 5871 SDtfs, 6298 SDslu, 14721 SDs, 0 SdLazy, 10541 SolverSat, 459 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 10.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 414 GetRequests, 110 SyntacticMatches, 34 SemanticMatches, 270 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 710 ImplicationChecksByTransitivity, 2.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=488294occurred in iteration=7, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 166.0s AutomataMinimizationTime, 31 MinimizatonAttempts, 754117 StatesRemovedByMinimization, 27 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.7s InterpolantComputationTime, 1673 NumberOfCodeBlocks, 1673 NumberOfCodeBlocksAsserted, 32 NumberOfCheckSat, 1571 ConstructedInterpolants, 0 QuantifiedInterpolants, 306810 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 31 InterpolantComputations, 31 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...