./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix045_rmo.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_c7de1eab-0a2f-4fa4-af55-d5f0060903d0/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_c7de1eab-0a2f-4fa4-af55-d5f0060903d0/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_c7de1eab-0a2f-4fa4-af55-d5f0060903d0/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_c7de1eab-0a2f-4fa4-af55-d5f0060903d0/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix045_rmo.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_c7de1eab-0a2f-4fa4-af55-d5f0060903d0/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_c7de1eab-0a2f-4fa4-af55-d5f0060903d0/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ffdb96218020f2881bb98b194a2936942fa2529d ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 16:28:50,390 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 16:28:50,391 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 16:28:50,399 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 16:28:50,399 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 16:28:50,400 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 16:28:50,401 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 16:28:50,402 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 16:28:50,404 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 16:28:50,404 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 16:28:50,405 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 16:28:50,406 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 16:28:50,406 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 16:28:50,406 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 16:28:50,407 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 16:28:50,408 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 16:28:50,408 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 16:28:50,409 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 16:28:50,410 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 16:28:50,412 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 16:28:50,413 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 16:28:50,413 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 16:28:50,414 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 16:28:50,414 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 16:28:50,416 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 16:28:50,416 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 16:28:50,416 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 16:28:50,417 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 16:28:50,417 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 16:28:50,418 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 16:28:50,418 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 16:28:50,418 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 16:28:50,419 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 16:28:50,419 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 16:28:50,420 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 16:28:50,420 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 16:28:50,420 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 16:28:50,420 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 16:28:50,420 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 16:28:50,421 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 16:28:50,421 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 16:28:50,422 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_c7de1eab-0a2f-4fa4-af55-d5f0060903d0/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 16:28:50,431 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 16:28:50,431 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 16:28:50,432 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 16:28:50,432 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 16:28:50,432 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 16:28:50,433 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 16:28:50,433 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 16:28:50,433 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 16:28:50,433 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 16:28:50,433 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 16:28:50,433 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 16:28:50,433 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 16:28:50,434 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 16:28:50,434 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 16:28:50,434 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 16:28:50,434 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 16:28:50,434 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 16:28:50,434 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 16:28:50,434 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 16:28:50,434 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 16:28:50,435 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 16:28:50,435 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 16:28:50,435 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 16:28:50,435 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 16:28:50,435 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 16:28:50,435 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 16:28:50,435 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 16:28:50,435 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 16:28:50,436 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 16:28:50,436 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_c7de1eab-0a2f-4fa4-af55-d5f0060903d0/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ffdb96218020f2881bb98b194a2936942fa2529d [2019-12-07 16:28:50,534 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 16:28:50,543 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 16:28:50,545 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 16:28:50,546 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 16:28:50,547 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 16:28:50,547 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_c7de1eab-0a2f-4fa4-af55-d5f0060903d0/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix045_rmo.opt.i [2019-12-07 16:28:50,592 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_c7de1eab-0a2f-4fa4-af55-d5f0060903d0/bin/uautomizer/data/20c073b08/c3897b9e1fc640499b0c88e24bbedfe7/FLAGc4c494851 [2019-12-07 16:28:50,944 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 16:28:50,945 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_c7de1eab-0a2f-4fa4-af55-d5f0060903d0/sv-benchmarks/c/pthread-wmm/mix045_rmo.opt.i [2019-12-07 16:28:50,954 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_c7de1eab-0a2f-4fa4-af55-d5f0060903d0/bin/uautomizer/data/20c073b08/c3897b9e1fc640499b0c88e24bbedfe7/FLAGc4c494851 [2019-12-07 16:28:50,963 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_c7de1eab-0a2f-4fa4-af55-d5f0060903d0/bin/uautomizer/data/20c073b08/c3897b9e1fc640499b0c88e24bbedfe7 [2019-12-07 16:28:50,965 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 16:28:50,966 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 16:28:50,966 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 16:28:50,966 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 16:28:50,968 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 16:28:50,969 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 04:28:50" (1/1) ... [2019-12-07 16:28:50,971 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5a2ff042 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:28:50, skipping insertion in model container [2019-12-07 16:28:50,971 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 04:28:50" (1/1) ... [2019-12-07 16:28:50,975 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 16:28:51,002 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 16:28:51,240 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 16:28:51,248 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 16:28:51,291 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 16:28:51,336 INFO L208 MainTranslator]: Completed translation [2019-12-07 16:28:51,336 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:28:51 WrapperNode [2019-12-07 16:28:51,336 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 16:28:51,337 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 16:28:51,337 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 16:28:51,337 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 16:28:51,343 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:28:51" (1/1) ... [2019-12-07 16:28:51,355 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:28:51" (1/1) ... [2019-12-07 16:28:51,377 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 16:28:51,377 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 16:28:51,377 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 16:28:51,377 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 16:28:51,383 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:28:51" (1/1) ... [2019-12-07 16:28:51,384 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:28:51" (1/1) ... [2019-12-07 16:28:51,387 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:28:51" (1/1) ... [2019-12-07 16:28:51,387 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:28:51" (1/1) ... [2019-12-07 16:28:51,394 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:28:51" (1/1) ... [2019-12-07 16:28:51,396 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:28:51" (1/1) ... [2019-12-07 16:28:51,399 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:28:51" (1/1) ... [2019-12-07 16:28:51,402 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 16:28:51,402 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 16:28:51,403 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 16:28:51,403 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 16:28:51,403 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:28:51" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_c7de1eab-0a2f-4fa4-af55-d5f0060903d0/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 16:28:51,449 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 16:28:51,449 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 16:28:51,449 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 16:28:51,449 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 16:28:51,449 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 16:28:51,449 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 16:28:51,449 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 16:28:51,450 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 16:28:51,450 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 16:28:51,450 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 16:28:51,450 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 16:28:51,450 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 16:28:51,450 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 16:28:51,451 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 16:28:51,784 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 16:28:51,784 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 16:28:51,785 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:28:51 BoogieIcfgContainer [2019-12-07 16:28:51,785 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 16:28:51,785 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 16:28:51,786 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 16:28:51,787 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 16:28:51,787 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 04:28:50" (1/3) ... [2019-12-07 16:28:51,788 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@50f7f411 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 04:28:51, skipping insertion in model container [2019-12-07 16:28:51,788 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:28:51" (2/3) ... [2019-12-07 16:28:51,788 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@50f7f411 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 04:28:51, skipping insertion in model container [2019-12-07 16:28:51,788 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:28:51" (3/3) ... [2019-12-07 16:28:51,789 INFO L109 eAbstractionObserver]: Analyzing ICFG mix045_rmo.opt.i [2019-12-07 16:28:51,795 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 16:28:51,796 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 16:28:51,800 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 16:28:51,801 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 16:28:51,822 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,822 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,822 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,822 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,822 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,823 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,823 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,823 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,823 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,823 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,823 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,824 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,824 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,824 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,824 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,824 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,824 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,824 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,824 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,824 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,825 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,825 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,825 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,825 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,825 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,825 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,825 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,825 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,826 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,826 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,826 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,826 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,826 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,826 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,826 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,826 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,827 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,827 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,827 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,827 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,827 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,827 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,828 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,828 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,828 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,828 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,828 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,828 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,828 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,828 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,829 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,829 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,829 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,829 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,829 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,829 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,829 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,829 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,829 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,830 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,830 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,830 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,830 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,830 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,830 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,830 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,830 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,830 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,831 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,831 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:28:51,845 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 16:28:51,859 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 16:28:51,859 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 16:28:51,859 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 16:28:51,859 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 16:28:51,859 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 16:28:51,859 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 16:28:51,860 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 16:28:51,860 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 16:28:51,870 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 164 places, 195 transitions [2019-12-07 16:28:51,872 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 164 places, 195 transitions [2019-12-07 16:28:51,929 INFO L134 PetriNetUnfolder]: 41/192 cut-off events. [2019-12-07 16:28:51,929 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 16:28:51,937 INFO L76 FinitePrefix]: Finished finitePrefix Result has 202 conditions, 192 events. 41/192 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 469 event pairs. 9/158 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-12-07 16:28:51,948 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 164 places, 195 transitions [2019-12-07 16:28:51,972 INFO L134 PetriNetUnfolder]: 41/192 cut-off events. [2019-12-07 16:28:51,973 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 16:28:51,977 INFO L76 FinitePrefix]: Finished finitePrefix Result has 202 conditions, 192 events. 41/192 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 469 event pairs. 9/158 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-12-07 16:28:51,987 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 11490 [2019-12-07 16:28:51,988 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 16:28:54,776 WARN L192 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 91 DAG size of output: 89 [2019-12-07 16:28:54,864 INFO L206 etLargeBlockEncoding]: Checked pairs total: 46792 [2019-12-07 16:28:54,864 INFO L214 etLargeBlockEncoding]: Total number of compositions: 114 [2019-12-07 16:28:54,867 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 82 places, 91 transitions [2019-12-07 16:28:55,557 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 16134 states. [2019-12-07 16:28:55,559 INFO L276 IsEmpty]: Start isEmpty. Operand 16134 states. [2019-12-07 16:28:55,563 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-12-07 16:28:55,563 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:55,563 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:55,564 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:55,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:55,567 INFO L82 PathProgramCache]: Analyzing trace with hash 1643101290, now seen corresponding path program 1 times [2019-12-07 16:28:55,573 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:28:55,573 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [269018912] [2019-12-07 16:28:55,573 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:55,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:55,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:55,727 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [269018912] [2019-12-07 16:28:55,728 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:55,728 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 16:28:55,729 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [440453931] [2019-12-07 16:28:55,732 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:28:55,732 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:28:55,741 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:28:55,741 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:28:55,743 INFO L87 Difference]: Start difference. First operand 16134 states. Second operand 3 states. [2019-12-07 16:28:55,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:55,967 INFO L93 Difference]: Finished difference Result 16034 states and 60310 transitions. [2019-12-07 16:28:55,967 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:28:55,968 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-12-07 16:28:55,968 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:56,135 INFO L225 Difference]: With dead ends: 16034 [2019-12-07 16:28:56,135 INFO L226 Difference]: Without dead ends: 15698 [2019-12-07 16:28:56,136 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:28:56,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15698 states. [2019-12-07 16:28:56,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15698 to 15698. [2019-12-07 16:28:56,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15698 states. [2019-12-07 16:28:56,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15698 states to 15698 states and 59106 transitions. [2019-12-07 16:28:56,640 INFO L78 Accepts]: Start accepts. Automaton has 15698 states and 59106 transitions. Word has length 7 [2019-12-07 16:28:56,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:56,641 INFO L462 AbstractCegarLoop]: Abstraction has 15698 states and 59106 transitions. [2019-12-07 16:28:56,641 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:28:56,642 INFO L276 IsEmpty]: Start isEmpty. Operand 15698 states and 59106 transitions. [2019-12-07 16:28:56,646 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 16:28:56,646 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:56,646 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:56,646 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:56,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:56,647 INFO L82 PathProgramCache]: Analyzing trace with hash 565568960, now seen corresponding path program 1 times [2019-12-07 16:28:56,647 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:28:56,647 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [946870319] [2019-12-07 16:28:56,647 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:56,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:56,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:56,724 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [946870319] [2019-12-07 16:28:56,725 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:56,725 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:28:56,725 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1706477806] [2019-12-07 16:28:56,726 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:28:56,726 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:28:56,726 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:28:56,726 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:28:56,726 INFO L87 Difference]: Start difference. First operand 15698 states and 59106 transitions. Second operand 4 states. [2019-12-07 16:28:57,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:57,034 INFO L93 Difference]: Finished difference Result 24414 states and 88322 transitions. [2019-12-07 16:28:57,035 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:28:57,035 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 16:28:57,035 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:57,203 INFO L225 Difference]: With dead ends: 24414 [2019-12-07 16:28:57,203 INFO L226 Difference]: Without dead ends: 24400 [2019-12-07 16:28:57,204 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:28:57,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24400 states. [2019-12-07 16:28:57,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24400 to 22284. [2019-12-07 16:28:57,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22284 states. [2019-12-07 16:28:57,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22284 states to 22284 states and 81513 transitions. [2019-12-07 16:28:57,663 INFO L78 Accepts]: Start accepts. Automaton has 22284 states and 81513 transitions. Word has length 13 [2019-12-07 16:28:57,663 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:57,663 INFO L462 AbstractCegarLoop]: Abstraction has 22284 states and 81513 transitions. [2019-12-07 16:28:57,664 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:28:57,664 INFO L276 IsEmpty]: Start isEmpty. Operand 22284 states and 81513 transitions. [2019-12-07 16:28:57,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 16:28:57,666 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:57,666 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:57,666 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:57,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:57,666 INFO L82 PathProgramCache]: Analyzing trace with hash 1863901117, now seen corresponding path program 1 times [2019-12-07 16:28:57,666 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:28:57,666 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239663613] [2019-12-07 16:28:57,667 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:57,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:57,700 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:57,700 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [239663613] [2019-12-07 16:28:57,700 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:57,700 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:28:57,701 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2083091248] [2019-12-07 16:28:57,701 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:28:57,701 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:28:57,701 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:28:57,701 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:28:57,702 INFO L87 Difference]: Start difference. First operand 22284 states and 81513 transitions. Second operand 3 states. [2019-12-07 16:28:57,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:57,738 INFO L93 Difference]: Finished difference Result 12731 states and 40311 transitions. [2019-12-07 16:28:57,738 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:28:57,739 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 13 [2019-12-07 16:28:57,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:57,830 INFO L225 Difference]: With dead ends: 12731 [2019-12-07 16:28:57,830 INFO L226 Difference]: Without dead ends: 12731 [2019-12-07 16:28:57,831 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:28:57,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12731 states. [2019-12-07 16:28:57,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12731 to 12731. [2019-12-07 16:28:57,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12731 states. [2019-12-07 16:28:58,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12731 states to 12731 states and 40311 transitions. [2019-12-07 16:28:58,017 INFO L78 Accepts]: Start accepts. Automaton has 12731 states and 40311 transitions. Word has length 13 [2019-12-07 16:28:58,017 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:58,017 INFO L462 AbstractCegarLoop]: Abstraction has 12731 states and 40311 transitions. [2019-12-07 16:28:58,017 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:28:58,018 INFO L276 IsEmpty]: Start isEmpty. Operand 12731 states and 40311 transitions. [2019-12-07 16:28:58,018 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2019-12-07 16:28:58,018 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:58,018 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:58,019 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:58,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:58,019 INFO L82 PathProgramCache]: Analyzing trace with hash -709244429, now seen corresponding path program 1 times [2019-12-07 16:28:58,019 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:28:58,019 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [247414466] [2019-12-07 16:28:58,019 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:58,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:58,069 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:58,070 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [247414466] [2019-12-07 16:28:58,070 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:58,070 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:28:58,070 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1700520935] [2019-12-07 16:28:58,070 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:28:58,070 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:28:58,071 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:28:58,071 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:28:58,071 INFO L87 Difference]: Start difference. First operand 12731 states and 40311 transitions. Second operand 4 states. [2019-12-07 16:28:58,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:58,207 INFO L93 Difference]: Finished difference Result 15391 states and 48077 transitions. [2019-12-07 16:28:58,208 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:28:58,208 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 14 [2019-12-07 16:28:58,208 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:58,233 INFO L225 Difference]: With dead ends: 15391 [2019-12-07 16:28:58,234 INFO L226 Difference]: Without dead ends: 15391 [2019-12-07 16:28:58,234 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:28:58,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15391 states. [2019-12-07 16:28:58,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15391 to 13966. [2019-12-07 16:28:58,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13966 states. [2019-12-07 16:28:58,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13966 states to 13966 states and 44017 transitions. [2019-12-07 16:28:58,480 INFO L78 Accepts]: Start accepts. Automaton has 13966 states and 44017 transitions. Word has length 14 [2019-12-07 16:28:58,480 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:58,480 INFO L462 AbstractCegarLoop]: Abstraction has 13966 states and 44017 transitions. [2019-12-07 16:28:58,480 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:28:58,480 INFO L276 IsEmpty]: Start isEmpty. Operand 13966 states and 44017 transitions. [2019-12-07 16:28:58,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2019-12-07 16:28:58,482 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:58,483 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:58,483 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:58,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:58,483 INFO L82 PathProgramCache]: Analyzing trace with hash 1059334979, now seen corresponding path program 1 times [2019-12-07 16:28:58,483 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:28:58,483 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [337677410] [2019-12-07 16:28:58,483 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:58,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:58,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:58,545 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [337677410] [2019-12-07 16:28:58,545 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:58,545 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:28:58,545 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2104749335] [2019-12-07 16:28:58,546 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:28:58,546 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:28:58,546 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:28:58,546 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:28:58,546 INFO L87 Difference]: Start difference. First operand 13966 states and 44017 transitions. Second operand 5 states. [2019-12-07 16:28:58,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:58,833 INFO L93 Difference]: Finished difference Result 18476 states and 56975 transitions. [2019-12-07 16:28:58,833 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 16:28:58,833 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 20 [2019-12-07 16:28:58,834 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:58,858 INFO L225 Difference]: With dead ends: 18476 [2019-12-07 16:28:58,858 INFO L226 Difference]: Without dead ends: 18469 [2019-12-07 16:28:58,859 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 16:28:58,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18469 states. [2019-12-07 16:28:59,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18469 to 14127. [2019-12-07 16:28:59,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14127 states. [2019-12-07 16:28:59,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14127 states to 14127 states and 44412 transitions. [2019-12-07 16:28:59,131 INFO L78 Accepts]: Start accepts. Automaton has 14127 states and 44412 transitions. Word has length 20 [2019-12-07 16:28:59,131 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:28:59,131 INFO L462 AbstractCegarLoop]: Abstraction has 14127 states and 44412 transitions. [2019-12-07 16:28:59,131 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:28:59,131 INFO L276 IsEmpty]: Start isEmpty. Operand 14127 states and 44412 transitions. [2019-12-07 16:28:59,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 16:28:59,139 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:28:59,139 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:28:59,139 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:28:59,139 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:28:59,139 INFO L82 PathProgramCache]: Analyzing trace with hash 1629892990, now seen corresponding path program 1 times [2019-12-07 16:28:59,140 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:28:59,140 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1017007389] [2019-12-07 16:28:59,140 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:28:59,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:28:59,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:28:59,260 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1017007389] [2019-12-07 16:28:59,260 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:28:59,260 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 16:28:59,260 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [49223981] [2019-12-07 16:28:59,261 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 16:28:59,261 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:28:59,261 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 16:28:59,261 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2019-12-07 16:28:59,261 INFO L87 Difference]: Start difference. First operand 14127 states and 44412 transitions. Second operand 8 states. [2019-12-07 16:28:59,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:28:59,662 INFO L93 Difference]: Finished difference Result 19872 states and 61083 transitions. [2019-12-07 16:28:59,662 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 16:28:59,662 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 28 [2019-12-07 16:28:59,662 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:28:59,683 INFO L225 Difference]: With dead ends: 19872 [2019-12-07 16:28:59,684 INFO L226 Difference]: Without dead ends: 19856 [2019-12-07 16:28:59,684 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=41, Invalid=91, Unknown=0, NotChecked=0, Total=132 [2019-12-07 16:28:59,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19856 states. [2019-12-07 16:28:59,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19856 to 18066. [2019-12-07 16:28:59,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18066 states. [2019-12-07 16:29:00,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18066 states to 18066 states and 55900 transitions. [2019-12-07 16:29:00,006 INFO L78 Accepts]: Start accepts. Automaton has 18066 states and 55900 transitions. Word has length 28 [2019-12-07 16:29:00,007 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:29:00,007 INFO L462 AbstractCegarLoop]: Abstraction has 18066 states and 55900 transitions. [2019-12-07 16:29:00,007 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 16:29:00,007 INFO L276 IsEmpty]: Start isEmpty. Operand 18066 states and 55900 transitions. [2019-12-07 16:29:00,018 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 16:29:00,018 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:29:00,018 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:29:00,018 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:29:00,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:29:00,019 INFO L82 PathProgramCache]: Analyzing trace with hash 987674292, now seen corresponding path program 1 times [2019-12-07 16:29:00,019 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:29:00,019 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [564235766] [2019-12-07 16:29:00,019 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:29:00,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:29:00,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:29:00,096 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [564235766] [2019-12-07 16:29:00,096 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:29:00,096 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:29:00,096 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [366193597] [2019-12-07 16:29:00,096 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 16:29:00,096 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:29:00,096 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 16:29:00,097 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:29:00,097 INFO L87 Difference]: Start difference. First operand 18066 states and 55900 transitions. Second operand 7 states. [2019-12-07 16:29:00,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:29:00,636 INFO L93 Difference]: Finished difference Result 23649 states and 71858 transitions. [2019-12-07 16:29:00,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 16:29:00,636 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 34 [2019-12-07 16:29:00,637 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:29:00,662 INFO L225 Difference]: With dead ends: 23649 [2019-12-07 16:29:00,662 INFO L226 Difference]: Without dead ends: 23621 [2019-12-07 16:29:00,663 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 0 SyntacticMatches, 4 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 55 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=81, Invalid=225, Unknown=0, NotChecked=0, Total=306 [2019-12-07 16:29:00,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23621 states. [2019-12-07 16:29:00,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23621 to 16546. [2019-12-07 16:29:00,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16546 states. [2019-12-07 16:29:00,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16546 states to 16546 states and 51456 transitions. [2019-12-07 16:29:00,932 INFO L78 Accepts]: Start accepts. Automaton has 16546 states and 51456 transitions. Word has length 34 [2019-12-07 16:29:00,932 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:29:00,932 INFO L462 AbstractCegarLoop]: Abstraction has 16546 states and 51456 transitions. [2019-12-07 16:29:00,932 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 16:29:00,932 INFO L276 IsEmpty]: Start isEmpty. Operand 16546 states and 51456 transitions. [2019-12-07 16:29:00,944 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 16:29:00,945 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:29:00,945 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:29:00,945 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:29:00,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:29:00,945 INFO L82 PathProgramCache]: Analyzing trace with hash -365129955, now seen corresponding path program 1 times [2019-12-07 16:29:00,945 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:29:00,946 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049314360] [2019-12-07 16:29:00,946 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:29:00,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:29:00,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:29:00,977 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2049314360] [2019-12-07 16:29:00,977 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:29:00,977 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:29:00,978 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1102658207] [2019-12-07 16:29:00,978 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:29:00,978 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:29:00,978 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:29:00,978 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:29:00,978 INFO L87 Difference]: Start difference. First operand 16546 states and 51456 transitions. Second operand 3 states. [2019-12-07 16:29:01,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:29:01,065 INFO L93 Difference]: Finished difference Result 20422 states and 62777 transitions. [2019-12-07 16:29:01,065 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:29:01,065 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 34 [2019-12-07 16:29:01,065 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:29:01,089 INFO L225 Difference]: With dead ends: 20422 [2019-12-07 16:29:01,089 INFO L226 Difference]: Without dead ends: 20422 [2019-12-07 16:29:01,089 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:29:01,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20422 states. [2019-12-07 16:29:01,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20422 to 17925. [2019-12-07 16:29:01,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17925 states. [2019-12-07 16:29:01,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17925 states to 17925 states and 55527 transitions. [2019-12-07 16:29:01,362 INFO L78 Accepts]: Start accepts. Automaton has 17925 states and 55527 transitions. Word has length 34 [2019-12-07 16:29:01,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:29:01,362 INFO L462 AbstractCegarLoop]: Abstraction has 17925 states and 55527 transitions. [2019-12-07 16:29:01,362 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:29:01,362 INFO L276 IsEmpty]: Start isEmpty. Operand 17925 states and 55527 transitions. [2019-12-07 16:29:01,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 16:29:01,374 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:29:01,374 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:29:01,374 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:29:01,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:29:01,374 INFO L82 PathProgramCache]: Analyzing trace with hash -369569775, now seen corresponding path program 1 times [2019-12-07 16:29:01,375 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:29:01,375 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529668835] [2019-12-07 16:29:01,375 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:29:01,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:29:01,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:29:01,522 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1529668835] [2019-12-07 16:29:01,522 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:29:01,522 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:29:01,522 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [771701294] [2019-12-07 16:29:01,522 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:29:01,522 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:29:01,523 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:29:01,523 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:29:01,523 INFO L87 Difference]: Start difference. First operand 17925 states and 55527 transitions. Second operand 6 states. [2019-12-07 16:29:01,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:29:01,721 INFO L93 Difference]: Finished difference Result 24469 states and 75051 transitions. [2019-12-07 16:29:01,721 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 16:29:01,721 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 34 [2019-12-07 16:29:01,722 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:29:01,747 INFO L225 Difference]: With dead ends: 24469 [2019-12-07 16:29:01,747 INFO L226 Difference]: Without dead ends: 22715 [2019-12-07 16:29:01,747 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2019-12-07 16:29:01,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22715 states. [2019-12-07 16:29:02,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22715 to 20030. [2019-12-07 16:29:02,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20030 states. [2019-12-07 16:29:02,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20030 states to 20030 states and 61498 transitions. [2019-12-07 16:29:02,042 INFO L78 Accepts]: Start accepts. Automaton has 20030 states and 61498 transitions. Word has length 34 [2019-12-07 16:29:02,042 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:29:02,042 INFO L462 AbstractCegarLoop]: Abstraction has 20030 states and 61498 transitions. [2019-12-07 16:29:02,042 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:29:02,042 INFO L276 IsEmpty]: Start isEmpty. Operand 20030 states and 61498 transitions. [2019-12-07 16:29:02,057 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-12-07 16:29:02,057 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:29:02,057 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:29:02,057 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:29:02,057 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:29:02,057 INFO L82 PathProgramCache]: Analyzing trace with hash 1754693472, now seen corresponding path program 1 times [2019-12-07 16:29:02,057 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:29:02,058 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [810047541] [2019-12-07 16:29:02,058 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:29:02,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:29:02,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:29:02,081 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [810047541] [2019-12-07 16:29:02,081 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:29:02,081 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:29:02,082 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [378616268] [2019-12-07 16:29:02,082 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:29:02,082 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:29:02,082 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:29:02,082 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:29:02,082 INFO L87 Difference]: Start difference. First operand 20030 states and 61498 transitions. Second operand 3 states. [2019-12-07 16:29:02,149 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:29:02,149 INFO L93 Difference]: Finished difference Result 20890 states and 63222 transitions. [2019-12-07 16:29:02,149 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:29:02,149 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-12-07 16:29:02,150 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:29:02,172 INFO L225 Difference]: With dead ends: 20890 [2019-12-07 16:29:02,172 INFO L226 Difference]: Without dead ends: 20890 [2019-12-07 16:29:02,172 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:29:02,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20890 states. [2019-12-07 16:29:02,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20890 to 18660. [2019-12-07 16:29:02,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18660 states. [2019-12-07 16:29:02,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18660 states to 18660 states and 56880 transitions. [2019-12-07 16:29:02,437 INFO L78 Accepts]: Start accepts. Automaton has 18660 states and 56880 transitions. Word has length 35 [2019-12-07 16:29:02,437 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:29:02,437 INFO L462 AbstractCegarLoop]: Abstraction has 18660 states and 56880 transitions. [2019-12-07 16:29:02,437 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:29:02,437 INFO L276 IsEmpty]: Start isEmpty. Operand 18660 states and 56880 transitions. [2019-12-07 16:29:02,451 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-12-07 16:29:02,451 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:29:02,451 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:29:02,451 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:29:02,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:29:02,451 INFO L82 PathProgramCache]: Analyzing trace with hash 581797047, now seen corresponding path program 1 times [2019-12-07 16:29:02,451 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:29:02,451 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1340066427] [2019-12-07 16:29:02,452 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:29:02,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:29:02,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:29:02,489 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1340066427] [2019-12-07 16:29:02,489 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:29:02,489 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:29:02,489 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [133494256] [2019-12-07 16:29:02,489 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:29:02,489 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:29:02,489 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:29:02,489 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:29:02,490 INFO L87 Difference]: Start difference. First operand 18660 states and 56880 transitions. Second operand 3 states. [2019-12-07 16:29:02,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:29:02,569 INFO L93 Difference]: Finished difference Result 18660 states and 56674 transitions. [2019-12-07 16:29:02,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:29:02,569 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-12-07 16:29:02,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:29:02,589 INFO L225 Difference]: With dead ends: 18660 [2019-12-07 16:29:02,589 INFO L226 Difference]: Without dead ends: 18660 [2019-12-07 16:29:02,590 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:29:02,680 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18660 states. [2019-12-07 16:29:02,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18660 to 18660. [2019-12-07 16:29:02,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18660 states. [2019-12-07 16:29:02,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18660 states to 18660 states and 56674 transitions. [2019-12-07 16:29:02,846 INFO L78 Accepts]: Start accepts. Automaton has 18660 states and 56674 transitions. Word has length 35 [2019-12-07 16:29:02,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:29:02,846 INFO L462 AbstractCegarLoop]: Abstraction has 18660 states and 56674 transitions. [2019-12-07 16:29:02,846 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:29:02,846 INFO L276 IsEmpty]: Start isEmpty. Operand 18660 states and 56674 transitions. [2019-12-07 16:29:02,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-12-07 16:29:02,858 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:29:02,858 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:29:02,858 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:29:02,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:29:02,859 INFO L82 PathProgramCache]: Analyzing trace with hash -44596194, now seen corresponding path program 1 times [2019-12-07 16:29:02,859 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:29:02,859 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1488408880] [2019-12-07 16:29:02,859 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:29:02,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:29:02,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:29:02,889 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1488408880] [2019-12-07 16:29:02,889 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:29:02,889 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:29:02,890 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [276717756] [2019-12-07 16:29:02,890 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:29:02,890 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:29:02,890 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:29:02,890 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:29:02,890 INFO L87 Difference]: Start difference. First operand 18660 states and 56674 transitions. Second operand 4 states. [2019-12-07 16:29:02,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:29:02,904 INFO L93 Difference]: Finished difference Result 2549 states and 5653 transitions. [2019-12-07 16:29:02,904 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 16:29:02,904 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-12-07 16:29:02,904 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:29:02,906 INFO L225 Difference]: With dead ends: 2549 [2019-12-07 16:29:02,906 INFO L226 Difference]: Without dead ends: 2549 [2019-12-07 16:29:02,906 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:29:02,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2549 states. [2019-12-07 16:29:02,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2549 to 2549. [2019-12-07 16:29:02,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2549 states. [2019-12-07 16:29:02,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2549 states to 2549 states and 5653 transitions. [2019-12-07 16:29:02,925 INFO L78 Accepts]: Start accepts. Automaton has 2549 states and 5653 transitions. Word has length 36 [2019-12-07 16:29:02,925 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:29:02,925 INFO L462 AbstractCegarLoop]: Abstraction has 2549 states and 5653 transitions. [2019-12-07 16:29:02,925 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:29:02,925 INFO L276 IsEmpty]: Start isEmpty. Operand 2549 states and 5653 transitions. [2019-12-07 16:29:02,927 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-12-07 16:29:02,927 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:29:02,927 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:29:02,927 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:29:02,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:29:02,927 INFO L82 PathProgramCache]: Analyzing trace with hash -582543129, now seen corresponding path program 1 times [2019-12-07 16:29:02,927 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:29:02,927 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [417558542] [2019-12-07 16:29:02,927 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:29:02,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:29:02,958 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:29:02,959 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [417558542] [2019-12-07 16:29:02,959 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:29:02,959 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:29:02,959 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1918218999] [2019-12-07 16:29:02,959 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:29:02,959 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:29:02,959 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:29:02,960 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:29:02,960 INFO L87 Difference]: Start difference. First operand 2549 states and 5653 transitions. Second operand 5 states. [2019-12-07 16:29:02,974 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:29:02,974 INFO L93 Difference]: Finished difference Result 683 states and 1561 transitions. [2019-12-07 16:29:02,974 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:29:02,974 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 45 [2019-12-07 16:29:02,975 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:29:02,975 INFO L225 Difference]: With dead ends: 683 [2019-12-07 16:29:02,975 INFO L226 Difference]: Without dead ends: 683 [2019-12-07 16:29:02,975 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:29:02,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 683 states. [2019-12-07 16:29:02,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 683 to 627. [2019-12-07 16:29:02,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 627 states. [2019-12-07 16:29:02,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 627 states to 627 states and 1429 transitions. [2019-12-07 16:29:02,981 INFO L78 Accepts]: Start accepts. Automaton has 627 states and 1429 transitions. Word has length 45 [2019-12-07 16:29:02,981 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:29:02,981 INFO L462 AbstractCegarLoop]: Abstraction has 627 states and 1429 transitions. [2019-12-07 16:29:02,981 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:29:02,981 INFO L276 IsEmpty]: Start isEmpty. Operand 627 states and 1429 transitions. [2019-12-07 16:29:02,981 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 16:29:02,981 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:29:02,982 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:29:02,982 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:29:02,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:29:02,982 INFO L82 PathProgramCache]: Analyzing trace with hash -502873348, now seen corresponding path program 1 times [2019-12-07 16:29:02,982 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:29:02,982 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671273505] [2019-12-07 16:29:02,982 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:29:02,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:29:03,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:29:03,029 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1671273505] [2019-12-07 16:29:03,029 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:29:03,030 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:29:03,030 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [874374384] [2019-12-07 16:29:03,030 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:29:03,030 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:29:03,030 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:29:03,030 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:29:03,030 INFO L87 Difference]: Start difference. First operand 627 states and 1429 transitions. Second operand 5 states. [2019-12-07 16:29:03,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:29:03,137 INFO L93 Difference]: Finished difference Result 916 states and 2101 transitions. [2019-12-07 16:29:03,138 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:29:03,138 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2019-12-07 16:29:03,138 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:29:03,139 INFO L225 Difference]: With dead ends: 916 [2019-12-07 16:29:03,139 INFO L226 Difference]: Without dead ends: 916 [2019-12-07 16:29:03,139 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:29:03,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 916 states. [2019-12-07 16:29:03,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 916 to 663. [2019-12-07 16:29:03,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 663 states. [2019-12-07 16:29:03,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 663 states to 663 states and 1521 transitions. [2019-12-07 16:29:03,145 INFO L78 Accepts]: Start accepts. Automaton has 663 states and 1521 transitions. Word has length 56 [2019-12-07 16:29:03,145 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:29:03,145 INFO L462 AbstractCegarLoop]: Abstraction has 663 states and 1521 transitions. [2019-12-07 16:29:03,145 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:29:03,145 INFO L276 IsEmpty]: Start isEmpty. Operand 663 states and 1521 transitions. [2019-12-07 16:29:03,146 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 16:29:03,146 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:29:03,146 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:29:03,146 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:29:03,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:29:03,146 INFO L82 PathProgramCache]: Analyzing trace with hash -916645642, now seen corresponding path program 2 times [2019-12-07 16:29:03,146 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:29:03,146 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328658708] [2019-12-07 16:29:03,147 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:29:03,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:29:03,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:29:03,194 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328658708] [2019-12-07 16:29:03,194 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:29:03,194 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:29:03,194 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [675008706] [2019-12-07 16:29:03,194 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:29:03,194 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:29:03,194 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:29:03,194 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:29:03,194 INFO L87 Difference]: Start difference. First operand 663 states and 1521 transitions. Second operand 3 states. [2019-12-07 16:29:03,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:29:03,205 INFO L93 Difference]: Finished difference Result 639 states and 1431 transitions. [2019-12-07 16:29:03,206 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:29:03,206 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 56 [2019-12-07 16:29:03,206 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:29:03,206 INFO L225 Difference]: With dead ends: 639 [2019-12-07 16:29:03,206 INFO L226 Difference]: Without dead ends: 639 [2019-12-07 16:29:03,207 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:29:03,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 639 states. [2019-12-07 16:29:03,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 639 to 603. [2019-12-07 16:29:03,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 603 states. [2019-12-07 16:29:03,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 603 states to 603 states and 1345 transitions. [2019-12-07 16:29:03,212 INFO L78 Accepts]: Start accepts. Automaton has 603 states and 1345 transitions. Word has length 56 [2019-12-07 16:29:03,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:29:03,212 INFO L462 AbstractCegarLoop]: Abstraction has 603 states and 1345 transitions. [2019-12-07 16:29:03,212 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:29:03,212 INFO L276 IsEmpty]: Start isEmpty. Operand 603 states and 1345 transitions. [2019-12-07 16:29:03,213 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-12-07 16:29:03,213 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:29:03,213 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:29:03,213 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:29:03,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:29:03,213 INFO L82 PathProgramCache]: Analyzing trace with hash -897693906, now seen corresponding path program 1 times [2019-12-07 16:29:03,213 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:29:03,213 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1942643735] [2019-12-07 16:29:03,213 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:29:03,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:29:03,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:29:03,300 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1942643735] [2019-12-07 16:29:03,300 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:29:03,300 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 16:29:03,301 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [115000557] [2019-12-07 16:29:03,301 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 16:29:03,301 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:29:03,301 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 16:29:03,301 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:29:03,301 INFO L87 Difference]: Start difference. First operand 603 states and 1345 transitions. Second operand 7 states. [2019-12-07 16:29:03,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:29:03,382 INFO L93 Difference]: Finished difference Result 1140 states and 2330 transitions. [2019-12-07 16:29:03,382 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 16:29:03,382 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 57 [2019-12-07 16:29:03,382 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:29:03,383 INFO L225 Difference]: With dead ends: 1140 [2019-12-07 16:29:03,383 INFO L226 Difference]: Without dead ends: 761 [2019-12-07 16:29:03,383 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=40, Invalid=70, Unknown=0, NotChecked=0, Total=110 [2019-12-07 16:29:03,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 761 states. [2019-12-07 16:29:03,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 761 to 541. [2019-12-07 16:29:03,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 541 states. [2019-12-07 16:29:03,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 541 states to 541 states and 1166 transitions. [2019-12-07 16:29:03,388 INFO L78 Accepts]: Start accepts. Automaton has 541 states and 1166 transitions. Word has length 57 [2019-12-07 16:29:03,388 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:29:03,388 INFO L462 AbstractCegarLoop]: Abstraction has 541 states and 1166 transitions. [2019-12-07 16:29:03,388 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 16:29:03,389 INFO L276 IsEmpty]: Start isEmpty. Operand 541 states and 1166 transitions. [2019-12-07 16:29:03,389 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-12-07 16:29:03,389 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:29:03,389 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:29:03,390 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:29:03,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:29:03,390 INFO L82 PathProgramCache]: Analyzing trace with hash 704044892, now seen corresponding path program 2 times [2019-12-07 16:29:03,390 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:29:03,390 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1851609798] [2019-12-07 16:29:03,390 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:29:03,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:29:03,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:29:03,474 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1851609798] [2019-12-07 16:29:03,474 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:29:03,474 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:29:03,475 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [342886891] [2019-12-07 16:29:03,475 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:29:03,475 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:29:03,475 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:29:03,475 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:29:03,476 INFO L87 Difference]: Start difference. First operand 541 states and 1166 transitions. Second operand 6 states. [2019-12-07 16:29:03,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:29:03,525 INFO L93 Difference]: Finished difference Result 776 states and 1618 transitions. [2019-12-07 16:29:03,525 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:29:03,525 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 57 [2019-12-07 16:29:03,525 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:29:03,525 INFO L225 Difference]: With dead ends: 776 [2019-12-07 16:29:03,525 INFO L226 Difference]: Without dead ends: 233 [2019-12-07 16:29:03,525 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 16:29:03,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233 states. [2019-12-07 16:29:03,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233 to 209. [2019-12-07 16:29:03,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 209 states. [2019-12-07 16:29:03,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209 states to 209 states and 361 transitions. [2019-12-07 16:29:03,527 INFO L78 Accepts]: Start accepts. Automaton has 209 states and 361 transitions. Word has length 57 [2019-12-07 16:29:03,527 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:29:03,527 INFO L462 AbstractCegarLoop]: Abstraction has 209 states and 361 transitions. [2019-12-07 16:29:03,528 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:29:03,528 INFO L276 IsEmpty]: Start isEmpty. Operand 209 states and 361 transitions. [2019-12-07 16:29:03,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-12-07 16:29:03,528 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:29:03,528 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:29:03,528 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:29:03,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:29:03,528 INFO L82 PathProgramCache]: Analyzing trace with hash -876750572, now seen corresponding path program 3 times [2019-12-07 16:29:03,528 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:29:03,529 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [14028699] [2019-12-07 16:29:03,529 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:29:03,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:29:03,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:29:03,661 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [14028699] [2019-12-07 16:29:03,661 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:29:03,661 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 16:29:03,661 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2039910354] [2019-12-07 16:29:03,661 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 16:29:03,662 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:29:03,662 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 16:29:03,662 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=105, Unknown=0, NotChecked=0, Total=132 [2019-12-07 16:29:03,662 INFO L87 Difference]: Start difference. First operand 209 states and 361 transitions. Second operand 12 states. [2019-12-07 16:29:03,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:29:03,840 INFO L93 Difference]: Finished difference Result 360 states and 604 transitions. [2019-12-07 16:29:03,840 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 16:29:03,841 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 57 [2019-12-07 16:29:03,841 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:29:03,841 INFO L225 Difference]: With dead ends: 360 [2019-12-07 16:29:03,841 INFO L226 Difference]: Without dead ends: 327 [2019-12-07 16:29:03,841 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 43 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=60, Invalid=246, Unknown=0, NotChecked=0, Total=306 [2019-12-07 16:29:03,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states. [2019-12-07 16:29:03,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 317. [2019-12-07 16:29:03,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 317 states. [2019-12-07 16:29:03,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 317 states to 317 states and 546 transitions. [2019-12-07 16:29:03,845 INFO L78 Accepts]: Start accepts. Automaton has 317 states and 546 transitions. Word has length 57 [2019-12-07 16:29:03,845 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:29:03,845 INFO L462 AbstractCegarLoop]: Abstraction has 317 states and 546 transitions. [2019-12-07 16:29:03,845 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 16:29:03,845 INFO L276 IsEmpty]: Start isEmpty. Operand 317 states and 546 transitions. [2019-12-07 16:29:03,845 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-12-07 16:29:03,845 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:29:03,845 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:29:03,845 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:29:03,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:29:03,846 INFO L82 PathProgramCache]: Analyzing trace with hash -1963724718, now seen corresponding path program 4 times [2019-12-07 16:29:03,846 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:29:03,846 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [185294929] [2019-12-07 16:29:03,846 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:29:03,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 16:29:03,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 16:29:03,939 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 16:29:03,939 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 16:29:03,942 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [749] [749] ULTIMATE.startENTRY-->L810: Formula: (let ((.cse0 (store |v_#valid_64| 0 0))) (and (= 0 v_~y$w_buff0~0_225) (= v_~x~0_72 0) (= 0 v_~y$read_delayed_var~0.offset_7) (= v_~y$r_buff0_thd1~0_30 0) (= 0 v_~__unbuffered_cnt~0_82) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1208~0.base_25| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1208~0.base_25|) |v_ULTIMATE.start_main_~#t1208~0.offset_19| 0)) |v_#memory_int_21|) (= v_~y$w_buff1_used~0_382 0) (= |v_#NULL.offset_6| 0) (= v_~y$read_delayed~0_7 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t1208~0.base_25| 1) |v_#valid_62|) (= v_~__unbuffered_p2_EBX~0_120 0) (= 0 v_~y$r_buff1_thd2~0_163) (= v_~y$r_buff1_thd1~0_106 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t1208~0.base_25|) (< 0 |v_#StackHeapBarrier_17|) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1208~0.base_25|)) (= v_~main$tmp_guard0~0_23 0) (= 0 v_~y$r_buff0_thd3~0_195) (= 0 |v_ULTIMATE.start_main_~#t1208~0.offset_19|) (= 0 v_~y$r_buff0_thd2~0_108) (= 0 v_~y$flush_delayed~0_58) (= 0 |v_#NULL.base_6|) (= v_~z~0_106 0) (= 0 v_~y$read_delayed_var~0.base_7) (= v_~y$w_buff1~0_183 0) (= v_~y$mem_tmp~0_20 0) (= 0 v_~__unbuffered_p2_EAX~0_120) (= v_~main$tmp_guard1~0_32 0) (= 0 v_~weak$$choice0~0_16) (= v_~a~0_45 0) (= (store |v_#length_24| |v_ULTIMATE.start_main_~#t1208~0.base_25| 4) |v_#length_23|) (= v_~y~0_155 0) (= 0 v_~y$r_buff1_thd3~0_156) (= v_~y$r_buff0_thd0~0_325 0) (= v_~weak$$choice2~0_108 0) (= v_~y$r_buff1_thd0~0_281 0) (= v_~y$w_buff0_used~0_625 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_22|, #length=|v_#length_24|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_37|, ULTIMATE.start_main_~#t1210~0.base=|v_ULTIMATE.start_main_~#t1210~0.base_25|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_22|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_28|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_45|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_26|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_45|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ~a~0=v_~a~0_45, ~y$mem_tmp~0=v_~y$mem_tmp~0_20, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_156, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_30, ULTIMATE.start_main_~#t1210~0.offset=|v_ULTIMATE.start_main_~#t1210~0.offset_19|, ~y$flush_delayed~0=v_~y$flush_delayed~0_58, #length=|v_#length_23|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_120, ULTIMATE.start_main_~#t1208~0.offset=|v_ULTIMATE.start_main_~#t1208~0.offset_19|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_120, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_26|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_30|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_24|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_37|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_38|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_48|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_68|, ~weak$$choice0~0=v_~weak$$choice0~0_16, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_26|, ~y$w_buff1~0=v_~y$w_buff1~0_183, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_108, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_8|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_22|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_82, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_281, ~x~0=v_~x~0_72, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_625, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_41|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_67|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_28|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_106|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_33|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_38|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_53|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_106, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_24|, ~y$w_buff0~0=v_~y$w_buff0~0_225, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_195, ~y~0=v_~y~0_155, ULTIMATE.start_main_~#t1209~0.offset=|v_ULTIMATE.start_main_~#t1209~0.offset_19|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_28|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_24|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_33|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_47|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_48|, ULTIMATE.start_main_~#t1209~0.base=|v_ULTIMATE.start_main_~#t1209~0.base_25|, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_29|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_163, ULTIMATE.start_main_~#t1208~0.base=|v_ULTIMATE.start_main_~#t1208~0.base_25|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_36|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_325, #valid=|v_#valid_62|, #memory_int=|v_#memory_int_21|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_8|, ~z~0=v_~z~0_106, ~weak$$choice2~0=v_~weak$$choice2~0_108, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_382} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1210~0.base, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~a~0, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ULTIMATE.start_main_~#t1210~0.offset, ~y$flush_delayed~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t1208~0.offset, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_~#t1209~0.offset, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_~#t1209~0.base, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_~#t1208~0.base, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 16:29:03,942 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [718] [718] L810-1-->L812: Formula: (and (= |v_#valid_42| (store |v_#valid_43| |v_ULTIMATE.start_main_~#t1209~0.base_13| 1)) (= (store |v_#length_18| |v_ULTIMATE.start_main_~#t1209~0.base_13| 4) |v_#length_17|) (not (= |v_ULTIMATE.start_main_~#t1209~0.base_13| 0)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1209~0.base_13|) (= 0 (select |v_#valid_43| |v_ULTIMATE.start_main_~#t1209~0.base_13|)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1209~0.base_13| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1209~0.base_13|) |v_ULTIMATE.start_main_~#t1209~0.offset_11| 1)) |v_#memory_int_15|) (= 0 |v_ULTIMATE.start_main_~#t1209~0.offset_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_43|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t1209~0.offset=|v_ULTIMATE.start_main_~#t1209~0.offset_11|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_42|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1209~0.base=|v_ULTIMATE.start_main_~#t1209~0.base_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1209~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t1209~0.base] because there is no mapped edge [2019-12-07 16:29:03,943 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [717] [717] L812-1-->L814: Formula: (and (= |v_ULTIMATE.start_main_~#t1210~0.offset_11| 0) (= |v_#valid_40| (store |v_#valid_41| |v_ULTIMATE.start_main_~#t1210~0.base_13| 1)) (not (= |v_ULTIMATE.start_main_~#t1210~0.base_13| 0)) (= 0 (select |v_#valid_41| |v_ULTIMATE.start_main_~#t1210~0.base_13|)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1210~0.base_13| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1210~0.base_13|) |v_ULTIMATE.start_main_~#t1210~0.offset_11| 2)) |v_#memory_int_13|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t1210~0.base_13|) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1210~0.base_13| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t1210~0.base=|v_ULTIMATE.start_main_~#t1210~0.base_13|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t1210~0.offset=|v_ULTIMATE.start_main_~#t1210~0.offset_11|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1210~0.base, #valid, #memory_int, ULTIMATE.start_main_~#t1210~0.offset, ULTIMATE.start_main_#t~nondet16, #length] because there is no mapped edge [2019-12-07 16:29:03,943 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [634] [634] P2ENTRY-->L4-3: Formula: (and (= |v_P2Thread1of1ForFork0_#in~arg.base_12| v_P2Thread1of1ForFork0_~arg.base_10) (= |v_P2Thread1of1ForFork0_#in~arg.offset_12| v_P2Thread1of1ForFork0_~arg.offset_10) (= v_~y$w_buff0~0_33 v_~y$w_buff1~0_29) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_12)) (= v_~y$w_buff0_used~0_130 1) (= (ite (not (and (not (= (mod v_~y$w_buff0_used~0_130 256) 0)) (not (= 0 (mod v_~y$w_buff1_used~0_75 256))))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_10|) (= 2 v_~y$w_buff0~0_32) (= v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_12 |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_10|) (= v_~y$w_buff1_used~0_75 v_~y$w_buff0_used~0_131)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_12|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_131, ~y$w_buff0~0=v_~y$w_buff0~0_33, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_12|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_10, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_12|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_10|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_130, ~y$w_buff1~0=v_~y$w_buff1~0_29, ~y$w_buff0~0=v_~y$w_buff0~0_32, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_10, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_12|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_12, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_75} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 16:29:03,943 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] P0ENTRY-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_71 1) v_~__unbuffered_cnt~0_70) (= 0 |v_P0Thread1of1ForFork1_#res.offset_7|) (= |v_P0Thread1of1ForFork1_#in~arg.base_15| v_P0Thread1of1ForFork1_~arg.base_13) (= v_~a~0_29 1) (= v_P0Thread1of1ForFork1_~arg.offset_13 |v_P0Thread1of1ForFork1_#in~arg.offset_15|) (= v_~x~0_52 1) (= 0 |v_P0Thread1of1ForFork1_#res.base_7|)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_15|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_71, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_15|} OutVars{~a~0=v_~a~0_29, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_7|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_15|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_7|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_13, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_70, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_15|, ~x~0=v_~x~0_52, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_13} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~x~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-12-07 16:29:03,945 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L788-->L788-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In1666267821 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In1666267821 256)))) (or (and (= 0 |P2Thread1of1ForFork0_#t~ite11_Out1666267821|) (not .cse0) (not .cse1)) (and (= ~y$w_buff0_used~0_In1666267821 |P2Thread1of1ForFork0_#t~ite11_Out1666267821|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1666267821, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1666267821} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1666267821, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out1666267821|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1666267821} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 16:29:03,945 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] L789-->L789-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In1452030553 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In1452030553 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1452030553 256))) (.cse3 (= 0 (mod ~y$r_buff1_thd3~0_In1452030553 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff1_used~0_In1452030553 |P2Thread1of1ForFork0_#t~ite12_Out1452030553|) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite12_Out1452030553|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1452030553, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1452030553, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1452030553, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1452030553} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1452030553, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1452030553, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out1452030553|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1452030553, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1452030553} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 16:29:03,945 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L790-->L791: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In869018788 256))) (.cse2 (= ~y$r_buff0_thd3~0_In869018788 ~y$r_buff0_thd3~0_Out869018788)) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In869018788 256)))) (or (and (= 0 ~y$r_buff0_thd3~0_Out869018788) (not .cse0) (not .cse1)) (and .cse2 .cse0) (and .cse2 .cse1))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In869018788, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In869018788} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In869018788, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out869018788, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out869018788|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 16:29:03,945 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L791-->L791-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd3~0_In1112231753 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1112231753 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In1112231753 256))) (.cse1 (= (mod ~y$r_buff0_thd3~0_In1112231753 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite14_Out1112231753| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P2Thread1of1ForFork0_#t~ite14_Out1112231753| ~y$r_buff1_thd3~0_In1112231753) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1112231753, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1112231753, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1112231753, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1112231753} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out1112231753|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1112231753, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1112231753, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1112231753, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1112231753} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 16:29:03,946 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [706] [706] L791-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= v_~__unbuffered_cnt~0_54 (+ v_~__unbuffered_cnt~0_55 1)) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_26| v_~y$r_buff1_thd3~0_94)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_25|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_94, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 16:29:03,946 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [698] [698] L752-2-->L752-4: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In1449172342 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd2~0_In1449172342 256) 0))) (or (and (= ~y~0_In1449172342 |P1Thread1of1ForFork2_#t~ite3_Out1449172342|) (or .cse0 .cse1)) (and (= |P1Thread1of1ForFork2_#t~ite3_Out1449172342| ~y$w_buff1~0_In1449172342) (not .cse1) (not .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1449172342, ~y$w_buff1~0=~y$w_buff1~0_In1449172342, ~y~0=~y~0_In1449172342, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1449172342} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1449172342, ~y$w_buff1~0=~y$w_buff1~0_In1449172342, ~y~0=~y~0_In1449172342, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out1449172342|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1449172342} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 16:29:03,946 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [629] [629] L752-4-->L753: Formula: (= v_~y~0_39 |v_P1Thread1of1ForFork2_#t~ite3_6|) InVars {P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_6|} OutVars{P1Thread1of1ForFork2_#t~ite4=|v_P1Thread1of1ForFork2_#t~ite4_7|, ~y~0=v_~y~0_39, P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_5|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, ~y~0, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 16:29:03,946 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L753-->L753-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1533216479 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In-1533216479 256)))) (or (and (not .cse0) (= 0 |P1Thread1of1ForFork2_#t~ite5_Out-1533216479|) (not .cse1)) (and (or .cse1 .cse0) (= ~y$w_buff0_used~0_In-1533216479 |P1Thread1of1ForFork2_#t~ite5_Out-1533216479|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1533216479, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1533216479} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1533216479, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1533216479, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out-1533216479|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 16:29:03,946 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L754-->L754-2: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In514739465 256) 0)) (.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In514739465 256))) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In514739465 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In514739465 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P1Thread1of1ForFork2_#t~ite6_Out514739465| ~y$w_buff1_used~0_In514739465)) (and (= |P1Thread1of1ForFork2_#t~ite6_Out514739465| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In514739465, ~y$w_buff0_used~0=~y$w_buff0_used~0_In514739465, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In514739465, ~y$w_buff1_used~0=~y$w_buff1_used~0_In514739465} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In514739465, ~y$w_buff0_used~0=~y$w_buff0_used~0_In514739465, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In514739465, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out514739465|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In514739465} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 16:29:03,947 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [696] [696] L755-->L755-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1992459920 256))) (.cse0 (= (mod ~y$r_buff0_thd2~0_In-1992459920 256) 0))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork2_#t~ite7_Out-1992459920| 0)) (and (= ~y$r_buff0_thd2~0_In-1992459920 |P1Thread1of1ForFork2_#t~ite7_Out-1992459920|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1992459920, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1992459920} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1992459920, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1992459920, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out-1992459920|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 16:29:03,947 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L756-->L756-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In-2123501806 256))) (.cse1 (= (mod ~y$r_buff1_thd2~0_In-2123501806 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In-2123501806 256))) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In-2123501806 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~y$r_buff1_thd2~0_In-2123501806 |P1Thread1of1ForFork2_#t~ite8_Out-2123501806|)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite8_Out-2123501806|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2123501806, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2123501806, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2123501806, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2123501806} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2123501806, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2123501806, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out-2123501806|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2123501806, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2123501806} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 16:29:03,947 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L756-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_61 1) v_~__unbuffered_cnt~0_60) (= |v_P1Thread1of1ForFork2_#t~ite8_28| v_~y$r_buff1_thd2~0_111)) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_28|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_61} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_111, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_27|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_60, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 16:29:03,947 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [661] [661] L814-1-->L820: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_11 256))) (= v_~main$tmp_guard0~0_11 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_28) 1 0) 0) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_28} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_28, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_10|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_11} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 16:29:03,947 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L820-2-->L820-5: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd0~0_In130559500 256))) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In130559500 256))) (.cse2 (= |ULTIMATE.start_main_#t~ite19_Out130559500| |ULTIMATE.start_main_#t~ite18_Out130559500|))) (or (and (= |ULTIMATE.start_main_#t~ite18_Out130559500| ~y~0_In130559500) (or .cse0 .cse1) .cse2) (and (= |ULTIMATE.start_main_#t~ite18_Out130559500| ~y$w_buff1~0_In130559500) (not .cse1) (not .cse0) .cse2))) InVars {~y$w_buff1~0=~y$w_buff1~0_In130559500, ~y~0=~y~0_In130559500, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In130559500, ~y$w_buff1_used~0=~y$w_buff1_used~0_In130559500} OutVars{~y$w_buff1~0=~y$w_buff1~0_In130559500, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out130559500|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out130559500|, ~y~0=~y~0_In130559500, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In130559500, ~y$w_buff1_used~0=~y$w_buff1_used~0_In130559500} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 16:29:03,948 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L821-->L821-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-216339353 256))) (.cse0 (= (mod ~y$r_buff0_thd0~0_In-216339353 256) 0))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite20_Out-216339353| 0) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite20_Out-216339353| ~y$w_buff0_used~0_In-216339353) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-216339353, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-216339353} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-216339353, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-216339353, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-216339353|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 16:29:03,948 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [695] [695] L822-->L822-2: Formula: (let ((.cse2 (= (mod ~y$r_buff0_thd0~0_In-47123031 256) 0)) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In-47123031 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-47123031 256) 0)) (.cse1 (= 0 (mod ~y$r_buff1_thd0~0_In-47123031 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite21_Out-47123031| ~y$w_buff1_used~0_In-47123031) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1))) (= |ULTIMATE.start_main_#t~ite21_Out-47123031| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-47123031, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-47123031, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-47123031, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-47123031} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-47123031, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-47123031, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-47123031|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-47123031, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-47123031} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 16:29:03,948 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L823-->L823-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In1765631419 256))) (.cse1 (= (mod ~y$r_buff0_thd0~0_In1765631419 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite22_Out1765631419|)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite22_Out1765631419| ~y$r_buff0_thd0~0_In1765631419)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1765631419, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1765631419} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1765631419, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1765631419, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1765631419|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 16:29:03,949 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L824-->L824-2: Formula: (let ((.cse2 (= (mod ~y$w_buff1_used~0_In1894438945 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd0~0_In1894438945 256))) (.cse0 (= (mod ~y$r_buff0_thd0~0_In1894438945 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In1894438945 256) 0))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd0~0_In1894438945 |ULTIMATE.start_main_#t~ite23_Out1894438945|) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1))) (= 0 |ULTIMATE.start_main_#t~ite23_Out1894438945|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1894438945, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1894438945, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1894438945, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1894438945} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1894438945, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1894438945, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1894438945, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out1894438945|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1894438945} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 16:29:03,950 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [733] [733] L833-->L833-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-1662870181 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite33_Out-1662870181| |ULTIMATE.start_main_#t~ite32_Out-1662870181|) .cse0 (= |ULTIMATE.start_main_#t~ite32_Out-1662870181| ~y$w_buff1~0_In-1662870181) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-1662870181 256) 0))) (or (= (mod ~y$w_buff0_used~0_In-1662870181 256) 0) (and .cse1 (= (mod ~y$w_buff1_used~0_In-1662870181 256) 0)) (and .cse1 (= 0 (mod ~y$r_buff1_thd0~0_In-1662870181 256)))))) (and (not .cse0) (= |ULTIMATE.start_main_#t~ite32_In-1662870181| |ULTIMATE.start_main_#t~ite32_Out-1662870181|) (= |ULTIMATE.start_main_#t~ite33_Out-1662870181| ~y$w_buff1~0_In-1662870181)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1662870181, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1662870181, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1662870181, ~weak$$choice2~0=~weak$$choice2~0_In-1662870181, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1662870181, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_In-1662870181|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1662870181} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1662870181, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1662870181, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1662870181, ~weak$$choice2~0=~weak$$choice2~0_In-1662870181, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_Out-1662870181|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1662870181, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out-1662870181|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1662870181} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_#t~ite33] because there is no mapped edge [2019-12-07 16:29:03,950 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [734] [734] L834-->L834-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-558944640 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite35_In-558944640| |ULTIMATE.start_main_#t~ite35_Out-558944640|) (= |ULTIMATE.start_main_#t~ite36_Out-558944640| ~y$w_buff0_used~0_In-558944640)) (and (= ~y$w_buff0_used~0_In-558944640 |ULTIMATE.start_main_#t~ite35_Out-558944640|) .cse0 (= |ULTIMATE.start_main_#t~ite36_Out-558944640| |ULTIMATE.start_main_#t~ite35_Out-558944640|) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-558944640 256)))) (or (and (= 0 (mod ~y$r_buff1_thd0~0_In-558944640 256)) .cse1) (and (= 0 (mod ~y$w_buff1_used~0_In-558944640 256)) .cse1) (= (mod ~y$w_buff0_used~0_In-558944640 256) 0)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-558944640, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-558944640, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_In-558944640|, ~weak$$choice2~0=~weak$$choice2~0_In-558944640, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-558944640, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-558944640} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-558944640, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-558944640, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_Out-558944640|, ULTIMATE.start_main_#t~ite36=|ULTIMATE.start_main_#t~ite36_Out-558944640|, ~weak$$choice2~0=~weak$$choice2~0_In-558944640, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-558944640, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-558944640} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36] because there is no mapped edge [2019-12-07 16:29:03,950 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [732] [732] L835-->L835-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In2024720771 256)))) (or (and (= |ULTIMATE.start_main_#t~ite38_In2024720771| |ULTIMATE.start_main_#t~ite38_Out2024720771|) (not .cse0) (= |ULTIMATE.start_main_#t~ite39_Out2024720771| ~y$w_buff1_used~0_In2024720771)) (and (= |ULTIMATE.start_main_#t~ite39_Out2024720771| |ULTIMATE.start_main_#t~ite38_Out2024720771|) (= ~y$w_buff1_used~0_In2024720771 |ULTIMATE.start_main_#t~ite38_Out2024720771|) .cse0 (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In2024720771 256) 0))) (or (= 0 (mod ~y$w_buff0_used~0_In2024720771 256)) (and .cse1 (= (mod ~y$w_buff1_used~0_In2024720771 256) 0)) (and (= (mod ~y$r_buff1_thd0~0_In2024720771 256) 0) .cse1)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In2024720771, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In2024720771, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_In2024720771|, ~weak$$choice2~0=~weak$$choice2~0_In2024720771, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In2024720771, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2024720771} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In2024720771, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out2024720771|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In2024720771, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out2024720771|, ~weak$$choice2~0=~weak$$choice2~0_In2024720771, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In2024720771, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2024720771} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38] because there is no mapped edge [2019-12-07 16:29:03,951 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [665] [665] L836-->L837: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_29 256))) (= v_~y$r_buff0_thd0~0_100 v_~y$r_buff0_thd0~0_99)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_100, ~weak$$choice2~0=v_~weak$$choice2~0_29} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_13|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_8|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_99, ~weak$$choice2~0=v_~weak$$choice2~0_29, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 16:29:03,951 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [731] [731] L839-->L4: Formula: (and (= v_~y~0_138 v_~y$mem_tmp~0_17) (= (mod v_~main$tmp_guard1~0_23 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|) (= 0 v_~y$flush_delayed~0_52) (not (= (mod v_~y$flush_delayed~0_53 256) 0))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_17, ~y$flush_delayed~0=v_~y$flush_delayed~0_53, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_17, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_12, ~y$flush_delayed~0=v_~y$flush_delayed~0_52, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_60|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~y~0=v_~y~0_138, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 16:29:03,951 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [726] [726] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 16:29:04,015 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 04:29:04 BasicIcfg [2019-12-07 16:29:04,015 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 16:29:04,016 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 16:29:04,016 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 16:29:04,016 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 16:29:04,016 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:28:51" (3/4) ... [2019-12-07 16:29:04,018 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 16:29:04,018 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [749] [749] ULTIMATE.startENTRY-->L810: Formula: (let ((.cse0 (store |v_#valid_64| 0 0))) (and (= 0 v_~y$w_buff0~0_225) (= v_~x~0_72 0) (= 0 v_~y$read_delayed_var~0.offset_7) (= v_~y$r_buff0_thd1~0_30 0) (= 0 v_~__unbuffered_cnt~0_82) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1208~0.base_25| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1208~0.base_25|) |v_ULTIMATE.start_main_~#t1208~0.offset_19| 0)) |v_#memory_int_21|) (= v_~y$w_buff1_used~0_382 0) (= |v_#NULL.offset_6| 0) (= v_~y$read_delayed~0_7 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t1208~0.base_25| 1) |v_#valid_62|) (= v_~__unbuffered_p2_EBX~0_120 0) (= 0 v_~y$r_buff1_thd2~0_163) (= v_~y$r_buff1_thd1~0_106 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t1208~0.base_25|) (< 0 |v_#StackHeapBarrier_17|) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1208~0.base_25|)) (= v_~main$tmp_guard0~0_23 0) (= 0 v_~y$r_buff0_thd3~0_195) (= 0 |v_ULTIMATE.start_main_~#t1208~0.offset_19|) (= 0 v_~y$r_buff0_thd2~0_108) (= 0 v_~y$flush_delayed~0_58) (= 0 |v_#NULL.base_6|) (= v_~z~0_106 0) (= 0 v_~y$read_delayed_var~0.base_7) (= v_~y$w_buff1~0_183 0) (= v_~y$mem_tmp~0_20 0) (= 0 v_~__unbuffered_p2_EAX~0_120) (= v_~main$tmp_guard1~0_32 0) (= 0 v_~weak$$choice0~0_16) (= v_~a~0_45 0) (= (store |v_#length_24| |v_ULTIMATE.start_main_~#t1208~0.base_25| 4) |v_#length_23|) (= v_~y~0_155 0) (= 0 v_~y$r_buff1_thd3~0_156) (= v_~y$r_buff0_thd0~0_325 0) (= v_~weak$$choice2~0_108 0) (= v_~y$r_buff1_thd0~0_281 0) (= v_~y$w_buff0_used~0_625 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_22|, #length=|v_#length_24|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_37|, ULTIMATE.start_main_~#t1210~0.base=|v_ULTIMATE.start_main_~#t1210~0.base_25|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_22|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_28|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_45|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_26|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_45|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ~a~0=v_~a~0_45, ~y$mem_tmp~0=v_~y$mem_tmp~0_20, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_156, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_30, ULTIMATE.start_main_~#t1210~0.offset=|v_ULTIMATE.start_main_~#t1210~0.offset_19|, ~y$flush_delayed~0=v_~y$flush_delayed~0_58, #length=|v_#length_23|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_120, ULTIMATE.start_main_~#t1208~0.offset=|v_ULTIMATE.start_main_~#t1208~0.offset_19|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_120, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_26|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_30|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_24|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_37|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_38|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_48|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_68|, ~weak$$choice0~0=v_~weak$$choice0~0_16, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_26|, ~y$w_buff1~0=v_~y$w_buff1~0_183, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_108, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_8|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_22|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_82, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_281, ~x~0=v_~x~0_72, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_625, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_41|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_67|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_28|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_106|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_33|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_38|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_53|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_106, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_24|, ~y$w_buff0~0=v_~y$w_buff0~0_225, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_195, ~y~0=v_~y~0_155, ULTIMATE.start_main_~#t1209~0.offset=|v_ULTIMATE.start_main_~#t1209~0.offset_19|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_28|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_24|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_33|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_47|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_48|, ULTIMATE.start_main_~#t1209~0.base=|v_ULTIMATE.start_main_~#t1209~0.base_25|, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_29|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_163, ULTIMATE.start_main_~#t1208~0.base=|v_ULTIMATE.start_main_~#t1208~0.base_25|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_36|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_325, #valid=|v_#valid_62|, #memory_int=|v_#memory_int_21|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_8|, ~z~0=v_~z~0_106, ~weak$$choice2~0=v_~weak$$choice2~0_108, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_382} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1210~0.base, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~a~0, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ULTIMATE.start_main_~#t1210~0.offset, ~y$flush_delayed~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t1208~0.offset, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_~#t1209~0.offset, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_~#t1209~0.base, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_~#t1208~0.base, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 16:29:04,019 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [718] [718] L810-1-->L812: Formula: (and (= |v_#valid_42| (store |v_#valid_43| |v_ULTIMATE.start_main_~#t1209~0.base_13| 1)) (= (store |v_#length_18| |v_ULTIMATE.start_main_~#t1209~0.base_13| 4) |v_#length_17|) (not (= |v_ULTIMATE.start_main_~#t1209~0.base_13| 0)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1209~0.base_13|) (= 0 (select |v_#valid_43| |v_ULTIMATE.start_main_~#t1209~0.base_13|)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1209~0.base_13| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1209~0.base_13|) |v_ULTIMATE.start_main_~#t1209~0.offset_11| 1)) |v_#memory_int_15|) (= 0 |v_ULTIMATE.start_main_~#t1209~0.offset_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_43|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t1209~0.offset=|v_ULTIMATE.start_main_~#t1209~0.offset_11|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_42|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1209~0.base=|v_ULTIMATE.start_main_~#t1209~0.base_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1209~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t1209~0.base] because there is no mapped edge [2019-12-07 16:29:04,019 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [717] [717] L812-1-->L814: Formula: (and (= |v_ULTIMATE.start_main_~#t1210~0.offset_11| 0) (= |v_#valid_40| (store |v_#valid_41| |v_ULTIMATE.start_main_~#t1210~0.base_13| 1)) (not (= |v_ULTIMATE.start_main_~#t1210~0.base_13| 0)) (= 0 (select |v_#valid_41| |v_ULTIMATE.start_main_~#t1210~0.base_13|)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1210~0.base_13| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1210~0.base_13|) |v_ULTIMATE.start_main_~#t1210~0.offset_11| 2)) |v_#memory_int_13|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t1210~0.base_13|) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1210~0.base_13| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t1210~0.base=|v_ULTIMATE.start_main_~#t1210~0.base_13|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t1210~0.offset=|v_ULTIMATE.start_main_~#t1210~0.offset_11|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1210~0.base, #valid, #memory_int, ULTIMATE.start_main_~#t1210~0.offset, ULTIMATE.start_main_#t~nondet16, #length] because there is no mapped edge [2019-12-07 16:29:04,019 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [634] [634] P2ENTRY-->L4-3: Formula: (and (= |v_P2Thread1of1ForFork0_#in~arg.base_12| v_P2Thread1of1ForFork0_~arg.base_10) (= |v_P2Thread1of1ForFork0_#in~arg.offset_12| v_P2Thread1of1ForFork0_~arg.offset_10) (= v_~y$w_buff0~0_33 v_~y$w_buff1~0_29) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_12)) (= v_~y$w_buff0_used~0_130 1) (= (ite (not (and (not (= (mod v_~y$w_buff0_used~0_130 256) 0)) (not (= 0 (mod v_~y$w_buff1_used~0_75 256))))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_10|) (= 2 v_~y$w_buff0~0_32) (= v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_12 |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_10|) (= v_~y$w_buff1_used~0_75 v_~y$w_buff0_used~0_131)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_12|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_131, ~y$w_buff0~0=v_~y$w_buff0~0_33, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_12|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_10, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_12|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_10|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_130, ~y$w_buff1~0=v_~y$w_buff1~0_29, ~y$w_buff0~0=v_~y$w_buff0~0_32, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_10, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_12|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_12, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_75} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 16:29:04,020 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] P0ENTRY-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_71 1) v_~__unbuffered_cnt~0_70) (= 0 |v_P0Thread1of1ForFork1_#res.offset_7|) (= |v_P0Thread1of1ForFork1_#in~arg.base_15| v_P0Thread1of1ForFork1_~arg.base_13) (= v_~a~0_29 1) (= v_P0Thread1of1ForFork1_~arg.offset_13 |v_P0Thread1of1ForFork1_#in~arg.offset_15|) (= v_~x~0_52 1) (= 0 |v_P0Thread1of1ForFork1_#res.base_7|)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_15|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_71, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_15|} OutVars{~a~0=v_~a~0_29, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_7|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_15|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_7|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_13, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_70, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_15|, ~x~0=v_~x~0_52, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_13} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~x~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-12-07 16:29:04,021 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L788-->L788-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In1666267821 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In1666267821 256)))) (or (and (= 0 |P2Thread1of1ForFork0_#t~ite11_Out1666267821|) (not .cse0) (not .cse1)) (and (= ~y$w_buff0_used~0_In1666267821 |P2Thread1of1ForFork0_#t~ite11_Out1666267821|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1666267821, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1666267821} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1666267821, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out1666267821|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1666267821} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 16:29:04,021 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] L789-->L789-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In1452030553 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In1452030553 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1452030553 256))) (.cse3 (= 0 (mod ~y$r_buff1_thd3~0_In1452030553 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff1_used~0_In1452030553 |P2Thread1of1ForFork0_#t~ite12_Out1452030553|) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite12_Out1452030553|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1452030553, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1452030553, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1452030553, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1452030553} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1452030553, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1452030553, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out1452030553|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1452030553, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1452030553} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 16:29:04,022 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L790-->L791: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In869018788 256))) (.cse2 (= ~y$r_buff0_thd3~0_In869018788 ~y$r_buff0_thd3~0_Out869018788)) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In869018788 256)))) (or (and (= 0 ~y$r_buff0_thd3~0_Out869018788) (not .cse0) (not .cse1)) (and .cse2 .cse0) (and .cse2 .cse1))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In869018788, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In869018788} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In869018788, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out869018788, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out869018788|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 16:29:04,022 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L791-->L791-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd3~0_In1112231753 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1112231753 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In1112231753 256))) (.cse1 (= (mod ~y$r_buff0_thd3~0_In1112231753 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite14_Out1112231753| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P2Thread1of1ForFork0_#t~ite14_Out1112231753| ~y$r_buff1_thd3~0_In1112231753) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1112231753, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1112231753, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1112231753, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1112231753} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out1112231753|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1112231753, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1112231753, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1112231753, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1112231753} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 16:29:04,022 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [706] [706] L791-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= v_~__unbuffered_cnt~0_54 (+ v_~__unbuffered_cnt~0_55 1)) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_26| v_~y$r_buff1_thd3~0_94)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_25|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_94, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 16:29:04,022 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [698] [698] L752-2-->L752-4: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In1449172342 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd2~0_In1449172342 256) 0))) (or (and (= ~y~0_In1449172342 |P1Thread1of1ForFork2_#t~ite3_Out1449172342|) (or .cse0 .cse1)) (and (= |P1Thread1of1ForFork2_#t~ite3_Out1449172342| ~y$w_buff1~0_In1449172342) (not .cse1) (not .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1449172342, ~y$w_buff1~0=~y$w_buff1~0_In1449172342, ~y~0=~y~0_In1449172342, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1449172342} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1449172342, ~y$w_buff1~0=~y$w_buff1~0_In1449172342, ~y~0=~y~0_In1449172342, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out1449172342|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1449172342} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 16:29:04,022 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [629] [629] L752-4-->L753: Formula: (= v_~y~0_39 |v_P1Thread1of1ForFork2_#t~ite3_6|) InVars {P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_6|} OutVars{P1Thread1of1ForFork2_#t~ite4=|v_P1Thread1of1ForFork2_#t~ite4_7|, ~y~0=v_~y~0_39, P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_5|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, ~y~0, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 16:29:04,023 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L753-->L753-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1533216479 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In-1533216479 256)))) (or (and (not .cse0) (= 0 |P1Thread1of1ForFork2_#t~ite5_Out-1533216479|) (not .cse1)) (and (or .cse1 .cse0) (= ~y$w_buff0_used~0_In-1533216479 |P1Thread1of1ForFork2_#t~ite5_Out-1533216479|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1533216479, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1533216479} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1533216479, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1533216479, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out-1533216479|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 16:29:04,023 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L754-->L754-2: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In514739465 256) 0)) (.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In514739465 256))) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In514739465 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In514739465 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P1Thread1of1ForFork2_#t~ite6_Out514739465| ~y$w_buff1_used~0_In514739465)) (and (= |P1Thread1of1ForFork2_#t~ite6_Out514739465| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In514739465, ~y$w_buff0_used~0=~y$w_buff0_used~0_In514739465, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In514739465, ~y$w_buff1_used~0=~y$w_buff1_used~0_In514739465} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In514739465, ~y$w_buff0_used~0=~y$w_buff0_used~0_In514739465, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In514739465, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out514739465|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In514739465} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 16:29:04,023 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [696] [696] L755-->L755-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1992459920 256))) (.cse0 (= (mod ~y$r_buff0_thd2~0_In-1992459920 256) 0))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork2_#t~ite7_Out-1992459920| 0)) (and (= ~y$r_buff0_thd2~0_In-1992459920 |P1Thread1of1ForFork2_#t~ite7_Out-1992459920|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1992459920, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1992459920} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1992459920, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1992459920, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out-1992459920|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 16:29:04,024 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L756-->L756-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In-2123501806 256))) (.cse1 (= (mod ~y$r_buff1_thd2~0_In-2123501806 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In-2123501806 256))) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In-2123501806 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~y$r_buff1_thd2~0_In-2123501806 |P1Thread1of1ForFork2_#t~ite8_Out-2123501806|)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite8_Out-2123501806|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2123501806, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2123501806, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2123501806, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2123501806} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2123501806, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2123501806, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out-2123501806|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2123501806, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2123501806} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 16:29:04,024 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L756-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_61 1) v_~__unbuffered_cnt~0_60) (= |v_P1Thread1of1ForFork2_#t~ite8_28| v_~y$r_buff1_thd2~0_111)) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_28|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_61} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_111, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_27|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_60, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 16:29:04,024 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [661] [661] L814-1-->L820: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_11 256))) (= v_~main$tmp_guard0~0_11 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_28) 1 0) 0) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_28} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_28, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_10|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_11} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 16:29:04,025 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L820-2-->L820-5: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd0~0_In130559500 256))) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In130559500 256))) (.cse2 (= |ULTIMATE.start_main_#t~ite19_Out130559500| |ULTIMATE.start_main_#t~ite18_Out130559500|))) (or (and (= |ULTIMATE.start_main_#t~ite18_Out130559500| ~y~0_In130559500) (or .cse0 .cse1) .cse2) (and (= |ULTIMATE.start_main_#t~ite18_Out130559500| ~y$w_buff1~0_In130559500) (not .cse1) (not .cse0) .cse2))) InVars {~y$w_buff1~0=~y$w_buff1~0_In130559500, ~y~0=~y~0_In130559500, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In130559500, ~y$w_buff1_used~0=~y$w_buff1_used~0_In130559500} OutVars{~y$w_buff1~0=~y$w_buff1~0_In130559500, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out130559500|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out130559500|, ~y~0=~y~0_In130559500, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In130559500, ~y$w_buff1_used~0=~y$w_buff1_used~0_In130559500} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 16:29:04,025 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L821-->L821-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-216339353 256))) (.cse0 (= (mod ~y$r_buff0_thd0~0_In-216339353 256) 0))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite20_Out-216339353| 0) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite20_Out-216339353| ~y$w_buff0_used~0_In-216339353) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-216339353, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-216339353} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-216339353, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-216339353, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-216339353|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 16:29:04,025 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [695] [695] L822-->L822-2: Formula: (let ((.cse2 (= (mod ~y$r_buff0_thd0~0_In-47123031 256) 0)) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In-47123031 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-47123031 256) 0)) (.cse1 (= 0 (mod ~y$r_buff1_thd0~0_In-47123031 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite21_Out-47123031| ~y$w_buff1_used~0_In-47123031) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1))) (= |ULTIMATE.start_main_#t~ite21_Out-47123031| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-47123031, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-47123031, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-47123031, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-47123031} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-47123031, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-47123031, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-47123031|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-47123031, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-47123031} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 16:29:04,026 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L823-->L823-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In1765631419 256))) (.cse1 (= (mod ~y$r_buff0_thd0~0_In1765631419 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite22_Out1765631419|)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite22_Out1765631419| ~y$r_buff0_thd0~0_In1765631419)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1765631419, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1765631419} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1765631419, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1765631419, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1765631419|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 16:29:04,026 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L824-->L824-2: Formula: (let ((.cse2 (= (mod ~y$w_buff1_used~0_In1894438945 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd0~0_In1894438945 256))) (.cse0 (= (mod ~y$r_buff0_thd0~0_In1894438945 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In1894438945 256) 0))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd0~0_In1894438945 |ULTIMATE.start_main_#t~ite23_Out1894438945|) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1))) (= 0 |ULTIMATE.start_main_#t~ite23_Out1894438945|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1894438945, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1894438945, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1894438945, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1894438945} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1894438945, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1894438945, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1894438945, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out1894438945|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1894438945} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 16:29:04,028 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [733] [733] L833-->L833-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-1662870181 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite33_Out-1662870181| |ULTIMATE.start_main_#t~ite32_Out-1662870181|) .cse0 (= |ULTIMATE.start_main_#t~ite32_Out-1662870181| ~y$w_buff1~0_In-1662870181) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-1662870181 256) 0))) (or (= (mod ~y$w_buff0_used~0_In-1662870181 256) 0) (and .cse1 (= (mod ~y$w_buff1_used~0_In-1662870181 256) 0)) (and .cse1 (= 0 (mod ~y$r_buff1_thd0~0_In-1662870181 256)))))) (and (not .cse0) (= |ULTIMATE.start_main_#t~ite32_In-1662870181| |ULTIMATE.start_main_#t~ite32_Out-1662870181|) (= |ULTIMATE.start_main_#t~ite33_Out-1662870181| ~y$w_buff1~0_In-1662870181)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1662870181, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1662870181, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1662870181, ~weak$$choice2~0=~weak$$choice2~0_In-1662870181, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1662870181, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_In-1662870181|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1662870181} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1662870181, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1662870181, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1662870181, ~weak$$choice2~0=~weak$$choice2~0_In-1662870181, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_Out-1662870181|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1662870181, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out-1662870181|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1662870181} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_#t~ite33] because there is no mapped edge [2019-12-07 16:29:04,029 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [734] [734] L834-->L834-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-558944640 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite35_In-558944640| |ULTIMATE.start_main_#t~ite35_Out-558944640|) (= |ULTIMATE.start_main_#t~ite36_Out-558944640| ~y$w_buff0_used~0_In-558944640)) (and (= ~y$w_buff0_used~0_In-558944640 |ULTIMATE.start_main_#t~ite35_Out-558944640|) .cse0 (= |ULTIMATE.start_main_#t~ite36_Out-558944640| |ULTIMATE.start_main_#t~ite35_Out-558944640|) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-558944640 256)))) (or (and (= 0 (mod ~y$r_buff1_thd0~0_In-558944640 256)) .cse1) (and (= 0 (mod ~y$w_buff1_used~0_In-558944640 256)) .cse1) (= (mod ~y$w_buff0_used~0_In-558944640 256) 0)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-558944640, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-558944640, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_In-558944640|, ~weak$$choice2~0=~weak$$choice2~0_In-558944640, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-558944640, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-558944640} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-558944640, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-558944640, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_Out-558944640|, ULTIMATE.start_main_#t~ite36=|ULTIMATE.start_main_#t~ite36_Out-558944640|, ~weak$$choice2~0=~weak$$choice2~0_In-558944640, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-558944640, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-558944640} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36] because there is no mapped edge [2019-12-07 16:29:04,029 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [732] [732] L835-->L835-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In2024720771 256)))) (or (and (= |ULTIMATE.start_main_#t~ite38_In2024720771| |ULTIMATE.start_main_#t~ite38_Out2024720771|) (not .cse0) (= |ULTIMATE.start_main_#t~ite39_Out2024720771| ~y$w_buff1_used~0_In2024720771)) (and (= |ULTIMATE.start_main_#t~ite39_Out2024720771| |ULTIMATE.start_main_#t~ite38_Out2024720771|) (= ~y$w_buff1_used~0_In2024720771 |ULTIMATE.start_main_#t~ite38_Out2024720771|) .cse0 (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In2024720771 256) 0))) (or (= 0 (mod ~y$w_buff0_used~0_In2024720771 256)) (and .cse1 (= (mod ~y$w_buff1_used~0_In2024720771 256) 0)) (and (= (mod ~y$r_buff1_thd0~0_In2024720771 256) 0) .cse1)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In2024720771, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In2024720771, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_In2024720771|, ~weak$$choice2~0=~weak$$choice2~0_In2024720771, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In2024720771, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2024720771} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In2024720771, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out2024720771|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In2024720771, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out2024720771|, ~weak$$choice2~0=~weak$$choice2~0_In2024720771, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In2024720771, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2024720771} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38] because there is no mapped edge [2019-12-07 16:29:04,030 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [665] [665] L836-->L837: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_29 256))) (= v_~y$r_buff0_thd0~0_100 v_~y$r_buff0_thd0~0_99)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_100, ~weak$$choice2~0=v_~weak$$choice2~0_29} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_13|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_8|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_99, ~weak$$choice2~0=v_~weak$$choice2~0_29, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 16:29:04,030 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [731] [731] L839-->L4: Formula: (and (= v_~y~0_138 v_~y$mem_tmp~0_17) (= (mod v_~main$tmp_guard1~0_23 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|) (= 0 v_~y$flush_delayed~0_52) (not (= (mod v_~y$flush_delayed~0_53 256) 0))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_17, ~y$flush_delayed~0=v_~y$flush_delayed~0_53, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_17, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_12, ~y$flush_delayed~0=v_~y$flush_delayed~0_52, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_60|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~y~0=v_~y~0_138, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 16:29:04,030 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [726] [726] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 16:29:04,089 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_c7de1eab-0a2f-4fa4-af55-d5f0060903d0/bin/uautomizer/witness.graphml [2019-12-07 16:29:04,089 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 16:29:04,090 INFO L168 Benchmark]: Toolchain (without parser) took 13124.81 ms. Allocated memory was 1.0 GB in the beginning and 1.9 GB in the end (delta: 890.2 MB). Free memory was 943.6 MB in the beginning and 1.0 GB in the end (delta: -92.7 MB). Peak memory consumption was 797.5 MB. Max. memory is 11.5 GB. [2019-12-07 16:29:04,090 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 964.0 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 16:29:04,091 INFO L168 Benchmark]: CACSL2BoogieTranslator took 370.54 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 94.4 MB). Free memory was 943.6 MB in the beginning and 1.1 GB in the end (delta: -120.0 MB). Peak memory consumption was 18.6 MB. Max. memory is 11.5 GB. [2019-12-07 16:29:04,091 INFO L168 Benchmark]: Boogie Procedure Inliner took 39.89 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 16:29:04,091 INFO L168 Benchmark]: Boogie Preprocessor took 25.05 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 16:29:04,091 INFO L168 Benchmark]: RCFGBuilder took 382.53 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 54.6 MB). Peak memory consumption was 54.6 MB. Max. memory is 11.5 GB. [2019-12-07 16:29:04,092 INFO L168 Benchmark]: TraceAbstraction took 12229.81 ms. Allocated memory was 1.1 GB in the beginning and 1.9 GB in the end (delta: 795.9 MB). Free memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: -58.3 MB). Peak memory consumption was 737.6 MB. Max. memory is 11.5 GB. [2019-12-07 16:29:04,092 INFO L168 Benchmark]: Witness Printer took 73.72 ms. Allocated memory is still 1.9 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 25.6 MB). Peak memory consumption was 25.6 MB. Max. memory is 11.5 GB. [2019-12-07 16:29:04,094 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 964.0 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 370.54 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 94.4 MB). Free memory was 943.6 MB in the beginning and 1.1 GB in the end (delta: -120.0 MB). Peak memory consumption was 18.6 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 39.89 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 25.05 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 382.53 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 54.6 MB). Peak memory consumption was 54.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 12229.81 ms. Allocated memory was 1.1 GB in the beginning and 1.9 GB in the end (delta: 795.9 MB). Free memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: -58.3 MB). Peak memory consumption was 737.6 MB. Max. memory is 11.5 GB. * Witness Printer took 73.72 ms. Allocated memory is still 1.9 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 25.6 MB). Peak memory consumption was 25.6 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 2.9s, 164 ProgramPointsBefore, 82 ProgramPointsAfterwards, 195 TransitionsBefore, 91 TransitionsAfterwards, 11490 CoEnabledTransitionPairs, 7 FixpointIterations, 33 TrivialSequentialCompositions, 42 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 39 ConcurrentYvCompositions, 26 ChoiceCompositions, 4376 VarBasedMoverChecksPositive, 193 VarBasedMoverChecksNegative, 58 SemBasedMoverChecksPositive, 191 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.6s, 0 MoverChecksTotal, 46792 CheckedPairsTotal, 114 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L810] FCALL, FORK 0 pthread_create(&t1208, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L812] FCALL, FORK 0 pthread_create(&t1209, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L814] FCALL, FORK 0 pthread_create(&t1210, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L771] 3 y$r_buff1_thd0 = y$r_buff0_thd0 [L772] 3 y$r_buff1_thd1 = y$r_buff0_thd1 [L773] 3 y$r_buff1_thd2 = y$r_buff0_thd2 [L774] 3 y$r_buff1_thd3 = y$r_buff0_thd3 [L775] 3 y$r_buff0_thd3 = (_Bool)1 [L778] 3 z = 1 [L781] 3 __unbuffered_p2_EAX = z [L784] 3 __unbuffered_p2_EBX = a VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L787] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L746] 2 x = 2 [L749] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L787] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L788] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L789] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L752] 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L753] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L754] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L755] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L820] EXPR 0 y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L820] 0 y = y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L821] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L822] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L823] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L824] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L827] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L828] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L829] 0 y$flush_delayed = weak$$choice2 [L830] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L831] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L831] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L832] EXPR 0 weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L832] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L833] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L834] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L835] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L837] EXPR 0 weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L837] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L838] 0 main$tmp_guard1 = !(x == 2 && y == 2 && __unbuffered_p2_EAX == 1 && __unbuffered_p2_EBX == 0) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 155 locations, 2 error locations. Result: UNSAFE, OverallTime: 12.0s, OverallIterations: 19, TraceHistogramMax: 1, AutomataDifference: 3.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 2126 SDtfs, 2169 SDslu, 4446 SDs, 0 SdLazy, 2287 SolverSat, 144 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 125 GetRequests, 19 SyntacticMatches, 12 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 127 ImplicationChecksByTransitivity, 0.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=22284occurred in iteration=2, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 3.3s AutomataMinimizationTime, 18 MinimizatonAttempts, 24759 StatesRemovedByMinimization, 14 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 0.9s InterpolantComputationTime, 688 NumberOfCodeBlocks, 688 NumberOfCodeBlocksAsserted, 19 NumberOfCheckSat, 613 ConstructedInterpolants, 0 QuantifiedInterpolants, 122564 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 18 InterpolantComputations, 18 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...