./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix047_tso.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_261dc733-82d1-4812-b451-301b6bcff852/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_261dc733-82d1-4812-b451-301b6bcff852/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_261dc733-82d1-4812-b451-301b6bcff852/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_261dc733-82d1-4812-b451-301b6bcff852/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix047_tso.oepc.i -s /tmp/vcloud-vcloud-master/worker/run_dir_261dc733-82d1-4812-b451-301b6bcff852/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_261dc733-82d1-4812-b451-301b6bcff852/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash fa598112c7541c99c974bc00db13a3884a17db5b ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:47:23,457 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:47:23,459 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:47:23,466 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:47:23,466 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:47:23,467 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:47:23,468 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:47:23,469 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:47:23,470 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:47:23,471 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:47:23,472 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:47:23,472 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:47:23,473 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:47:23,473 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:47:23,474 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:47:23,475 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:47:23,475 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:47:23,476 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:47:23,477 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:47:23,479 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:47:23,480 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:47:23,480 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:47:23,481 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:47:23,481 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:47:23,483 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:47:23,483 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:47:23,483 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:47:23,484 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:47:23,484 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:47:23,485 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:47:23,485 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:47:23,485 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:47:23,486 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:47:23,486 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:47:23,487 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:47:23,487 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:47:23,487 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:47:23,487 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:47:23,487 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:47:23,488 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:47:23,488 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:47:23,489 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_261dc733-82d1-4812-b451-301b6bcff852/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 18:47:23,498 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:47:23,498 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:47:23,499 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:47:23,499 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:47:23,499 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:47:23,500 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:47:23,500 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:47:23,500 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:47:23,500 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:47:23,500 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:47:23,500 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 18:47:23,500 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 18:47:23,501 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 18:47:23,501 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:47:23,501 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:47:23,501 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:47:23,501 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 18:47:23,501 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:47:23,501 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:47:23,501 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 18:47:23,502 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 18:47:23,502 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:47:23,502 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:47:23,502 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 18:47:23,502 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 18:47:23,502 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:47:23,502 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 18:47:23,502 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 18:47:23,502 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:47:23,503 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_261dc733-82d1-4812-b451-301b6bcff852/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> fa598112c7541c99c974bc00db13a3884a17db5b [2019-12-07 18:47:23,605 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:47:23,612 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:47:23,615 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:47:23,615 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:47:23,616 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:47:23,616 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_261dc733-82d1-4812-b451-301b6bcff852/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix047_tso.oepc.i [2019-12-07 18:47:23,652 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_261dc733-82d1-4812-b451-301b6bcff852/bin/uautomizer/data/2017270c1/08c1923b920c461ca67c95975483f001/FLAGdc11a2462 [2019-12-07 18:47:24,127 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:47:24,127 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_261dc733-82d1-4812-b451-301b6bcff852/sv-benchmarks/c/pthread-wmm/mix047_tso.oepc.i [2019-12-07 18:47:24,137 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_261dc733-82d1-4812-b451-301b6bcff852/bin/uautomizer/data/2017270c1/08c1923b920c461ca67c95975483f001/FLAGdc11a2462 [2019-12-07 18:47:24,147 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_261dc733-82d1-4812-b451-301b6bcff852/bin/uautomizer/data/2017270c1/08c1923b920c461ca67c95975483f001 [2019-12-07 18:47:24,149 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:47:24,149 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:47:24,150 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:47:24,150 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:47:24,152 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:47:24,153 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:47:24" (1/1) ... [2019-12-07 18:47:24,155 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3f8fae9c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:24, skipping insertion in model container [2019-12-07 18:47:24,155 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:47:24" (1/1) ... [2019-12-07 18:47:24,160 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:47:24,187 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:47:24,434 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:47:24,442 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:47:24,485 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:47:24,531 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:47:24,531 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:24 WrapperNode [2019-12-07 18:47:24,531 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:47:24,532 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:47:24,532 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:47:24,532 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:47:24,537 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:24" (1/1) ... [2019-12-07 18:47:24,550 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:24" (1/1) ... [2019-12-07 18:47:24,573 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:47:24,574 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:47:24,574 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:47:24,574 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:47:24,580 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:24" (1/1) ... [2019-12-07 18:47:24,580 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:24" (1/1) ... [2019-12-07 18:47:24,584 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:24" (1/1) ... [2019-12-07 18:47:24,584 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:24" (1/1) ... [2019-12-07 18:47:24,591 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:24" (1/1) ... [2019-12-07 18:47:24,594 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:24" (1/1) ... [2019-12-07 18:47:24,596 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:24" (1/1) ... [2019-12-07 18:47:24,599 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:47:24,600 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:47:24,600 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:47:24,600 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:47:24,601 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:24" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_261dc733-82d1-4812-b451-301b6bcff852/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:47:24,641 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 18:47:24,641 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 18:47:24,641 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 18:47:24,641 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 18:47:24,641 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 18:47:24,641 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 18:47:24,641 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 18:47:24,641 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 18:47:24,642 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 18:47:24,642 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 18:47:24,642 INFO L130 BoogieDeclarations]: Found specification of procedure P3 [2019-12-07 18:47:24,642 INFO L138 BoogieDeclarations]: Found implementation of procedure P3 [2019-12-07 18:47:24,642 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 18:47:24,642 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:47:24,642 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:47:24,643 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 18:47:25,011 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:47:25,011 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 18:47:25,012 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:47:25 BoogieIcfgContainer [2019-12-07 18:47:25,012 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:47:25,013 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 18:47:25,013 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 18:47:25,015 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 18:47:25,016 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 06:47:24" (1/3) ... [2019-12-07 18:47:25,016 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@610ed7d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:47:25, skipping insertion in model container [2019-12-07 18:47:25,016 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:24" (2/3) ... [2019-12-07 18:47:25,016 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@610ed7d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:47:25, skipping insertion in model container [2019-12-07 18:47:25,017 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:47:25" (3/3) ... [2019-12-07 18:47:25,018 INFO L109 eAbstractionObserver]: Analyzing ICFG mix047_tso.oepc.i [2019-12-07 18:47:25,024 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 18:47:25,025 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 18:47:25,030 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 18:47:25,031 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 18:47:25,057 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,057 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,057 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,057 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,058 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,058 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,058 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,058 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,058 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,058 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,058 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,058 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,059 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,059 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,059 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,059 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,059 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,059 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,059 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,060 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,060 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,060 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,060 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,060 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,060 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,060 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,060 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,061 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,061 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,061 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,061 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,061 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,061 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,061 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,062 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,062 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,062 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,062 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,062 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,062 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,063 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,063 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,063 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,064 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,064 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,064 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,064 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,064 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,064 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,064 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork3___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,065 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,065 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,065 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,065 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,065 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,065 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,065 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,065 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,066 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,066 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,066 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,066 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,066 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,066 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,066 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,066 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,067 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,067 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,067 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,067 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,067 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,067 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,068 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,068 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,068 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,068 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork3_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:25,084 INFO L249 AbstractCegarLoop]: Starting to check reachability of 7 error locations. [2019-12-07 18:47:25,100 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 18:47:25,101 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 18:47:25,101 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 18:47:25,101 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:47:25,101 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:47:25,101 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 18:47:25,101 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:47:25,101 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 18:47:25,113 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 180 places, 208 transitions [2019-12-07 18:47:25,114 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 180 places, 208 transitions [2019-12-07 18:47:25,176 INFO L134 PetriNetUnfolder]: 41/204 cut-off events. [2019-12-07 18:47:25,176 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:47:25,186 INFO L76 FinitePrefix]: Finished finitePrefix Result has 217 conditions, 204 events. 41/204 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 480 event pairs. 12/173 useless extension candidates. Maximal degree in co-relation 172. Up to 2 conditions per place. [2019-12-07 18:47:25,199 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 180 places, 208 transitions [2019-12-07 18:47:25,232 INFO L134 PetriNetUnfolder]: 41/204 cut-off events. [2019-12-07 18:47:25,233 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:47:25,238 INFO L76 FinitePrefix]: Finished finitePrefix Result has 217 conditions, 204 events. 41/204 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 480 event pairs. 12/173 useless extension candidates. Maximal degree in co-relation 172. Up to 2 conditions per place. [2019-12-07 18:47:25,252 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 12668 [2019-12-07 18:47:25,253 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 18:47:28,141 WARN L192 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 97 DAG size of output: 95 [2019-12-07 18:47:28,262 INFO L206 etLargeBlockEncoding]: Checked pairs total: 49999 [2019-12-07 18:47:28,263 INFO L214 etLargeBlockEncoding]: Total number of compositions: 122 [2019-12-07 18:47:28,265 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 89 places, 95 transitions [2019-12-07 18:47:30,183 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 34566 states. [2019-12-07 18:47:30,185 INFO L276 IsEmpty]: Start isEmpty. Operand 34566 states. [2019-12-07 18:47:30,189 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2019-12-07 18:47:30,189 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:30,190 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:30,190 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:30,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:30,194 INFO L82 PathProgramCache]: Analyzing trace with hash -1471654446, now seen corresponding path program 1 times [2019-12-07 18:47:30,199 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:30,199 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1340233590] [2019-12-07 18:47:30,199 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:30,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:30,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:30,370 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1340233590] [2019-12-07 18:47:30,370 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:30,371 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:47:30,371 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1058220441] [2019-12-07 18:47:30,374 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:47:30,374 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:30,383 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:47:30,384 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:47:30,385 INFO L87 Difference]: Start difference. First operand 34566 states. Second operand 3 states. [2019-12-07 18:47:30,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:30,724 INFO L93 Difference]: Finished difference Result 34366 states and 145616 transitions. [2019-12-07 18:47:30,725 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:47:30,726 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 9 [2019-12-07 18:47:30,726 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:30,945 INFO L225 Difference]: With dead ends: 34366 [2019-12-07 18:47:30,945 INFO L226 Difference]: Without dead ends: 33638 [2019-12-07 18:47:30,946 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:47:31,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33638 states. [2019-12-07 18:47:31,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33638 to 33638. [2019-12-07 18:47:31,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33638 states. [2019-12-07 18:47:31,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33638 states to 33638 states and 142648 transitions. [2019-12-07 18:47:31,957 INFO L78 Accepts]: Start accepts. Automaton has 33638 states and 142648 transitions. Word has length 9 [2019-12-07 18:47:31,957 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:31,958 INFO L462 AbstractCegarLoop]: Abstraction has 33638 states and 142648 transitions. [2019-12-07 18:47:31,958 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:47:31,958 INFO L276 IsEmpty]: Start isEmpty. Operand 33638 states and 142648 transitions. [2019-12-07 18:47:31,963 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 18:47:31,963 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:31,963 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:31,964 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:31,964 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:31,964 INFO L82 PathProgramCache]: Analyzing trace with hash 1198985017, now seen corresponding path program 1 times [2019-12-07 18:47:31,964 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:31,964 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345499051] [2019-12-07 18:47:31,964 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:31,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:32,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:32,027 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1345499051] [2019-12-07 18:47:32,027 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:32,028 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:47:32,028 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2135192742] [2019-12-07 18:47:32,029 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:47:32,029 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:32,029 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:47:32,029 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:47:32,029 INFO L87 Difference]: Start difference. First operand 33638 states and 142648 transitions. Second operand 4 states. [2019-12-07 18:47:32,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:32,522 INFO L93 Difference]: Finished difference Result 52350 states and 214824 transitions. [2019-12-07 18:47:32,523 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:47:32,523 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 18:47:32,523 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:32,675 INFO L225 Difference]: With dead ends: 52350 [2019-12-07 18:47:32,675 INFO L226 Difference]: Without dead ends: 52322 [2019-12-07 18:47:32,675 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:47:32,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52322 states. [2019-12-07 18:47:33,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52322 to 47746. [2019-12-07 18:47:33,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47746 states. [2019-12-07 18:47:33,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47746 states to 47746 states and 197744 transitions. [2019-12-07 18:47:33,848 INFO L78 Accepts]: Start accepts. Automaton has 47746 states and 197744 transitions. Word has length 15 [2019-12-07 18:47:33,848 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:33,848 INFO L462 AbstractCegarLoop]: Abstraction has 47746 states and 197744 transitions. [2019-12-07 18:47:33,848 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:47:33,848 INFO L276 IsEmpty]: Start isEmpty. Operand 47746 states and 197744 transitions. [2019-12-07 18:47:33,850 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 18:47:33,850 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:33,850 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:33,850 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:33,851 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:33,851 INFO L82 PathProgramCache]: Analyzing trace with hash -633584, now seen corresponding path program 1 times [2019-12-07 18:47:33,851 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:33,851 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1795402382] [2019-12-07 18:47:33,851 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:33,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:33,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:33,899 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1795402382] [2019-12-07 18:47:33,899 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:33,899 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:47:33,899 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869440609] [2019-12-07 18:47:33,899 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:47:33,899 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:33,899 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:47:33,900 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:47:33,900 INFO L87 Difference]: Start difference. First operand 47746 states and 197744 transitions. Second operand 4 states. [2019-12-07 18:47:34,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:34,371 INFO L93 Difference]: Finished difference Result 59254 states and 242916 transitions. [2019-12-07 18:47:34,372 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:47:34,372 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 18:47:34,372 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:34,515 INFO L225 Difference]: With dead ends: 59254 [2019-12-07 18:47:34,515 INFO L226 Difference]: Without dead ends: 59254 [2019-12-07 18:47:34,515 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:47:34,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59254 states. [2019-12-07 18:47:35,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59254 to 52846. [2019-12-07 18:47:35,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52846 states. [2019-12-07 18:47:35,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52846 states to 52846 states and 218200 transitions. [2019-12-07 18:47:35,783 INFO L78 Accepts]: Start accepts. Automaton has 52846 states and 218200 transitions. Word has length 15 [2019-12-07 18:47:35,784 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:35,784 INFO L462 AbstractCegarLoop]: Abstraction has 52846 states and 218200 transitions. [2019-12-07 18:47:35,784 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:47:35,784 INFO L276 IsEmpty]: Start isEmpty. Operand 52846 states and 218200 transitions. [2019-12-07 18:47:35,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 18:47:35,796 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:35,796 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:35,796 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:35,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:35,797 INFO L82 PathProgramCache]: Analyzing trace with hash 254508137, now seen corresponding path program 1 times [2019-12-07 18:47:35,797 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:35,797 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1762914832] [2019-12-07 18:47:35,797 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:35,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:35,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:35,876 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1762914832] [2019-12-07 18:47:35,876 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:35,876 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:47:35,876 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1204910583] [2019-12-07 18:47:35,877 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:47:35,877 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:35,877 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:47:35,877 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:47:35,877 INFO L87 Difference]: Start difference. First operand 52846 states and 218200 transitions. Second operand 5 states. [2019-12-07 18:47:36,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:36,379 INFO L93 Difference]: Finished difference Result 70826 states and 287832 transitions. [2019-12-07 18:47:36,379 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:47:36,380 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2019-12-07 18:47:36,380 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:36,537 INFO L225 Difference]: With dead ends: 70826 [2019-12-07 18:47:36,538 INFO L226 Difference]: Without dead ends: 70798 [2019-12-07 18:47:36,538 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:47:37,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70798 states. [2019-12-07 18:47:37,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70798 to 52914. [2019-12-07 18:47:37,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52914 states. [2019-12-07 18:47:37,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52914 states to 52914 states and 218104 transitions. [2019-12-07 18:47:37,889 INFO L78 Accepts]: Start accepts. Automaton has 52914 states and 218104 transitions. Word has length 21 [2019-12-07 18:47:37,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:37,889 INFO L462 AbstractCegarLoop]: Abstraction has 52914 states and 218104 transitions. [2019-12-07 18:47:37,889 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:47:37,889 INFO L276 IsEmpty]: Start isEmpty. Operand 52914 states and 218104 transitions. [2019-12-07 18:47:38,082 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-12-07 18:47:38,083 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:38,083 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:38,083 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:38,083 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:38,083 INFO L82 PathProgramCache]: Analyzing trace with hash 1007840852, now seen corresponding path program 1 times [2019-12-07 18:47:38,083 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:38,083 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1939296658] [2019-12-07 18:47:38,084 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:38,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:38,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:38,118 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1939296658] [2019-12-07 18:47:38,118 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:38,118 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:47:38,118 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1564582062] [2019-12-07 18:47:38,118 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:47:38,119 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:38,119 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:47:38,119 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:47:38,119 INFO L87 Difference]: Start difference. First operand 52914 states and 218104 transitions. Second operand 3 states. [2019-12-07 18:47:38,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:38,256 INFO L93 Difference]: Finished difference Result 41543 states and 158120 transitions. [2019-12-07 18:47:38,256 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:47:38,256 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 29 [2019-12-07 18:47:38,257 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:38,337 INFO L225 Difference]: With dead ends: 41543 [2019-12-07 18:47:38,337 INFO L226 Difference]: Without dead ends: 41543 [2019-12-07 18:47:38,337 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:47:38,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41543 states. [2019-12-07 18:47:39,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41543 to 41543. [2019-12-07 18:47:39,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41543 states. [2019-12-07 18:47:39,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41543 states to 41543 states and 158120 transitions. [2019-12-07 18:47:39,125 INFO L78 Accepts]: Start accepts. Automaton has 41543 states and 158120 transitions. Word has length 29 [2019-12-07 18:47:39,125 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:39,125 INFO L462 AbstractCegarLoop]: Abstraction has 41543 states and 158120 transitions. [2019-12-07 18:47:39,125 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:47:39,126 INFO L276 IsEmpty]: Start isEmpty. Operand 41543 states and 158120 transitions. [2019-12-07 18:47:39,149 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2019-12-07 18:47:39,150 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:39,150 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:39,150 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:39,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:39,150 INFO L82 PathProgramCache]: Analyzing trace with hash -1153771889, now seen corresponding path program 1 times [2019-12-07 18:47:39,150 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:39,150 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184110658] [2019-12-07 18:47:39,150 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:39,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:39,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:39,196 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [184110658] [2019-12-07 18:47:39,196 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:39,196 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:47:39,196 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1628071123] [2019-12-07 18:47:39,197 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:47:39,197 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:39,197 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:47:39,197 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:47:39,197 INFO L87 Difference]: Start difference. First operand 41543 states and 158120 transitions. Second operand 4 states. [2019-12-07 18:47:39,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:39,252 INFO L93 Difference]: Finished difference Result 17329 states and 54594 transitions. [2019-12-07 18:47:39,252 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:47:39,252 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 30 [2019-12-07 18:47:39,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:39,274 INFO L225 Difference]: With dead ends: 17329 [2019-12-07 18:47:39,274 INFO L226 Difference]: Without dead ends: 17329 [2019-12-07 18:47:39,274 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:47:39,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17329 states. [2019-12-07 18:47:39,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17329 to 17329. [2019-12-07 18:47:39,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17329 states. [2019-12-07 18:47:39,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17329 states to 17329 states and 54594 transitions. [2019-12-07 18:47:39,531 INFO L78 Accepts]: Start accepts. Automaton has 17329 states and 54594 transitions. Word has length 30 [2019-12-07 18:47:39,531 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:39,531 INFO L462 AbstractCegarLoop]: Abstraction has 17329 states and 54594 transitions. [2019-12-07 18:47:39,532 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:47:39,532 INFO L276 IsEmpty]: Start isEmpty. Operand 17329 states and 54594 transitions. [2019-12-07 18:47:39,540 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 18:47:39,540 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:39,540 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:39,541 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:39,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:39,541 INFO L82 PathProgramCache]: Analyzing trace with hash 2070972968, now seen corresponding path program 1 times [2019-12-07 18:47:39,541 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:39,541 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856914878] [2019-12-07 18:47:39,541 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:39,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:39,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:39,584 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856914878] [2019-12-07 18:47:39,584 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:39,584 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:47:39,584 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1603023693] [2019-12-07 18:47:39,584 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:47:39,584 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:39,584 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:47:39,585 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:47:39,585 INFO L87 Difference]: Start difference. First operand 17329 states and 54594 transitions. Second operand 5 states. [2019-12-07 18:47:39,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:39,607 INFO L93 Difference]: Finished difference Result 2957 states and 7512 transitions. [2019-12-07 18:47:39,607 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:47:39,607 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 31 [2019-12-07 18:47:39,607 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:39,610 INFO L225 Difference]: With dead ends: 2957 [2019-12-07 18:47:39,610 INFO L226 Difference]: Without dead ends: 2957 [2019-12-07 18:47:39,610 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:47:39,615 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2957 states. [2019-12-07 18:47:39,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2957 to 2957. [2019-12-07 18:47:39,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2957 states. [2019-12-07 18:47:39,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2957 states to 2957 states and 7512 transitions. [2019-12-07 18:47:39,638 INFO L78 Accepts]: Start accepts. Automaton has 2957 states and 7512 transitions. Word has length 31 [2019-12-07 18:47:39,638 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:39,638 INFO L462 AbstractCegarLoop]: Abstraction has 2957 states and 7512 transitions. [2019-12-07 18:47:39,638 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:47:39,638 INFO L276 IsEmpty]: Start isEmpty. Operand 2957 states and 7512 transitions. [2019-12-07 18:47:39,642 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2019-12-07 18:47:39,643 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:39,643 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:39,643 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:39,643 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:39,643 INFO L82 PathProgramCache]: Analyzing trace with hash -1919926116, now seen corresponding path program 1 times [2019-12-07 18:47:39,643 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:39,643 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1342378651] [2019-12-07 18:47:39,643 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:39,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:39,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:39,694 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1342378651] [2019-12-07 18:47:39,694 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:39,694 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:47:39,694 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [26530220] [2019-12-07 18:47:39,695 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:47:39,695 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:39,695 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:47:39,695 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:47:39,695 INFO L87 Difference]: Start difference. First operand 2957 states and 7512 transitions. Second operand 6 states. [2019-12-07 18:47:39,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:39,728 INFO L93 Difference]: Finished difference Result 1371 states and 3902 transitions. [2019-12-07 18:47:39,729 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:47:39,729 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 43 [2019-12-07 18:47:39,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:39,731 INFO L225 Difference]: With dead ends: 1371 [2019-12-07 18:47:39,731 INFO L226 Difference]: Without dead ends: 1371 [2019-12-07 18:47:39,731 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:47:39,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1371 states. [2019-12-07 18:47:39,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1371 to 1231. [2019-12-07 18:47:39,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1231 states. [2019-12-07 18:47:39,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1231 states to 1231 states and 3502 transitions. [2019-12-07 18:47:39,749 INFO L78 Accepts]: Start accepts. Automaton has 1231 states and 3502 transitions. Word has length 43 [2019-12-07 18:47:39,749 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:39,749 INFO L462 AbstractCegarLoop]: Abstraction has 1231 states and 3502 transitions. [2019-12-07 18:47:39,749 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:47:39,749 INFO L276 IsEmpty]: Start isEmpty. Operand 1231 states and 3502 transitions. [2019-12-07 18:47:39,751 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 18:47:39,751 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:39,751 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:39,751 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:39,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:39,751 INFO L82 PathProgramCache]: Analyzing trace with hash 593702588, now seen corresponding path program 1 times [2019-12-07 18:47:39,751 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:39,751 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [583478363] [2019-12-07 18:47:39,751 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:39,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:39,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:39,789 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [583478363] [2019-12-07 18:47:39,789 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:39,789 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:47:39,789 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1223826895] [2019-12-07 18:47:39,789 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:47:39,789 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:39,789 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:47:39,790 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:47:39,790 INFO L87 Difference]: Start difference. First operand 1231 states and 3502 transitions. Second operand 3 states. [2019-12-07 18:47:39,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:39,816 INFO L93 Difference]: Finished difference Result 1239 states and 3510 transitions. [2019-12-07 18:47:39,817 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:47:39,817 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 58 [2019-12-07 18:47:39,817 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:39,819 INFO L225 Difference]: With dead ends: 1239 [2019-12-07 18:47:39,819 INFO L226 Difference]: Without dead ends: 1239 [2019-12-07 18:47:39,819 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:47:39,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1239 states. [2019-12-07 18:47:39,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1239 to 1234. [2019-12-07 18:47:39,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1234 states. [2019-12-07 18:47:39,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1234 states to 1234 states and 3505 transitions. [2019-12-07 18:47:39,837 INFO L78 Accepts]: Start accepts. Automaton has 1234 states and 3505 transitions. Word has length 58 [2019-12-07 18:47:39,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:39,838 INFO L462 AbstractCegarLoop]: Abstraction has 1234 states and 3505 transitions. [2019-12-07 18:47:39,838 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:47:39,838 INFO L276 IsEmpty]: Start isEmpty. Operand 1234 states and 3505 transitions. [2019-12-07 18:47:39,840 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 18:47:39,841 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:39,841 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:39,841 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:39,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:39,841 INFO L82 PathProgramCache]: Analyzing trace with hash -1128085639, now seen corresponding path program 1 times [2019-12-07 18:47:39,842 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:39,842 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [697389576] [2019-12-07 18:47:39,842 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:39,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:39,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:39,917 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [697389576] [2019-12-07 18:47:39,917 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:39,917 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:47:39,917 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1926697739] [2019-12-07 18:47:39,917 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:47:39,918 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:39,918 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:47:39,918 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:47:39,918 INFO L87 Difference]: Start difference. First operand 1234 states and 3505 transitions. Second operand 5 states. [2019-12-07 18:47:40,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:40,048 INFO L93 Difference]: Finished difference Result 1775 states and 5027 transitions. [2019-12-07 18:47:40,048 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:47:40,048 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 58 [2019-12-07 18:47:40,048 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:40,050 INFO L225 Difference]: With dead ends: 1775 [2019-12-07 18:47:40,050 INFO L226 Difference]: Without dead ends: 1775 [2019-12-07 18:47:40,050 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:47:40,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1775 states. [2019-12-07 18:47:40,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1775 to 1599. [2019-12-07 18:47:40,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1599 states. [2019-12-07 18:47:40,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1599 states to 1599 states and 4535 transitions. [2019-12-07 18:47:40,067 INFO L78 Accepts]: Start accepts. Automaton has 1599 states and 4535 transitions. Word has length 58 [2019-12-07 18:47:40,067 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:40,067 INFO L462 AbstractCegarLoop]: Abstraction has 1599 states and 4535 transitions. [2019-12-07 18:47:40,068 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:47:40,068 INFO L276 IsEmpty]: Start isEmpty. Operand 1599 states and 4535 transitions. [2019-12-07 18:47:40,069 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 18:47:40,070 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:40,070 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:40,070 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:40,070 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:40,070 INFO L82 PathProgramCache]: Analyzing trace with hash -2139138521, now seen corresponding path program 2 times [2019-12-07 18:47:40,070 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:40,070 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1252753110] [2019-12-07 18:47:40,070 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:40,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:40,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:40,148 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1252753110] [2019-12-07 18:47:40,149 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:40,149 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:47:40,149 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [338732289] [2019-12-07 18:47:40,149 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:47:40,149 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:40,149 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:47:40,150 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:47:40,150 INFO L87 Difference]: Start difference. First operand 1599 states and 4535 transitions. Second operand 6 states. [2019-12-07 18:47:40,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:40,366 INFO L93 Difference]: Finished difference Result 2377 states and 6739 transitions. [2019-12-07 18:47:40,366 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:47:40,366 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 58 [2019-12-07 18:47:40,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:40,368 INFO L225 Difference]: With dead ends: 2377 [2019-12-07 18:47:40,368 INFO L226 Difference]: Without dead ends: 2377 [2019-12-07 18:47:40,369 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:47:40,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2377 states. [2019-12-07 18:47:40,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2377 to 1743. [2019-12-07 18:47:40,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1743 states. [2019-12-07 18:47:40,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1743 states to 1743 states and 4963 transitions. [2019-12-07 18:47:40,389 INFO L78 Accepts]: Start accepts. Automaton has 1743 states and 4963 transitions. Word has length 58 [2019-12-07 18:47:40,390 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:40,390 INFO L462 AbstractCegarLoop]: Abstraction has 1743 states and 4963 transitions. [2019-12-07 18:47:40,390 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:47:40,390 INFO L276 IsEmpty]: Start isEmpty. Operand 1743 states and 4963 transitions. [2019-12-07 18:47:40,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 18:47:40,392 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:40,392 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:40,392 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:40,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:40,392 INFO L82 PathProgramCache]: Analyzing trace with hash -1500936233, now seen corresponding path program 3 times [2019-12-07 18:47:40,392 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:40,392 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [171652005] [2019-12-07 18:47:40,392 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:40,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:40,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:40,455 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [171652005] [2019-12-07 18:47:40,455 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:40,456 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:47:40,456 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [242531271] [2019-12-07 18:47:40,456 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:47:40,456 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:40,456 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:47:40,456 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:47:40,456 INFO L87 Difference]: Start difference. First operand 1743 states and 4963 transitions. Second operand 6 states. [2019-12-07 18:47:40,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:40,664 INFO L93 Difference]: Finished difference Result 2557 states and 7219 transitions. [2019-12-07 18:47:40,664 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 18:47:40,664 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 58 [2019-12-07 18:47:40,665 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:40,668 INFO L225 Difference]: With dead ends: 2557 [2019-12-07 18:47:40,668 INFO L226 Difference]: Without dead ends: 2557 [2019-12-07 18:47:40,668 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 8 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:47:40,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2557 states. [2019-12-07 18:47:40,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2557 to 1903. [2019-12-07 18:47:40,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1903 states. [2019-12-07 18:47:40,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1903 states to 1903 states and 5419 transitions. [2019-12-07 18:47:40,697 INFO L78 Accepts]: Start accepts. Automaton has 1903 states and 5419 transitions. Word has length 58 [2019-12-07 18:47:40,697 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:40,697 INFO L462 AbstractCegarLoop]: Abstraction has 1903 states and 5419 transitions. [2019-12-07 18:47:40,697 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:47:40,697 INFO L276 IsEmpty]: Start isEmpty. Operand 1903 states and 5419 transitions. [2019-12-07 18:47:40,700 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 18:47:40,700 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:40,700 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:40,700 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:40,700 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:40,701 INFO L82 PathProgramCache]: Analyzing trace with hash -774913423, now seen corresponding path program 4 times [2019-12-07 18:47:40,701 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:40,701 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [578269411] [2019-12-07 18:47:40,701 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:40,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:40,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:40,779 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [578269411] [2019-12-07 18:47:40,779 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:40,779 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 18:47:40,779 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1047832208] [2019-12-07 18:47:40,779 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:47:40,779 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:40,779 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:47:40,780 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:47:40,780 INFO L87 Difference]: Start difference. First operand 1903 states and 5419 transitions. Second operand 7 states. [2019-12-07 18:47:41,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:41,071 INFO L93 Difference]: Finished difference Result 2834 states and 8013 transitions. [2019-12-07 18:47:41,071 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 18:47:41,071 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 58 [2019-12-07 18:47:41,072 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:41,074 INFO L225 Difference]: With dead ends: 2834 [2019-12-07 18:47:41,074 INFO L226 Difference]: Without dead ends: 2834 [2019-12-07 18:47:41,075 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 7 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:47:41,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2834 states. [2019-12-07 18:47:41,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2834 to 1847. [2019-12-07 18:47:41,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1847 states. [2019-12-07 18:47:41,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1847 states to 1847 states and 5259 transitions. [2019-12-07 18:47:41,099 INFO L78 Accepts]: Start accepts. Automaton has 1847 states and 5259 transitions. Word has length 58 [2019-12-07 18:47:41,100 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:41,100 INFO L462 AbstractCegarLoop]: Abstraction has 1847 states and 5259 transitions. [2019-12-07 18:47:41,100 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:47:41,100 INFO L276 IsEmpty]: Start isEmpty. Operand 1847 states and 5259 transitions. [2019-12-07 18:47:41,102 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 18:47:41,102 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:41,102 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:41,102 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:41,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:41,102 INFO L82 PathProgramCache]: Analyzing trace with hash -240075320, now seen corresponding path program 1 times [2019-12-07 18:47:41,103 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:41,103 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [289888365] [2019-12-07 18:47:41,103 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:41,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:41,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:41,142 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [289888365] [2019-12-07 18:47:41,142 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:41,142 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:47:41,142 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [994936879] [2019-12-07 18:47:41,142 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:47:41,142 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:41,142 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:47:41,143 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:47:41,143 INFO L87 Difference]: Start difference. First operand 1847 states and 5259 transitions. Second operand 3 states. [2019-12-07 18:47:41,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:41,175 INFO L93 Difference]: Finished difference Result 1847 states and 5258 transitions. [2019-12-07 18:47:41,175 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:47:41,175 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 59 [2019-12-07 18:47:41,175 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:41,177 INFO L225 Difference]: With dead ends: 1847 [2019-12-07 18:47:41,177 INFO L226 Difference]: Without dead ends: 1847 [2019-12-07 18:47:41,177 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:47:41,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1847 states. [2019-12-07 18:47:41,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1847 to 1314. [2019-12-07 18:47:41,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1314 states. [2019-12-07 18:47:41,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1314 states to 1314 states and 3752 transitions. [2019-12-07 18:47:41,192 INFO L78 Accepts]: Start accepts. Automaton has 1314 states and 3752 transitions. Word has length 59 [2019-12-07 18:47:41,193 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:41,193 INFO L462 AbstractCegarLoop]: Abstraction has 1314 states and 3752 transitions. [2019-12-07 18:47:41,193 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:47:41,193 INFO L276 IsEmpty]: Start isEmpty. Operand 1314 states and 3752 transitions. [2019-12-07 18:47:41,194 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 18:47:41,194 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:41,194 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:41,195 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:41,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:41,195 INFO L82 PathProgramCache]: Analyzing trace with hash -248733535, now seen corresponding path program 1 times [2019-12-07 18:47:41,195 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:41,195 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [74626432] [2019-12-07 18:47:41,195 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:41,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:41,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:41,228 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [74626432] [2019-12-07 18:47:41,228 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:41,228 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:47:41,228 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [899370722] [2019-12-07 18:47:41,229 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:47:41,229 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:41,229 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:47:41,229 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:47:41,229 INFO L87 Difference]: Start difference. First operand 1314 states and 3752 transitions. Second operand 3 states. [2019-12-07 18:47:41,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:41,240 INFO L93 Difference]: Finished difference Result 1246 states and 3480 transitions. [2019-12-07 18:47:41,240 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:47:41,241 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 59 [2019-12-07 18:47:41,241 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:41,242 INFO L225 Difference]: With dead ends: 1246 [2019-12-07 18:47:41,242 INFO L226 Difference]: Without dead ends: 1246 [2019-12-07 18:47:41,242 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:47:41,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1246 states. [2019-12-07 18:47:41,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1246 to 1182. [2019-12-07 18:47:41,252 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1182 states. [2019-12-07 18:47:41,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1182 states to 1182 states and 3296 transitions. [2019-12-07 18:47:41,254 INFO L78 Accepts]: Start accepts. Automaton has 1182 states and 3296 transitions. Word has length 59 [2019-12-07 18:47:41,254 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:41,254 INFO L462 AbstractCegarLoop]: Abstraction has 1182 states and 3296 transitions. [2019-12-07 18:47:41,254 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:47:41,254 INFO L276 IsEmpty]: Start isEmpty. Operand 1182 states and 3296 transitions. [2019-12-07 18:47:41,256 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 18:47:41,256 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:41,256 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:41,256 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:41,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:41,256 INFO L82 PathProgramCache]: Analyzing trace with hash 1978644192, now seen corresponding path program 1 times [2019-12-07 18:47:41,256 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:41,256 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745368119] [2019-12-07 18:47:41,256 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:41,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:41,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:41,343 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1745368119] [2019-12-07 18:47:41,343 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:41,343 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:47:41,343 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1729697620] [2019-12-07 18:47:41,344 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:47:41,344 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:41,344 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:47:41,344 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:47:41,344 INFO L87 Difference]: Start difference. First operand 1182 states and 3296 transitions. Second operand 7 states. [2019-12-07 18:47:41,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:41,428 INFO L93 Difference]: Finished difference Result 2446 states and 6404 transitions. [2019-12-07 18:47:41,429 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 18:47:41,429 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 60 [2019-12-07 18:47:41,429 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:41,430 INFO L225 Difference]: With dead ends: 2446 [2019-12-07 18:47:41,430 INFO L226 Difference]: Without dead ends: 1739 [2019-12-07 18:47:41,431 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=40, Invalid=70, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:47:41,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1739 states. [2019-12-07 18:47:41,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1739 to 1056. [2019-12-07 18:47:41,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1056 states. [2019-12-07 18:47:41,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1056 states to 1056 states and 2872 transitions. [2019-12-07 18:47:41,447 INFO L78 Accepts]: Start accepts. Automaton has 1056 states and 2872 transitions. Word has length 60 [2019-12-07 18:47:41,447 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:41,447 INFO L462 AbstractCegarLoop]: Abstraction has 1056 states and 2872 transitions. [2019-12-07 18:47:41,447 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:47:41,447 INFO L276 IsEmpty]: Start isEmpty. Operand 1056 states and 2872 transitions. [2019-12-07 18:47:41,448 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 18:47:41,448 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:41,448 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:41,449 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:41,449 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:41,449 INFO L82 PathProgramCache]: Analyzing trace with hash 1465585068, now seen corresponding path program 2 times [2019-12-07 18:47:41,449 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:41,449 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1965539523] [2019-12-07 18:47:41,449 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:41,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:41,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:41,516 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1965539523] [2019-12-07 18:47:41,516 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:41,516 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:47:41,516 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [543918836] [2019-12-07 18:47:41,516 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:47:41,516 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:41,516 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:47:41,516 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:47:41,517 INFO L87 Difference]: Start difference. First operand 1056 states and 2872 transitions. Second operand 5 states. [2019-12-07 18:47:41,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:41,547 INFO L93 Difference]: Finished difference Result 1332 states and 3351 transitions. [2019-12-07 18:47:41,547 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:47:41,547 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 60 [2019-12-07 18:47:41,548 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:41,548 INFO L225 Difference]: With dead ends: 1332 [2019-12-07 18:47:41,548 INFO L226 Difference]: Without dead ends: 777 [2019-12-07 18:47:41,549 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:47:41,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 777 states. [2019-12-07 18:47:41,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 777 to 777. [2019-12-07 18:47:41,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 777 states. [2019-12-07 18:47:41,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 777 states to 777 states and 1851 transitions. [2019-12-07 18:47:41,556 INFO L78 Accepts]: Start accepts. Automaton has 777 states and 1851 transitions. Word has length 60 [2019-12-07 18:47:41,556 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:41,556 INFO L462 AbstractCegarLoop]: Abstraction has 777 states and 1851 transitions. [2019-12-07 18:47:41,556 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:47:41,556 INFO L276 IsEmpty]: Start isEmpty. Operand 777 states and 1851 transitions. [2019-12-07 18:47:41,557 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 18:47:41,557 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:41,557 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:41,557 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:41,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:41,558 INFO L82 PathProgramCache]: Analyzing trace with hash -665728346, now seen corresponding path program 3 times [2019-12-07 18:47:41,558 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:41,558 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1862072454] [2019-12-07 18:47:41,558 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:41,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:41,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:41,651 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1862072454] [2019-12-07 18:47:41,652 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:41,652 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:47:41,652 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [138783095] [2019-12-07 18:47:41,652 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:47:41,652 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:41,652 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:47:41,652 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:47:41,653 INFO L87 Difference]: Start difference. First operand 777 states and 1851 transitions. Second operand 6 states. [2019-12-07 18:47:41,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:41,699 INFO L93 Difference]: Finished difference Result 1212 states and 2871 transitions. [2019-12-07 18:47:41,699 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:47:41,699 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 60 [2019-12-07 18:47:41,699 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:41,699 INFO L225 Difference]: With dead ends: 1212 [2019-12-07 18:47:41,699 INFO L226 Difference]: Without dead ends: 264 [2019-12-07 18:47:41,700 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:47:41,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 264 states. [2019-12-07 18:47:41,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 264 to 232. [2019-12-07 18:47:41,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 232 states. [2019-12-07 18:47:41,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 232 states to 232 states and 410 transitions. [2019-12-07 18:47:41,702 INFO L78 Accepts]: Start accepts. Automaton has 232 states and 410 transitions. Word has length 60 [2019-12-07 18:47:41,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:41,702 INFO L462 AbstractCegarLoop]: Abstraction has 232 states and 410 transitions. [2019-12-07 18:47:41,702 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:47:41,702 INFO L276 IsEmpty]: Start isEmpty. Operand 232 states and 410 transitions. [2019-12-07 18:47:41,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 18:47:41,703 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:41,703 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:41,703 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:41,703 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:41,703 INFO L82 PathProgramCache]: Analyzing trace with hash 1097199394, now seen corresponding path program 4 times [2019-12-07 18:47:41,703 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:41,703 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1448723961] [2019-12-07 18:47:41,703 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:41,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:41,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:41,856 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1448723961] [2019-12-07 18:47:41,856 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:41,856 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 18:47:41,856 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1940725444] [2019-12-07 18:47:41,856 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 18:47:41,856 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:41,856 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 18:47:41,856 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=106, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:47:41,857 INFO L87 Difference]: Start difference. First operand 232 states and 410 transitions. Second operand 12 states. [2019-12-07 18:47:42,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:42,125 INFO L93 Difference]: Finished difference Result 386 states and 663 transitions. [2019-12-07 18:47:42,126 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 18:47:42,126 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 60 [2019-12-07 18:47:42,126 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:42,126 INFO L225 Difference]: With dead ends: 386 [2019-12-07 18:47:42,126 INFO L226 Difference]: Without dead ends: 358 [2019-12-07 18:47:42,127 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=62, Invalid=280, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:47:42,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 358 states. [2019-12-07 18:47:42,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 358 to 328. [2019-12-07 18:47:42,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 328 states. [2019-12-07 18:47:42,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 328 states to 328 states and 574 transitions. [2019-12-07 18:47:42,130 INFO L78 Accepts]: Start accepts. Automaton has 328 states and 574 transitions. Word has length 60 [2019-12-07 18:47:42,130 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:42,130 INFO L462 AbstractCegarLoop]: Abstraction has 328 states and 574 transitions. [2019-12-07 18:47:42,130 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 18:47:42,130 INFO L276 IsEmpty]: Start isEmpty. Operand 328 states and 574 transitions. [2019-12-07 18:47:42,130 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 18:47:42,130 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:42,130 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:42,131 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:42,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:42,131 INFO L82 PathProgramCache]: Analyzing trace with hash -1151648330, now seen corresponding path program 5 times [2019-12-07 18:47:42,131 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:42,131 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [494134272] [2019-12-07 18:47:42,131 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:42,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:42,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:42,261 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [494134272] [2019-12-07 18:47:42,261 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:42,261 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 18:47:42,261 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [515202445] [2019-12-07 18:47:42,261 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 18:47:42,262 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:42,262 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 18:47:42,262 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=107, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:47:42,262 INFO L87 Difference]: Start difference. First operand 328 states and 574 transitions. Second operand 12 states. [2019-12-07 18:47:42,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:42,540 INFO L93 Difference]: Finished difference Result 442 states and 749 transitions. [2019-12-07 18:47:42,540 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-12-07 18:47:42,540 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 60 [2019-12-07 18:47:42,540 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:42,540 INFO L225 Difference]: With dead ends: 442 [2019-12-07 18:47:42,541 INFO L226 Difference]: Without dead ends: 414 [2019-12-07 18:47:42,541 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 54 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=72, Invalid=348, Unknown=0, NotChecked=0, Total=420 [2019-12-07 18:47:42,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 414 states. [2019-12-07 18:47:42,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 414 to 332. [2019-12-07 18:47:42,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 332 states. [2019-12-07 18:47:42,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 332 states to 332 states and 581 transitions. [2019-12-07 18:47:42,544 INFO L78 Accepts]: Start accepts. Automaton has 332 states and 581 transitions. Word has length 60 [2019-12-07 18:47:42,544 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:42,544 INFO L462 AbstractCegarLoop]: Abstraction has 332 states and 581 transitions. [2019-12-07 18:47:42,544 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 18:47:42,544 INFO L276 IsEmpty]: Start isEmpty. Operand 332 states and 581 transitions. [2019-12-07 18:47:42,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 18:47:42,544 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:42,544 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:42,545 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:42,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:42,545 INFO L82 PathProgramCache]: Analyzing trace with hash -2140500766, now seen corresponding path program 6 times [2019-12-07 18:47:42,545 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:42,545 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [343079506] [2019-12-07 18:47:42,545 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:42,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:42,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:42,752 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [343079506] [2019-12-07 18:47:42,752 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:42,752 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 18:47:42,753 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [23144044] [2019-12-07 18:47:42,753 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 18:47:42,753 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:42,753 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 18:47:42,753 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=173, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:47:42,754 INFO L87 Difference]: Start difference. First operand 332 states and 581 transitions. Second operand 15 states. [2019-12-07 18:47:43,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:43,208 INFO L93 Difference]: Finished difference Result 529 states and 897 transitions. [2019-12-07 18:47:43,208 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-12-07 18:47:43,208 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 60 [2019-12-07 18:47:43,208 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:43,208 INFO L225 Difference]: With dead ends: 529 [2019-12-07 18:47:43,208 INFO L226 Difference]: Without dead ends: 501 [2019-12-07 18:47:43,209 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 106 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=149, Invalid=663, Unknown=0, NotChecked=0, Total=812 [2019-12-07 18:47:43,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 501 states. [2019-12-07 18:47:43,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 501 to 342. [2019-12-07 18:47:43,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 342 states. [2019-12-07 18:47:43,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 342 states to 342 states and 599 transitions. [2019-12-07 18:47:43,212 INFO L78 Accepts]: Start accepts. Automaton has 342 states and 599 transitions. Word has length 60 [2019-12-07 18:47:43,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:43,212 INFO L462 AbstractCegarLoop]: Abstraction has 342 states and 599 transitions. [2019-12-07 18:47:43,212 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 18:47:43,212 INFO L276 IsEmpty]: Start isEmpty. Operand 342 states and 599 transitions. [2019-12-07 18:47:43,213 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 18:47:43,213 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:43,213 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:43,213 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:43,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:43,213 INFO L82 PathProgramCache]: Analyzing trace with hash 1366424482, now seen corresponding path program 7 times [2019-12-07 18:47:43,213 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:43,213 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2124905912] [2019-12-07 18:47:43,214 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:43,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:47:43,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:47:43,390 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2124905912] [2019-12-07 18:47:43,390 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:47:43,390 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 18:47:43,391 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [700658726] [2019-12-07 18:47:43,391 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 18:47:43,391 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:47:43,391 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 18:47:43,391 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=150, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:47:43,391 INFO L87 Difference]: Start difference. First operand 342 states and 599 transitions. Second operand 14 states. [2019-12-07 18:47:43,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:47:43,748 INFO L93 Difference]: Finished difference Result 440 states and 746 transitions. [2019-12-07 18:47:43,749 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 18:47:43,749 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 60 [2019-12-07 18:47:43,749 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:47:43,749 INFO L225 Difference]: With dead ends: 440 [2019-12-07 18:47:43,749 INFO L226 Difference]: Without dead ends: 412 [2019-12-07 18:47:43,750 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 74 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=117, Invalid=483, Unknown=0, NotChecked=0, Total=600 [2019-12-07 18:47:43,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 412 states. [2019-12-07 18:47:43,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 412 to 340. [2019-12-07 18:47:43,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 340 states. [2019-12-07 18:47:43,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 595 transitions. [2019-12-07 18:47:43,753 INFO L78 Accepts]: Start accepts. Automaton has 340 states and 595 transitions. Word has length 60 [2019-12-07 18:47:43,753 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:47:43,753 INFO L462 AbstractCegarLoop]: Abstraction has 340 states and 595 transitions. [2019-12-07 18:47:43,753 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 18:47:43,753 INFO L276 IsEmpty]: Start isEmpty. Operand 340 states and 595 transitions. [2019-12-07 18:47:43,753 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 18:47:43,753 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:47:43,753 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:47:43,754 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:47:43,754 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:47:43,754 INFO L82 PathProgramCache]: Analyzing trace with hash -1858118138, now seen corresponding path program 8 times [2019-12-07 18:47:43,754 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:47:43,754 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981790291] [2019-12-07 18:47:43,754 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:47:43,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:47:43,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:47:43,817 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:47:43,817 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 18:47:43,819 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [786] [786] ULTIMATE.startENTRY-->L831: Formula: (let ((.cse0 (store |v_#valid_75| 0 0))) (and (= 0 v_~z$flush_delayed~0_54) (= |v_#NULL.offset_7| 0) (= v_~z$w_buff1_used~0_609 0) (= 0 v_~z$r_buff1_thd3~0_278) (= v_~z$w_buff0_used~0_830 0) (= v_~z$r_buff0_thd1~0_77 0) (= v_~x~0_53 0) (< 0 |v_#StackHeapBarrier_21|) (= v_~z$w_buff0~0_376 0) (= v_~z$r_buff0_thd0~0_415 0) (= v_~z$read_delayed~0_5 0) (= 0 v_~weak$$choice0~0_32) (= v_~z$read_delayed_var~0.base_5 0) (= v_~z$w_buff1~0_367 0) (= v_~weak$$choice2~0_172 0) (= v_~z$r_buff1_thd2~0_207 0) (< |v_#StackHeapBarrier_21| |v_ULTIMATE.start_main_~#t1273~0.base_21|) (= v_~z$r_buff1_thd1~0_207 0) (= v_~z$read_delayed_var~0.offset_5 0) (= v_~y~0_52 0) (= 0 v_~z$r_buff1_thd4~0_260) (= v_~z$mem_tmp~0_37 0) (= |v_ULTIMATE.start_main_~#t1273~0.offset_17| 0) (= 0 v_~z$r_buff0_thd3~0_189) (= v_~__unbuffered_cnt~0_145 0) (= |v_#valid_73| (store .cse0 |v_ULTIMATE.start_main_~#t1273~0.base_21| 1)) (= 0 |v_#NULL.base_7|) (= v_~main$tmp_guard0~0_21 0) (= v_~z~0_157 0) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1273~0.base_21| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1273~0.base_21|) |v_ULTIMATE.start_main_~#t1273~0.offset_17| 0)) |v_#memory_int_23|) (= v_~a~0_207 0) (= 0 v_~z$r_buff0_thd4~0_332) (= 0 v_~__unbuffered_p3_EBX~0_219) (= v_~z$r_buff0_thd2~0_78 0) (= v_~main$tmp_guard1~0_24 0) (= v_~z$r_buff1_thd0~0_431 0) (= v_~b~0_98 0) (= v_~__unbuffered_p3_EAX~0_219 0) (= |v_#length_29| (store |v_#length_30| |v_ULTIMATE.start_main_~#t1273~0.base_21| 4)) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1273~0.base_21|)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_21|, #valid=|v_#valid_75|, #memory_int=|v_#memory_int_24|, #length=|v_#length_30|} OutVars{ULTIMATE.start_main_~#t1274~0.base=|v_ULTIMATE.start_main_~#t1274~0.base_23|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_42|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_207, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_72|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_33|, #NULL.offset=|v_#NULL.offset_7|, ULTIMATE.start_main_~#t1273~0.offset=|v_ULTIMATE.start_main_~#t1273~0.offset_17|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_40|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_35|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_134|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_39|, ~a~0=v_~a~0_207, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_415, ~z$r_buff0_thd4~0=v_~z$r_buff0_thd4~0_332, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_219, #length=|v_#length_29|, ULTIMATE.start_main_~#t1276~0.offset=|v_ULTIMATE.start_main_~#t1276~0.offset_18|, ~z$mem_tmp~0=v_~z$mem_tmp~0_37, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_66|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_41|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_609, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_40|, ULTIMATE.start_main_~#t1275~0.base=|v_ULTIMATE.start_main_~#t1275~0.base_22|, ~z$flush_delayed~0=v_~z$flush_delayed~0_54, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_52|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_76|, ULTIMATE.start_main_~#t1275~0.offset=|v_ULTIMATE.start_main_~#t1275~0.offset_18|, ULTIMATE.start_main_~#t1274~0.offset=|v_ULTIMATE.start_main_~#t1274~0.offset_18|, ~weak$$choice0~0=v_~weak$$choice0~0_32, #StackHeapBarrier=|v_#StackHeapBarrier_21|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_40|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_207, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_9|, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_5, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_189, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_8|, ULTIMATE.start_main_~#t1276~0.base=|v_ULTIMATE.start_main_~#t1276~0.base_23|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_145, ~x~0=v_~x~0_53, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_260, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_36|, ~z$read_delayed~0=v_~z$read_delayed~0_5, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_42|, ~z$w_buff1~0=v_~z$w_buff1~0_367, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_24, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_30|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_5, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_44|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_34|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_36|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_42|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_48|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_431, ULTIMATE.start_main_#t~nondet26=|v_ULTIMATE.start_main_#t~nondet26_56|, ~y~0=v_~y~0_52, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_78, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_830, ~z$w_buff0~0=v_~z$w_buff0~0_376, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_30|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_56|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_278, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_53|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_82|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_21, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_219, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_55|, #NULL.base=|v_#NULL.base_7|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_70|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_34|, ~b~0=v_~b~0_98, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_23|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_9|, ULTIMATE.start_main_~#t1273~0.base=|v_ULTIMATE.start_main_~#t1273~0.base_21|, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_20|, ~z~0=v_~z~0_157, ~weak$$choice2~0=v_~weak$$choice2~0_172, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_77} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1274~0.base, ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_~#t1273~0.offset, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~a~0, ~z$r_buff0_thd0~0, ~z$r_buff0_thd4~0, ~__unbuffered_p3_EAX~0, #length, ULTIMATE.start_main_~#t1276~0.offset, ~z$mem_tmp~0, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_~#t1275~0.base, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_~#t1275~0.offset, ULTIMATE.start_main_~#t1274~0.offset, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ULTIMATE.start_main_#t~nondet15, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ULTIMATE.start_main_#t~nondet17, ULTIMATE.start_main_~#t1276~0.base, ~__unbuffered_cnt~0, ~x~0, ~z$r_buff1_thd4~0, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite30, ~z$r_buff1_thd0~0, ULTIMATE.start_main_#t~nondet26, ~y~0, ~z$r_buff0_thd2~0, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~__unbuffered_p3_EBX~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ~b~0, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t1273~0.base, ULTIMATE.start_main_#t~nondet18, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 18:47:43,820 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L831-1-->L833: Formula: (and (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t1274~0.base_13| 4)) (= |v_#memory_int_15| (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1274~0.base_13| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1274~0.base_13|) |v_ULTIMATE.start_main_~#t1274~0.offset_11| 1))) (= |v_ULTIMATE.start_main_~#t1274~0.offset_11| 0) (= |v_#valid_44| (store |v_#valid_45| |v_ULTIMATE.start_main_~#t1274~0.base_13| 1)) (= 0 (select |v_#valid_45| |v_ULTIMATE.start_main_~#t1274~0.base_13|)) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t1274~0.base_13|) (not (= 0 |v_ULTIMATE.start_main_~#t1274~0.base_13|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_16|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_~#t1274~0.offset=|v_ULTIMATE.start_main_~#t1274~0.offset_11|, #StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_~#t1274~0.base=|v_ULTIMATE.start_main_~#t1274~0.base_13|, #valid=|v_#valid_44|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_6|, #length=|v_#length_21|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1274~0.offset, ULTIMATE.start_main_~#t1274~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length] because there is no mapped edge [2019-12-07 18:47:43,820 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [749] [749] L833-1-->L835: Formula: (and (not (= |v_ULTIMATE.start_main_~#t1275~0.base_11| 0)) (= |v_#valid_40| (store |v_#valid_41| |v_ULTIMATE.start_main_~#t1275~0.base_11| 1)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1275~0.base_11|) (= |v_ULTIMATE.start_main_~#t1275~0.offset_10| 0) (= (select |v_#valid_41| |v_ULTIMATE.start_main_~#t1275~0.base_11|) 0) (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t1275~0.base_11| 4)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1275~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1275~0.base_11|) |v_ULTIMATE.start_main_~#t1275~0.offset_10| 2)) |v_#memory_int_13|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_14|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_6|, #length=|v_#length_19|, ULTIMATE.start_main_~#t1275~0.base=|v_ULTIMATE.start_main_~#t1275~0.base_11|, ULTIMATE.start_main_~#t1275~0.offset=|v_ULTIMATE.start_main_~#t1275~0.offset_10|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length, ULTIMATE.start_main_~#t1275~0.base, ULTIMATE.start_main_~#t1275~0.offset] because there is no mapped edge [2019-12-07 18:47:43,820 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L835-1-->L837: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t1276~0.base_13|)) (= (store |v_#valid_47| |v_ULTIMATE.start_main_~#t1276~0.base_13| 1) |v_#valid_46|) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t1276~0.base_13|) (= (select |v_#valid_47| |v_ULTIMATE.start_main_~#t1276~0.base_13|) 0) (= |v_ULTIMATE.start_main_~#t1276~0.offset_11| 0) (= |v_#memory_int_17| (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1276~0.base_13| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1276~0.base_13|) |v_ULTIMATE.start_main_~#t1276~0.offset_11| 3))) (= |v_#length_23| (store |v_#length_24| |v_ULTIMATE.start_main_~#t1276~0.base_13| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_18|, #length=|v_#length_24|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_~#t1276~0.base=|v_ULTIMATE.start_main_~#t1276~0.base_13|, #length=|v_#length_23|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_5|, ULTIMATE.start_main_~#t1276~0.offset=|v_ULTIMATE.start_main_~#t1276~0.offset_11|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_~#t1276~0.base, #length, ULTIMATE.start_main_#t~nondet17, ULTIMATE.start_main_~#t1276~0.offset] because there is no mapped edge [2019-12-07 18:47:43,821 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L4-->L808: Formula: (and (= v_~z$r_buff0_thd4~0_36 1) (= v_~z$r_buff1_thd2~0_8 v_~z$r_buff0_thd2~0_7) (= v_~z$r_buff0_thd0~0_114 v_~z$r_buff1_thd0~0_75) (= 1 v_~a~0_7) (= v_~z$r_buff0_thd4~0_37 v_~z$r_buff1_thd4~0_34) (= v_~__unbuffered_p3_EAX~0_8 v_~a~0_7) (= v_~z$r_buff1_thd1~0_8 v_~z$r_buff0_thd1~0_7) (= v_~z$r_buff0_thd3~0_42 v_~z$r_buff1_thd3~0_34) (= v_~b~0_17 v_~__unbuffered_p3_EBX~0_8) (not (= v_P3Thread1of1ForFork3___VERIFIER_assert_~expression_16 0))) InVars {P3Thread1of1ForFork3___VERIFIER_assert_~expression=v_P3Thread1of1ForFork3___VERIFIER_assert_~expression_16, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_114, ~b~0=v_~b~0_17, ~z$r_buff0_thd4~0=v_~z$r_buff0_thd4~0_37, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_42, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_7, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_7} OutVars{P3Thread1of1ForFork3___VERIFIER_assert_~expression=v_P3Thread1of1ForFork3___VERIFIER_assert_~expression_16, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_34, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_34, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_8, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_8, ~a~0=v_~a~0_7, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_114, ~b~0=v_~b~0_17, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_75, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_8, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_8, ~z$r_buff0_thd4~0=v_~z$r_buff0_thd4~0_36, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_42, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_7, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_7} AuxVars[] AssignedVars[~a~0, ~z$r_buff1_thd4~0, ~z$r_buff1_thd3~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~__unbuffered_p3_EAX~0, ~z$r_buff0_thd4~0, ~__unbuffered_p3_EBX~0] because there is no mapped edge [2019-12-07 18:47:43,821 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] P0ENTRY-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork0_#res.base_9|) (= v_~b~0_62 1) (= |v_P0Thread1of1ForFork0_#res.offset_9| 0) (= v_P0Thread1of1ForFork0_~arg.offset_19 |v_P0Thread1of1ForFork0_#in~arg.offset_21|) (= v_P0Thread1of1ForFork0_~arg.base_19 |v_P0Thread1of1ForFork0_#in~arg.base_21|) (= v_~__unbuffered_cnt~0_119 (+ v_~__unbuffered_cnt~0_120 1)) (= v_~x~0_42 1)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_21|, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_120} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_21|, P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_9|, ~b~0=v_~b~0_62, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_21|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_9|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_119, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_19, ~x~0=v_~x~0_42, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_19} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, ~b~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P0Thread1of1ForFork0_~arg.base, ~x~0, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 18:47:43,821 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [743] [743] P1ENTRY-->P1EXIT: Formula: (and (= v_P1Thread1of1ForFork1_~arg.base_12 |v_P1Thread1of1ForFork1_#in~arg.base_14|) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= |v_P1Thread1of1ForFork1_#in~arg.offset_14| v_P1Thread1of1ForFork1_~arg.offset_12) (= v_~y~0_33 1) (= v_~x~0_29 2) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_84 1) v_~__unbuffered_cnt~0_83)) InVars {P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_14|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_14|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_84} OutVars{P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_12, P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_12, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_14|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_14|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_83, ~y~0=v_~y~0_33, ~x~0=v_~x~0_29, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1_#res.offset, P1Thread1of1ForFork1_~arg.base, ~__unbuffered_cnt~0, ~y~0, ~x~0, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 18:47:43,822 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [727] [727] L809-->L809-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd4~0_In1339614723 256) 0)) (.cse0 (= (mod ~z$w_buff0_used~0_In1339614723 256) 0))) (or (and (not .cse0) (= 0 |P3Thread1of1ForFork3_#t~ite11_Out1339614723|) (not .cse1)) (and (= |P3Thread1of1ForFork3_#t~ite11_Out1339614723| ~z$w_buff0_used~0_In1339614723) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1339614723, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In1339614723} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1339614723, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In1339614723, P3Thread1of1ForFork3_#t~ite11=|P3Thread1of1ForFork3_#t~ite11_Out1339614723|} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite11] because there is no mapped edge [2019-12-07 18:47:43,823 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [728] [728] L810-->L810-2: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd4~0_In-202933783 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-202933783 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In-202933783 256) 0)) (.cse3 (= 0 (mod ~z$r_buff0_thd4~0_In-202933783 256)))) (or (and (= 0 |P3Thread1of1ForFork3_#t~ite12_Out-202933783|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$w_buff1_used~0_In-202933783 |P3Thread1of1ForFork3_#t~ite12_Out-202933783|) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-202933783, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-202933783, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-202933783, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-202933783} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-202933783, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-202933783, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-202933783, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-202933783, P3Thread1of1ForFork3_#t~ite12=|P3Thread1of1ForFork3_#t~ite12_Out-202933783|} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite12] because there is no mapped edge [2019-12-07 18:47:43,823 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [718] [718] L772-2-->L772-4: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In-1996925979 256) 0)) (.cse0 (= 0 (mod ~z$r_buff1_thd3~0_In-1996925979 256)))) (or (and (or .cse0 .cse1) (= ~z~0_In-1996925979 |P2Thread1of1ForFork2_#t~ite3_Out-1996925979|)) (and (= ~z$w_buff1~0_In-1996925979 |P2Thread1of1ForFork2_#t~ite3_Out-1996925979|) (not .cse1) (not .cse0)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1996925979, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1996925979, ~z$w_buff1~0=~z$w_buff1~0_In-1996925979, ~z~0=~z~0_In-1996925979} OutVars{P2Thread1of1ForFork2_#t~ite3=|P2Thread1of1ForFork2_#t~ite3_Out-1996925979|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1996925979, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1996925979, ~z$w_buff1~0=~z$w_buff1~0_In-1996925979, ~z~0=~z~0_In-1996925979} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 18:47:43,823 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [663] [663] L772-4-->L773: Formula: (= v_~z~0_32 |v_P2Thread1of1ForFork2_#t~ite3_8|) InVars {P2Thread1of1ForFork2_#t~ite3=|v_P2Thread1of1ForFork2_#t~ite3_8|} OutVars{P2Thread1of1ForFork2_#t~ite4=|v_P2Thread1of1ForFork2_#t~ite4_13|, P2Thread1of1ForFork2_#t~ite3=|v_P2Thread1of1ForFork2_#t~ite3_7|, ~z~0=v_~z~0_32} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite4, P2Thread1of1ForFork2_#t~ite3, ~z~0] because there is no mapped edge [2019-12-07 18:47:43,823 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [707] [707] L773-->L773-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In694862629 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In694862629 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P2Thread1of1ForFork2_#t~ite5_Out694862629|)) (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In694862629 |P2Thread1of1ForFork2_#t~ite5_Out694862629|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In694862629, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In694862629} OutVars{P2Thread1of1ForFork2_#t~ite5=|P2Thread1of1ForFork2_#t~ite5_Out694862629|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In694862629, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In694862629} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 18:47:43,823 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L774-->L774-2: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In-915845322 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd3~0_In-915845322 256) 0)) (.cse3 (= 0 (mod ~z$r_buff0_thd3~0_In-915845322 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In-915845322 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork2_#t~ite6_Out-915845322| 0)) (and (= |P2Thread1of1ForFork2_#t~ite6_Out-915845322| ~z$w_buff1_used~0_In-915845322) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-915845322, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-915845322, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-915845322, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-915845322} OutVars{P2Thread1of1ForFork2_#t~ite6=|P2Thread1of1ForFork2_#t~ite6_Out-915845322|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-915845322, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-915845322, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-915845322, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-915845322} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 18:47:43,823 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L775-->L775-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In-1526394517 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-1526394517 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |P2Thread1of1ForFork2_#t~ite7_Out-1526394517|)) (and (or .cse0 .cse1) (= ~z$r_buff0_thd3~0_In-1526394517 |P2Thread1of1ForFork2_#t~ite7_Out-1526394517|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1526394517, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1526394517} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1526394517, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1526394517, P2Thread1of1ForFork2_#t~ite7=|P2Thread1of1ForFork2_#t~ite7_Out-1526394517|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 18:47:43,824 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L776-->L776-2: Formula: (let ((.cse3 (= 0 (mod ~z$w_buff1_used~0_In-812263784 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In-812263784 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-812263784 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-812263784 256)))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite8_Out-812263784|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse0 .cse1) (= ~z$r_buff1_thd3~0_In-812263784 |P2Thread1of1ForFork2_#t~ite8_Out-812263784|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-812263784, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-812263784, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-812263784, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-812263784} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-812263784, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-812263784, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-812263784, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-812263784, P2Thread1of1ForFork2_#t~ite8=|P2Thread1of1ForFork2_#t~ite8_Out-812263784|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 18:47:43,824 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [739] [739] L776-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= |v_P2Thread1of1ForFork2_#t~ite8_34| v_~z$r_buff1_thd3~0_64) (= v_~__unbuffered_cnt~0_77 (+ v_~__unbuffered_cnt~0_78 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_78, P2Thread1of1ForFork2_#t~ite8=|v_P2Thread1of1ForFork2_#t~ite8_34|} OutVars{~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_64, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_77, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|, P2Thread1of1ForFork2_#t~ite8=|v_P2Thread1of1ForFork2_#t~ite8_33|} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset, P2Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 18:47:43,824 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L811-->L812: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In159571 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd4~0_In159571 256))) (.cse0 (= ~z$r_buff0_thd4~0_Out159571 ~z$r_buff0_thd4~0_In159571))) (or (and .cse0 .cse1) (and (not .cse1) (= 0 ~z$r_buff0_thd4~0_Out159571) (not .cse2)) (and .cse2 .cse0))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In159571, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In159571} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In159571, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out159571, P3Thread1of1ForFork3_#t~ite13=|P3Thread1of1ForFork3_#t~ite13_Out159571|} AuxVars[] AssignedVars[~z$r_buff0_thd4~0, P3Thread1of1ForFork3_#t~ite13] because there is no mapped edge [2019-12-07 18:47:43,824 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L812-->L812-2: Formula: (let ((.cse2 (= (mod ~z$w_buff1_used~0_In1945376630 256) 0)) (.cse3 (= (mod ~z$r_buff1_thd4~0_In1945376630 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd4~0_In1945376630 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In1945376630 256) 0))) (or (and (= 0 |P3Thread1of1ForFork3_#t~ite14_Out1945376630|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P3Thread1of1ForFork3_#t~ite14_Out1945376630| ~z$r_buff1_thd4~0_In1945376630) (or .cse2 .cse3) (or .cse0 .cse1)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In1945376630, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1945376630, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In1945376630, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1945376630} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In1945376630, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1945376630, P3Thread1of1ForFork3_#t~ite14=|P3Thread1of1ForFork3_#t~ite14_Out1945376630|, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In1945376630, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1945376630} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite14] because there is no mapped edge [2019-12-07 18:47:43,824 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [750] [750] L812-2-->P3EXIT: Formula: (and (= v_~__unbuffered_cnt~0_107 (+ v_~__unbuffered_cnt~0_108 1)) (= 0 |v_P3Thread1of1ForFork3_#res.base_3|) (= 0 |v_P3Thread1of1ForFork3_#res.offset_3|) (= |v_P3Thread1of1ForFork3_#t~ite14_44| v_~z$r_buff1_thd4~0_75)) InVars {P3Thread1of1ForFork3_#t~ite14=|v_P3Thread1of1ForFork3_#t~ite14_44|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_108} OutVars{~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_75, P3Thread1of1ForFork3_#t~ite14=|v_P3Thread1of1ForFork3_#t~ite14_43|, P3Thread1of1ForFork3_#res.base=|v_P3Thread1of1ForFork3_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_107, P3Thread1of1ForFork3_#res.offset=|v_P3Thread1of1ForFork3_#res.offset_3|} AuxVars[] AssignedVars[~z$r_buff1_thd4~0, P3Thread1of1ForFork3_#t~ite14, P3Thread1of1ForFork3_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork3_#res.offset] because there is no mapped edge [2019-12-07 18:47:43,825 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L837-1-->L843: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (= (ite (= 0 (ite (= 4 v_~__unbuffered_cnt~0_62) 1 0)) 0 1) v_~main$tmp_guard0~0_8)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_62} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_62, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_8|} AuxVars[] AssignedVars[~main$tmp_guard0~0, ULTIMATE.start_main_#t~nondet18] because there is no mapped edge [2019-12-07 18:47:43,825 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L843-2-->L843-5: Formula: (let ((.cse2 (= |ULTIMATE.start_main_#t~ite19_Out-1898741722| |ULTIMATE.start_main_#t~ite20_Out-1898741722|)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-1898741722 256) 0)) (.cse0 (= (mod ~z$w_buff1_used~0_In-1898741722 256) 0))) (or (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In-1898741722 |ULTIMATE.start_main_#t~ite19_Out-1898741722|) .cse2) (and (= ~z~0_In-1898741722 |ULTIMATE.start_main_#t~ite19_Out-1898741722|) .cse2 (or .cse1 .cse0)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1898741722, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1898741722, ~z$w_buff1~0=~z$w_buff1~0_In-1898741722, ~z~0=~z~0_In-1898741722} OutVars{ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-1898741722|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1898741722, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1898741722, ~z$w_buff1~0=~z$w_buff1~0_In-1898741722, ~z~0=~z~0_In-1898741722, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-1898741722|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 18:47:43,825 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L844-->L844-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1683167558 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-1683167558 256)))) (or (and (= ~z$w_buff0_used~0_In-1683167558 |ULTIMATE.start_main_#t~ite21_Out-1683167558|) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite21_Out-1683167558|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1683167558, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1683167558} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1683167558, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1683167558, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-1683167558|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 18:47:43,826 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [717] [717] L845-->L845-2: Formula: (let ((.cse3 (= (mod ~z$r_buff1_thd0~0_In-276731491 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In-276731491 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-276731491 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-276731491 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite22_Out-276731491|)) (and (or .cse3 .cse2) (= ~z$w_buff1_used~0_In-276731491 |ULTIMATE.start_main_#t~ite22_Out-276731491|) (or .cse1 .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-276731491, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-276731491, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-276731491, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-276731491} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-276731491, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-276731491, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-276731491, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-276731491, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-276731491|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 18:47:43,826 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [711] [711] L846-->L846-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In36371985 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In36371985 256)))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite23_Out36371985|) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite23_Out36371985| ~z$r_buff0_thd0~0_In36371985) (or .cse0 .cse1)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In36371985, ~z$w_buff0_used~0=~z$w_buff0_used~0_In36371985} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In36371985, ~z$w_buff0_used~0=~z$w_buff0_used~0_In36371985, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out36371985|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 18:47:43,826 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] L847-->L847-2: Formula: (let ((.cse2 (= 0 (mod ~z$w_buff1_used~0_In-1795374250 256))) (.cse3 (= (mod ~z$r_buff1_thd0~0_In-1795374250 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1795374250 256))) (.cse1 (= (mod ~z$r_buff0_thd0~0_In-1795374250 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$r_buff1_thd0~0_In-1795374250 |ULTIMATE.start_main_#t~ite24_Out-1795374250|)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1))) (= 0 |ULTIMATE.start_main_#t~ite24_Out-1795374250|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1795374250, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1795374250, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1795374250, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1795374250} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1795374250, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1795374250, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1795374250, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-1795374250|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1795374250} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 18:47:43,827 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L855-->L855-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In680750930 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite30_In680750930| |ULTIMATE.start_main_#t~ite30_Out680750930|) (not .cse0) (= ~z$w_buff0~0_In680750930 |ULTIMATE.start_main_#t~ite31_Out680750930|)) (and .cse0 (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In680750930 256) 0))) (or (and (= 0 (mod ~z$w_buff1_used~0_In680750930 256)) .cse1) (= (mod ~z$w_buff0_used~0_In680750930 256) 0) (and (= (mod ~z$r_buff1_thd0~0_In680750930 256) 0) .cse1))) (= |ULTIMATE.start_main_#t~ite30_Out680750930| ~z$w_buff0~0_In680750930) (= |ULTIMATE.start_main_#t~ite30_Out680750930| |ULTIMATE.start_main_#t~ite31_Out680750930|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In680750930, ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_In680750930|, ~z$w_buff0~0=~z$w_buff0~0_In680750930, ~z$w_buff0_used~0=~z$w_buff0_used~0_In680750930, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In680750930, ~z$w_buff1_used~0=~z$w_buff1_used~0_In680750930, ~weak$$choice2~0=~weak$$choice2~0_In680750930} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In680750930, ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out680750930|, ~z$w_buff0~0=~z$w_buff0~0_In680750930, ~z$w_buff0_used~0=~z$w_buff0_used~0_In680750930, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In680750930, ~z$w_buff1_used~0=~z$w_buff1_used~0_In680750930, ULTIMATE.start_main_#t~ite31=|ULTIMATE.start_main_#t~ite31_Out680750930|, ~weak$$choice2~0=~weak$$choice2~0_In680750930} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite31] because there is no mapped edge [2019-12-07 18:47:43,827 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L856-->L856-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In115977584 256)))) (or (and (= ~z$w_buff1~0_In115977584 |ULTIMATE.start_main_#t~ite34_Out115977584|) (= |ULTIMATE.start_main_#t~ite33_In115977584| |ULTIMATE.start_main_#t~ite33_Out115977584|) (not .cse0)) (and (= ~z$w_buff1~0_In115977584 |ULTIMATE.start_main_#t~ite33_Out115977584|) .cse0 (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In115977584 256) 0))) (or (and .cse1 (= 0 (mod ~z$r_buff1_thd0~0_In115977584 256))) (and .cse1 (= (mod ~z$w_buff1_used~0_In115977584 256) 0)) (= 0 (mod ~z$w_buff0_used~0_In115977584 256)))) (= |ULTIMATE.start_main_#t~ite34_Out115977584| |ULTIMATE.start_main_#t~ite33_Out115977584|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In115977584, ~z$w_buff0_used~0=~z$w_buff0_used~0_In115977584, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In115977584, ~z$w_buff1_used~0=~z$w_buff1_used~0_In115977584, ~z$w_buff1~0=~z$w_buff1~0_In115977584, ~weak$$choice2~0=~weak$$choice2~0_In115977584, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_In115977584|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In115977584, ~z$w_buff0_used~0=~z$w_buff0_used~0_In115977584, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In115977584, ~z$w_buff1_used~0=~z$w_buff1_used~0_In115977584, ~z$w_buff1~0=~z$w_buff1~0_In115977584, ~weak$$choice2~0=~weak$$choice2~0_In115977584, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out115977584|, ULTIMATE.start_main_#t~ite34=|ULTIMATE.start_main_#t~ite34_Out115977584|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_#t~ite34] because there is no mapped edge [2019-12-07 18:47:43,829 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L859-->L860: Formula: (and (= v_~z$r_buff0_thd0~0_108 v_~z$r_buff0_thd0~0_107) (not (= 0 (mod v_~weak$$choice2~0_33 256)))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_108, ~weak$$choice2~0=v_~weak$$choice2~0_33} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_8|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_107, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_9|, ~weak$$choice2~0=v_~weak$$choice2~0_33, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 18:47:43,829 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L860-->L860-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In-654080605 256)))) (or (and (= |ULTIMATE.start_main_#t~ite45_Out-654080605| |ULTIMATE.start_main_#t~ite46_Out-654080605|) (let ((.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-654080605 256)))) (or (and .cse0 (= 0 (mod ~z$r_buff1_thd0~0_In-654080605 256))) (and .cse0 (= 0 (mod ~z$w_buff1_used~0_In-654080605 256))) (= (mod ~z$w_buff0_used~0_In-654080605 256) 0))) (= |ULTIMATE.start_main_#t~ite45_Out-654080605| ~z$r_buff1_thd0~0_In-654080605) .cse1) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite46_Out-654080605| ~z$r_buff1_thd0~0_In-654080605) (= |ULTIMATE.start_main_#t~ite45_In-654080605| |ULTIMATE.start_main_#t~ite45_Out-654080605|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-654080605, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-654080605, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-654080605, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-654080605, ~weak$$choice2~0=~weak$$choice2~0_In-654080605, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In-654080605|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-654080605, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-654080605, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-654080605, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-654080605, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out-654080605|, ~weak$$choice2~0=~weak$$choice2~0_In-654080605, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out-654080605|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45] because there is no mapped edge [2019-12-07 18:47:43,829 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [734] [734] L862-->L4: Formula: (and (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5| (mod v_~main$tmp_guard1~0_8 256)) (not (= 0 (mod v_~z$flush_delayed~0_30 256))) (= v_~z$mem_tmp~0_20 v_~z~0_83) (= 0 v_~z$flush_delayed~0_29)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_20, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_8, ~z$flush_delayed~0=v_~z$flush_delayed~0_30} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_20, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_17|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_8, ~z$flush_delayed~0=v_~z$flush_delayed~0_29, ~z~0=v_~z~0_83, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ULTIMATE.start_main_#t~ite47, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:47:43,829 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_12 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_12 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_12, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:47:43,883 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 06:47:43 BasicIcfg [2019-12-07 18:47:43,883 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 18:47:43,883 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:47:43,883 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:47:43,883 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:47:43,884 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:47:25" (3/4) ... [2019-12-07 18:47:43,886 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 18:47:43,886 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [786] [786] ULTIMATE.startENTRY-->L831: Formula: (let ((.cse0 (store |v_#valid_75| 0 0))) (and (= 0 v_~z$flush_delayed~0_54) (= |v_#NULL.offset_7| 0) (= v_~z$w_buff1_used~0_609 0) (= 0 v_~z$r_buff1_thd3~0_278) (= v_~z$w_buff0_used~0_830 0) (= v_~z$r_buff0_thd1~0_77 0) (= v_~x~0_53 0) (< 0 |v_#StackHeapBarrier_21|) (= v_~z$w_buff0~0_376 0) (= v_~z$r_buff0_thd0~0_415 0) (= v_~z$read_delayed~0_5 0) (= 0 v_~weak$$choice0~0_32) (= v_~z$read_delayed_var~0.base_5 0) (= v_~z$w_buff1~0_367 0) (= v_~weak$$choice2~0_172 0) (= v_~z$r_buff1_thd2~0_207 0) (< |v_#StackHeapBarrier_21| |v_ULTIMATE.start_main_~#t1273~0.base_21|) (= v_~z$r_buff1_thd1~0_207 0) (= v_~z$read_delayed_var~0.offset_5 0) (= v_~y~0_52 0) (= 0 v_~z$r_buff1_thd4~0_260) (= v_~z$mem_tmp~0_37 0) (= |v_ULTIMATE.start_main_~#t1273~0.offset_17| 0) (= 0 v_~z$r_buff0_thd3~0_189) (= v_~__unbuffered_cnt~0_145 0) (= |v_#valid_73| (store .cse0 |v_ULTIMATE.start_main_~#t1273~0.base_21| 1)) (= 0 |v_#NULL.base_7|) (= v_~main$tmp_guard0~0_21 0) (= v_~z~0_157 0) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1273~0.base_21| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1273~0.base_21|) |v_ULTIMATE.start_main_~#t1273~0.offset_17| 0)) |v_#memory_int_23|) (= v_~a~0_207 0) (= 0 v_~z$r_buff0_thd4~0_332) (= 0 v_~__unbuffered_p3_EBX~0_219) (= v_~z$r_buff0_thd2~0_78 0) (= v_~main$tmp_guard1~0_24 0) (= v_~z$r_buff1_thd0~0_431 0) (= v_~b~0_98 0) (= v_~__unbuffered_p3_EAX~0_219 0) (= |v_#length_29| (store |v_#length_30| |v_ULTIMATE.start_main_~#t1273~0.base_21| 4)) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1273~0.base_21|)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_21|, #valid=|v_#valid_75|, #memory_int=|v_#memory_int_24|, #length=|v_#length_30|} OutVars{ULTIMATE.start_main_~#t1274~0.base=|v_ULTIMATE.start_main_~#t1274~0.base_23|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_42|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_207, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_72|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_33|, #NULL.offset=|v_#NULL.offset_7|, ULTIMATE.start_main_~#t1273~0.offset=|v_ULTIMATE.start_main_~#t1273~0.offset_17|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_40|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_35|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_134|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_39|, ~a~0=v_~a~0_207, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_415, ~z$r_buff0_thd4~0=v_~z$r_buff0_thd4~0_332, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_219, #length=|v_#length_29|, ULTIMATE.start_main_~#t1276~0.offset=|v_ULTIMATE.start_main_~#t1276~0.offset_18|, ~z$mem_tmp~0=v_~z$mem_tmp~0_37, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_66|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_41|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_609, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_40|, ULTIMATE.start_main_~#t1275~0.base=|v_ULTIMATE.start_main_~#t1275~0.base_22|, ~z$flush_delayed~0=v_~z$flush_delayed~0_54, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_52|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_76|, ULTIMATE.start_main_~#t1275~0.offset=|v_ULTIMATE.start_main_~#t1275~0.offset_18|, ULTIMATE.start_main_~#t1274~0.offset=|v_ULTIMATE.start_main_~#t1274~0.offset_18|, ~weak$$choice0~0=v_~weak$$choice0~0_32, #StackHeapBarrier=|v_#StackHeapBarrier_21|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_40|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_207, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_9|, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_5, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_189, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_8|, ULTIMATE.start_main_~#t1276~0.base=|v_ULTIMATE.start_main_~#t1276~0.base_23|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_145, ~x~0=v_~x~0_53, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_260, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_36|, ~z$read_delayed~0=v_~z$read_delayed~0_5, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_42|, ~z$w_buff1~0=v_~z$w_buff1~0_367, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_24, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_30|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_5, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_44|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_34|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_36|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_42|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_48|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_431, ULTIMATE.start_main_#t~nondet26=|v_ULTIMATE.start_main_#t~nondet26_56|, ~y~0=v_~y~0_52, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_78, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_830, ~z$w_buff0~0=v_~z$w_buff0~0_376, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_30|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_56|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_278, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_53|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_82|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_21, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_219, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_55|, #NULL.base=|v_#NULL.base_7|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_70|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_34|, ~b~0=v_~b~0_98, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_23|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_9|, ULTIMATE.start_main_~#t1273~0.base=|v_ULTIMATE.start_main_~#t1273~0.base_21|, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_20|, ~z~0=v_~z~0_157, ~weak$$choice2~0=v_~weak$$choice2~0_172, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_77} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1274~0.base, ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_~#t1273~0.offset, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~a~0, ~z$r_buff0_thd0~0, ~z$r_buff0_thd4~0, ~__unbuffered_p3_EAX~0, #length, ULTIMATE.start_main_~#t1276~0.offset, ~z$mem_tmp~0, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_~#t1275~0.base, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_~#t1275~0.offset, ULTIMATE.start_main_~#t1274~0.offset, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ULTIMATE.start_main_#t~nondet15, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ULTIMATE.start_main_#t~nondet17, ULTIMATE.start_main_~#t1276~0.base, ~__unbuffered_cnt~0, ~x~0, ~z$r_buff1_thd4~0, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite30, ~z$r_buff1_thd0~0, ULTIMATE.start_main_#t~nondet26, ~y~0, ~z$r_buff0_thd2~0, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~__unbuffered_p3_EBX~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ~b~0, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t1273~0.base, ULTIMATE.start_main_#t~nondet18, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 18:47:43,886 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L831-1-->L833: Formula: (and (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t1274~0.base_13| 4)) (= |v_#memory_int_15| (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1274~0.base_13| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1274~0.base_13|) |v_ULTIMATE.start_main_~#t1274~0.offset_11| 1))) (= |v_ULTIMATE.start_main_~#t1274~0.offset_11| 0) (= |v_#valid_44| (store |v_#valid_45| |v_ULTIMATE.start_main_~#t1274~0.base_13| 1)) (= 0 (select |v_#valid_45| |v_ULTIMATE.start_main_~#t1274~0.base_13|)) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t1274~0.base_13|) (not (= 0 |v_ULTIMATE.start_main_~#t1274~0.base_13|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_16|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_~#t1274~0.offset=|v_ULTIMATE.start_main_~#t1274~0.offset_11|, #StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_~#t1274~0.base=|v_ULTIMATE.start_main_~#t1274~0.base_13|, #valid=|v_#valid_44|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_6|, #length=|v_#length_21|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1274~0.offset, ULTIMATE.start_main_~#t1274~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length] because there is no mapped edge [2019-12-07 18:47:43,887 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [749] [749] L833-1-->L835: Formula: (and (not (= |v_ULTIMATE.start_main_~#t1275~0.base_11| 0)) (= |v_#valid_40| (store |v_#valid_41| |v_ULTIMATE.start_main_~#t1275~0.base_11| 1)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1275~0.base_11|) (= |v_ULTIMATE.start_main_~#t1275~0.offset_10| 0) (= (select |v_#valid_41| |v_ULTIMATE.start_main_~#t1275~0.base_11|) 0) (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t1275~0.base_11| 4)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1275~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1275~0.base_11|) |v_ULTIMATE.start_main_~#t1275~0.offset_10| 2)) |v_#memory_int_13|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_14|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_6|, #length=|v_#length_19|, ULTIMATE.start_main_~#t1275~0.base=|v_ULTIMATE.start_main_~#t1275~0.base_11|, ULTIMATE.start_main_~#t1275~0.offset=|v_ULTIMATE.start_main_~#t1275~0.offset_10|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length, ULTIMATE.start_main_~#t1275~0.base, ULTIMATE.start_main_~#t1275~0.offset] because there is no mapped edge [2019-12-07 18:47:43,887 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L835-1-->L837: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t1276~0.base_13|)) (= (store |v_#valid_47| |v_ULTIMATE.start_main_~#t1276~0.base_13| 1) |v_#valid_46|) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t1276~0.base_13|) (= (select |v_#valid_47| |v_ULTIMATE.start_main_~#t1276~0.base_13|) 0) (= |v_ULTIMATE.start_main_~#t1276~0.offset_11| 0) (= |v_#memory_int_17| (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1276~0.base_13| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1276~0.base_13|) |v_ULTIMATE.start_main_~#t1276~0.offset_11| 3))) (= |v_#length_23| (store |v_#length_24| |v_ULTIMATE.start_main_~#t1276~0.base_13| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_18|, #length=|v_#length_24|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_~#t1276~0.base=|v_ULTIMATE.start_main_~#t1276~0.base_13|, #length=|v_#length_23|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_5|, ULTIMATE.start_main_~#t1276~0.offset=|v_ULTIMATE.start_main_~#t1276~0.offset_11|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_~#t1276~0.base, #length, ULTIMATE.start_main_#t~nondet17, ULTIMATE.start_main_~#t1276~0.offset] because there is no mapped edge [2019-12-07 18:47:43,887 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L4-->L808: Formula: (and (= v_~z$r_buff0_thd4~0_36 1) (= v_~z$r_buff1_thd2~0_8 v_~z$r_buff0_thd2~0_7) (= v_~z$r_buff0_thd0~0_114 v_~z$r_buff1_thd0~0_75) (= 1 v_~a~0_7) (= v_~z$r_buff0_thd4~0_37 v_~z$r_buff1_thd4~0_34) (= v_~__unbuffered_p3_EAX~0_8 v_~a~0_7) (= v_~z$r_buff1_thd1~0_8 v_~z$r_buff0_thd1~0_7) (= v_~z$r_buff0_thd3~0_42 v_~z$r_buff1_thd3~0_34) (= v_~b~0_17 v_~__unbuffered_p3_EBX~0_8) (not (= v_P3Thread1of1ForFork3___VERIFIER_assert_~expression_16 0))) InVars {P3Thread1of1ForFork3___VERIFIER_assert_~expression=v_P3Thread1of1ForFork3___VERIFIER_assert_~expression_16, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_114, ~b~0=v_~b~0_17, ~z$r_buff0_thd4~0=v_~z$r_buff0_thd4~0_37, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_42, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_7, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_7} OutVars{P3Thread1of1ForFork3___VERIFIER_assert_~expression=v_P3Thread1of1ForFork3___VERIFIER_assert_~expression_16, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_34, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_34, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_8, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_8, ~a~0=v_~a~0_7, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_114, ~b~0=v_~b~0_17, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_75, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_8, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_8, ~z$r_buff0_thd4~0=v_~z$r_buff0_thd4~0_36, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_42, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_7, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_7} AuxVars[] AssignedVars[~a~0, ~z$r_buff1_thd4~0, ~z$r_buff1_thd3~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~__unbuffered_p3_EAX~0, ~z$r_buff0_thd4~0, ~__unbuffered_p3_EBX~0] because there is no mapped edge [2019-12-07 18:47:43,888 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] P0ENTRY-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork0_#res.base_9|) (= v_~b~0_62 1) (= |v_P0Thread1of1ForFork0_#res.offset_9| 0) (= v_P0Thread1of1ForFork0_~arg.offset_19 |v_P0Thread1of1ForFork0_#in~arg.offset_21|) (= v_P0Thread1of1ForFork0_~arg.base_19 |v_P0Thread1of1ForFork0_#in~arg.base_21|) (= v_~__unbuffered_cnt~0_119 (+ v_~__unbuffered_cnt~0_120 1)) (= v_~x~0_42 1)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_21|, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_120} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_21|, P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_9|, ~b~0=v_~b~0_62, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_21|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_9|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_119, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_19, ~x~0=v_~x~0_42, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_19} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, ~b~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P0Thread1of1ForFork0_~arg.base, ~x~0, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 18:47:43,888 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [743] [743] P1ENTRY-->P1EXIT: Formula: (and (= v_P1Thread1of1ForFork1_~arg.base_12 |v_P1Thread1of1ForFork1_#in~arg.base_14|) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= |v_P1Thread1of1ForFork1_#in~arg.offset_14| v_P1Thread1of1ForFork1_~arg.offset_12) (= v_~y~0_33 1) (= v_~x~0_29 2) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_84 1) v_~__unbuffered_cnt~0_83)) InVars {P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_14|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_14|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_84} OutVars{P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_12, P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_12, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_14|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_14|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_83, ~y~0=v_~y~0_33, ~x~0=v_~x~0_29, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1_#res.offset, P1Thread1of1ForFork1_~arg.base, ~__unbuffered_cnt~0, ~y~0, ~x~0, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 18:47:43,888 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [727] [727] L809-->L809-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd4~0_In1339614723 256) 0)) (.cse0 (= (mod ~z$w_buff0_used~0_In1339614723 256) 0))) (or (and (not .cse0) (= 0 |P3Thread1of1ForFork3_#t~ite11_Out1339614723|) (not .cse1)) (and (= |P3Thread1of1ForFork3_#t~ite11_Out1339614723| ~z$w_buff0_used~0_In1339614723) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1339614723, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In1339614723} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1339614723, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In1339614723, P3Thread1of1ForFork3_#t~ite11=|P3Thread1of1ForFork3_#t~ite11_Out1339614723|} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite11] because there is no mapped edge [2019-12-07 18:47:43,889 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [728] [728] L810-->L810-2: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd4~0_In-202933783 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-202933783 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In-202933783 256) 0)) (.cse3 (= 0 (mod ~z$r_buff0_thd4~0_In-202933783 256)))) (or (and (= 0 |P3Thread1of1ForFork3_#t~ite12_Out-202933783|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$w_buff1_used~0_In-202933783 |P3Thread1of1ForFork3_#t~ite12_Out-202933783|) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-202933783, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-202933783, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-202933783, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-202933783} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-202933783, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-202933783, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-202933783, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-202933783, P3Thread1of1ForFork3_#t~ite12=|P3Thread1of1ForFork3_#t~ite12_Out-202933783|} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite12] because there is no mapped edge [2019-12-07 18:47:43,889 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [718] [718] L772-2-->L772-4: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In-1996925979 256) 0)) (.cse0 (= 0 (mod ~z$r_buff1_thd3~0_In-1996925979 256)))) (or (and (or .cse0 .cse1) (= ~z~0_In-1996925979 |P2Thread1of1ForFork2_#t~ite3_Out-1996925979|)) (and (= ~z$w_buff1~0_In-1996925979 |P2Thread1of1ForFork2_#t~ite3_Out-1996925979|) (not .cse1) (not .cse0)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1996925979, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1996925979, ~z$w_buff1~0=~z$w_buff1~0_In-1996925979, ~z~0=~z~0_In-1996925979} OutVars{P2Thread1of1ForFork2_#t~ite3=|P2Thread1of1ForFork2_#t~ite3_Out-1996925979|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1996925979, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1996925979, ~z$w_buff1~0=~z$w_buff1~0_In-1996925979, ~z~0=~z~0_In-1996925979} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 18:47:43,889 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [663] [663] L772-4-->L773: Formula: (= v_~z~0_32 |v_P2Thread1of1ForFork2_#t~ite3_8|) InVars {P2Thread1of1ForFork2_#t~ite3=|v_P2Thread1of1ForFork2_#t~ite3_8|} OutVars{P2Thread1of1ForFork2_#t~ite4=|v_P2Thread1of1ForFork2_#t~ite4_13|, P2Thread1of1ForFork2_#t~ite3=|v_P2Thread1of1ForFork2_#t~ite3_7|, ~z~0=v_~z~0_32} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite4, P2Thread1of1ForFork2_#t~ite3, ~z~0] because there is no mapped edge [2019-12-07 18:47:43,889 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [707] [707] L773-->L773-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In694862629 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In694862629 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P2Thread1of1ForFork2_#t~ite5_Out694862629|)) (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In694862629 |P2Thread1of1ForFork2_#t~ite5_Out694862629|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In694862629, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In694862629} OutVars{P2Thread1of1ForFork2_#t~ite5=|P2Thread1of1ForFork2_#t~ite5_Out694862629|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In694862629, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In694862629} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 18:47:43,889 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L774-->L774-2: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In-915845322 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd3~0_In-915845322 256) 0)) (.cse3 (= 0 (mod ~z$r_buff0_thd3~0_In-915845322 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In-915845322 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork2_#t~ite6_Out-915845322| 0)) (and (= |P2Thread1of1ForFork2_#t~ite6_Out-915845322| ~z$w_buff1_used~0_In-915845322) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-915845322, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-915845322, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-915845322, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-915845322} OutVars{P2Thread1of1ForFork2_#t~ite6=|P2Thread1of1ForFork2_#t~ite6_Out-915845322|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-915845322, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-915845322, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-915845322, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-915845322} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 18:47:43,890 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L775-->L775-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In-1526394517 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-1526394517 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |P2Thread1of1ForFork2_#t~ite7_Out-1526394517|)) (and (or .cse0 .cse1) (= ~z$r_buff0_thd3~0_In-1526394517 |P2Thread1of1ForFork2_#t~ite7_Out-1526394517|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1526394517, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1526394517} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1526394517, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1526394517, P2Thread1of1ForFork2_#t~ite7=|P2Thread1of1ForFork2_#t~ite7_Out-1526394517|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 18:47:43,890 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L776-->L776-2: Formula: (let ((.cse3 (= 0 (mod ~z$w_buff1_used~0_In-812263784 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In-812263784 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-812263784 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-812263784 256)))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite8_Out-812263784|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse0 .cse1) (= ~z$r_buff1_thd3~0_In-812263784 |P2Thread1of1ForFork2_#t~ite8_Out-812263784|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-812263784, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-812263784, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-812263784, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-812263784} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-812263784, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-812263784, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-812263784, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-812263784, P2Thread1of1ForFork2_#t~ite8=|P2Thread1of1ForFork2_#t~ite8_Out-812263784|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 18:47:43,890 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [739] [739] L776-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= |v_P2Thread1of1ForFork2_#t~ite8_34| v_~z$r_buff1_thd3~0_64) (= v_~__unbuffered_cnt~0_77 (+ v_~__unbuffered_cnt~0_78 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_78, P2Thread1of1ForFork2_#t~ite8=|v_P2Thread1of1ForFork2_#t~ite8_34|} OutVars{~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_64, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_77, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|, P2Thread1of1ForFork2_#t~ite8=|v_P2Thread1of1ForFork2_#t~ite8_33|} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset, P2Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 18:47:43,890 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L811-->L812: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In159571 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd4~0_In159571 256))) (.cse0 (= ~z$r_buff0_thd4~0_Out159571 ~z$r_buff0_thd4~0_In159571))) (or (and .cse0 .cse1) (and (not .cse1) (= 0 ~z$r_buff0_thd4~0_Out159571) (not .cse2)) (and .cse2 .cse0))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In159571, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In159571} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In159571, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out159571, P3Thread1of1ForFork3_#t~ite13=|P3Thread1of1ForFork3_#t~ite13_Out159571|} AuxVars[] AssignedVars[~z$r_buff0_thd4~0, P3Thread1of1ForFork3_#t~ite13] because there is no mapped edge [2019-12-07 18:47:43,891 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L812-->L812-2: Formula: (let ((.cse2 (= (mod ~z$w_buff1_used~0_In1945376630 256) 0)) (.cse3 (= (mod ~z$r_buff1_thd4~0_In1945376630 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd4~0_In1945376630 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In1945376630 256) 0))) (or (and (= 0 |P3Thread1of1ForFork3_#t~ite14_Out1945376630|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P3Thread1of1ForFork3_#t~ite14_Out1945376630| ~z$r_buff1_thd4~0_In1945376630) (or .cse2 .cse3) (or .cse0 .cse1)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In1945376630, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1945376630, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In1945376630, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1945376630} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In1945376630, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1945376630, P3Thread1of1ForFork3_#t~ite14=|P3Thread1of1ForFork3_#t~ite14_Out1945376630|, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In1945376630, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1945376630} AuxVars[] AssignedVars[P3Thread1of1ForFork3_#t~ite14] because there is no mapped edge [2019-12-07 18:47:43,891 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [750] [750] L812-2-->P3EXIT: Formula: (and (= v_~__unbuffered_cnt~0_107 (+ v_~__unbuffered_cnt~0_108 1)) (= 0 |v_P3Thread1of1ForFork3_#res.base_3|) (= 0 |v_P3Thread1of1ForFork3_#res.offset_3|) (= |v_P3Thread1of1ForFork3_#t~ite14_44| v_~z$r_buff1_thd4~0_75)) InVars {P3Thread1of1ForFork3_#t~ite14=|v_P3Thread1of1ForFork3_#t~ite14_44|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_108} OutVars{~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_75, P3Thread1of1ForFork3_#t~ite14=|v_P3Thread1of1ForFork3_#t~ite14_43|, P3Thread1of1ForFork3_#res.base=|v_P3Thread1of1ForFork3_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_107, P3Thread1of1ForFork3_#res.offset=|v_P3Thread1of1ForFork3_#res.offset_3|} AuxVars[] AssignedVars[~z$r_buff1_thd4~0, P3Thread1of1ForFork3_#t~ite14, P3Thread1of1ForFork3_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork3_#res.offset] because there is no mapped edge [2019-12-07 18:47:43,891 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L837-1-->L843: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (= (ite (= 0 (ite (= 4 v_~__unbuffered_cnt~0_62) 1 0)) 0 1) v_~main$tmp_guard0~0_8)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_62} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_62, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_8|} AuxVars[] AssignedVars[~main$tmp_guard0~0, ULTIMATE.start_main_#t~nondet18] because there is no mapped edge [2019-12-07 18:47:43,891 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L843-2-->L843-5: Formula: (let ((.cse2 (= |ULTIMATE.start_main_#t~ite19_Out-1898741722| |ULTIMATE.start_main_#t~ite20_Out-1898741722|)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-1898741722 256) 0)) (.cse0 (= (mod ~z$w_buff1_used~0_In-1898741722 256) 0))) (or (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In-1898741722 |ULTIMATE.start_main_#t~ite19_Out-1898741722|) .cse2) (and (= ~z~0_In-1898741722 |ULTIMATE.start_main_#t~ite19_Out-1898741722|) .cse2 (or .cse1 .cse0)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1898741722, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1898741722, ~z$w_buff1~0=~z$w_buff1~0_In-1898741722, ~z~0=~z~0_In-1898741722} OutVars{ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-1898741722|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1898741722, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1898741722, ~z$w_buff1~0=~z$w_buff1~0_In-1898741722, ~z~0=~z~0_In-1898741722, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-1898741722|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 18:47:43,891 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L844-->L844-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1683167558 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-1683167558 256)))) (or (and (= ~z$w_buff0_used~0_In-1683167558 |ULTIMATE.start_main_#t~ite21_Out-1683167558|) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite21_Out-1683167558|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1683167558, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1683167558} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1683167558, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1683167558, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-1683167558|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 18:47:43,892 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [717] [717] L845-->L845-2: Formula: (let ((.cse3 (= (mod ~z$r_buff1_thd0~0_In-276731491 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In-276731491 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-276731491 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-276731491 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite22_Out-276731491|)) (and (or .cse3 .cse2) (= ~z$w_buff1_used~0_In-276731491 |ULTIMATE.start_main_#t~ite22_Out-276731491|) (or .cse1 .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-276731491, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-276731491, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-276731491, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-276731491} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-276731491, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-276731491, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-276731491, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-276731491, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-276731491|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 18:47:43,892 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [711] [711] L846-->L846-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In36371985 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In36371985 256)))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite23_Out36371985|) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite23_Out36371985| ~z$r_buff0_thd0~0_In36371985) (or .cse0 .cse1)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In36371985, ~z$w_buff0_used~0=~z$w_buff0_used~0_In36371985} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In36371985, ~z$w_buff0_used~0=~z$w_buff0_used~0_In36371985, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out36371985|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 18:47:43,892 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] L847-->L847-2: Formula: (let ((.cse2 (= 0 (mod ~z$w_buff1_used~0_In-1795374250 256))) (.cse3 (= (mod ~z$r_buff1_thd0~0_In-1795374250 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1795374250 256))) (.cse1 (= (mod ~z$r_buff0_thd0~0_In-1795374250 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$r_buff1_thd0~0_In-1795374250 |ULTIMATE.start_main_#t~ite24_Out-1795374250|)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1))) (= 0 |ULTIMATE.start_main_#t~ite24_Out-1795374250|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1795374250, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1795374250, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1795374250, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1795374250} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1795374250, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1795374250, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1795374250, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-1795374250|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1795374250} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 18:47:43,893 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L855-->L855-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In680750930 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite30_In680750930| |ULTIMATE.start_main_#t~ite30_Out680750930|) (not .cse0) (= ~z$w_buff0~0_In680750930 |ULTIMATE.start_main_#t~ite31_Out680750930|)) (and .cse0 (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In680750930 256) 0))) (or (and (= 0 (mod ~z$w_buff1_used~0_In680750930 256)) .cse1) (= (mod ~z$w_buff0_used~0_In680750930 256) 0) (and (= (mod ~z$r_buff1_thd0~0_In680750930 256) 0) .cse1))) (= |ULTIMATE.start_main_#t~ite30_Out680750930| ~z$w_buff0~0_In680750930) (= |ULTIMATE.start_main_#t~ite30_Out680750930| |ULTIMATE.start_main_#t~ite31_Out680750930|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In680750930, ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_In680750930|, ~z$w_buff0~0=~z$w_buff0~0_In680750930, ~z$w_buff0_used~0=~z$w_buff0_used~0_In680750930, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In680750930, ~z$w_buff1_used~0=~z$w_buff1_used~0_In680750930, ~weak$$choice2~0=~weak$$choice2~0_In680750930} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In680750930, ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out680750930|, ~z$w_buff0~0=~z$w_buff0~0_In680750930, ~z$w_buff0_used~0=~z$w_buff0_used~0_In680750930, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In680750930, ~z$w_buff1_used~0=~z$w_buff1_used~0_In680750930, ULTIMATE.start_main_#t~ite31=|ULTIMATE.start_main_#t~ite31_Out680750930|, ~weak$$choice2~0=~weak$$choice2~0_In680750930} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite31] because there is no mapped edge [2019-12-07 18:47:43,894 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L856-->L856-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In115977584 256)))) (or (and (= ~z$w_buff1~0_In115977584 |ULTIMATE.start_main_#t~ite34_Out115977584|) (= |ULTIMATE.start_main_#t~ite33_In115977584| |ULTIMATE.start_main_#t~ite33_Out115977584|) (not .cse0)) (and (= ~z$w_buff1~0_In115977584 |ULTIMATE.start_main_#t~ite33_Out115977584|) .cse0 (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In115977584 256) 0))) (or (and .cse1 (= 0 (mod ~z$r_buff1_thd0~0_In115977584 256))) (and .cse1 (= (mod ~z$w_buff1_used~0_In115977584 256) 0)) (= 0 (mod ~z$w_buff0_used~0_In115977584 256)))) (= |ULTIMATE.start_main_#t~ite34_Out115977584| |ULTIMATE.start_main_#t~ite33_Out115977584|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In115977584, ~z$w_buff0_used~0=~z$w_buff0_used~0_In115977584, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In115977584, ~z$w_buff1_used~0=~z$w_buff1_used~0_In115977584, ~z$w_buff1~0=~z$w_buff1~0_In115977584, ~weak$$choice2~0=~weak$$choice2~0_In115977584, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_In115977584|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In115977584, ~z$w_buff0_used~0=~z$w_buff0_used~0_In115977584, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In115977584, ~z$w_buff1_used~0=~z$w_buff1_used~0_In115977584, ~z$w_buff1~0=~z$w_buff1~0_In115977584, ~weak$$choice2~0=~weak$$choice2~0_In115977584, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out115977584|, ULTIMATE.start_main_#t~ite34=|ULTIMATE.start_main_#t~ite34_Out115977584|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_#t~ite34] because there is no mapped edge [2019-12-07 18:47:43,895 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L859-->L860: Formula: (and (= v_~z$r_buff0_thd0~0_108 v_~z$r_buff0_thd0~0_107) (not (= 0 (mod v_~weak$$choice2~0_33 256)))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_108, ~weak$$choice2~0=v_~weak$$choice2~0_33} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_8|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_107, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_9|, ~weak$$choice2~0=v_~weak$$choice2~0_33, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 18:47:43,895 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L860-->L860-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In-654080605 256)))) (or (and (= |ULTIMATE.start_main_#t~ite45_Out-654080605| |ULTIMATE.start_main_#t~ite46_Out-654080605|) (let ((.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-654080605 256)))) (or (and .cse0 (= 0 (mod ~z$r_buff1_thd0~0_In-654080605 256))) (and .cse0 (= 0 (mod ~z$w_buff1_used~0_In-654080605 256))) (= (mod ~z$w_buff0_used~0_In-654080605 256) 0))) (= |ULTIMATE.start_main_#t~ite45_Out-654080605| ~z$r_buff1_thd0~0_In-654080605) .cse1) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite46_Out-654080605| ~z$r_buff1_thd0~0_In-654080605) (= |ULTIMATE.start_main_#t~ite45_In-654080605| |ULTIMATE.start_main_#t~ite45_Out-654080605|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-654080605, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-654080605, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-654080605, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-654080605, ~weak$$choice2~0=~weak$$choice2~0_In-654080605, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In-654080605|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-654080605, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-654080605, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-654080605, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-654080605, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out-654080605|, ~weak$$choice2~0=~weak$$choice2~0_In-654080605, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out-654080605|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45] because there is no mapped edge [2019-12-07 18:47:43,895 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [734] [734] L862-->L4: Formula: (and (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5| (mod v_~main$tmp_guard1~0_8 256)) (not (= 0 (mod v_~z$flush_delayed~0_30 256))) (= v_~z$mem_tmp~0_20 v_~z~0_83) (= 0 v_~z$flush_delayed~0_29)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_20, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_8, ~z$flush_delayed~0=v_~z$flush_delayed~0_30} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_20, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_17|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_8, ~z$flush_delayed~0=v_~z$flush_delayed~0_29, ~z~0=v_~z~0_83, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ULTIMATE.start_main_#t~ite47, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:47:43,895 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_12 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_12 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_12, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:47:43,965 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_261dc733-82d1-4812-b451-301b6bcff852/bin/uautomizer/witness.graphml [2019-12-07 18:47:43,965 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:47:43,966 INFO L168 Benchmark]: Toolchain (without parser) took 19816.93 ms. Allocated memory was 1.0 GB in the beginning and 2.9 GB in the end (delta: 1.9 GB). Free memory was 932.6 MB in the beginning and 2.2 GB in the end (delta: -1.3 GB). Peak memory consumption was 1.7 GB. Max. memory is 11.5 GB. [2019-12-07 18:47:43,966 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:47:43,967 INFO L168 Benchmark]: CACSL2BoogieTranslator took 381.47 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 115.9 MB). Free memory was 932.6 MB in the beginning and 1.1 GB in the end (delta: -151.0 MB). Peak memory consumption was 18.3 MB. Max. memory is 11.5 GB. [2019-12-07 18:47:43,967 INFO L168 Benchmark]: Boogie Procedure Inliner took 41.83 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:47:43,967 INFO L168 Benchmark]: Boogie Preprocessor took 25.69 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:47:43,967 INFO L168 Benchmark]: RCFGBuilder took 412.79 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 51.4 MB). Peak memory consumption was 51.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:47:43,968 INFO L168 Benchmark]: TraceAbstraction took 18869.62 ms. Allocated memory was 1.1 GB in the beginning and 2.4 GB in the end (delta: 1.3 GB). Free memory was 1.0 GB in the beginning and 624.5 MB in the end (delta: 396.9 MB). Peak memory consumption was 1.7 GB. Max. memory is 11.5 GB. [2019-12-07 18:47:43,968 INFO L168 Benchmark]: Witness Printer took 82.11 ms. Allocated memory was 2.4 GB in the beginning and 2.9 GB in the end (delta: 452.5 MB). Free memory was 624.5 MB in the beginning and 2.2 GB in the end (delta: -1.6 GB). Peak memory consumption was 16.6 MB. Max. memory is 11.5 GB. [2019-12-07 18:47:43,970 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 381.47 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 115.9 MB). Free memory was 932.6 MB in the beginning and 1.1 GB in the end (delta: -151.0 MB). Peak memory consumption was 18.3 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 41.83 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 25.69 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 412.79 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 51.4 MB). Peak memory consumption was 51.4 MB. Max. memory is 11.5 GB. * TraceAbstraction took 18869.62 ms. Allocated memory was 1.1 GB in the beginning and 2.4 GB in the end (delta: 1.3 GB). Free memory was 1.0 GB in the beginning and 624.5 MB in the end (delta: 396.9 MB). Peak memory consumption was 1.7 GB. Max. memory is 11.5 GB. * Witness Printer took 82.11 ms. Allocated memory was 2.4 GB in the beginning and 2.9 GB in the end (delta: 452.5 MB). Free memory was 624.5 MB in the beginning and 2.2 GB in the end (delta: -1.6 GB). Peak memory consumption was 16.6 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.1s, 180 ProgramPointsBefore, 89 ProgramPointsAfterwards, 208 TransitionsBefore, 95 TransitionsAfterwards, 12668 CoEnabledTransitionPairs, 7 FixpointIterations, 36 TrivialSequentialCompositions, 50 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 36 ConcurrentYvCompositions, 27 ChoiceCompositions, 5121 VarBasedMoverChecksPositive, 269 VarBasedMoverChecksNegative, 136 SemBasedMoverChecksPositive, 198 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.7s, 0 MoverChecksTotal, 49999 CheckedPairsTotal, 122 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L831] FCALL, FORK 0 pthread_create(&t1273, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L833] FCALL, FORK 0 pthread_create(&t1274, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L835] FCALL, FORK 0 pthread_create(&t1275, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L837] FCALL, FORK 0 pthread_create(&t1276, ((void *)0), P3, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L786] 4 z$w_buff1 = z$w_buff0 [L787] 4 z$w_buff0 = 2 [L788] 4 z$w_buff1_used = z$w_buff0_used [L789] 4 z$w_buff0_used = (_Bool)1 [L808] EXPR 4 z$w_buff0_used && z$r_buff0_thd4 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd4 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L766] 3 y = 2 [L769] 3 z = 1 VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=2, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L808] 4 z = z$w_buff0_used && z$r_buff0_thd4 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd4 ? z$w_buff1 : z) [L772] 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=2, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L809] 4 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd4 ? (_Bool)0 : z$w_buff0_used [L773] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L774] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L775] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L810] 4 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd4 || z$w_buff1_used && z$r_buff1_thd4 ? (_Bool)0 : z$w_buff1_used [L843] EXPR 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L843] 0 z = z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) [L844] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L845] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L846] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L847] 0 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L850] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L851] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L852] 0 z$flush_delayed = weak$$choice2 [L853] 0 z$mem_tmp = z VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L854] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L854] 0 z = !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) [L855] 0 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) [L856] 0 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) [L857] EXPR 0 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L857] 0 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) [L858] EXPR 0 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L858] 0 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L860] 0 z$r_buff1_thd0 = weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L861] 0 main$tmp_guard1 = !(x == 2 && y == 2 && z == 2 && __unbuffered_p3_EAX == 1 && __unbuffered_p3_EBX == 0) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 168 locations, 2 error locations. Result: UNSAFE, OverallTime: 18.7s, OverallIterations: 23, TraceHistogramMax: 1, AutomataDifference: 5.3s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 2403 SDtfs, 2313 SDslu, 6759 SDs, 0 SdLazy, 3408 SolverSat, 216 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 218 GetRequests, 43 SyntacticMatches, 13 SemanticMatches, 162 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 316 ImplicationChecksByTransitivity, 1.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=52914occurred in iteration=4, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 6.0s AutomataMinimizationTime, 22 MinimizatonAttempts, 33119 StatesRemovedByMinimization, 17 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.3s InterpolantComputationTime, 1081 NumberOfCodeBlocks, 1081 NumberOfCodeBlocksAsserted, 23 NumberOfCheckSat, 999 ConstructedInterpolants, 0 QuantifiedInterpolants, 227854 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 22 InterpolantComputations, 22 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...