./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix053_tso.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_464aa81c-7005-4763-90d5-511086e375c5/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_464aa81c-7005-4763-90d5-511086e375c5/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_464aa81c-7005-4763-90d5-511086e375c5/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_464aa81c-7005-4763-90d5-511086e375c5/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix053_tso.oepc.i -s /tmp/vcloud-vcloud-master/worker/run_dir_464aa81c-7005-4763-90d5-511086e375c5/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_464aa81c-7005-4763-90d5-511086e375c5/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 3b2177d57090ed0cb996ff1637f1929a86099f24 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 17:28:41,136 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 17:28:41,137 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 17:28:41,145 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 17:28:41,145 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 17:28:41,146 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 17:28:41,147 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 17:28:41,148 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 17:28:41,149 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 17:28:41,150 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 17:28:41,151 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 17:28:41,151 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 17:28:41,152 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 17:28:41,152 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 17:28:41,153 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 17:28:41,154 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 17:28:41,154 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 17:28:41,155 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 17:28:41,157 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 17:28:41,158 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 17:28:41,159 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 17:28:41,160 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 17:28:41,161 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 17:28:41,161 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 17:28:41,163 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 17:28:41,163 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 17:28:41,163 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 17:28:41,164 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 17:28:41,164 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 17:28:41,165 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 17:28:41,165 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 17:28:41,165 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 17:28:41,166 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 17:28:41,166 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 17:28:41,167 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 17:28:41,167 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 17:28:41,167 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 17:28:41,167 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 17:28:41,167 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 17:28:41,168 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 17:28:41,168 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 17:28:41,169 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_464aa81c-7005-4763-90d5-511086e375c5/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 17:28:41,178 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 17:28:41,178 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 17:28:41,179 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 17:28:41,179 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 17:28:41,179 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 17:28:41,179 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 17:28:41,179 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 17:28:41,180 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 17:28:41,180 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 17:28:41,180 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 17:28:41,180 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 17:28:41,180 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 17:28:41,180 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 17:28:41,180 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 17:28:41,180 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 17:28:41,180 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 17:28:41,181 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 17:28:41,181 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 17:28:41,181 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 17:28:41,181 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 17:28:41,181 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 17:28:41,181 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:28:41,181 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 17:28:41,182 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 17:28:41,182 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 17:28:41,182 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 17:28:41,182 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 17:28:41,182 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 17:28:41,182 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 17:28:41,182 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_464aa81c-7005-4763-90d5-511086e375c5/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 3b2177d57090ed0cb996ff1637f1929a86099f24 [2019-12-07 17:28:41,283 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 17:28:41,291 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 17:28:41,293 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 17:28:41,294 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 17:28:41,294 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 17:28:41,295 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_464aa81c-7005-4763-90d5-511086e375c5/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix053_tso.oepc.i [2019-12-07 17:28:41,331 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_464aa81c-7005-4763-90d5-511086e375c5/bin/uautomizer/data/49094cd56/e987a387b44846c8887945ac2b553e6b/FLAG45066703b [2019-12-07 17:28:41,732 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 17:28:41,732 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_464aa81c-7005-4763-90d5-511086e375c5/sv-benchmarks/c/pthread-wmm/mix053_tso.oepc.i [2019-12-07 17:28:41,742 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_464aa81c-7005-4763-90d5-511086e375c5/bin/uautomizer/data/49094cd56/e987a387b44846c8887945ac2b553e6b/FLAG45066703b [2019-12-07 17:28:41,751 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_464aa81c-7005-4763-90d5-511086e375c5/bin/uautomizer/data/49094cd56/e987a387b44846c8887945ac2b553e6b [2019-12-07 17:28:41,753 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 17:28:41,754 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 17:28:41,754 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 17:28:41,755 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 17:28:41,757 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 17:28:41,757 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:28:41" (1/1) ... [2019-12-07 17:28:41,759 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6c5fb732 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:28:41, skipping insertion in model container [2019-12-07 17:28:41,759 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:28:41" (1/1) ... [2019-12-07 17:28:41,763 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 17:28:41,790 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 17:28:42,044 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:28:42,051 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 17:28:42,092 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:28:42,138 INFO L208 MainTranslator]: Completed translation [2019-12-07 17:28:42,139 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:28:42 WrapperNode [2019-12-07 17:28:42,139 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 17:28:42,139 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 17:28:42,139 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 17:28:42,139 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 17:28:42,145 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:28:42" (1/1) ... [2019-12-07 17:28:42,158 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:28:42" (1/1) ... [2019-12-07 17:28:42,179 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 17:28:42,180 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 17:28:42,180 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 17:28:42,180 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 17:28:42,186 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:28:42" (1/1) ... [2019-12-07 17:28:42,186 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:28:42" (1/1) ... [2019-12-07 17:28:42,189 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:28:42" (1/1) ... [2019-12-07 17:28:42,190 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:28:42" (1/1) ... [2019-12-07 17:28:42,197 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:28:42" (1/1) ... [2019-12-07 17:28:42,200 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:28:42" (1/1) ... [2019-12-07 17:28:42,202 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:28:42" (1/1) ... [2019-12-07 17:28:42,206 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 17:28:42,206 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 17:28:42,206 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 17:28:42,206 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 17:28:42,207 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:28:42" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_464aa81c-7005-4763-90d5-511086e375c5/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:28:42,247 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 17:28:42,248 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 17:28:42,248 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 17:28:42,248 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 17:28:42,248 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 17:28:42,248 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 17:28:42,248 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 17:28:42,248 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 17:28:42,248 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 17:28:42,248 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 17:28:42,248 INFO L130 BoogieDeclarations]: Found specification of procedure P3 [2019-12-07 17:28:42,248 INFO L138 BoogieDeclarations]: Found implementation of procedure P3 [2019-12-07 17:28:42,249 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 17:28:42,249 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 17:28:42,249 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 17:28:42,250 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 17:28:42,629 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 17:28:42,629 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 17:28:42,630 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:28:42 BoogieIcfgContainer [2019-12-07 17:28:42,631 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 17:28:42,631 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 17:28:42,631 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 17:28:42,633 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 17:28:42,633 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 05:28:41" (1/3) ... [2019-12-07 17:28:42,634 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@343c5fb5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:28:42, skipping insertion in model container [2019-12-07 17:28:42,634 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:28:42" (2/3) ... [2019-12-07 17:28:42,634 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@343c5fb5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:28:42, skipping insertion in model container [2019-12-07 17:28:42,634 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:28:42" (3/3) ... [2019-12-07 17:28:42,635 INFO L109 eAbstractionObserver]: Analyzing ICFG mix053_tso.oepc.i [2019-12-07 17:28:42,642 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 17:28:42,642 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 17:28:42,647 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 17:28:42,647 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 17:28:42,673 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,673 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,673 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,673 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,673 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,674 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,674 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,674 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,674 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork3_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,674 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork3_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,674 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,674 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,675 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,675 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,675 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,675 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,675 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,675 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,675 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,675 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,676 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,676 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,676 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,676 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,676 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,676 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,676 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,676 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,676 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,677 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,677 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,677 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,677 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,677 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,677 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,677 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,678 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,678 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,678 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,678 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,678 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,678 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,678 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,679 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,679 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,679 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,679 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,679 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,679 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,679 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,679 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,682 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,682 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,682 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,682 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,682 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,682 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,682 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,682 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,683 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,683 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,683 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,683 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,683 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,683 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,683 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,683 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,683 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,684 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,684 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,684 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,684 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,684 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,684 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,684 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,684 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,684 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,685 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,685 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,685 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,685 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:28:42,697 INFO L249 AbstractCegarLoop]: Starting to check reachability of 7 error locations. [2019-12-07 17:28:42,709 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 17:28:42,710 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 17:28:42,710 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 17:28:42,710 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 17:28:42,710 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 17:28:42,710 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 17:28:42,710 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 17:28:42,710 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 17:28:42,721 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 191 places, 225 transitions [2019-12-07 17:28:42,722 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 191 places, 225 transitions [2019-12-07 17:28:42,780 INFO L134 PetriNetUnfolder]: 47/221 cut-off events. [2019-12-07 17:28:42,780 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 17:28:42,791 INFO L76 FinitePrefix]: Finished finitePrefix Result has 234 conditions, 221 events. 47/221 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 578 event pairs. 12/184 useless extension candidates. Maximal degree in co-relation 190. Up to 2 conditions per place. [2019-12-07 17:28:42,806 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 191 places, 225 transitions [2019-12-07 17:28:42,838 INFO L134 PetriNetUnfolder]: 47/221 cut-off events. [2019-12-07 17:28:42,838 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 17:28:42,843 INFO L76 FinitePrefix]: Finished finitePrefix Result has 234 conditions, 221 events. 47/221 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 578 event pairs. 12/184 useless extension candidates. Maximal degree in co-relation 190. Up to 2 conditions per place. [2019-12-07 17:28:42,858 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 18432 [2019-12-07 17:28:42,859 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 17:28:45,835 WARN L192 SmtUtils]: Spent 163.00 ms on a formula simplification. DAG size of input: 95 DAG size of output: 93 [2019-12-07 17:28:45,965 INFO L206 etLargeBlockEncoding]: Checked pairs total: 90358 [2019-12-07 17:28:45,966 INFO L214 etLargeBlockEncoding]: Total number of compositions: 120 [2019-12-07 17:28:45,968 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 102 places, 111 transitions [2019-12-07 17:29:33,418 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 225010 states. [2019-12-07 17:29:33,420 INFO L276 IsEmpty]: Start isEmpty. Operand 225010 states. [2019-12-07 17:29:33,423 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-12-07 17:29:33,423 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:29:33,424 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:33,424 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:29:33,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:33,428 INFO L82 PathProgramCache]: Analyzing trace with hash -544334600, now seen corresponding path program 1 times [2019-12-07 17:29:33,433 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:33,433 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2073847954] [2019-12-07 17:29:33,433 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:33,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:33,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:33,583 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2073847954] [2019-12-07 17:29:33,584 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:33,584 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 17:29:33,585 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1611937321] [2019-12-07 17:29:33,588 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:29:33,588 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:33,597 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:29:33,597 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:33,598 INFO L87 Difference]: Start difference. First operand 225010 states. Second operand 3 states. [2019-12-07 17:29:36,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:36,739 INFO L93 Difference]: Finished difference Result 224242 states and 1068870 transitions. [2019-12-07 17:29:36,740 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:29:36,740 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-12-07 17:29:36,741 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:29:37,657 INFO L225 Difference]: With dead ends: 224242 [2019-12-07 17:29:37,657 INFO L226 Difference]: Without dead ends: 219874 [2019-12-07 17:29:37,658 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:45,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219874 states. [2019-12-07 17:29:48,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219874 to 219874. [2019-12-07 17:29:48,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 219874 states. [2019-12-07 17:29:49,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219874 states to 219874 states and 1048850 transitions. [2019-12-07 17:29:49,385 INFO L78 Accepts]: Start accepts. Automaton has 219874 states and 1048850 transitions. Word has length 7 [2019-12-07 17:29:49,386 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:29:49,386 INFO L462 AbstractCegarLoop]: Abstraction has 219874 states and 1048850 transitions. [2019-12-07 17:29:49,386 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:29:49,386 INFO L276 IsEmpty]: Start isEmpty. Operand 219874 states and 1048850 transitions. [2019-12-07 17:29:49,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 17:29:49,392 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:29:49,392 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:49,392 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:29:49,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:49,393 INFO L82 PathProgramCache]: Analyzing trace with hash 1188084738, now seen corresponding path program 1 times [2019-12-07 17:29:49,393 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:49,393 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049870731] [2019-12-07 17:29:49,393 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:49,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:49,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:49,471 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2049870731] [2019-12-07 17:29:49,471 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:49,471 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:29:49,471 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1019440910] [2019-12-07 17:29:49,472 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:29:49,472 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:49,473 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:29:49,473 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:29:49,473 INFO L87 Difference]: Start difference. First operand 219874 states and 1048850 transitions. Second operand 4 states. [2019-12-07 17:29:51,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:51,325 INFO L93 Difference]: Finished difference Result 353090 states and 1624232 transitions. [2019-12-07 17:29:51,326 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:29:51,326 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 17:29:51,326 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:29:56,401 INFO L225 Difference]: With dead ends: 353090 [2019-12-07 17:29:56,401 INFO L226 Difference]: Without dead ends: 352992 [2019-12-07 17:29:56,402 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:30:05,593 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 352992 states. [2019-12-07 17:30:10,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 352992 to 319358. [2019-12-07 17:30:10,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 319358 states. [2019-12-07 17:30:11,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 319358 states to 319358 states and 1483718 transitions. [2019-12-07 17:30:11,757 INFO L78 Accepts]: Start accepts. Automaton has 319358 states and 1483718 transitions. Word has length 13 [2019-12-07 17:30:11,758 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:30:11,758 INFO L462 AbstractCegarLoop]: Abstraction has 319358 states and 1483718 transitions. [2019-12-07 17:30:11,758 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:30:11,758 INFO L276 IsEmpty]: Start isEmpty. Operand 319358 states and 1483718 transitions. [2019-12-07 17:30:11,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 17:30:11,761 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:30:11,761 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:30:11,762 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:30:11,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:30:11,762 INFO L82 PathProgramCache]: Analyzing trace with hash 1434409872, now seen corresponding path program 1 times [2019-12-07 17:30:11,762 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:30:11,762 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1992582958] [2019-12-07 17:30:11,762 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:30:11,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:11,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:30:11,815 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1992582958] [2019-12-07 17:30:11,816 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:30:11,816 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:30:11,816 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1059278655] [2019-12-07 17:30:11,816 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:30:11,816 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:30:11,816 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:30:11,816 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:30:11,816 INFO L87 Difference]: Start difference. First operand 319358 states and 1483718 transitions. Second operand 4 states. [2019-12-07 17:30:17,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:30:17,713 INFO L93 Difference]: Finished difference Result 402462 states and 1845978 transitions. [2019-12-07 17:30:17,714 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:30:17,714 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 17:30:17,714 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:30:18,901 INFO L225 Difference]: With dead ends: 402462 [2019-12-07 17:30:18,901 INFO L226 Difference]: Without dead ends: 402462 [2019-12-07 17:30:18,902 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:30:28,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 402462 states. [2019-12-07 17:30:34,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 402462 to 357810. [2019-12-07 17:30:34,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 357810 states. [2019-12-07 17:30:35,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 357810 states to 357810 states and 1654236 transitions. [2019-12-07 17:30:35,834 INFO L78 Accepts]: Start accepts. Automaton has 357810 states and 1654236 transitions. Word has length 15 [2019-12-07 17:30:35,834 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:30:35,834 INFO L462 AbstractCegarLoop]: Abstraction has 357810 states and 1654236 transitions. [2019-12-07 17:30:35,834 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:30:35,834 INFO L276 IsEmpty]: Start isEmpty. Operand 357810 states and 1654236 transitions. [2019-12-07 17:30:35,838 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 17:30:35,838 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:30:35,838 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:30:35,838 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:30:35,838 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:30:35,838 INFO L82 PathProgramCache]: Analyzing trace with hash -784300791, now seen corresponding path program 1 times [2019-12-07 17:30:35,838 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:30:35,838 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1784646419] [2019-12-07 17:30:35,838 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:30:35,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:35,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:30:35,895 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1784646419] [2019-12-07 17:30:35,895 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:30:35,895 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:30:35,895 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1240775043] [2019-12-07 17:30:35,895 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:30:35,895 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:30:35,896 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:30:35,896 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:30:35,896 INFO L87 Difference]: Start difference. First operand 357810 states and 1654236 transitions. Second operand 4 states. [2019-12-07 17:30:42,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:30:42,817 INFO L93 Difference]: Finished difference Result 493966 states and 2247286 transitions. [2019-12-07 17:30:42,818 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:30:42,818 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 17:30:42,819 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:30:44,291 INFO L225 Difference]: With dead ends: 493966 [2019-12-07 17:30:44,291 INFO L226 Difference]: Without dead ends: 493840 [2019-12-07 17:30:44,292 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:30:55,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 493840 states. [2019-12-07 17:31:02,017 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 493840 to 401172. [2019-12-07 17:31:02,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 401172 states. [2019-12-07 17:31:03,828 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 401172 states to 401172 states and 1852715 transitions. [2019-12-07 17:31:03,828 INFO L78 Accepts]: Start accepts. Automaton has 401172 states and 1852715 transitions. Word has length 15 [2019-12-07 17:31:03,828 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:31:03,829 INFO L462 AbstractCegarLoop]: Abstraction has 401172 states and 1852715 transitions. [2019-12-07 17:31:03,829 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:31:03,829 INFO L276 IsEmpty]: Start isEmpty. Operand 401172 states and 1852715 transitions. [2019-12-07 17:31:03,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 17:31:03,869 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:31:03,869 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:31:03,869 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:31:03,869 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:31:03,869 INFO L82 PathProgramCache]: Analyzing trace with hash -163146082, now seen corresponding path program 1 times [2019-12-07 17:31:03,869 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:31:03,870 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1663919070] [2019-12-07 17:31:03,870 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:31:03,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:03,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:31:03,941 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1663919070] [2019-12-07 17:31:03,942 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:31:03,942 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:31:03,942 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [872100053] [2019-12-07 17:31:03,942 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:31:03,942 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:31:03,942 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:31:03,942 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:31:03,943 INFO L87 Difference]: Start difference. First operand 401172 states and 1852715 transitions. Second operand 5 states. [2019-12-07 17:31:13,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:31:13,592 INFO L93 Difference]: Finished difference Result 593580 states and 2686363 transitions. [2019-12-07 17:31:13,592 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:31:13,592 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2019-12-07 17:31:13,593 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:31:15,301 INFO L225 Difference]: With dead ends: 593580 [2019-12-07 17:31:15,301 INFO L226 Difference]: Without dead ends: 593454 [2019-12-07 17:31:15,301 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:31:27,685 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 593454 states. [2019-12-07 17:31:35,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 593454 to 424932. [2019-12-07 17:31:35,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 424932 states. [2019-12-07 17:31:36,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 424932 states to 424932 states and 1953289 transitions. [2019-12-07 17:31:36,811 INFO L78 Accepts]: Start accepts. Automaton has 424932 states and 1953289 transitions. Word has length 21 [2019-12-07 17:31:36,811 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:31:36,811 INFO L462 AbstractCegarLoop]: Abstraction has 424932 states and 1953289 transitions. [2019-12-07 17:31:36,812 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:31:36,812 INFO L276 IsEmpty]: Start isEmpty. Operand 424932 states and 1953289 transitions. [2019-12-07 17:31:36,836 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 17:31:36,836 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:31:36,836 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:31:36,837 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:31:36,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:31:36,837 INFO L82 PathProgramCache]: Analyzing trace with hash -284252006, now seen corresponding path program 1 times [2019-12-07 17:31:36,837 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:31:36,837 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [785306950] [2019-12-07 17:31:36,837 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:31:36,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:36,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:31:36,862 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [785306950] [2019-12-07 17:31:36,862 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:31:36,862 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:31:36,862 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1909603002] [2019-12-07 17:31:36,863 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:31:36,863 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:31:36,863 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:31:36,863 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:31:36,863 INFO L87 Difference]: Start difference. First operand 424932 states and 1953289 transitions. Second operand 3 states. [2019-12-07 17:31:38,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:31:38,448 INFO L93 Difference]: Finished difference Result 254046 states and 1045422 transitions. [2019-12-07 17:31:38,449 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:31:38,449 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 21 [2019-12-07 17:31:38,449 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:31:39,072 INFO L225 Difference]: With dead ends: 254046 [2019-12-07 17:31:39,073 INFO L226 Difference]: Without dead ends: 254046 [2019-12-07 17:31:39,073 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:31:48,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 254046 states. [2019-12-07 17:31:51,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 254046 to 254046. [2019-12-07 17:31:51,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 254046 states. [2019-12-07 17:31:51,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 254046 states to 254046 states and 1045422 transitions. [2019-12-07 17:31:51,944 INFO L78 Accepts]: Start accepts. Automaton has 254046 states and 1045422 transitions. Word has length 21 [2019-12-07 17:31:51,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:31:51,944 INFO L462 AbstractCegarLoop]: Abstraction has 254046 states and 1045422 transitions. [2019-12-07 17:31:51,944 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:31:51,944 INFO L276 IsEmpty]: Start isEmpty. Operand 254046 states and 1045422 transitions. [2019-12-07 17:31:51,956 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 17:31:51,956 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:31:51,956 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:31:51,957 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:31:51,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:31:51,957 INFO L82 PathProgramCache]: Analyzing trace with hash -1235283117, now seen corresponding path program 1 times [2019-12-07 17:31:51,957 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:31:51,957 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1861478022] [2019-12-07 17:31:51,957 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:31:51,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:52,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:31:52,023 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1861478022] [2019-12-07 17:31:52,023 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:31:52,023 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:31:52,023 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [722802081] [2019-12-07 17:31:52,023 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:31:52,024 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:31:52,024 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:31:52,024 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:31:52,024 INFO L87 Difference]: Start difference. First operand 254046 states and 1045422 transitions. Second operand 5 states. [2019-12-07 17:31:54,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:31:54,226 INFO L93 Difference]: Finished difference Result 382506 states and 1542885 transitions. [2019-12-07 17:31:54,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:31:54,226 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2019-12-07 17:31:54,226 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:31:55,668 INFO L225 Difference]: With dead ends: 382506 [2019-12-07 17:31:55,668 INFO L226 Difference]: Without dead ends: 382353 [2019-12-07 17:31:55,669 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:32:02,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 382353 states. [2019-12-07 17:32:06,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 382353 to 265010. [2019-12-07 17:32:06,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 265010 states. [2019-12-07 17:32:07,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 265010 states to 265010 states and 1089715 transitions. [2019-12-07 17:32:07,076 INFO L78 Accepts]: Start accepts. Automaton has 265010 states and 1089715 transitions. Word has length 21 [2019-12-07 17:32:07,076 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:32:07,076 INFO L462 AbstractCegarLoop]: Abstraction has 265010 states and 1089715 transitions. [2019-12-07 17:32:07,076 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:32:07,076 INFO L276 IsEmpty]: Start isEmpty. Operand 265010 states and 1089715 transitions. [2019-12-07 17:32:07,091 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 17:32:07,091 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:32:07,091 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:32:07,091 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:32:07,091 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:32:07,091 INFO L82 PathProgramCache]: Analyzing trace with hash -1332793814, now seen corresponding path program 1 times [2019-12-07 17:32:07,091 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:32:07,091 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1427010773] [2019-12-07 17:32:07,092 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:32:07,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:32:07,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:32:07,139 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1427010773] [2019-12-07 17:32:07,139 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:32:07,139 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:32:07,139 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1626111647] [2019-12-07 17:32:07,140 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:32:07,140 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:32:07,140 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:32:07,140 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:32:07,140 INFO L87 Difference]: Start difference. First operand 265010 states and 1089715 transitions. Second operand 5 states. [2019-12-07 17:32:12,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:32:12,373 INFO L93 Difference]: Finished difference Result 383540 states and 1549952 transitions. [2019-12-07 17:32:12,374 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:32:12,374 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 22 [2019-12-07 17:32:12,374 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:32:13,303 INFO L225 Difference]: With dead ends: 383540 [2019-12-07 17:32:13,303 INFO L226 Difference]: Without dead ends: 383477 [2019-12-07 17:32:13,304 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:32:19,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 383477 states. [2019-12-07 17:32:24,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 383477 to 285834. [2019-12-07 17:32:24,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 285834 states. [2019-12-07 17:32:24,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 285834 states to 285834 states and 1173508 transitions. [2019-12-07 17:32:24,795 INFO L78 Accepts]: Start accepts. Automaton has 285834 states and 1173508 transitions. Word has length 22 [2019-12-07 17:32:24,795 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:32:24,795 INFO L462 AbstractCegarLoop]: Abstraction has 285834 states and 1173508 transitions. [2019-12-07 17:32:24,795 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:32:24,795 INFO L276 IsEmpty]: Start isEmpty. Operand 285834 states and 1173508 transitions. [2019-12-07 17:32:24,857 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 17:32:24,857 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:32:24,857 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:32:24,857 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:32:24,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:32:24,857 INFO L82 PathProgramCache]: Analyzing trace with hash -1835074888, now seen corresponding path program 1 times [2019-12-07 17:32:24,858 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:32:24,858 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1310479696] [2019-12-07 17:32:24,858 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:32:24,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:32:24,888 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:32:24,888 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1310479696] [2019-12-07 17:32:24,889 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:32:24,889 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:32:24,889 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [845912703] [2019-12-07 17:32:24,889 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:32:24,889 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:32:24,889 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:32:24,889 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:32:24,889 INFO L87 Difference]: Start difference. First operand 285834 states and 1173508 transitions. Second operand 4 states. [2019-12-07 17:32:25,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:32:25,061 INFO L93 Difference]: Finished difference Result 53490 states and 175338 transitions. [2019-12-07 17:32:25,061 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 17:32:25,061 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 28 [2019-12-07 17:32:25,062 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:32:25,142 INFO L225 Difference]: With dead ends: 53490 [2019-12-07 17:32:25,143 INFO L226 Difference]: Without dead ends: 53490 [2019-12-07 17:32:25,143 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:32:25,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53490 states. [2019-12-07 17:32:26,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53490 to 53490. [2019-12-07 17:32:26,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53490 states. [2019-12-07 17:32:26,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53490 states to 53490 states and 175338 transitions. [2019-12-07 17:32:26,387 INFO L78 Accepts]: Start accepts. Automaton has 53490 states and 175338 transitions. Word has length 28 [2019-12-07 17:32:26,387 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:32:26,387 INFO L462 AbstractCegarLoop]: Abstraction has 53490 states and 175338 transitions. [2019-12-07 17:32:26,387 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:32:26,387 INFO L276 IsEmpty]: Start isEmpty. Operand 53490 states and 175338 transitions. [2019-12-07 17:32:26,406 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 17:32:26,406 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:32:26,406 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:32:26,406 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:32:26,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:32:26,406 INFO L82 PathProgramCache]: Analyzing trace with hash -1367341089, now seen corresponding path program 1 times [2019-12-07 17:32:26,407 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:32:26,407 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1623763903] [2019-12-07 17:32:26,407 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:32:26,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:32:26,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:32:26,440 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1623763903] [2019-12-07 17:32:26,440 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:32:26,440 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:32:26,440 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1001544906] [2019-12-07 17:32:26,440 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:32:26,441 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:32:26,441 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:32:26,441 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:32:26,441 INFO L87 Difference]: Start difference. First operand 53490 states and 175338 transitions. Second operand 5 states. [2019-12-07 17:32:26,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:32:26,498 INFO L93 Difference]: Finished difference Result 14896 states and 47020 transitions. [2019-12-07 17:32:26,498 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:32:26,498 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 34 [2019-12-07 17:32:26,498 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:32:26,516 INFO L225 Difference]: With dead ends: 14896 [2019-12-07 17:32:26,516 INFO L226 Difference]: Without dead ends: 14896 [2019-12-07 17:32:26,516 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:32:26,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14896 states. [2019-12-07 17:32:26,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14896 to 14560. [2019-12-07 17:32:26,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14560 states. [2019-12-07 17:32:26,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14560 states to 14560 states and 45892 transitions. [2019-12-07 17:32:26,715 INFO L78 Accepts]: Start accepts. Automaton has 14560 states and 45892 transitions. Word has length 34 [2019-12-07 17:32:26,715 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:32:26,715 INFO L462 AbstractCegarLoop]: Abstraction has 14560 states and 45892 transitions. [2019-12-07 17:32:26,715 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:32:26,715 INFO L276 IsEmpty]: Start isEmpty. Operand 14560 states and 45892 transitions. [2019-12-07 17:32:26,727 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-12-07 17:32:26,727 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:32:26,727 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:32:26,727 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:32:26,727 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:32:26,728 INFO L82 PathProgramCache]: Analyzing trace with hash 49356404, now seen corresponding path program 1 times [2019-12-07 17:32:26,728 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:32:26,728 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1967735307] [2019-12-07 17:32:26,728 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:32:26,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:32:26,776 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:32:26,776 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1967735307] [2019-12-07 17:32:26,776 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:32:26,776 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:32:26,776 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [126905082] [2019-12-07 17:32:26,777 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:32:26,777 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:32:26,777 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:32:26,777 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:32:26,777 INFO L87 Difference]: Start difference. First operand 14560 states and 45892 transitions. Second operand 6 states. [2019-12-07 17:32:26,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:32:26,836 INFO L93 Difference]: Finished difference Result 11892 states and 39737 transitions. [2019-12-07 17:32:26,836 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:32:26,836 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 40 [2019-12-07 17:32:26,837 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:32:26,851 INFO L225 Difference]: With dead ends: 11892 [2019-12-07 17:32:26,852 INFO L226 Difference]: Without dead ends: 11892 [2019-12-07 17:32:26,852 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:32:26,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11892 states. [2019-12-07 17:32:26,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11892 to 10310. [2019-12-07 17:32:26,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10310 states. [2019-12-07 17:32:27,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10310 states to 10310 states and 34664 transitions. [2019-12-07 17:32:27,008 INFO L78 Accepts]: Start accepts. Automaton has 10310 states and 34664 transitions. Word has length 40 [2019-12-07 17:32:27,008 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:32:27,008 INFO L462 AbstractCegarLoop]: Abstraction has 10310 states and 34664 transitions. [2019-12-07 17:32:27,008 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:32:27,008 INFO L276 IsEmpty]: Start isEmpty. Operand 10310 states and 34664 transitions. [2019-12-07 17:32:27,019 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 17:32:27,020 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:32:27,020 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:32:27,020 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:32:27,020 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:32:27,020 INFO L82 PathProgramCache]: Analyzing trace with hash 784628321, now seen corresponding path program 1 times [2019-12-07 17:32:27,020 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:32:27,021 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882737603] [2019-12-07 17:32:27,021 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:32:27,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:32:27,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:32:27,063 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882737603] [2019-12-07 17:32:27,063 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:32:27,063 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:32:27,064 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [833601847] [2019-12-07 17:32:27,064 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:32:27,064 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:32:27,064 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:32:27,064 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:32:27,064 INFO L87 Difference]: Start difference. First operand 10310 states and 34664 transitions. Second operand 3 states. [2019-12-07 17:32:27,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:32:27,112 INFO L93 Difference]: Finished difference Result 10323 states and 34677 transitions. [2019-12-07 17:32:27,112 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:32:27,112 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 68 [2019-12-07 17:32:27,113 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:32:27,125 INFO L225 Difference]: With dead ends: 10323 [2019-12-07 17:32:27,125 INFO L226 Difference]: Without dead ends: 10323 [2019-12-07 17:32:27,125 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:32:27,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10323 states. [2019-12-07 17:32:27,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10323 to 10315. [2019-12-07 17:32:27,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10315 states. [2019-12-07 17:32:27,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10315 states to 10315 states and 34669 transitions. [2019-12-07 17:32:27,263 INFO L78 Accepts]: Start accepts. Automaton has 10315 states and 34669 transitions. Word has length 68 [2019-12-07 17:32:27,263 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:32:27,263 INFO L462 AbstractCegarLoop]: Abstraction has 10315 states and 34669 transitions. [2019-12-07 17:32:27,263 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:32:27,263 INFO L276 IsEmpty]: Start isEmpty. Operand 10315 states and 34669 transitions. [2019-12-07 17:32:27,272 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 17:32:27,272 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:32:27,272 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:32:27,272 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:32:27,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:32:27,273 INFO L82 PathProgramCache]: Analyzing trace with hash 1420682600, now seen corresponding path program 1 times [2019-12-07 17:32:27,273 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:32:27,273 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [291366237] [2019-12-07 17:32:27,273 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:32:27,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:32:27,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:32:27,326 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [291366237] [2019-12-07 17:32:27,326 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:32:27,326 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:32:27,326 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [515215082] [2019-12-07 17:32:27,326 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:32:27,327 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:32:27,327 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:32:27,327 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:32:27,327 INFO L87 Difference]: Start difference. First operand 10315 states and 34669 transitions. Second operand 5 states. [2019-12-07 17:32:27,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:32:27,526 INFO L93 Difference]: Finished difference Result 15402 states and 51486 transitions. [2019-12-07 17:32:27,526 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:32:27,527 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 68 [2019-12-07 17:32:27,527 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:32:27,546 INFO L225 Difference]: With dead ends: 15402 [2019-12-07 17:32:27,547 INFO L226 Difference]: Without dead ends: 15402 [2019-12-07 17:32:27,547 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:32:27,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15402 states. [2019-12-07 17:32:27,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15402 to 12993. [2019-12-07 17:32:27,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12993 states. [2019-12-07 17:32:27,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12993 states to 12993 states and 43768 transitions. [2019-12-07 17:32:27,749 INFO L78 Accepts]: Start accepts. Automaton has 12993 states and 43768 transitions. Word has length 68 [2019-12-07 17:32:27,749 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:32:27,749 INFO L462 AbstractCegarLoop]: Abstraction has 12993 states and 43768 transitions. [2019-12-07 17:32:27,749 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:32:27,749 INFO L276 IsEmpty]: Start isEmpty. Operand 12993 states and 43768 transitions. [2019-12-07 17:32:27,762 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 17:32:27,762 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:32:27,762 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:32:27,762 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:32:27,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:32:27,762 INFO L82 PathProgramCache]: Analyzing trace with hash -1734766032, now seen corresponding path program 2 times [2019-12-07 17:32:27,763 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:32:27,763 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [911001059] [2019-12-07 17:32:27,763 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:32:27,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:32:27,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:32:27,830 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [911001059] [2019-12-07 17:32:27,831 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:32:27,831 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:32:27,831 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1921897784] [2019-12-07 17:32:27,831 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:32:27,832 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:32:27,832 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:32:27,832 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:32:27,832 INFO L87 Difference]: Start difference. First operand 12993 states and 43768 transitions. Second operand 3 states. [2019-12-07 17:32:27,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:32:27,886 INFO L93 Difference]: Finished difference Result 12993 states and 43258 transitions. [2019-12-07 17:32:27,887 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:32:27,887 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 68 [2019-12-07 17:32:27,887 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:32:27,905 INFO L225 Difference]: With dead ends: 12993 [2019-12-07 17:32:27,905 INFO L226 Difference]: Without dead ends: 12993 [2019-12-07 17:32:27,905 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:32:27,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12993 states. [2019-12-07 17:32:28,462 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12993 to 12681. [2019-12-07 17:32:28,462 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12681 states. [2019-12-07 17:32:28,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12681 states to 12681 states and 42242 transitions. [2019-12-07 17:32:28,483 INFO L78 Accepts]: Start accepts. Automaton has 12681 states and 42242 transitions. Word has length 68 [2019-12-07 17:32:28,483 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:32:28,483 INFO L462 AbstractCegarLoop]: Abstraction has 12681 states and 42242 transitions. [2019-12-07 17:32:28,483 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:32:28,483 INFO L276 IsEmpty]: Start isEmpty. Operand 12681 states and 42242 transitions. [2019-12-07 17:32:28,495 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-12-07 17:32:28,495 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:32:28,495 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:32:28,495 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:32:28,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:32:28,495 INFO L82 PathProgramCache]: Analyzing trace with hash -361290589, now seen corresponding path program 1 times [2019-12-07 17:32:28,496 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:32:28,496 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [802789995] [2019-12-07 17:32:28,496 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:32:28,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:32:28,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:32:28,558 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [802789995] [2019-12-07 17:32:28,558 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:32:28,558 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:32:28,558 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1678965050] [2019-12-07 17:32:28,559 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:32:28,559 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:32:28,559 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:32:28,559 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:32:28,559 INFO L87 Difference]: Start difference. First operand 12681 states and 42242 transitions. Second operand 3 states. [2019-12-07 17:32:28,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:32:28,598 INFO L93 Difference]: Finished difference Result 12079 states and 39785 transitions. [2019-12-07 17:32:28,598 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:32:28,598 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 69 [2019-12-07 17:32:28,598 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:32:28,612 INFO L225 Difference]: With dead ends: 12079 [2019-12-07 17:32:28,612 INFO L226 Difference]: Without dead ends: 12079 [2019-12-07 17:32:28,613 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:32:28,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12079 states. [2019-12-07 17:32:28,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12079 to 11407. [2019-12-07 17:32:28,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11407 states. [2019-12-07 17:32:28,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11407 states to 11407 states and 37593 transitions. [2019-12-07 17:32:28,768 INFO L78 Accepts]: Start accepts. Automaton has 11407 states and 37593 transitions. Word has length 69 [2019-12-07 17:32:28,768 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:32:28,769 INFO L462 AbstractCegarLoop]: Abstraction has 11407 states and 37593 transitions. [2019-12-07 17:32:28,769 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:32:28,769 INFO L276 IsEmpty]: Start isEmpty. Operand 11407 states and 37593 transitions. [2019-12-07 17:32:28,779 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 17:32:28,779 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:32:28,779 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:32:28,779 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:32:28,779 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:32:28,779 INFO L82 PathProgramCache]: Analyzing trace with hash -1688370102, now seen corresponding path program 1 times [2019-12-07 17:32:28,779 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:32:28,779 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280154933] [2019-12-07 17:32:28,780 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:32:28,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:32:28,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:32:28,840 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [280154933] [2019-12-07 17:32:28,840 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:32:28,840 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:32:28,841 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [691657771] [2019-12-07 17:32:28,841 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:32:28,841 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:32:28,841 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:32:28,841 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:32:28,841 INFO L87 Difference]: Start difference. First operand 11407 states and 37593 transitions. Second operand 6 states. [2019-12-07 17:32:29,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:32:29,180 INFO L93 Difference]: Finished difference Result 17392 states and 56662 transitions. [2019-12-07 17:32:29,180 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 17:32:29,180 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 70 [2019-12-07 17:32:29,180 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:32:29,200 INFO L225 Difference]: With dead ends: 17392 [2019-12-07 17:32:29,201 INFO L226 Difference]: Without dead ends: 17392 [2019-12-07 17:32:29,201 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 8 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2019-12-07 17:32:29,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17392 states. [2019-12-07 17:32:29,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17392 to 12391. [2019-12-07 17:32:29,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12391 states. [2019-12-07 17:32:29,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12391 states to 12391 states and 40839 transitions. [2019-12-07 17:32:29,409 INFO L78 Accepts]: Start accepts. Automaton has 12391 states and 40839 transitions. Word has length 70 [2019-12-07 17:32:29,409 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:32:29,409 INFO L462 AbstractCegarLoop]: Abstraction has 12391 states and 40839 transitions. [2019-12-07 17:32:29,409 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:32:29,409 INFO L276 IsEmpty]: Start isEmpty. Operand 12391 states and 40839 transitions. [2019-12-07 17:32:29,421 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 17:32:29,421 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:32:29,421 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:32:29,421 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:32:29,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:32:29,422 INFO L82 PathProgramCache]: Analyzing trace with hash -948068296, now seen corresponding path program 2 times [2019-12-07 17:32:29,422 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:32:29,422 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [851456426] [2019-12-07 17:32:29,422 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:32:29,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:32:29,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:32:29,486 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [851456426] [2019-12-07 17:32:29,486 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:32:29,486 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:32:29,487 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1786562226] [2019-12-07 17:32:29,487 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:32:29,487 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:32:29,487 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:32:29,487 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:32:29,487 INFO L87 Difference]: Start difference. First operand 12391 states and 40839 transitions. Second operand 6 states. [2019-12-07 17:32:29,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:32:29,571 INFO L93 Difference]: Finished difference Result 17540 states and 55142 transitions. [2019-12-07 17:32:29,572 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:32:29,572 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 70 [2019-12-07 17:32:29,572 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:32:29,585 INFO L225 Difference]: With dead ends: 17540 [2019-12-07 17:32:29,585 INFO L226 Difference]: Without dead ends: 11313 [2019-12-07 17:32:29,585 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:32:29,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11313 states. [2019-12-07 17:32:29,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11313 to 11313. [2019-12-07 17:32:29,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11313 states. [2019-12-07 17:32:29,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11313 states to 11313 states and 36685 transitions. [2019-12-07 17:32:29,733 INFO L78 Accepts]: Start accepts. Automaton has 11313 states and 36685 transitions. Word has length 70 [2019-12-07 17:32:29,733 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:32:29,734 INFO L462 AbstractCegarLoop]: Abstraction has 11313 states and 36685 transitions. [2019-12-07 17:32:29,734 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:32:29,734 INFO L276 IsEmpty]: Start isEmpty. Operand 11313 states and 36685 transitions. [2019-12-07 17:32:29,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 17:32:29,743 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:32:29,743 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:32:29,743 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:32:29,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:32:29,743 INFO L82 PathProgramCache]: Analyzing trace with hash 2011966362, now seen corresponding path program 3 times [2019-12-07 17:32:29,743 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:32:29,743 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195542834] [2019-12-07 17:32:29,743 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:32:29,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:32:29,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:32:29,777 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1195542834] [2019-12-07 17:32:29,778 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:32:29,778 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:32:29,778 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2042891628] [2019-12-07 17:32:29,778 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:32:29,778 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:32:29,778 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:32:29,779 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:32:29,779 INFO L87 Difference]: Start difference. First operand 11313 states and 36685 transitions. Second operand 3 states. [2019-12-07 17:32:29,837 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:32:29,837 INFO L93 Difference]: Finished difference Result 11312 states and 36683 transitions. [2019-12-07 17:32:29,838 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:32:29,838 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2019-12-07 17:32:29,838 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:32:29,853 INFO L225 Difference]: With dead ends: 11312 [2019-12-07 17:32:29,853 INFO L226 Difference]: Without dead ends: 11312 [2019-12-07 17:32:29,854 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:32:29,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11312 states. [2019-12-07 17:32:29,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11312 to 6648. [2019-12-07 17:32:29,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6648 states. [2019-12-07 17:32:29,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6648 states to 6648 states and 21668 transitions. [2019-12-07 17:32:29,976 INFO L78 Accepts]: Start accepts. Automaton has 6648 states and 21668 transitions. Word has length 70 [2019-12-07 17:32:29,976 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:32:29,976 INFO L462 AbstractCegarLoop]: Abstraction has 6648 states and 21668 transitions. [2019-12-07 17:32:29,976 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:32:29,976 INFO L276 IsEmpty]: Start isEmpty. Operand 6648 states and 21668 transitions. [2019-12-07 17:32:29,982 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-12-07 17:32:29,982 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:32:29,982 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:32:29,982 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:32:29,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:32:29,982 INFO L82 PathProgramCache]: Analyzing trace with hash 782381861, now seen corresponding path program 1 times [2019-12-07 17:32:29,983 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:32:29,983 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [236437454] [2019-12-07 17:32:29,983 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:32:29,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:32:30,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:32:30,041 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [236437454] [2019-12-07 17:32:30,041 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:32:30,041 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:32:30,041 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1881189628] [2019-12-07 17:32:30,042 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:32:30,042 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:32:30,042 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:32:30,042 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:32:30,042 INFO L87 Difference]: Start difference. First operand 6648 states and 21668 transitions. Second operand 6 states. [2019-12-07 17:32:30,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:32:30,107 INFO L93 Difference]: Finished difference Result 11178 states and 36500 transitions. [2019-12-07 17:32:30,108 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:32:30,108 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 71 [2019-12-07 17:32:30,108 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:32:30,114 INFO L225 Difference]: With dead ends: 11178 [2019-12-07 17:32:30,114 INFO L226 Difference]: Without dead ends: 5146 [2019-12-07 17:32:30,114 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:32:30,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5146 states. [2019-12-07 17:32:30,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5146 to 5146. [2019-12-07 17:32:30,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5146 states. [2019-12-07 17:32:30,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5146 states to 5146 states and 16563 transitions. [2019-12-07 17:32:30,189 INFO L78 Accepts]: Start accepts. Automaton has 5146 states and 16563 transitions. Word has length 71 [2019-12-07 17:32:30,189 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:32:30,189 INFO L462 AbstractCegarLoop]: Abstraction has 5146 states and 16563 transitions. [2019-12-07 17:32:30,189 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:32:30,189 INFO L276 IsEmpty]: Start isEmpty. Operand 5146 states and 16563 transitions. [2019-12-07 17:32:30,194 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-12-07 17:32:30,194 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:32:30,194 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:32:30,194 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:32:30,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:32:30,194 INFO L82 PathProgramCache]: Analyzing trace with hash -927821351, now seen corresponding path program 2 times [2019-12-07 17:32:30,194 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:32:30,194 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1779620451] [2019-12-07 17:32:30,194 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:32:30,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:32:30,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:32:30,367 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1779620451] [2019-12-07 17:32:30,367 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:32:30,367 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 17:32:30,368 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [556239122] [2019-12-07 17:32:30,368 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 17:32:30,368 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:32:30,368 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 17:32:30,368 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=129, Unknown=0, NotChecked=0, Total=156 [2019-12-07 17:32:30,368 INFO L87 Difference]: Start difference. First operand 5146 states and 16563 transitions. Second operand 13 states. [2019-12-07 17:32:30,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:32:30,736 INFO L93 Difference]: Finished difference Result 8702 states and 28077 transitions. [2019-12-07 17:32:30,736 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 17:32:30,736 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 71 [2019-12-07 17:32:30,736 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:32:30,746 INFO L225 Difference]: With dead ends: 8702 [2019-12-07 17:32:30,746 INFO L226 Difference]: Without dead ends: 8670 [2019-12-07 17:32:30,746 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=136, Invalid=514, Unknown=0, NotChecked=0, Total=650 [2019-12-07 17:32:30,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8670 states. [2019-12-07 17:32:31,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8670 to 7264. [2019-12-07 17:32:31,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7264 states. [2019-12-07 17:32:31,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7264 states to 7264 states and 23368 transitions. [2019-12-07 17:32:31,078 INFO L78 Accepts]: Start accepts. Automaton has 7264 states and 23368 transitions. Word has length 71 [2019-12-07 17:32:31,078 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:32:31,078 INFO L462 AbstractCegarLoop]: Abstraction has 7264 states and 23368 transitions. [2019-12-07 17:32:31,078 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 17:32:31,078 INFO L276 IsEmpty]: Start isEmpty. Operand 7264 states and 23368 transitions. [2019-12-07 17:32:31,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-12-07 17:32:31,084 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:32:31,084 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:32:31,084 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:32:31,084 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:32:31,084 INFO L82 PathProgramCache]: Analyzing trace with hash -710173609, now seen corresponding path program 3 times [2019-12-07 17:32:31,084 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:32:31,085 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [742052972] [2019-12-07 17:32:31,085 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:32:31,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:32:31,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:32:31,167 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:32:31,167 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 17:32:31,169 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [864] [864] ULTIMATE.startENTRY-->L828: Formula: (let ((.cse0 (store |v_#valid_77| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= 0 v_~y$r_buff1_thd3~0_186) (< 0 |v_#StackHeapBarrier_23|) (= v_~y$w_buff1_used~0_459 0) (= 0 v_~__unbuffered_p2_EAX~0_128) (= 0 v_~y$w_buff0~0_224) (= v_~a~0_40 0) (= 0 v_~y$r_buff0_thd3~0_213) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1433~0.base_27|)) (= v_~main$tmp_guard0~0_34 0) (= v_~y$r_buff0_thd1~0_40 0) (= v_~y$w_buff1~0_177 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t1433~0.base_27| 1) |v_#valid_75|) (= 0 v_~y$r_buff1_thd2~0_203) (= v_~main$tmp_guard1~0_21 0) (= 0 v_~y$r_buff1_thd4~0_197) (= v_~y$read_delayed~0_6 0) (= v_~y$mem_tmp~0_18 0) (= |v_ULTIMATE.start_main_~#t1433~0.offset_21| 0) (= v_~y$r_buff1_thd0~0_278 0) (= v_~y$r_buff0_thd0~0_327 0) (= v_~y$r_buff1_thd1~0_121 0) (< |v_#StackHeapBarrier_23| |v_ULTIMATE.start_main_~#t1433~0.base_27|) (= v_~z~0_47 0) (= 0 |v_#NULL.base_4|) (= 0 v_~__unbuffered_p3_EAX~0_23) (= v_~y~0_186 0) (= v_~x~0_50 0) (= v_~weak$$choice2~0_123 0) (= |v_#NULL.offset_4| 0) (= (store |v_#memory_int_30| |v_ULTIMATE.start_main_~#t1433~0.base_27| (store (select |v_#memory_int_30| |v_ULTIMATE.start_main_~#t1433~0.base_27|) |v_ULTIMATE.start_main_~#t1433~0.offset_21| 0)) |v_#memory_int_29|) (= v_~y$w_buff0_used~0_726 0) (= 0 v_~y$read_delayed_var~0.offset_6) (= 0 v_~weak$$choice0~0_13) (= v_~__unbuffered_cnt~0_227 0) (= |v_#length_33| (store |v_#length_34| |v_ULTIMATE.start_main_~#t1433~0.base_27| 4)) (= 0 v_~y$r_buff0_thd2~0_133) (= 0 v_~y$r_buff0_thd4~0_116) (= 0 v_~y$flush_delayed~0_34))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_23|, #valid=|v_#valid_77|, #memory_int=|v_#memory_int_30|, #length=|v_#length_34|} OutVars{ULTIMATE.start_main_#t~nondet32=|v_ULTIMATE.start_main_#t~nondet32_22|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_126|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_30|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_30|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_18|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_36|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_67|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_46|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~a~0=v_~a~0_40, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_34|, ~y$mem_tmp~0=v_~y$mem_tmp~0_18, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_186, ULTIMATE.start_main_~#t1433~0.offset=|v_ULTIMATE.start_main_~#t1433~0.offset_21|, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_40, ~y$flush_delayed~0=v_~y$flush_delayed~0_34, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_23, #length=|v_#length_33|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_128, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_41|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_36|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_31|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_22|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_60|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_23|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_45|, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_197, ULTIMATE.start_main_~#t1436~0.base=|v_ULTIMATE.start_main_~#t1436~0.base_21|, ~y$w_buff1~0=v_~y$w_buff1~0_177, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ULTIMATE.start_main_~#t1436~0.offset=|v_ULTIMATE.start_main_~#t1436~0.offset_17|, ULTIMATE.start_main_~#t1435~0.offset=|v_ULTIMATE.start_main_~#t1435~0.offset_18|, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_133, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_227, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_278, ~x~0=v_~x~0_50, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_22|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ULTIMATE.start_main_~#t1434~0.offset=|v_ULTIMATE.start_main_~#t1434~0.offset_21|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_726, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_32|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_36|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_53|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_26|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_30|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_67|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_121, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_34|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_48|, ~y$w_buff0~0=v_~y$w_buff0~0_224, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_213, ~y~0=v_~y~0_186, ULTIMATE.start_main_~#t1435~0.base=|v_ULTIMATE.start_main_~#t1435~0.base_23|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_10|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_10|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_35|, ULTIMATE.start_main_~#t1434~0.base=|v_ULTIMATE.start_main_~#t1434~0.base_27|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_35|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_34, ULTIMATE.start_main_~#t1433~0.base=|v_ULTIMATE.start_main_~#t1433~0.base_27|, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_33|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_104|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_203, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_116, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_31|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_21|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_327, #valid=|v_#valid_75|, #memory_int=|v_#memory_int_29|, ~z~0=v_~z~0_47, ~weak$$choice2~0=v_~weak$$choice2~0_123, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_459} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet32, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ~y$read_delayed~0, ~a~0, ULTIMATE.start_main_#t~ite52, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ULTIMATE.start_main_~#t1433~0.offset, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ~__unbuffered_p3_EAX~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$r_buff1_thd4~0, ULTIMATE.start_main_~#t1436~0.base, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ULTIMATE.start_main_~#t1436~0.offset, ULTIMATE.start_main_~#t1435~0.offset, ~y$r_buff0_thd2~0, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ~y$read_delayed_var~0.offset, ULTIMATE.start_main_~#t1434~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite51, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_~#t1435~0.base, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_~#t1434~0.base, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_~#t1433~0.base, ULTIMATE.start_main_#t~ite53, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ~y$r_buff0_thd4~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 17:32:31,170 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [842] [842] L828-1-->L830: Formula: (and (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1434~0.base_13| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1434~0.base_13|) |v_ULTIMATE.start_main_~#t1434~0.offset_11| 1)) |v_#memory_int_19|) (= (store |v_#length_24| |v_ULTIMATE.start_main_~#t1434~0.base_13| 4) |v_#length_23|) (= |v_ULTIMATE.start_main_~#t1434~0.offset_11| 0) (= 0 (select |v_#valid_51| |v_ULTIMATE.start_main_~#t1434~0.base_13|)) (< |v_#StackHeapBarrier_15| |v_ULTIMATE.start_main_~#t1434~0.base_13|) (not (= 0 |v_ULTIMATE.start_main_~#t1434~0.base_13|)) (= |v_#valid_50| (store |v_#valid_51| |v_ULTIMATE.start_main_~#t1434~0.base_13| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_51|, #memory_int=|v_#memory_int_20|, #length=|v_#length_24|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_15|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_5|, ULTIMATE.start_main_~#t1434~0.offset=|v_ULTIMATE.start_main_~#t1434~0.offset_11|, #valid=|v_#valid_50|, #memory_int=|v_#memory_int_19|, ULTIMATE.start_main_~#t1434~0.base=|v_ULTIMATE.start_main_~#t1434~0.base_13|, #length=|v_#length_23|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t1434~0.offset, #valid, #memory_int, ULTIMATE.start_main_~#t1434~0.base, #length] because there is no mapped edge [2019-12-07 17:32:31,170 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [836] [836] L830-1-->L832: Formula: (and (not (= |v_ULTIMATE.start_main_~#t1435~0.base_12| 0)) (= 0 (select |v_#valid_47| |v_ULTIMATE.start_main_~#t1435~0.base_12|)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1435~0.base_12| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1435~0.base_12|) |v_ULTIMATE.start_main_~#t1435~0.offset_11| 2)) |v_#memory_int_15|) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t1435~0.base_12|) (= |v_ULTIMATE.start_main_~#t1435~0.offset_11| 0) (= |v_#valid_46| (store |v_#valid_47| |v_ULTIMATE.start_main_~#t1435~0.base_12| 1)) (= (store |v_#length_20| |v_ULTIMATE.start_main_~#t1435~0.base_12| 4) |v_#length_19|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, ULTIMATE.start_main_~#t1435~0.offset=|v_ULTIMATE.start_main_~#t1435~0.offset_11|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_15|, #length=|v_#length_19|, ULTIMATE.start_main_~#t1435~0.base=|v_ULTIMATE.start_main_~#t1435~0.base_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_~#t1435~0.offset, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1435~0.base] because there is no mapped edge [2019-12-07 17:32:31,171 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L832-1-->L834: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t1436~0.base_12|)) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t1436~0.base_12|) (= |v_#valid_48| (store |v_#valid_49| |v_ULTIMATE.start_main_~#t1436~0.base_12| 1)) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1436~0.base_12| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1436~0.base_12|) |v_ULTIMATE.start_main_~#t1436~0.offset_10| 3)) |v_#memory_int_17|) (= |v_ULTIMATE.start_main_~#t1436~0.offset_10| 0) (= 0 (select |v_#valid_49| |v_ULTIMATE.start_main_~#t1436~0.base_12|)) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t1436~0.base_12| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_49|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_~#t1436~0.base=|v_ULTIMATE.start_main_~#t1436~0.base_12|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ULTIMATE.start_main_~#t1436~0.offset=|v_ULTIMATE.start_main_~#t1436~0.offset_10|, #valid=|v_#valid_48|, #memory_int=|v_#memory_int_17|, #length=|v_#length_21|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1436~0.base, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_~#t1436~0.offset, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 17:32:31,171 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [750] [750] L4-->L785: Formula: (and (= v_~y$r_buff0_thd2~0_39 v_~y$r_buff1_thd2~0_26) (= v_~y$r_buff0_thd3~0_25 1) (= v_~y$r_buff1_thd1~0_5 v_~y$r_buff0_thd1~0_6) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_16)) (= v_~__unbuffered_p2_EAX~0_6 v_~z~0_8) (= v_~y$r_buff0_thd0~0_74 v_~y$r_buff1_thd0~0_48) (= v_~y$r_buff0_thd4~0_30 v_~y$r_buff1_thd4~0_17) (= v_~y$r_buff0_thd3~0_26 v_~y$r_buff1_thd3~0_18)) InVars {~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_30, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_26, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_74, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_39, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_6, ~z~0=v_~z~0_8, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_16} OutVars{P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_16, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_26, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_30, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_5, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_17, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_18, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_25, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_74, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_39, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_6, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_6, ~z~0=v_~z~0_8, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_48} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, ~y$r_buff1_thd1~0, ~y$r_buff1_thd4~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd3~0, ~__unbuffered_p2_EAX~0, ~y$r_buff1_thd0~0] because there is no mapped edge [2019-12-07 17:32:31,172 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [810] [810] L786-->L786-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd3~0_In-2076152962 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In-2076152962 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite11_Out-2076152962| ~y$w_buff0_used~0_In-2076152962) (or .cse0 .cse1)) (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out-2076152962| 0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-2076152962, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2076152962} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-2076152962, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-2076152962|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2076152962} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 17:32:31,172 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L787-->L787-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1063874344 256))) (.cse3 (= 0 (mod ~y$r_buff1_thd3~0_In-1063874344 256))) (.cse1 (= (mod ~y$r_buff0_thd3~0_In-1063874344 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1063874344 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite12_Out-1063874344| ~y$w_buff1_used~0_In-1063874344) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |P2Thread1of1ForFork0_#t~ite12_Out-1063874344| 0)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1063874344, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1063874344, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1063874344, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1063874344} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1063874344, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1063874344, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-1063874344|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1063874344, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1063874344} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 17:32:31,172 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [809] [809] L788-->L789: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd3~0_In-1120891944 256) 0)) (.cse2 (= ~y$r_buff0_thd3~0_In-1120891944 ~y$r_buff0_thd3~0_Out-1120891944)) (.cse1 (= (mod ~y$w_buff0_used~0_In-1120891944 256) 0))) (or (and (not .cse0) (= 0 ~y$r_buff0_thd3~0_Out-1120891944) (not .cse1)) (and .cse0 .cse2) (and .cse2 .cse1))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1120891944, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1120891944} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1120891944, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-1120891944, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-1120891944|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 17:32:31,172 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [813] [813] L789-->L789-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In898364897 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In898364897 256) 0)) (.cse1 (= (mod ~y$w_buff1_used~0_In898364897 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd3~0_In898364897 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork0_#t~ite14_Out898364897| 0)) (and (or .cse2 .cse3) (or .cse1 .cse0) (= |P2Thread1of1ForFork0_#t~ite14_Out898364897| ~y$r_buff1_thd3~0_In898364897)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In898364897, ~y$w_buff0_used~0=~y$w_buff0_used~0_In898364897, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In898364897, ~y$w_buff1_used~0=~y$w_buff1_used~0_In898364897} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out898364897|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In898364897, ~y$w_buff0_used~0=~y$w_buff0_used~0_In898364897, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In898364897, ~y$w_buff1_used~0=~y$w_buff1_used~0_In898364897} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 17:32:31,173 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L805-2-->L805-4: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In495156446 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd4~0_In495156446 256)))) (or (and (not .cse0) (= |P3Thread1of1ForFork1_#t~ite15_Out495156446| ~y$w_buff1~0_In495156446) (not .cse1)) (and (= |P3Thread1of1ForFork1_#t~ite15_Out495156446| ~y~0_In495156446) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In495156446, ~y$w_buff1~0=~y$w_buff1~0_In495156446, ~y~0=~y~0_In495156446, ~y$w_buff1_used~0=~y$w_buff1_used~0_In495156446} OutVars{~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In495156446, ~y$w_buff1~0=~y$w_buff1~0_In495156446, P3Thread1of1ForFork1_#t~ite15=|P3Thread1of1ForFork1_#t~ite15_Out495156446|, ~y~0=~y~0_In495156446, ~y$w_buff1_used~0=~y$w_buff1_used~0_In495156446} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite15] because there is no mapped edge [2019-12-07 17:32:31,173 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [828] [828] P0ENTRY-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork2_#res.offset_9| 0) (= |v_P0Thread1of1ForFork2_#in~arg.offset_15| v_P0Thread1of1ForFork2_~arg.offset_13) (= v_~x~0_24 1) (= v_P0Thread1of1ForFork2_~arg.base_13 |v_P0Thread1of1ForFork2_#in~arg.base_15|) (= 0 |v_P0Thread1of1ForFork2_#res.base_9|) (= (+ v_~__unbuffered_cnt~0_67 1) v_~__unbuffered_cnt~0_66) (= v_~a~0_18 1)) InVars {P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_15|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_15|} OutVars{~a~0=v_~a~0_18, P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_15|, P0Thread1of1ForFork2_~arg.offset=v_P0Thread1of1ForFork2_~arg.offset_13, P0Thread1of1ForFork2_#res.offset=|v_P0Thread1of1ForFork2_#res.offset_9|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_15|, P0Thread1of1ForFork2_#res.base=|v_P0Thread1of1ForFork2_#res.base_9|, ~x~0=v_~x~0_24, P0Thread1of1ForFork2_~arg.base=v_P0Thread1of1ForFork2_~arg.base_13} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork2_~arg.offset, P0Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0, P0Thread1of1ForFork2_#res.base, ~x~0, P0Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-12-07 17:32:31,173 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [830] [830] L789-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#t~ite14_32| v_~y$r_buff1_thd3~0_59) (= (+ v_~__unbuffered_cnt~0_85 1) v_~__unbuffered_cnt~0_84) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_85} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_31|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_59, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_84, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 17:32:31,174 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L805-4-->L806: Formula: (= v_~y~0_21 |v_P3Thread1of1ForFork1_#t~ite15_6|) InVars {P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_6|} OutVars{P3Thread1of1ForFork1_#t~ite16=|v_P3Thread1of1ForFork1_#t~ite16_5|, P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_5|, ~y~0=v_~y~0_21} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite16, P3Thread1of1ForFork1_#t~ite15, ~y~0] because there is no mapped edge [2019-12-07 17:32:31,174 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L806-->L806-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-788707118 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd4~0_In-788707118 256)))) (or (and (= ~y$w_buff0_used~0_In-788707118 |P3Thread1of1ForFork1_#t~ite17_Out-788707118|) (or .cse0 .cse1)) (and (not .cse0) (= 0 |P3Thread1of1ForFork1_#t~ite17_Out-788707118|) (not .cse1)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-788707118, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-788707118} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-788707118, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-788707118, P3Thread1of1ForFork1_#t~ite17=|P3Thread1of1ForFork1_#t~ite17_Out-788707118|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite17] because there is no mapped edge [2019-12-07 17:32:31,174 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L807-->L807-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In1961982443 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd4~0_In1961982443 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In1961982443 256) 0)) (.cse1 (= 0 (mod ~y$r_buff1_thd4~0_In1961982443 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P3Thread1of1ForFork1_#t~ite18_Out1961982443| 0)) (and (or .cse3 .cse2) (= |P3Thread1of1ForFork1_#t~ite18_Out1961982443| ~y$w_buff1_used~0_In1961982443) (or .cse0 .cse1)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1961982443, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1961982443, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1961982443, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1961982443} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1961982443, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1961982443, P3Thread1of1ForFork1_#t~ite18=|P3Thread1of1ForFork1_#t~ite18_Out1961982443|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1961982443, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1961982443} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite18] because there is no mapped edge [2019-12-07 17:32:31,174 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [794] [794] L755-2-->L755-5: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In257192711 256))) (.cse0 (= |P1Thread1of1ForFork3_#t~ite4_Out257192711| |P1Thread1of1ForFork3_#t~ite3_Out257192711|)) (.cse1 (= (mod ~y$r_buff1_thd2~0_In257192711 256) 0))) (or (and .cse0 (= ~y~0_In257192711 |P1Thread1of1ForFork3_#t~ite3_Out257192711|) (or .cse1 .cse2)) (and (not .cse2) (= ~y$w_buff1~0_In257192711 |P1Thread1of1ForFork3_#t~ite3_Out257192711|) .cse0 (not .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In257192711, ~y$w_buff1~0=~y$w_buff1~0_In257192711, ~y~0=~y~0_In257192711, ~y$w_buff1_used~0=~y$w_buff1_used~0_In257192711} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In257192711, ~y$w_buff1~0=~y$w_buff1~0_In257192711, P1Thread1of1ForFork3_#t~ite4=|P1Thread1of1ForFork3_#t~ite4_Out257192711|, P1Thread1of1ForFork3_#t~ite3=|P1Thread1of1ForFork3_#t~ite3_Out257192711|, ~y~0=~y~0_In257192711, ~y$w_buff1_used~0=~y$w_buff1_used~0_In257192711} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite4, P1Thread1of1ForFork3_#t~ite3] because there is no mapped edge [2019-12-07 17:32:31,175 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [808] [808] L808-->L808-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In2137503829 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd4~0_In2137503829 256)))) (or (and (not .cse0) (= 0 |P3Thread1of1ForFork1_#t~ite19_Out2137503829|) (not .cse1)) (and (or .cse1 .cse0) (= |P3Thread1of1ForFork1_#t~ite19_Out2137503829| ~y$r_buff0_thd4~0_In2137503829)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In2137503829, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2137503829} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In2137503829, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2137503829, P3Thread1of1ForFork1_#t~ite19=|P3Thread1of1ForFork1_#t~ite19_Out2137503829|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite19] because there is no mapped edge [2019-12-07 17:32:31,175 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L756-->L756-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1583603154 256) 0)) (.cse0 (= (mod ~y$r_buff0_thd2~0_In-1583603154 256) 0))) (or (and (= |P1Thread1of1ForFork3_#t~ite5_Out-1583603154| ~y$w_buff0_used~0_In-1583603154) (or .cse0 .cse1)) (and (= |P1Thread1of1ForFork3_#t~ite5_Out-1583603154| 0) (not .cse1) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1583603154, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1583603154} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1583603154, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1583603154, P1Thread1of1ForFork3_#t~ite5=|P1Thread1of1ForFork3_#t~ite5_Out-1583603154|} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite5] because there is no mapped edge [2019-12-07 17:32:31,175 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L757-->L757-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In-2136991176 256))) (.cse0 (= (mod ~y$r_buff1_thd2~0_In-2136991176 256) 0)) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In-2136991176 256))) (.cse2 (= (mod ~y$r_buff0_thd2~0_In-2136991176 256) 0))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork3_#t~ite6_Out-2136991176| ~y$w_buff1_used~0_In-2136991176) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2))) (= |P1Thread1of1ForFork3_#t~ite6_Out-2136991176| 0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2136991176, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2136991176, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2136991176, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2136991176} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2136991176, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2136991176, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2136991176, P1Thread1of1ForFork3_#t~ite6=|P1Thread1of1ForFork3_#t~ite6_Out-2136991176|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2136991176} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite6] because there is no mapped edge [2019-12-07 17:32:31,176 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [812] [812] L758-->L758-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd2~0_In-1692963214 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1692963214 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork3_#t~ite7_Out-1692963214|)) (and (= ~y$r_buff0_thd2~0_In-1692963214 |P1Thread1of1ForFork3_#t~ite7_Out-1692963214|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1692963214, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1692963214} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1692963214, P1Thread1of1ForFork3_#t~ite7=|P1Thread1of1ForFork3_#t~ite7_Out-1692963214|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1692963214} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite7] because there is no mapped edge [2019-12-07 17:32:31,176 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L809-->L809-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd4~0_In-788594088 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In-788594088 256) 0)) (.cse2 (= (mod ~y$w_buff1_used~0_In-788594088 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd4~0_In-788594088 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P3Thread1of1ForFork1_#t~ite20_Out-788594088| ~y$r_buff1_thd4~0_In-788594088)) (and (= |P3Thread1of1ForFork1_#t~ite20_Out-788594088| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-788594088, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-788594088, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-788594088, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-788594088} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-788594088, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-788594088, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-788594088, P3Thread1of1ForFork1_#t~ite20=|P3Thread1of1ForFork1_#t~ite20_Out-788594088|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-788594088} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 17:32:31,176 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L809-2-->P3EXIT: Formula: (and (= v_~__unbuffered_cnt~0_144 (+ v_~__unbuffered_cnt~0_145 1)) (= |v_P3Thread1of1ForFork1_#t~ite20_56| v_~y$r_buff1_thd4~0_148) (= |v_P3Thread1of1ForFork1_#res.offset_3| 0) (= |v_P3Thread1of1ForFork1_#res.base_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_145, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_56|} OutVars{~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_148, P3Thread1of1ForFork1_#res.base=|v_P3Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_144, P3Thread1of1ForFork1_#res.offset=|v_P3Thread1of1ForFork1_#res.offset_3|, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_55|} AuxVars[] AssignedVars[~y$r_buff1_thd4~0, P3Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork1_#res.offset, P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 17:32:31,177 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [797] [797] L759-->L759-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In-1406188992 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In-1406188992 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In-1406188992 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In-1406188992 256) 0))) (or (and (= ~y$r_buff1_thd2~0_In-1406188992 |P1Thread1of1ForFork3_#t~ite8_Out-1406188992|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork3_#t~ite8_Out-1406188992| 0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1406188992, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1406188992, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1406188992, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1406188992} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1406188992, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1406188992, P1Thread1of1ForFork3_#t~ite8=|P1Thread1of1ForFork3_#t~ite8_Out-1406188992|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1406188992, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1406188992} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite8] because there is no mapped edge [2019-12-07 17:32:31,177 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [831] [831] L759-2-->P1EXIT: Formula: (and (= v_~__unbuffered_cnt~0_108 (+ v_~__unbuffered_cnt~0_109 1)) (= 0 |v_P1Thread1of1ForFork3_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork3_#res.base_3|) (= |v_P1Thread1of1ForFork3_#t~ite8_48| v_~y$r_buff1_thd2~0_69)) InVars {P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_48|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_109} OutVars{P1Thread1of1ForFork3_#res.base=|v_P1Thread1of1ForFork3_#res.base_3|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_69, P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_47|, P1Thread1of1ForFork3_#res.offset=|v_P1Thread1of1ForFork3_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_108} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#res.base, ~y$r_buff1_thd2~0, P1Thread1of1ForFork3_#t~ite8, P1Thread1of1ForFork3_#res.offset, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 17:32:31,177 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [742] [742] L834-1-->L840: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (= v_~main$tmp_guard0~0_8 (ite (= 0 (ite (= 4 v_~__unbuffered_cnt~0_26) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_26} OutVars{ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_7|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_26, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet24, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 17:32:31,177 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L840-2-->L840-4: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-1662439110 256))) (.cse1 (= (mod ~y$w_buff1_used~0_In-1662439110 256) 0))) (or (and (or .cse0 .cse1) (= ~y~0_In-1662439110 |ULTIMATE.start_main_#t~ite25_Out-1662439110|)) (and (not .cse0) (= |ULTIMATE.start_main_#t~ite25_Out-1662439110| ~y$w_buff1~0_In-1662439110) (not .cse1)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1662439110, ~y~0=~y~0_In-1662439110, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1662439110, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1662439110} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1662439110, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-1662439110|, ~y~0=~y~0_In-1662439110, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1662439110, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1662439110} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 17:32:31,177 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [749] [749] L840-4-->L841: Formula: (= v_~y~0_56 |v_ULTIMATE.start_main_#t~ite25_9|) InVars {ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_9|} OutVars{ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_8|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_12|, ~y~0=v_~y~0_56} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite26, ~y~0] because there is no mapped edge [2019-12-07 17:32:31,177 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [811] [811] L841-->L841-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In329806678 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In329806678 256)))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite27_Out329806678|) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite27_Out329806678| ~y$w_buff0_used~0_In329806678) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In329806678, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In329806678} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In329806678, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In329806678, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out329806678|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 17:32:31,178 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L842-->L842-2: Formula: (let ((.cse2 (= (mod ~y$r_buff0_thd0~0_In-1669046022 256) 0)) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In-1669046022 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In-1669046022 256))) (.cse0 (= (mod ~y$r_buff1_thd0~0_In-1669046022 256) 0))) (or (and (= ~y$w_buff1_used~0_In-1669046022 |ULTIMATE.start_main_#t~ite28_Out-1669046022|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |ULTIMATE.start_main_#t~ite28_Out-1669046022|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1669046022, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1669046022, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1669046022, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1669046022} OutVars{ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out-1669046022|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1669046022, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1669046022, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1669046022, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1669046022} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 17:32:31,178 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [790] [790] L843-->L843-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In746283412 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In746283412 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite29_Out746283412|)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite29_Out746283412| ~y$r_buff0_thd0~0_In746283412)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In746283412, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In746283412} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In746283412, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out746283412|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In746283412} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 17:32:31,178 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [814] [814] L844-->L844-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In826701854 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In826701854 256))) (.cse3 (= 0 (mod ~y$r_buff0_thd0~0_In826701854 256))) (.cse2 (= (mod ~y$w_buff0_used~0_In826701854 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite30_Out826701854|)) (and (or .cse0 .cse1) (or .cse3 .cse2) (= ~y$r_buff1_thd0~0_In826701854 |ULTIMATE.start_main_#t~ite30_Out826701854|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In826701854, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In826701854, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In826701854, ~y$w_buff1_used~0=~y$w_buff1_used~0_In826701854} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out826701854|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In826701854, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In826701854, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In826701854, ~y$w_buff1_used~0=~y$w_buff1_used~0_In826701854} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30] because there is no mapped edge [2019-12-07 17:32:31,180 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L853-->L853-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In649326340 256)))) (or (and (= |ULTIMATE.start_main_#t~ite40_Out649326340| ~y$w_buff1~0_In649326340) (not .cse0) (= |ULTIMATE.start_main_#t~ite39_In649326340| |ULTIMATE.start_main_#t~ite39_Out649326340|)) (and (= |ULTIMATE.start_main_#t~ite39_Out649326340| ~y$w_buff1~0_In649326340) .cse0 (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In649326340 256)))) (or (and (= 0 (mod ~y$r_buff1_thd0~0_In649326340 256)) .cse1) (= 0 (mod ~y$w_buff0_used~0_In649326340 256)) (and (= (mod ~y$w_buff1_used~0_In649326340 256) 0) .cse1))) (= |ULTIMATE.start_main_#t~ite39_Out649326340| |ULTIMATE.start_main_#t~ite40_Out649326340|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In649326340, ~y$w_buff0_used~0=~y$w_buff0_used~0_In649326340, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_In649326340|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In649326340, ~weak$$choice2~0=~weak$$choice2~0_In649326340, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In649326340, ~y$w_buff1_used~0=~y$w_buff1_used~0_In649326340} OutVars{ULTIMATE.start_main_#t~ite40=|ULTIMATE.start_main_#t~ite40_Out649326340|, ~y$w_buff1~0=~y$w_buff1~0_In649326340, ~y$w_buff0_used~0=~y$w_buff0_used~0_In649326340, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out649326340|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In649326340, ~weak$$choice2~0=~weak$$choice2~0_In649326340, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In649326340, ~y$w_buff1_used~0=~y$w_buff1_used~0_In649326340} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 17:32:31,181 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L856-->L857: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_15 256))) (= v_~y$r_buff0_thd0~0_45 v_~y$r_buff0_thd0~0_46)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_46, ~weak$$choice2~0=v_~weak$$choice2~0_15} OutVars{~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_45, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_7|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_8|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_8|, ~weak$$choice2~0=v_~weak$$choice2~0_15} AuxVars[] AssignedVars[~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 17:32:31,182 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [818] [818] L859-->L862-1: Formula: (and (= 0 v_~y$flush_delayed~0_19) (not (= 0 (mod v_~y$flush_delayed~0_20 256))) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4| (mod v_~main$tmp_guard1~0_8 256)) (= v_~y~0_103 v_~y$mem_tmp~0_9)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_9, ~y$flush_delayed~0=v_~y$flush_delayed~0_20, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_8} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_9, ~y$flush_delayed~0=v_~y$flush_delayed~0_19, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_8, ~y~0=v_~y~0_103, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_17|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[~y$flush_delayed~0, ~y~0, ULTIMATE.start_main_#t~ite53, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 17:32:31,182 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] L862-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 17:32:31,242 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 05:32:31 BasicIcfg [2019-12-07 17:32:31,242 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 17:32:31,242 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 17:32:31,243 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 17:32:31,243 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 17:32:31,243 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:28:42" (3/4) ... [2019-12-07 17:32:31,244 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 17:32:31,245 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [864] [864] ULTIMATE.startENTRY-->L828: Formula: (let ((.cse0 (store |v_#valid_77| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= 0 v_~y$r_buff1_thd3~0_186) (< 0 |v_#StackHeapBarrier_23|) (= v_~y$w_buff1_used~0_459 0) (= 0 v_~__unbuffered_p2_EAX~0_128) (= 0 v_~y$w_buff0~0_224) (= v_~a~0_40 0) (= 0 v_~y$r_buff0_thd3~0_213) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1433~0.base_27|)) (= v_~main$tmp_guard0~0_34 0) (= v_~y$r_buff0_thd1~0_40 0) (= v_~y$w_buff1~0_177 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t1433~0.base_27| 1) |v_#valid_75|) (= 0 v_~y$r_buff1_thd2~0_203) (= v_~main$tmp_guard1~0_21 0) (= 0 v_~y$r_buff1_thd4~0_197) (= v_~y$read_delayed~0_6 0) (= v_~y$mem_tmp~0_18 0) (= |v_ULTIMATE.start_main_~#t1433~0.offset_21| 0) (= v_~y$r_buff1_thd0~0_278 0) (= v_~y$r_buff0_thd0~0_327 0) (= v_~y$r_buff1_thd1~0_121 0) (< |v_#StackHeapBarrier_23| |v_ULTIMATE.start_main_~#t1433~0.base_27|) (= v_~z~0_47 0) (= 0 |v_#NULL.base_4|) (= 0 v_~__unbuffered_p3_EAX~0_23) (= v_~y~0_186 0) (= v_~x~0_50 0) (= v_~weak$$choice2~0_123 0) (= |v_#NULL.offset_4| 0) (= (store |v_#memory_int_30| |v_ULTIMATE.start_main_~#t1433~0.base_27| (store (select |v_#memory_int_30| |v_ULTIMATE.start_main_~#t1433~0.base_27|) |v_ULTIMATE.start_main_~#t1433~0.offset_21| 0)) |v_#memory_int_29|) (= v_~y$w_buff0_used~0_726 0) (= 0 v_~y$read_delayed_var~0.offset_6) (= 0 v_~weak$$choice0~0_13) (= v_~__unbuffered_cnt~0_227 0) (= |v_#length_33| (store |v_#length_34| |v_ULTIMATE.start_main_~#t1433~0.base_27| 4)) (= 0 v_~y$r_buff0_thd2~0_133) (= 0 v_~y$r_buff0_thd4~0_116) (= 0 v_~y$flush_delayed~0_34))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_23|, #valid=|v_#valid_77|, #memory_int=|v_#memory_int_30|, #length=|v_#length_34|} OutVars{ULTIMATE.start_main_#t~nondet32=|v_ULTIMATE.start_main_#t~nondet32_22|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_126|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_30|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_30|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_18|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_36|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_67|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_46|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~a~0=v_~a~0_40, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_34|, ~y$mem_tmp~0=v_~y$mem_tmp~0_18, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_186, ULTIMATE.start_main_~#t1433~0.offset=|v_ULTIMATE.start_main_~#t1433~0.offset_21|, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_40, ~y$flush_delayed~0=v_~y$flush_delayed~0_34, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_23, #length=|v_#length_33|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_128, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_41|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_36|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_31|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_22|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_60|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_23|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_45|, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_197, ULTIMATE.start_main_~#t1436~0.base=|v_ULTIMATE.start_main_~#t1436~0.base_21|, ~y$w_buff1~0=v_~y$w_buff1~0_177, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ULTIMATE.start_main_~#t1436~0.offset=|v_ULTIMATE.start_main_~#t1436~0.offset_17|, ULTIMATE.start_main_~#t1435~0.offset=|v_ULTIMATE.start_main_~#t1435~0.offset_18|, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_133, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_227, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_278, ~x~0=v_~x~0_50, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_22|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ULTIMATE.start_main_~#t1434~0.offset=|v_ULTIMATE.start_main_~#t1434~0.offset_21|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_726, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_32|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_36|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_53|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_26|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_30|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_67|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_121, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_34|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_48|, ~y$w_buff0~0=v_~y$w_buff0~0_224, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_213, ~y~0=v_~y~0_186, ULTIMATE.start_main_~#t1435~0.base=|v_ULTIMATE.start_main_~#t1435~0.base_23|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_10|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_10|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_35|, ULTIMATE.start_main_~#t1434~0.base=|v_ULTIMATE.start_main_~#t1434~0.base_27|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_35|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_34, ULTIMATE.start_main_~#t1433~0.base=|v_ULTIMATE.start_main_~#t1433~0.base_27|, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_33|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_104|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_203, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_116, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_31|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_21|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_327, #valid=|v_#valid_75|, #memory_int=|v_#memory_int_29|, ~z~0=v_~z~0_47, ~weak$$choice2~0=v_~weak$$choice2~0_123, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_459} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet32, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ~y$read_delayed~0, ~a~0, ULTIMATE.start_main_#t~ite52, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ULTIMATE.start_main_~#t1433~0.offset, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ~__unbuffered_p3_EAX~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$r_buff1_thd4~0, ULTIMATE.start_main_~#t1436~0.base, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ULTIMATE.start_main_~#t1436~0.offset, ULTIMATE.start_main_~#t1435~0.offset, ~y$r_buff0_thd2~0, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ~y$read_delayed_var~0.offset, ULTIMATE.start_main_~#t1434~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite51, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_~#t1435~0.base, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_~#t1434~0.base, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_~#t1433~0.base, ULTIMATE.start_main_#t~ite53, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ~y$r_buff0_thd4~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 17:32:31,245 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [842] [842] L828-1-->L830: Formula: (and (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1434~0.base_13| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t1434~0.base_13|) |v_ULTIMATE.start_main_~#t1434~0.offset_11| 1)) |v_#memory_int_19|) (= (store |v_#length_24| |v_ULTIMATE.start_main_~#t1434~0.base_13| 4) |v_#length_23|) (= |v_ULTIMATE.start_main_~#t1434~0.offset_11| 0) (= 0 (select |v_#valid_51| |v_ULTIMATE.start_main_~#t1434~0.base_13|)) (< |v_#StackHeapBarrier_15| |v_ULTIMATE.start_main_~#t1434~0.base_13|) (not (= 0 |v_ULTIMATE.start_main_~#t1434~0.base_13|)) (= |v_#valid_50| (store |v_#valid_51| |v_ULTIMATE.start_main_~#t1434~0.base_13| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_51|, #memory_int=|v_#memory_int_20|, #length=|v_#length_24|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_15|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_5|, ULTIMATE.start_main_~#t1434~0.offset=|v_ULTIMATE.start_main_~#t1434~0.offset_11|, #valid=|v_#valid_50|, #memory_int=|v_#memory_int_19|, ULTIMATE.start_main_~#t1434~0.base=|v_ULTIMATE.start_main_~#t1434~0.base_13|, #length=|v_#length_23|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t1434~0.offset, #valid, #memory_int, ULTIMATE.start_main_~#t1434~0.base, #length] because there is no mapped edge [2019-12-07 17:32:31,245 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [836] [836] L830-1-->L832: Formula: (and (not (= |v_ULTIMATE.start_main_~#t1435~0.base_12| 0)) (= 0 (select |v_#valid_47| |v_ULTIMATE.start_main_~#t1435~0.base_12|)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1435~0.base_12| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1435~0.base_12|) |v_ULTIMATE.start_main_~#t1435~0.offset_11| 2)) |v_#memory_int_15|) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t1435~0.base_12|) (= |v_ULTIMATE.start_main_~#t1435~0.offset_11| 0) (= |v_#valid_46| (store |v_#valid_47| |v_ULTIMATE.start_main_~#t1435~0.base_12| 1)) (= (store |v_#length_20| |v_ULTIMATE.start_main_~#t1435~0.base_12| 4) |v_#length_19|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, ULTIMATE.start_main_~#t1435~0.offset=|v_ULTIMATE.start_main_~#t1435~0.offset_11|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_15|, #length=|v_#length_19|, ULTIMATE.start_main_~#t1435~0.base=|v_ULTIMATE.start_main_~#t1435~0.base_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_~#t1435~0.offset, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1435~0.base] because there is no mapped edge [2019-12-07 17:32:31,246 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L832-1-->L834: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t1436~0.base_12|)) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t1436~0.base_12|) (= |v_#valid_48| (store |v_#valid_49| |v_ULTIMATE.start_main_~#t1436~0.base_12| 1)) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1436~0.base_12| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1436~0.base_12|) |v_ULTIMATE.start_main_~#t1436~0.offset_10| 3)) |v_#memory_int_17|) (= |v_ULTIMATE.start_main_~#t1436~0.offset_10| 0) (= 0 (select |v_#valid_49| |v_ULTIMATE.start_main_~#t1436~0.base_12|)) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t1436~0.base_12| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_49|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_~#t1436~0.base=|v_ULTIMATE.start_main_~#t1436~0.base_12|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ULTIMATE.start_main_~#t1436~0.offset=|v_ULTIMATE.start_main_~#t1436~0.offset_10|, #valid=|v_#valid_48|, #memory_int=|v_#memory_int_17|, #length=|v_#length_21|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1436~0.base, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_~#t1436~0.offset, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 17:32:31,246 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [750] [750] L4-->L785: Formula: (and (= v_~y$r_buff0_thd2~0_39 v_~y$r_buff1_thd2~0_26) (= v_~y$r_buff0_thd3~0_25 1) (= v_~y$r_buff1_thd1~0_5 v_~y$r_buff0_thd1~0_6) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_16)) (= v_~__unbuffered_p2_EAX~0_6 v_~z~0_8) (= v_~y$r_buff0_thd0~0_74 v_~y$r_buff1_thd0~0_48) (= v_~y$r_buff0_thd4~0_30 v_~y$r_buff1_thd4~0_17) (= v_~y$r_buff0_thd3~0_26 v_~y$r_buff1_thd3~0_18)) InVars {~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_30, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_26, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_74, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_39, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_6, ~z~0=v_~z~0_8, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_16} OutVars{P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_16, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_26, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_30, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_5, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_17, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_18, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_25, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_74, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_39, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_6, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_6, ~z~0=v_~z~0_8, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_48} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, ~y$r_buff1_thd1~0, ~y$r_buff1_thd4~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd3~0, ~__unbuffered_p2_EAX~0, ~y$r_buff1_thd0~0] because there is no mapped edge [2019-12-07 17:32:31,247 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [810] [810] L786-->L786-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd3~0_In-2076152962 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In-2076152962 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite11_Out-2076152962| ~y$w_buff0_used~0_In-2076152962) (or .cse0 .cse1)) (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out-2076152962| 0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-2076152962, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2076152962} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-2076152962, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-2076152962|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2076152962} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 17:32:31,247 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L787-->L787-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1063874344 256))) (.cse3 (= 0 (mod ~y$r_buff1_thd3~0_In-1063874344 256))) (.cse1 (= (mod ~y$r_buff0_thd3~0_In-1063874344 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1063874344 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite12_Out-1063874344| ~y$w_buff1_used~0_In-1063874344) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |P2Thread1of1ForFork0_#t~ite12_Out-1063874344| 0)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1063874344, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1063874344, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1063874344, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1063874344} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1063874344, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1063874344, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-1063874344|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1063874344, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1063874344} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 17:32:31,247 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [809] [809] L788-->L789: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd3~0_In-1120891944 256) 0)) (.cse2 (= ~y$r_buff0_thd3~0_In-1120891944 ~y$r_buff0_thd3~0_Out-1120891944)) (.cse1 (= (mod ~y$w_buff0_used~0_In-1120891944 256) 0))) (or (and (not .cse0) (= 0 ~y$r_buff0_thd3~0_Out-1120891944) (not .cse1)) (and .cse0 .cse2) (and .cse2 .cse1))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1120891944, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1120891944} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1120891944, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-1120891944, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-1120891944|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 17:32:31,247 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [813] [813] L789-->L789-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In898364897 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In898364897 256) 0)) (.cse1 (= (mod ~y$w_buff1_used~0_In898364897 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd3~0_In898364897 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork0_#t~ite14_Out898364897| 0)) (and (or .cse2 .cse3) (or .cse1 .cse0) (= |P2Thread1of1ForFork0_#t~ite14_Out898364897| ~y$r_buff1_thd3~0_In898364897)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In898364897, ~y$w_buff0_used~0=~y$w_buff0_used~0_In898364897, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In898364897, ~y$w_buff1_used~0=~y$w_buff1_used~0_In898364897} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out898364897|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In898364897, ~y$w_buff0_used~0=~y$w_buff0_used~0_In898364897, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In898364897, ~y$w_buff1_used~0=~y$w_buff1_used~0_In898364897} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 17:32:31,248 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L805-2-->L805-4: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In495156446 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd4~0_In495156446 256)))) (or (and (not .cse0) (= |P3Thread1of1ForFork1_#t~ite15_Out495156446| ~y$w_buff1~0_In495156446) (not .cse1)) (and (= |P3Thread1of1ForFork1_#t~ite15_Out495156446| ~y~0_In495156446) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In495156446, ~y$w_buff1~0=~y$w_buff1~0_In495156446, ~y~0=~y~0_In495156446, ~y$w_buff1_used~0=~y$w_buff1_used~0_In495156446} OutVars{~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In495156446, ~y$w_buff1~0=~y$w_buff1~0_In495156446, P3Thread1of1ForFork1_#t~ite15=|P3Thread1of1ForFork1_#t~ite15_Out495156446|, ~y~0=~y~0_In495156446, ~y$w_buff1_used~0=~y$w_buff1_used~0_In495156446} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite15] because there is no mapped edge [2019-12-07 17:32:31,248 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [828] [828] P0ENTRY-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork2_#res.offset_9| 0) (= |v_P0Thread1of1ForFork2_#in~arg.offset_15| v_P0Thread1of1ForFork2_~arg.offset_13) (= v_~x~0_24 1) (= v_P0Thread1of1ForFork2_~arg.base_13 |v_P0Thread1of1ForFork2_#in~arg.base_15|) (= 0 |v_P0Thread1of1ForFork2_#res.base_9|) (= (+ v_~__unbuffered_cnt~0_67 1) v_~__unbuffered_cnt~0_66) (= v_~a~0_18 1)) InVars {P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_15|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_15|} OutVars{~a~0=v_~a~0_18, P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_15|, P0Thread1of1ForFork2_~arg.offset=v_P0Thread1of1ForFork2_~arg.offset_13, P0Thread1of1ForFork2_#res.offset=|v_P0Thread1of1ForFork2_#res.offset_9|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_15|, P0Thread1of1ForFork2_#res.base=|v_P0Thread1of1ForFork2_#res.base_9|, ~x~0=v_~x~0_24, P0Thread1of1ForFork2_~arg.base=v_P0Thread1of1ForFork2_~arg.base_13} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork2_~arg.offset, P0Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0, P0Thread1of1ForFork2_#res.base, ~x~0, P0Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-12-07 17:32:31,248 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [830] [830] L789-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#t~ite14_32| v_~y$r_buff1_thd3~0_59) (= (+ v_~__unbuffered_cnt~0_85 1) v_~__unbuffered_cnt~0_84) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_85} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_31|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_59, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_84, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 17:32:31,249 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L805-4-->L806: Formula: (= v_~y~0_21 |v_P3Thread1of1ForFork1_#t~ite15_6|) InVars {P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_6|} OutVars{P3Thread1of1ForFork1_#t~ite16=|v_P3Thread1of1ForFork1_#t~ite16_5|, P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_5|, ~y~0=v_~y~0_21} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite16, P3Thread1of1ForFork1_#t~ite15, ~y~0] because there is no mapped edge [2019-12-07 17:32:31,249 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L806-->L806-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-788707118 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd4~0_In-788707118 256)))) (or (and (= ~y$w_buff0_used~0_In-788707118 |P3Thread1of1ForFork1_#t~ite17_Out-788707118|) (or .cse0 .cse1)) (and (not .cse0) (= 0 |P3Thread1of1ForFork1_#t~ite17_Out-788707118|) (not .cse1)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-788707118, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-788707118} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-788707118, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-788707118, P3Thread1of1ForFork1_#t~ite17=|P3Thread1of1ForFork1_#t~ite17_Out-788707118|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite17] because there is no mapped edge [2019-12-07 17:32:31,249 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L807-->L807-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In1961982443 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd4~0_In1961982443 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In1961982443 256) 0)) (.cse1 (= 0 (mod ~y$r_buff1_thd4~0_In1961982443 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P3Thread1of1ForFork1_#t~ite18_Out1961982443| 0)) (and (or .cse3 .cse2) (= |P3Thread1of1ForFork1_#t~ite18_Out1961982443| ~y$w_buff1_used~0_In1961982443) (or .cse0 .cse1)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1961982443, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1961982443, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1961982443, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1961982443} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1961982443, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1961982443, P3Thread1of1ForFork1_#t~ite18=|P3Thread1of1ForFork1_#t~ite18_Out1961982443|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1961982443, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1961982443} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite18] because there is no mapped edge [2019-12-07 17:32:31,249 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [794] [794] L755-2-->L755-5: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In257192711 256))) (.cse0 (= |P1Thread1of1ForFork3_#t~ite4_Out257192711| |P1Thread1of1ForFork3_#t~ite3_Out257192711|)) (.cse1 (= (mod ~y$r_buff1_thd2~0_In257192711 256) 0))) (or (and .cse0 (= ~y~0_In257192711 |P1Thread1of1ForFork3_#t~ite3_Out257192711|) (or .cse1 .cse2)) (and (not .cse2) (= ~y$w_buff1~0_In257192711 |P1Thread1of1ForFork3_#t~ite3_Out257192711|) .cse0 (not .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In257192711, ~y$w_buff1~0=~y$w_buff1~0_In257192711, ~y~0=~y~0_In257192711, ~y$w_buff1_used~0=~y$w_buff1_used~0_In257192711} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In257192711, ~y$w_buff1~0=~y$w_buff1~0_In257192711, P1Thread1of1ForFork3_#t~ite4=|P1Thread1of1ForFork3_#t~ite4_Out257192711|, P1Thread1of1ForFork3_#t~ite3=|P1Thread1of1ForFork3_#t~ite3_Out257192711|, ~y~0=~y~0_In257192711, ~y$w_buff1_used~0=~y$w_buff1_used~0_In257192711} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite4, P1Thread1of1ForFork3_#t~ite3] because there is no mapped edge [2019-12-07 17:32:31,250 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [808] [808] L808-->L808-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In2137503829 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd4~0_In2137503829 256)))) (or (and (not .cse0) (= 0 |P3Thread1of1ForFork1_#t~ite19_Out2137503829|) (not .cse1)) (and (or .cse1 .cse0) (= |P3Thread1of1ForFork1_#t~ite19_Out2137503829| ~y$r_buff0_thd4~0_In2137503829)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In2137503829, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2137503829} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In2137503829, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2137503829, P3Thread1of1ForFork1_#t~ite19=|P3Thread1of1ForFork1_#t~ite19_Out2137503829|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite19] because there is no mapped edge [2019-12-07 17:32:31,250 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L756-->L756-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1583603154 256) 0)) (.cse0 (= (mod ~y$r_buff0_thd2~0_In-1583603154 256) 0))) (or (and (= |P1Thread1of1ForFork3_#t~ite5_Out-1583603154| ~y$w_buff0_used~0_In-1583603154) (or .cse0 .cse1)) (and (= |P1Thread1of1ForFork3_#t~ite5_Out-1583603154| 0) (not .cse1) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1583603154, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1583603154} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1583603154, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1583603154, P1Thread1of1ForFork3_#t~ite5=|P1Thread1of1ForFork3_#t~ite5_Out-1583603154|} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite5] because there is no mapped edge [2019-12-07 17:32:31,250 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L757-->L757-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In-2136991176 256))) (.cse0 (= (mod ~y$r_buff1_thd2~0_In-2136991176 256) 0)) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In-2136991176 256))) (.cse2 (= (mod ~y$r_buff0_thd2~0_In-2136991176 256) 0))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork3_#t~ite6_Out-2136991176| ~y$w_buff1_used~0_In-2136991176) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2))) (= |P1Thread1of1ForFork3_#t~ite6_Out-2136991176| 0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2136991176, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2136991176, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2136991176, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2136991176} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2136991176, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2136991176, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2136991176, P1Thread1of1ForFork3_#t~ite6=|P1Thread1of1ForFork3_#t~ite6_Out-2136991176|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2136991176} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite6] because there is no mapped edge [2019-12-07 17:32:31,251 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [812] [812] L758-->L758-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd2~0_In-1692963214 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1692963214 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork3_#t~ite7_Out-1692963214|)) (and (= ~y$r_buff0_thd2~0_In-1692963214 |P1Thread1of1ForFork3_#t~ite7_Out-1692963214|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1692963214, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1692963214} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1692963214, P1Thread1of1ForFork3_#t~ite7=|P1Thread1of1ForFork3_#t~ite7_Out-1692963214|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1692963214} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite7] because there is no mapped edge [2019-12-07 17:32:31,251 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L809-->L809-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd4~0_In-788594088 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In-788594088 256) 0)) (.cse2 (= (mod ~y$w_buff1_used~0_In-788594088 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd4~0_In-788594088 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P3Thread1of1ForFork1_#t~ite20_Out-788594088| ~y$r_buff1_thd4~0_In-788594088)) (and (= |P3Thread1of1ForFork1_#t~ite20_Out-788594088| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-788594088, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-788594088, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-788594088, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-788594088} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-788594088, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-788594088, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-788594088, P3Thread1of1ForFork1_#t~ite20=|P3Thread1of1ForFork1_#t~ite20_Out-788594088|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-788594088} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 17:32:31,251 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L809-2-->P3EXIT: Formula: (and (= v_~__unbuffered_cnt~0_144 (+ v_~__unbuffered_cnt~0_145 1)) (= |v_P3Thread1of1ForFork1_#t~ite20_56| v_~y$r_buff1_thd4~0_148) (= |v_P3Thread1of1ForFork1_#res.offset_3| 0) (= |v_P3Thread1of1ForFork1_#res.base_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_145, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_56|} OutVars{~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_148, P3Thread1of1ForFork1_#res.base=|v_P3Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_144, P3Thread1of1ForFork1_#res.offset=|v_P3Thread1of1ForFork1_#res.offset_3|, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_55|} AuxVars[] AssignedVars[~y$r_buff1_thd4~0, P3Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork1_#res.offset, P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 17:32:31,251 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [797] [797] L759-->L759-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In-1406188992 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In-1406188992 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In-1406188992 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In-1406188992 256) 0))) (or (and (= ~y$r_buff1_thd2~0_In-1406188992 |P1Thread1of1ForFork3_#t~ite8_Out-1406188992|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork3_#t~ite8_Out-1406188992| 0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1406188992, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1406188992, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1406188992, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1406188992} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1406188992, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1406188992, P1Thread1of1ForFork3_#t~ite8=|P1Thread1of1ForFork3_#t~ite8_Out-1406188992|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1406188992, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1406188992} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite8] because there is no mapped edge [2019-12-07 17:32:31,251 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [831] [831] L759-2-->P1EXIT: Formula: (and (= v_~__unbuffered_cnt~0_108 (+ v_~__unbuffered_cnt~0_109 1)) (= 0 |v_P1Thread1of1ForFork3_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork3_#res.base_3|) (= |v_P1Thread1of1ForFork3_#t~ite8_48| v_~y$r_buff1_thd2~0_69)) InVars {P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_48|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_109} OutVars{P1Thread1of1ForFork3_#res.base=|v_P1Thread1of1ForFork3_#res.base_3|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_69, P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_47|, P1Thread1of1ForFork3_#res.offset=|v_P1Thread1of1ForFork3_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_108} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#res.base, ~y$r_buff1_thd2~0, P1Thread1of1ForFork3_#t~ite8, P1Thread1of1ForFork3_#res.offset, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 17:32:31,251 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [742] [742] L834-1-->L840: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (= v_~main$tmp_guard0~0_8 (ite (= 0 (ite (= 4 v_~__unbuffered_cnt~0_26) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_26} OutVars{ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_7|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_26, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet24, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 17:32:31,252 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L840-2-->L840-4: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-1662439110 256))) (.cse1 (= (mod ~y$w_buff1_used~0_In-1662439110 256) 0))) (or (and (or .cse0 .cse1) (= ~y~0_In-1662439110 |ULTIMATE.start_main_#t~ite25_Out-1662439110|)) (and (not .cse0) (= |ULTIMATE.start_main_#t~ite25_Out-1662439110| ~y$w_buff1~0_In-1662439110) (not .cse1)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1662439110, ~y~0=~y~0_In-1662439110, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1662439110, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1662439110} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1662439110, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-1662439110|, ~y~0=~y~0_In-1662439110, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1662439110, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1662439110} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 17:32:31,252 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [749] [749] L840-4-->L841: Formula: (= v_~y~0_56 |v_ULTIMATE.start_main_#t~ite25_9|) InVars {ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_9|} OutVars{ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_8|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_12|, ~y~0=v_~y~0_56} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite26, ~y~0] because there is no mapped edge [2019-12-07 17:32:31,252 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [811] [811] L841-->L841-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In329806678 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In329806678 256)))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite27_Out329806678|) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite27_Out329806678| ~y$w_buff0_used~0_In329806678) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In329806678, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In329806678} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In329806678, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In329806678, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out329806678|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 17:32:31,252 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L842-->L842-2: Formula: (let ((.cse2 (= (mod ~y$r_buff0_thd0~0_In-1669046022 256) 0)) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In-1669046022 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In-1669046022 256))) (.cse0 (= (mod ~y$r_buff1_thd0~0_In-1669046022 256) 0))) (or (and (= ~y$w_buff1_used~0_In-1669046022 |ULTIMATE.start_main_#t~ite28_Out-1669046022|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |ULTIMATE.start_main_#t~ite28_Out-1669046022|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1669046022, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1669046022, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1669046022, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1669046022} OutVars{ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out-1669046022|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1669046022, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1669046022, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1669046022, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1669046022} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 17:32:31,253 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [790] [790] L843-->L843-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In746283412 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In746283412 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite29_Out746283412|)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite29_Out746283412| ~y$r_buff0_thd0~0_In746283412)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In746283412, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In746283412} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In746283412, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out746283412|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In746283412} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 17:32:31,253 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [814] [814] L844-->L844-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In826701854 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In826701854 256))) (.cse3 (= 0 (mod ~y$r_buff0_thd0~0_In826701854 256))) (.cse2 (= (mod ~y$w_buff0_used~0_In826701854 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite30_Out826701854|)) (and (or .cse0 .cse1) (or .cse3 .cse2) (= ~y$r_buff1_thd0~0_In826701854 |ULTIMATE.start_main_#t~ite30_Out826701854|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In826701854, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In826701854, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In826701854, ~y$w_buff1_used~0=~y$w_buff1_used~0_In826701854} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out826701854|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In826701854, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In826701854, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In826701854, ~y$w_buff1_used~0=~y$w_buff1_used~0_In826701854} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30] because there is no mapped edge [2019-12-07 17:32:31,254 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L853-->L853-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In649326340 256)))) (or (and (= |ULTIMATE.start_main_#t~ite40_Out649326340| ~y$w_buff1~0_In649326340) (not .cse0) (= |ULTIMATE.start_main_#t~ite39_In649326340| |ULTIMATE.start_main_#t~ite39_Out649326340|)) (and (= |ULTIMATE.start_main_#t~ite39_Out649326340| ~y$w_buff1~0_In649326340) .cse0 (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In649326340 256)))) (or (and (= 0 (mod ~y$r_buff1_thd0~0_In649326340 256)) .cse1) (= 0 (mod ~y$w_buff0_used~0_In649326340 256)) (and (= (mod ~y$w_buff1_used~0_In649326340 256) 0) .cse1))) (= |ULTIMATE.start_main_#t~ite39_Out649326340| |ULTIMATE.start_main_#t~ite40_Out649326340|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In649326340, ~y$w_buff0_used~0=~y$w_buff0_used~0_In649326340, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_In649326340|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In649326340, ~weak$$choice2~0=~weak$$choice2~0_In649326340, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In649326340, ~y$w_buff1_used~0=~y$w_buff1_used~0_In649326340} OutVars{ULTIMATE.start_main_#t~ite40=|ULTIMATE.start_main_#t~ite40_Out649326340|, ~y$w_buff1~0=~y$w_buff1~0_In649326340, ~y$w_buff0_used~0=~y$w_buff0_used~0_In649326340, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out649326340|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In649326340, ~weak$$choice2~0=~weak$$choice2~0_In649326340, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In649326340, ~y$w_buff1_used~0=~y$w_buff1_used~0_In649326340} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 17:32:31,256 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L856-->L857: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_15 256))) (= v_~y$r_buff0_thd0~0_45 v_~y$r_buff0_thd0~0_46)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_46, ~weak$$choice2~0=v_~weak$$choice2~0_15} OutVars{~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_45, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_7|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_8|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_8|, ~weak$$choice2~0=v_~weak$$choice2~0_15} AuxVars[] AssignedVars[~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 17:32:31,256 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [818] [818] L859-->L862-1: Formula: (and (= 0 v_~y$flush_delayed~0_19) (not (= 0 (mod v_~y$flush_delayed~0_20 256))) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4| (mod v_~main$tmp_guard1~0_8 256)) (= v_~y~0_103 v_~y$mem_tmp~0_9)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_9, ~y$flush_delayed~0=v_~y$flush_delayed~0_20, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_8} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_9, ~y$flush_delayed~0=v_~y$flush_delayed~0_19, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_8, ~y~0=v_~y~0_103, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_17|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[~y$flush_delayed~0, ~y~0, ULTIMATE.start_main_#t~ite53, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 17:32:31,256 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] L862-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 17:32:31,313 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_464aa81c-7005-4763-90d5-511086e375c5/bin/uautomizer/witness.graphml [2019-12-07 17:32:31,313 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 17:32:31,314 INFO L168 Benchmark]: Toolchain (without parser) took 229560.14 ms. Allocated memory was 1.0 GB in the beginning and 9.0 GB in the end (delta: 8.0 GB). Free memory was 937.2 MB in the beginning and 4.9 GB in the end (delta: -4.0 GB). Peak memory consumption was 4.0 GB. Max. memory is 11.5 GB. [2019-12-07 17:32:31,314 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 958.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 17:32:31,314 INFO L168 Benchmark]: CACSL2BoogieTranslator took 384.53 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 137.9 MB). Free memory was 937.2 MB in the beginning and 1.1 GB in the end (delta: -163.0 MB). Peak memory consumption was 18.5 MB. Max. memory is 11.5 GB. [2019-12-07 17:32:31,315 INFO L168 Benchmark]: Boogie Procedure Inliner took 40.30 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 17:32:31,315 INFO L168 Benchmark]: Boogie Preprocessor took 26.43 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 17:32:31,315 INFO L168 Benchmark]: RCFGBuilder took 424.45 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.2 MB). Peak memory consumption was 55.2 MB. Max. memory is 11.5 GB. [2019-12-07 17:32:31,315 INFO L168 Benchmark]: TraceAbstraction took 228611.03 ms. Allocated memory was 1.2 GB in the beginning and 9.0 GB in the end (delta: 7.8 GB). Free memory was 1.0 GB in the beginning and 5.0 GB in the end (delta: -3.9 GB). Peak memory consumption was 3.9 GB. Max. memory is 11.5 GB. [2019-12-07 17:32:31,315 INFO L168 Benchmark]: Witness Printer took 70.30 ms. Allocated memory is still 9.0 GB. Free memory was 5.0 GB in the beginning and 4.9 GB in the end (delta: 37.8 MB). Peak memory consumption was 37.8 MB. Max. memory is 11.5 GB. [2019-12-07 17:32:31,317 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 958.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 384.53 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 137.9 MB). Free memory was 937.2 MB in the beginning and 1.1 GB in the end (delta: -163.0 MB). Peak memory consumption was 18.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 40.30 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.43 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 424.45 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.2 MB). Peak memory consumption was 55.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 228611.03 ms. Allocated memory was 1.2 GB in the beginning and 9.0 GB in the end (delta: 7.8 GB). Free memory was 1.0 GB in the beginning and 5.0 GB in the end (delta: -3.9 GB). Peak memory consumption was 3.9 GB. Max. memory is 11.5 GB. * Witness Printer took 70.30 ms. Allocated memory is still 9.0 GB. Free memory was 5.0 GB in the beginning and 4.9 GB in the end (delta: 37.8 MB). Peak memory consumption was 37.8 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.2s, 191 ProgramPointsBefore, 102 ProgramPointsAfterwards, 225 TransitionsBefore, 111 TransitionsAfterwards, 18432 CoEnabledTransitionPairs, 8 FixpointIterations, 35 TrivialSequentialCompositions, 45 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 40 ConcurrentYvCompositions, 30 ChoiceCompositions, 7107 VarBasedMoverChecksPositive, 245 VarBasedMoverChecksNegative, 82 SemBasedMoverChecksPositive, 237 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.8s, 0 MoverChecksTotal, 90358 CheckedPairsTotal, 120 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L828] FCALL, FORK 0 pthread_create(&t1433, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L830] FCALL, FORK 0 pthread_create(&t1434, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L832] FCALL, FORK 0 pthread_create(&t1435, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L769] 3 y$w_buff1 = y$w_buff0 [L770] 3 y$w_buff0 = 2 [L771] 3 y$w_buff1_used = y$w_buff0_used [L772] 3 y$w_buff0_used = (_Bool)1 [L834] FCALL, FORK 0 pthread_create(&t1436, ((void *)0), P3, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=0] [L785] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=0] [L785] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L786] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L787] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L799] 4 z = 1 [L802] 4 __unbuffered_p3_EAX = a VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L805] 4 y$w_buff0_used && y$r_buff0_thd4 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd4 ? y$w_buff1 : y) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L749] 2 x = 2 [L752] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, y$w_buff1_used && y$r_buff1_thd4 ? y$w_buff1 : y=2, z=1] [L755] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, y$w_buff1_used && y$r_buff1_thd4 ? y$w_buff1 : y=2, z=1] [L806] 4 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd4 ? (_Bool)0 : y$w_buff0_used [L755] 2 y = y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) [L807] 4 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd4 || y$w_buff1_used && y$r_buff1_thd4 ? (_Bool)0 : y$w_buff1_used [L756] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L757] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L808] 4 y$r_buff0_thd4 = y$w_buff0_used && y$r_buff0_thd4 ? (_Bool)0 : y$r_buff0_thd4 [L758] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L840] 0 y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L841] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L842] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L843] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L844] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L847] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L848] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L849] 0 y$flush_delayed = weak$$choice2 [L850] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L851] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L851] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L852] EXPR 0 weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L852] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L853] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L854] EXPR 0 weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L854] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L855] EXPR 0 weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L855] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L857] EXPR 0 weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L857] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L858] 0 main$tmp_guard1 = !(x == 2 && y == 2 && __unbuffered_p2_EAX == 0 && __unbuffered_p3_EAX == 0) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 179 locations, 2 error locations. Result: UNSAFE, OverallTime: 228.4s, OverallIterations: 21, TraceHistogramMax: 1, AutomataDifference: 51.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 3328 SDtfs, 2761 SDslu, 6223 SDs, 0 SdLazy, 2845 SolverSat, 150 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 144 GetRequests, 32 SyntacticMatches, 15 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 123 ImplicationChecksByTransitivity, 0.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=424932occurred in iteration=5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 124.3s AutomataMinimizationTime, 20 MinimizatonAttempts, 570852 StatesRemovedByMinimization, 15 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 0.8s InterpolantComputationTime, 933 NumberOfCodeBlocks, 933 NumberOfCodeBlocksAsserted, 21 NumberOfCheckSat, 842 ConstructedInterpolants, 0 QuantifiedInterpolants, 170231 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 20 InterpolantComputations, 20 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...