./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix057_pso.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_63a3ea3c-e52a-495d-8b24-6ec983fbeb86/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_63a3ea3c-e52a-495d-8b24-6ec983fbeb86/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_63a3ea3c-e52a-495d-8b24-6ec983fbeb86/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_63a3ea3c-e52a-495d-8b24-6ec983fbeb86/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix057_pso.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_63a3ea3c-e52a-495d-8b24-6ec983fbeb86/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_63a3ea3c-e52a-495d-8b24-6ec983fbeb86/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ad686c605e14bdf1ca981a585fa7d70654556c90 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 17:13:12,093 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 17:13:12,094 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 17:13:12,102 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 17:13:12,102 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 17:13:12,103 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 17:13:12,104 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 17:13:12,105 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 17:13:12,106 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 17:13:12,107 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 17:13:12,107 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 17:13:12,108 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 17:13:12,108 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 17:13:12,109 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 17:13:12,110 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 17:13:12,110 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 17:13:12,111 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 17:13:12,112 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 17:13:12,113 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 17:13:12,114 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 17:13:12,115 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 17:13:12,116 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 17:13:12,117 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 17:13:12,117 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 17:13:12,119 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 17:13:12,119 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 17:13:12,119 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 17:13:12,120 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 17:13:12,120 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 17:13:12,121 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 17:13:12,121 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 17:13:12,121 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 17:13:12,121 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 17:13:12,122 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 17:13:12,122 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 17:13:12,123 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 17:13:12,123 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 17:13:12,123 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 17:13:12,123 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 17:13:12,124 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 17:13:12,124 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 17:13:12,125 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_63a3ea3c-e52a-495d-8b24-6ec983fbeb86/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 17:13:12,133 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 17:13:12,133 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 17:13:12,134 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 17:13:12,134 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 17:13:12,134 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 17:13:12,135 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 17:13:12,135 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 17:13:12,135 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 17:13:12,135 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 17:13:12,135 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 17:13:12,135 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 17:13:12,135 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 17:13:12,135 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 17:13:12,135 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 17:13:12,136 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 17:13:12,136 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 17:13:12,136 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 17:13:12,136 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 17:13:12,136 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 17:13:12,136 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 17:13:12,136 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 17:13:12,136 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:13:12,137 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 17:13:12,137 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 17:13:12,137 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 17:13:12,137 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 17:13:12,137 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 17:13:12,137 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 17:13:12,137 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 17:13:12,138 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_63a3ea3c-e52a-495d-8b24-6ec983fbeb86/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ad686c605e14bdf1ca981a585fa7d70654556c90 [2019-12-07 17:13:12,238 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 17:13:12,245 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 17:13:12,248 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 17:13:12,249 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 17:13:12,249 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 17:13:12,249 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_63a3ea3c-e52a-495d-8b24-6ec983fbeb86/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix057_pso.opt.i [2019-12-07 17:13:12,287 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_63a3ea3c-e52a-495d-8b24-6ec983fbeb86/bin/uautomizer/data/f79a8b574/65361d72847240719b36d69104adc93b/FLAGfa9bcd6ab [2019-12-07 17:13:12,785 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 17:13:12,786 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_63a3ea3c-e52a-495d-8b24-6ec983fbeb86/sv-benchmarks/c/pthread-wmm/mix057_pso.opt.i [2019-12-07 17:13:12,795 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_63a3ea3c-e52a-495d-8b24-6ec983fbeb86/bin/uautomizer/data/f79a8b574/65361d72847240719b36d69104adc93b/FLAGfa9bcd6ab [2019-12-07 17:13:12,804 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_63a3ea3c-e52a-495d-8b24-6ec983fbeb86/bin/uautomizer/data/f79a8b574/65361d72847240719b36d69104adc93b [2019-12-07 17:13:12,806 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 17:13:12,807 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 17:13:12,807 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 17:13:12,808 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 17:13:12,810 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 17:13:12,810 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:13:12" (1/1) ... [2019-12-07 17:13:12,812 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@490253ea and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:13:12, skipping insertion in model container [2019-12-07 17:13:12,812 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:13:12" (1/1) ... [2019-12-07 17:13:12,817 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 17:13:12,845 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 17:13:13,092 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:13:13,100 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 17:13:13,150 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:13:13,216 INFO L208 MainTranslator]: Completed translation [2019-12-07 17:13:13,216 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:13:13 WrapperNode [2019-12-07 17:13:13,216 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 17:13:13,217 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 17:13:13,217 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 17:13:13,217 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 17:13:13,225 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:13:13" (1/1) ... [2019-12-07 17:13:13,243 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:13:13" (1/1) ... [2019-12-07 17:13:13,273 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 17:13:13,273 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 17:13:13,274 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 17:13:13,274 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 17:13:13,283 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:13:13" (1/1) ... [2019-12-07 17:13:13,284 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:13:13" (1/1) ... [2019-12-07 17:13:13,288 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:13:13" (1/1) ... [2019-12-07 17:13:13,289 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:13:13" (1/1) ... [2019-12-07 17:13:13,299 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:13:13" (1/1) ... [2019-12-07 17:13:13,303 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:13:13" (1/1) ... [2019-12-07 17:13:13,307 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:13:13" (1/1) ... [2019-12-07 17:13:13,312 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 17:13:13,312 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 17:13:13,312 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 17:13:13,312 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 17:13:13,313 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:13:13" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_63a3ea3c-e52a-495d-8b24-6ec983fbeb86/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:13:13,359 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 17:13:13,359 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 17:13:13,359 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 17:13:13,359 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 17:13:13,359 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 17:13:13,360 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 17:13:13,360 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 17:13:13,360 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 17:13:13,360 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 17:13:13,360 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 17:13:13,360 INFO L130 BoogieDeclarations]: Found specification of procedure P3 [2019-12-07 17:13:13,361 INFO L138 BoogieDeclarations]: Found implementation of procedure P3 [2019-12-07 17:13:13,361 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 17:13:13,361 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 17:13:13,361 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 17:13:13,363 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 17:13:13,723 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 17:13:13,723 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 17:13:13,724 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:13:13 BoogieIcfgContainer [2019-12-07 17:13:13,724 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 17:13:13,725 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 17:13:13,725 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 17:13:13,727 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 17:13:13,727 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 05:13:12" (1/3) ... [2019-12-07 17:13:13,728 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@81894c7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:13:13, skipping insertion in model container [2019-12-07 17:13:13,728 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:13:13" (2/3) ... [2019-12-07 17:13:13,728 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@81894c7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:13:13, skipping insertion in model container [2019-12-07 17:13:13,728 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:13:13" (3/3) ... [2019-12-07 17:13:13,729 INFO L109 eAbstractionObserver]: Analyzing ICFG mix057_pso.opt.i [2019-12-07 17:13:13,735 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 17:13:13,736 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 17:13:13,741 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 17:13:13,741 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 17:13:13,764 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork3_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,764 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork3_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,765 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork3_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,765 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork3_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,765 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork3_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,765 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork3_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,765 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,765 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,766 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,766 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,766 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,766 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,766 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,766 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,766 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,766 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,767 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,767 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,767 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,767 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,767 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,767 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,767 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,767 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,768 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,768 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,768 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,768 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,768 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,768 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,768 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,768 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,768 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,769 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,769 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,769 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,769 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,769 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,769 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,769 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,769 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,769 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,770 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,770 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,770 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,770 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,770 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,770 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,771 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,771 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,771 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,771 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,771 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,771 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,771 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,772 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,772 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,772 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,772 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,772 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,772 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,772 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,772 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,772 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,773 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,773 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,773 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,773 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,773 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,773 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,773 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,773 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,773 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,773 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,774 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,774 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:13:13,786 INFO L249 AbstractCegarLoop]: Starting to check reachability of 7 error locations. [2019-12-07 17:13:13,798 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 17:13:13,798 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 17:13:13,798 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 17:13:13,799 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 17:13:13,799 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 17:13:13,799 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 17:13:13,799 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 17:13:13,799 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 17:13:13,812 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 178 places, 206 transitions [2019-12-07 17:13:13,813 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 178 places, 206 transitions [2019-12-07 17:13:13,876 INFO L134 PetriNetUnfolder]: 41/202 cut-off events. [2019-12-07 17:13:13,876 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 17:13:13,885 INFO L76 FinitePrefix]: Finished finitePrefix Result has 215 conditions, 202 events. 41/202 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 483 event pairs. 12/171 useless extension candidates. Maximal degree in co-relation 172. Up to 2 conditions per place. [2019-12-07 17:13:13,896 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 178 places, 206 transitions [2019-12-07 17:13:13,932 INFO L134 PetriNetUnfolder]: 41/202 cut-off events. [2019-12-07 17:13:13,933 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 17:13:13,937 INFO L76 FinitePrefix]: Finished finitePrefix Result has 215 conditions, 202 events. 41/202 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 483 event pairs. 12/171 useless extension candidates. Maximal degree in co-relation 172. Up to 2 conditions per place. [2019-12-07 17:13:13,949 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 12668 [2019-12-07 17:13:13,950 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 17:13:16,991 WARN L192 SmtUtils]: Spent 172.00 ms on a formula simplification. DAG size of input: 93 DAG size of output: 91 [2019-12-07 17:13:17,080 INFO L206 etLargeBlockEncoding]: Checked pairs total: 56276 [2019-12-07 17:13:17,080 INFO L214 etLargeBlockEncoding]: Total number of compositions: 119 [2019-12-07 17:13:17,082 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 91 places, 100 transitions [2019-12-07 17:13:18,885 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 32878 states. [2019-12-07 17:13:18,887 INFO L276 IsEmpty]: Start isEmpty. Operand 32878 states. [2019-12-07 17:13:18,891 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2019-12-07 17:13:18,892 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:13:18,892 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:13:18,892 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:13:18,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:13:18,896 INFO L82 PathProgramCache]: Analyzing trace with hash -667351009, now seen corresponding path program 1 times [2019-12-07 17:13:18,901 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:13:18,902 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [492934347] [2019-12-07 17:13:18,902 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:13:18,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:13:19,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:13:19,056 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [492934347] [2019-12-07 17:13:19,057 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:13:19,057 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 17:13:19,057 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [833293379] [2019-12-07 17:13:19,060 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:13:19,061 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:13:19,069 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:13:19,070 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:13:19,071 INFO L87 Difference]: Start difference. First operand 32878 states. Second operand 3 states. [2019-12-07 17:13:19,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:13:19,383 INFO L93 Difference]: Finished difference Result 32686 states and 139960 transitions. [2019-12-07 17:13:19,384 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:13:19,385 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 9 [2019-12-07 17:13:19,385 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:13:19,591 INFO L225 Difference]: With dead ends: 32686 [2019-12-07 17:13:19,592 INFO L226 Difference]: Without dead ends: 32062 [2019-12-07 17:13:19,593 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:13:19,841 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32062 states. [2019-12-07 17:13:20,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32062 to 32062. [2019-12-07 17:13:20,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32062 states. [2019-12-07 17:13:20,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32062 states to 32062 states and 137412 transitions. [2019-12-07 17:13:20,566 INFO L78 Accepts]: Start accepts. Automaton has 32062 states and 137412 transitions. Word has length 9 [2019-12-07 17:13:20,567 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:13:20,567 INFO L462 AbstractCegarLoop]: Abstraction has 32062 states and 137412 transitions. [2019-12-07 17:13:20,567 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:13:20,567 INFO L276 IsEmpty]: Start isEmpty. Operand 32062 states and 137412 transitions. [2019-12-07 17:13:20,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 17:13:20,572 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:13:20,572 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:13:20,572 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:13:20,573 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:13:20,573 INFO L82 PathProgramCache]: Analyzing trace with hash -139405083, now seen corresponding path program 1 times [2019-12-07 17:13:20,573 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:13:20,573 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800439528] [2019-12-07 17:13:20,573 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:13:20,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:13:20,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:13:20,631 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1800439528] [2019-12-07 17:13:20,631 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:13:20,631 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:13:20,631 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [678353826] [2019-12-07 17:13:20,632 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:13:20,633 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:13:20,633 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:13:20,633 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:13:20,633 INFO L87 Difference]: Start difference. First operand 32062 states and 137412 transitions. Second operand 4 states. [2019-12-07 17:13:21,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:13:21,159 INFO L93 Difference]: Finished difference Result 51166 states and 211740 transitions. [2019-12-07 17:13:21,159 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:13:21,159 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 17:13:21,160 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:13:21,351 INFO L225 Difference]: With dead ends: 51166 [2019-12-07 17:13:21,351 INFO L226 Difference]: Without dead ends: 51138 [2019-12-07 17:13:21,352 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:13:21,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51138 states. [2019-12-07 17:13:22,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51138 to 46670. [2019-12-07 17:13:22,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46670 states. [2019-12-07 17:13:22,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46670 states to 46670 states and 195108 transitions. [2019-12-07 17:13:22,491 INFO L78 Accepts]: Start accepts. Automaton has 46670 states and 195108 transitions. Word has length 15 [2019-12-07 17:13:22,491 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:13:22,491 INFO L462 AbstractCegarLoop]: Abstraction has 46670 states and 195108 transitions. [2019-12-07 17:13:22,492 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:13:22,492 INFO L276 IsEmpty]: Start isEmpty. Operand 46670 states and 195108 transitions. [2019-12-07 17:13:22,494 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 17:13:22,494 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:13:22,494 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:13:22,494 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:13:22,494 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:13:22,495 INFO L82 PathProgramCache]: Analyzing trace with hash 2113277815, now seen corresponding path program 1 times [2019-12-07 17:13:22,495 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:13:22,495 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915976727] [2019-12-07 17:13:22,495 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:13:22,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:13:22,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:13:22,540 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1915976727] [2019-12-07 17:13:22,540 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:13:22,540 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:13:22,540 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1007191775] [2019-12-07 17:13:22,540 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:13:22,540 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:13:22,541 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:13:22,541 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:13:22,541 INFO L87 Difference]: Start difference. First operand 46670 states and 195108 transitions. Second operand 4 states. [2019-12-07 17:13:22,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:13:22,886 INFO L93 Difference]: Finished difference Result 57898 states and 240332 transitions. [2019-12-07 17:13:22,887 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:13:22,887 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 17:13:22,887 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:13:23,199 INFO L225 Difference]: With dead ends: 57898 [2019-12-07 17:13:23,199 INFO L226 Difference]: Without dead ends: 57898 [2019-12-07 17:13:23,199 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:13:23,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57898 states. [2019-12-07 17:13:24,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57898 to 51310. [2019-12-07 17:13:24,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51310 states. [2019-12-07 17:13:24,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51310 states to 51310 states and 214288 transitions. [2019-12-07 17:13:24,454 INFO L78 Accepts]: Start accepts. Automaton has 51310 states and 214288 transitions. Word has length 15 [2019-12-07 17:13:24,454 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:13:24,454 INFO L462 AbstractCegarLoop]: Abstraction has 51310 states and 214288 transitions. [2019-12-07 17:13:24,454 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:13:24,454 INFO L276 IsEmpty]: Start isEmpty. Operand 51310 states and 214288 transitions. [2019-12-07 17:13:24,462 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 17:13:24,463 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:13:24,463 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:13:24,463 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:13:24,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:13:24,463 INFO L82 PathProgramCache]: Analyzing trace with hash -942234691, now seen corresponding path program 1 times [2019-12-07 17:13:24,463 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:13:24,464 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1092346027] [2019-12-07 17:13:24,464 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:13:24,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:13:24,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:13:24,544 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1092346027] [2019-12-07 17:13:24,544 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:13:24,544 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:13:24,544 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1717612310] [2019-12-07 17:13:24,544 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:13:24,544 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:13:24,545 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:13:24,545 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:13:24,545 INFO L87 Difference]: Start difference. First operand 51310 states and 214288 transitions. Second operand 6 states. [2019-12-07 17:13:25,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:13:25,077 INFO L93 Difference]: Finished difference Result 66694 states and 274624 transitions. [2019-12-07 17:13:25,078 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 17:13:25,078 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 21 [2019-12-07 17:13:25,078 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:13:25,230 INFO L225 Difference]: With dead ends: 66694 [2019-12-07 17:13:25,230 INFO L226 Difference]: Without dead ends: 66694 [2019-12-07 17:13:25,230 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2019-12-07 17:13:25,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66694 states. [2019-12-07 17:13:26,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66694 to 51986. [2019-12-07 17:13:26,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51986 states. [2019-12-07 17:13:26,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51986 states to 51986 states and 216784 transitions. [2019-12-07 17:13:26,567 INFO L78 Accepts]: Start accepts. Automaton has 51986 states and 216784 transitions. Word has length 21 [2019-12-07 17:13:26,567 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:13:26,567 INFO L462 AbstractCegarLoop]: Abstraction has 51986 states and 216784 transitions. [2019-12-07 17:13:26,567 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:13:26,567 INFO L276 IsEmpty]: Start isEmpty. Operand 51986 states and 216784 transitions. [2019-12-07 17:13:26,585 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 17:13:26,585 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:13:26,585 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:13:26,585 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:13:26,585 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:13:26,585 INFO L82 PathProgramCache]: Analyzing trace with hash 1938077526, now seen corresponding path program 1 times [2019-12-07 17:13:26,586 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:13:26,586 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776257360] [2019-12-07 17:13:26,586 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:13:26,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:13:26,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:13:26,637 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1776257360] [2019-12-07 17:13:26,637 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:13:26,637 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:13:26,637 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2050990078] [2019-12-07 17:13:26,637 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:13:26,637 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:13:26,638 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:13:26,638 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:13:26,638 INFO L87 Difference]: Start difference. First operand 51986 states and 216784 transitions. Second operand 5 states. [2019-12-07 17:13:27,185 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:13:27,185 INFO L93 Difference]: Finished difference Result 68254 states and 280512 transitions. [2019-12-07 17:13:27,186 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:13:27,186 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 25 [2019-12-07 17:13:27,186 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:13:27,341 INFO L225 Difference]: With dead ends: 68254 [2019-12-07 17:13:27,342 INFO L226 Difference]: Without dead ends: 68226 [2019-12-07 17:13:27,342 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:13:27,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68226 states. [2019-12-07 17:13:28,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68226 to 50958. [2019-12-07 17:13:28,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50958 states. [2019-12-07 17:13:28,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50958 states to 50958 states and 212388 transitions. [2019-12-07 17:13:28,666 INFO L78 Accepts]: Start accepts. Automaton has 50958 states and 212388 transitions. Word has length 25 [2019-12-07 17:13:28,667 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:13:28,667 INFO L462 AbstractCegarLoop]: Abstraction has 50958 states and 212388 transitions. [2019-12-07 17:13:28,667 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:13:28,667 INFO L276 IsEmpty]: Start isEmpty. Operand 50958 states and 212388 transitions. [2019-12-07 17:13:28,697 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-12-07 17:13:28,698 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:13:28,698 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:13:28,698 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:13:28,698 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:13:28,698 INFO L82 PathProgramCache]: Analyzing trace with hash 1902768364, now seen corresponding path program 1 times [2019-12-07 17:13:28,698 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:13:28,699 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [937585377] [2019-12-07 17:13:28,699 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:13:28,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:13:28,731 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:13:28,731 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [937585377] [2019-12-07 17:13:28,731 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:13:28,732 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:13:28,732 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [931544883] [2019-12-07 17:13:28,732 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:13:28,732 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:13:28,732 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:13:28,733 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:13:28,733 INFO L87 Difference]: Start difference. First operand 50958 states and 212388 transitions. Second operand 3 states. [2019-12-07 17:13:28,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:13:28,876 INFO L93 Difference]: Finished difference Result 40092 states and 154478 transitions. [2019-12-07 17:13:28,877 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:13:28,877 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 29 [2019-12-07 17:13:28,877 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:13:28,960 INFO L225 Difference]: With dead ends: 40092 [2019-12-07 17:13:28,960 INFO L226 Difference]: Without dead ends: 40092 [2019-12-07 17:13:28,960 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:13:29,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40092 states. [2019-12-07 17:13:29,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40092 to 40092. [2019-12-07 17:13:29,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40092 states. [2019-12-07 17:13:29,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40092 states to 40092 states and 154478 transitions. [2019-12-07 17:13:29,845 INFO L78 Accepts]: Start accepts. Automaton has 40092 states and 154478 transitions. Word has length 29 [2019-12-07 17:13:29,845 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:13:29,845 INFO L462 AbstractCegarLoop]: Abstraction has 40092 states and 154478 transitions. [2019-12-07 17:13:29,845 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:13:29,845 INFO L276 IsEmpty]: Start isEmpty. Operand 40092 states and 154478 transitions. [2019-12-07 17:13:29,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2019-12-07 17:13:29,867 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:13:29,867 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:13:29,867 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:13:29,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:13:29,868 INFO L82 PathProgramCache]: Analyzing trace with hash 847829435, now seen corresponding path program 1 times [2019-12-07 17:13:29,868 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:13:29,868 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1779545152] [2019-12-07 17:13:29,868 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:13:29,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:13:29,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:13:29,908 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1779545152] [2019-12-07 17:13:29,909 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:13:29,909 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:13:29,909 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1006087557] [2019-12-07 17:13:29,909 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:13:29,909 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:13:29,910 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:13:29,910 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:13:29,910 INFO L87 Difference]: Start difference. First operand 40092 states and 154478 transitions. Second operand 4 states. [2019-12-07 17:13:29,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:13:29,973 INFO L93 Difference]: Finished difference Result 16844 states and 53822 transitions. [2019-12-07 17:13:29,973 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 17:13:29,973 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 30 [2019-12-07 17:13:29,973 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:13:29,996 INFO L225 Difference]: With dead ends: 16844 [2019-12-07 17:13:29,997 INFO L226 Difference]: Without dead ends: 16844 [2019-12-07 17:13:29,997 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:13:30,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16844 states. [2019-12-07 17:13:30,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16844 to 16844. [2019-12-07 17:13:30,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16844 states. [2019-12-07 17:13:30,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16844 states to 16844 states and 53822 transitions. [2019-12-07 17:13:30,247 INFO L78 Accepts]: Start accepts. Automaton has 16844 states and 53822 transitions. Word has length 30 [2019-12-07 17:13:30,248 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:13:30,248 INFO L462 AbstractCegarLoop]: Abstraction has 16844 states and 53822 transitions. [2019-12-07 17:13:30,248 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:13:30,248 INFO L276 IsEmpty]: Start isEmpty. Operand 16844 states and 53822 transitions. [2019-12-07 17:13:30,256 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 17:13:30,256 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:13:30,256 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:13:30,256 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:13:30,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:13:30,256 INFO L82 PathProgramCache]: Analyzing trace with hash 613602003, now seen corresponding path program 1 times [2019-12-07 17:13:30,257 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:13:30,257 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [980900836] [2019-12-07 17:13:30,257 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:13:30,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:13:30,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:13:30,298 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [980900836] [2019-12-07 17:13:30,298 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:13:30,298 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:13:30,299 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [814178794] [2019-12-07 17:13:30,299 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:13:30,299 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:13:30,299 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:13:30,299 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:13:30,299 INFO L87 Difference]: Start difference. First operand 16844 states and 53822 transitions. Second operand 5 states. [2019-12-07 17:13:30,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:13:30,322 INFO L93 Difference]: Finished difference Result 2883 states and 7333 transitions. [2019-12-07 17:13:30,323 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:13:30,323 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 31 [2019-12-07 17:13:30,323 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:13:30,326 INFO L225 Difference]: With dead ends: 2883 [2019-12-07 17:13:30,326 INFO L226 Difference]: Without dead ends: 2883 [2019-12-07 17:13:30,326 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:13:30,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2883 states. [2019-12-07 17:13:30,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2883 to 2883. [2019-12-07 17:13:30,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2883 states. [2019-12-07 17:13:30,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2883 states to 2883 states and 7333 transitions. [2019-12-07 17:13:30,354 INFO L78 Accepts]: Start accepts. Automaton has 2883 states and 7333 transitions. Word has length 31 [2019-12-07 17:13:30,354 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:13:30,354 INFO L462 AbstractCegarLoop]: Abstraction has 2883 states and 7333 transitions. [2019-12-07 17:13:30,354 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:13:30,354 INFO L276 IsEmpty]: Start isEmpty. Operand 2883 states and 7333 transitions. [2019-12-07 17:13:30,357 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2019-12-07 17:13:30,357 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:13:30,357 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:13:30,357 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:13:30,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:13:30,357 INFO L82 PathProgramCache]: Analyzing trace with hash 2131566482, now seen corresponding path program 1 times [2019-12-07 17:13:30,357 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:13:30,358 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [12637045] [2019-12-07 17:13:30,358 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:13:30,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:13:30,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:13:30,405 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [12637045] [2019-12-07 17:13:30,405 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:13:30,405 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:13:30,405 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [768803377] [2019-12-07 17:13:30,405 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:13:30,406 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:13:30,406 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:13:30,406 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:13:30,406 INFO L87 Difference]: Start difference. First operand 2883 states and 7333 transitions. Second operand 6 states. [2019-12-07 17:13:30,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:13:30,434 INFO L93 Difference]: Finished difference Result 1241 states and 3509 transitions. [2019-12-07 17:13:30,434 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:13:30,434 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 43 [2019-12-07 17:13:30,435 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:13:30,436 INFO L225 Difference]: With dead ends: 1241 [2019-12-07 17:13:30,436 INFO L226 Difference]: Without dead ends: 1241 [2019-12-07 17:13:30,437 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:13:30,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1241 states. [2019-12-07 17:13:30,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1241 to 1129. [2019-12-07 17:13:30,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1129 states. [2019-12-07 17:13:30,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1129 states to 1129 states and 3189 transitions. [2019-12-07 17:13:30,454 INFO L78 Accepts]: Start accepts. Automaton has 1129 states and 3189 transitions. Word has length 43 [2019-12-07 17:13:30,454 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:13:30,454 INFO L462 AbstractCegarLoop]: Abstraction has 1129 states and 3189 transitions. [2019-12-07 17:13:30,454 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:13:30,454 INFO L276 IsEmpty]: Start isEmpty. Operand 1129 states and 3189 transitions. [2019-12-07 17:13:30,457 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 17:13:30,457 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:13:30,457 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:13:30,457 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:13:30,457 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:13:30,458 INFO L82 PathProgramCache]: Analyzing trace with hash -275883304, now seen corresponding path program 1 times [2019-12-07 17:13:30,458 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:13:30,458 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1597066346] [2019-12-07 17:13:30,458 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:13:30,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:13:30,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:13:30,507 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1597066346] [2019-12-07 17:13:30,507 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:13:30,507 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:13:30,508 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [92369610] [2019-12-07 17:13:30,508 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:13:30,508 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:13:30,508 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:13:30,508 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:13:30,509 INFO L87 Difference]: Start difference. First operand 1129 states and 3189 transitions. Second operand 3 states. [2019-12-07 17:13:30,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:13:30,547 INFO L93 Difference]: Finished difference Result 1141 states and 3206 transitions. [2019-12-07 17:13:30,548 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:13:30,548 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 58 [2019-12-07 17:13:30,548 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:13:30,550 INFO L225 Difference]: With dead ends: 1141 [2019-12-07 17:13:30,550 INFO L226 Difference]: Without dead ends: 1141 [2019-12-07 17:13:30,550 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:13:30,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1141 states. [2019-12-07 17:13:30,564 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1141 to 1135. [2019-12-07 17:13:30,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1135 states. [2019-12-07 17:13:30,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1135 states to 1135 states and 3199 transitions. [2019-12-07 17:13:30,567 INFO L78 Accepts]: Start accepts. Automaton has 1135 states and 3199 transitions. Word has length 58 [2019-12-07 17:13:30,567 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:13:30,567 INFO L462 AbstractCegarLoop]: Abstraction has 1135 states and 3199 transitions. [2019-12-07 17:13:30,567 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:13:30,567 INFO L276 IsEmpty]: Start isEmpty. Operand 1135 states and 3199 transitions. [2019-12-07 17:13:30,569 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 17:13:30,569 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:13:30,570 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:13:30,570 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:13:30,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:13:30,570 INFO L82 PathProgramCache]: Analyzing trace with hash -791070951, now seen corresponding path program 1 times [2019-12-07 17:13:30,570 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:13:30,570 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1283239816] [2019-12-07 17:13:30,570 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:13:30,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:13:30,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:13:30,638 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1283239816] [2019-12-07 17:13:30,638 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:13:30,638 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:13:30,638 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [998241248] [2019-12-07 17:13:30,639 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:13:30,639 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:13:30,639 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:13:30,639 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:13:30,639 INFO L87 Difference]: Start difference. First operand 1135 states and 3199 transitions. Second operand 5 states. [2019-12-07 17:13:30,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:13:30,800 INFO L93 Difference]: Finished difference Result 1644 states and 4637 transitions. [2019-12-07 17:13:30,800 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 17:13:30,800 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 58 [2019-12-07 17:13:30,800 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:13:30,802 INFO L225 Difference]: With dead ends: 1644 [2019-12-07 17:13:30,802 INFO L226 Difference]: Without dead ends: 1644 [2019-12-07 17:13:30,802 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:13:30,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1644 states. [2019-12-07 17:13:30,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1644 to 1448. [2019-12-07 17:13:30,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1448 states. [2019-12-07 17:13:30,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1448 states to 1448 states and 4085 transitions. [2019-12-07 17:13:30,816 INFO L78 Accepts]: Start accepts. Automaton has 1448 states and 4085 transitions. Word has length 58 [2019-12-07 17:13:30,816 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:13:30,816 INFO L462 AbstractCegarLoop]: Abstraction has 1448 states and 4085 transitions. [2019-12-07 17:13:30,816 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:13:30,816 INFO L276 IsEmpty]: Start isEmpty. Operand 1448 states and 4085 transitions. [2019-12-07 17:13:30,818 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 17:13:30,818 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:13:30,818 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:13:30,818 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:13:30,818 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:13:30,819 INFO L82 PathProgramCache]: Analyzing trace with hash 867176459, now seen corresponding path program 2 times [2019-12-07 17:13:30,819 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:13:30,819 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1570375937] [2019-12-07 17:13:30,819 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:13:30,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:13:30,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:13:30,881 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1570375937] [2019-12-07 17:13:30,881 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:13:30,881 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:13:30,881 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1018798225] [2019-12-07 17:13:30,881 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:13:30,881 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:13:30,881 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:13:30,882 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:13:30,882 INFO L87 Difference]: Start difference. First operand 1448 states and 4085 transitions. Second operand 6 states. [2019-12-07 17:13:31,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:13:31,060 INFO L93 Difference]: Finished difference Result 1722 states and 4730 transitions. [2019-12-07 17:13:31,060 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 17:13:31,060 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 58 [2019-12-07 17:13:31,060 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:13:31,062 INFO L225 Difference]: With dead ends: 1722 [2019-12-07 17:13:31,062 INFO L226 Difference]: Without dead ends: 1722 [2019-12-07 17:13:31,062 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:13:31,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1722 states. [2019-12-07 17:13:31,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1722 to 1500. [2019-12-07 17:13:31,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1500 states. [2019-12-07 17:13:31,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1500 states to 1500 states and 4161 transitions. [2019-12-07 17:13:31,076 INFO L78 Accepts]: Start accepts. Automaton has 1500 states and 4161 transitions. Word has length 58 [2019-12-07 17:13:31,076 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:13:31,076 INFO L462 AbstractCegarLoop]: Abstraction has 1500 states and 4161 transitions. [2019-12-07 17:13:31,076 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:13:31,076 INFO L276 IsEmpty]: Start isEmpty. Operand 1500 states and 4161 transitions. [2019-12-07 17:13:31,078 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 17:13:31,078 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:13:31,078 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:13:31,078 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:13:31,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:13:31,078 INFO L82 PathProgramCache]: Analyzing trace with hash -2105802411, now seen corresponding path program 3 times [2019-12-07 17:13:31,079 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:13:31,079 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55784153] [2019-12-07 17:13:31,079 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:13:31,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:13:31,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:13:31,145 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [55784153] [2019-12-07 17:13:31,145 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:13:31,145 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:13:31,145 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [530736260] [2019-12-07 17:13:31,146 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:13:31,146 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:13:31,146 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:13:31,146 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:13:31,146 INFO L87 Difference]: Start difference. First operand 1500 states and 4161 transitions. Second operand 6 states. [2019-12-07 17:13:31,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:13:31,303 INFO L93 Difference]: Finished difference Result 1982 states and 5473 transitions. [2019-12-07 17:13:31,303 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 17:13:31,303 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 58 [2019-12-07 17:13:31,303 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:13:31,305 INFO L225 Difference]: With dead ends: 1982 [2019-12-07 17:13:31,305 INFO L226 Difference]: Without dead ends: 1982 [2019-12-07 17:13:31,305 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 6 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:13:31,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1982 states. [2019-12-07 17:13:31,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1982 to 1528. [2019-12-07 17:13:31,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1528 states. [2019-12-07 17:13:31,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1528 states to 1528 states and 4241 transitions. [2019-12-07 17:13:31,321 INFO L78 Accepts]: Start accepts. Automaton has 1528 states and 4241 transitions. Word has length 58 [2019-12-07 17:13:31,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:13:31,321 INFO L462 AbstractCegarLoop]: Abstraction has 1528 states and 4241 transitions. [2019-12-07 17:13:31,322 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:13:31,322 INFO L276 IsEmpty]: Start isEmpty. Operand 1528 states and 4241 transitions. [2019-12-07 17:13:31,323 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 17:13:31,323 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:13:31,324 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:13:31,324 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:13:31,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:13:31,324 INFO L82 PathProgramCache]: Analyzing trace with hash -645544041, now seen corresponding path program 4 times [2019-12-07 17:13:31,324 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:13:31,324 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1426852893] [2019-12-07 17:13:31,324 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:13:31,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:13:31,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:13:31,358 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1426852893] [2019-12-07 17:13:31,358 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:13:31,359 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:13:31,359 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2096978524] [2019-12-07 17:13:31,359 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:13:31,359 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:13:31,359 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:13:31,359 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:13:31,359 INFO L87 Difference]: Start difference. First operand 1528 states and 4241 transitions. Second operand 3 states. [2019-12-07 17:13:31,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:13:31,371 INFO L93 Difference]: Finished difference Result 1444 states and 3973 transitions. [2019-12-07 17:13:31,371 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:13:31,371 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 58 [2019-12-07 17:13:31,371 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:13:31,373 INFO L225 Difference]: With dead ends: 1444 [2019-12-07 17:13:31,373 INFO L226 Difference]: Without dead ends: 1444 [2019-12-07 17:13:31,373 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:13:31,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1444 states. [2019-12-07 17:13:31,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1444 to 1444. [2019-12-07 17:13:31,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1444 states. [2019-12-07 17:13:31,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1444 states to 1444 states and 3973 transitions. [2019-12-07 17:13:31,393 INFO L78 Accepts]: Start accepts. Automaton has 1444 states and 3973 transitions. Word has length 58 [2019-12-07 17:13:31,393 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:13:31,393 INFO L462 AbstractCegarLoop]: Abstraction has 1444 states and 3973 transitions. [2019-12-07 17:13:31,393 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:13:31,393 INFO L276 IsEmpty]: Start isEmpty. Operand 1444 states and 3973 transitions. [2019-12-07 17:13:31,396 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 17:13:31,396 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:13:31,396 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:13:31,396 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:13:31,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:13:31,397 INFO L82 PathProgramCache]: Analyzing trace with hash -515953626, now seen corresponding path program 1 times [2019-12-07 17:13:31,397 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:13:31,397 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [925389758] [2019-12-07 17:13:31,397 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:13:31,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:13:31,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:13:31,559 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [925389758] [2019-12-07 17:13:31,560 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:13:31,560 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 17:13:31,560 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [569015013] [2019-12-07 17:13:31,560 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 17:13:31,560 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:13:31,560 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 17:13:31,560 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=107, Unknown=0, NotChecked=0, Total=132 [2019-12-07 17:13:31,560 INFO L87 Difference]: Start difference. First operand 1444 states and 3973 transitions. Second operand 12 states. [2019-12-07 17:13:32,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:13:32,390 INFO L93 Difference]: Finished difference Result 3584 states and 9183 transitions. [2019-12-07 17:13:32,390 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-12-07 17:13:32,390 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 59 [2019-12-07 17:13:32,390 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:13:32,392 INFO L225 Difference]: With dead ends: 3584 [2019-12-07 17:13:32,392 INFO L226 Difference]: Without dead ends: 2353 [2019-12-07 17:13:32,393 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 363 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=280, Invalid=1280, Unknown=0, NotChecked=0, Total=1560 [2019-12-07 17:13:32,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2353 states. [2019-12-07 17:13:32,407 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2353 to 1304. [2019-12-07 17:13:32,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1304 states. [2019-12-07 17:13:32,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1304 states to 1304 states and 3502 transitions. [2019-12-07 17:13:32,409 INFO L78 Accepts]: Start accepts. Automaton has 1304 states and 3502 transitions. Word has length 59 [2019-12-07 17:13:32,409 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:13:32,409 INFO L462 AbstractCegarLoop]: Abstraction has 1304 states and 3502 transitions. [2019-12-07 17:13:32,409 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 17:13:32,409 INFO L276 IsEmpty]: Start isEmpty. Operand 1304 states and 3502 transitions. [2019-12-07 17:13:32,410 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 17:13:32,410 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:13:32,410 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:13:32,411 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:13:32,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:13:32,411 INFO L82 PathProgramCache]: Analyzing trace with hash -1634865510, now seen corresponding path program 2 times [2019-12-07 17:13:32,411 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:13:32,411 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713848427] [2019-12-07 17:13:32,411 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:13:32,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:13:32,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:13:32,447 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1713848427] [2019-12-07 17:13:32,447 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:13:32,448 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:13:32,448 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1134511339] [2019-12-07 17:13:32,448 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:13:32,448 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:13:32,448 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:13:32,448 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:13:32,448 INFO L87 Difference]: Start difference. First operand 1304 states and 3502 transitions. Second operand 3 states. [2019-12-07 17:13:32,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:13:32,482 INFO L93 Difference]: Finished difference Result 1303 states and 3500 transitions. [2019-12-07 17:13:32,482 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:13:32,482 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 59 [2019-12-07 17:13:32,482 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:13:32,483 INFO L225 Difference]: With dead ends: 1303 [2019-12-07 17:13:32,483 INFO L226 Difference]: Without dead ends: 1303 [2019-12-07 17:13:32,484 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:13:32,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1303 states. [2019-12-07 17:13:32,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1303 to 1022. [2019-12-07 17:13:32,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1022 states. [2019-12-07 17:13:32,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1022 states to 1022 states and 2726 transitions. [2019-12-07 17:13:32,494 INFO L78 Accepts]: Start accepts. Automaton has 1022 states and 2726 transitions. Word has length 59 [2019-12-07 17:13:32,495 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:13:32,495 INFO L462 AbstractCegarLoop]: Abstraction has 1022 states and 2726 transitions. [2019-12-07 17:13:32,495 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:13:32,495 INFO L276 IsEmpty]: Start isEmpty. Operand 1022 states and 2726 transitions. [2019-12-07 17:13:32,496 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 17:13:32,496 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:13:32,496 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:13:32,496 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:13:32,496 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:13:32,496 INFO L82 PathProgramCache]: Analyzing trace with hash -92263015, now seen corresponding path program 1 times [2019-12-07 17:13:32,496 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:13:32,497 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [361872675] [2019-12-07 17:13:32,497 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:13:32,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:13:32,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:13:32,568 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [361872675] [2019-12-07 17:13:32,569 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:13:32,569 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:13:32,569 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [122269582] [2019-12-07 17:13:32,569 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:13:32,569 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:13:32,569 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:13:32,569 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:13:32,569 INFO L87 Difference]: Start difference. First operand 1022 states and 2726 transitions. Second operand 6 states. [2019-12-07 17:13:32,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:13:32,623 INFO L93 Difference]: Finished difference Result 1761 states and 4311 transitions. [2019-12-07 17:13:32,624 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:13:32,624 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 60 [2019-12-07 17:13:32,624 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:13:32,625 INFO L225 Difference]: With dead ends: 1761 [2019-12-07 17:13:32,625 INFO L226 Difference]: Without dead ends: 965 [2019-12-07 17:13:32,626 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 17:13:32,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 965 states. [2019-12-07 17:13:32,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 965 to 750. [2019-12-07 17:13:32,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 750 states. [2019-12-07 17:13:32,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 750 states to 750 states and 1748 transitions. [2019-12-07 17:13:32,637 INFO L78 Accepts]: Start accepts. Automaton has 750 states and 1748 transitions. Word has length 60 [2019-12-07 17:13:32,637 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:13:32,637 INFO L462 AbstractCegarLoop]: Abstraction has 750 states and 1748 transitions. [2019-12-07 17:13:32,637 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:13:32,637 INFO L276 IsEmpty]: Start isEmpty. Operand 750 states and 1748 transitions. [2019-12-07 17:13:32,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 17:13:32,638 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:13:32,638 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:13:32,639 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:13:32,639 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:13:32,639 INFO L82 PathProgramCache]: Analyzing trace with hash -1752143333, now seen corresponding path program 2 times [2019-12-07 17:13:32,639 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:13:32,639 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1158194980] [2019-12-07 17:13:32,639 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:13:32,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:13:32,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:13:32,716 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1158194980] [2019-12-07 17:13:32,716 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:13:32,716 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:13:32,716 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1475779726] [2019-12-07 17:13:32,717 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:13:32,717 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:13:32,717 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:13:32,717 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:13:32,717 INFO L87 Difference]: Start difference. First operand 750 states and 1748 transitions. Second operand 5 states. [2019-12-07 17:13:32,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:13:32,750 INFO L93 Difference]: Finished difference Result 922 states and 2048 transitions. [2019-12-07 17:13:32,750 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:13:32,750 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 60 [2019-12-07 17:13:32,751 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:13:32,751 INFO L225 Difference]: With dead ends: 922 [2019-12-07 17:13:32,751 INFO L226 Difference]: Without dead ends: 213 [2019-12-07 17:13:32,751 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:13:32,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 213 states. [2019-12-07 17:13:32,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 213 to 213. [2019-12-07 17:13:32,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 213 states. [2019-12-07 17:13:32,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 213 states to 213 states and 368 transitions. [2019-12-07 17:13:32,754 INFO L78 Accepts]: Start accepts. Automaton has 213 states and 368 transitions. Word has length 60 [2019-12-07 17:13:32,754 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:13:32,754 INFO L462 AbstractCegarLoop]: Abstraction has 213 states and 368 transitions. [2019-12-07 17:13:32,754 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:13:32,754 INFO L276 IsEmpty]: Start isEmpty. Operand 213 states and 368 transitions. [2019-12-07 17:13:32,755 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 17:13:32,755 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:13:32,755 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:13:32,755 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:13:32,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:13:32,755 INFO L82 PathProgramCache]: Analyzing trace with hash -524819563, now seen corresponding path program 3 times [2019-12-07 17:13:32,756 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:13:32,756 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312089671] [2019-12-07 17:13:32,756 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:13:32,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:13:32,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:13:32,848 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:13:32,848 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 17:13:32,851 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] ULTIMATE.startENTRY-->L821: Formula: (let ((.cse0 (store |v_#valid_75| 0 0))) (and (= v_~weak$$choice2~0_146 0) (= v_~z$w_buff0_used~0_885 0) (= v_~z$mem_tmp~0_22 0) (= v_~z$r_buff1_thd0~0_298 0) (= 0 v_~z$r_buff1_thd2~0_83) (= 0 v_~z$r_buff1_thd4~0_140) (= 0 v_~z$r_buff1_thd1~0_83) (= 0 v_~z$flush_delayed~0_36) (= v_~z$r_buff0_thd3~0_92 0) (= |v_#valid_73| (store .cse0 |v_ULTIMATE.start_main_~#t1525~0.base_24| 1)) (= v_~z$read_delayed_var~0.offset_7 0) (= (select .cse0 |v_ULTIMATE.start_main_~#t1525~0.base_24|) 0) (= 0 |v_ULTIMATE.start_main_~#t1525~0.offset_18|) (< 0 |v_#StackHeapBarrier_18|) (= v_~__unbuffered_p3_EAX~0_100 0) (= v_~z$w_buff0~0_503 0) (= v_~z$w_buff1_used~0_515 0) (= v_~a~0_48 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t1525~0.base_24|) (= v_~x~0_57 0) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$read_delayed~0_7 0) (= v_~z~0_155 0) (= v_~main$tmp_guard1~0_32 0) (= 0 v_~weak$$choice0~0_16) (= v_~__unbuffered_cnt~0_141 0) (= 0 v_~z$r_buff1_thd3~0_146) (= v_~z$w_buff1~0_306 0) (= v_~z$r_buff0_thd0~0_394 0) (= |v_#NULL.offset_5| 0) (= v_~z$r_buff0_thd2~0_32 0) (= (store |v_#memory_int_26| |v_ULTIMATE.start_main_~#t1525~0.base_24| (store (select |v_#memory_int_26| |v_ULTIMATE.start_main_~#t1525~0.base_24|) |v_ULTIMATE.start_main_~#t1525~0.offset_18| 0)) |v_#memory_int_25|) (= v_~main$tmp_guard0~0_22 0) (= 0 v_~z$r_buff0_thd4~0_161) (= v_~y~0_76 0) (= v_~z$r_buff0_thd1~0_32 0) (= |v_#length_29| (store |v_#length_30| |v_ULTIMATE.start_main_~#t1525~0.base_24| 4)) (= 0 |v_#NULL.base_5|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_75|, #memory_int=|v_#memory_int_26|, #length=|v_#length_30|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_59|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_83, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_41|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_32|, ULTIMATE.start_main_~#t1527~0.offset=|v_ULTIMATE.start_main_~#t1527~0.offset_16|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_35|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_30|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_45|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_60|, ~a~0=v_~a~0_48, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_394, ~z$r_buff0_thd4~0=v_~z$r_buff0_thd4~0_161, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_100, #length=|v_#length_29|, ~z$mem_tmp~0=v_~z$mem_tmp~0_22, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_48|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_114|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_515, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_191|, ~z$flush_delayed~0=v_~z$flush_delayed~0_36, ULTIMATE.start_main_~#t1525~0.offset=|v_ULTIMATE.start_main_~#t1525~0.offset_18|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_35|, ULTIMATE.start_main_~#t1526~0.base=|v_ULTIMATE.start_main_~#t1526~0.base_22|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_44|, ULTIMATE.start_main_~#t1525~0.base=|v_ULTIMATE.start_main_~#t1525~0.base_24|, ~weak$$choice0~0=v_~weak$$choice0~0_16, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_38|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_83, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_10|, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_92, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_141, ~x~0=v_~x~0_57, ULTIMATE.start_main_~#t1526~0.offset=|v_ULTIMATE.start_main_~#t1526~0.offset_17|, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_140, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_40|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_57|, ~z$w_buff1~0=v_~z$w_buff1~0_306, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_43|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_31|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_29|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_51|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_44|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_298, ULTIMATE.start_main_#t~nondet26=|v_ULTIMATE.start_main_#t~nondet26_25|, ULTIMATE.start_main_~#t1527~0.base=|v_ULTIMATE.start_main_~#t1527~0.base_20|, ULTIMATE.start_main_~#t1528~0.offset=|v_ULTIMATE.start_main_~#t1528~0.offset_17|, ~y~0=v_~y~0_76, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_32, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_885, ~z$w_buff0~0=v_~z$w_buff0~0_503, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_39|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_25|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_146, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_122|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_44|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_22, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_36|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_35|, ULTIMATE.start_main_~#t1528~0.base=|v_ULTIMATE.start_main_~#t1528~0.base_21|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_31|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_25|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_9|, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_23|, ~z~0=v_~z~0_155, ~weak$$choice2~0=v_~weak$$choice2~0_146, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_32} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_~#t1527~0.offset, #NULL.offset, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~a~0, ~z$r_buff0_thd0~0, ~z$r_buff0_thd4~0, ~__unbuffered_p3_EAX~0, #length, ~z$mem_tmp~0, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_~#t1525~0.offset, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_~#t1526~0.base, ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_~#t1525~0.base, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ULTIMATE.start_main_#t~nondet15, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_~#t1526~0.offset, ~z$r_buff1_thd4~0, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite30, ~z$r_buff1_thd0~0, ULTIMATE.start_main_#t~nondet26, ULTIMATE.start_main_~#t1527~0.base, ULTIMATE.start_main_~#t1528~0.offset, ~y~0, ~z$r_buff0_thd2~0, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_~#t1528~0.base, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_#t~nondet18, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 17:13:32,852 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [732] [732] L821-1-->L823: Formula: (and (= 0 |v_ULTIMATE.start_main_~#t1526~0.offset_9|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1526~0.base_10| 4)) (not (= 0 |v_ULTIMATE.start_main_~#t1526~0.base_10|)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1526~0.base_10| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1526~0.base_10|) |v_ULTIMATE.start_main_~#t1526~0.offset_9| 1)) |v_#memory_int_13|) (= |v_#valid_35| (store |v_#valid_36| |v_ULTIMATE.start_main_~#t1526~0.base_10| 1)) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1526~0.base_10|) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t1526~0.base_10|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1526~0.base=|v_ULTIMATE.start_main_~#t1526~0.base_10|, ULTIMATE.start_main_~#t1526~0.offset=|v_ULTIMATE.start_main_~#t1526~0.offset_9|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t1526~0.base, ULTIMATE.start_main_~#t1526~0.offset] because there is no mapped edge [2019-12-07 17:13:32,852 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [753] [753] L823-1-->L825: Formula: (and (= |v_#valid_45| (store |v_#valid_46| |v_ULTIMATE.start_main_~#t1527~0.base_12| 1)) (= (select |v_#valid_46| |v_ULTIMATE.start_main_~#t1527~0.base_12|) 0) (not (= |v_ULTIMATE.start_main_~#t1527~0.base_12| 0)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1527~0.base_12|) (= 0 |v_ULTIMATE.start_main_~#t1527~0.offset_10|) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1527~0.base_12| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1527~0.base_12|) |v_ULTIMATE.start_main_~#t1527~0.offset_10| 2)) |v_#memory_int_17|) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t1527~0.base_12| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_~#t1527~0.offset=|v_ULTIMATE.start_main_~#t1527~0.offset_10|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, ULTIMATE.start_main_~#t1527~0.base=|v_ULTIMATE.start_main_~#t1527~0.base_12|, #length=|v_#length_21|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_~#t1527~0.offset, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t1527~0.base, #length] because there is no mapped edge [2019-12-07 17:13:32,852 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [743] [743] L825-1-->L827: Formula: (and (= (store |v_#length_20| |v_ULTIMATE.start_main_~#t1528~0.base_11| 4) |v_#length_19|) (= |v_#valid_39| (store |v_#valid_40| |v_ULTIMATE.start_main_~#t1528~0.base_11| 1)) (not (= 0 |v_ULTIMATE.start_main_~#t1528~0.base_11|)) (= 0 |v_ULTIMATE.start_main_~#t1528~0.offset_10|) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1528~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1528~0.base_11|) |v_ULTIMATE.start_main_~#t1528~0.offset_10| 3)) |v_#memory_int_15|) (= 0 (select |v_#valid_40| |v_ULTIMATE.start_main_~#t1528~0.base_11|)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t1528~0.base_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{ULTIMATE.start_main_~#t1528~0.base=|v_ULTIMATE.start_main_~#t1528~0.base_11|, #StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_15|, #length=|v_#length_19|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|, ULTIMATE.start_main_~#t1528~0.offset=|v_ULTIMATE.start_main_~#t1528~0.offset_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1528~0.base, #valid, #memory_int, #length, ULTIMATE.start_main_#t~nondet17, ULTIMATE.start_main_~#t1528~0.offset] because there is no mapped edge [2019-12-07 17:13:32,853 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] P3ENTRY-->L4-3: Formula: (and (not (= v_P3Thread1of1ForFork2___VERIFIER_assert_~expression_11 0)) (= v_P3Thread1of1ForFork2_~arg.base_9 |v_P3Thread1of1ForFork2_#in~arg.base_11|) (= v_P3Thread1of1ForFork2___VERIFIER_assert_~expression_11 |v_P3Thread1of1ForFork2___VERIFIER_assert_#in~expression_9|) (= (ite (not (and (not (= (mod v_~z$w_buff0_used~0_218 256) 0)) (not (= (mod v_~z$w_buff1_used~0_99 256) 0)))) 1 0) |v_P3Thread1of1ForFork2___VERIFIER_assert_#in~expression_9|) (= |v_P3Thread1of1ForFork2_#in~arg.offset_11| v_P3Thread1of1ForFork2_~arg.offset_9) (= v_~z$w_buff0_used~0_218 1) (= v_~z$w_buff0~0_48 v_~z$w_buff1~0_32) (= 2 v_~z$w_buff0~0_47) (= v_~z$w_buff0_used~0_219 v_~z$w_buff1_used~0_99)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_219, ~z$w_buff0~0=v_~z$w_buff0~0_48, P3Thread1of1ForFork2_#in~arg.offset=|v_P3Thread1of1ForFork2_#in~arg.offset_11|, P3Thread1of1ForFork2_#in~arg.base=|v_P3Thread1of1ForFork2_#in~arg.base_11|} OutVars{P3Thread1of1ForFork2___VERIFIER_assert_~expression=v_P3Thread1of1ForFork2___VERIFIER_assert_~expression_11, P3Thread1of1ForFork2_~arg.offset=v_P3Thread1of1ForFork2_~arg.offset_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_218, ~z$w_buff0~0=v_~z$w_buff0~0_47, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_99, P3Thread1of1ForFork2_#in~arg.offset=|v_P3Thread1of1ForFork2_#in~arg.offset_11|, ~z$w_buff1~0=v_~z$w_buff1~0_32, P3Thread1of1ForFork2___VERIFIER_assert_#in~expression=|v_P3Thread1of1ForFork2___VERIFIER_assert_#in~expression_9|, P3Thread1of1ForFork2_~arg.base=v_P3Thread1of1ForFork2_~arg.base_9, P3Thread1of1ForFork2_#in~arg.base=|v_P3Thread1of1ForFork2_#in~arg.base_11|} AuxVars[] AssignedVars[P3Thread1of1ForFork2___VERIFIER_assert_~expression, P3Thread1of1ForFork2_~arg.offset, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$w_buff1_used~0, ~z$w_buff1~0, P3Thread1of1ForFork2___VERIFIER_assert_#in~expression, P3Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-12-07 17:13:32,853 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_44 1) (= v_~__unbuffered_cnt~0_102 (+ v_~__unbuffered_cnt~0_103 1)) (= v_P0Thread1of1ForFork3_~arg.base_17 |v_P0Thread1of1ForFork3_#in~arg.base_19|) (= v_~a~0_40 1) (= |v_P0Thread1of1ForFork3_#res.offset_9| 0) (= |v_P0Thread1of1ForFork3_#in~arg.offset_19| v_P0Thread1of1ForFork3_~arg.offset_17) (= 0 |v_P0Thread1of1ForFork3_#res.base_9|)) InVars {P0Thread1of1ForFork3_#in~arg.offset=|v_P0Thread1of1ForFork3_#in~arg.offset_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_103, P0Thread1of1ForFork3_#in~arg.base=|v_P0Thread1of1ForFork3_#in~arg.base_19|} OutVars{~a~0=v_~a~0_40, P0Thread1of1ForFork3_#in~arg.offset=|v_P0Thread1of1ForFork3_#in~arg.offset_19|, P0Thread1of1ForFork3_~arg.base=v_P0Thread1of1ForFork3_~arg.base_17, P0Thread1of1ForFork3_#res.base=|v_P0Thread1of1ForFork3_#res.base_9|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_102, P0Thread1of1ForFork3_#res.offset=|v_P0Thread1of1ForFork3_#res.offset_9|, P0Thread1of1ForFork3_~arg.offset=v_P0Thread1of1ForFork3_~arg.offset_17, P0Thread1of1ForFork3_#in~arg.base=|v_P0Thread1of1ForFork3_#in~arg.base_19|, ~x~0=v_~x~0_44} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork3_~arg.base, P0Thread1of1ForFork3_#res.base, ~__unbuffered_cnt~0, P0Thread1of1ForFork3_#res.offset, P0Thread1of1ForFork3_~arg.offset, ~x~0] because there is no mapped edge [2019-12-07 17:13:32,853 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [746] [746] P1ENTRY-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork0_#res.offset_3|) (= v_~x~0_39 2) (= v_~__unbuffered_cnt~0_78 (+ v_~__unbuffered_cnt~0_79 1)) (= v_~y~0_50 1) (= 0 |v_P1Thread1of1ForFork0_#res.base_3|) (= |v_P1Thread1of1ForFork0_#in~arg.base_10| v_P1Thread1of1ForFork0_~arg.base_8) (= |v_P1Thread1of1ForFork0_#in~arg.offset_10| v_P1Thread1of1ForFork0_~arg.offset_8)) InVars {P1Thread1of1ForFork0_#in~arg.base=|v_P1Thread1of1ForFork0_#in~arg.base_10|, P1Thread1of1ForFork0_#in~arg.offset=|v_P1Thread1of1ForFork0_#in~arg.offset_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_79} OutVars{P1Thread1of1ForFork0_~arg.offset=v_P1Thread1of1ForFork0_~arg.offset_8, P1Thread1of1ForFork0_~arg.base=v_P1Thread1of1ForFork0_~arg.base_8, P1Thread1of1ForFork0_#in~arg.base=|v_P1Thread1of1ForFork0_#in~arg.base_10|, P1Thread1of1ForFork0_#in~arg.offset=|v_P1Thread1of1ForFork0_#in~arg.offset_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_78, P1Thread1of1ForFork0_#res.offset=|v_P1Thread1of1ForFork0_#res.offset_3|, ~y~0=v_~y~0_50, P1Thread1of1ForFork0_#res.base=|v_P1Thread1of1ForFork0_#res.base_3|, ~x~0=v_~x~0_39} AuxVars[] AssignedVars[P1Thread1of1ForFork0_~arg.offset, P1Thread1of1ForFork0_~arg.base, ~__unbuffered_cnt~0, P1Thread1of1ForFork0_#res.offset, ~y~0, P1Thread1of1ForFork0_#res.base, ~x~0] because there is no mapped edge [2019-12-07 17:13:32,854 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L768-2-->L768-5: Formula: (let ((.cse0 (= |P2Thread1of1ForFork1_#t~ite4_Out-1958956457| |P2Thread1of1ForFork1_#t~ite3_Out-1958956457|)) (.cse2 (= (mod ~z$r_buff1_thd3~0_In-1958956457 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1958956457 256)))) (or (and .cse0 (not .cse1) (= ~z$w_buff1~0_In-1958956457 |P2Thread1of1ForFork1_#t~ite3_Out-1958956457|) (not .cse2)) (and .cse0 (= ~z~0_In-1958956457 |P2Thread1of1ForFork1_#t~ite3_Out-1958956457|) (or .cse2 .cse1)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1958956457, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1958956457, ~z$w_buff1~0=~z$w_buff1~0_In-1958956457, ~z~0=~z~0_In-1958956457} OutVars{P2Thread1of1ForFork1_#t~ite4=|P2Thread1of1ForFork1_#t~ite4_Out-1958956457|, P2Thread1of1ForFork1_#t~ite3=|P2Thread1of1ForFork1_#t~ite3_Out-1958956457|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1958956457, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1958956457, ~z$w_buff1~0=~z$w_buff1~0_In-1958956457, ~z~0=~z~0_In-1958956457} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite4, P2Thread1of1ForFork1_#t~ite3] because there is no mapped edge [2019-12-07 17:13:32,854 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L769-->L769-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-525449033 256))) (.cse1 (= (mod ~z$r_buff0_thd3~0_In-525449033 256) 0))) (or (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In-525449033 |P2Thread1of1ForFork1_#t~ite5_Out-525449033|)) (and (= 0 |P2Thread1of1ForFork1_#t~ite5_Out-525449033|) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-525449033, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-525449033} OutVars{P2Thread1of1ForFork1_#t~ite5=|P2Thread1of1ForFork1_#t~ite5_Out-525449033|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-525449033, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-525449033} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite5] because there is no mapped edge [2019-12-07 17:13:32,854 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] L770-->L770-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In47298888 256))) (.cse1 (= (mod ~z$r_buff0_thd3~0_In47298888 256) 0)) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In47298888 256))) (.cse3 (= (mod ~z$r_buff1_thd3~0_In47298888 256) 0))) (or (and (= ~z$w_buff1_used~0_In47298888 |P2Thread1of1ForFork1_#t~ite6_Out47298888|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P2Thread1of1ForFork1_#t~ite6_Out47298888| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In47298888, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In47298888, ~z$w_buff1_used~0=~z$w_buff1_used~0_In47298888, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In47298888} OutVars{P2Thread1of1ForFork1_#t~ite6=|P2Thread1of1ForFork1_#t~ite6_Out47298888|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In47298888, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In47298888, ~z$w_buff1_used~0=~z$w_buff1_used~0_In47298888, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In47298888} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite6] because there is no mapped edge [2019-12-07 17:13:32,855 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [710] [710] L771-->L771-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In1728282874 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In1728282874 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork1_#t~ite7_Out1728282874| ~z$r_buff0_thd3~0_In1728282874)) (and (not .cse0) (= |P2Thread1of1ForFork1_#t~ite7_Out1728282874| 0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1728282874, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1728282874} OutVars{P2Thread1of1ForFork1_#t~ite7=|P2Thread1of1ForFork1_#t~ite7_Out1728282874|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1728282874, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1728282874} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite7] because there is no mapped edge [2019-12-07 17:13:32,855 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L772-->L772-2: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In1456030982 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd3~0_In1456030982 256) 0)) (.cse2 (= (mod ~z$r_buff0_thd3~0_In1456030982 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In1456030982 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork1_#t~ite8_Out1456030982| 0)) (and (= |P2Thread1of1ForFork1_#t~ite8_Out1456030982| ~z$r_buff1_thd3~0_In1456030982) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1456030982, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1456030982, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1456030982, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1456030982} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1456030982, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1456030982, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1456030982, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1456030982, P2Thread1of1ForFork1_#t~ite8=|P2Thread1of1ForFork1_#t~ite8_Out1456030982|} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 17:13:32,855 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [752] [752] L772-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork1_#res.offset_3|) (= v_~z$r_buff1_thd3~0_127 |v_P2Thread1of1ForFork1_#t~ite8_44|) (= v_~__unbuffered_cnt~0_100 (+ v_~__unbuffered_cnt~0_101 1)) (= 0 |v_P2Thread1of1ForFork1_#res.base_3|)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_101, P2Thread1of1ForFork1_#t~ite8=|v_P2Thread1of1ForFork1_#t~ite8_44|} OutVars{P2Thread1of1ForFork1_#res.base=|v_P2Thread1of1ForFork1_#res.base_3|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_127, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_100, P2Thread1of1ForFork1_#res.offset=|v_P2Thread1of1ForFork1_#res.offset_3|, P2Thread1of1ForFork1_#t~ite8=|v_P2Thread1of1ForFork1_#t~ite8_43|} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#res.base, ~z$r_buff1_thd3~0, ~__unbuffered_cnt~0, P2Thread1of1ForFork1_#res.offset, P2Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 17:13:32,856 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [727] [727] L799-->L799-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd4~0_In-850061479 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-850061479 256) 0))) (or (and (or .cse0 .cse1) (= |P3Thread1of1ForFork2_#t~ite11_Out-850061479| ~z$w_buff0_used~0_In-850061479)) (and (not .cse0) (not .cse1) (= 0 |P3Thread1of1ForFork2_#t~ite11_Out-850061479|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-850061479, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-850061479} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-850061479, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-850061479, P3Thread1of1ForFork2_#t~ite11=|P3Thread1of1ForFork2_#t~ite11_Out-850061479|} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-12-07 17:13:32,856 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L800-->L800-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd4~0_In811056250 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In811056250 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd4~0_In811056250 256))) (.cse3 (= (mod ~z$w_buff0_used~0_In811056250 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P3Thread1of1ForFork2_#t~ite12_Out811056250| 0)) (and (= |P3Thread1of1ForFork2_#t~ite12_Out811056250| ~z$w_buff1_used~0_In811056250) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In811056250, ~z$w_buff0_used~0=~z$w_buff0_used~0_In811056250, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In811056250, ~z$w_buff1_used~0=~z$w_buff1_used~0_In811056250} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In811056250, ~z$w_buff0_used~0=~z$w_buff0_used~0_In811056250, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In811056250, ~z$w_buff1_used~0=~z$w_buff1_used~0_In811056250, P3Thread1of1ForFork2_#t~ite12=|P3Thread1of1ForFork2_#t~ite12_Out811056250|} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite12] because there is no mapped edge [2019-12-07 17:13:32,856 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L801-->L802: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-48204289 256) 0)) (.cse0 (= ~z$r_buff0_thd4~0_Out-48204289 ~z$r_buff0_thd4~0_In-48204289)) (.cse2 (= 0 (mod ~z$r_buff0_thd4~0_In-48204289 256)))) (or (and .cse0 .cse1) (and (not .cse2) (= 0 ~z$r_buff0_thd4~0_Out-48204289) (not .cse1)) (and .cse0 .cse2))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-48204289, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-48204289} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-48204289, P3Thread1of1ForFork2_#t~ite13=|P3Thread1of1ForFork2_#t~ite13_Out-48204289|, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out-48204289} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite13, ~z$r_buff0_thd4~0] because there is no mapped edge [2019-12-07 17:13:32,856 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L802-->L802-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd4~0_In-695131456 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-695131456 256))) (.cse3 (= (mod ~z$w_buff1_used~0_In-695131456 256) 0)) (.cse2 (= (mod ~z$r_buff1_thd4~0_In-695131456 256) 0))) (or (and (= |P3Thread1of1ForFork2_#t~ite14_Out-695131456| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse3 .cse2) (= |P3Thread1of1ForFork2_#t~ite14_Out-695131456| ~z$r_buff1_thd4~0_In-695131456)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-695131456, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-695131456, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-695131456, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-695131456} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-695131456, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-695131456, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-695131456, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-695131456, P3Thread1of1ForFork2_#t~ite14=|P3Thread1of1ForFork2_#t~ite14_Out-695131456|} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite14] because there is no mapped edge [2019-12-07 17:13:32,856 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L802-2-->P3EXIT: Formula: (and (= |v_P3Thread1of1ForFork2_#t~ite14_54| v_~z$r_buff1_thd4~0_130) (= 0 |v_P3Thread1of1ForFork2_#res.base_3|) (= v_~__unbuffered_cnt~0_126 (+ v_~__unbuffered_cnt~0_127 1)) (= 0 |v_P3Thread1of1ForFork2_#res.offset_3|)) InVars {P3Thread1of1ForFork2_#t~ite14=|v_P3Thread1of1ForFork2_#t~ite14_54|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_127} OutVars{P3Thread1of1ForFork2_#res.base=|v_P3Thread1of1ForFork2_#res.base_3|, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_130, P3Thread1of1ForFork2_#t~ite14=|v_P3Thread1of1ForFork2_#t~ite14_53|, P3Thread1of1ForFork2_#res.offset=|v_P3Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_126} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#res.base, ~z$r_buff1_thd4~0, P3Thread1of1ForFork2_#t~ite14, P3Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 17:13:32,857 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [673] [673] L827-1-->L833: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= (ite (= 4 v_~__unbuffered_cnt~0_21) 1 0) 0) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_21} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_21, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_6|} AuxVars[] AssignedVars[~main$tmp_guard0~0, ULTIMATE.start_main_#t~nondet18] because there is no mapped edge [2019-12-07 17:13:32,857 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L833-2-->L833-4: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In-2097104797 256))) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-2097104797 256) 0))) (or (and (= ~z$w_buff1~0_In-2097104797 |ULTIMATE.start_main_#t~ite19_Out-2097104797|) (not .cse0) (not .cse1)) (and (= ~z~0_In-2097104797 |ULTIMATE.start_main_#t~ite19_Out-2097104797|) (or .cse0 .cse1)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-2097104797, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2097104797, ~z$w_buff1~0=~z$w_buff1~0_In-2097104797, ~z~0=~z~0_In-2097104797} OutVars{ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-2097104797|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-2097104797, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2097104797, ~z$w_buff1~0=~z$w_buff1~0_In-2097104797, ~z~0=~z~0_In-2097104797} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 17:13:32,857 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [658] [658] L833-4-->L834: Formula: (= v_~z~0_31 |v_ULTIMATE.start_main_#t~ite19_8|) InVars {ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_8|} OutVars{ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_7|, ~z~0=v_~z~0_31, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19, ~z~0, ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 17:13:32,857 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L834-->L834-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In1490144348 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In1490144348 256)))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite21_Out1490144348|)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite21_Out1490144348| ~z$w_buff0_used~0_In1490144348)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1490144348, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1490144348} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1490144348, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1490144348, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out1490144348|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 17:13:32,857 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [725] [725] L835-->L835-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In-2061247142 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-2061247142 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In-2061247142 256) 0)) (.cse3 (= (mod ~z$r_buff0_thd0~0_In-2061247142 256) 0))) (or (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In-2061247142 |ULTIMATE.start_main_#t~ite22_Out-2061247142|) (or .cse2 .cse3)) (and (= |ULTIMATE.start_main_#t~ite22_Out-2061247142| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-2061247142, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-2061247142, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-2061247142, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2061247142} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-2061247142, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-2061247142, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-2061247142, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2061247142, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-2061247142|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 17:13:32,858 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [718] [718] L836-->L836-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In-1608978250 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-1608978250 256) 0))) (or (and (or .cse0 .cse1) (= ~z$r_buff0_thd0~0_In-1608978250 |ULTIMATE.start_main_#t~ite23_Out-1608978250|)) (and (= 0 |ULTIMATE.start_main_#t~ite23_Out-1608978250|) (not .cse1) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1608978250, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1608978250} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1608978250, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1608978250, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-1608978250|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 17:13:32,858 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [711] [711] L837-->L837-2: Formula: (let ((.cse3 (= (mod ~z$w_buff1_used~0_In286853322 256) 0)) (.cse2 (= (mod ~z$r_buff1_thd0~0_In286853322 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In286853322 256))) (.cse0 (= (mod ~z$r_buff0_thd0~0_In286853322 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite24_Out286853322| ~z$r_buff1_thd0~0_In286853322)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0))) (= |ULTIMATE.start_main_#t~ite24_Out286853322| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In286853322, ~z$w_buff0_used~0=~z$w_buff0_used~0_In286853322, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In286853322, ~z$w_buff1_used~0=~z$w_buff1_used~0_In286853322} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In286853322, ~z$w_buff0_used~0=~z$w_buff0_used~0_In286853322, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In286853322, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out286853322|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In286853322} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 17:13:32,861 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L849-->L850: Formula: (and (= v_~z$r_buff0_thd0~0_119 v_~z$r_buff0_thd0~0_120) (not (= 0 (mod v_~weak$$choice2~0_29 256)))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_120, ~weak$$choice2~0=v_~weak$$choice2~0_29} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_8|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_119, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_9|, ~weak$$choice2~0=v_~weak$$choice2~0_29, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 17:13:32,861 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L850-->L850-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In1800623210 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite46_Out1800623210| ~z$r_buff1_thd0~0_In1800623210) (= |ULTIMATE.start_main_#t~ite45_In1800623210| |ULTIMATE.start_main_#t~ite45_Out1800623210|)) (and (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In1800623210 256)))) (or (= (mod ~z$w_buff0_used~0_In1800623210 256) 0) (and .cse1 (= 0 (mod ~z$r_buff1_thd0~0_In1800623210 256))) (and (= 0 (mod ~z$w_buff1_used~0_In1800623210 256)) .cse1))) (= |ULTIMATE.start_main_#t~ite45_Out1800623210| ~z$r_buff1_thd0~0_In1800623210) (= |ULTIMATE.start_main_#t~ite45_Out1800623210| |ULTIMATE.start_main_#t~ite46_Out1800623210|) .cse0))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1800623210, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1800623210, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1800623210, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1800623210, ~weak$$choice2~0=~weak$$choice2~0_In1800623210, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In1800623210|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1800623210, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1800623210, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1800623210, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1800623210, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out1800623210|, ~weak$$choice2~0=~weak$$choice2~0_In1800623210, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out1800623210|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45] because there is no mapped edge [2019-12-07 17:13:32,861 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L852-->L855-1: Formula: (and (= v_~z$mem_tmp~0_13 v_~z~0_120) (= 0 v_~z$flush_delayed~0_24) (= (mod v_~main$tmp_guard1~0_23 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (not (= 0 (mod v_~z$flush_delayed~0_25 256)))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_13, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~z$flush_delayed~0=v_~z$flush_delayed~0_25} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_13, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~z$flush_delayed~0=v_~z$flush_delayed~0_24, ~z~0=v_~z~0_120, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 17:13:32,861 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [729] [729] L855-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 17:13:32,915 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 05:13:32 BasicIcfg [2019-12-07 17:13:32,915 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 17:13:32,916 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 17:13:32,916 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 17:13:32,916 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 17:13:32,916 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:13:13" (3/4) ... [2019-12-07 17:13:32,918 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 17:13:32,918 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] ULTIMATE.startENTRY-->L821: Formula: (let ((.cse0 (store |v_#valid_75| 0 0))) (and (= v_~weak$$choice2~0_146 0) (= v_~z$w_buff0_used~0_885 0) (= v_~z$mem_tmp~0_22 0) (= v_~z$r_buff1_thd0~0_298 0) (= 0 v_~z$r_buff1_thd2~0_83) (= 0 v_~z$r_buff1_thd4~0_140) (= 0 v_~z$r_buff1_thd1~0_83) (= 0 v_~z$flush_delayed~0_36) (= v_~z$r_buff0_thd3~0_92 0) (= |v_#valid_73| (store .cse0 |v_ULTIMATE.start_main_~#t1525~0.base_24| 1)) (= v_~z$read_delayed_var~0.offset_7 0) (= (select .cse0 |v_ULTIMATE.start_main_~#t1525~0.base_24|) 0) (= 0 |v_ULTIMATE.start_main_~#t1525~0.offset_18|) (< 0 |v_#StackHeapBarrier_18|) (= v_~__unbuffered_p3_EAX~0_100 0) (= v_~z$w_buff0~0_503 0) (= v_~z$w_buff1_used~0_515 0) (= v_~a~0_48 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t1525~0.base_24|) (= v_~x~0_57 0) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$read_delayed~0_7 0) (= v_~z~0_155 0) (= v_~main$tmp_guard1~0_32 0) (= 0 v_~weak$$choice0~0_16) (= v_~__unbuffered_cnt~0_141 0) (= 0 v_~z$r_buff1_thd3~0_146) (= v_~z$w_buff1~0_306 0) (= v_~z$r_buff0_thd0~0_394 0) (= |v_#NULL.offset_5| 0) (= v_~z$r_buff0_thd2~0_32 0) (= (store |v_#memory_int_26| |v_ULTIMATE.start_main_~#t1525~0.base_24| (store (select |v_#memory_int_26| |v_ULTIMATE.start_main_~#t1525~0.base_24|) |v_ULTIMATE.start_main_~#t1525~0.offset_18| 0)) |v_#memory_int_25|) (= v_~main$tmp_guard0~0_22 0) (= 0 v_~z$r_buff0_thd4~0_161) (= v_~y~0_76 0) (= v_~z$r_buff0_thd1~0_32 0) (= |v_#length_29| (store |v_#length_30| |v_ULTIMATE.start_main_~#t1525~0.base_24| 4)) (= 0 |v_#NULL.base_5|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_75|, #memory_int=|v_#memory_int_26|, #length=|v_#length_30|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_59|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_83, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_41|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_32|, ULTIMATE.start_main_~#t1527~0.offset=|v_ULTIMATE.start_main_~#t1527~0.offset_16|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_35|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_30|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_45|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_60|, ~a~0=v_~a~0_48, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_394, ~z$r_buff0_thd4~0=v_~z$r_buff0_thd4~0_161, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_100, #length=|v_#length_29|, ~z$mem_tmp~0=v_~z$mem_tmp~0_22, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_48|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_114|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_515, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_191|, ~z$flush_delayed~0=v_~z$flush_delayed~0_36, ULTIMATE.start_main_~#t1525~0.offset=|v_ULTIMATE.start_main_~#t1525~0.offset_18|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_35|, ULTIMATE.start_main_~#t1526~0.base=|v_ULTIMATE.start_main_~#t1526~0.base_22|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_44|, ULTIMATE.start_main_~#t1525~0.base=|v_ULTIMATE.start_main_~#t1525~0.base_24|, ~weak$$choice0~0=v_~weak$$choice0~0_16, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_38|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_83, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_10|, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_92, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_141, ~x~0=v_~x~0_57, ULTIMATE.start_main_~#t1526~0.offset=|v_ULTIMATE.start_main_~#t1526~0.offset_17|, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_140, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_40|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_57|, ~z$w_buff1~0=v_~z$w_buff1~0_306, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_43|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_31|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_29|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_51|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_44|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_298, ULTIMATE.start_main_#t~nondet26=|v_ULTIMATE.start_main_#t~nondet26_25|, ULTIMATE.start_main_~#t1527~0.base=|v_ULTIMATE.start_main_~#t1527~0.base_20|, ULTIMATE.start_main_~#t1528~0.offset=|v_ULTIMATE.start_main_~#t1528~0.offset_17|, ~y~0=v_~y~0_76, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_32, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_885, ~z$w_buff0~0=v_~z$w_buff0~0_503, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_39|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_25|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_146, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_122|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_44|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_22, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_36|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_35|, ULTIMATE.start_main_~#t1528~0.base=|v_ULTIMATE.start_main_~#t1528~0.base_21|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_31|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_25|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_9|, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_23|, ~z~0=v_~z~0_155, ~weak$$choice2~0=v_~weak$$choice2~0_146, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_32} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_~#t1527~0.offset, #NULL.offset, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~a~0, ~z$r_buff0_thd0~0, ~z$r_buff0_thd4~0, ~__unbuffered_p3_EAX~0, #length, ~z$mem_tmp~0, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_~#t1525~0.offset, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_~#t1526~0.base, ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_~#t1525~0.base, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ULTIMATE.start_main_#t~nondet15, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_~#t1526~0.offset, ~z$r_buff1_thd4~0, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite30, ~z$r_buff1_thd0~0, ULTIMATE.start_main_#t~nondet26, ULTIMATE.start_main_~#t1527~0.base, ULTIMATE.start_main_~#t1528~0.offset, ~y~0, ~z$r_buff0_thd2~0, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_~#t1528~0.base, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_#t~nondet18, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 17:13:32,918 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [732] [732] L821-1-->L823: Formula: (and (= 0 |v_ULTIMATE.start_main_~#t1526~0.offset_9|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1526~0.base_10| 4)) (not (= 0 |v_ULTIMATE.start_main_~#t1526~0.base_10|)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1526~0.base_10| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1526~0.base_10|) |v_ULTIMATE.start_main_~#t1526~0.offset_9| 1)) |v_#memory_int_13|) (= |v_#valid_35| (store |v_#valid_36| |v_ULTIMATE.start_main_~#t1526~0.base_10| 1)) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1526~0.base_10|) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t1526~0.base_10|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1526~0.base=|v_ULTIMATE.start_main_~#t1526~0.base_10|, ULTIMATE.start_main_~#t1526~0.offset=|v_ULTIMATE.start_main_~#t1526~0.offset_9|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t1526~0.base, ULTIMATE.start_main_~#t1526~0.offset] because there is no mapped edge [2019-12-07 17:13:32,919 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [753] [753] L823-1-->L825: Formula: (and (= |v_#valid_45| (store |v_#valid_46| |v_ULTIMATE.start_main_~#t1527~0.base_12| 1)) (= (select |v_#valid_46| |v_ULTIMATE.start_main_~#t1527~0.base_12|) 0) (not (= |v_ULTIMATE.start_main_~#t1527~0.base_12| 0)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1527~0.base_12|) (= 0 |v_ULTIMATE.start_main_~#t1527~0.offset_10|) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1527~0.base_12| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1527~0.base_12|) |v_ULTIMATE.start_main_~#t1527~0.offset_10| 2)) |v_#memory_int_17|) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t1527~0.base_12| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_~#t1527~0.offset=|v_ULTIMATE.start_main_~#t1527~0.offset_10|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, ULTIMATE.start_main_~#t1527~0.base=|v_ULTIMATE.start_main_~#t1527~0.base_12|, #length=|v_#length_21|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_~#t1527~0.offset, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t1527~0.base, #length] because there is no mapped edge [2019-12-07 17:13:32,919 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [743] [743] L825-1-->L827: Formula: (and (= (store |v_#length_20| |v_ULTIMATE.start_main_~#t1528~0.base_11| 4) |v_#length_19|) (= |v_#valid_39| (store |v_#valid_40| |v_ULTIMATE.start_main_~#t1528~0.base_11| 1)) (not (= 0 |v_ULTIMATE.start_main_~#t1528~0.base_11|)) (= 0 |v_ULTIMATE.start_main_~#t1528~0.offset_10|) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1528~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1528~0.base_11|) |v_ULTIMATE.start_main_~#t1528~0.offset_10| 3)) |v_#memory_int_15|) (= 0 (select |v_#valid_40| |v_ULTIMATE.start_main_~#t1528~0.base_11|)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t1528~0.base_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{ULTIMATE.start_main_~#t1528~0.base=|v_ULTIMATE.start_main_~#t1528~0.base_11|, #StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_15|, #length=|v_#length_19|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|, ULTIMATE.start_main_~#t1528~0.offset=|v_ULTIMATE.start_main_~#t1528~0.offset_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1528~0.base, #valid, #memory_int, #length, ULTIMATE.start_main_#t~nondet17, ULTIMATE.start_main_~#t1528~0.offset] because there is no mapped edge [2019-12-07 17:13:32,919 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] P3ENTRY-->L4-3: Formula: (and (not (= v_P3Thread1of1ForFork2___VERIFIER_assert_~expression_11 0)) (= v_P3Thread1of1ForFork2_~arg.base_9 |v_P3Thread1of1ForFork2_#in~arg.base_11|) (= v_P3Thread1of1ForFork2___VERIFIER_assert_~expression_11 |v_P3Thread1of1ForFork2___VERIFIER_assert_#in~expression_9|) (= (ite (not (and (not (= (mod v_~z$w_buff0_used~0_218 256) 0)) (not (= (mod v_~z$w_buff1_used~0_99 256) 0)))) 1 0) |v_P3Thread1of1ForFork2___VERIFIER_assert_#in~expression_9|) (= |v_P3Thread1of1ForFork2_#in~arg.offset_11| v_P3Thread1of1ForFork2_~arg.offset_9) (= v_~z$w_buff0_used~0_218 1) (= v_~z$w_buff0~0_48 v_~z$w_buff1~0_32) (= 2 v_~z$w_buff0~0_47) (= v_~z$w_buff0_used~0_219 v_~z$w_buff1_used~0_99)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_219, ~z$w_buff0~0=v_~z$w_buff0~0_48, P3Thread1of1ForFork2_#in~arg.offset=|v_P3Thread1of1ForFork2_#in~arg.offset_11|, P3Thread1of1ForFork2_#in~arg.base=|v_P3Thread1of1ForFork2_#in~arg.base_11|} OutVars{P3Thread1of1ForFork2___VERIFIER_assert_~expression=v_P3Thread1of1ForFork2___VERIFIER_assert_~expression_11, P3Thread1of1ForFork2_~arg.offset=v_P3Thread1of1ForFork2_~arg.offset_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_218, ~z$w_buff0~0=v_~z$w_buff0~0_47, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_99, P3Thread1of1ForFork2_#in~arg.offset=|v_P3Thread1of1ForFork2_#in~arg.offset_11|, ~z$w_buff1~0=v_~z$w_buff1~0_32, P3Thread1of1ForFork2___VERIFIER_assert_#in~expression=|v_P3Thread1of1ForFork2___VERIFIER_assert_#in~expression_9|, P3Thread1of1ForFork2_~arg.base=v_P3Thread1of1ForFork2_~arg.base_9, P3Thread1of1ForFork2_#in~arg.base=|v_P3Thread1of1ForFork2_#in~arg.base_11|} AuxVars[] AssignedVars[P3Thread1of1ForFork2___VERIFIER_assert_~expression, P3Thread1of1ForFork2_~arg.offset, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$w_buff1_used~0, ~z$w_buff1~0, P3Thread1of1ForFork2___VERIFIER_assert_#in~expression, P3Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-12-07 17:13:32,919 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_44 1) (= v_~__unbuffered_cnt~0_102 (+ v_~__unbuffered_cnt~0_103 1)) (= v_P0Thread1of1ForFork3_~arg.base_17 |v_P0Thread1of1ForFork3_#in~arg.base_19|) (= v_~a~0_40 1) (= |v_P0Thread1of1ForFork3_#res.offset_9| 0) (= |v_P0Thread1of1ForFork3_#in~arg.offset_19| v_P0Thread1of1ForFork3_~arg.offset_17) (= 0 |v_P0Thread1of1ForFork3_#res.base_9|)) InVars {P0Thread1of1ForFork3_#in~arg.offset=|v_P0Thread1of1ForFork3_#in~arg.offset_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_103, P0Thread1of1ForFork3_#in~arg.base=|v_P0Thread1of1ForFork3_#in~arg.base_19|} OutVars{~a~0=v_~a~0_40, P0Thread1of1ForFork3_#in~arg.offset=|v_P0Thread1of1ForFork3_#in~arg.offset_19|, P0Thread1of1ForFork3_~arg.base=v_P0Thread1of1ForFork3_~arg.base_17, P0Thread1of1ForFork3_#res.base=|v_P0Thread1of1ForFork3_#res.base_9|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_102, P0Thread1of1ForFork3_#res.offset=|v_P0Thread1of1ForFork3_#res.offset_9|, P0Thread1of1ForFork3_~arg.offset=v_P0Thread1of1ForFork3_~arg.offset_17, P0Thread1of1ForFork3_#in~arg.base=|v_P0Thread1of1ForFork3_#in~arg.base_19|, ~x~0=v_~x~0_44} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork3_~arg.base, P0Thread1of1ForFork3_#res.base, ~__unbuffered_cnt~0, P0Thread1of1ForFork3_#res.offset, P0Thread1of1ForFork3_~arg.offset, ~x~0] because there is no mapped edge [2019-12-07 17:13:32,919 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [746] [746] P1ENTRY-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork0_#res.offset_3|) (= v_~x~0_39 2) (= v_~__unbuffered_cnt~0_78 (+ v_~__unbuffered_cnt~0_79 1)) (= v_~y~0_50 1) (= 0 |v_P1Thread1of1ForFork0_#res.base_3|) (= |v_P1Thread1of1ForFork0_#in~arg.base_10| v_P1Thread1of1ForFork0_~arg.base_8) (= |v_P1Thread1of1ForFork0_#in~arg.offset_10| v_P1Thread1of1ForFork0_~arg.offset_8)) InVars {P1Thread1of1ForFork0_#in~arg.base=|v_P1Thread1of1ForFork0_#in~arg.base_10|, P1Thread1of1ForFork0_#in~arg.offset=|v_P1Thread1of1ForFork0_#in~arg.offset_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_79} OutVars{P1Thread1of1ForFork0_~arg.offset=v_P1Thread1of1ForFork0_~arg.offset_8, P1Thread1of1ForFork0_~arg.base=v_P1Thread1of1ForFork0_~arg.base_8, P1Thread1of1ForFork0_#in~arg.base=|v_P1Thread1of1ForFork0_#in~arg.base_10|, P1Thread1of1ForFork0_#in~arg.offset=|v_P1Thread1of1ForFork0_#in~arg.offset_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_78, P1Thread1of1ForFork0_#res.offset=|v_P1Thread1of1ForFork0_#res.offset_3|, ~y~0=v_~y~0_50, P1Thread1of1ForFork0_#res.base=|v_P1Thread1of1ForFork0_#res.base_3|, ~x~0=v_~x~0_39} AuxVars[] AssignedVars[P1Thread1of1ForFork0_~arg.offset, P1Thread1of1ForFork0_~arg.base, ~__unbuffered_cnt~0, P1Thread1of1ForFork0_#res.offset, ~y~0, P1Thread1of1ForFork0_#res.base, ~x~0] because there is no mapped edge [2019-12-07 17:13:32,920 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L768-2-->L768-5: Formula: (let ((.cse0 (= |P2Thread1of1ForFork1_#t~ite4_Out-1958956457| |P2Thread1of1ForFork1_#t~ite3_Out-1958956457|)) (.cse2 (= (mod ~z$r_buff1_thd3~0_In-1958956457 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1958956457 256)))) (or (and .cse0 (not .cse1) (= ~z$w_buff1~0_In-1958956457 |P2Thread1of1ForFork1_#t~ite3_Out-1958956457|) (not .cse2)) (and .cse0 (= ~z~0_In-1958956457 |P2Thread1of1ForFork1_#t~ite3_Out-1958956457|) (or .cse2 .cse1)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1958956457, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1958956457, ~z$w_buff1~0=~z$w_buff1~0_In-1958956457, ~z~0=~z~0_In-1958956457} OutVars{P2Thread1of1ForFork1_#t~ite4=|P2Thread1of1ForFork1_#t~ite4_Out-1958956457|, P2Thread1of1ForFork1_#t~ite3=|P2Thread1of1ForFork1_#t~ite3_Out-1958956457|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1958956457, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1958956457, ~z$w_buff1~0=~z$w_buff1~0_In-1958956457, ~z~0=~z~0_In-1958956457} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite4, P2Thread1of1ForFork1_#t~ite3] because there is no mapped edge [2019-12-07 17:13:32,920 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L769-->L769-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-525449033 256))) (.cse1 (= (mod ~z$r_buff0_thd3~0_In-525449033 256) 0))) (or (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In-525449033 |P2Thread1of1ForFork1_#t~ite5_Out-525449033|)) (and (= 0 |P2Thread1of1ForFork1_#t~ite5_Out-525449033|) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-525449033, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-525449033} OutVars{P2Thread1of1ForFork1_#t~ite5=|P2Thread1of1ForFork1_#t~ite5_Out-525449033|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-525449033, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-525449033} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite5] because there is no mapped edge [2019-12-07 17:13:32,921 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] L770-->L770-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In47298888 256))) (.cse1 (= (mod ~z$r_buff0_thd3~0_In47298888 256) 0)) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In47298888 256))) (.cse3 (= (mod ~z$r_buff1_thd3~0_In47298888 256) 0))) (or (and (= ~z$w_buff1_used~0_In47298888 |P2Thread1of1ForFork1_#t~ite6_Out47298888|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P2Thread1of1ForFork1_#t~ite6_Out47298888| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In47298888, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In47298888, ~z$w_buff1_used~0=~z$w_buff1_used~0_In47298888, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In47298888} OutVars{P2Thread1of1ForFork1_#t~ite6=|P2Thread1of1ForFork1_#t~ite6_Out47298888|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In47298888, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In47298888, ~z$w_buff1_used~0=~z$w_buff1_used~0_In47298888, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In47298888} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite6] because there is no mapped edge [2019-12-07 17:13:32,921 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [710] [710] L771-->L771-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In1728282874 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In1728282874 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork1_#t~ite7_Out1728282874| ~z$r_buff0_thd3~0_In1728282874)) (and (not .cse0) (= |P2Thread1of1ForFork1_#t~ite7_Out1728282874| 0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1728282874, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1728282874} OutVars{P2Thread1of1ForFork1_#t~ite7=|P2Thread1of1ForFork1_#t~ite7_Out1728282874|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1728282874, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1728282874} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite7] because there is no mapped edge [2019-12-07 17:13:32,921 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L772-->L772-2: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In1456030982 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd3~0_In1456030982 256) 0)) (.cse2 (= (mod ~z$r_buff0_thd3~0_In1456030982 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In1456030982 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork1_#t~ite8_Out1456030982| 0)) (and (= |P2Thread1of1ForFork1_#t~ite8_Out1456030982| ~z$r_buff1_thd3~0_In1456030982) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1456030982, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1456030982, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1456030982, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1456030982} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1456030982, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1456030982, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1456030982, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1456030982, P2Thread1of1ForFork1_#t~ite8=|P2Thread1of1ForFork1_#t~ite8_Out1456030982|} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 17:13:32,921 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [752] [752] L772-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork1_#res.offset_3|) (= v_~z$r_buff1_thd3~0_127 |v_P2Thread1of1ForFork1_#t~ite8_44|) (= v_~__unbuffered_cnt~0_100 (+ v_~__unbuffered_cnt~0_101 1)) (= 0 |v_P2Thread1of1ForFork1_#res.base_3|)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_101, P2Thread1of1ForFork1_#t~ite8=|v_P2Thread1of1ForFork1_#t~ite8_44|} OutVars{P2Thread1of1ForFork1_#res.base=|v_P2Thread1of1ForFork1_#res.base_3|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_127, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_100, P2Thread1of1ForFork1_#res.offset=|v_P2Thread1of1ForFork1_#res.offset_3|, P2Thread1of1ForFork1_#t~ite8=|v_P2Thread1of1ForFork1_#t~ite8_43|} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#res.base, ~z$r_buff1_thd3~0, ~__unbuffered_cnt~0, P2Thread1of1ForFork1_#res.offset, P2Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 17:13:32,922 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [727] [727] L799-->L799-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd4~0_In-850061479 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-850061479 256) 0))) (or (and (or .cse0 .cse1) (= |P3Thread1of1ForFork2_#t~ite11_Out-850061479| ~z$w_buff0_used~0_In-850061479)) (and (not .cse0) (not .cse1) (= 0 |P3Thread1of1ForFork2_#t~ite11_Out-850061479|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-850061479, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-850061479} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-850061479, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-850061479, P3Thread1of1ForFork2_#t~ite11=|P3Thread1of1ForFork2_#t~ite11_Out-850061479|} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-12-07 17:13:32,922 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L800-->L800-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd4~0_In811056250 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In811056250 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd4~0_In811056250 256))) (.cse3 (= (mod ~z$w_buff0_used~0_In811056250 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P3Thread1of1ForFork2_#t~ite12_Out811056250| 0)) (and (= |P3Thread1of1ForFork2_#t~ite12_Out811056250| ~z$w_buff1_used~0_In811056250) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In811056250, ~z$w_buff0_used~0=~z$w_buff0_used~0_In811056250, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In811056250, ~z$w_buff1_used~0=~z$w_buff1_used~0_In811056250} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In811056250, ~z$w_buff0_used~0=~z$w_buff0_used~0_In811056250, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In811056250, ~z$w_buff1_used~0=~z$w_buff1_used~0_In811056250, P3Thread1of1ForFork2_#t~ite12=|P3Thread1of1ForFork2_#t~ite12_Out811056250|} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite12] because there is no mapped edge [2019-12-07 17:13:32,923 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L801-->L802: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-48204289 256) 0)) (.cse0 (= ~z$r_buff0_thd4~0_Out-48204289 ~z$r_buff0_thd4~0_In-48204289)) (.cse2 (= 0 (mod ~z$r_buff0_thd4~0_In-48204289 256)))) (or (and .cse0 .cse1) (and (not .cse2) (= 0 ~z$r_buff0_thd4~0_Out-48204289) (not .cse1)) (and .cse0 .cse2))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-48204289, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-48204289} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-48204289, P3Thread1of1ForFork2_#t~ite13=|P3Thread1of1ForFork2_#t~ite13_Out-48204289|, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out-48204289} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite13, ~z$r_buff0_thd4~0] because there is no mapped edge [2019-12-07 17:13:32,923 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L802-->L802-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd4~0_In-695131456 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-695131456 256))) (.cse3 (= (mod ~z$w_buff1_used~0_In-695131456 256) 0)) (.cse2 (= (mod ~z$r_buff1_thd4~0_In-695131456 256) 0))) (or (and (= |P3Thread1of1ForFork2_#t~ite14_Out-695131456| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse3 .cse2) (= |P3Thread1of1ForFork2_#t~ite14_Out-695131456| ~z$r_buff1_thd4~0_In-695131456)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-695131456, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-695131456, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-695131456, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-695131456} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In-695131456, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-695131456, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-695131456, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-695131456, P3Thread1of1ForFork2_#t~ite14=|P3Thread1of1ForFork2_#t~ite14_Out-695131456|} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite14] because there is no mapped edge [2019-12-07 17:13:32,923 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L802-2-->P3EXIT: Formula: (and (= |v_P3Thread1of1ForFork2_#t~ite14_54| v_~z$r_buff1_thd4~0_130) (= 0 |v_P3Thread1of1ForFork2_#res.base_3|) (= v_~__unbuffered_cnt~0_126 (+ v_~__unbuffered_cnt~0_127 1)) (= 0 |v_P3Thread1of1ForFork2_#res.offset_3|)) InVars {P3Thread1of1ForFork2_#t~ite14=|v_P3Thread1of1ForFork2_#t~ite14_54|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_127} OutVars{P3Thread1of1ForFork2_#res.base=|v_P3Thread1of1ForFork2_#res.base_3|, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_130, P3Thread1of1ForFork2_#t~ite14=|v_P3Thread1of1ForFork2_#t~ite14_53|, P3Thread1of1ForFork2_#res.offset=|v_P3Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_126} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#res.base, ~z$r_buff1_thd4~0, P3Thread1of1ForFork2_#t~ite14, P3Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 17:13:32,923 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [673] [673] L827-1-->L833: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= (ite (= 4 v_~__unbuffered_cnt~0_21) 1 0) 0) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_21} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_21, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_6|} AuxVars[] AssignedVars[~main$tmp_guard0~0, ULTIMATE.start_main_#t~nondet18] because there is no mapped edge [2019-12-07 17:13:32,923 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L833-2-->L833-4: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In-2097104797 256))) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-2097104797 256) 0))) (or (and (= ~z$w_buff1~0_In-2097104797 |ULTIMATE.start_main_#t~ite19_Out-2097104797|) (not .cse0) (not .cse1)) (and (= ~z~0_In-2097104797 |ULTIMATE.start_main_#t~ite19_Out-2097104797|) (or .cse0 .cse1)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-2097104797, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2097104797, ~z$w_buff1~0=~z$w_buff1~0_In-2097104797, ~z~0=~z~0_In-2097104797} OutVars{ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-2097104797|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-2097104797, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2097104797, ~z$w_buff1~0=~z$w_buff1~0_In-2097104797, ~z~0=~z~0_In-2097104797} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 17:13:32,923 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [658] [658] L833-4-->L834: Formula: (= v_~z~0_31 |v_ULTIMATE.start_main_#t~ite19_8|) InVars {ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_8|} OutVars{ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_7|, ~z~0=v_~z~0_31, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19, ~z~0, ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 17:13:32,923 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L834-->L834-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In1490144348 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In1490144348 256)))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite21_Out1490144348|)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite21_Out1490144348| ~z$w_buff0_used~0_In1490144348)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1490144348, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1490144348} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1490144348, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1490144348, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out1490144348|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 17:13:32,924 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [725] [725] L835-->L835-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In-2061247142 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-2061247142 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In-2061247142 256) 0)) (.cse3 (= (mod ~z$r_buff0_thd0~0_In-2061247142 256) 0))) (or (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In-2061247142 |ULTIMATE.start_main_#t~ite22_Out-2061247142|) (or .cse2 .cse3)) (and (= |ULTIMATE.start_main_#t~ite22_Out-2061247142| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-2061247142, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-2061247142, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-2061247142, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2061247142} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-2061247142, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-2061247142, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-2061247142, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2061247142, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-2061247142|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 17:13:32,924 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [718] [718] L836-->L836-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In-1608978250 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-1608978250 256) 0))) (or (and (or .cse0 .cse1) (= ~z$r_buff0_thd0~0_In-1608978250 |ULTIMATE.start_main_#t~ite23_Out-1608978250|)) (and (= 0 |ULTIMATE.start_main_#t~ite23_Out-1608978250|) (not .cse1) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1608978250, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1608978250} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1608978250, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1608978250, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-1608978250|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 17:13:32,924 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [711] [711] L837-->L837-2: Formula: (let ((.cse3 (= (mod ~z$w_buff1_used~0_In286853322 256) 0)) (.cse2 (= (mod ~z$r_buff1_thd0~0_In286853322 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In286853322 256))) (.cse0 (= (mod ~z$r_buff0_thd0~0_In286853322 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite24_Out286853322| ~z$r_buff1_thd0~0_In286853322)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0))) (= |ULTIMATE.start_main_#t~ite24_Out286853322| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In286853322, ~z$w_buff0_used~0=~z$w_buff0_used~0_In286853322, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In286853322, ~z$w_buff1_used~0=~z$w_buff1_used~0_In286853322} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In286853322, ~z$w_buff0_used~0=~z$w_buff0_used~0_In286853322, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In286853322, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out286853322|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In286853322} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 17:13:32,927 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L849-->L850: Formula: (and (= v_~z$r_buff0_thd0~0_119 v_~z$r_buff0_thd0~0_120) (not (= 0 (mod v_~weak$$choice2~0_29 256)))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_120, ~weak$$choice2~0=v_~weak$$choice2~0_29} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_8|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_119, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_9|, ~weak$$choice2~0=v_~weak$$choice2~0_29, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 17:13:32,927 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L850-->L850-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In1800623210 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite46_Out1800623210| ~z$r_buff1_thd0~0_In1800623210) (= |ULTIMATE.start_main_#t~ite45_In1800623210| |ULTIMATE.start_main_#t~ite45_Out1800623210|)) (and (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In1800623210 256)))) (or (= (mod ~z$w_buff0_used~0_In1800623210 256) 0) (and .cse1 (= 0 (mod ~z$r_buff1_thd0~0_In1800623210 256))) (and (= 0 (mod ~z$w_buff1_used~0_In1800623210 256)) .cse1))) (= |ULTIMATE.start_main_#t~ite45_Out1800623210| ~z$r_buff1_thd0~0_In1800623210) (= |ULTIMATE.start_main_#t~ite45_Out1800623210| |ULTIMATE.start_main_#t~ite46_Out1800623210|) .cse0))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1800623210, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1800623210, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1800623210, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1800623210, ~weak$$choice2~0=~weak$$choice2~0_In1800623210, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In1800623210|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1800623210, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1800623210, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1800623210, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1800623210, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out1800623210|, ~weak$$choice2~0=~weak$$choice2~0_In1800623210, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out1800623210|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45] because there is no mapped edge [2019-12-07 17:13:32,928 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L852-->L855-1: Formula: (and (= v_~z$mem_tmp~0_13 v_~z~0_120) (= 0 v_~z$flush_delayed~0_24) (= (mod v_~main$tmp_guard1~0_23 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (not (= 0 (mod v_~z$flush_delayed~0_25 256)))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_13, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~z$flush_delayed~0=v_~z$flush_delayed~0_25} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_13, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~z$flush_delayed~0=v_~z$flush_delayed~0_24, ~z~0=v_~z~0_120, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 17:13:32,928 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [729] [729] L855-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 17:13:32,985 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_63a3ea3c-e52a-495d-8b24-6ec983fbeb86/bin/uautomizer/witness.graphml [2019-12-07 17:13:32,985 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 17:13:32,986 INFO L168 Benchmark]: Toolchain (without parser) took 20179.55 ms. Allocated memory was 1.0 GB in the beginning and 3.1 GB in the end (delta: 2.1 GB). Free memory was 935.2 MB in the beginning and 2.4 GB in the end (delta: -1.5 GB). Peak memory consumption was 630.0 MB. Max. memory is 11.5 GB. [2019-12-07 17:13:32,987 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 954.1 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 17:13:32,987 INFO L168 Benchmark]: CACSL2BoogieTranslator took 409.16 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 109.6 MB). Free memory was 935.2 MB in the beginning and 1.1 GB in the end (delta: -142.0 MB). Peak memory consumption was 22.4 MB. Max. memory is 11.5 GB. [2019-12-07 17:13:32,987 INFO L168 Benchmark]: Boogie Procedure Inliner took 56.22 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 4.0 MB). Peak memory consumption was 4.0 MB. Max. memory is 11.5 GB. [2019-12-07 17:13:32,987 INFO L168 Benchmark]: Boogie Preprocessor took 38.58 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. [2019-12-07 17:13:32,988 INFO L168 Benchmark]: RCFGBuilder took 412.21 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 53.1 MB). Peak memory consumption was 53.1 MB. Max. memory is 11.5 GB. [2019-12-07 17:13:32,988 INFO L168 Benchmark]: TraceAbstraction took 19190.40 ms. Allocated memory was 1.1 GB in the beginning and 3.1 GB in the end (delta: 2.0 GB). Free memory was 1.0 GB in the beginning and 2.4 GB in the end (delta: -1.4 GB). Peak memory consumption was 547.5 MB. Max. memory is 11.5 GB. [2019-12-07 17:13:32,988 INFO L168 Benchmark]: Witness Printer took 69.78 ms. Allocated memory is still 3.1 GB. Free memory was 2.4 GB in the beginning and 2.4 GB in the end (delta: 48.4 MB). Peak memory consumption was 48.4 MB. Max. memory is 11.5 GB. [2019-12-07 17:13:32,990 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 954.1 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 409.16 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 109.6 MB). Free memory was 935.2 MB in the beginning and 1.1 GB in the end (delta: -142.0 MB). Peak memory consumption was 22.4 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 56.22 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 4.0 MB). Peak memory consumption was 4.0 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 38.58 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 412.21 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 53.1 MB). Peak memory consumption was 53.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 19190.40 ms. Allocated memory was 1.1 GB in the beginning and 3.1 GB in the end (delta: 2.0 GB). Free memory was 1.0 GB in the beginning and 2.4 GB in the end (delta: -1.4 GB). Peak memory consumption was 547.5 MB. Max. memory is 11.5 GB. * Witness Printer took 69.78 ms. Allocated memory is still 3.1 GB. Free memory was 2.4 GB in the beginning and 2.4 GB in the end (delta: 48.4 MB). Peak memory consumption was 48.4 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.2s, 178 ProgramPointsBefore, 91 ProgramPointsAfterwards, 206 TransitionsBefore, 100 TransitionsAfterwards, 12668 CoEnabledTransitionPairs, 8 FixpointIterations, 34 TrivialSequentialCompositions, 49 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 36 ConcurrentYvCompositions, 24 ChoiceCompositions, 4617 VarBasedMoverChecksPositive, 237 VarBasedMoverChecksNegative, 66 SemBasedMoverChecksPositive, 231 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.9s, 0 MoverChecksTotal, 56276 CheckedPairsTotal, 119 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L821] FCALL, FORK 0 pthread_create(&t1525, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L823] FCALL, FORK 0 pthread_create(&t1526, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L825] FCALL, FORK 0 pthread_create(&t1527, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L827] FCALL, FORK 0 pthread_create(&t1528, ((void *)0), P3, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L787] 4 z$r_buff1_thd0 = z$r_buff0_thd0 [L788] 4 z$r_buff1_thd1 = z$r_buff0_thd1 [L789] 4 z$r_buff1_thd2 = z$r_buff0_thd2 [L790] 4 z$r_buff1_thd3 = z$r_buff0_thd3 [L791] 4 z$r_buff1_thd4 = z$r_buff0_thd4 [L792] 4 z$r_buff0_thd4 = (_Bool)1 [L795] 4 __unbuffered_p3_EAX = a VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L762] 3 y = 2 [L765] 3 z = 1 VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=2, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L768] EXPR 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=2, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L768] 3 z = z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) [L769] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L770] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L771] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L798] EXPR 4 z$w_buff0_used && z$r_buff0_thd4 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd4 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L798] 4 z = z$w_buff0_used && z$r_buff0_thd4 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd4 ? z$w_buff1 : z) [L799] 4 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd4 ? (_Bool)0 : z$w_buff0_used [L800] 4 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd4 || z$w_buff1_used && z$r_buff1_thd4 ? (_Bool)0 : z$w_buff1_used [L833] 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L834] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L835] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L836] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L837] 0 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L840] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L841] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L842] 0 z$flush_delayed = weak$$choice2 [L843] 0 z$mem_tmp = z VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L844] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L844] 0 z = !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) [L845] EXPR 0 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L845] 0 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) [L846] EXPR 0 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L846] 0 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) [L847] EXPR 0 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L847] 0 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) [L848] EXPR 0 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L848] 0 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L850] 0 z$r_buff1_thd0 = weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L851] 0 main$tmp_guard1 = !(x == 2 && y == 2 && z == 2 && __unbuffered_p3_EAX == 0) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 166 locations, 2 error locations. Result: UNSAFE, OverallTime: 19.0s, OverallIterations: 19, TraceHistogramMax: 1, AutomataDifference: 5.1s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 2202 SDtfs, 2119 SDslu, 4390 SDs, 0 SdLazy, 2514 SolverSat, 178 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 141 GetRequests, 29 SyntacticMatches, 11 SemanticMatches, 101 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 380 ImplicationChecksByTransitivity, 0.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=51986occurred in iteration=4, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 7.3s AutomataMinimizationTime, 18 MinimizatonAttempts, 45567 StatesRemovedByMinimization, 12 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 0.7s InterpolantComputationTime, 806 NumberOfCodeBlocks, 806 NumberOfCodeBlocksAsserted, 19 NumberOfCheckSat, 728 ConstructedInterpolants, 0 QuantifiedInterpolants, 103893 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 18 InterpolantComputations, 18 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...