./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix057_tso.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_a7ded2e5-15b1-4e8a-af1f-a731b5758483/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_a7ded2e5-15b1-4e8a-af1f-a731b5758483/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_a7ded2e5-15b1-4e8a-af1f-a731b5758483/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_a7ded2e5-15b1-4e8a-af1f-a731b5758483/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix057_tso.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_a7ded2e5-15b1-4e8a-af1f-a731b5758483/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_a7ded2e5-15b1-4e8a-af1f-a731b5758483/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 56b2f9696651505995923f0121e06c7344e7e02e ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 14:15:40,569 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 14:15:40,570 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 14:15:40,579 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 14:15:40,579 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 14:15:40,580 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 14:15:40,581 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 14:15:40,582 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 14:15:40,584 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 14:15:40,585 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 14:15:40,586 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 14:15:40,587 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 14:15:40,587 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 14:15:40,588 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 14:15:40,589 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 14:15:40,590 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 14:15:40,591 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 14:15:40,591 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 14:15:40,593 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 14:15:40,595 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 14:15:40,597 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 14:15:40,598 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 14:15:40,598 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 14:15:40,599 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 14:15:40,601 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 14:15:40,601 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 14:15:40,602 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 14:15:40,602 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 14:15:40,602 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 14:15:40,603 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 14:15:40,603 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 14:15:40,604 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 14:15:40,604 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 14:15:40,605 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 14:15:40,606 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 14:15:40,606 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 14:15:40,606 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 14:15:40,606 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 14:15:40,607 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 14:15:40,607 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 14:15:40,608 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 14:15:40,609 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_a7ded2e5-15b1-4e8a-af1f-a731b5758483/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 14:15:40,620 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 14:15:40,620 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 14:15:40,621 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 14:15:40,621 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 14:15:40,621 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 14:15:40,621 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 14:15:40,621 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 14:15:40,621 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 14:15:40,621 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 14:15:40,621 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 14:15:40,621 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 14:15:40,622 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 14:15:40,622 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 14:15:40,622 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 14:15:40,622 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 14:15:40,622 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 14:15:40,622 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 14:15:40,622 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 14:15:40,623 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 14:15:40,623 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 14:15:40,623 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 14:15:40,623 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 14:15:40,623 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 14:15:40,623 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 14:15:40,623 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 14:15:40,623 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 14:15:40,624 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 14:15:40,624 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 14:15:40,624 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 14:15:40,624 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_a7ded2e5-15b1-4e8a-af1f-a731b5758483/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 56b2f9696651505995923f0121e06c7344e7e02e [2019-12-07 14:15:40,736 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 14:15:40,743 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 14:15:40,746 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 14:15:40,746 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 14:15:40,747 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 14:15:40,747 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_a7ded2e5-15b1-4e8a-af1f-a731b5758483/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix057_tso.opt.i [2019-12-07 14:15:40,784 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_a7ded2e5-15b1-4e8a-af1f-a731b5758483/bin/uautomizer/data/9b13fd346/73ac35a58cb8400db672d4869301b515/FLAG8cf490656 [2019-12-07 14:15:41,268 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 14:15:41,268 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_a7ded2e5-15b1-4e8a-af1f-a731b5758483/sv-benchmarks/c/pthread-wmm/mix057_tso.opt.i [2019-12-07 14:15:41,279 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_a7ded2e5-15b1-4e8a-af1f-a731b5758483/bin/uautomizer/data/9b13fd346/73ac35a58cb8400db672d4869301b515/FLAG8cf490656 [2019-12-07 14:15:41,288 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_a7ded2e5-15b1-4e8a-af1f-a731b5758483/bin/uautomizer/data/9b13fd346/73ac35a58cb8400db672d4869301b515 [2019-12-07 14:15:41,290 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 14:15:41,291 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 14:15:41,292 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 14:15:41,292 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 14:15:41,294 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 14:15:41,295 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 02:15:41" (1/1) ... [2019-12-07 14:15:41,297 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6a1693e9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:15:41, skipping insertion in model container [2019-12-07 14:15:41,297 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 02:15:41" (1/1) ... [2019-12-07 14:15:41,302 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 14:15:41,331 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 14:15:41,575 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 14:15:41,584 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 14:15:41,627 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 14:15:41,673 INFO L208 MainTranslator]: Completed translation [2019-12-07 14:15:41,673 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:15:41 WrapperNode [2019-12-07 14:15:41,674 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 14:15:41,674 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 14:15:41,674 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 14:15:41,674 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 14:15:41,680 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:15:41" (1/1) ... [2019-12-07 14:15:41,694 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:15:41" (1/1) ... [2019-12-07 14:15:41,717 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 14:15:41,717 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 14:15:41,717 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 14:15:41,718 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 14:15:41,724 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:15:41" (1/1) ... [2019-12-07 14:15:41,724 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:15:41" (1/1) ... [2019-12-07 14:15:41,727 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:15:41" (1/1) ... [2019-12-07 14:15:41,727 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:15:41" (1/1) ... [2019-12-07 14:15:41,734 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:15:41" (1/1) ... [2019-12-07 14:15:41,737 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:15:41" (1/1) ... [2019-12-07 14:15:41,740 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:15:41" (1/1) ... [2019-12-07 14:15:41,744 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 14:15:41,744 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 14:15:41,744 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 14:15:41,744 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 14:15:41,745 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:15:41" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_a7ded2e5-15b1-4e8a-af1f-a731b5758483/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 14:15:41,786 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 14:15:41,786 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 14:15:41,786 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 14:15:41,787 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 14:15:41,787 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 14:15:41,787 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 14:15:41,787 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 14:15:41,787 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 14:15:41,787 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 14:15:41,787 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 14:15:41,787 INFO L130 BoogieDeclarations]: Found specification of procedure P3 [2019-12-07 14:15:41,787 INFO L138 BoogieDeclarations]: Found implementation of procedure P3 [2019-12-07 14:15:41,787 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 14:15:41,787 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 14:15:41,788 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 14:15:41,789 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 14:15:42,140 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 14:15:42,140 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 14:15:42,141 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 02:15:42 BoogieIcfgContainer [2019-12-07 14:15:42,141 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 14:15:42,142 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 14:15:42,142 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 14:15:42,144 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 14:15:42,144 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 02:15:41" (1/3) ... [2019-12-07 14:15:42,144 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7fcd0fda and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 02:15:42, skipping insertion in model container [2019-12-07 14:15:42,144 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:15:41" (2/3) ... [2019-12-07 14:15:42,145 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7fcd0fda and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 02:15:42, skipping insertion in model container [2019-12-07 14:15:42,145 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 02:15:42" (3/3) ... [2019-12-07 14:15:42,146 INFO L109 eAbstractionObserver]: Analyzing ICFG mix057_tso.opt.i [2019-12-07 14:15:42,152 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 14:15:42,152 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 14:15:42,157 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 14:15:42,158 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 14:15:42,181 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork3_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,181 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork3_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,181 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork3_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,181 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork3_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,182 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork3_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,182 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork3_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,182 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,182 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,182 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,182 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,183 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,183 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,183 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,183 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,183 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,183 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,184 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,184 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,184 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,184 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,184 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,184 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,184 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,185 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,185 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,185 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,185 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,185 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,185 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,185 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,185 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,186 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,186 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,186 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,186 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,186 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,186 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,186 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,187 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,187 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,187 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,187 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,188 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,188 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,188 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,188 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,188 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,189 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,189 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,189 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,189 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,189 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,189 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,189 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,189 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,190 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,190 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,190 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,190 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,190 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,190 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,190 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,190 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,191 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,191 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,191 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,191 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,191 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,191 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,191 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,191 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,192 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,192 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,192 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,192 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,192 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:15:42,208 INFO L249 AbstractCegarLoop]: Starting to check reachability of 7 error locations. [2019-12-07 14:15:42,222 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 14:15:42,222 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 14:15:42,222 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 14:15:42,223 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 14:15:42,223 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 14:15:42,223 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 14:15:42,223 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 14:15:42,223 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 14:15:42,234 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 178 places, 206 transitions [2019-12-07 14:15:42,235 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 178 places, 206 transitions [2019-12-07 14:15:42,294 INFO L134 PetriNetUnfolder]: 41/202 cut-off events. [2019-12-07 14:15:42,294 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 14:15:42,303 INFO L76 FinitePrefix]: Finished finitePrefix Result has 215 conditions, 202 events. 41/202 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 483 event pairs. 12/171 useless extension candidates. Maximal degree in co-relation 172. Up to 2 conditions per place. [2019-12-07 14:15:42,314 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 178 places, 206 transitions [2019-12-07 14:15:42,342 INFO L134 PetriNetUnfolder]: 41/202 cut-off events. [2019-12-07 14:15:42,342 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 14:15:42,346 INFO L76 FinitePrefix]: Finished finitePrefix Result has 215 conditions, 202 events. 41/202 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 483 event pairs. 12/171 useless extension candidates. Maximal degree in co-relation 172. Up to 2 conditions per place. [2019-12-07 14:15:42,356 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 12668 [2019-12-07 14:15:42,357 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 14:15:45,406 WARN L192 SmtUtils]: Spent 170.00 ms on a formula simplification. DAG size of input: 93 DAG size of output: 91 [2019-12-07 14:15:45,498 INFO L206 etLargeBlockEncoding]: Checked pairs total: 56276 [2019-12-07 14:15:45,498 INFO L214 etLargeBlockEncoding]: Total number of compositions: 119 [2019-12-07 14:15:45,500 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 91 places, 100 transitions [2019-12-07 14:15:47,286 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 32878 states. [2019-12-07 14:15:47,287 INFO L276 IsEmpty]: Start isEmpty. Operand 32878 states. [2019-12-07 14:15:47,292 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2019-12-07 14:15:47,292 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:15:47,292 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:15:47,293 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:15:47,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:15:47,296 INFO L82 PathProgramCache]: Analyzing trace with hash -667351009, now seen corresponding path program 1 times [2019-12-07 14:15:47,302 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:15:47,302 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [614893187] [2019-12-07 14:15:47,302 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:15:47,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:15:47,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:15:47,456 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [614893187] [2019-12-07 14:15:47,457 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:15:47,457 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 14:15:47,458 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [947577741] [2019-12-07 14:15:47,461 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:15:47,461 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:15:47,470 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:15:47,470 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:15:47,471 INFO L87 Difference]: Start difference. First operand 32878 states. Second operand 3 states. [2019-12-07 14:15:47,809 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:15:47,809 INFO L93 Difference]: Finished difference Result 32686 states and 139960 transitions. [2019-12-07 14:15:47,810 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:15:47,811 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 9 [2019-12-07 14:15:47,811 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:15:48,014 INFO L225 Difference]: With dead ends: 32686 [2019-12-07 14:15:48,014 INFO L226 Difference]: Without dead ends: 32062 [2019-12-07 14:15:48,015 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:15:48,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32062 states. [2019-12-07 14:15:48,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32062 to 32062. [2019-12-07 14:15:48,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32062 states. [2019-12-07 14:15:49,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32062 states to 32062 states and 137412 transitions. [2019-12-07 14:15:49,001 INFO L78 Accepts]: Start accepts. Automaton has 32062 states and 137412 transitions. Word has length 9 [2019-12-07 14:15:49,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:15:49,002 INFO L462 AbstractCegarLoop]: Abstraction has 32062 states and 137412 transitions. [2019-12-07 14:15:49,002 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:15:49,002 INFO L276 IsEmpty]: Start isEmpty. Operand 32062 states and 137412 transitions. [2019-12-07 14:15:49,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 14:15:49,006 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:15:49,006 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:15:49,007 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:15:49,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:15:49,007 INFO L82 PathProgramCache]: Analyzing trace with hash -139405083, now seen corresponding path program 1 times [2019-12-07 14:15:49,007 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:15:49,007 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1571183257] [2019-12-07 14:15:49,007 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:15:49,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:15:49,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:15:49,064 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1571183257] [2019-12-07 14:15:49,064 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:15:49,064 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:15:49,064 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2132067302] [2019-12-07 14:15:49,065 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 14:15:49,065 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:15:49,065 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 14:15:49,065 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:15:49,066 INFO L87 Difference]: Start difference. First operand 32062 states and 137412 transitions. Second operand 4 states. [2019-12-07 14:15:49,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:15:49,595 INFO L93 Difference]: Finished difference Result 51166 states and 211740 transitions. [2019-12-07 14:15:49,596 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:15:49,596 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 14:15:49,596 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:15:49,784 INFO L225 Difference]: With dead ends: 51166 [2019-12-07 14:15:49,784 INFO L226 Difference]: Without dead ends: 51138 [2019-12-07 14:15:49,785 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:15:50,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51138 states. [2019-12-07 14:15:50,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51138 to 46670. [2019-12-07 14:15:50,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46670 states. [2019-12-07 14:15:50,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46670 states to 46670 states and 195108 transitions. [2019-12-07 14:15:50,843 INFO L78 Accepts]: Start accepts. Automaton has 46670 states and 195108 transitions. Word has length 15 [2019-12-07 14:15:50,844 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:15:50,844 INFO L462 AbstractCegarLoop]: Abstraction has 46670 states and 195108 transitions. [2019-12-07 14:15:50,844 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 14:15:50,844 INFO L276 IsEmpty]: Start isEmpty. Operand 46670 states and 195108 transitions. [2019-12-07 14:15:50,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 14:15:50,846 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:15:50,846 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:15:50,846 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:15:50,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:15:50,846 INFO L82 PathProgramCache]: Analyzing trace with hash 2113277815, now seen corresponding path program 1 times [2019-12-07 14:15:50,846 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:15:50,846 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [308251703] [2019-12-07 14:15:50,846 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:15:50,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:15:50,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:15:50,894 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [308251703] [2019-12-07 14:15:50,894 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:15:50,894 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:15:50,894 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1029036942] [2019-12-07 14:15:50,895 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 14:15:50,895 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:15:50,895 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 14:15:50,895 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:15:50,895 INFO L87 Difference]: Start difference. First operand 46670 states and 195108 transitions. Second operand 4 states. [2019-12-07 14:15:51,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:15:51,232 INFO L93 Difference]: Finished difference Result 57898 states and 240332 transitions. [2019-12-07 14:15:51,233 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:15:51,233 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 14:15:51,234 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:15:51,528 INFO L225 Difference]: With dead ends: 57898 [2019-12-07 14:15:51,529 INFO L226 Difference]: Without dead ends: 57898 [2019-12-07 14:15:51,529 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:15:51,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57898 states. [2019-12-07 14:15:52,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57898 to 51310. [2019-12-07 14:15:52,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51310 states. [2019-12-07 14:15:52,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51310 states to 51310 states and 214288 transitions. [2019-12-07 14:15:52,702 INFO L78 Accepts]: Start accepts. Automaton has 51310 states and 214288 transitions. Word has length 15 [2019-12-07 14:15:52,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:15:52,702 INFO L462 AbstractCegarLoop]: Abstraction has 51310 states and 214288 transitions. [2019-12-07 14:15:52,702 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 14:15:52,702 INFO L276 IsEmpty]: Start isEmpty. Operand 51310 states and 214288 transitions. [2019-12-07 14:15:52,712 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 14:15:52,712 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:15:52,712 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:15:52,712 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:15:52,712 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:15:52,713 INFO L82 PathProgramCache]: Analyzing trace with hash -942234691, now seen corresponding path program 1 times [2019-12-07 14:15:52,713 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:15:52,713 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [631703122] [2019-12-07 14:15:52,713 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:15:52,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:15:52,782 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:15:52,783 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [631703122] [2019-12-07 14:15:52,783 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:15:52,783 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:15:52,783 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [778893143] [2019-12-07 14:15:52,784 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:15:52,784 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:15:52,784 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:15:52,784 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:15:52,784 INFO L87 Difference]: Start difference. First operand 51310 states and 214288 transitions. Second operand 5 states. [2019-12-07 14:15:53,292 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:15:53,293 INFO L93 Difference]: Finished difference Result 69354 states and 284756 transitions. [2019-12-07 14:15:53,293 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 14:15:53,294 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2019-12-07 14:15:53,294 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:15:53,444 INFO L225 Difference]: With dead ends: 69354 [2019-12-07 14:15:53,444 INFO L226 Difference]: Without dead ends: 69326 [2019-12-07 14:15:53,444 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:15:53,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69326 states. [2019-12-07 14:15:54,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69326 to 51342. [2019-12-07 14:15:54,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51342 states. [2019-12-07 14:15:54,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51342 states to 51342 states and 213896 transitions. [2019-12-07 14:15:54,682 INFO L78 Accepts]: Start accepts. Automaton has 51342 states and 213896 transitions. Word has length 21 [2019-12-07 14:15:54,682 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:15:54,682 INFO L462 AbstractCegarLoop]: Abstraction has 51342 states and 213896 transitions. [2019-12-07 14:15:54,682 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:15:54,683 INFO L276 IsEmpty]: Start isEmpty. Operand 51342 states and 213896 transitions. [2019-12-07 14:15:54,710 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-12-07 14:15:54,711 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:15:54,711 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:15:54,711 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:15:54,711 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:15:54,711 INFO L82 PathProgramCache]: Analyzing trace with hash 1902768364, now seen corresponding path program 1 times [2019-12-07 14:15:54,711 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:15:54,711 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899214985] [2019-12-07 14:15:54,711 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:15:54,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:15:54,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:15:54,743 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [899214985] [2019-12-07 14:15:54,743 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:15:54,743 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:15:54,743 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1735757589] [2019-12-07 14:15:54,744 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:15:54,744 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:15:54,744 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:15:54,744 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:15:54,744 INFO L87 Difference]: Start difference. First operand 51342 states and 213896 transitions. Second operand 3 states. [2019-12-07 14:15:54,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:15:54,886 INFO L93 Difference]: Finished difference Result 40388 states and 155545 transitions. [2019-12-07 14:15:54,887 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:15:54,887 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 29 [2019-12-07 14:15:54,887 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:15:54,958 INFO L225 Difference]: With dead ends: 40388 [2019-12-07 14:15:54,958 INFO L226 Difference]: Without dead ends: 40388 [2019-12-07 14:15:54,959 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:15:55,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40388 states. [2019-12-07 14:15:55,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40388 to 40388. [2019-12-07 14:15:55,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40388 states. [2019-12-07 14:15:55,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40388 states to 40388 states and 155545 transitions. [2019-12-07 14:15:55,750 INFO L78 Accepts]: Start accepts. Automaton has 40388 states and 155545 transitions. Word has length 29 [2019-12-07 14:15:55,750 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:15:55,750 INFO L462 AbstractCegarLoop]: Abstraction has 40388 states and 155545 transitions. [2019-12-07 14:15:55,750 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:15:55,750 INFO L276 IsEmpty]: Start isEmpty. Operand 40388 states and 155545 transitions. [2019-12-07 14:15:55,770 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2019-12-07 14:15:55,771 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:15:55,771 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:15:55,771 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:15:55,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:15:55,771 INFO L82 PathProgramCache]: Analyzing trace with hash 847829435, now seen corresponding path program 1 times [2019-12-07 14:15:55,771 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:15:55,771 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1991991216] [2019-12-07 14:15:55,771 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:15:55,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:15:55,809 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:15:55,810 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1991991216] [2019-12-07 14:15:55,810 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:15:55,810 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:15:55,810 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1623118462] [2019-12-07 14:15:55,811 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 14:15:55,811 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:15:55,811 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 14:15:55,811 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:15:55,811 INFO L87 Difference]: Start difference. First operand 40388 states and 155545 transitions. Second operand 4 states. [2019-12-07 14:15:55,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:15:55,874 INFO L93 Difference]: Finished difference Result 16956 states and 54151 transitions. [2019-12-07 14:15:55,874 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 14:15:55,875 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 30 [2019-12-07 14:15:55,875 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:15:55,895 INFO L225 Difference]: With dead ends: 16956 [2019-12-07 14:15:55,896 INFO L226 Difference]: Without dead ends: 16956 [2019-12-07 14:15:55,896 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:15:55,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16956 states. [2019-12-07 14:15:56,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16956 to 16956. [2019-12-07 14:15:56,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16956 states. [2019-12-07 14:15:56,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16956 states to 16956 states and 54151 transitions. [2019-12-07 14:15:56,130 INFO L78 Accepts]: Start accepts. Automaton has 16956 states and 54151 transitions. Word has length 30 [2019-12-07 14:15:56,130 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:15:56,130 INFO L462 AbstractCegarLoop]: Abstraction has 16956 states and 54151 transitions. [2019-12-07 14:15:56,130 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 14:15:56,130 INFO L276 IsEmpty]: Start isEmpty. Operand 16956 states and 54151 transitions. [2019-12-07 14:15:56,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 14:15:56,137 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:15:56,138 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:15:56,138 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:15:56,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:15:56,138 INFO L82 PathProgramCache]: Analyzing trace with hash 613602003, now seen corresponding path program 1 times [2019-12-07 14:15:56,138 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:15:56,138 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [977966064] [2019-12-07 14:15:56,138 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:15:56,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:15:56,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:15:56,173 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [977966064] [2019-12-07 14:15:56,173 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:15:56,173 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 14:15:56,173 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1036855528] [2019-12-07 14:15:56,173 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:15:56,173 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:15:56,173 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:15:56,173 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:15:56,174 INFO L87 Difference]: Start difference. First operand 16956 states and 54151 transitions. Second operand 5 states. [2019-12-07 14:15:56,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:15:56,196 INFO L93 Difference]: Finished difference Result 2891 states and 7349 transitions. [2019-12-07 14:15:56,196 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:15:56,197 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 31 [2019-12-07 14:15:56,197 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:15:56,199 INFO L225 Difference]: With dead ends: 2891 [2019-12-07 14:15:56,199 INFO L226 Difference]: Without dead ends: 2891 [2019-12-07 14:15:56,200 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:15:56,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2891 states. [2019-12-07 14:15:56,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2891 to 2891. [2019-12-07 14:15:56,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2891 states. [2019-12-07 14:15:56,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2891 states to 2891 states and 7349 transitions. [2019-12-07 14:15:56,227 INFO L78 Accepts]: Start accepts. Automaton has 2891 states and 7349 transitions. Word has length 31 [2019-12-07 14:15:56,227 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:15:56,227 INFO L462 AbstractCegarLoop]: Abstraction has 2891 states and 7349 transitions. [2019-12-07 14:15:56,227 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:15:56,227 INFO L276 IsEmpty]: Start isEmpty. Operand 2891 states and 7349 transitions. [2019-12-07 14:15:56,230 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2019-12-07 14:15:56,230 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:15:56,230 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:15:56,230 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:15:56,230 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:15:56,230 INFO L82 PathProgramCache]: Analyzing trace with hash 2131566482, now seen corresponding path program 1 times [2019-12-07 14:15:56,231 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:15:56,231 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1110727200] [2019-12-07 14:15:56,231 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:15:56,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:15:56,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:15:56,276 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1110727200] [2019-12-07 14:15:56,277 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:15:56,277 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 14:15:56,277 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1608841666] [2019-12-07 14:15:56,277 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 14:15:56,277 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:15:56,277 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 14:15:56,277 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2019-12-07 14:15:56,277 INFO L87 Difference]: Start difference. First operand 2891 states and 7349 transitions. Second operand 6 states. [2019-12-07 14:15:56,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:15:56,303 INFO L93 Difference]: Finished difference Result 1241 states and 3509 transitions. [2019-12-07 14:15:56,303 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 14:15:56,303 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 43 [2019-12-07 14:15:56,303 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:15:56,304 INFO L225 Difference]: With dead ends: 1241 [2019-12-07 14:15:56,304 INFO L226 Difference]: Without dead ends: 1241 [2019-12-07 14:15:56,305 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2019-12-07 14:15:56,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1241 states. [2019-12-07 14:15:56,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1241 to 1129. [2019-12-07 14:15:56,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1129 states. [2019-12-07 14:15:56,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1129 states to 1129 states and 3189 transitions. [2019-12-07 14:15:56,316 INFO L78 Accepts]: Start accepts. Automaton has 1129 states and 3189 transitions. Word has length 43 [2019-12-07 14:15:56,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:15:56,317 INFO L462 AbstractCegarLoop]: Abstraction has 1129 states and 3189 transitions. [2019-12-07 14:15:56,317 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 14:15:56,317 INFO L276 IsEmpty]: Start isEmpty. Operand 1129 states and 3189 transitions. [2019-12-07 14:15:56,318 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 14:15:56,318 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:15:56,318 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:15:56,319 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:15:56,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:15:56,319 INFO L82 PathProgramCache]: Analyzing trace with hash -275883304, now seen corresponding path program 1 times [2019-12-07 14:15:56,319 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:15:56,319 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1654723269] [2019-12-07 14:15:56,319 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:15:56,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:15:56,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:15:56,357 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1654723269] [2019-12-07 14:15:56,357 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:15:56,357 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:15:56,357 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [758836258] [2019-12-07 14:15:56,357 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:15:56,357 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:15:56,357 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:15:56,357 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:15:56,358 INFO L87 Difference]: Start difference. First operand 1129 states and 3189 transitions. Second operand 3 states. [2019-12-07 14:15:56,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:15:56,393 INFO L93 Difference]: Finished difference Result 1141 states and 3206 transitions. [2019-12-07 14:15:56,394 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:15:56,394 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 58 [2019-12-07 14:15:56,394 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:15:56,395 INFO L225 Difference]: With dead ends: 1141 [2019-12-07 14:15:56,395 INFO L226 Difference]: Without dead ends: 1141 [2019-12-07 14:15:56,396 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:15:56,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1141 states. [2019-12-07 14:15:56,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1141 to 1135. [2019-12-07 14:15:56,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1135 states. [2019-12-07 14:15:56,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1135 states to 1135 states and 3199 transitions. [2019-12-07 14:15:56,407 INFO L78 Accepts]: Start accepts. Automaton has 1135 states and 3199 transitions. Word has length 58 [2019-12-07 14:15:56,407 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:15:56,408 INFO L462 AbstractCegarLoop]: Abstraction has 1135 states and 3199 transitions. [2019-12-07 14:15:56,408 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:15:56,408 INFO L276 IsEmpty]: Start isEmpty. Operand 1135 states and 3199 transitions. [2019-12-07 14:15:56,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 14:15:56,409 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:15:56,409 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:15:56,409 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:15:56,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:15:56,410 INFO L82 PathProgramCache]: Analyzing trace with hash -791070951, now seen corresponding path program 1 times [2019-12-07 14:15:56,410 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:15:56,410 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1838746280] [2019-12-07 14:15:56,410 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:15:56,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:15:56,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:15:56,466 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1838746280] [2019-12-07 14:15:56,467 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:15:56,467 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 14:15:56,467 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1352292896] [2019-12-07 14:15:56,467 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:15:56,467 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:15:56,467 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:15:56,467 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:15:56,467 INFO L87 Difference]: Start difference. First operand 1135 states and 3199 transitions. Second operand 5 states. [2019-12-07 14:15:56,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:15:56,621 INFO L93 Difference]: Finished difference Result 1644 states and 4637 transitions. [2019-12-07 14:15:56,622 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 14:15:56,622 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 58 [2019-12-07 14:15:56,622 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:15:56,623 INFO L225 Difference]: With dead ends: 1644 [2019-12-07 14:15:56,623 INFO L226 Difference]: Without dead ends: 1644 [2019-12-07 14:15:56,624 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:15:56,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1644 states. [2019-12-07 14:15:56,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1644 to 1448. [2019-12-07 14:15:56,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1448 states. [2019-12-07 14:15:56,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1448 states to 1448 states and 4085 transitions. [2019-12-07 14:15:56,638 INFO L78 Accepts]: Start accepts. Automaton has 1448 states and 4085 transitions. Word has length 58 [2019-12-07 14:15:56,639 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:15:56,639 INFO L462 AbstractCegarLoop]: Abstraction has 1448 states and 4085 transitions. [2019-12-07 14:15:56,639 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:15:56,639 INFO L276 IsEmpty]: Start isEmpty. Operand 1448 states and 4085 transitions. [2019-12-07 14:15:56,640 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 14:15:56,640 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:15:56,641 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:15:56,641 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:15:56,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:15:56,641 INFO L82 PathProgramCache]: Analyzing trace with hash 867176459, now seen corresponding path program 2 times [2019-12-07 14:15:56,641 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:15:56,641 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1344242989] [2019-12-07 14:15:56,641 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:15:56,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:15:56,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:15:56,703 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1344242989] [2019-12-07 14:15:56,703 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:15:56,703 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 14:15:56,703 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869421712] [2019-12-07 14:15:56,703 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 14:15:56,703 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:15:56,704 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 14:15:56,704 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 14:15:56,704 INFO L87 Difference]: Start difference. First operand 1448 states and 4085 transitions. Second operand 6 states. [2019-12-07 14:15:56,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:15:56,897 INFO L93 Difference]: Finished difference Result 1722 states and 4730 transitions. [2019-12-07 14:15:56,897 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 14:15:56,897 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 58 [2019-12-07 14:15:56,897 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:15:56,899 INFO L225 Difference]: With dead ends: 1722 [2019-12-07 14:15:56,899 INFO L226 Difference]: Without dead ends: 1722 [2019-12-07 14:15:56,899 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:15:56,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1722 states. [2019-12-07 14:15:56,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1722 to 1500. [2019-12-07 14:15:56,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1500 states. [2019-12-07 14:15:56,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1500 states to 1500 states and 4161 transitions. [2019-12-07 14:15:56,913 INFO L78 Accepts]: Start accepts. Automaton has 1500 states and 4161 transitions. Word has length 58 [2019-12-07 14:15:56,913 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:15:56,913 INFO L462 AbstractCegarLoop]: Abstraction has 1500 states and 4161 transitions. [2019-12-07 14:15:56,913 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 14:15:56,913 INFO L276 IsEmpty]: Start isEmpty. Operand 1500 states and 4161 transitions. [2019-12-07 14:15:56,915 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 14:15:56,915 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:15:56,915 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:15:56,915 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:15:56,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:15:56,915 INFO L82 PathProgramCache]: Analyzing trace with hash -2105802411, now seen corresponding path program 3 times [2019-12-07 14:15:56,916 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:15:56,916 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1022300745] [2019-12-07 14:15:56,916 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:15:56,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:15:56,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:15:56,975 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1022300745] [2019-12-07 14:15:56,975 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:15:56,975 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 14:15:56,976 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1308142541] [2019-12-07 14:15:56,976 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 14:15:56,976 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:15:56,976 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 14:15:56,976 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 14:15:56,977 INFO L87 Difference]: Start difference. First operand 1500 states and 4161 transitions. Second operand 6 states. [2019-12-07 14:15:57,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:15:57,136 INFO L93 Difference]: Finished difference Result 1982 states and 5473 transitions. [2019-12-07 14:15:57,136 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 14:15:57,136 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 58 [2019-12-07 14:15:57,136 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:15:57,138 INFO L225 Difference]: With dead ends: 1982 [2019-12-07 14:15:57,138 INFO L226 Difference]: Without dead ends: 1982 [2019-12-07 14:15:57,138 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 6 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:15:57,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1982 states. [2019-12-07 14:15:57,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1982 to 1528. [2019-12-07 14:15:57,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1528 states. [2019-12-07 14:15:57,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1528 states to 1528 states and 4241 transitions. [2019-12-07 14:15:57,154 INFO L78 Accepts]: Start accepts. Automaton has 1528 states and 4241 transitions. Word has length 58 [2019-12-07 14:15:57,154 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:15:57,154 INFO L462 AbstractCegarLoop]: Abstraction has 1528 states and 4241 transitions. [2019-12-07 14:15:57,154 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 14:15:57,154 INFO L276 IsEmpty]: Start isEmpty. Operand 1528 states and 4241 transitions. [2019-12-07 14:15:57,156 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 14:15:57,156 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:15:57,156 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:15:57,156 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:15:57,156 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:15:57,157 INFO L82 PathProgramCache]: Analyzing trace with hash -645544041, now seen corresponding path program 4 times [2019-12-07 14:15:57,157 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:15:57,157 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [941370876] [2019-12-07 14:15:57,157 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:15:57,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:15:57,240 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:15:57,240 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [941370876] [2019-12-07 14:15:57,240 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:15:57,240 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 14:15:57,240 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1523391639] [2019-12-07 14:15:57,240 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 14:15:57,241 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:15:57,241 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 14:15:57,241 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2019-12-07 14:15:57,241 INFO L87 Difference]: Start difference. First operand 1528 states and 4241 transitions. Second operand 8 states. [2019-12-07 14:15:57,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:15:57,496 INFO L93 Difference]: Finished difference Result 2195 states and 6052 transitions. [2019-12-07 14:15:57,497 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 14:15:57,497 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 58 [2019-12-07 14:15:57,497 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:15:57,499 INFO L225 Difference]: With dead ends: 2195 [2019-12-07 14:15:57,499 INFO L226 Difference]: Without dead ends: 2195 [2019-12-07 14:15:57,499 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 8 SyntacticMatches, 2 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=44, Invalid=112, Unknown=0, NotChecked=0, Total=156 [2019-12-07 14:15:57,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2195 states. [2019-12-07 14:15:57,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2195 to 1528. [2019-12-07 14:15:57,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1528 states. [2019-12-07 14:15:57,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1528 states to 1528 states and 4241 transitions. [2019-12-07 14:15:57,516 INFO L78 Accepts]: Start accepts. Automaton has 1528 states and 4241 transitions. Word has length 58 [2019-12-07 14:15:57,516 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:15:57,516 INFO L462 AbstractCegarLoop]: Abstraction has 1528 states and 4241 transitions. [2019-12-07 14:15:57,516 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 14:15:57,516 INFO L276 IsEmpty]: Start isEmpty. Operand 1528 states and 4241 transitions. [2019-12-07 14:15:57,518 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 14:15:57,518 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:15:57,518 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:15:57,518 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:15:57,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:15:57,519 INFO L82 PathProgramCache]: Analyzing trace with hash -515953626, now seen corresponding path program 1 times [2019-12-07 14:15:57,519 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:15:57,519 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1351742418] [2019-12-07 14:15:57,519 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:15:57,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:15:57,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:15:57,668 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1351742418] [2019-12-07 14:15:57,668 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:15:57,669 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 14:15:57,669 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [744883504] [2019-12-07 14:15:57,669 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 14:15:57,669 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:15:57,669 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 14:15:57,669 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2019-12-07 14:15:57,669 INFO L87 Difference]: Start difference. First operand 1528 states and 4241 transitions. Second operand 12 states. [2019-12-07 14:15:58,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:15:58,112 INFO L93 Difference]: Finished difference Result 3581 states and 9053 transitions. [2019-12-07 14:15:58,112 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 14:15:58,112 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 59 [2019-12-07 14:15:58,113 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:15:58,114 INFO L225 Difference]: With dead ends: 3581 [2019-12-07 14:15:58,115 INFO L226 Difference]: Without dead ends: 2312 [2019-12-07 14:15:58,115 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 92 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=173, Invalid=427, Unknown=0, NotChecked=0, Total=600 [2019-12-07 14:15:58,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2312 states. [2019-12-07 14:15:58,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2312 to 1382. [2019-12-07 14:15:58,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1382 states. [2019-12-07 14:15:58,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1382 states to 1382 states and 3747 transitions. [2019-12-07 14:15:58,133 INFO L78 Accepts]: Start accepts. Automaton has 1382 states and 3747 transitions. Word has length 59 [2019-12-07 14:15:58,133 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:15:58,134 INFO L462 AbstractCegarLoop]: Abstraction has 1382 states and 3747 transitions. [2019-12-07 14:15:58,134 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 14:15:58,134 INFO L276 IsEmpty]: Start isEmpty. Operand 1382 states and 3747 transitions. [2019-12-07 14:15:58,136 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 14:15:58,136 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:15:58,136 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:15:58,136 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:15:58,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:15:58,136 INFO L82 PathProgramCache]: Analyzing trace with hash -1634865510, now seen corresponding path program 2 times [2019-12-07 14:15:58,137 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:15:58,137 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1808678100] [2019-12-07 14:15:58,137 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:15:58,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:15:58,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:15:58,186 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1808678100] [2019-12-07 14:15:58,186 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:15:58,186 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:15:58,186 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1304525877] [2019-12-07 14:15:58,187 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:15:58,187 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:15:58,187 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:15:58,187 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:15:58,187 INFO L87 Difference]: Start difference. First operand 1382 states and 3747 transitions. Second operand 3 states. [2019-12-07 14:15:58,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:15:58,225 INFO L93 Difference]: Finished difference Result 1381 states and 3745 transitions. [2019-12-07 14:15:58,225 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:15:58,225 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 59 [2019-12-07 14:15:58,225 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:15:58,227 INFO L225 Difference]: With dead ends: 1381 [2019-12-07 14:15:58,227 INFO L226 Difference]: Without dead ends: 1381 [2019-12-07 14:15:58,227 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:15:58,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1381 states. [2019-12-07 14:15:58,241 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1381 to 1040. [2019-12-07 14:15:58,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1040 states. [2019-12-07 14:15:58,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1040 states to 1040 states and 2795 transitions. [2019-12-07 14:15:58,243 INFO L78 Accepts]: Start accepts. Automaton has 1040 states and 2795 transitions. Word has length 59 [2019-12-07 14:15:58,243 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:15:58,243 INFO L462 AbstractCegarLoop]: Abstraction has 1040 states and 2795 transitions. [2019-12-07 14:15:58,243 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:15:58,243 INFO L276 IsEmpty]: Start isEmpty. Operand 1040 states and 2795 transitions. [2019-12-07 14:15:58,245 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 14:15:58,245 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:15:58,245 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:15:58,245 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:15:58,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:15:58,245 INFO L82 PathProgramCache]: Analyzing trace with hash -516800392, now seen corresponding path program 1 times [2019-12-07 14:15:58,245 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:15:58,246 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1045435359] [2019-12-07 14:15:58,246 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:15:58,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:15:58,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:15:58,330 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1045435359] [2019-12-07 14:15:58,330 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:15:58,330 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 14:15:58,331 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1122491898] [2019-12-07 14:15:58,331 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 14:15:58,331 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:15:58,331 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 14:15:58,331 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 14:15:58,331 INFO L87 Difference]: Start difference. First operand 1040 states and 2795 transitions. Second operand 6 states. [2019-12-07 14:15:58,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:15:58,390 INFO L93 Difference]: Finished difference Result 1797 states and 4434 transitions. [2019-12-07 14:15:58,390 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 14:15:58,390 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 59 [2019-12-07 14:15:58,390 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:15:58,391 INFO L225 Difference]: With dead ends: 1797 [2019-12-07 14:15:58,392 INFO L226 Difference]: Without dead ends: 987 [2019-12-07 14:15:58,392 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 14:15:58,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 987 states. [2019-12-07 14:15:58,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 987 to 762. [2019-12-07 14:15:58,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 762 states. [2019-12-07 14:15:58,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 762 states to 762 states and 1791 transitions. [2019-12-07 14:15:58,402 INFO L78 Accepts]: Start accepts. Automaton has 762 states and 1791 transitions. Word has length 59 [2019-12-07 14:15:58,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:15:58,402 INFO L462 AbstractCegarLoop]: Abstraction has 762 states and 1791 transitions. [2019-12-07 14:15:58,402 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 14:15:58,402 INFO L276 IsEmpty]: Start isEmpty. Operand 762 states and 1791 transitions. [2019-12-07 14:15:58,403 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 14:15:58,403 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:15:58,403 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:15:58,404 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:15:58,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:15:58,404 INFO L82 PathProgramCache]: Analyzing trace with hash 1216020614, now seen corresponding path program 2 times [2019-12-07 14:15:58,404 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:15:58,404 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1140117289] [2019-12-07 14:15:58,404 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:15:58,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:15:58,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:15:58,471 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1140117289] [2019-12-07 14:15:58,471 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:15:58,471 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 14:15:58,471 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1491780617] [2019-12-07 14:15:58,472 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:15:58,472 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:15:58,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:15:58,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:15:58,472 INFO L87 Difference]: Start difference. First operand 762 states and 1791 transitions. Second operand 5 states. [2019-12-07 14:15:58,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:15:58,504 INFO L93 Difference]: Finished difference Result 944 states and 2114 transitions. [2019-12-07 14:15:58,504 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:15:58,504 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 59 [2019-12-07 14:15:58,505 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:15:58,505 INFO L225 Difference]: With dead ends: 944 [2019-12-07 14:15:58,505 INFO L226 Difference]: Without dead ends: 223 [2019-12-07 14:15:58,505 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:15:58,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states. [2019-12-07 14:15:58,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 223. [2019-12-07 14:15:58,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 223 states. [2019-12-07 14:15:58,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 223 states to 223 states and 391 transitions. [2019-12-07 14:15:58,507 INFO L78 Accepts]: Start accepts. Automaton has 223 states and 391 transitions. Word has length 59 [2019-12-07 14:15:58,507 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:15:58,507 INFO L462 AbstractCegarLoop]: Abstraction has 223 states and 391 transitions. [2019-12-07 14:15:58,507 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:15:58,507 INFO L276 IsEmpty]: Start isEmpty. Operand 223 states and 391 transitions. [2019-12-07 14:15:58,508 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 14:15:58,508 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:15:58,508 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:15:58,508 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:15:58,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:15:58,508 INFO L82 PathProgramCache]: Analyzing trace with hash 2087557674, now seen corresponding path program 3 times [2019-12-07 14:15:58,508 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:15:58,508 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769580532] [2019-12-07 14:15:58,508 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:15:58,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:15:58,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:15:58,539 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1769580532] [2019-12-07 14:15:58,539 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:15:58,539 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:15:58,540 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1593387931] [2019-12-07 14:15:58,540 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:15:58,540 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:15:58,540 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:15:58,540 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:15:58,540 INFO L87 Difference]: Start difference. First operand 223 states and 391 transitions. Second operand 3 states. [2019-12-07 14:15:58,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:15:58,547 INFO L93 Difference]: Finished difference Result 213 states and 368 transitions. [2019-12-07 14:15:58,548 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:15:58,548 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 59 [2019-12-07 14:15:58,548 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:15:58,548 INFO L225 Difference]: With dead ends: 213 [2019-12-07 14:15:58,548 INFO L226 Difference]: Without dead ends: 213 [2019-12-07 14:15:58,549 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:15:58,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 213 states. [2019-12-07 14:15:58,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 213 to 213. [2019-12-07 14:15:58,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 213 states. [2019-12-07 14:15:58,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 213 states to 213 states and 368 transitions. [2019-12-07 14:15:58,551 INFO L78 Accepts]: Start accepts. Automaton has 213 states and 368 transitions. Word has length 59 [2019-12-07 14:15:58,551 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:15:58,551 INFO L462 AbstractCegarLoop]: Abstraction has 213 states and 368 transitions. [2019-12-07 14:15:58,551 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:15:58,552 INFO L276 IsEmpty]: Start isEmpty. Operand 213 states and 368 transitions. [2019-12-07 14:15:58,552 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-12-07 14:15:58,552 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:15:58,552 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:15:58,552 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:15:58,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:15:58,553 INFO L82 PathProgramCache]: Analyzing trace with hash -524819563, now seen corresponding path program 1 times [2019-12-07 14:15:58,553 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:15:58,553 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522945990] [2019-12-07 14:15:58,553 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:15:58,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 14:15:58,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 14:15:58,634 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 14:15:58,634 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 14:15:58,636 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] ULTIMATE.startENTRY-->L821: Formula: (let ((.cse0 (store |v_#valid_75| 0 0))) (and (= |v_#valid_73| (store .cse0 |v_ULTIMATE.start_main_~#t1541~0.base_24| 1)) (= v_~weak$$choice2~0_146 0) (= v_~z$w_buff0_used~0_885 0) (= v_~z$mem_tmp~0_22 0) (= v_~z$r_buff1_thd0~0_298 0) (= 0 v_~z$r_buff1_thd2~0_83) (= 0 v_~z$r_buff1_thd4~0_140) (= 0 v_~z$r_buff1_thd1~0_83) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t1541~0.base_24|) (= 0 v_~z$flush_delayed~0_36) (= v_~z$r_buff0_thd3~0_92 0) (= |v_#length_29| (store |v_#length_30| |v_ULTIMATE.start_main_~#t1541~0.base_24| 4)) (= v_~z$read_delayed_var~0.offset_7 0) (= 0 |v_ULTIMATE.start_main_~#t1541~0.offset_18|) (< 0 |v_#StackHeapBarrier_18|) (= v_~__unbuffered_p3_EAX~0_100 0) (= v_~z$w_buff0~0_503 0) (= v_~z$w_buff1_used~0_515 0) (= v_~a~0_48 0) (= v_~x~0_57 0) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$read_delayed~0_7 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1541~0.base_24|)) (= v_~z~0_155 0) (= v_~main$tmp_guard1~0_32 0) (= 0 v_~weak$$choice0~0_16) (= v_~__unbuffered_cnt~0_141 0) (= 0 v_~z$r_buff1_thd3~0_146) (= v_~z$w_buff1~0_306 0) (= v_~z$r_buff0_thd0~0_394 0) (= |v_#NULL.offset_5| 0) (= v_~z$r_buff0_thd2~0_32 0) (= (store |v_#memory_int_26| |v_ULTIMATE.start_main_~#t1541~0.base_24| (store (select |v_#memory_int_26| |v_ULTIMATE.start_main_~#t1541~0.base_24|) |v_ULTIMATE.start_main_~#t1541~0.offset_18| 0)) |v_#memory_int_25|) (= v_~main$tmp_guard0~0_22 0) (= 0 v_~z$r_buff0_thd4~0_161) (= v_~y~0_76 0) (= v_~z$r_buff0_thd1~0_32 0) (= 0 |v_#NULL.base_5|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_75|, #memory_int=|v_#memory_int_26|, #length=|v_#length_30|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_59|, ULTIMATE.start_main_~#t1544~0.offset=|v_ULTIMATE.start_main_~#t1544~0.offset_17|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_83, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_41|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_32|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_35|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_30|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_45|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_60|, ~a~0=v_~a~0_48, ULTIMATE.start_main_~#t1544~0.base=|v_ULTIMATE.start_main_~#t1544~0.base_21|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_394, ~z$r_buff0_thd4~0=v_~z$r_buff0_thd4~0_161, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_100, #length=|v_#length_29|, ~z$mem_tmp~0=v_~z$mem_tmp~0_22, ULTIMATE.start_main_~#t1543~0.base=|v_ULTIMATE.start_main_~#t1543~0.base_20|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_48|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_114|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_515, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_191|, ~z$flush_delayed~0=v_~z$flush_delayed~0_36, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_35|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_44|, ~weak$$choice0~0=v_~weak$$choice0~0_16, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_38|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_83, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_10|, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_92, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_141, ~x~0=v_~x~0_57, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_140, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_40|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_57|, ~z$w_buff1~0=v_~z$w_buff1~0_306, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_43|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_31|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_29|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_51|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_44|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_298, ULTIMATE.start_main_~#t1543~0.offset=|v_ULTIMATE.start_main_~#t1543~0.offset_16|, ULTIMATE.start_main_#t~nondet26=|v_ULTIMATE.start_main_#t~nondet26_25|, ULTIMATE.start_main_~#t1542~0.base=|v_ULTIMATE.start_main_~#t1542~0.base_22|, ~y~0=v_~y~0_76, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_32, ULTIMATE.start_main_~#t1542~0.offset=|v_ULTIMATE.start_main_~#t1542~0.offset_17|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_885, ~z$w_buff0~0=v_~z$w_buff0~0_503, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_39|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_25|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_146, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_122|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_44|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_22, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_36|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_35|, ULTIMATE.start_main_~#t1541~0.base=|v_ULTIMATE.start_main_~#t1541~0.base_24|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_31|, ULTIMATE.start_main_~#t1541~0.offset=|v_ULTIMATE.start_main_~#t1541~0.offset_18|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_25|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_9|, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_23|, ~z~0=v_~z~0_155, ~weak$$choice2~0=v_~weak$$choice2~0_146, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_32} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1544~0.offset, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~a~0, ULTIMATE.start_main_~#t1544~0.base, ~z$r_buff0_thd0~0, ~z$r_buff0_thd4~0, ~__unbuffered_p3_EAX~0, #length, ~z$mem_tmp~0, ULTIMATE.start_main_~#t1543~0.base, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ULTIMATE.start_main_#t~nondet15, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~x~0, ~z$r_buff1_thd4~0, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite30, ~z$r_buff1_thd0~0, ULTIMATE.start_main_~#t1543~0.offset, ULTIMATE.start_main_#t~nondet26, ULTIMATE.start_main_~#t1542~0.base, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_~#t1542~0.offset, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_~#t1541~0.base, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_~#t1541~0.offset, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_#t~nondet18, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 14:15:58,637 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [732] [732] L821-1-->L823: Formula: (and (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1542~0.base_10|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1542~0.base_10| 4)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1542~0.base_10| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1542~0.base_10|) |v_ULTIMATE.start_main_~#t1542~0.offset_9| 1)) |v_#memory_int_13|) (= |v_ULTIMATE.start_main_~#t1542~0.offset_9| 0) (= (store |v_#valid_36| |v_ULTIMATE.start_main_~#t1542~0.base_10| 1) |v_#valid_35|) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t1542~0.base_10|)) (not (= |v_ULTIMATE.start_main_~#t1542~0.base_10| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t1542~0.offset=|v_ULTIMATE.start_main_~#t1542~0.offset_9|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1542~0.base=|v_ULTIMATE.start_main_~#t1542~0.base_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1542~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t1542~0.base] because there is no mapped edge [2019-12-07 14:15:58,637 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [753] [753] L823-1-->L825: Formula: (and (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1543~0.base_12|) (not (= 0 |v_ULTIMATE.start_main_~#t1543~0.base_12|)) (= |v_#valid_45| (store |v_#valid_46| |v_ULTIMATE.start_main_~#t1543~0.base_12| 1)) (= 0 (select |v_#valid_46| |v_ULTIMATE.start_main_~#t1543~0.base_12|)) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1543~0.base_12| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1543~0.base_12|) |v_ULTIMATE.start_main_~#t1543~0.offset_10| 2)) |v_#memory_int_17|) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t1543~0.base_12| 4)) (= 0 |v_ULTIMATE.start_main_~#t1543~0.offset_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_~#t1543~0.base=|v_ULTIMATE.start_main_~#t1543~0.base_12|, ULTIMATE.start_main_~#t1543~0.offset=|v_ULTIMATE.start_main_~#t1543~0.offset_10|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_21|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1543~0.base, ULTIMATE.start_main_~#t1543~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length] because there is no mapped edge [2019-12-07 14:15:58,637 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [743] [743] L825-1-->L827: Formula: (and (= 0 (select |v_#valid_40| |v_ULTIMATE.start_main_~#t1544~0.base_11|)) (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t1544~0.base_11| 4)) (= |v_#valid_39| (store |v_#valid_40| |v_ULTIMATE.start_main_~#t1544~0.base_11| 1)) (not (= |v_ULTIMATE.start_main_~#t1544~0.base_11| 0)) (= 0 |v_ULTIMATE.start_main_~#t1544~0.offset_10|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t1544~0.base_11|) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1544~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1544~0.base_11|) |v_ULTIMATE.start_main_~#t1544~0.offset_10| 3)) |v_#memory_int_15|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{ULTIMATE.start_main_~#t1544~0.base=|v_ULTIMATE.start_main_~#t1544~0.base_11|, #StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t1544~0.offset=|v_ULTIMATE.start_main_~#t1544~0.offset_10|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_15|, #length=|v_#length_19|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1544~0.base, ULTIMATE.start_main_~#t1544~0.offset, #valid, #memory_int, #length, ULTIMATE.start_main_#t~nondet17] because there is no mapped edge [2019-12-07 14:15:58,638 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] P3ENTRY-->L4-3: Formula: (and (not (= v_P3Thread1of1ForFork2___VERIFIER_assert_~expression_11 0)) (= v_P3Thread1of1ForFork2_~arg.base_9 |v_P3Thread1of1ForFork2_#in~arg.base_11|) (= v_P3Thread1of1ForFork2___VERIFIER_assert_~expression_11 |v_P3Thread1of1ForFork2___VERIFIER_assert_#in~expression_9|) (= (ite (not (and (not (= (mod v_~z$w_buff0_used~0_218 256) 0)) (not (= (mod v_~z$w_buff1_used~0_99 256) 0)))) 1 0) |v_P3Thread1of1ForFork2___VERIFIER_assert_#in~expression_9|) (= |v_P3Thread1of1ForFork2_#in~arg.offset_11| v_P3Thread1of1ForFork2_~arg.offset_9) (= v_~z$w_buff0_used~0_218 1) (= v_~z$w_buff0~0_48 v_~z$w_buff1~0_32) (= 2 v_~z$w_buff0~0_47) (= v_~z$w_buff0_used~0_219 v_~z$w_buff1_used~0_99)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_219, ~z$w_buff0~0=v_~z$w_buff0~0_48, P3Thread1of1ForFork2_#in~arg.offset=|v_P3Thread1of1ForFork2_#in~arg.offset_11|, P3Thread1of1ForFork2_#in~arg.base=|v_P3Thread1of1ForFork2_#in~arg.base_11|} OutVars{P3Thread1of1ForFork2___VERIFIER_assert_~expression=v_P3Thread1of1ForFork2___VERIFIER_assert_~expression_11, P3Thread1of1ForFork2_~arg.offset=v_P3Thread1of1ForFork2_~arg.offset_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_218, ~z$w_buff0~0=v_~z$w_buff0~0_47, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_99, P3Thread1of1ForFork2_#in~arg.offset=|v_P3Thread1of1ForFork2_#in~arg.offset_11|, ~z$w_buff1~0=v_~z$w_buff1~0_32, P3Thread1of1ForFork2___VERIFIER_assert_#in~expression=|v_P3Thread1of1ForFork2___VERIFIER_assert_#in~expression_9|, P3Thread1of1ForFork2_~arg.base=v_P3Thread1of1ForFork2_~arg.base_9, P3Thread1of1ForFork2_#in~arg.base=|v_P3Thread1of1ForFork2_#in~arg.base_11|} AuxVars[] AssignedVars[P3Thread1of1ForFork2___VERIFIER_assert_~expression, P3Thread1of1ForFork2_~arg.offset, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$w_buff1_used~0, ~z$w_buff1~0, P3Thread1of1ForFork2___VERIFIER_assert_#in~expression, P3Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-12-07 14:15:58,638 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_44 1) (= v_~__unbuffered_cnt~0_102 (+ v_~__unbuffered_cnt~0_103 1)) (= v_P0Thread1of1ForFork3_~arg.base_17 |v_P0Thread1of1ForFork3_#in~arg.base_19|) (= v_~a~0_40 1) (= |v_P0Thread1of1ForFork3_#res.offset_9| 0) (= |v_P0Thread1of1ForFork3_#in~arg.offset_19| v_P0Thread1of1ForFork3_~arg.offset_17) (= 0 |v_P0Thread1of1ForFork3_#res.base_9|)) InVars {P0Thread1of1ForFork3_#in~arg.offset=|v_P0Thread1of1ForFork3_#in~arg.offset_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_103, P0Thread1of1ForFork3_#in~arg.base=|v_P0Thread1of1ForFork3_#in~arg.base_19|} OutVars{~a~0=v_~a~0_40, P0Thread1of1ForFork3_#in~arg.offset=|v_P0Thread1of1ForFork3_#in~arg.offset_19|, P0Thread1of1ForFork3_~arg.base=v_P0Thread1of1ForFork3_~arg.base_17, P0Thread1of1ForFork3_#res.base=|v_P0Thread1of1ForFork3_#res.base_9|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_102, P0Thread1of1ForFork3_#res.offset=|v_P0Thread1of1ForFork3_#res.offset_9|, P0Thread1of1ForFork3_~arg.offset=v_P0Thread1of1ForFork3_~arg.offset_17, P0Thread1of1ForFork3_#in~arg.base=|v_P0Thread1of1ForFork3_#in~arg.base_19|, ~x~0=v_~x~0_44} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork3_~arg.base, P0Thread1of1ForFork3_#res.base, ~__unbuffered_cnt~0, P0Thread1of1ForFork3_#res.offset, P0Thread1of1ForFork3_~arg.offset, ~x~0] because there is no mapped edge [2019-12-07 14:15:58,638 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [746] [746] P1ENTRY-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork0_#res.offset_3|) (= v_~x~0_39 2) (= v_~__unbuffered_cnt~0_78 (+ v_~__unbuffered_cnt~0_79 1)) (= v_~y~0_50 1) (= 0 |v_P1Thread1of1ForFork0_#res.base_3|) (= |v_P1Thread1of1ForFork0_#in~arg.base_10| v_P1Thread1of1ForFork0_~arg.base_8) (= |v_P1Thread1of1ForFork0_#in~arg.offset_10| v_P1Thread1of1ForFork0_~arg.offset_8)) InVars {P1Thread1of1ForFork0_#in~arg.base=|v_P1Thread1of1ForFork0_#in~arg.base_10|, P1Thread1of1ForFork0_#in~arg.offset=|v_P1Thread1of1ForFork0_#in~arg.offset_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_79} OutVars{P1Thread1of1ForFork0_~arg.offset=v_P1Thread1of1ForFork0_~arg.offset_8, P1Thread1of1ForFork0_~arg.base=v_P1Thread1of1ForFork0_~arg.base_8, P1Thread1of1ForFork0_#in~arg.base=|v_P1Thread1of1ForFork0_#in~arg.base_10|, P1Thread1of1ForFork0_#in~arg.offset=|v_P1Thread1of1ForFork0_#in~arg.offset_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_78, P1Thread1of1ForFork0_#res.offset=|v_P1Thread1of1ForFork0_#res.offset_3|, ~y~0=v_~y~0_50, P1Thread1of1ForFork0_#res.base=|v_P1Thread1of1ForFork0_#res.base_3|, ~x~0=v_~x~0_39} AuxVars[] AssignedVars[P1Thread1of1ForFork0_~arg.offset, P1Thread1of1ForFork0_~arg.base, ~__unbuffered_cnt~0, P1Thread1of1ForFork0_#res.offset, ~y~0, P1Thread1of1ForFork0_#res.base, ~x~0] because there is no mapped edge [2019-12-07 14:15:58,639 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L768-2-->L768-5: Formula: (let ((.cse1 (= |P2Thread1of1ForFork1_#t~ite3_Out486558540| |P2Thread1of1ForFork1_#t~ite4_Out486558540|)) (.cse2 (= (mod ~z$r_buff1_thd3~0_In486558540 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In486558540 256)))) (or (and (not .cse0) (= |P2Thread1of1ForFork1_#t~ite3_Out486558540| ~z$w_buff1~0_In486558540) .cse1 (not .cse2)) (and (= |P2Thread1of1ForFork1_#t~ite3_Out486558540| ~z~0_In486558540) .cse1 (or .cse2 .cse0)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In486558540, ~z$w_buff1_used~0=~z$w_buff1_used~0_In486558540, ~z$w_buff1~0=~z$w_buff1~0_In486558540, ~z~0=~z~0_In486558540} OutVars{P2Thread1of1ForFork1_#t~ite4=|P2Thread1of1ForFork1_#t~ite4_Out486558540|, P2Thread1of1ForFork1_#t~ite3=|P2Thread1of1ForFork1_#t~ite3_Out486558540|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In486558540, ~z$w_buff1_used~0=~z$w_buff1_used~0_In486558540, ~z$w_buff1~0=~z$w_buff1~0_In486558540, ~z~0=~z~0_In486558540} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite4, P2Thread1of1ForFork1_#t~ite3] because there is no mapped edge [2019-12-07 14:15:58,639 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L769-->L769-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-510534579 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd3~0_In-510534579 256) 0))) (or (and (= ~z$w_buff0_used~0_In-510534579 |P2Thread1of1ForFork1_#t~ite5_Out-510534579|) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |P2Thread1of1ForFork1_#t~ite5_Out-510534579| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-510534579, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-510534579} OutVars{P2Thread1of1ForFork1_#t~ite5=|P2Thread1of1ForFork1_#t~ite5_Out-510534579|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-510534579, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-510534579} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite5] because there is no mapped edge [2019-12-07 14:15:58,640 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] L770-->L770-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-517358891 256))) (.cse1 (= (mod ~z$r_buff0_thd3~0_In-517358891 256) 0)) (.cse2 (= (mod ~z$r_buff1_thd3~0_In-517358891 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In-517358891 256)))) (or (and (= |P2Thread1of1ForFork1_#t~ite6_Out-517358891| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork1_#t~ite6_Out-517358891| ~z$w_buff1_used~0_In-517358891)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-517358891, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-517358891, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-517358891, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-517358891} OutVars{P2Thread1of1ForFork1_#t~ite6=|P2Thread1of1ForFork1_#t~ite6_Out-517358891|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-517358891, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-517358891, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-517358891, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-517358891} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite6] because there is no mapped edge [2019-12-07 14:15:58,640 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [710] [710] L771-->L771-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In2099053648 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In2099053648 256)))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork1_#t~ite7_Out2099053648| ~z$r_buff0_thd3~0_In2099053648)) (and (= |P2Thread1of1ForFork1_#t~ite7_Out2099053648| 0) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In2099053648, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In2099053648} OutVars{P2Thread1of1ForFork1_#t~ite7=|P2Thread1of1ForFork1_#t~ite7_Out2099053648|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2099053648, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In2099053648} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite7] because there is no mapped edge [2019-12-07 14:15:58,641 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L772-->L772-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd3~0_In-163911467 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-163911467 256))) (.cse1 (= (mod ~z$r_buff1_thd3~0_In-163911467 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-163911467 256)))) (or (and (= |P2Thread1of1ForFork1_#t~ite8_Out-163911467| ~z$r_buff1_thd3~0_In-163911467) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork1_#t~ite8_Out-163911467|) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-163911467, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-163911467, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-163911467, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-163911467} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-163911467, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-163911467, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-163911467, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-163911467, P2Thread1of1ForFork1_#t~ite8=|P2Thread1of1ForFork1_#t~ite8_Out-163911467|} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 14:15:58,641 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [752] [752] L772-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork1_#res.offset_3|) (= v_~z$r_buff1_thd3~0_127 |v_P2Thread1of1ForFork1_#t~ite8_44|) (= v_~__unbuffered_cnt~0_100 (+ v_~__unbuffered_cnt~0_101 1)) (= 0 |v_P2Thread1of1ForFork1_#res.base_3|)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_101, P2Thread1of1ForFork1_#t~ite8=|v_P2Thread1of1ForFork1_#t~ite8_44|} OutVars{P2Thread1of1ForFork1_#res.base=|v_P2Thread1of1ForFork1_#res.base_3|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_127, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_100, P2Thread1of1ForFork1_#res.offset=|v_P2Thread1of1ForFork1_#res.offset_3|, P2Thread1of1ForFork1_#t~ite8=|v_P2Thread1of1ForFork1_#t~ite8_43|} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#res.base, ~z$r_buff1_thd3~0, ~__unbuffered_cnt~0, P2Thread1of1ForFork1_#res.offset, P2Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 14:15:58,641 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [727] [727] L799-->L799-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-930988101 256) 0)) (.cse1 (= (mod ~z$r_buff0_thd4~0_In-930988101 256) 0))) (or (and (= |P3Thread1of1ForFork2_#t~ite11_Out-930988101| ~z$w_buff0_used~0_In-930988101) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |P3Thread1of1ForFork2_#t~ite11_Out-930988101| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-930988101, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-930988101} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-930988101, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-930988101, P3Thread1of1ForFork2_#t~ite11=|P3Thread1of1ForFork2_#t~ite11_Out-930988101|} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-12-07 14:15:58,642 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L800-->L800-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd4~0_In2122144501 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In2122144501 256))) (.cse1 (= (mod ~z$r_buff1_thd4~0_In2122144501 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In2122144501 256)))) (or (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In2122144501 |P3Thread1of1ForFork2_#t~ite12_Out2122144501|) (or .cse2 .cse3)) (and (= 0 |P3Thread1of1ForFork2_#t~ite12_Out2122144501|) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In2122144501, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2122144501, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In2122144501, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2122144501} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In2122144501, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2122144501, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In2122144501, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2122144501, P3Thread1of1ForFork2_#t~ite12=|P3Thread1of1ForFork2_#t~ite12_Out2122144501|} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite12] because there is no mapped edge [2019-12-07 14:15:58,642 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L801-->L802: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd4~0_In-153120946 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-153120946 256))) (.cse2 (= ~z$r_buff0_thd4~0_Out-153120946 ~z$r_buff0_thd4~0_In-153120946))) (or (and (= ~z$r_buff0_thd4~0_Out-153120946 0) (not .cse0) (not .cse1)) (and .cse1 .cse2) (and .cse0 .cse2))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-153120946, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-153120946} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-153120946, P3Thread1of1ForFork2_#t~ite13=|P3Thread1of1ForFork2_#t~ite13_Out-153120946|, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out-153120946} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite13, ~z$r_buff0_thd4~0] because there is no mapped edge [2019-12-07 14:15:58,642 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L802-->L802-2: Formula: (let ((.cse2 (= 0 (mod ~z$r_buff0_thd4~0_In230326796 256))) (.cse3 (= (mod ~z$w_buff0_used~0_In230326796 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In230326796 256))) (.cse0 (= (mod ~z$r_buff1_thd4~0_In230326796 256) 0))) (or (and (or .cse0 .cse1) (= |P3Thread1of1ForFork2_#t~ite14_Out230326796| ~z$r_buff1_thd4~0_In230326796) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |P3Thread1of1ForFork2_#t~ite14_Out230326796| 0)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In230326796, ~z$w_buff0_used~0=~z$w_buff0_used~0_In230326796, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In230326796, ~z$w_buff1_used~0=~z$w_buff1_used~0_In230326796} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In230326796, ~z$w_buff0_used~0=~z$w_buff0_used~0_In230326796, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In230326796, ~z$w_buff1_used~0=~z$w_buff1_used~0_In230326796, P3Thread1of1ForFork2_#t~ite14=|P3Thread1of1ForFork2_#t~ite14_Out230326796|} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite14] because there is no mapped edge [2019-12-07 14:15:58,642 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L802-2-->P3EXIT: Formula: (and (= |v_P3Thread1of1ForFork2_#t~ite14_54| v_~z$r_buff1_thd4~0_130) (= 0 |v_P3Thread1of1ForFork2_#res.base_3|) (= v_~__unbuffered_cnt~0_126 (+ v_~__unbuffered_cnt~0_127 1)) (= 0 |v_P3Thread1of1ForFork2_#res.offset_3|)) InVars {P3Thread1of1ForFork2_#t~ite14=|v_P3Thread1of1ForFork2_#t~ite14_54|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_127} OutVars{P3Thread1of1ForFork2_#res.base=|v_P3Thread1of1ForFork2_#res.base_3|, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_130, P3Thread1of1ForFork2_#t~ite14=|v_P3Thread1of1ForFork2_#t~ite14_53|, P3Thread1of1ForFork2_#res.offset=|v_P3Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_126} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#res.base, ~z$r_buff1_thd4~0, P3Thread1of1ForFork2_#t~ite14, P3Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 14:15:58,642 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [673] [673] L827-1-->L833: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= (ite (= 4 v_~__unbuffered_cnt~0_21) 1 0) 0) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_21} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_21, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_6|} AuxVars[] AssignedVars[~main$tmp_guard0~0, ULTIMATE.start_main_#t~nondet18] because there is no mapped edge [2019-12-07 14:15:58,643 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L833-2-->L833-4: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd0~0_In432049801 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In432049801 256) 0))) (or (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In432049801 |ULTIMATE.start_main_#t~ite19_Out432049801|)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite19_Out432049801| ~z~0_In432049801)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In432049801, ~z$w_buff1_used~0=~z$w_buff1_used~0_In432049801, ~z$w_buff1~0=~z$w_buff1~0_In432049801, ~z~0=~z~0_In432049801} OutVars{ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out432049801|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In432049801, ~z$w_buff1_used~0=~z$w_buff1_used~0_In432049801, ~z$w_buff1~0=~z$w_buff1~0_In432049801, ~z~0=~z~0_In432049801} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 14:15:58,643 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [658] [658] L833-4-->L834: Formula: (= v_~z~0_31 |v_ULTIMATE.start_main_#t~ite19_8|) InVars {ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_8|} OutVars{ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_7|, ~z~0=v_~z~0_31, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19, ~z~0, ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 14:15:58,643 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L834-->L834-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In554615859 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd0~0_In554615859 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite21_Out554615859|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite21_Out554615859| ~z$w_buff0_used~0_In554615859)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In554615859, ~z$w_buff0_used~0=~z$w_buff0_used~0_In554615859} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In554615859, ~z$w_buff0_used~0=~z$w_buff0_used~0_In554615859, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out554615859|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 14:15:58,643 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [725] [725] L835-->L835-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In1738539894 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In1738539894 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In1738539894 256))) (.cse2 (= (mod ~z$r_buff1_thd0~0_In1738539894 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite22_Out1738539894| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |ULTIMATE.start_main_#t~ite22_Out1738539894| ~z$w_buff1_used~0_In1738539894) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1738539894, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1738539894, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1738539894, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1738539894} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1738539894, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1738539894, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1738539894, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1738539894, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1738539894|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 14:15:58,644 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [718] [718] L836-->L836-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-1571101226 256) 0)) (.cse1 (= (mod ~z$r_buff0_thd0~0_In-1571101226 256) 0))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite23_Out-1571101226| 0)) (and (or .cse0 .cse1) (= ~z$r_buff0_thd0~0_In-1571101226 |ULTIMATE.start_main_#t~ite23_Out-1571101226|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1571101226, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1571101226} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1571101226, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1571101226, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-1571101226|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 14:15:58,644 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [711] [711] L837-->L837-2: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In1663486002 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In1663486002 256) 0)) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In1663486002 256))) (.cse3 (= (mod ~z$r_buff0_thd0~0_In1663486002 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite24_Out1663486002| 0)) (and (= |ULTIMATE.start_main_#t~ite24_Out1663486002| ~z$r_buff1_thd0~0_In1663486002) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1663486002, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1663486002, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1663486002, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1663486002} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1663486002, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1663486002, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1663486002, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out1663486002|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1663486002} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 14:15:58,647 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L849-->L850: Formula: (and (= v_~z$r_buff0_thd0~0_119 v_~z$r_buff0_thd0~0_120) (not (= 0 (mod v_~weak$$choice2~0_29 256)))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_120, ~weak$$choice2~0=v_~weak$$choice2~0_29} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_8|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_119, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_9|, ~weak$$choice2~0=v_~weak$$choice2~0_29, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 14:15:58,647 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L850-->L850-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-673966695 256)))) (or (and (= |ULTIMATE.start_main_#t~ite45_Out-673966695| ~z$r_buff1_thd0~0_In-673966695) .cse0 (= |ULTIMATE.start_main_#t~ite45_Out-673966695| |ULTIMATE.start_main_#t~ite46_Out-673966695|) (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In-673966695 256)))) (or (= 0 (mod ~z$w_buff0_used~0_In-673966695 256)) (and (= (mod ~z$w_buff1_used~0_In-673966695 256) 0) .cse1) (and .cse1 (= (mod ~z$r_buff1_thd0~0_In-673966695 256) 0))))) (and (= |ULTIMATE.start_main_#t~ite46_Out-673966695| ~z$r_buff1_thd0~0_In-673966695) (= |ULTIMATE.start_main_#t~ite45_In-673966695| |ULTIMATE.start_main_#t~ite45_Out-673966695|) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-673966695, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-673966695, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-673966695, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-673966695, ~weak$$choice2~0=~weak$$choice2~0_In-673966695, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In-673966695|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-673966695, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-673966695, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-673966695, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-673966695, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out-673966695|, ~weak$$choice2~0=~weak$$choice2~0_In-673966695, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out-673966695|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45] because there is no mapped edge [2019-12-07 14:15:58,647 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L852-->L855-1: Formula: (and (= v_~z$mem_tmp~0_13 v_~z~0_120) (= 0 v_~z$flush_delayed~0_24) (= (mod v_~main$tmp_guard1~0_23 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (not (= 0 (mod v_~z$flush_delayed~0_25 256)))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_13, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~z$flush_delayed~0=v_~z$flush_delayed~0_25} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_13, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~z$flush_delayed~0=v_~z$flush_delayed~0_24, ~z~0=v_~z~0_120, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 14:15:58,647 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [729] [729] L855-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 14:15:58,709 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 02:15:58 BasicIcfg [2019-12-07 14:15:58,709 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 14:15:58,709 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 14:15:58,709 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 14:15:58,709 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 14:15:58,710 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 02:15:42" (3/4) ... [2019-12-07 14:15:58,711 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 14:15:58,712 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] ULTIMATE.startENTRY-->L821: Formula: (let ((.cse0 (store |v_#valid_75| 0 0))) (and (= |v_#valid_73| (store .cse0 |v_ULTIMATE.start_main_~#t1541~0.base_24| 1)) (= v_~weak$$choice2~0_146 0) (= v_~z$w_buff0_used~0_885 0) (= v_~z$mem_tmp~0_22 0) (= v_~z$r_buff1_thd0~0_298 0) (= 0 v_~z$r_buff1_thd2~0_83) (= 0 v_~z$r_buff1_thd4~0_140) (= 0 v_~z$r_buff1_thd1~0_83) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t1541~0.base_24|) (= 0 v_~z$flush_delayed~0_36) (= v_~z$r_buff0_thd3~0_92 0) (= |v_#length_29| (store |v_#length_30| |v_ULTIMATE.start_main_~#t1541~0.base_24| 4)) (= v_~z$read_delayed_var~0.offset_7 0) (= 0 |v_ULTIMATE.start_main_~#t1541~0.offset_18|) (< 0 |v_#StackHeapBarrier_18|) (= v_~__unbuffered_p3_EAX~0_100 0) (= v_~z$w_buff0~0_503 0) (= v_~z$w_buff1_used~0_515 0) (= v_~a~0_48 0) (= v_~x~0_57 0) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$read_delayed~0_7 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1541~0.base_24|)) (= v_~z~0_155 0) (= v_~main$tmp_guard1~0_32 0) (= 0 v_~weak$$choice0~0_16) (= v_~__unbuffered_cnt~0_141 0) (= 0 v_~z$r_buff1_thd3~0_146) (= v_~z$w_buff1~0_306 0) (= v_~z$r_buff0_thd0~0_394 0) (= |v_#NULL.offset_5| 0) (= v_~z$r_buff0_thd2~0_32 0) (= (store |v_#memory_int_26| |v_ULTIMATE.start_main_~#t1541~0.base_24| (store (select |v_#memory_int_26| |v_ULTIMATE.start_main_~#t1541~0.base_24|) |v_ULTIMATE.start_main_~#t1541~0.offset_18| 0)) |v_#memory_int_25|) (= v_~main$tmp_guard0~0_22 0) (= 0 v_~z$r_buff0_thd4~0_161) (= v_~y~0_76 0) (= v_~z$r_buff0_thd1~0_32 0) (= 0 |v_#NULL.base_5|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_75|, #memory_int=|v_#memory_int_26|, #length=|v_#length_30|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_59|, ULTIMATE.start_main_~#t1544~0.offset=|v_ULTIMATE.start_main_~#t1544~0.offset_17|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_83, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_41|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_32|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_35|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_30|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_45|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_60|, ~a~0=v_~a~0_48, ULTIMATE.start_main_~#t1544~0.base=|v_ULTIMATE.start_main_~#t1544~0.base_21|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_394, ~z$r_buff0_thd4~0=v_~z$r_buff0_thd4~0_161, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_100, #length=|v_#length_29|, ~z$mem_tmp~0=v_~z$mem_tmp~0_22, ULTIMATE.start_main_~#t1543~0.base=|v_ULTIMATE.start_main_~#t1543~0.base_20|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_48|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_114|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_515, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_191|, ~z$flush_delayed~0=v_~z$flush_delayed~0_36, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_35|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_44|, ~weak$$choice0~0=v_~weak$$choice0~0_16, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_38|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_83, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_10|, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_92, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_141, ~x~0=v_~x~0_57, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_140, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_40|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_57|, ~z$w_buff1~0=v_~z$w_buff1~0_306, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_43|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_31|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_29|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_51|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_44|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_298, ULTIMATE.start_main_~#t1543~0.offset=|v_ULTIMATE.start_main_~#t1543~0.offset_16|, ULTIMATE.start_main_#t~nondet26=|v_ULTIMATE.start_main_#t~nondet26_25|, ULTIMATE.start_main_~#t1542~0.base=|v_ULTIMATE.start_main_~#t1542~0.base_22|, ~y~0=v_~y~0_76, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_32, ULTIMATE.start_main_~#t1542~0.offset=|v_ULTIMATE.start_main_~#t1542~0.offset_17|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_885, ~z$w_buff0~0=v_~z$w_buff0~0_503, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_39|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_25|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_146, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_122|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_44|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_22, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_36|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_35|, ULTIMATE.start_main_~#t1541~0.base=|v_ULTIMATE.start_main_~#t1541~0.base_24|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_31|, ULTIMATE.start_main_~#t1541~0.offset=|v_ULTIMATE.start_main_~#t1541~0.offset_18|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_25|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_9|, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_23|, ~z~0=v_~z~0_155, ~weak$$choice2~0=v_~weak$$choice2~0_146, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_32} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1544~0.offset, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~a~0, ULTIMATE.start_main_~#t1544~0.base, ~z$r_buff0_thd0~0, ~z$r_buff0_thd4~0, ~__unbuffered_p3_EAX~0, #length, ~z$mem_tmp~0, ULTIMATE.start_main_~#t1543~0.base, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ULTIMATE.start_main_#t~nondet15, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~x~0, ~z$r_buff1_thd4~0, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite30, ~z$r_buff1_thd0~0, ULTIMATE.start_main_~#t1543~0.offset, ULTIMATE.start_main_#t~nondet26, ULTIMATE.start_main_~#t1542~0.base, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_~#t1542~0.offset, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_~#t1541~0.base, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_~#t1541~0.offset, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_#t~nondet18, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 14:15:58,712 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [732] [732] L821-1-->L823: Formula: (and (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1542~0.base_10|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1542~0.base_10| 4)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1542~0.base_10| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1542~0.base_10|) |v_ULTIMATE.start_main_~#t1542~0.offset_9| 1)) |v_#memory_int_13|) (= |v_ULTIMATE.start_main_~#t1542~0.offset_9| 0) (= (store |v_#valid_36| |v_ULTIMATE.start_main_~#t1542~0.base_10| 1) |v_#valid_35|) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t1542~0.base_10|)) (not (= |v_ULTIMATE.start_main_~#t1542~0.base_10| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t1542~0.offset=|v_ULTIMATE.start_main_~#t1542~0.offset_9|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1542~0.base=|v_ULTIMATE.start_main_~#t1542~0.base_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1542~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t1542~0.base] because there is no mapped edge [2019-12-07 14:15:58,712 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [753] [753] L823-1-->L825: Formula: (and (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1543~0.base_12|) (not (= 0 |v_ULTIMATE.start_main_~#t1543~0.base_12|)) (= |v_#valid_45| (store |v_#valid_46| |v_ULTIMATE.start_main_~#t1543~0.base_12| 1)) (= 0 (select |v_#valid_46| |v_ULTIMATE.start_main_~#t1543~0.base_12|)) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1543~0.base_12| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1543~0.base_12|) |v_ULTIMATE.start_main_~#t1543~0.offset_10| 2)) |v_#memory_int_17|) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t1543~0.base_12| 4)) (= 0 |v_ULTIMATE.start_main_~#t1543~0.offset_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_~#t1543~0.base=|v_ULTIMATE.start_main_~#t1543~0.base_12|, ULTIMATE.start_main_~#t1543~0.offset=|v_ULTIMATE.start_main_~#t1543~0.offset_10|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_21|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1543~0.base, ULTIMATE.start_main_~#t1543~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length] because there is no mapped edge [2019-12-07 14:15:58,713 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [743] [743] L825-1-->L827: Formula: (and (= 0 (select |v_#valid_40| |v_ULTIMATE.start_main_~#t1544~0.base_11|)) (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t1544~0.base_11| 4)) (= |v_#valid_39| (store |v_#valid_40| |v_ULTIMATE.start_main_~#t1544~0.base_11| 1)) (not (= |v_ULTIMATE.start_main_~#t1544~0.base_11| 0)) (= 0 |v_ULTIMATE.start_main_~#t1544~0.offset_10|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t1544~0.base_11|) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1544~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1544~0.base_11|) |v_ULTIMATE.start_main_~#t1544~0.offset_10| 3)) |v_#memory_int_15|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{ULTIMATE.start_main_~#t1544~0.base=|v_ULTIMATE.start_main_~#t1544~0.base_11|, #StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t1544~0.offset=|v_ULTIMATE.start_main_~#t1544~0.offset_10|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_15|, #length=|v_#length_19|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1544~0.base, ULTIMATE.start_main_~#t1544~0.offset, #valid, #memory_int, #length, ULTIMATE.start_main_#t~nondet17] because there is no mapped edge [2019-12-07 14:15:58,713 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] P3ENTRY-->L4-3: Formula: (and (not (= v_P3Thread1of1ForFork2___VERIFIER_assert_~expression_11 0)) (= v_P3Thread1of1ForFork2_~arg.base_9 |v_P3Thread1of1ForFork2_#in~arg.base_11|) (= v_P3Thread1of1ForFork2___VERIFIER_assert_~expression_11 |v_P3Thread1of1ForFork2___VERIFIER_assert_#in~expression_9|) (= (ite (not (and (not (= (mod v_~z$w_buff0_used~0_218 256) 0)) (not (= (mod v_~z$w_buff1_used~0_99 256) 0)))) 1 0) |v_P3Thread1of1ForFork2___VERIFIER_assert_#in~expression_9|) (= |v_P3Thread1of1ForFork2_#in~arg.offset_11| v_P3Thread1of1ForFork2_~arg.offset_9) (= v_~z$w_buff0_used~0_218 1) (= v_~z$w_buff0~0_48 v_~z$w_buff1~0_32) (= 2 v_~z$w_buff0~0_47) (= v_~z$w_buff0_used~0_219 v_~z$w_buff1_used~0_99)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_219, ~z$w_buff0~0=v_~z$w_buff0~0_48, P3Thread1of1ForFork2_#in~arg.offset=|v_P3Thread1of1ForFork2_#in~arg.offset_11|, P3Thread1of1ForFork2_#in~arg.base=|v_P3Thread1of1ForFork2_#in~arg.base_11|} OutVars{P3Thread1of1ForFork2___VERIFIER_assert_~expression=v_P3Thread1of1ForFork2___VERIFIER_assert_~expression_11, P3Thread1of1ForFork2_~arg.offset=v_P3Thread1of1ForFork2_~arg.offset_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_218, ~z$w_buff0~0=v_~z$w_buff0~0_47, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_99, P3Thread1of1ForFork2_#in~arg.offset=|v_P3Thread1of1ForFork2_#in~arg.offset_11|, ~z$w_buff1~0=v_~z$w_buff1~0_32, P3Thread1of1ForFork2___VERIFIER_assert_#in~expression=|v_P3Thread1of1ForFork2___VERIFIER_assert_#in~expression_9|, P3Thread1of1ForFork2_~arg.base=v_P3Thread1of1ForFork2_~arg.base_9, P3Thread1of1ForFork2_#in~arg.base=|v_P3Thread1of1ForFork2_#in~arg.base_11|} AuxVars[] AssignedVars[P3Thread1of1ForFork2___VERIFIER_assert_~expression, P3Thread1of1ForFork2_~arg.offset, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$w_buff1_used~0, ~z$w_buff1~0, P3Thread1of1ForFork2___VERIFIER_assert_#in~expression, P3Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-12-07 14:15:58,713 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_44 1) (= v_~__unbuffered_cnt~0_102 (+ v_~__unbuffered_cnt~0_103 1)) (= v_P0Thread1of1ForFork3_~arg.base_17 |v_P0Thread1of1ForFork3_#in~arg.base_19|) (= v_~a~0_40 1) (= |v_P0Thread1of1ForFork3_#res.offset_9| 0) (= |v_P0Thread1of1ForFork3_#in~arg.offset_19| v_P0Thread1of1ForFork3_~arg.offset_17) (= 0 |v_P0Thread1of1ForFork3_#res.base_9|)) InVars {P0Thread1of1ForFork3_#in~arg.offset=|v_P0Thread1of1ForFork3_#in~arg.offset_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_103, P0Thread1of1ForFork3_#in~arg.base=|v_P0Thread1of1ForFork3_#in~arg.base_19|} OutVars{~a~0=v_~a~0_40, P0Thread1of1ForFork3_#in~arg.offset=|v_P0Thread1of1ForFork3_#in~arg.offset_19|, P0Thread1of1ForFork3_~arg.base=v_P0Thread1of1ForFork3_~arg.base_17, P0Thread1of1ForFork3_#res.base=|v_P0Thread1of1ForFork3_#res.base_9|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_102, P0Thread1of1ForFork3_#res.offset=|v_P0Thread1of1ForFork3_#res.offset_9|, P0Thread1of1ForFork3_~arg.offset=v_P0Thread1of1ForFork3_~arg.offset_17, P0Thread1of1ForFork3_#in~arg.base=|v_P0Thread1of1ForFork3_#in~arg.base_19|, ~x~0=v_~x~0_44} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork3_~arg.base, P0Thread1of1ForFork3_#res.base, ~__unbuffered_cnt~0, P0Thread1of1ForFork3_#res.offset, P0Thread1of1ForFork3_~arg.offset, ~x~0] because there is no mapped edge [2019-12-07 14:15:58,713 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [746] [746] P1ENTRY-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork0_#res.offset_3|) (= v_~x~0_39 2) (= v_~__unbuffered_cnt~0_78 (+ v_~__unbuffered_cnt~0_79 1)) (= v_~y~0_50 1) (= 0 |v_P1Thread1of1ForFork0_#res.base_3|) (= |v_P1Thread1of1ForFork0_#in~arg.base_10| v_P1Thread1of1ForFork0_~arg.base_8) (= |v_P1Thread1of1ForFork0_#in~arg.offset_10| v_P1Thread1of1ForFork0_~arg.offset_8)) InVars {P1Thread1of1ForFork0_#in~arg.base=|v_P1Thread1of1ForFork0_#in~arg.base_10|, P1Thread1of1ForFork0_#in~arg.offset=|v_P1Thread1of1ForFork0_#in~arg.offset_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_79} OutVars{P1Thread1of1ForFork0_~arg.offset=v_P1Thread1of1ForFork0_~arg.offset_8, P1Thread1of1ForFork0_~arg.base=v_P1Thread1of1ForFork0_~arg.base_8, P1Thread1of1ForFork0_#in~arg.base=|v_P1Thread1of1ForFork0_#in~arg.base_10|, P1Thread1of1ForFork0_#in~arg.offset=|v_P1Thread1of1ForFork0_#in~arg.offset_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_78, P1Thread1of1ForFork0_#res.offset=|v_P1Thread1of1ForFork0_#res.offset_3|, ~y~0=v_~y~0_50, P1Thread1of1ForFork0_#res.base=|v_P1Thread1of1ForFork0_#res.base_3|, ~x~0=v_~x~0_39} AuxVars[] AssignedVars[P1Thread1of1ForFork0_~arg.offset, P1Thread1of1ForFork0_~arg.base, ~__unbuffered_cnt~0, P1Thread1of1ForFork0_#res.offset, ~y~0, P1Thread1of1ForFork0_#res.base, ~x~0] because there is no mapped edge [2019-12-07 14:15:58,714 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L768-2-->L768-5: Formula: (let ((.cse1 (= |P2Thread1of1ForFork1_#t~ite3_Out486558540| |P2Thread1of1ForFork1_#t~ite4_Out486558540|)) (.cse2 (= (mod ~z$r_buff1_thd3~0_In486558540 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In486558540 256)))) (or (and (not .cse0) (= |P2Thread1of1ForFork1_#t~ite3_Out486558540| ~z$w_buff1~0_In486558540) .cse1 (not .cse2)) (and (= |P2Thread1of1ForFork1_#t~ite3_Out486558540| ~z~0_In486558540) .cse1 (or .cse2 .cse0)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In486558540, ~z$w_buff1_used~0=~z$w_buff1_used~0_In486558540, ~z$w_buff1~0=~z$w_buff1~0_In486558540, ~z~0=~z~0_In486558540} OutVars{P2Thread1of1ForFork1_#t~ite4=|P2Thread1of1ForFork1_#t~ite4_Out486558540|, P2Thread1of1ForFork1_#t~ite3=|P2Thread1of1ForFork1_#t~ite3_Out486558540|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In486558540, ~z$w_buff1_used~0=~z$w_buff1_used~0_In486558540, ~z$w_buff1~0=~z$w_buff1~0_In486558540, ~z~0=~z~0_In486558540} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite4, P2Thread1of1ForFork1_#t~ite3] because there is no mapped edge [2019-12-07 14:15:58,714 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L769-->L769-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-510534579 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd3~0_In-510534579 256) 0))) (or (and (= ~z$w_buff0_used~0_In-510534579 |P2Thread1of1ForFork1_#t~ite5_Out-510534579|) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |P2Thread1of1ForFork1_#t~ite5_Out-510534579| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-510534579, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-510534579} OutVars{P2Thread1of1ForFork1_#t~ite5=|P2Thread1of1ForFork1_#t~ite5_Out-510534579|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-510534579, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-510534579} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite5] because there is no mapped edge [2019-12-07 14:15:58,715 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] L770-->L770-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-517358891 256))) (.cse1 (= (mod ~z$r_buff0_thd3~0_In-517358891 256) 0)) (.cse2 (= (mod ~z$r_buff1_thd3~0_In-517358891 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In-517358891 256)))) (or (and (= |P2Thread1of1ForFork1_#t~ite6_Out-517358891| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork1_#t~ite6_Out-517358891| ~z$w_buff1_used~0_In-517358891)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-517358891, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-517358891, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-517358891, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-517358891} OutVars{P2Thread1of1ForFork1_#t~ite6=|P2Thread1of1ForFork1_#t~ite6_Out-517358891|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-517358891, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-517358891, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-517358891, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-517358891} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite6] because there is no mapped edge [2019-12-07 14:15:58,715 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [710] [710] L771-->L771-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In2099053648 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In2099053648 256)))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork1_#t~ite7_Out2099053648| ~z$r_buff0_thd3~0_In2099053648)) (and (= |P2Thread1of1ForFork1_#t~ite7_Out2099053648| 0) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In2099053648, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In2099053648} OutVars{P2Thread1of1ForFork1_#t~ite7=|P2Thread1of1ForFork1_#t~ite7_Out2099053648|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2099053648, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In2099053648} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite7] because there is no mapped edge [2019-12-07 14:15:58,715 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L772-->L772-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd3~0_In-163911467 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-163911467 256))) (.cse1 (= (mod ~z$r_buff1_thd3~0_In-163911467 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-163911467 256)))) (or (and (= |P2Thread1of1ForFork1_#t~ite8_Out-163911467| ~z$r_buff1_thd3~0_In-163911467) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork1_#t~ite8_Out-163911467|) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-163911467, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-163911467, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-163911467, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-163911467} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-163911467, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-163911467, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-163911467, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-163911467, P2Thread1of1ForFork1_#t~ite8=|P2Thread1of1ForFork1_#t~ite8_Out-163911467|} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 14:15:58,716 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [752] [752] L772-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork1_#res.offset_3|) (= v_~z$r_buff1_thd3~0_127 |v_P2Thread1of1ForFork1_#t~ite8_44|) (= v_~__unbuffered_cnt~0_100 (+ v_~__unbuffered_cnt~0_101 1)) (= 0 |v_P2Thread1of1ForFork1_#res.base_3|)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_101, P2Thread1of1ForFork1_#t~ite8=|v_P2Thread1of1ForFork1_#t~ite8_44|} OutVars{P2Thread1of1ForFork1_#res.base=|v_P2Thread1of1ForFork1_#res.base_3|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_127, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_100, P2Thread1of1ForFork1_#res.offset=|v_P2Thread1of1ForFork1_#res.offset_3|, P2Thread1of1ForFork1_#t~ite8=|v_P2Thread1of1ForFork1_#t~ite8_43|} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#res.base, ~z$r_buff1_thd3~0, ~__unbuffered_cnt~0, P2Thread1of1ForFork1_#res.offset, P2Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 14:15:58,716 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [727] [727] L799-->L799-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-930988101 256) 0)) (.cse1 (= (mod ~z$r_buff0_thd4~0_In-930988101 256) 0))) (or (and (= |P3Thread1of1ForFork2_#t~ite11_Out-930988101| ~z$w_buff0_used~0_In-930988101) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |P3Thread1of1ForFork2_#t~ite11_Out-930988101| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-930988101, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-930988101} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-930988101, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-930988101, P3Thread1of1ForFork2_#t~ite11=|P3Thread1of1ForFork2_#t~ite11_Out-930988101|} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-12-07 14:15:58,717 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L800-->L800-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd4~0_In2122144501 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In2122144501 256))) (.cse1 (= (mod ~z$r_buff1_thd4~0_In2122144501 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In2122144501 256)))) (or (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In2122144501 |P3Thread1of1ForFork2_#t~ite12_Out2122144501|) (or .cse2 .cse3)) (and (= 0 |P3Thread1of1ForFork2_#t~ite12_Out2122144501|) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In2122144501, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2122144501, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In2122144501, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2122144501} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In2122144501, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2122144501, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In2122144501, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2122144501, P3Thread1of1ForFork2_#t~ite12=|P3Thread1of1ForFork2_#t~ite12_Out2122144501|} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite12] because there is no mapped edge [2019-12-07 14:15:58,717 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L801-->L802: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd4~0_In-153120946 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-153120946 256))) (.cse2 (= ~z$r_buff0_thd4~0_Out-153120946 ~z$r_buff0_thd4~0_In-153120946))) (or (and (= ~z$r_buff0_thd4~0_Out-153120946 0) (not .cse0) (not .cse1)) (and .cse1 .cse2) (and .cse0 .cse2))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-153120946, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-153120946} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-153120946, P3Thread1of1ForFork2_#t~ite13=|P3Thread1of1ForFork2_#t~ite13_Out-153120946|, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out-153120946} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite13, ~z$r_buff0_thd4~0] because there is no mapped edge [2019-12-07 14:15:58,717 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L802-->L802-2: Formula: (let ((.cse2 (= 0 (mod ~z$r_buff0_thd4~0_In230326796 256))) (.cse3 (= (mod ~z$w_buff0_used~0_In230326796 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In230326796 256))) (.cse0 (= (mod ~z$r_buff1_thd4~0_In230326796 256) 0))) (or (and (or .cse0 .cse1) (= |P3Thread1of1ForFork2_#t~ite14_Out230326796| ~z$r_buff1_thd4~0_In230326796) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |P3Thread1of1ForFork2_#t~ite14_Out230326796| 0)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In230326796, ~z$w_buff0_used~0=~z$w_buff0_used~0_In230326796, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In230326796, ~z$w_buff1_used~0=~z$w_buff1_used~0_In230326796} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In230326796, ~z$w_buff0_used~0=~z$w_buff0_used~0_In230326796, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In230326796, ~z$w_buff1_used~0=~z$w_buff1_used~0_In230326796, P3Thread1of1ForFork2_#t~ite14=|P3Thread1of1ForFork2_#t~ite14_Out230326796|} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite14] because there is no mapped edge [2019-12-07 14:15:58,717 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L802-2-->P3EXIT: Formula: (and (= |v_P3Thread1of1ForFork2_#t~ite14_54| v_~z$r_buff1_thd4~0_130) (= 0 |v_P3Thread1of1ForFork2_#res.base_3|) (= v_~__unbuffered_cnt~0_126 (+ v_~__unbuffered_cnt~0_127 1)) (= 0 |v_P3Thread1of1ForFork2_#res.offset_3|)) InVars {P3Thread1of1ForFork2_#t~ite14=|v_P3Thread1of1ForFork2_#t~ite14_54|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_127} OutVars{P3Thread1of1ForFork2_#res.base=|v_P3Thread1of1ForFork2_#res.base_3|, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_130, P3Thread1of1ForFork2_#t~ite14=|v_P3Thread1of1ForFork2_#t~ite14_53|, P3Thread1of1ForFork2_#res.offset=|v_P3Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_126} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#res.base, ~z$r_buff1_thd4~0, P3Thread1of1ForFork2_#t~ite14, P3Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 14:15:58,717 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [673] [673] L827-1-->L833: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= (ite (= 4 v_~__unbuffered_cnt~0_21) 1 0) 0) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_21} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_21, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_6|} AuxVars[] AssignedVars[~main$tmp_guard0~0, ULTIMATE.start_main_#t~nondet18] because there is no mapped edge [2019-12-07 14:15:58,718 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L833-2-->L833-4: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd0~0_In432049801 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In432049801 256) 0))) (or (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In432049801 |ULTIMATE.start_main_#t~ite19_Out432049801|)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite19_Out432049801| ~z~0_In432049801)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In432049801, ~z$w_buff1_used~0=~z$w_buff1_used~0_In432049801, ~z$w_buff1~0=~z$w_buff1~0_In432049801, ~z~0=~z~0_In432049801} OutVars{ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out432049801|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In432049801, ~z$w_buff1_used~0=~z$w_buff1_used~0_In432049801, ~z$w_buff1~0=~z$w_buff1~0_In432049801, ~z~0=~z~0_In432049801} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 14:15:58,718 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [658] [658] L833-4-->L834: Formula: (= v_~z~0_31 |v_ULTIMATE.start_main_#t~ite19_8|) InVars {ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_8|} OutVars{ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_7|, ~z~0=v_~z~0_31, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19, ~z~0, ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 14:15:58,718 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L834-->L834-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In554615859 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd0~0_In554615859 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite21_Out554615859|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite21_Out554615859| ~z$w_buff0_used~0_In554615859)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In554615859, ~z$w_buff0_used~0=~z$w_buff0_used~0_In554615859} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In554615859, ~z$w_buff0_used~0=~z$w_buff0_used~0_In554615859, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out554615859|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 14:15:58,718 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [725] [725] L835-->L835-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In1738539894 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In1738539894 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In1738539894 256))) (.cse2 (= (mod ~z$r_buff1_thd0~0_In1738539894 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite22_Out1738539894| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |ULTIMATE.start_main_#t~ite22_Out1738539894| ~z$w_buff1_used~0_In1738539894) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1738539894, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1738539894, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1738539894, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1738539894} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1738539894, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1738539894, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1738539894, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1738539894, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1738539894|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 14:15:58,718 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [718] [718] L836-->L836-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-1571101226 256) 0)) (.cse1 (= (mod ~z$r_buff0_thd0~0_In-1571101226 256) 0))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite23_Out-1571101226| 0)) (and (or .cse0 .cse1) (= ~z$r_buff0_thd0~0_In-1571101226 |ULTIMATE.start_main_#t~ite23_Out-1571101226|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1571101226, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1571101226} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1571101226, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1571101226, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-1571101226|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 14:15:58,719 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [711] [711] L837-->L837-2: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In1663486002 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In1663486002 256) 0)) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In1663486002 256))) (.cse3 (= (mod ~z$r_buff0_thd0~0_In1663486002 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite24_Out1663486002| 0)) (and (= |ULTIMATE.start_main_#t~ite24_Out1663486002| ~z$r_buff1_thd0~0_In1663486002) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1663486002, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1663486002, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1663486002, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1663486002} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1663486002, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1663486002, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1663486002, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out1663486002|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1663486002} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 14:15:58,722 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L849-->L850: Formula: (and (= v_~z$r_buff0_thd0~0_119 v_~z$r_buff0_thd0~0_120) (not (= 0 (mod v_~weak$$choice2~0_29 256)))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_120, ~weak$$choice2~0=v_~weak$$choice2~0_29} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_8|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_119, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_9|, ~weak$$choice2~0=v_~weak$$choice2~0_29, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 14:15:58,722 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L850-->L850-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-673966695 256)))) (or (and (= |ULTIMATE.start_main_#t~ite45_Out-673966695| ~z$r_buff1_thd0~0_In-673966695) .cse0 (= |ULTIMATE.start_main_#t~ite45_Out-673966695| |ULTIMATE.start_main_#t~ite46_Out-673966695|) (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In-673966695 256)))) (or (= 0 (mod ~z$w_buff0_used~0_In-673966695 256)) (and (= (mod ~z$w_buff1_used~0_In-673966695 256) 0) .cse1) (and .cse1 (= (mod ~z$r_buff1_thd0~0_In-673966695 256) 0))))) (and (= |ULTIMATE.start_main_#t~ite46_Out-673966695| ~z$r_buff1_thd0~0_In-673966695) (= |ULTIMATE.start_main_#t~ite45_In-673966695| |ULTIMATE.start_main_#t~ite45_Out-673966695|) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-673966695, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-673966695, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-673966695, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-673966695, ~weak$$choice2~0=~weak$$choice2~0_In-673966695, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In-673966695|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-673966695, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-673966695, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-673966695, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-673966695, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out-673966695|, ~weak$$choice2~0=~weak$$choice2~0_In-673966695, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out-673966695|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45] because there is no mapped edge [2019-12-07 14:15:58,722 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L852-->L855-1: Formula: (and (= v_~z$mem_tmp~0_13 v_~z~0_120) (= 0 v_~z$flush_delayed~0_24) (= (mod v_~main$tmp_guard1~0_23 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (not (= 0 (mod v_~z$flush_delayed~0_25 256)))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_13, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~z$flush_delayed~0=v_~z$flush_delayed~0_25} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_13, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~z$flush_delayed~0=v_~z$flush_delayed~0_24, ~z~0=v_~z~0_120, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 14:15:58,722 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [729] [729] L855-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 14:15:58,778 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_a7ded2e5-15b1-4e8a-af1f-a731b5758483/bin/uautomizer/witness.graphml [2019-12-07 14:15:58,778 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 14:15:58,779 INFO L168 Benchmark]: Toolchain (without parser) took 17487.98 ms. Allocated memory was 1.0 GB in the beginning and 2.6 GB in the end (delta: 1.6 GB). Free memory was 935.3 MB in the beginning and 1.8 GB in the end (delta: -892.2 MB). Peak memory consumption was 671.2 MB. Max. memory is 11.5 GB. [2019-12-07 14:15:58,779 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 14:15:58,780 INFO L168 Benchmark]: CACSL2BoogieTranslator took 381.86 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 107.0 MB). Free memory was 935.3 MB in the beginning and 1.1 GB in the end (delta: -139.3 MB). Peak memory consumption was 18.4 MB. Max. memory is 11.5 GB. [2019-12-07 14:15:58,780 INFO L168 Benchmark]: Boogie Procedure Inliner took 43.06 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 14:15:58,780 INFO L168 Benchmark]: Boogie Preprocessor took 26.27 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 14:15:58,780 INFO L168 Benchmark]: RCFGBuilder took 397.27 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 57.3 MB). Peak memory consumption was 57.3 MB. Max. memory is 11.5 GB. [2019-12-07 14:15:58,781 INFO L168 Benchmark]: TraceAbstraction took 16567.27 ms. Allocated memory was 1.1 GB in the beginning and 2.6 GB in the end (delta: 1.5 GB). Free memory was 1.0 GB in the beginning and 1.9 GB in the end (delta: -850.1 MB). Peak memory consumption was 606.4 MB. Max. memory is 11.5 GB. [2019-12-07 14:15:58,781 INFO L168 Benchmark]: Witness Printer took 69.06 ms. Allocated memory is still 2.6 GB. Free memory was 1.9 GB in the beginning and 1.8 GB in the end (delta: 34.5 MB). Peak memory consumption was 34.5 MB. Max. memory is 11.5 GB. [2019-12-07 14:15:58,782 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 381.86 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 107.0 MB). Free memory was 935.3 MB in the beginning and 1.1 GB in the end (delta: -139.3 MB). Peak memory consumption was 18.4 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 43.06 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.27 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 397.27 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 57.3 MB). Peak memory consumption was 57.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 16567.27 ms. Allocated memory was 1.1 GB in the beginning and 2.6 GB in the end (delta: 1.5 GB). Free memory was 1.0 GB in the beginning and 1.9 GB in the end (delta: -850.1 MB). Peak memory consumption was 606.4 MB. Max. memory is 11.5 GB. * Witness Printer took 69.06 ms. Allocated memory is still 2.6 GB. Free memory was 1.9 GB in the beginning and 1.8 GB in the end (delta: 34.5 MB). Peak memory consumption was 34.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.2s, 178 ProgramPointsBefore, 91 ProgramPointsAfterwards, 206 TransitionsBefore, 100 TransitionsAfterwards, 12668 CoEnabledTransitionPairs, 8 FixpointIterations, 34 TrivialSequentialCompositions, 49 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 36 ConcurrentYvCompositions, 24 ChoiceCompositions, 4617 VarBasedMoverChecksPositive, 237 VarBasedMoverChecksNegative, 66 SemBasedMoverChecksPositive, 231 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.9s, 0 MoverChecksTotal, 56276 CheckedPairsTotal, 119 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L821] FCALL, FORK 0 pthread_create(&t1541, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L823] FCALL, FORK 0 pthread_create(&t1542, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L825] FCALL, FORK 0 pthread_create(&t1543, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L827] FCALL, FORK 0 pthread_create(&t1544, ((void *)0), P3, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L787] 4 z$r_buff1_thd0 = z$r_buff0_thd0 [L788] 4 z$r_buff1_thd1 = z$r_buff0_thd1 [L789] 4 z$r_buff1_thd2 = z$r_buff0_thd2 [L790] 4 z$r_buff1_thd3 = z$r_buff0_thd3 [L791] 4 z$r_buff1_thd4 = z$r_buff0_thd4 [L792] 4 z$r_buff0_thd4 = (_Bool)1 [L795] 4 __unbuffered_p3_EAX = a VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L762] 3 y = 2 [L765] 3 z = 1 VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=2, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L768] EXPR 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=2, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L768] 3 z = z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) [L769] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L770] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L771] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L798] EXPR 4 z$w_buff0_used && z$r_buff0_thd4 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd4 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L798] 4 z = z$w_buff0_used && z$r_buff0_thd4 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd4 ? z$w_buff1 : z) [L799] 4 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd4 ? (_Bool)0 : z$w_buff0_used [L800] 4 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd4 || z$w_buff1_used && z$r_buff1_thd4 ? (_Bool)0 : z$w_buff1_used [L833] 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L834] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L835] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L836] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L837] 0 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L840] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L841] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L842] 0 z$flush_delayed = weak$$choice2 [L843] 0 z$mem_tmp = z VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L844] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L844] 0 z = !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) [L845] EXPR 0 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L845] 0 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) [L846] EXPR 0 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L846] 0 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) [L847] EXPR 0 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L847] 0 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) [L848] EXPR 0 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L848] 0 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L850] 0 z$r_buff1_thd0 = weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L851] 0 main$tmp_guard1 = !(x == 2 && y == 2 && z == 2 && __unbuffered_p3_EAX == 0) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 166 locations, 2 error locations. Result: UNSAFE, OverallTime: 16.4s, OverallIterations: 19, TraceHistogramMax: 1, AutomataDifference: 4.3s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 2181 SDtfs, 1893 SDslu, 4526 SDs, 0 SdLazy, 2283 SolverSat, 154 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 138 GetRequests, 36 SyntacticMatches, 13 SemanticMatches, 89 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 123 ImplicationChecksByTransitivity, 0.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=51342occurred in iteration=4, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 5.6s AutomataMinimizationTime, 18 MinimizatonAttempts, 32193 StatesRemovedByMinimization, 12 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 0.7s InterpolantComputationTime, 838 NumberOfCodeBlocks, 838 NumberOfCodeBlocksAsserted, 19 NumberOfCheckSat, 760 ConstructedInterpolants, 0 QuantifiedInterpolants, 110591 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 18 InterpolantComputations, 18 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...