./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.1.ufo.BOUNDED-10.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_62e78249-d907-4cec-92b9-62485cadb9fb/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_62e78249-d907-4cec-92b9-62485cadb9fb/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_62e78249-d907-4cec-92b9-62485cadb9fb/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_62e78249-d907-4cec-92b9-62485cadb9fb/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.1.ufo.BOUNDED-10.pals.c -s /tmp/vcloud-vcloud-master/worker/run_dir_62e78249-d907-4cec-92b9-62485cadb9fb/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_62e78249-d907-4cec-92b9-62485cadb9fb/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash b3b24d22acbd30abb2bd6c739c1741063240b31f ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 16:00:32,592 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 16:00:32,593 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 16:00:32,601 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 16:00:32,601 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 16:00:32,602 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 16:00:32,603 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 16:00:32,604 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 16:00:32,606 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 16:00:32,607 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 16:00:32,608 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 16:00:32,609 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 16:00:32,609 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 16:00:32,610 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 16:00:32,611 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 16:00:32,612 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 16:00:32,612 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 16:00:32,613 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 16:00:32,615 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 16:00:32,617 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 16:00:32,618 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 16:00:32,619 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 16:00:32,620 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 16:00:32,621 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 16:00:32,623 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 16:00:32,623 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 16:00:32,623 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 16:00:32,624 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 16:00:32,624 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 16:00:32,625 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 16:00:32,625 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 16:00:32,626 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 16:00:32,626 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 16:00:32,627 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 16:00:32,627 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 16:00:32,628 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 16:00:32,628 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 16:00:32,628 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 16:00:32,628 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 16:00:32,629 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 16:00:32,630 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 16:00:32,630 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_62e78249-d907-4cec-92b9-62485cadb9fb/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 16:00:32,643 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 16:00:32,643 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 16:00:32,644 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 16:00:32,644 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 16:00:32,644 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 16:00:32,644 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 16:00:32,644 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 16:00:32,644 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 16:00:32,644 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 16:00:32,645 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 16:00:32,645 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 16:00:32,645 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 16:00:32,645 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 16:00:32,645 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 16:00:32,645 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 16:00:32,646 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 16:00:32,646 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 16:00:32,646 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 16:00:32,646 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 16:00:32,646 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 16:00:32,646 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 16:00:32,646 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 16:00:32,647 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 16:00:32,647 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 16:00:32,647 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 16:00:32,647 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 16:00:32,647 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 16:00:32,647 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 16:00:32,647 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 16:00:32,647 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_62e78249-d907-4cec-92b9-62485cadb9fb/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b3b24d22acbd30abb2bd6c739c1741063240b31f [2019-12-07 16:00:32,756 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 16:00:32,767 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 16:00:32,770 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 16:00:32,771 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 16:00:32,771 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 16:00:32,772 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_62e78249-d907-4cec-92b9-62485cadb9fb/bin/uautomizer/../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.1.ufo.BOUNDED-10.pals.c [2019-12-07 16:00:32,814 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_62e78249-d907-4cec-92b9-62485cadb9fb/bin/uautomizer/data/7b4e10f5c/bbe9108ac4cc4b1fa7accb54a27ce871/FLAG8de8c7fff [2019-12-07 16:00:33,189 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 16:00:33,189 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_62e78249-d907-4cec-92b9-62485cadb9fb/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.1.ufo.BOUNDED-10.pals.c [2019-12-07 16:00:33,197 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_62e78249-d907-4cec-92b9-62485cadb9fb/bin/uautomizer/data/7b4e10f5c/bbe9108ac4cc4b1fa7accb54a27ce871/FLAG8de8c7fff [2019-12-07 16:00:33,206 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_62e78249-d907-4cec-92b9-62485cadb9fb/bin/uautomizer/data/7b4e10f5c/bbe9108ac4cc4b1fa7accb54a27ce871 [2019-12-07 16:00:33,208 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 16:00:33,209 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 16:00:33,210 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 16:00:33,210 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 16:00:33,212 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 16:00:33,212 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 04:00:33" (1/1) ... [2019-12-07 16:00:33,214 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@581b80cd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:00:33, skipping insertion in model container [2019-12-07 16:00:33,214 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 04:00:33" (1/1) ... [2019-12-07 16:00:33,219 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 16:00:33,244 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 16:00:33,436 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 16:00:33,442 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 16:00:33,483 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 16:00:33,496 INFO L208 MainTranslator]: Completed translation [2019-12-07 16:00:33,496 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:00:33 WrapperNode [2019-12-07 16:00:33,496 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 16:00:33,497 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 16:00:33,497 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 16:00:33,497 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 16:00:33,502 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:00:33" (1/1) ... [2019-12-07 16:00:33,510 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:00:33" (1/1) ... [2019-12-07 16:00:33,541 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 16:00:33,542 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 16:00:33,542 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 16:00:33,542 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 16:00:33,548 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:00:33" (1/1) ... [2019-12-07 16:00:33,548 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:00:33" (1/1) ... [2019-12-07 16:00:33,552 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:00:33" (1/1) ... [2019-12-07 16:00:33,553 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:00:33" (1/1) ... [2019-12-07 16:00:33,565 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:00:33" (1/1) ... [2019-12-07 16:00:33,575 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:00:33" (1/1) ... [2019-12-07 16:00:33,579 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:00:33" (1/1) ... [2019-12-07 16:00:33,586 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 16:00:33,586 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 16:00:33,586 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 16:00:33,587 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 16:00:33,587 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:00:33" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_62e78249-d907-4cec-92b9-62485cadb9fb/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 16:00:33,633 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 16:00:33,633 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 16:00:34,165 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 16:00:34,165 INFO L287 CfgBuilder]: Removed 119 assume(true) statements. [2019-12-07 16:00:34,166 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:00:34 BoogieIcfgContainer [2019-12-07 16:00:34,166 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 16:00:34,167 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 16:00:34,167 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 16:00:34,168 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 16:00:34,169 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 04:00:33" (1/3) ... [2019-12-07 16:00:34,169 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@108469dc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 04:00:34, skipping insertion in model container [2019-12-07 16:00:34,169 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:00:33" (2/3) ... [2019-12-07 16:00:34,169 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@108469dc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 04:00:34, skipping insertion in model container [2019-12-07 16:00:34,170 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:00:34" (3/3) ... [2019-12-07 16:00:34,171 INFO L109 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby.1.ufo.BOUNDED-10.pals.c [2019-12-07 16:00:34,177 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 16:00:34,182 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 23 error locations. [2019-12-07 16:00:34,189 INFO L249 AbstractCegarLoop]: Starting to check reachability of 23 error locations. [2019-12-07 16:00:34,207 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 16:00:34,207 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 16:00:34,207 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 16:00:34,207 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 16:00:34,207 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 16:00:34,207 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 16:00:34,207 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 16:00:34,207 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 16:00:34,225 INFO L276 IsEmpty]: Start isEmpty. Operand 293 states. [2019-12-07 16:00:34,230 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 16:00:34,230 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:34,231 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:34,231 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:34,235 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:34,235 INFO L82 PathProgramCache]: Analyzing trace with hash 211735483, now seen corresponding path program 1 times [2019-12-07 16:00:34,241 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:34,241 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [128112108] [2019-12-07 16:00:34,241 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:34,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:34,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:34,375 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [128112108] [2019-12-07 16:00:34,375 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:34,375 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:00:34,376 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1749845609] [2019-12-07 16:00:34,380 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:00:34,380 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:34,388 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:00:34,389 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:00:34,390 INFO L87 Difference]: Start difference. First operand 293 states. Second operand 3 states. [2019-12-07 16:00:34,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:34,450 INFO L93 Difference]: Finished difference Result 572 states and 892 transitions. [2019-12-07 16:00:34,450 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:00:34,451 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 31 [2019-12-07 16:00:34,451 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:34,461 INFO L225 Difference]: With dead ends: 572 [2019-12-07 16:00:34,461 INFO L226 Difference]: Without dead ends: 289 [2019-12-07 16:00:34,464 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:00:34,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 289 states. [2019-12-07 16:00:34,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 289 to 289. [2019-12-07 16:00:34,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 289 states. [2019-12-07 16:00:34,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 289 states to 289 states and 413 transitions. [2019-12-07 16:00:34,502 INFO L78 Accepts]: Start accepts. Automaton has 289 states and 413 transitions. Word has length 31 [2019-12-07 16:00:34,503 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:34,503 INFO L462 AbstractCegarLoop]: Abstraction has 289 states and 413 transitions. [2019-12-07 16:00:34,503 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:00:34,503 INFO L276 IsEmpty]: Start isEmpty. Operand 289 states and 413 transitions. [2019-12-07 16:00:34,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-12-07 16:00:34,505 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:34,505 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:34,506 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:34,506 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:34,506 INFO L82 PathProgramCache]: Analyzing trace with hash -1187444686, now seen corresponding path program 1 times [2019-12-07 16:00:34,506 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:34,507 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989594541] [2019-12-07 16:00:34,507 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:34,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:34,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:34,628 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [989594541] [2019-12-07 16:00:34,629 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:34,629 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:00:34,629 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2110053070] [2019-12-07 16:00:34,630 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:00:34,630 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:34,630 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:00:34,631 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:00:34,631 INFO L87 Difference]: Start difference. First operand 289 states and 413 transitions. Second operand 3 states. [2019-12-07 16:00:34,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:34,668 INFO L93 Difference]: Finished difference Result 597 states and 861 transitions. [2019-12-07 16:00:34,668 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:00:34,668 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 42 [2019-12-07 16:00:34,669 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:34,671 INFO L225 Difference]: With dead ends: 597 [2019-12-07 16:00:34,671 INFO L226 Difference]: Without dead ends: 323 [2019-12-07 16:00:34,672 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:00:34,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 323 states. [2019-12-07 16:00:34,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 265. [2019-12-07 16:00:34,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 265 states. [2019-12-07 16:00:34,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 265 states to 265 states and 377 transitions. [2019-12-07 16:00:34,686 INFO L78 Accepts]: Start accepts. Automaton has 265 states and 377 transitions. Word has length 42 [2019-12-07 16:00:34,686 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:34,686 INFO L462 AbstractCegarLoop]: Abstraction has 265 states and 377 transitions. [2019-12-07 16:00:34,686 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:00:34,686 INFO L276 IsEmpty]: Start isEmpty. Operand 265 states and 377 transitions. [2019-12-07 16:00:34,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-12-07 16:00:34,687 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:34,687 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:34,688 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:34,688 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:34,688 INFO L82 PathProgramCache]: Analyzing trace with hash 1273755287, now seen corresponding path program 1 times [2019-12-07 16:00:34,688 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:34,688 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [204040925] [2019-12-07 16:00:34,688 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:34,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:34,744 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:34,744 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [204040925] [2019-12-07 16:00:34,745 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:34,745 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:00:34,745 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [175971788] [2019-12-07 16:00:34,746 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:00:34,746 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:34,746 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:00:34,746 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:00:34,746 INFO L87 Difference]: Start difference. First operand 265 states and 377 transitions. Second operand 3 states. [2019-12-07 16:00:34,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:34,777 INFO L93 Difference]: Finished difference Result 742 states and 1066 transitions. [2019-12-07 16:00:34,778 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:00:34,778 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-12-07 16:00:34,779 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:34,781 INFO L225 Difference]: With dead ends: 742 [2019-12-07 16:00:34,781 INFO L226 Difference]: Without dead ends: 492 [2019-12-07 16:00:34,782 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:00:34,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 492 states. [2019-12-07 16:00:34,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 492 to 300. [2019-12-07 16:00:34,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 300 states. [2019-12-07 16:00:34,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 300 states to 300 states and 429 transitions. [2019-12-07 16:00:34,798 INFO L78 Accepts]: Start accepts. Automaton has 300 states and 429 transitions. Word has length 49 [2019-12-07 16:00:34,798 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:34,798 INFO L462 AbstractCegarLoop]: Abstraction has 300 states and 429 transitions. [2019-12-07 16:00:34,799 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:00:34,799 INFO L276 IsEmpty]: Start isEmpty. Operand 300 states and 429 transitions. [2019-12-07 16:00:34,800 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2019-12-07 16:00:34,800 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:34,800 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:34,801 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:34,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:34,801 INFO L82 PathProgramCache]: Analyzing trace with hash -1910840580, now seen corresponding path program 1 times [2019-12-07 16:00:34,801 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:34,801 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922137260] [2019-12-07 16:00:34,801 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:34,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:34,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:34,867 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1922137260] [2019-12-07 16:00:34,867 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:34,868 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:00:34,868 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [429690852] [2019-12-07 16:00:34,868 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:00:34,868 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:34,868 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:00:34,868 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:00:34,869 INFO L87 Difference]: Start difference. First operand 300 states and 429 transitions. Second operand 5 states. [2019-12-07 16:00:35,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:35,044 INFO L93 Difference]: Finished difference Result 942 states and 1360 transitions. [2019-12-07 16:00:35,045 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:00:35,045 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2019-12-07 16:00:35,045 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:35,049 INFO L225 Difference]: With dead ends: 942 [2019-12-07 16:00:35,050 INFO L226 Difference]: Without dead ends: 657 [2019-12-07 16:00:35,051 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 16:00:35,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 657 states. [2019-12-07 16:00:35,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 657 to 386. [2019-12-07 16:00:35,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 386 states. [2019-12-07 16:00:35,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386 states to 386 states and 552 transitions. [2019-12-07 16:00:35,070 INFO L78 Accepts]: Start accepts. Automaton has 386 states and 552 transitions. Word has length 50 [2019-12-07 16:00:35,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:35,070 INFO L462 AbstractCegarLoop]: Abstraction has 386 states and 552 transitions. [2019-12-07 16:00:35,070 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:00:35,070 INFO L276 IsEmpty]: Start isEmpty. Operand 386 states and 552 transitions. [2019-12-07 16:00:35,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 16:00:35,072 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:35,072 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:35,072 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:35,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:35,073 INFO L82 PathProgramCache]: Analyzing trace with hash -1041102253, now seen corresponding path program 1 times [2019-12-07 16:00:35,073 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:35,073 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [757491735] [2019-12-07 16:00:35,073 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:35,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:35,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:35,130 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [757491735] [2019-12-07 16:00:35,130 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:35,130 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:00:35,131 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1900979453] [2019-12-07 16:00:35,131 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:00:35,131 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:35,131 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:00:35,131 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:00:35,131 INFO L87 Difference]: Start difference. First operand 386 states and 552 transitions. Second operand 5 states. [2019-12-07 16:00:35,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:35,290 INFO L93 Difference]: Finished difference Result 944 states and 1360 transitions. [2019-12-07 16:00:35,291 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:00:35,291 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-12-07 16:00:35,291 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:35,295 INFO L225 Difference]: With dead ends: 944 [2019-12-07 16:00:35,295 INFO L226 Difference]: Without dead ends: 659 [2019-12-07 16:00:35,296 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 16:00:35,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 659 states. [2019-12-07 16:00:35,312 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 659 to 390. [2019-12-07 16:00:35,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 390 states. [2019-12-07 16:00:35,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 390 states to 390 states and 556 transitions. [2019-12-07 16:00:35,314 INFO L78 Accepts]: Start accepts. Automaton has 390 states and 556 transitions. Word has length 51 [2019-12-07 16:00:35,314 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:35,314 INFO L462 AbstractCegarLoop]: Abstraction has 390 states and 556 transitions. [2019-12-07 16:00:35,314 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:00:35,314 INFO L276 IsEmpty]: Start isEmpty. Operand 390 states and 556 transitions. [2019-12-07 16:00:35,315 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-12-07 16:00:35,316 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:35,316 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:35,316 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:35,316 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:35,316 INFO L82 PathProgramCache]: Analyzing trace with hash -458607163, now seen corresponding path program 1 times [2019-12-07 16:00:35,317 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:35,317 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [360108329] [2019-12-07 16:00:35,317 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:35,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:35,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:35,391 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [360108329] [2019-12-07 16:00:35,391 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:35,391 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:00:35,391 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1335112788] [2019-12-07 16:00:35,392 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:00:35,392 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:35,392 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:00:35,392 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:00:35,392 INFO L87 Difference]: Start difference. First operand 390 states and 556 transitions. Second operand 4 states. [2019-12-07 16:00:35,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:35,538 INFO L93 Difference]: Finished difference Result 944 states and 1356 transitions. [2019-12-07 16:00:35,538 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:00:35,538 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 53 [2019-12-07 16:00:35,539 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:35,541 INFO L225 Difference]: With dead ends: 944 [2019-12-07 16:00:35,542 INFO L226 Difference]: Without dead ends: 659 [2019-12-07 16:00:35,542 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:00:35,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 659 states. [2019-12-07 16:00:35,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 659 to 390. [2019-12-07 16:00:35,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 390 states. [2019-12-07 16:00:35,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 390 states to 390 states and 554 transitions. [2019-12-07 16:00:35,554 INFO L78 Accepts]: Start accepts. Automaton has 390 states and 554 transitions. Word has length 53 [2019-12-07 16:00:35,555 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:35,555 INFO L462 AbstractCegarLoop]: Abstraction has 390 states and 554 transitions. [2019-12-07 16:00:35,555 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:00:35,555 INFO L276 IsEmpty]: Start isEmpty. Operand 390 states and 554 transitions. [2019-12-07 16:00:35,555 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-12-07 16:00:35,555 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:35,556 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:35,556 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:35,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:35,556 INFO L82 PathProgramCache]: Analyzing trace with hash 1789775306, now seen corresponding path program 1 times [2019-12-07 16:00:35,556 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:35,556 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [798497185] [2019-12-07 16:00:35,557 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:35,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:35,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:35,650 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [798497185] [2019-12-07 16:00:35,650 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:35,650 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:00:35,650 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1212471692] [2019-12-07 16:00:35,651 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:00:35,651 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:35,651 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:00:35,651 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:00:35,651 INFO L87 Difference]: Start difference. First operand 390 states and 554 transitions. Second operand 5 states. [2019-12-07 16:00:35,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:35,698 INFO L93 Difference]: Finished difference Result 776 states and 1117 transitions. [2019-12-07 16:00:35,699 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 16:00:35,699 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 54 [2019-12-07 16:00:35,699 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:35,702 INFO L225 Difference]: With dead ends: 776 [2019-12-07 16:00:35,702 INFO L226 Difference]: Without dead ends: 491 [2019-12-07 16:00:35,703 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:00:35,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 491 states. [2019-12-07 16:00:35,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 491 to 385. [2019-12-07 16:00:35,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 385 states. [2019-12-07 16:00:35,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 385 states to 385 states and 546 transitions. [2019-12-07 16:00:35,717 INFO L78 Accepts]: Start accepts. Automaton has 385 states and 546 transitions. Word has length 54 [2019-12-07 16:00:35,717 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:35,717 INFO L462 AbstractCegarLoop]: Abstraction has 385 states and 546 transitions. [2019-12-07 16:00:35,717 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:00:35,717 INFO L276 IsEmpty]: Start isEmpty. Operand 385 states and 546 transitions. [2019-12-07 16:00:35,718 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 16:00:35,718 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:35,718 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:35,719 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:35,719 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:35,719 INFO L82 PathProgramCache]: Analyzing trace with hash 1630366882, now seen corresponding path program 1 times [2019-12-07 16:00:35,719 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:35,719 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [62390222] [2019-12-07 16:00:35,719 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:35,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:35,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:35,806 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [62390222] [2019-12-07 16:00:35,806 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:35,806 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:00:35,806 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1428569740] [2019-12-07 16:00:35,807 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:00:35,807 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:35,807 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:00:35,807 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:00:35,807 INFO L87 Difference]: Start difference. First operand 385 states and 546 transitions. Second operand 5 states. [2019-12-07 16:00:35,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:35,894 INFO L93 Difference]: Finished difference Result 807 states and 1166 transitions. [2019-12-07 16:00:35,895 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:00:35,895 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 58 [2019-12-07 16:00:35,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:35,898 INFO L225 Difference]: With dead ends: 807 [2019-12-07 16:00:35,898 INFO L226 Difference]: Without dead ends: 527 [2019-12-07 16:00:35,899 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:00:35,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states. [2019-12-07 16:00:35,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 355. [2019-12-07 16:00:35,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 355 states. [2019-12-07 16:00:35,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 355 states to 355 states and 500 transitions. [2019-12-07 16:00:35,917 INFO L78 Accepts]: Start accepts. Automaton has 355 states and 500 transitions. Word has length 58 [2019-12-07 16:00:35,917 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:35,917 INFO L462 AbstractCegarLoop]: Abstraction has 355 states and 500 transitions. [2019-12-07 16:00:35,917 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:00:35,917 INFO L276 IsEmpty]: Start isEmpty. Operand 355 states and 500 transitions. [2019-12-07 16:00:35,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-12-07 16:00:35,918 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:35,918 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:35,918 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:35,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:35,918 INFO L82 PathProgramCache]: Analyzing trace with hash 644191382, now seen corresponding path program 1 times [2019-12-07 16:00:35,918 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:35,918 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [182064097] [2019-12-07 16:00:35,919 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:35,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:35,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:36,000 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [182064097] [2019-12-07 16:00:36,000 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:36,000 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:00:36,000 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [485512739] [2019-12-07 16:00:36,000 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:00:36,000 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:36,000 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:00:36,001 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:00:36,001 INFO L87 Difference]: Start difference. First operand 355 states and 500 transitions. Second operand 5 states. [2019-12-07 16:00:36,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:36,084 INFO L93 Difference]: Finished difference Result 904 states and 1296 transitions. [2019-12-07 16:00:36,085 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:00:36,085 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 63 [2019-12-07 16:00:36,085 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:36,087 INFO L225 Difference]: With dead ends: 904 [2019-12-07 16:00:36,087 INFO L226 Difference]: Without dead ends: 654 [2019-12-07 16:00:36,088 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:00:36,088 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 654 states. [2019-12-07 16:00:36,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 654 to 325. [2019-12-07 16:00:36,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 325 states. [2019-12-07 16:00:36,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 325 states to 325 states and 454 transitions. [2019-12-07 16:00:36,102 INFO L78 Accepts]: Start accepts. Automaton has 325 states and 454 transitions. Word has length 63 [2019-12-07 16:00:36,102 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:36,102 INFO L462 AbstractCegarLoop]: Abstraction has 325 states and 454 transitions. [2019-12-07 16:00:36,102 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:00:36,102 INFO L276 IsEmpty]: Start isEmpty. Operand 325 states and 454 transitions. [2019-12-07 16:00:36,103 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:00:36,103 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:36,103 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:36,103 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:36,103 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:36,103 INFO L82 PathProgramCache]: Analyzing trace with hash 157991886, now seen corresponding path program 1 times [2019-12-07 16:00:36,103 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:36,103 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1012917936] [2019-12-07 16:00:36,103 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:36,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:36,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:36,199 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1012917936] [2019-12-07 16:00:36,199 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:36,199 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 16:00:36,199 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1829076457] [2019-12-07 16:00:36,199 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:00:36,199 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:36,199 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:00:36,200 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:00:36,200 INFO L87 Difference]: Start difference. First operand 325 states and 454 transitions. Second operand 6 states. [2019-12-07 16:00:36,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:36,368 INFO L93 Difference]: Finished difference Result 1105 states and 1564 transitions. [2019-12-07 16:00:36,368 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 16:00:36,368 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 68 [2019-12-07 16:00:36,368 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:36,372 INFO L225 Difference]: With dead ends: 1105 [2019-12-07 16:00:36,372 INFO L226 Difference]: Without dead ends: 885 [2019-12-07 16:00:36,373 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-12-07 16:00:36,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 885 states. [2019-12-07 16:00:36,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 885 to 364. [2019-12-07 16:00:36,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 364 states. [2019-12-07 16:00:36,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 364 states to 364 states and 508 transitions. [2019-12-07 16:00:36,390 INFO L78 Accepts]: Start accepts. Automaton has 364 states and 508 transitions. Word has length 68 [2019-12-07 16:00:36,391 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:36,391 INFO L462 AbstractCegarLoop]: Abstraction has 364 states and 508 transitions. [2019-12-07 16:00:36,391 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:00:36,391 INFO L276 IsEmpty]: Start isEmpty. Operand 364 states and 508 transitions. [2019-12-07 16:00:36,391 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-12-07 16:00:36,391 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:36,391 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:36,392 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:36,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:36,392 INFO L82 PathProgramCache]: Analyzing trace with hash -2134355609, now seen corresponding path program 1 times [2019-12-07 16:00:36,392 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:36,392 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [351255585] [2019-12-07 16:00:36,392 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:36,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:36,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:36,428 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [351255585] [2019-12-07 16:00:36,428 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:36,428 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:00:36,428 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1884586014] [2019-12-07 16:00:36,429 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:00:36,429 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:36,429 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:00:36,429 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:00:36,429 INFO L87 Difference]: Start difference. First operand 364 states and 508 transitions. Second operand 3 states. [2019-12-07 16:00:36,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:36,465 INFO L93 Difference]: Finished difference Result 662 states and 935 transitions. [2019-12-07 16:00:36,465 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:00:36,465 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 69 [2019-12-07 16:00:36,465 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:36,467 INFO L225 Difference]: With dead ends: 662 [2019-12-07 16:00:36,467 INFO L226 Difference]: Without dead ends: 442 [2019-12-07 16:00:36,467 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:00:36,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 442 states. [2019-12-07 16:00:36,481 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 442 to 360. [2019-12-07 16:00:36,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 360 states. [2019-12-07 16:00:36,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 360 states to 360 states and 501 transitions. [2019-12-07 16:00:36,482 INFO L78 Accepts]: Start accepts. Automaton has 360 states and 501 transitions. Word has length 69 [2019-12-07 16:00:36,482 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:36,482 INFO L462 AbstractCegarLoop]: Abstraction has 360 states and 501 transitions. [2019-12-07 16:00:36,482 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:00:36,483 INFO L276 IsEmpty]: Start isEmpty. Operand 360 states and 501 transitions. [2019-12-07 16:00:36,483 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 16:00:36,483 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:36,483 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:36,483 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:36,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:36,483 INFO L82 PathProgramCache]: Analyzing trace with hash 1585943340, now seen corresponding path program 1 times [2019-12-07 16:00:36,484 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:36,484 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2056605293] [2019-12-07 16:00:36,484 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:36,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:36,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:36,517 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2056605293] [2019-12-07 16:00:36,517 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:36,517 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:00:36,517 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1165906770] [2019-12-07 16:00:36,517 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:00:36,518 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:36,518 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:00:36,518 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:00:36,518 INFO L87 Difference]: Start difference. First operand 360 states and 501 transitions. Second operand 4 states. [2019-12-07 16:00:36,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:36,619 INFO L93 Difference]: Finished difference Result 953 states and 1330 transitions. [2019-12-07 16:00:36,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:00:36,619 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 72 [2019-12-07 16:00:36,619 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:36,623 INFO L225 Difference]: With dead ends: 953 [2019-12-07 16:00:36,623 INFO L226 Difference]: Without dead ends: 727 [2019-12-07 16:00:36,624 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:00:36,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 727 states. [2019-12-07 16:00:36,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 727 to 530. [2019-12-07 16:00:36,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 530 states. [2019-12-07 16:00:36,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 530 states to 530 states and 734 transitions. [2019-12-07 16:00:36,653 INFO L78 Accepts]: Start accepts. Automaton has 530 states and 734 transitions. Word has length 72 [2019-12-07 16:00:36,654 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:36,654 INFO L462 AbstractCegarLoop]: Abstraction has 530 states and 734 transitions. [2019-12-07 16:00:36,654 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:00:36,654 INFO L276 IsEmpty]: Start isEmpty. Operand 530 states and 734 transitions. [2019-12-07 16:00:36,654 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 16:00:36,654 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:36,654 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:36,655 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:36,655 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:36,655 INFO L82 PathProgramCache]: Analyzing trace with hash -2083950892, now seen corresponding path program 1 times [2019-12-07 16:00:36,655 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:36,655 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [740627590] [2019-12-07 16:00:36,655 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:36,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:36,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:36,683 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [740627590] [2019-12-07 16:00:36,683 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:36,683 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:00:36,683 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [778534505] [2019-12-07 16:00:36,683 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:00:36,684 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:36,684 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:00:36,684 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:00:36,684 INFO L87 Difference]: Start difference. First operand 530 states and 734 transitions. Second operand 3 states. [2019-12-07 16:00:36,715 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:36,715 INFO L93 Difference]: Finished difference Result 909 states and 1264 transitions. [2019-12-07 16:00:36,715 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:00:36,715 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-12-07 16:00:36,716 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:36,718 INFO L225 Difference]: With dead ends: 909 [2019-12-07 16:00:36,718 INFO L226 Difference]: Without dead ends: 530 [2019-12-07 16:00:36,719 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:00:36,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 530 states. [2019-12-07 16:00:36,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 530 to 530. [2019-12-07 16:00:36,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 530 states. [2019-12-07 16:00:36,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 530 states to 530 states and 730 transitions. [2019-12-07 16:00:36,752 INFO L78 Accepts]: Start accepts. Automaton has 530 states and 730 transitions. Word has length 72 [2019-12-07 16:00:36,752 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:36,752 INFO L462 AbstractCegarLoop]: Abstraction has 530 states and 730 transitions. [2019-12-07 16:00:36,752 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:00:36,752 INFO L276 IsEmpty]: Start isEmpty. Operand 530 states and 730 transitions. [2019-12-07 16:00:36,753 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 16:00:36,753 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:36,753 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:36,754 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:36,754 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:36,754 INFO L82 PathProgramCache]: Analyzing trace with hash 2070467794, now seen corresponding path program 1 times [2019-12-07 16:00:36,754 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:36,754 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [575587302] [2019-12-07 16:00:36,754 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:36,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:36,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:36,781 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [575587302] [2019-12-07 16:00:36,781 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:36,781 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:00:36,781 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [542307264] [2019-12-07 16:00:36,782 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:00:36,782 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:36,782 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:00:36,782 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:00:36,782 INFO L87 Difference]: Start difference. First operand 530 states and 730 transitions. Second operand 3 states. [2019-12-07 16:00:36,819 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:36,819 INFO L93 Difference]: Finished difference Result 1253 states and 1720 transitions. [2019-12-07 16:00:36,819 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:00:36,819 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-12-07 16:00:36,820 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:36,823 INFO L225 Difference]: With dead ends: 1253 [2019-12-07 16:00:36,823 INFO L226 Difference]: Without dead ends: 837 [2019-12-07 16:00:36,823 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:00:36,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 837 states. [2019-12-07 16:00:36,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 837 to 564. [2019-12-07 16:00:36,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 564 states. [2019-12-07 16:00:36,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 564 states to 564 states and 774 transitions. [2019-12-07 16:00:36,850 INFO L78 Accepts]: Start accepts. Automaton has 564 states and 774 transitions. Word has length 72 [2019-12-07 16:00:36,850 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:36,850 INFO L462 AbstractCegarLoop]: Abstraction has 564 states and 774 transitions. [2019-12-07 16:00:36,850 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:00:36,850 INFO L276 IsEmpty]: Start isEmpty. Operand 564 states and 774 transitions. [2019-12-07 16:00:36,851 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 16:00:36,851 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:36,851 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:36,852 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:36,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:36,852 INFO L82 PathProgramCache]: Analyzing trace with hash -1917205063, now seen corresponding path program 1 times [2019-12-07 16:00:36,852 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:36,852 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [399836596] [2019-12-07 16:00:36,852 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:36,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:36,942 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:36,942 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [399836596] [2019-12-07 16:00:36,942 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:36,943 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 16:00:36,943 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [839187971] [2019-12-07 16:00:36,943 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:00:36,943 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:36,943 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:00:36,943 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:00:36,944 INFO L87 Difference]: Start difference. First operand 564 states and 774 transitions. Second operand 6 states. [2019-12-07 16:00:37,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:37,147 INFO L93 Difference]: Finished difference Result 1770 states and 2483 transitions. [2019-12-07 16:00:37,147 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 16:00:37,147 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2019-12-07 16:00:37,148 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:37,155 INFO L225 Difference]: With dead ends: 1770 [2019-12-07 16:00:37,155 INFO L226 Difference]: Without dead ends: 1436 [2019-12-07 16:00:37,156 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-12-07 16:00:37,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1436 states. [2019-12-07 16:00:37,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1436 to 568. [2019-12-07 16:00:37,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 568 states. [2019-12-07 16:00:37,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 568 states to 568 states and 779 transitions. [2019-12-07 16:00:37,196 INFO L78 Accepts]: Start accepts. Automaton has 568 states and 779 transitions. Word has length 73 [2019-12-07 16:00:37,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:37,196 INFO L462 AbstractCegarLoop]: Abstraction has 568 states and 779 transitions. [2019-12-07 16:00:37,196 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:00:37,196 INFO L276 IsEmpty]: Start isEmpty. Operand 568 states and 779 transitions. [2019-12-07 16:00:37,197 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 16:00:37,197 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:37,197 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:37,197 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:37,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:37,197 INFO L82 PathProgramCache]: Analyzing trace with hash 197100160, now seen corresponding path program 1 times [2019-12-07 16:00:37,197 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:37,197 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [327567699] [2019-12-07 16:00:37,198 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:37,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:37,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:37,265 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [327567699] [2019-12-07 16:00:37,266 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:37,266 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:00:37,266 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320022858] [2019-12-07 16:00:37,266 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:00:37,266 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:37,267 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:00:37,267 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:00:37,267 INFO L87 Difference]: Start difference. First operand 568 states and 779 transitions. Second operand 5 states. [2019-12-07 16:00:37,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:37,388 INFO L93 Difference]: Finished difference Result 888 states and 1239 transitions. [2019-12-07 16:00:37,388 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:00:37,388 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 73 [2019-12-07 16:00:37,389 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:37,393 INFO L225 Difference]: With dead ends: 888 [2019-12-07 16:00:37,393 INFO L226 Difference]: Without dead ends: 886 [2019-12-07 16:00:37,394 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 16:00:37,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 886 states. [2019-12-07 16:00:37,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 886 to 570. [2019-12-07 16:00:37,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 570 states. [2019-12-07 16:00:37,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 570 states to 570 states and 781 transitions. [2019-12-07 16:00:37,434 INFO L78 Accepts]: Start accepts. Automaton has 570 states and 781 transitions. Word has length 73 [2019-12-07 16:00:37,434 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:37,434 INFO L462 AbstractCegarLoop]: Abstraction has 570 states and 781 transitions. [2019-12-07 16:00:37,434 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:00:37,434 INFO L276 IsEmpty]: Start isEmpty. Operand 570 states and 781 transitions. [2019-12-07 16:00:37,435 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 16:00:37,435 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:37,435 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:37,436 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:37,436 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:37,436 INFO L82 PathProgramCache]: Analyzing trace with hash 2083582807, now seen corresponding path program 1 times [2019-12-07 16:00:37,436 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:37,436 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1096290856] [2019-12-07 16:00:37,436 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:37,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:37,506 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:37,506 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1096290856] [2019-12-07 16:00:37,506 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:37,506 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 16:00:37,507 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618815913] [2019-12-07 16:00:37,507 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:00:37,507 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:37,507 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:00:37,507 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:00:37,507 INFO L87 Difference]: Start difference. First operand 570 states and 781 transitions. Second operand 6 states. [2019-12-07 16:00:37,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:37,818 INFO L93 Difference]: Finished difference Result 2037 states and 2828 transitions. [2019-12-07 16:00:37,818 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 16:00:37,818 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2019-12-07 16:00:37,818 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:37,824 INFO L225 Difference]: With dead ends: 2037 [2019-12-07 16:00:37,824 INFO L226 Difference]: Without dead ends: 1662 [2019-12-07 16:00:37,825 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-12-07 16:00:37,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1662 states. [2019-12-07 16:00:37,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1662 to 616. [2019-12-07 16:00:37,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 616 states. [2019-12-07 16:00:37,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 616 states to 616 states and 839 transitions. [2019-12-07 16:00:37,871 INFO L78 Accepts]: Start accepts. Automaton has 616 states and 839 transitions. Word has length 73 [2019-12-07 16:00:37,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:37,871 INFO L462 AbstractCegarLoop]: Abstraction has 616 states and 839 transitions. [2019-12-07 16:00:37,871 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:00:37,871 INFO L276 IsEmpty]: Start isEmpty. Operand 616 states and 839 transitions. [2019-12-07 16:00:37,871 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-12-07 16:00:37,872 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:37,872 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:37,872 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:37,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:37,872 INFO L82 PathProgramCache]: Analyzing trace with hash 1204676769, now seen corresponding path program 1 times [2019-12-07 16:00:37,872 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:37,872 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1649876581] [2019-12-07 16:00:37,872 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:37,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:37,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:37,932 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1649876581] [2019-12-07 16:00:37,932 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:37,932 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 16:00:37,933 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1865386677] [2019-12-07 16:00:37,933 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:00:37,933 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:37,933 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:00:37,933 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:00:37,933 INFO L87 Difference]: Start difference. First operand 616 states and 839 transitions. Second operand 6 states. [2019-12-07 16:00:38,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:38,230 INFO L93 Difference]: Finished difference Result 2364 states and 3261 transitions. [2019-12-07 16:00:38,230 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 16:00:38,231 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 74 [2019-12-07 16:00:38,231 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:38,238 INFO L225 Difference]: With dead ends: 2364 [2019-12-07 16:00:38,238 INFO L226 Difference]: Without dead ends: 1981 [2019-12-07 16:00:38,239 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-12-07 16:00:38,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1981 states. [2019-12-07 16:00:38,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1981 to 694. [2019-12-07 16:00:38,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 694 states. [2019-12-07 16:00:38,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 694 states to 694 states and 941 transitions. [2019-12-07 16:00:38,283 INFO L78 Accepts]: Start accepts. Automaton has 694 states and 941 transitions. Word has length 74 [2019-12-07 16:00:38,283 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:38,283 INFO L462 AbstractCegarLoop]: Abstraction has 694 states and 941 transitions. [2019-12-07 16:00:38,283 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:00:38,283 INFO L276 IsEmpty]: Start isEmpty. Operand 694 states and 941 transitions. [2019-12-07 16:00:38,284 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-12-07 16:00:38,284 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:38,284 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:38,284 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:38,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:38,284 INFO L82 PathProgramCache]: Analyzing trace with hash -217796256, now seen corresponding path program 1 times [2019-12-07 16:00:38,285 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:38,285 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1400497776] [2019-12-07 16:00:38,285 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:38,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:38,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:38,332 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1400497776] [2019-12-07 16:00:38,333 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:38,333 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 16:00:38,333 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [788887431] [2019-12-07 16:00:38,333 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:00:38,333 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:38,334 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:00:38,334 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:00:38,334 INFO L87 Difference]: Start difference. First operand 694 states and 941 transitions. Second operand 6 states. [2019-12-07 16:00:38,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:38,496 INFO L93 Difference]: Finished difference Result 1560 states and 2200 transitions. [2019-12-07 16:00:38,496 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 16:00:38,496 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 74 [2019-12-07 16:00:38,497 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:38,502 INFO L225 Difference]: With dead ends: 1560 [2019-12-07 16:00:38,503 INFO L226 Difference]: Without dead ends: 1160 [2019-12-07 16:00:38,504 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2019-12-07 16:00:38,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1160 states. [2019-12-07 16:00:38,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1160 to 700. [2019-12-07 16:00:38,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 700 states. [2019-12-07 16:00:38,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 700 states to 700 states and 947 transitions. [2019-12-07 16:00:38,546 INFO L78 Accepts]: Start accepts. Automaton has 700 states and 947 transitions. Word has length 74 [2019-12-07 16:00:38,546 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:38,546 INFO L462 AbstractCegarLoop]: Abstraction has 700 states and 947 transitions. [2019-12-07 16:00:38,546 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:00:38,546 INFO L276 IsEmpty]: Start isEmpty. Operand 700 states and 947 transitions. [2019-12-07 16:00:38,547 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-12-07 16:00:38,547 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:38,547 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:38,547 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:38,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:38,548 INFO L82 PathProgramCache]: Analyzing trace with hash -1278252476, now seen corresponding path program 1 times [2019-12-07 16:00:38,548 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:38,548 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948962450] [2019-12-07 16:00:38,548 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:38,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:00:38,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:00:38,582 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1948962450] [2019-12-07 16:00:38,582 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:00:38,582 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:00:38,582 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [468192088] [2019-12-07 16:00:38,582 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:00:38,582 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:00:38,583 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:00:38,583 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:00:38,583 INFO L87 Difference]: Start difference. First operand 700 states and 947 transitions. Second operand 3 states. [2019-12-07 16:00:38,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:00:38,668 INFO L93 Difference]: Finished difference Result 1374 states and 1891 transitions. [2019-12-07 16:00:38,669 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:00:38,669 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 74 [2019-12-07 16:00:38,669 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:00:38,672 INFO L225 Difference]: With dead ends: 1374 [2019-12-07 16:00:38,672 INFO L226 Difference]: Without dead ends: 905 [2019-12-07 16:00:38,673 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:00:38,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 905 states. [2019-12-07 16:00:38,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 905 to 679. [2019-12-07 16:00:38,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 679 states. [2019-12-07 16:00:38,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 679 states to 679 states and 910 transitions. [2019-12-07 16:00:38,726 INFO L78 Accepts]: Start accepts. Automaton has 679 states and 910 transitions. Word has length 74 [2019-12-07 16:00:38,727 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:00:38,727 INFO L462 AbstractCegarLoop]: Abstraction has 679 states and 910 transitions. [2019-12-07 16:00:38,727 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:00:38,727 INFO L276 IsEmpty]: Start isEmpty. Operand 679 states and 910 transitions. [2019-12-07 16:00:38,727 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-12-07 16:00:38,727 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:00:38,728 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:00:38,728 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:00:38,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:00:38,728 INFO L82 PathProgramCache]: Analyzing trace with hash -1698648942, now seen corresponding path program 1 times [2019-12-07 16:00:38,728 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:00:38,728 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [581520792] [2019-12-07 16:00:38,728 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:00:38,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 16:00:38,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 16:00:38,802 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 16:00:38,802 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 16:00:38,881 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 04:00:38 BoogieIcfgContainer [2019-12-07 16:00:38,881 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 16:00:38,882 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 16:00:38,882 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 16:00:38,882 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 16:00:38,882 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:00:34" (3/4) ... [2019-12-07 16:00:38,884 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 16:00:38,965 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_62e78249-d907-4cec-92b9-62485cadb9fb/bin/uautomizer/witness.graphml [2019-12-07 16:00:38,965 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 16:00:38,967 INFO L168 Benchmark]: Toolchain (without parser) took 5757.59 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 249.0 MB). Free memory was 939.7 MB in the beginning and 1.2 GB in the end (delta: -222.0 MB). Peak memory consumption was 27.0 MB. Max. memory is 11.5 GB. [2019-12-07 16:00:38,967 INFO L168 Benchmark]: CDTParser took 0.22 ms. Allocated memory is still 1.0 GB. Free memory is still 955.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 16:00:38,967 INFO L168 Benchmark]: CACSL2BoogieTranslator took 286.77 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 133.7 MB). Free memory was 939.7 MB in the beginning and 1.1 GB in the end (delta: -183.4 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. [2019-12-07 16:00:38,967 INFO L168 Benchmark]: Boogie Procedure Inliner took 45.06 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 16:00:38,968 INFO L168 Benchmark]: Boogie Preprocessor took 44.29 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 16:00:38,968 INFO L168 Benchmark]: RCFGBuilder took 579.77 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 89.3 MB). Peak memory consumption was 89.3 MB. Max. memory is 11.5 GB. [2019-12-07 16:00:38,968 INFO L168 Benchmark]: TraceAbstraction took 4714.74 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 115.3 MB). Free memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: -165.5 MB). There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 16:00:38,968 INFO L168 Benchmark]: Witness Printer took 83.81 ms. Allocated memory is still 1.3 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 26.9 MB). Peak memory consumption was 26.9 MB. Max. memory is 11.5 GB. [2019-12-07 16:00:38,970 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.22 ms. Allocated memory is still 1.0 GB. Free memory is still 955.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 286.77 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 133.7 MB). Free memory was 939.7 MB in the beginning and 1.1 GB in the end (delta: -183.4 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 45.06 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 44.29 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 579.77 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 89.3 MB). Peak memory consumption was 89.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 4714.74 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 115.3 MB). Free memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: -165.5 MB). There was no memory consumed. Max. memory is 11.5 GB. * Witness Printer took 83.81 ms. Allocated memory is still 1.3 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 26.9 MB). Peak memory consumption was 26.9 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 662]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L69] msg_t nomsg = (msg_t )-1; [L70] port_t cs1 ; [L71] int8_t cs1_old ; [L72] int8_t cs1_new ; [L73] port_t cs2 ; [L74] int8_t cs2_old ; [L75] int8_t cs2_new ; [L76] port_t s1s2 ; [L77] int8_t s1s2_old ; [L78] int8_t s1s2_new ; [L79] port_t s1s1 ; [L80] int8_t s1s1_old ; [L81] int8_t s1s1_new ; [L82] port_t s2s1 ; [L83] int8_t s2s1_old ; [L84] int8_t s2s1_new ; [L85] port_t s2s2 ; [L86] int8_t s2s2_old ; [L87] int8_t s2s2_new ; [L88] port_t s1p ; [L89] int8_t s1p_old ; [L90] int8_t s1p_new ; [L91] port_t s2p ; [L92] int8_t s2p_old ; [L93] int8_t s2p_new ; [L96] _Bool side1Failed ; [L97] _Bool side2Failed ; [L98] msg_t side1_written ; [L99] msg_t side2_written ; [L102] static _Bool side1Failed_History_0 ; [L103] static _Bool side1Failed_History_1 ; [L104] static _Bool side1Failed_History_2 ; [L105] static _Bool side2Failed_History_0 ; [L106] static _Bool side2Failed_History_1 ; [L107] static _Bool side2Failed_History_2 ; [L108] static int8_t active_side_History_0 ; [L109] static int8_t active_side_History_1 ; [L110] static int8_t active_side_History_2 ; [L111] static msg_t manual_selection_History_0 ; [L112] static msg_t manual_selection_History_1 ; [L113] static msg_t manual_selection_History_2 ; [L463] void (*nodes[4])(void) = { & Console_task_each_pals_period, & Side1_activestandby_task_each_pals_period, & Side2_activestandby_task_each_pals_period, & Pendulum_prism_task_each_pals_period}; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=0, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L585] int c1 ; [L586] int i2 ; [L589] c1 = 0 [L590] side1Failed = __VERIFIER_nondet_bool() [L591] side2Failed = __VERIFIER_nondet_bool() [L592] side1_written = __VERIFIER_nondet_char() [L593] side2_written = __VERIFIER_nondet_char() [L594] side1Failed_History_0 = __VERIFIER_nondet_bool() [L595] side1Failed_History_1 = __VERIFIER_nondet_bool() [L596] side1Failed_History_2 = __VERIFIER_nondet_bool() [L597] side2Failed_History_0 = __VERIFIER_nondet_bool() [L598] side2Failed_History_1 = __VERIFIER_nondet_bool() [L599] side2Failed_History_2 = __VERIFIER_nondet_bool() [L600] active_side_History_0 = __VERIFIER_nondet_char() [L601] active_side_History_1 = __VERIFIER_nondet_char() [L602] active_side_History_2 = __VERIFIER_nondet_char() [L603] manual_selection_History_0 = __VERIFIER_nondet_char() [L604] manual_selection_History_1 = __VERIFIER_nondet_char() [L605] manual_selection_History_2 = __VERIFIER_nondet_char() [L239] COND FALSE !((int )side1Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=5, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L242] COND FALSE !((int )side2Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=5, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L245] COND FALSE !((int )active_side_History_0 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=5, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L248] COND FALSE !((int )manual_selection_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=5, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L251] COND FALSE !((int )side1Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=5, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L254] COND FALSE !((int )side2Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=5, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L257] COND FALSE !((int )active_side_History_1 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=5, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L260] COND FALSE !((int )manual_selection_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=5, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L263] COND FALSE !((int )side1Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=5, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L266] COND FALSE !((int )side2Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=5, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L269] COND FALSE !((int )active_side_History_2 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=5, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L272] COND FALSE !((int )manual_selection_History_2 != 0) [L275] return (1); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=5, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L606] i2 = init() [L608] cs1_old = nomsg [L609] cs1_new = nomsg [L610] cs2_old = nomsg [L611] cs2_new = nomsg [L612] s1s2_old = nomsg [L613] s1s2_new = nomsg [L614] s1s1_old = nomsg [L615] s1s1_new = nomsg [L616] s2s1_old = nomsg [L617] s2s1_new = nomsg [L618] s2s2_old = nomsg [L619] s2s2_new = nomsg [L620] s1p_old = nomsg [L621] s1p_new = nomsg [L622] s2p_old = nomsg [L623] s2p_new = nomsg [L624] i2 = 0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=5, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L625] COND TRUE i2 < 10 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=5, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=5, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=5, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=5, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND FALSE !(\read(side1Failed)) [L326] side1 = s1s1_old [L327] s1s1_old = nomsg [L328] side2 = s2s1_old [L329] s2s1_old = nomsg [L330] manual_selection = cs1_old [L331] cs1_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L332] COND TRUE (int )side1 == (int )side2 [L333] next_state = (int8_t )1 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L356] EXPR next_state != nomsg && s1s1_new == nomsg ? next_state : s1s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L356] s1s1_new = next_state != nomsg && s1s1_new == nomsg ? next_state : s1s1_new [L357] EXPR next_state != nomsg && s1s2_new == nomsg ? next_state : s1s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L357] s1s2_new = next_state != nomsg && s1s2_new == nomsg ? next_state : s1s2_new [L358] EXPR next_state != nomsg && s1p_new == nomsg ? next_state : s1p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L358] s1p_new = next_state != nomsg && s1p_new == nomsg ? next_state : s1p_new [L359] side1_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=4, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND TRUE (int )side1 == (int )side2 [L390] next_state = (int8_t )1 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] side2_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L450] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L451] COND FALSE !((int )side2 == 0) [L454] active_side = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L631] cs1_old = cs1_new [L632] cs1_new = nomsg [L633] cs2_old = cs2_new [L634] cs2_new = nomsg [L635] s1s2_old = s1s2_new [L636] s1s2_new = nomsg [L637] s1s1_old = s1s1_new [L638] s1s1_new = nomsg [L639] s2s1_old = s2s1_new [L640] s2s1_new = nomsg [L641] s2s2_old = s2s2_new [L642] s2s2_new = nomsg [L643] s1p_old = s1p_new [L644] s1p_new = nomsg [L645] s2p_old = s2p_new [L646] s2p_new = nomsg [L466] int tmp ; [L467] msg_t tmp___0 ; [L468] _Bool tmp___1 ; [L469] _Bool tmp___2 ; [L470] _Bool tmp___3 ; [L471] _Bool tmp___4 ; [L472] int8_t tmp___5 ; [L473] _Bool tmp___6 ; [L474] _Bool tmp___7 ; [L475] _Bool tmp___8 ; [L476] int8_t tmp___9 ; [L477] _Bool tmp___10 ; [L478] _Bool tmp___11 ; [L479] _Bool tmp___12 ; [L480] msg_t tmp___13 ; [L481] _Bool tmp___14 ; [L482] _Bool tmp___15 ; [L483] _Bool tmp___16 ; [L484] _Bool tmp___17 ; [L485] int8_t tmp___18 ; [L486] int8_t tmp___19 ; [L487] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L490] COND TRUE ! side1Failed [L491] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L499] tmp___0 = read_manual_selection_history((unsigned char)1) [L500] COND TRUE ! tmp___0 [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L501] tmp___1 = read_side1_failed_history((unsigned char)1) [L502] COND TRUE ! tmp___1 [L130] COND TRUE (int )index == 0 [L131] return (side1Failed_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L503] tmp___2 = read_side1_failed_history((unsigned char)0) [L504] COND TRUE ! tmp___2 [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L505] tmp___3 = read_side2_failed_history((unsigned char)1) [L506] COND TRUE ! tmp___3 [L160] COND TRUE (int )index == 0 [L161] return (side2Failed_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L507] tmp___4 = read_side2_failed_history((unsigned char)0) [L508] COND TRUE ! tmp___4 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L509] COND FALSE !(! ((int )side1_written == 1)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L514] COND FALSE !(! (! ((int )side1_written == 0))) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L519] COND TRUE ! (! ((int )side1_written == 1)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L520] COND TRUE ! ((int )side2_written == 0) [L521] return (0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L647] c1 = check() [L660] COND TRUE ! arg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L662] __VERIFIER_error() VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 293 locations, 23 error locations. Result: UNSAFE, OverallTime: 4.5s, OverallIterations: 21, TraceHistogramMax: 1, AutomataDifference: 2.5s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 9033 SDtfs, 12752 SDslu, 14301 SDs, 0 SdLazy, 1331 SolverSat, 143 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 164 GetRequests, 63 SyntacticMatches, 8 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 61 ImplicationChecksByTransitivity, 0.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=700occurred in iteration=19, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.5s AutomataMinimizationTime, 20 MinimizatonAttempts, 6942 StatesRemovedByMinimization, 18 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 0.8s InterpolantComputationTime, 1320 NumberOfCodeBlocks, 1320 NumberOfCodeBlocksAsserted, 21 NumberOfCheckSat, 1225 ConstructedInterpolants, 0 QuantifiedInterpolants, 255377 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 20 InterpolantComputations, 20 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...