./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c -s /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 51b120a585d23a491f06d4bb80c2a463453987ac ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 16:02:07,432 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 16:02:07,433 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 16:02:07,442 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 16:02:07,442 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 16:02:07,443 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 16:02:07,444 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 16:02:07,445 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 16:02:07,447 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 16:02:07,448 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 16:02:07,449 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 16:02:07,450 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 16:02:07,450 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 16:02:07,451 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 16:02:07,451 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 16:02:07,453 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 16:02:07,453 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 16:02:07,454 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 16:02:07,456 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 16:02:07,457 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 16:02:07,459 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 16:02:07,460 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 16:02:07,461 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 16:02:07,461 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 16:02:07,464 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 16:02:07,464 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 16:02:07,464 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 16:02:07,465 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 16:02:07,465 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 16:02:07,466 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 16:02:07,466 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 16:02:07,466 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 16:02:07,467 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 16:02:07,467 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 16:02:07,468 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 16:02:07,468 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 16:02:07,469 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 16:02:07,469 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 16:02:07,469 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 16:02:07,470 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 16:02:07,470 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 16:02:07,471 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 16:02:07,482 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 16:02:07,483 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 16:02:07,483 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 16:02:07,484 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 16:02:07,484 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 16:02:07,484 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 16:02:07,484 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 16:02:07,484 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 16:02:07,484 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 16:02:07,484 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 16:02:07,484 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 16:02:07,485 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 16:02:07,485 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 16:02:07,485 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 16:02:07,485 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 16:02:07,485 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 16:02:07,485 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 16:02:07,486 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 16:02:07,486 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 16:02:07,486 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 16:02:07,486 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 16:02:07,486 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 16:02:07,486 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 16:02:07,486 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 16:02:07,487 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 16:02:07,487 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 16:02:07,487 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 16:02:07,487 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 16:02:07,487 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 16:02:07,487 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 51b120a585d23a491f06d4bb80c2a463453987ac [2019-12-07 16:02:07,595 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 16:02:07,602 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 16:02:07,605 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 16:02:07,606 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 16:02:07,606 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 16:02:07,606 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer/../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c [2019-12-07 16:02:07,643 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer/data/9c0ff757d/e00f888dc5e04def8ece74d024cc27de/FLAG9f9727fda [2019-12-07 16:02:08,068 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 16:02:08,068 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c [2019-12-07 16:02:08,075 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer/data/9c0ff757d/e00f888dc5e04def8ece74d024cc27de/FLAG9f9727fda [2019-12-07 16:02:08,084 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer/data/9c0ff757d/e00f888dc5e04def8ece74d024cc27de [2019-12-07 16:02:08,086 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 16:02:08,086 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 16:02:08,087 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 16:02:08,087 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 16:02:08,089 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 16:02:08,090 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 04:02:08" (1/1) ... [2019-12-07 16:02:08,091 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2c2b2671 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:02:08, skipping insertion in model container [2019-12-07 16:02:08,092 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 04:02:08" (1/1) ... [2019-12-07 16:02:08,096 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 16:02:08,121 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 16:02:08,322 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 16:02:08,328 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 16:02:08,371 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 16:02:08,384 INFO L208 MainTranslator]: Completed translation [2019-12-07 16:02:08,384 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:02:08 WrapperNode [2019-12-07 16:02:08,384 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 16:02:08,385 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 16:02:08,385 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 16:02:08,385 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 16:02:08,390 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:02:08" (1/1) ... [2019-12-07 16:02:08,399 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:02:08" (1/1) ... [2019-12-07 16:02:08,429 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 16:02:08,429 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 16:02:08,429 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 16:02:08,429 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 16:02:08,435 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:02:08" (1/1) ... [2019-12-07 16:02:08,436 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:02:08" (1/1) ... [2019-12-07 16:02:08,440 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:02:08" (1/1) ... [2019-12-07 16:02:08,440 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:02:08" (1/1) ... [2019-12-07 16:02:08,451 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:02:08" (1/1) ... [2019-12-07 16:02:08,459 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:02:08" (1/1) ... [2019-12-07 16:02:08,462 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:02:08" (1/1) ... [2019-12-07 16:02:08,467 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 16:02:08,467 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 16:02:08,467 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 16:02:08,467 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 16:02:08,468 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:02:08" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 16:02:08,515 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 16:02:08,515 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 16:02:09,064 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 16:02:09,064 INFO L287 CfgBuilder]: Removed 119 assume(true) statements. [2019-12-07 16:02:09,065 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:02:09 BoogieIcfgContainer [2019-12-07 16:02:09,065 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 16:02:09,065 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 16:02:09,065 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 16:02:09,067 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 16:02:09,067 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 04:02:08" (1/3) ... [2019-12-07 16:02:09,068 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@539b72e4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 04:02:09, skipping insertion in model container [2019-12-07 16:02:09,068 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:02:08" (2/3) ... [2019-12-07 16:02:09,068 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@539b72e4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 04:02:09, skipping insertion in model container [2019-12-07 16:02:09,068 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:02:09" (3/3) ... [2019-12-07 16:02:09,069 INFO L109 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c [2019-12-07 16:02:09,076 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 16:02:09,081 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 23 error locations. [2019-12-07 16:02:09,088 INFO L249 AbstractCegarLoop]: Starting to check reachability of 23 error locations. [2019-12-07 16:02:09,106 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 16:02:09,106 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 16:02:09,106 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 16:02:09,106 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 16:02:09,106 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 16:02:09,106 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 16:02:09,106 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 16:02:09,106 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 16:02:09,124 INFO L276 IsEmpty]: Start isEmpty. Operand 290 states. [2019-12-07 16:02:09,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 16:02:09,129 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:09,129 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:09,130 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:09,134 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:09,134 INFO L82 PathProgramCache]: Analyzing trace with hash 211735483, now seen corresponding path program 1 times [2019-12-07 16:02:09,140 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:09,140 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411477538] [2019-12-07 16:02:09,140 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:09,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:09,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:09,273 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [411477538] [2019-12-07 16:02:09,274 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:09,274 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:02:09,275 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2118085855] [2019-12-07 16:02:09,278 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:02:09,279 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:09,287 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:02:09,288 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:02:09,289 INFO L87 Difference]: Start difference. First operand 290 states. Second operand 3 states. [2019-12-07 16:02:09,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:09,353 INFO L93 Difference]: Finished difference Result 562 states and 879 transitions. [2019-12-07 16:02:09,354 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:02:09,355 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 31 [2019-12-07 16:02:09,355 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:09,367 INFO L225 Difference]: With dead ends: 562 [2019-12-07 16:02:09,367 INFO L226 Difference]: Without dead ends: 286 [2019-12-07 16:02:09,371 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:02:09,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 286 states. [2019-12-07 16:02:09,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 286 to 286. [2019-12-07 16:02:09,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 286 states. [2019-12-07 16:02:09,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 286 states to 286 states and 408 transitions. [2019-12-07 16:02:09,409 INFO L78 Accepts]: Start accepts. Automaton has 286 states and 408 transitions. Word has length 31 [2019-12-07 16:02:09,410 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:09,410 INFO L462 AbstractCegarLoop]: Abstraction has 286 states and 408 transitions. [2019-12-07 16:02:09,410 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:02:09,410 INFO L276 IsEmpty]: Start isEmpty. Operand 286 states and 408 transitions. [2019-12-07 16:02:09,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-12-07 16:02:09,411 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:09,411 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:09,412 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:09,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:09,412 INFO L82 PathProgramCache]: Analyzing trace with hash -1187444686, now seen corresponding path program 1 times [2019-12-07 16:02:09,412 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:09,412 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [62638959] [2019-12-07 16:02:09,412 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:09,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:09,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:09,512 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [62638959] [2019-12-07 16:02:09,512 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:09,512 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:02:09,513 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [863242573] [2019-12-07 16:02:09,514 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:02:09,514 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:09,514 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:02:09,514 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:02:09,514 INFO L87 Difference]: Start difference. First operand 286 states and 408 transitions. Second operand 3 states. [2019-12-07 16:02:09,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:09,553 INFO L93 Difference]: Finished difference Result 590 states and 850 transitions. [2019-12-07 16:02:09,553 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:02:09,553 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 42 [2019-12-07 16:02:09,553 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:09,556 INFO L225 Difference]: With dead ends: 590 [2019-12-07 16:02:09,556 INFO L226 Difference]: Without dead ends: 319 [2019-12-07 16:02:09,558 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:02:09,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 319 states. [2019-12-07 16:02:09,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 319 to 262. [2019-12-07 16:02:09,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 262 states. [2019-12-07 16:02:09,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 262 states to 262 states and 372 transitions. [2019-12-07 16:02:09,576 INFO L78 Accepts]: Start accepts. Automaton has 262 states and 372 transitions. Word has length 42 [2019-12-07 16:02:09,577 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:09,577 INFO L462 AbstractCegarLoop]: Abstraction has 262 states and 372 transitions. [2019-12-07 16:02:09,577 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:02:09,577 INFO L276 IsEmpty]: Start isEmpty. Operand 262 states and 372 transitions. [2019-12-07 16:02:09,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-12-07 16:02:09,579 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:09,579 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:09,579 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:09,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:09,580 INFO L82 PathProgramCache]: Analyzing trace with hash -365626229, now seen corresponding path program 1 times [2019-12-07 16:02:09,580 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:09,580 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1845495911] [2019-12-07 16:02:09,580 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:09,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:09,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:09,659 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1845495911] [2019-12-07 16:02:09,660 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:09,660 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:02:09,660 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [652067866] [2019-12-07 16:02:09,661 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:02:09,661 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:09,661 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:02:09,661 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:02:09,661 INFO L87 Difference]: Start difference. First operand 262 states and 372 transitions. Second operand 3 states. [2019-12-07 16:02:09,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:09,689 INFO L93 Difference]: Finished difference Result 733 states and 1051 transitions. [2019-12-07 16:02:09,689 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:02:09,690 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-12-07 16:02:09,690 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:09,693 INFO L225 Difference]: With dead ends: 733 [2019-12-07 16:02:09,693 INFO L226 Difference]: Without dead ends: 486 [2019-12-07 16:02:09,694 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:02:09,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 486 states. [2019-12-07 16:02:09,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 486 to 295. [2019-12-07 16:02:09,709 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 295 states. [2019-12-07 16:02:09,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 295 states to 295 states and 420 transitions. [2019-12-07 16:02:09,711 INFO L78 Accepts]: Start accepts. Automaton has 295 states and 420 transitions. Word has length 49 [2019-12-07 16:02:09,711 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:09,712 INFO L462 AbstractCegarLoop]: Abstraction has 295 states and 420 transitions. [2019-12-07 16:02:09,712 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:02:09,712 INFO L276 IsEmpty]: Start isEmpty. Operand 295 states and 420 transitions. [2019-12-07 16:02:09,714 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2019-12-07 16:02:09,714 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:09,714 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:09,714 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:09,715 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:09,715 INFO L82 PathProgramCache]: Analyzing trace with hash 744745200, now seen corresponding path program 1 times [2019-12-07 16:02:09,715 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:09,715 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [295510916] [2019-12-07 16:02:09,715 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:09,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:09,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:09,779 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [295510916] [2019-12-07 16:02:09,779 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:09,779 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:02:09,780 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [740304549] [2019-12-07 16:02:09,780 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:02:09,780 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:09,780 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:02:09,780 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:02:09,780 INFO L87 Difference]: Start difference. First operand 295 states and 420 transitions. Second operand 5 states. [2019-12-07 16:02:09,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:09,953 INFO L93 Difference]: Finished difference Result 929 states and 1337 transitions. [2019-12-07 16:02:09,954 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:02:09,954 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2019-12-07 16:02:09,954 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:09,957 INFO L225 Difference]: With dead ends: 929 [2019-12-07 16:02:09,957 INFO L226 Difference]: Without dead ends: 649 [2019-12-07 16:02:09,958 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 16:02:09,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 649 states. [2019-12-07 16:02:09,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 649 to 381. [2019-12-07 16:02:09,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 381 states. [2019-12-07 16:02:09,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 381 states to 381 states and 543 transitions. [2019-12-07 16:02:09,971 INFO L78 Accepts]: Start accepts. Automaton has 381 states and 543 transitions. Word has length 50 [2019-12-07 16:02:09,972 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:09,972 INFO L462 AbstractCegarLoop]: Abstraction has 381 states and 543 transitions. [2019-12-07 16:02:09,972 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:02:09,972 INFO L276 IsEmpty]: Start isEmpty. Operand 381 states and 543 transitions. [2019-12-07 16:02:09,973 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 16:02:09,973 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:09,974 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:09,974 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:09,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:09,974 INFO L82 PathProgramCache]: Analyzing trace with hash 1614483527, now seen corresponding path program 1 times [2019-12-07 16:02:09,974 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:09,975 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [69547662] [2019-12-07 16:02:09,975 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:09,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:10,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:10,032 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [69547662] [2019-12-07 16:02:10,032 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:10,032 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:02:10,033 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1599355932] [2019-12-07 16:02:10,033 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:02:10,033 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:10,033 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:02:10,033 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:02:10,034 INFO L87 Difference]: Start difference. First operand 381 states and 543 transitions. Second operand 5 states. [2019-12-07 16:02:10,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:10,189 INFO L93 Difference]: Finished difference Result 929 states and 1333 transitions. [2019-12-07 16:02:10,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:02:10,189 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-12-07 16:02:10,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:10,193 INFO L225 Difference]: With dead ends: 929 [2019-12-07 16:02:10,194 INFO L226 Difference]: Without dead ends: 649 [2019-12-07 16:02:10,194 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 16:02:10,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 649 states. [2019-12-07 16:02:10,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 649 to 381. [2019-12-07 16:02:10,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 381 states. [2019-12-07 16:02:10,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 381 states to 381 states and 541 transitions. [2019-12-07 16:02:10,210 INFO L78 Accepts]: Start accepts. Automaton has 381 states and 541 transitions. Word has length 51 [2019-12-07 16:02:10,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:10,210 INFO L462 AbstractCegarLoop]: Abstraction has 381 states and 541 transitions. [2019-12-07 16:02:10,210 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:02:10,210 INFO L276 IsEmpty]: Start isEmpty. Operand 381 states and 541 transitions. [2019-12-07 16:02:10,211 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-12-07 16:02:10,211 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:10,211 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:10,212 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:10,212 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:10,212 INFO L82 PathProgramCache]: Analyzing trace with hash 251892323, now seen corresponding path program 1 times [2019-12-07 16:02:10,212 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:10,212 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [349018872] [2019-12-07 16:02:10,212 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:10,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:10,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:10,300 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [349018872] [2019-12-07 16:02:10,300 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:10,300 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:02:10,300 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386651629] [2019-12-07 16:02:10,300 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:02:10,301 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:10,301 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:02:10,301 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:02:10,301 INFO L87 Difference]: Start difference. First operand 381 states and 541 transitions. Second operand 5 states. [2019-12-07 16:02:10,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:10,338 INFO L93 Difference]: Finished difference Result 757 states and 1086 transitions. [2019-12-07 16:02:10,338 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 16:02:10,338 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 52 [2019-12-07 16:02:10,338 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:10,340 INFO L225 Difference]: With dead ends: 757 [2019-12-07 16:02:10,340 INFO L226 Difference]: Without dead ends: 477 [2019-12-07 16:02:10,341 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:02:10,342 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 477 states. [2019-12-07 16:02:10,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 477 to 376. [2019-12-07 16:02:10,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 376 states. [2019-12-07 16:02:10,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 376 states to 376 states and 533 transitions. [2019-12-07 16:02:10,352 INFO L78 Accepts]: Start accepts. Automaton has 376 states and 533 transitions. Word has length 52 [2019-12-07 16:02:10,353 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:10,353 INFO L462 AbstractCegarLoop]: Abstraction has 376 states and 533 transitions. [2019-12-07 16:02:10,353 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:02:10,353 INFO L276 IsEmpty]: Start isEmpty. Operand 376 states and 533 transitions. [2019-12-07 16:02:10,353 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 16:02:10,353 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:10,353 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:10,354 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:10,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:10,354 INFO L82 PathProgramCache]: Analyzing trace with hash -1519937093, now seen corresponding path program 1 times [2019-12-07 16:02:10,354 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:10,354 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412487558] [2019-12-07 16:02:10,354 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:10,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:10,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:10,436 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [412487558] [2019-12-07 16:02:10,436 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:10,436 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:02:10,436 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1834076712] [2019-12-07 16:02:10,436 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:02:10,436 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:10,437 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:02:10,437 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:02:10,437 INFO L87 Difference]: Start difference. First operand 376 states and 533 transitions. Second operand 5 states. [2019-12-07 16:02:10,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:10,515 INFO L93 Difference]: Finished difference Result 788 states and 1135 transitions. [2019-12-07 16:02:10,516 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:02:10,516 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2019-12-07 16:02:10,516 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:10,518 INFO L225 Difference]: With dead ends: 788 [2019-12-07 16:02:10,518 INFO L226 Difference]: Without dead ends: 513 [2019-12-07 16:02:10,519 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:02:10,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 513 states. [2019-12-07 16:02:10,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 513 to 346. [2019-12-07 16:02:10,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 346 states. [2019-12-07 16:02:10,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 346 states to 346 states and 487 transitions. [2019-12-07 16:02:10,531 INFO L78 Accepts]: Start accepts. Automaton has 346 states and 487 transitions. Word has length 56 [2019-12-07 16:02:10,531 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:10,531 INFO L462 AbstractCegarLoop]: Abstraction has 346 states and 487 transitions. [2019-12-07 16:02:10,531 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:02:10,531 INFO L276 IsEmpty]: Start isEmpty. Operand 346 states and 487 transitions. [2019-12-07 16:02:10,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-12-07 16:02:10,532 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:10,532 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:10,532 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:10,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:10,532 INFO L82 PathProgramCache]: Analyzing trace with hash 1786376721, now seen corresponding path program 1 times [2019-12-07 16:02:10,533 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:10,533 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209816747] [2019-12-07 16:02:10,533 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:10,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:10,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:10,617 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1209816747] [2019-12-07 16:02:10,617 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:10,617 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:02:10,617 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [139717468] [2019-12-07 16:02:10,618 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:02:10,618 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:10,618 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:02:10,618 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:02:10,618 INFO L87 Difference]: Start difference. First operand 346 states and 487 transitions. Second operand 5 states. [2019-12-07 16:02:10,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:10,710 INFO L93 Difference]: Finished difference Result 880 states and 1256 transitions. [2019-12-07 16:02:10,710 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:02:10,710 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 61 [2019-12-07 16:02:10,710 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:10,713 INFO L225 Difference]: With dead ends: 880 [2019-12-07 16:02:10,713 INFO L226 Difference]: Without dead ends: 635 [2019-12-07 16:02:10,713 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:02:10,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 635 states. [2019-12-07 16:02:10,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 635 to 316. [2019-12-07 16:02:10,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 316 states. [2019-12-07 16:02:10,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 316 states to 316 states and 441 transitions. [2019-12-07 16:02:10,727 INFO L78 Accepts]: Start accepts. Automaton has 316 states and 441 transitions. Word has length 61 [2019-12-07 16:02:10,728 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:10,728 INFO L462 AbstractCegarLoop]: Abstraction has 316 states and 441 transitions. [2019-12-07 16:02:10,728 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:02:10,728 INFO L276 IsEmpty]: Start isEmpty. Operand 316 states and 441 transitions. [2019-12-07 16:02:10,728 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 16:02:10,728 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:10,729 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:10,729 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:10,729 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:10,729 INFO L82 PathProgramCache]: Analyzing trace with hash -1245848025, now seen corresponding path program 1 times [2019-12-07 16:02:10,729 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:10,729 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [380686001] [2019-12-07 16:02:10,729 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:10,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:10,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:10,817 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [380686001] [2019-12-07 16:02:10,817 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:10,817 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 16:02:10,817 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1588151456] [2019-12-07 16:02:10,817 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:02:10,817 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:10,818 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:02:10,818 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:02:10,818 INFO L87 Difference]: Start difference. First operand 316 states and 441 transitions. Second operand 6 states. [2019-12-07 16:02:10,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:10,969 INFO L93 Difference]: Finished difference Result 1074 states and 1513 transitions. [2019-12-07 16:02:10,969 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 16:02:10,970 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 66 [2019-12-07 16:02:10,970 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:10,974 INFO L225 Difference]: With dead ends: 1074 [2019-12-07 16:02:10,975 INFO L226 Difference]: Without dead ends: 859 [2019-12-07 16:02:10,976 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-12-07 16:02:10,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 859 states. [2019-12-07 16:02:11,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 859 to 355. [2019-12-07 16:02:11,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 355 states. [2019-12-07 16:02:11,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 355 states to 355 states and 495 transitions. [2019-12-07 16:02:11,005 INFO L78 Accepts]: Start accepts. Automaton has 355 states and 495 transitions. Word has length 66 [2019-12-07 16:02:11,006 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:11,006 INFO L462 AbstractCegarLoop]: Abstraction has 355 states and 495 transitions. [2019-12-07 16:02:11,006 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:02:11,006 INFO L276 IsEmpty]: Start isEmpty. Operand 355 states and 495 transitions. [2019-12-07 16:02:11,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 16:02:11,006 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:11,006 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:11,007 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:11,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:11,007 INFO L82 PathProgramCache]: Analyzing trace with hash 1591247394, now seen corresponding path program 1 times [2019-12-07 16:02:11,007 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:11,007 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [612180324] [2019-12-07 16:02:11,007 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:11,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:11,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:11,046 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [612180324] [2019-12-07 16:02:11,047 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:11,047 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:02:11,047 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1704640123] [2019-12-07 16:02:11,047 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:02:11,047 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:11,048 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:02:11,048 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:02:11,048 INFO L87 Difference]: Start difference. First operand 355 states and 495 transitions. Second operand 3 states. [2019-12-07 16:02:11,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:11,087 INFO L93 Difference]: Finished difference Result 647 states and 912 transitions. [2019-12-07 16:02:11,088 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:02:11,088 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 16:02:11,088 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:11,090 INFO L225 Difference]: With dead ends: 647 [2019-12-07 16:02:11,090 INFO L226 Difference]: Without dead ends: 432 [2019-12-07 16:02:11,091 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:02:11,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 432 states. [2019-12-07 16:02:11,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 432 to 351. [2019-12-07 16:02:11,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 351 states. [2019-12-07 16:02:11,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 351 states to 351 states and 488 transitions. [2019-12-07 16:02:11,106 INFO L78 Accepts]: Start accepts. Automaton has 351 states and 488 transitions. Word has length 67 [2019-12-07 16:02:11,106 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:11,107 INFO L462 AbstractCegarLoop]: Abstraction has 351 states and 488 transitions. [2019-12-07 16:02:11,107 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:02:11,107 INFO L276 IsEmpty]: Start isEmpty. Operand 351 states and 488 transitions. [2019-12-07 16:02:11,107 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 16:02:11,107 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:11,108 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:11,108 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:11,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:11,108 INFO L82 PathProgramCache]: Analyzing trace with hash 480130565, now seen corresponding path program 1 times [2019-12-07 16:02:11,108 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:11,109 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1224116252] [2019-12-07 16:02:11,109 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:11,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:11,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:11,145 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1224116252] [2019-12-07 16:02:11,146 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:11,146 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:02:11,146 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1122240822] [2019-12-07 16:02:11,146 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:02:11,146 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:11,146 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:02:11,146 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:02:11,146 INFO L87 Difference]: Start difference. First operand 351 states and 488 transitions. Second operand 4 states. [2019-12-07 16:02:11,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:11,233 INFO L93 Difference]: Finished difference Result 933 states and 1300 transitions. [2019-12-07 16:02:11,233 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:02:11,233 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 70 [2019-12-07 16:02:11,234 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:11,236 INFO L225 Difference]: With dead ends: 933 [2019-12-07 16:02:11,236 INFO L226 Difference]: Without dead ends: 712 [2019-12-07 16:02:11,237 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:02:11,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 712 states. [2019-12-07 16:02:11,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 712 to 517. [2019-12-07 16:02:11,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 517 states. [2019-12-07 16:02:11,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 517 states to 517 states and 715 transitions. [2019-12-07 16:02:11,258 INFO L78 Accepts]: Start accepts. Automaton has 517 states and 715 transitions. Word has length 70 [2019-12-07 16:02:11,258 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:11,258 INFO L462 AbstractCegarLoop]: Abstraction has 517 states and 715 transitions. [2019-12-07 16:02:11,258 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:02:11,259 INFO L276 IsEmpty]: Start isEmpty. Operand 517 states and 715 transitions. [2019-12-07 16:02:11,259 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 16:02:11,259 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:11,259 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:11,259 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:11,260 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:11,260 INFO L82 PathProgramCache]: Analyzing trace with hash -1523824051, now seen corresponding path program 1 times [2019-12-07 16:02:11,260 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:11,260 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640624755] [2019-12-07 16:02:11,260 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:11,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:11,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:11,289 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [640624755] [2019-12-07 16:02:11,289 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:11,290 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:02:11,290 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [265912360] [2019-12-07 16:02:11,290 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:02:11,290 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:11,290 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:02:11,290 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:02:11,290 INFO L87 Difference]: Start difference. First operand 517 states and 715 transitions. Second operand 3 states. [2019-12-07 16:02:11,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:11,326 INFO L93 Difference]: Finished difference Result 1220 states and 1679 transitions. [2019-12-07 16:02:11,326 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:02:11,327 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2019-12-07 16:02:11,327 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:11,330 INFO L225 Difference]: With dead ends: 1220 [2019-12-07 16:02:11,330 INFO L226 Difference]: Without dead ends: 850 [2019-12-07 16:02:11,331 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:02:11,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 850 states. [2019-12-07 16:02:11,354 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 850 to 578. [2019-12-07 16:02:11,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 578 states. [2019-12-07 16:02:11,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 578 states to 578 states and 792 transitions. [2019-12-07 16:02:11,355 INFO L78 Accepts]: Start accepts. Automaton has 578 states and 792 transitions. Word has length 70 [2019-12-07 16:02:11,356 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:11,356 INFO L462 AbstractCegarLoop]: Abstraction has 578 states and 792 transitions. [2019-12-07 16:02:11,356 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:02:11,356 INFO L276 IsEmpty]: Start isEmpty. Operand 578 states and 792 transitions. [2019-12-07 16:02:11,356 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 16:02:11,356 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:11,357 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:11,357 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:11,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:11,357 INFO L82 PathProgramCache]: Analyzing trace with hash -1383275441, now seen corresponding path program 1 times [2019-12-07 16:02:11,357 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:11,357 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994810436] [2019-12-07 16:02:11,357 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:11,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:11,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:11,387 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1994810436] [2019-12-07 16:02:11,387 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:11,387 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:02:11,387 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2031708804] [2019-12-07 16:02:11,387 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:02:11,387 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:11,387 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:02:11,388 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:02:11,388 INFO L87 Difference]: Start difference. First operand 578 states and 792 transitions. Second operand 3 states. [2019-12-07 16:02:11,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:11,409 INFO L93 Difference]: Finished difference Result 982 states and 1355 transitions. [2019-12-07 16:02:11,409 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:02:11,409 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2019-12-07 16:02:11,409 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:11,411 INFO L225 Difference]: With dead ends: 982 [2019-12-07 16:02:11,411 INFO L226 Difference]: Without dead ends: 543 [2019-12-07 16:02:11,412 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:02:11,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 543 states. [2019-12-07 16:02:11,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 543 to 543. [2019-12-07 16:02:11,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 543 states. [2019-12-07 16:02:11,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 543 states to 543 states and 743 transitions. [2019-12-07 16:02:11,433 INFO L78 Accepts]: Start accepts. Automaton has 543 states and 743 transitions. Word has length 70 [2019-12-07 16:02:11,434 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:11,434 INFO L462 AbstractCegarLoop]: Abstraction has 543 states and 743 transitions. [2019-12-07 16:02:11,434 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:02:11,434 INFO L276 IsEmpty]: Start isEmpty. Operand 543 states and 743 transitions. [2019-12-07 16:02:11,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-12-07 16:02:11,434 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:11,434 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:11,435 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:11,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:11,435 INFO L82 PathProgramCache]: Analyzing trace with hash -1837662732, now seen corresponding path program 1 times [2019-12-07 16:02:11,435 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:11,435 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [801057858] [2019-12-07 16:02:11,435 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:11,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:11,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:11,515 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [801057858] [2019-12-07 16:02:11,515 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:11,515 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 16:02:11,515 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [295453529] [2019-12-07 16:02:11,515 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:02:11,515 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:11,516 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:02:11,516 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:02:11,516 INFO L87 Difference]: Start difference. First operand 543 states and 743 transitions. Second operand 6 states. [2019-12-07 16:02:11,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:11,721 INFO L93 Difference]: Finished difference Result 1703 states and 2366 transitions. [2019-12-07 16:02:11,722 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 16:02:11,722 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 71 [2019-12-07 16:02:11,722 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:11,729 INFO L225 Difference]: With dead ends: 1703 [2019-12-07 16:02:11,729 INFO L226 Difference]: Without dead ends: 1380 [2019-12-07 16:02:11,730 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-12-07 16:02:11,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1380 states. [2019-12-07 16:02:11,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1380 to 547. [2019-12-07 16:02:11,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 547 states. [2019-12-07 16:02:11,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 547 states to 547 states and 748 transitions. [2019-12-07 16:02:11,772 INFO L78 Accepts]: Start accepts. Automaton has 547 states and 748 transitions. Word has length 71 [2019-12-07 16:02:11,772 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:11,772 INFO L462 AbstractCegarLoop]: Abstraction has 547 states and 748 transitions. [2019-12-07 16:02:11,772 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:02:11,772 INFO L276 IsEmpty]: Start isEmpty. Operand 547 states and 748 transitions. [2019-12-07 16:02:11,773 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-12-07 16:02:11,773 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:11,774 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:11,774 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:11,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:11,774 INFO L82 PathProgramCache]: Analyzing trace with hash 276642491, now seen corresponding path program 1 times [2019-12-07 16:02:11,774 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:11,775 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [959131913] [2019-12-07 16:02:11,775 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:11,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:11,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:11,836 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [959131913] [2019-12-07 16:02:11,836 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:11,836 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:02:11,836 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1192649191] [2019-12-07 16:02:11,837 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:02:11,837 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:11,837 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:02:11,837 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:02:11,837 INFO L87 Difference]: Start difference. First operand 547 states and 748 transitions. Second operand 5 states. [2019-12-07 16:02:11,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:11,927 INFO L93 Difference]: Finished difference Result 856 states and 1187 transitions. [2019-12-07 16:02:11,927 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:02:11,927 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 71 [2019-12-07 16:02:11,927 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:11,930 INFO L225 Difference]: With dead ends: 856 [2019-12-07 16:02:11,930 INFO L226 Difference]: Without dead ends: 854 [2019-12-07 16:02:11,931 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 16:02:11,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 854 states. [2019-12-07 16:02:11,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 854 to 549. [2019-12-07 16:02:11,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 549 states. [2019-12-07 16:02:11,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 549 states and 750 transitions. [2019-12-07 16:02:11,954 INFO L78 Accepts]: Start accepts. Automaton has 549 states and 750 transitions. Word has length 71 [2019-12-07 16:02:11,954 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:11,954 INFO L462 AbstractCegarLoop]: Abstraction has 549 states and 750 transitions. [2019-12-07 16:02:11,954 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:02:11,955 INFO L276 IsEmpty]: Start isEmpty. Operand 549 states and 750 transitions. [2019-12-07 16:02:11,955 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-12-07 16:02:11,955 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:11,955 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:11,955 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:11,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:11,956 INFO L82 PathProgramCache]: Analyzing trace with hash -66828782, now seen corresponding path program 1 times [2019-12-07 16:02:11,956 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:11,956 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1690819873] [2019-12-07 16:02:11,956 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:11,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:12,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:12,018 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1690819873] [2019-12-07 16:02:12,019 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:12,019 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 16:02:12,019 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1023666608] [2019-12-07 16:02:12,019 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:02:12,019 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:12,019 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:02:12,019 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:02:12,019 INFO L87 Difference]: Start difference. First operand 549 states and 750 transitions. Second operand 6 states. [2019-12-07 16:02:12,347 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:12,347 INFO L93 Difference]: Finished difference Result 1970 states and 2711 transitions. [2019-12-07 16:02:12,347 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 16:02:12,347 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 71 [2019-12-07 16:02:12,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:12,353 INFO L225 Difference]: With dead ends: 1970 [2019-12-07 16:02:12,353 INFO L226 Difference]: Without dead ends: 1606 [2019-12-07 16:02:12,354 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-12-07 16:02:12,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1606 states. [2019-12-07 16:02:12,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1606 to 595. [2019-12-07 16:02:12,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 595 states. [2019-12-07 16:02:12,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 595 states to 595 states and 808 transitions. [2019-12-07 16:02:12,386 INFO L78 Accepts]: Start accepts. Automaton has 595 states and 808 transitions. Word has length 71 [2019-12-07 16:02:12,386 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:12,386 INFO L462 AbstractCegarLoop]: Abstraction has 595 states and 808 transitions. [2019-12-07 16:02:12,386 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:02:12,386 INFO L276 IsEmpty]: Start isEmpty. Operand 595 states and 808 transitions. [2019-12-07 16:02:12,387 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 16:02:12,387 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:12,387 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:12,387 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:12,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:12,387 INFO L82 PathProgramCache]: Analyzing trace with hash -624478278, now seen corresponding path program 1 times [2019-12-07 16:02:12,387 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:12,387 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [946980030] [2019-12-07 16:02:12,388 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:12,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:12,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:12,450 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [946980030] [2019-12-07 16:02:12,450 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:12,450 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 16:02:12,450 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [692104873] [2019-12-07 16:02:12,451 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:02:12,451 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:12,451 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:02:12,451 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:02:12,451 INFO L87 Difference]: Start difference. First operand 595 states and 808 transitions. Second operand 6 states. [2019-12-07 16:02:12,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:12,730 INFO L93 Difference]: Finished difference Result 2296 states and 3143 transitions. [2019-12-07 16:02:12,731 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 16:02:12,731 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 72 [2019-12-07 16:02:12,731 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:12,737 INFO L225 Difference]: With dead ends: 2296 [2019-12-07 16:02:12,737 INFO L226 Difference]: Without dead ends: 1924 [2019-12-07 16:02:12,738 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-12-07 16:02:12,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1924 states. [2019-12-07 16:02:12,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1924 to 673. [2019-12-07 16:02:12,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 673 states. [2019-12-07 16:02:12,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 673 states to 673 states and 910 transitions. [2019-12-07 16:02:12,775 INFO L78 Accepts]: Start accepts. Automaton has 673 states and 910 transitions. Word has length 72 [2019-12-07 16:02:12,775 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:12,775 INFO L462 AbstractCegarLoop]: Abstraction has 673 states and 910 transitions. [2019-12-07 16:02:12,775 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:02:12,775 INFO L276 IsEmpty]: Start isEmpty. Operand 673 states and 910 transitions. [2019-12-07 16:02:12,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 16:02:12,776 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:12,776 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:12,776 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:12,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:12,777 INFO L82 PathProgramCache]: Analyzing trace with hash -2046951303, now seen corresponding path program 1 times [2019-12-07 16:02:12,777 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:12,777 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613936991] [2019-12-07 16:02:12,777 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:12,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:12,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:12,820 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [613936991] [2019-12-07 16:02:12,820 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:12,820 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 16:02:12,820 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1416877828] [2019-12-07 16:02:12,821 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:02:12,821 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:12,821 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:02:12,821 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:02:12,821 INFO L87 Difference]: Start difference. First operand 673 states and 910 transitions. Second operand 6 states. [2019-12-07 16:02:12,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:12,951 INFO L93 Difference]: Finished difference Result 1495 states and 2085 transitions. [2019-12-07 16:02:12,952 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 16:02:12,952 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 72 [2019-12-07 16:02:12,952 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:12,956 INFO L225 Difference]: With dead ends: 1495 [2019-12-07 16:02:12,956 INFO L226 Difference]: Without dead ends: 1106 [2019-12-07 16:02:12,956 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2019-12-07 16:02:12,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1106 states. [2019-12-07 16:02:12,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1106 to 679. [2019-12-07 16:02:12,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 679 states. [2019-12-07 16:02:12,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 679 states to 679 states and 916 transitions. [2019-12-07 16:02:12,992 INFO L78 Accepts]: Start accepts. Automaton has 679 states and 916 transitions. Word has length 72 [2019-12-07 16:02:12,993 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:12,993 INFO L462 AbstractCegarLoop]: Abstraction has 679 states and 916 transitions. [2019-12-07 16:02:12,993 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:02:12,993 INFO L276 IsEmpty]: Start isEmpty. Operand 679 states and 916 transitions. [2019-12-07 16:02:12,993 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 16:02:12,993 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:12,993 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:12,994 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:12,994 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:12,994 INFO L82 PathProgramCache]: Analyzing trace with hash 778464989, now seen corresponding path program 1 times [2019-12-07 16:02:12,994 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:12,994 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1683745656] [2019-12-07 16:02:12,994 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:13,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:13,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:13,021 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1683745656] [2019-12-07 16:02:13,021 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:13,021 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:02:13,021 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [690614826] [2019-12-07 16:02:13,022 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:02:13,022 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:13,022 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:02:13,022 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:02:13,022 INFO L87 Difference]: Start difference. First operand 679 states and 916 transitions. Second operand 3 states. [2019-12-07 16:02:13,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:13,089 INFO L93 Difference]: Finished difference Result 1331 states and 1818 transitions. [2019-12-07 16:02:13,089 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:02:13,090 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-12-07 16:02:13,090 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:13,093 INFO L225 Difference]: With dead ends: 1331 [2019-12-07 16:02:13,093 INFO L226 Difference]: Without dead ends: 873 [2019-12-07 16:02:13,093 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:02:13,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 873 states. [2019-12-07 16:02:13,127 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 873 to 658. [2019-12-07 16:02:13,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 658 states. [2019-12-07 16:02:13,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 658 states to 658 states and 879 transitions. [2019-12-07 16:02:13,128 INFO L78 Accepts]: Start accepts. Automaton has 658 states and 879 transitions. Word has length 72 [2019-12-07 16:02:13,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:13,129 INFO L462 AbstractCegarLoop]: Abstraction has 658 states and 879 transitions. [2019-12-07 16:02:13,129 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:02:13,129 INFO L276 IsEmpty]: Start isEmpty. Operand 658 states and 879 transitions. [2019-12-07 16:02:13,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 16:02:13,129 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:13,129 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:13,130 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:13,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:13,130 INFO L82 PathProgramCache]: Analyzing trace with hash 449594347, now seen corresponding path program 1 times [2019-12-07 16:02:13,130 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:13,130 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1945156785] [2019-12-07 16:02:13,130 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:13,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:13,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:13,159 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1945156785] [2019-12-07 16:02:13,159 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:13,159 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:02:13,160 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1943024581] [2019-12-07 16:02:13,160 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:02:13,160 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:13,160 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:02:13,160 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:02:13,160 INFO L87 Difference]: Start difference. First operand 658 states and 879 transitions. Second operand 4 states. [2019-12-07 16:02:13,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:13,277 INFO L93 Difference]: Finished difference Result 1698 states and 2278 transitions. [2019-12-07 16:02:13,277 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:02:13,278 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 73 [2019-12-07 16:02:13,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:13,282 INFO L225 Difference]: With dead ends: 1698 [2019-12-07 16:02:13,282 INFO L226 Difference]: Without dead ends: 1293 [2019-12-07 16:02:13,283 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:02:13,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1293 states. [2019-12-07 16:02:13,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1293 to 892. [2019-12-07 16:02:13,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 892 states. [2019-12-07 16:02:13,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 892 states to 892 states and 1190 transitions. [2019-12-07 16:02:13,340 INFO L78 Accepts]: Start accepts. Automaton has 892 states and 1190 transitions. Word has length 73 [2019-12-07 16:02:13,340 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:13,341 INFO L462 AbstractCegarLoop]: Abstraction has 892 states and 1190 transitions. [2019-12-07 16:02:13,341 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:02:13,341 INFO L276 IsEmpty]: Start isEmpty. Operand 892 states and 1190 transitions. [2019-12-07 16:02:13,341 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 16:02:13,342 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:13,342 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:13,342 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:13,342 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:13,342 INFO L82 PathProgramCache]: Analyzing trace with hash 1828954211, now seen corresponding path program 1 times [2019-12-07 16:02:13,342 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:13,342 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635978368] [2019-12-07 16:02:13,342 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:13,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:13,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:13,374 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1635978368] [2019-12-07 16:02:13,375 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:13,375 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:02:13,375 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [938984610] [2019-12-07 16:02:13,375 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:02:13,375 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:13,375 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:02:13,375 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:02:13,375 INFO L87 Difference]: Start difference. First operand 892 states and 1190 transitions. Second operand 3 states. [2019-12-07 16:02:13,474 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:13,474 INFO L93 Difference]: Finished difference Result 1867 states and 2508 transitions. [2019-12-07 16:02:13,475 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:02:13,475 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-12-07 16:02:13,475 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:13,479 INFO L225 Difference]: With dead ends: 1867 [2019-12-07 16:02:13,479 INFO L226 Difference]: Without dead ends: 1279 [2019-12-07 16:02:13,480 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:02:13,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1279 states. [2019-12-07 16:02:13,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1279 to 848. [2019-12-07 16:02:13,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 848 states. [2019-12-07 16:02:13,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 848 states to 848 states and 1126 transitions. [2019-12-07 16:02:13,527 INFO L78 Accepts]: Start accepts. Automaton has 848 states and 1126 transitions. Word has length 73 [2019-12-07 16:02:13,528 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:13,528 INFO L462 AbstractCegarLoop]: Abstraction has 848 states and 1126 transitions. [2019-12-07 16:02:13,528 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:02:13,528 INFO L276 IsEmpty]: Start isEmpty. Operand 848 states and 1126 transitions. [2019-12-07 16:02:13,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 16:02:13,528 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:13,528 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:13,529 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:13,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:13,529 INFO L82 PathProgramCache]: Analyzing trace with hash 1948644571, now seen corresponding path program 1 times [2019-12-07 16:02:13,529 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:13,529 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1035854418] [2019-12-07 16:02:13,529 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:13,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:13,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:13,558 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1035854418] [2019-12-07 16:02:13,558 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:13,558 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:02:13,559 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [589301197] [2019-12-07 16:02:13,559 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:02:13,559 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:13,559 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:02:13,559 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:02:13,559 INFO L87 Difference]: Start difference. First operand 848 states and 1126 transitions. Second operand 4 states. [2019-12-07 16:02:13,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:13,709 INFO L93 Difference]: Finished difference Result 1982 states and 2626 transitions. [2019-12-07 16:02:13,709 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:02:13,709 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 73 [2019-12-07 16:02:13,710 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:13,714 INFO L225 Difference]: With dead ends: 1982 [2019-12-07 16:02:13,714 INFO L226 Difference]: Without dead ends: 1423 [2019-12-07 16:02:13,715 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:02:13,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1423 states. [2019-12-07 16:02:13,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1423 to 1130. [2019-12-07 16:02:13,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1130 states. [2019-12-07 16:02:13,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1130 states to 1130 states and 1490 transitions. [2019-12-07 16:02:13,777 INFO L78 Accepts]: Start accepts. Automaton has 1130 states and 1490 transitions. Word has length 73 [2019-12-07 16:02:13,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:13,777 INFO L462 AbstractCegarLoop]: Abstraction has 1130 states and 1490 transitions. [2019-12-07 16:02:13,777 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:02:13,777 INFO L276 IsEmpty]: Start isEmpty. Operand 1130 states and 1490 transitions. [2019-12-07 16:02:13,778 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-12-07 16:02:13,778 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:13,778 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:13,778 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:13,778 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:13,778 INFO L82 PathProgramCache]: Analyzing trace with hash 1795806066, now seen corresponding path program 1 times [2019-12-07 16:02:13,779 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:13,779 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1352857497] [2019-12-07 16:02:13,779 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:13,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:13,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:13,796 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1352857497] [2019-12-07 16:02:13,796 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:13,796 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:02:13,796 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1528969080] [2019-12-07 16:02:13,796 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:02:13,796 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:13,796 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:02:13,796 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:02:13,796 INFO L87 Difference]: Start difference. First operand 1130 states and 1490 transitions. Second operand 3 states. [2019-12-07 16:02:13,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:13,967 INFO L93 Difference]: Finished difference Result 2791 states and 3670 transitions. [2019-12-07 16:02:13,968 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:02:13,968 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 74 [2019-12-07 16:02:13,968 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:13,974 INFO L225 Difference]: With dead ends: 2791 [2019-12-07 16:02:13,974 INFO L226 Difference]: Without dead ends: 1894 [2019-12-07 16:02:13,975 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:02:13,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1894 states. [2019-12-07 16:02:14,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1894 to 1132. [2019-12-07 16:02:14,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1132 states. [2019-12-07 16:02:14,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1132 states to 1132 states and 1492 transitions. [2019-12-07 16:02:14,043 INFO L78 Accepts]: Start accepts. Automaton has 1132 states and 1492 transitions. Word has length 74 [2019-12-07 16:02:14,043 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:14,043 INFO L462 AbstractCegarLoop]: Abstraction has 1132 states and 1492 transitions. [2019-12-07 16:02:14,043 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:02:14,043 INFO L276 IsEmpty]: Start isEmpty. Operand 1132 states and 1492 transitions. [2019-12-07 16:02:14,044 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-12-07 16:02:14,044 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:14,044 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:14,044 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:14,044 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:14,044 INFO L82 PathProgramCache]: Analyzing trace with hash 230569326, now seen corresponding path program 1 times [2019-12-07 16:02:14,044 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:14,044 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510209658] [2019-12-07 16:02:14,045 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:14,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:14,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:14,091 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1510209658] [2019-12-07 16:02:14,091 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:14,091 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:02:14,091 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [258807506] [2019-12-07 16:02:14,091 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:02:14,092 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:14,092 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:02:14,092 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:02:14,092 INFO L87 Difference]: Start difference. First operand 1132 states and 1492 transitions. Second operand 4 states. [2019-12-07 16:02:14,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:14,195 INFO L93 Difference]: Finished difference Result 2362 states and 3100 transitions. [2019-12-07 16:02:14,196 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:02:14,196 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 75 [2019-12-07 16:02:14,196 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:14,200 INFO L225 Difference]: With dead ends: 2362 [2019-12-07 16:02:14,200 INFO L226 Difference]: Without dead ends: 1285 [2019-12-07 16:02:14,201 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:02:14,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1285 states. [2019-12-07 16:02:14,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1285 to 945. [2019-12-07 16:02:14,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 945 states. [2019-12-07 16:02:14,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 945 states to 945 states and 1236 transitions. [2019-12-07 16:02:14,263 INFO L78 Accepts]: Start accepts. Automaton has 945 states and 1236 transitions. Word has length 75 [2019-12-07 16:02:14,264 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:14,264 INFO L462 AbstractCegarLoop]: Abstraction has 945 states and 1236 transitions. [2019-12-07 16:02:14,264 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:02:14,264 INFO L276 IsEmpty]: Start isEmpty. Operand 945 states and 1236 transitions. [2019-12-07 16:02:14,264 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2019-12-07 16:02:14,264 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:14,265 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:14,265 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:14,265 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:14,265 INFO L82 PathProgramCache]: Analyzing trace with hash -818028433, now seen corresponding path program 1 times [2019-12-07 16:02:14,265 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:14,265 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [319473289] [2019-12-07 16:02:14,265 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:14,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:14,305 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:14,305 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [319473289] [2019-12-07 16:02:14,306 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:14,306 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:02:14,306 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2093960572] [2019-12-07 16:02:14,306 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:02:14,306 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:14,306 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:02:14,306 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:02:14,307 INFO L87 Difference]: Start difference. First operand 945 states and 1236 transitions. Second operand 4 states. [2019-12-07 16:02:14,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:14,419 INFO L93 Difference]: Finished difference Result 2175 states and 2852 transitions. [2019-12-07 16:02:14,419 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:02:14,419 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 76 [2019-12-07 16:02:14,419 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:14,423 INFO L225 Difference]: With dead ends: 2175 [2019-12-07 16:02:14,424 INFO L226 Difference]: Without dead ends: 1305 [2019-12-07 16:02:14,424 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:02:14,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1305 states. [2019-12-07 16:02:14,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1305 to 891. [2019-12-07 16:02:14,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 891 states. [2019-12-07 16:02:14,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 891 states to 891 states and 1158 transitions. [2019-12-07 16:02:14,492 INFO L78 Accepts]: Start accepts. Automaton has 891 states and 1158 transitions. Word has length 76 [2019-12-07 16:02:14,492 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:14,492 INFO L462 AbstractCegarLoop]: Abstraction has 891 states and 1158 transitions. [2019-12-07 16:02:14,492 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:02:14,492 INFO L276 IsEmpty]: Start isEmpty. Operand 891 states and 1158 transitions. [2019-12-07 16:02:14,493 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2019-12-07 16:02:14,493 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:14,493 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:14,493 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:14,494 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:14,494 INFO L82 PathProgramCache]: Analyzing trace with hash 231668988, now seen corresponding path program 1 times [2019-12-07 16:02:14,494 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:14,494 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661846321] [2019-12-07 16:02:14,494 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:14,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:14,674 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:14,674 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1661846321] [2019-12-07 16:02:14,674 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1704600556] [2019-12-07 16:02:14,674 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 16:02:14,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:14,771 INFO L264 TraceCheckSpWp]: Trace formula consists of 720 conjuncts, 9 conjunts are in the unsatisfiable core [2019-12-07 16:02:14,779 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 16:02:14,842 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-12-07 16:02:14,842 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-12-07 16:02:14,842 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-12-07 16:02:14,842 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [302627433] [2019-12-07 16:02:14,843 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:02:14,843 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:14,843 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:02:14,843 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-12-07 16:02:14,843 INFO L87 Difference]: Start difference. First operand 891 states and 1158 transitions. Second operand 6 states. [2019-12-07 16:02:15,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:15,136 INFO L93 Difference]: Finished difference Result 2714 states and 3666 transitions. [2019-12-07 16:02:15,136 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 16:02:15,136 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 119 [2019-12-07 16:02:15,137 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:15,144 INFO L225 Difference]: With dead ends: 2714 [2019-12-07 16:02:15,144 INFO L226 Difference]: Without dead ends: 1964 [2019-12-07 16:02:15,145 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 116 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2019-12-07 16:02:15,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1964 states. [2019-12-07 16:02:15,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1964 to 891. [2019-12-07 16:02:15,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 891 states. [2019-12-07 16:02:15,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 891 states to 891 states and 1155 transitions. [2019-12-07 16:02:15,213 INFO L78 Accepts]: Start accepts. Automaton has 891 states and 1155 transitions. Word has length 119 [2019-12-07 16:02:15,213 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:15,213 INFO L462 AbstractCegarLoop]: Abstraction has 891 states and 1155 transitions. [2019-12-07 16:02:15,213 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:02:15,213 INFO L276 IsEmpty]: Start isEmpty. Operand 891 states and 1155 transitions. [2019-12-07 16:02:15,215 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2019-12-07 16:02:15,215 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:15,216 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:15,416 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 16:02:15,416 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:15,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:15,417 INFO L82 PathProgramCache]: Analyzing trace with hash -1539750943, now seen corresponding path program 1 times [2019-12-07 16:02:15,417 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:15,417 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1134063051] [2019-12-07 16:02:15,417 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:15,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:15,605 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:15,605 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1134063051] [2019-12-07 16:02:15,605 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1547321197] [2019-12-07 16:02:15,606 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 16:02:15,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:15,724 INFO L264 TraceCheckSpWp]: Trace formula consists of 733 conjuncts, 8 conjunts are in the unsatisfiable core [2019-12-07 16:02:15,728 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 16:02:15,790 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-12-07 16:02:15,791 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-12-07 16:02:15,791 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-12-07 16:02:15,791 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [709659910] [2019-12-07 16:02:15,791 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:02:15,791 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:15,791 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:02:15,791 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-12-07 16:02:15,792 INFO L87 Difference]: Start difference. First operand 891 states and 1155 transitions. Second operand 6 states. [2019-12-07 16:02:16,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:16,018 INFO L93 Difference]: Finished difference Result 2443 states and 3263 transitions. [2019-12-07 16:02:16,019 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 16:02:16,019 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 123 [2019-12-07 16:02:16,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:16,024 INFO L225 Difference]: With dead ends: 2443 [2019-12-07 16:02:16,024 INFO L226 Difference]: Without dead ends: 1693 [2019-12-07 16:02:16,025 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 139 GetRequests, 120 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=58, Invalid=362, Unknown=0, NotChecked=0, Total=420 [2019-12-07 16:02:16,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1693 states. [2019-12-07 16:02:16,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1693 to 891. [2019-12-07 16:02:16,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 891 states. [2019-12-07 16:02:16,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 891 states to 891 states and 1152 transitions. [2019-12-07 16:02:16,088 INFO L78 Accepts]: Start accepts. Automaton has 891 states and 1152 transitions. Word has length 123 [2019-12-07 16:02:16,088 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:16,088 INFO L462 AbstractCegarLoop]: Abstraction has 891 states and 1152 transitions. [2019-12-07 16:02:16,088 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:02:16,088 INFO L276 IsEmpty]: Start isEmpty. Operand 891 states and 1152 transitions. [2019-12-07 16:02:16,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2019-12-07 16:02:16,089 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:16,090 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:16,290 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 16:02:16,291 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:16,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:16,292 INFO L82 PathProgramCache]: Analyzing trace with hash 1067023105, now seen corresponding path program 1 times [2019-12-07 16:02:16,292 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:16,292 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [612725883] [2019-12-07 16:02:16,293 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:16,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:16,545 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:16,546 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [612725883] [2019-12-07 16:02:16,546 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [54220589] [2019-12-07 16:02:16,546 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 16:02:16,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:16,648 INFO L264 TraceCheckSpWp]: Trace formula consists of 745 conjuncts, 12 conjunts are in the unsatisfiable core [2019-12-07 16:02:16,651 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 16:02:16,712 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-12-07 16:02:16,712 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-12-07 16:02:16,712 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-12-07 16:02:16,712 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [466286909] [2019-12-07 16:02:16,712 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:02:16,712 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:16,712 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:02:16,713 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-12-07 16:02:16,713 INFO L87 Difference]: Start difference. First operand 891 states and 1152 transitions. Second operand 6 states. [2019-12-07 16:02:17,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:17,020 INFO L93 Difference]: Finished difference Result 2805 states and 3772 transitions. [2019-12-07 16:02:17,020 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 16:02:17,020 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 126 [2019-12-07 16:02:17,021 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:17,024 INFO L225 Difference]: With dead ends: 2805 [2019-12-07 16:02:17,024 INFO L226 Difference]: Without dead ends: 2042 [2019-12-07 16:02:17,025 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 147 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=79, Invalid=427, Unknown=0, NotChecked=0, Total=506 [2019-12-07 16:02:17,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2042 states. [2019-12-07 16:02:17,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2042 to 839. [2019-12-07 16:02:17,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 839 states. [2019-12-07 16:02:17,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 839 states to 839 states and 1074 transitions. [2019-12-07 16:02:17,092 INFO L78 Accepts]: Start accepts. Automaton has 839 states and 1074 transitions. Word has length 126 [2019-12-07 16:02:17,092 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:17,092 INFO L462 AbstractCegarLoop]: Abstraction has 839 states and 1074 transitions. [2019-12-07 16:02:17,093 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:02:17,093 INFO L276 IsEmpty]: Start isEmpty. Operand 839 states and 1074 transitions. [2019-12-07 16:02:17,094 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2019-12-07 16:02:17,094 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:17,094 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:17,294 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 16:02:17,295 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:17,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:17,296 INFO L82 PathProgramCache]: Analyzing trace with hash -569114610, now seen corresponding path program 1 times [2019-12-07 16:02:17,297 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:17,297 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246699804] [2019-12-07 16:02:17,297 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:17,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:17,448 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 15 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:17,448 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [246699804] [2019-12-07 16:02:17,448 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1383004967] [2019-12-07 16:02:17,448 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 16:02:17,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:17,547 INFO L264 TraceCheckSpWp]: Trace formula consists of 746 conjuncts, 8 conjunts are in the unsatisfiable core [2019-12-07 16:02:17,549 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 16:02:17,606 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-12-07 16:02:17,606 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-12-07 16:02:17,606 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [8] total 13 [2019-12-07 16:02:17,606 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1735949951] [2019-12-07 16:02:17,607 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:02:17,607 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:17,607 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:02:17,607 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=131, Unknown=0, NotChecked=0, Total=156 [2019-12-07 16:02:17,607 INFO L87 Difference]: Start difference. First operand 839 states and 1074 transitions. Second operand 6 states. [2019-12-07 16:02:17,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:17,831 INFO L93 Difference]: Finished difference Result 2159 states and 2876 transitions. [2019-12-07 16:02:17,831 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 16:02:17,831 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 127 [2019-12-07 16:02:17,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:17,833 INFO L225 Difference]: With dead ends: 2159 [2019-12-07 16:02:17,833 INFO L226 Difference]: Without dead ends: 1475 [2019-12-07 16:02:17,834 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 139 GetRequests, 124 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=44, Invalid=228, Unknown=0, NotChecked=0, Total=272 [2019-12-07 16:02:17,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1475 states. [2019-12-07 16:02:17,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1475 to 839. [2019-12-07 16:02:17,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 839 states. [2019-12-07 16:02:17,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 839 states to 839 states and 1073 transitions. [2019-12-07 16:02:17,898 INFO L78 Accepts]: Start accepts. Automaton has 839 states and 1073 transitions. Word has length 127 [2019-12-07 16:02:17,898 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:17,898 INFO L462 AbstractCegarLoop]: Abstraction has 839 states and 1073 transitions. [2019-12-07 16:02:17,898 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:02:17,898 INFO L276 IsEmpty]: Start isEmpty. Operand 839 states and 1073 transitions. [2019-12-07 16:02:17,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2019-12-07 16:02:17,899 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:17,899 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:18,100 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 16:02:18,101 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:18,101 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:18,101 INFO L82 PathProgramCache]: Analyzing trace with hash -503152461, now seen corresponding path program 1 times [2019-12-07 16:02:18,102 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:18,102 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [493008317] [2019-12-07 16:02:18,102 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:18,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:18,259 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 15 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:18,259 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [493008317] [2019-12-07 16:02:18,259 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [227016115] [2019-12-07 16:02:18,259 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 16:02:18,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:18,370 INFO L264 TraceCheckSpWp]: Trace formula consists of 760 conjuncts, 45 conjunts are in the unsatisfiable core [2019-12-07 16:02:18,372 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 16:02:18,563 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:18,563 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 16:02:18,564 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 12] total 17 [2019-12-07 16:02:18,564 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2114349536] [2019-12-07 16:02:18,564 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 16:02:18,564 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:18,564 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 16:02:18,564 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=251, Unknown=0, NotChecked=0, Total=306 [2019-12-07 16:02:18,565 INFO L87 Difference]: Start difference. First operand 839 states and 1073 transitions. Second operand 18 states. [2019-12-07 16:02:20,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:20,685 INFO L93 Difference]: Finished difference Result 3430 states and 4518 transitions. [2019-12-07 16:02:20,686 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2019-12-07 16:02:20,686 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 131 [2019-12-07 16:02:20,686 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:20,688 INFO L225 Difference]: With dead ends: 3430 [2019-12-07 16:02:20,688 INFO L226 Difference]: Without dead ends: 2752 [2019-12-07 16:02:20,691 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 118 SyntacticMatches, 4 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1942 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1261, Invalid=4745, Unknown=0, NotChecked=0, Total=6006 [2019-12-07 16:02:20,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2752 states. [2019-12-07 16:02:20,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2752 to 1322. [2019-12-07 16:02:20,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1322 states. [2019-12-07 16:02:20,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1322 states to 1322 states and 1712 transitions. [2019-12-07 16:02:20,809 INFO L78 Accepts]: Start accepts. Automaton has 1322 states and 1712 transitions. Word has length 131 [2019-12-07 16:02:20,810 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:20,810 INFO L462 AbstractCegarLoop]: Abstraction has 1322 states and 1712 transitions. [2019-12-07 16:02:20,810 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 16:02:20,810 INFO L276 IsEmpty]: Start isEmpty. Operand 1322 states and 1712 transitions. [2019-12-07 16:02:20,811 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2019-12-07 16:02:20,811 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:20,811 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:21,011 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 16:02:21,013 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:21,013 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:21,014 INFO L82 PathProgramCache]: Analyzing trace with hash -1629002450, now seen corresponding path program 1 times [2019-12-07 16:02:21,014 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:21,014 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [686149422] [2019-12-07 16:02:21,014 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:21,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:21,066 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2019-12-07 16:02:21,066 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [686149422] [2019-12-07 16:02:21,066 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:21,067 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:02:21,067 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [215449353] [2019-12-07 16:02:21,067 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:02:21,067 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:21,067 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:02:21,067 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:02:21,068 INFO L87 Difference]: Start difference. First operand 1322 states and 1712 transitions. Second operand 4 states. [2019-12-07 16:02:21,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:21,312 INFO L93 Difference]: Finished difference Result 3257 states and 4242 transitions. [2019-12-07 16:02:21,313 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:02:21,313 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 132 [2019-12-07 16:02:21,313 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:21,315 INFO L225 Difference]: With dead ends: 3257 [2019-12-07 16:02:21,315 INFO L226 Difference]: Without dead ends: 2063 [2019-12-07 16:02:21,316 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:02:21,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2063 states. [2019-12-07 16:02:21,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2063 to 1382. [2019-12-07 16:02:21,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1382 states. [2019-12-07 16:02:21,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1382 states to 1382 states and 1766 transitions. [2019-12-07 16:02:21,434 INFO L78 Accepts]: Start accepts. Automaton has 1382 states and 1766 transitions. Word has length 132 [2019-12-07 16:02:21,434 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:21,434 INFO L462 AbstractCegarLoop]: Abstraction has 1382 states and 1766 transitions. [2019-12-07 16:02:21,434 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:02:21,434 INFO L276 IsEmpty]: Start isEmpty. Operand 1382 states and 1766 transitions. [2019-12-07 16:02:21,435 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2019-12-07 16:02:21,435 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:21,436 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:21,436 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:21,436 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:21,436 INFO L82 PathProgramCache]: Analyzing trace with hash 1003109554, now seen corresponding path program 1 times [2019-12-07 16:02:21,436 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:21,436 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1951101804] [2019-12-07 16:02:21,436 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:21,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:21,507 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2019-12-07 16:02:21,508 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1951101804] [2019-12-07 16:02:21,508 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:21,508 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:02:21,508 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1549006262] [2019-12-07 16:02:21,508 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:02:21,508 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:21,508 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:02:21,508 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:02:21,508 INFO L87 Difference]: Start difference. First operand 1382 states and 1766 transitions. Second operand 5 states. [2019-12-07 16:02:21,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:21,693 INFO L93 Difference]: Finished difference Result 2508 states and 3252 transitions. [2019-12-07 16:02:21,694 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:02:21,694 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 132 [2019-12-07 16:02:21,694 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:21,696 INFO L225 Difference]: With dead ends: 2508 [2019-12-07 16:02:21,696 INFO L226 Difference]: Without dead ends: 1254 [2019-12-07 16:02:21,697 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:02:21,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1254 states. [2019-12-07 16:02:21,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1254 to 1254. [2019-12-07 16:02:21,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1254 states. [2019-12-07 16:02:21,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1254 states to 1254 states and 1618 transitions. [2019-12-07 16:02:21,818 INFO L78 Accepts]: Start accepts. Automaton has 1254 states and 1618 transitions. Word has length 132 [2019-12-07 16:02:21,819 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:21,819 INFO L462 AbstractCegarLoop]: Abstraction has 1254 states and 1618 transitions. [2019-12-07 16:02:21,819 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:02:21,819 INFO L276 IsEmpty]: Start isEmpty. Operand 1254 states and 1618 transitions. [2019-12-07 16:02:21,820 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-12-07 16:02:21,820 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:21,820 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:21,820 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:21,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:21,820 INFO L82 PathProgramCache]: Analyzing trace with hash 1193716731, now seen corresponding path program 1 times [2019-12-07 16:02:21,821 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:21,821 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [901509777] [2019-12-07 16:02:21,821 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:21,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:21,864 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 16 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2019-12-07 16:02:21,864 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [901509777] [2019-12-07 16:02:21,864 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:21,864 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 16:02:21,864 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [929973838] [2019-12-07 16:02:21,864 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:02:21,864 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:21,864 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:02:21,865 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:02:21,865 INFO L87 Difference]: Start difference. First operand 1254 states and 1618 transitions. Second operand 6 states. [2019-12-07 16:02:22,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:22,490 INFO L93 Difference]: Finished difference Result 6564 states and 8664 transitions. [2019-12-07 16:02:22,490 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 16:02:22,490 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 133 [2019-12-07 16:02:22,490 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:22,496 INFO L225 Difference]: With dead ends: 6564 [2019-12-07 16:02:22,496 INFO L226 Difference]: Without dead ends: 5491 [2019-12-07 16:02:22,498 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=66, Invalid=144, Unknown=0, NotChecked=0, Total=210 [2019-12-07 16:02:22,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5491 states. [2019-12-07 16:02:22,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5491 to 1596. [2019-12-07 16:02:22,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1596 states. [2019-12-07 16:02:22,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1596 states to 1596 states and 2018 transitions. [2019-12-07 16:02:22,656 INFO L78 Accepts]: Start accepts. Automaton has 1596 states and 2018 transitions. Word has length 133 [2019-12-07 16:02:22,657 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:22,657 INFO L462 AbstractCegarLoop]: Abstraction has 1596 states and 2018 transitions. [2019-12-07 16:02:22,657 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:02:22,657 INFO L276 IsEmpty]: Start isEmpty. Operand 1596 states and 2018 transitions. [2019-12-07 16:02:22,658 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-12-07 16:02:22,658 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:22,658 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:22,658 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:22,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:22,658 INFO L82 PathProgramCache]: Analyzing trace with hash 2094959115, now seen corresponding path program 1 times [2019-12-07 16:02:22,659 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:22,659 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412367803] [2019-12-07 16:02:22,659 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:22,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:22,853 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:22,853 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [412367803] [2019-12-07 16:02:22,853 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1797417218] [2019-12-07 16:02:22,853 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 16:02:22,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:22,954 INFO L264 TraceCheckSpWp]: Trace formula consists of 772 conjuncts, 8 conjunts are in the unsatisfiable core [2019-12-07 16:02:22,956 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 16:02:23,013 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-12-07 16:02:23,013 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-12-07 16:02:23,014 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-12-07 16:02:23,014 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [915033457] [2019-12-07 16:02:23,014 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:02:23,014 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:23,014 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:02:23,014 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-12-07 16:02:23,015 INFO L87 Difference]: Start difference. First operand 1596 states and 2018 transitions. Second operand 6 states. [2019-12-07 16:02:23,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:23,457 INFO L93 Difference]: Finished difference Result 4898 states and 6314 transitions. [2019-12-07 16:02:23,457 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 16:02:23,457 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 134 [2019-12-07 16:02:23,458 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:23,461 INFO L225 Difference]: With dead ends: 4898 [2019-12-07 16:02:23,461 INFO L226 Difference]: Without dead ends: 3463 [2019-12-07 16:02:23,462 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 150 GetRequests, 131 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=58, Invalid=362, Unknown=0, NotChecked=0, Total=420 [2019-12-07 16:02:23,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3463 states. [2019-12-07 16:02:23,613 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3463 to 1596. [2019-12-07 16:02:23,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1596 states. [2019-12-07 16:02:23,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1596 states to 1596 states and 2016 transitions. [2019-12-07 16:02:23,615 INFO L78 Accepts]: Start accepts. Automaton has 1596 states and 2016 transitions. Word has length 134 [2019-12-07 16:02:23,615 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:23,615 INFO L462 AbstractCegarLoop]: Abstraction has 1596 states and 2016 transitions. [2019-12-07 16:02:23,615 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:02:23,615 INFO L276 IsEmpty]: Start isEmpty. Operand 1596 states and 2016 transitions. [2019-12-07 16:02:23,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-12-07 16:02:23,616 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:23,616 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:23,816 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 16:02:23,817 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:23,818 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:23,818 INFO L82 PathProgramCache]: Analyzing trace with hash -1714435691, now seen corresponding path program 1 times [2019-12-07 16:02:23,818 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:23,818 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282107296] [2019-12-07 16:02:23,819 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:23,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:23,956 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 28 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:23,956 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [282107296] [2019-12-07 16:02:23,957 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2112025066] [2019-12-07 16:02:23,957 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 16:02:24,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:24,053 INFO L264 TraceCheckSpWp]: Trace formula consists of 762 conjuncts, 46 conjunts are in the unsatisfiable core [2019-12-07 16:02:24,055 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 16:02:24,264 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 28 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:02:24,264 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 16:02:24,265 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 20 [2019-12-07 16:02:24,265 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1362903683] [2019-12-07 16:02:24,265 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 16:02:24,265 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:24,265 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 16:02:24,266 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=352, Unknown=0, NotChecked=0, Total=420 [2019-12-07 16:02:24,266 INFO L87 Difference]: Start difference. First operand 1596 states and 2016 transitions. Second operand 21 states. [2019-12-07 16:02:26,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:26,263 INFO L93 Difference]: Finished difference Result 4380 states and 5555 transitions. [2019-12-07 16:02:26,264 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-12-07 16:02:26,264 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 134 [2019-12-07 16:02:26,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:26,267 INFO L225 Difference]: With dead ends: 4380 [2019-12-07 16:02:26,267 INFO L226 Difference]: Without dead ends: 2965 [2019-12-07 16:02:26,269 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 120 SyntacticMatches, 4 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 997 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=649, Invalid=3133, Unknown=0, NotChecked=0, Total=3782 [2019-12-07 16:02:26,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2965 states. [2019-12-07 16:02:26,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2965 to 1815. [2019-12-07 16:02:26,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1815 states. [2019-12-07 16:02:26,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1815 states to 1815 states and 2286 transitions. [2019-12-07 16:02:26,447 INFO L78 Accepts]: Start accepts. Automaton has 1815 states and 2286 transitions. Word has length 134 [2019-12-07 16:02:26,447 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:26,447 INFO L462 AbstractCegarLoop]: Abstraction has 1815 states and 2286 transitions. [2019-12-07 16:02:26,447 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 16:02:26,447 INFO L276 IsEmpty]: Start isEmpty. Operand 1815 states and 2286 transitions. [2019-12-07 16:02:26,449 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-12-07 16:02:26,449 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:26,449 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:26,649 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 16:02:26,650 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:26,650 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:26,650 INFO L82 PathProgramCache]: Analyzing trace with hash 1273389207, now seen corresponding path program 1 times [2019-12-07 16:02:26,650 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:26,650 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1632664690] [2019-12-07 16:02:26,650 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:26,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:02:26,692 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2019-12-07 16:02:26,692 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1632664690] [2019-12-07 16:02:26,692 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:02:26,693 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:02:26,693 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [178366821] [2019-12-07 16:02:26,693 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:02:26,693 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:02:26,693 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:02:26,693 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:02:26,693 INFO L87 Difference]: Start difference. First operand 1815 states and 2286 transitions. Second operand 4 states. [2019-12-07 16:02:26,902 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:02:26,902 INFO L93 Difference]: Finished difference Result 3309 states and 4194 transitions. [2019-12-07 16:02:26,902 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 16:02:26,903 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 134 [2019-12-07 16:02:26,903 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:02:26,904 INFO L225 Difference]: With dead ends: 3309 [2019-12-07 16:02:26,904 INFO L226 Difference]: Without dead ends: 1620 [2019-12-07 16:02:26,905 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:02:26,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1620 states. [2019-12-07 16:02:27,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1620 to 1620. [2019-12-07 16:02:27,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1620 states. [2019-12-07 16:02:27,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1620 states to 1620 states and 2026 transitions. [2019-12-07 16:02:27,058 INFO L78 Accepts]: Start accepts. Automaton has 1620 states and 2026 transitions. Word has length 134 [2019-12-07 16:02:27,058 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:02:27,058 INFO L462 AbstractCegarLoop]: Abstraction has 1620 states and 2026 transitions. [2019-12-07 16:02:27,058 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:02:27,058 INFO L276 IsEmpty]: Start isEmpty. Operand 1620 states and 2026 transitions. [2019-12-07 16:02:27,060 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-12-07 16:02:27,060 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:02:27,060 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:02:27,060 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:02:27,060 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:02:27,060 INFO L82 PathProgramCache]: Analyzing trace with hash 1769777121, now seen corresponding path program 1 times [2019-12-07 16:02:27,060 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:02:27,060 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [556903386] [2019-12-07 16:02:27,060 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:02:27,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 16:02:27,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 16:02:27,186 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 16:02:27,186 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 16:02:27,310 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 04:02:27 BoogieIcfgContainer [2019-12-07 16:02:27,310 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 16:02:27,310 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 16:02:27,310 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 16:02:27,310 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 16:02:27,310 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:02:09" (3/4) ... [2019-12-07 16:02:27,312 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 16:02:27,429 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_d7a6cdf8-d504-4044-a099-35b4788a0244/bin/uautomizer/witness.graphml [2019-12-07 16:02:27,429 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 16:02:27,430 INFO L168 Benchmark]: Toolchain (without parser) took 19343.33 ms. Allocated memory was 1.0 GB in the beginning and 1.8 GB in the end (delta: 777.0 MB). Free memory was 948.9 MB in the beginning and 1.4 GB in the end (delta: -472.0 MB). Peak memory consumption was 305.0 MB. Max. memory is 11.5 GB. [2019-12-07 16:02:27,430 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 963.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 16:02:27,431 INFO L168 Benchmark]: CACSL2BoogieTranslator took 297.53 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 99.6 MB). Free memory was 948.9 MB in the beginning and 1.1 GB in the end (delta: -140.2 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. [2019-12-07 16:02:27,431 INFO L168 Benchmark]: Boogie Procedure Inliner took 44.11 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 16:02:27,431 INFO L168 Benchmark]: Boogie Preprocessor took 37.69 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 16:02:27,431 INFO L168 Benchmark]: RCFGBuilder took 597.91 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 989.3 MB in the end (delta: 89.0 MB). Peak memory consumption was 89.0 MB. Max. memory is 11.5 GB. [2019-12-07 16:02:27,431 INFO L168 Benchmark]: TraceAbstraction took 18244.30 ms. Allocated memory was 1.1 GB in the beginning and 1.8 GB in the end (delta: 677.4 MB). Free memory was 989.3 MB in the beginning and 1.5 GB in the end (delta: -475.9 MB). Peak memory consumption was 201.5 MB. Max. memory is 11.5 GB. [2019-12-07 16:02:27,432 INFO L168 Benchmark]: Witness Printer took 118.84 ms. Allocated memory is still 1.8 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 44.3 MB). Peak memory consumption was 44.3 MB. Max. memory is 11.5 GB. [2019-12-07 16:02:27,433 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 963.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 297.53 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 99.6 MB). Free memory was 948.9 MB in the beginning and 1.1 GB in the end (delta: -140.2 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 44.11 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 37.69 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 597.91 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 989.3 MB in the end (delta: 89.0 MB). Peak memory consumption was 89.0 MB. Max. memory is 11.5 GB. * TraceAbstraction took 18244.30 ms. Allocated memory was 1.1 GB in the beginning and 1.8 GB in the end (delta: 677.4 MB). Free memory was 989.3 MB in the beginning and 1.5 GB in the end (delta: -475.9 MB). Peak memory consumption was 201.5 MB. Max. memory is 11.5 GB. * Witness Printer took 118.84 ms. Allocated memory is still 1.8 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 44.3 MB). Peak memory consumption was 44.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 653]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L69] msg_t nomsg = (msg_t )-1; [L70] port_t cs1 ; [L71] int8_t cs1_old ; [L72] int8_t cs1_new ; [L73] port_t cs2 ; [L74] int8_t cs2_old ; [L75] int8_t cs2_new ; [L76] port_t s1s2 ; [L77] int8_t s1s2_old ; [L78] int8_t s1s2_new ; [L79] port_t s1s1 ; [L80] int8_t s1s1_old ; [L81] int8_t s1s1_new ; [L82] port_t s2s1 ; [L83] int8_t s2s1_old ; [L84] int8_t s2s1_new ; [L85] port_t s2s2 ; [L86] int8_t s2s2_old ; [L87] int8_t s2s2_new ; [L88] port_t s1p ; [L89] int8_t s1p_old ; [L90] int8_t s1p_new ; [L91] port_t s2p ; [L92] int8_t s2p_old ; [L93] int8_t s2p_new ; [L96] _Bool side1Failed ; [L97] _Bool side2Failed ; [L98] msg_t side1_written ; [L99] msg_t side2_written ; [L102] static _Bool side1Failed_History_0 ; [L103] static _Bool side1Failed_History_1 ; [L104] static _Bool side1Failed_History_2 ; [L105] static _Bool side2Failed_History_0 ; [L106] static _Bool side2Failed_History_1 ; [L107] static _Bool side2Failed_History_2 ; [L108] static int8_t active_side_History_0 ; [L109] static int8_t active_side_History_1 ; [L110] static int8_t active_side_History_2 ; [L111] static msg_t manual_selection_History_0 ; [L112] static msg_t manual_selection_History_1 ; [L113] static msg_t manual_selection_History_2 ; [L455] void (*nodes[4])(void) = { & Console_task_each_pals_period, & Side1_activestandby_task_each_pals_period, & Side2_activestandby_task_each_pals_period, & Pendulum_prism_task_each_pals_period}; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=0, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L577] int c1 ; [L578] int i2 ; [L581] c1 = 0 [L582] side1Failed = __VERIFIER_nondet_bool() [L583] side2Failed = __VERIFIER_nondet_bool() [L584] side1_written = __VERIFIER_nondet_char() [L585] side2_written = __VERIFIER_nondet_char() [L586] side1Failed_History_0 = __VERIFIER_nondet_bool() [L587] side1Failed_History_1 = __VERIFIER_nondet_bool() [L588] side1Failed_History_2 = __VERIFIER_nondet_bool() [L589] side2Failed_History_0 = __VERIFIER_nondet_bool() [L590] side2Failed_History_1 = __VERIFIER_nondet_bool() [L591] side2Failed_History_2 = __VERIFIER_nondet_bool() [L592] active_side_History_0 = __VERIFIER_nondet_char() [L593] active_side_History_1 = __VERIFIER_nondet_char() [L594] active_side_History_2 = __VERIFIER_nondet_char() [L595] manual_selection_History_0 = __VERIFIER_nondet_char() [L596] manual_selection_History_1 = __VERIFIER_nondet_char() [L597] manual_selection_History_2 = __VERIFIER_nondet_char() [L239] COND FALSE !((int )side1Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L242] COND FALSE !((int )side2Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L245] COND FALSE !((int )active_side_History_0 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L248] COND FALSE !((int )manual_selection_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L251] COND FALSE !((int )side1Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L254] COND FALSE !((int )side2Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L257] COND FALSE !((int )active_side_History_1 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L260] COND FALSE !((int )manual_selection_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L263] COND FALSE !((int )side1Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L266] COND FALSE !((int )side2Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L269] COND FALSE !((int )active_side_History_2 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L272] COND FALSE !((int )manual_selection_History_2 != 0) [L275] return (1); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L598] i2 = init() [L600] cs1_old = nomsg [L601] cs1_new = nomsg [L602] cs2_old = nomsg [L603] cs2_new = nomsg [L604] s1s2_old = nomsg [L605] s1s2_new = nomsg [L606] s1s1_old = nomsg [L607] s1s1_new = nomsg [L608] s2s1_old = nomsg [L609] s2s1_new = nomsg [L610] s2s2_old = nomsg [L611] s2s2_new = nomsg [L612] s1p_old = nomsg [L613] s1p_new = nomsg [L614] s2p_old = nomsg [L615] s2p_new = nomsg [L616] i2 = 0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L617] COND TRUE 1 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND TRUE \read(side1Failed) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] EXPR nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L321] EXPR nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L321] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L322] EXPR nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L322] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L323] side1_written = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND TRUE (int )side1 == (int )side2 [L390] next_state = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] side2_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) [L449] active_side = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L623] cs1_old = cs1_new [L624] cs1_new = nomsg [L625] cs2_old = cs2_new [L626] cs2_new = nomsg [L627] s1s2_old = s1s2_new [L628] s1s2_new = nomsg [L629] s1s1_old = s1s1_new [L630] s1s1_new = nomsg [L631] s2s1_old = s2s1_new [L632] s2s1_new = nomsg [L633] s2s2_old = s2s2_new [L634] s2s2_new = nomsg [L635] s1p_old = s1p_new [L636] s1p_new = nomsg [L637] s2p_old = s2p_new [L638] s2p_new = nomsg [L458] int tmp ; [L459] msg_t tmp___0 ; [L460] _Bool tmp___1 ; [L461] _Bool tmp___2 ; [L462] _Bool tmp___3 ; [L463] _Bool tmp___4 ; [L464] int8_t tmp___5 ; [L465] _Bool tmp___6 ; [L466] _Bool tmp___7 ; [L467] _Bool tmp___8 ; [L468] int8_t tmp___9 ; [L469] _Bool tmp___10 ; [L470] _Bool tmp___11 ; [L471] _Bool tmp___12 ; [L472] msg_t tmp___13 ; [L473] _Bool tmp___14 ; [L474] _Bool tmp___15 ; [L475] _Bool tmp___16 ; [L476] _Bool tmp___17 ; [L477] int8_t tmp___18 ; [L478] int8_t tmp___19 ; [L479] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L482] COND FALSE !(! side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L485] COND TRUE ! side2Failed [L486] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L491] tmp___0 = read_manual_selection_history((unsigned char)1) [L492] COND TRUE ! tmp___0 [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L493] tmp___1 = read_side1_failed_history((unsigned char)1) [L494] COND TRUE ! tmp___1 [L130] COND TRUE (int )index == 0 [L131] return (side1Failed_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L495] tmp___2 = read_side1_failed_history((unsigned char)0) [L496] COND FALSE !(! tmp___2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L521] tmp___7 = read_side1_failed_history((unsigned char)1) [L522] COND FALSE !(\read(tmp___7)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L537] tmp___11 = read_side1_failed_history((unsigned char)1) [L538] COND TRUE ! tmp___11 [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L539] tmp___12 = read_side2_failed_history((unsigned char)1) [L540] COND FALSE !(\read(tmp___12)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L190] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L193] COND FALSE !((int )index == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L196] COND TRUE (int )index == 2 [L197] return (active_side_History_2); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L553] tmp___20 = read_active_side_history((unsigned char)2) [L554] COND FALSE !((int )tmp___20 > -2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L572] return (1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L639] c1 = check() [L651] COND FALSE !(! arg) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L617] COND TRUE 1 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-128, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND FALSE !(\read(side1Failed)) [L326] side1 = s1s1_old [L327] s1s1_old = nomsg [L328] side2 = s2s1_old [L329] s2s1_old = nomsg [L330] manual_selection = cs1_old [L331] cs1_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L332] COND FALSE !((int )side1 == (int )side2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L335] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L336] COND TRUE (int )side2 != (int )nomsg [L337] next_state = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L356] EXPR next_state != nomsg && s1s1_new == nomsg ? next_state : s1s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L356] s1s1_new = next_state != nomsg && s1s1_new == nomsg ? next_state : s1s1_new [L357] EXPR next_state != nomsg && s1s2_new == nomsg ? next_state : s1s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L357] s1s2_new = next_state != nomsg && s1s2_new == nomsg ? next_state : s1s2_new [L358] EXPR next_state != nomsg && s1p_new == nomsg ? next_state : s1p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L358] s1p_new = next_state != nomsg && s1p_new == nomsg ? next_state : s1p_new [L359] side1_written = next_state VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND TRUE \read(side2Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L377] EXPR nomsg != nomsg && s2s1_new == nomsg ? nomsg : s2s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L377] s2s1_new = nomsg != nomsg && s2s1_new == nomsg ? nomsg : s2s1_new [L378] EXPR nomsg != nomsg && s2s2_new == nomsg ? nomsg : s2s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L378] s2s2_new = nomsg != nomsg && s2s2_new == nomsg ? nomsg : s2s2_new [L379] EXPR nomsg != nomsg && s2p_new == nomsg ? nomsg : s2p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L379] s2p_new = nomsg != nomsg && s2p_new == nomsg ? nomsg : s2p_new [L380] side2_written = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) [L449] active_side = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-128, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L623] cs1_old = cs1_new [L624] cs1_new = nomsg [L625] cs2_old = cs2_new [L626] cs2_new = nomsg [L627] s1s2_old = s1s2_new [L628] s1s2_new = nomsg [L629] s1s1_old = s1s1_new [L630] s1s1_new = nomsg [L631] s2s1_old = s2s1_new [L632] s2s1_new = nomsg [L633] s2s2_old = s2s2_new [L634] s2s2_new = nomsg [L635] s1p_old = s1p_new [L636] s1p_new = nomsg [L637] s2p_old = s2p_new [L638] s2p_new = nomsg [L458] int tmp ; [L459] msg_t tmp___0 ; [L460] _Bool tmp___1 ; [L461] _Bool tmp___2 ; [L462] _Bool tmp___3 ; [L463] _Bool tmp___4 ; [L464] int8_t tmp___5 ; [L465] _Bool tmp___6 ; [L466] _Bool tmp___7 ; [L467] _Bool tmp___8 ; [L468] int8_t tmp___9 ; [L469] _Bool tmp___10 ; [L470] _Bool tmp___11 ; [L471] _Bool tmp___12 ; [L472] msg_t tmp___13 ; [L473] _Bool tmp___14 ; [L474] _Bool tmp___15 ; [L475] _Bool tmp___16 ; [L476] _Bool tmp___17 ; [L477] int8_t tmp___18 ; [L478] int8_t tmp___19 ; [L479] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L482] COND TRUE ! side1Failed [L483] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L491] tmp___0 = read_manual_selection_history((unsigned char)1) [L492] COND FALSE !(! tmp___0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L521] tmp___7 = read_side1_failed_history((unsigned char)1) [L522] COND TRUE \read(tmp___7) [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L523] tmp___8 = read_side2_failed_history((unsigned char)1) [L524] COND TRUE ! tmp___8 [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L525] tmp___5 = read_active_side_history((unsigned char)0) [L526] COND TRUE ! ((int )tmp___5 == 2) [L527] return (0); VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L639] c1 = check() [L651] COND TRUE ! arg VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] [L653] __VERIFIER_error() VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=-1, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 290 locations, 23 error locations. Result: UNSAFE, OverallTime: 18.0s, OverallIterations: 37, TraceHistogramMax: 2, AutomataDifference: 9.9s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 15650 SDtfs, 27851 SDslu, 35782 SDs, 0 SdLazy, 5608 SolverSat, 397 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1315 GetRequests, 943 SyntacticMatches, 19 SemanticMatches, 353 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3347 ImplicationChecksByTransitivity, 3.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=1815occurred in iteration=35, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 2.0s AutomataMinimizationTime, 36 MinimizatonAttempts, 21843 StatesRemovedByMinimization, 32 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.2s SsaConstructionTime, 0.9s SatisfiabilityAnalysisTime, 2.6s InterpolantComputationTime, 4062 NumberOfCodeBlocks, 4062 NumberOfCodeBlocksAsserted, 44 NumberOfCheckSat, 3884 ConstructedInterpolants, 0 QuantifiedInterpolants, 1555146 SizeOfPredicates, 38 NumberOfNonLiveVariables, 5238 ConjunctsInSsa, 136 ConjunctsInUnsatCore, 43 InterpolantComputations, 34 PerfectInterpolantSequences, 576/673 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...