./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.BOUNDED-10.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.BOUNDED-10.pals.c -s /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 75de94c5f78b6878c3cbd09fac99b01e14f23f29 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:46:04,621 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:46:04,623 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:46:04,632 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:46:04,633 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:46:04,633 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:46:04,634 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:46:04,635 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:46:04,637 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:46:04,637 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:46:04,638 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:46:04,639 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:46:04,639 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:46:04,639 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:46:04,640 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:46:04,641 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:46:04,642 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:46:04,642 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:46:04,644 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:46:04,645 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:46:04,646 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:46:04,647 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:46:04,648 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:46:04,648 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:46:04,650 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:46:04,650 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:46:04,650 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:46:04,651 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:46:04,651 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:46:04,652 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:46:04,652 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:46:04,652 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:46:04,653 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:46:04,654 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:46:04,654 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:46:04,655 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:46:04,655 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:46:04,655 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:46:04,655 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:46:04,656 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:46:04,657 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:46:04,657 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 18:46:04,670 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:46:04,670 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:46:04,671 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:46:04,671 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:46:04,671 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:46:04,671 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:46:04,672 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:46:04,672 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:46:04,672 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:46:04,672 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:46:04,672 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 18:46:04,672 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 18:46:04,673 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 18:46:04,673 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:46:04,673 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:46:04,673 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:46:04,673 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 18:46:04,674 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:46:04,674 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:46:04,674 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 18:46:04,674 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 18:46:04,674 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:46:04,675 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:46:04,675 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 18:46:04,675 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 18:46:04,675 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:46:04,675 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 18:46:04,675 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 18:46:04,676 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:46:04,676 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 75de94c5f78b6878c3cbd09fac99b01e14f23f29 [2019-12-07 18:46:04,778 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:46:04,788 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:46:04,791 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:46:04,792 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:46:04,792 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:46:04,793 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.BOUNDED-10.pals.c [2019-12-07 18:46:04,831 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/data/f1db23216/3289d83807384d3f94916cfa1d2dffcd/FLAGd5e7dff52 [2019-12-07 18:46:05,271 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:46:05,272 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.BOUNDED-10.pals.c [2019-12-07 18:46:05,279 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/data/f1db23216/3289d83807384d3f94916cfa1d2dffcd/FLAGd5e7dff52 [2019-12-07 18:46:05,287 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/data/f1db23216/3289d83807384d3f94916cfa1d2dffcd [2019-12-07 18:46:05,289 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:46:05,290 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:46:05,291 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:46:05,291 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:46:05,293 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:46:05,293 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:46:05" (1/1) ... [2019-12-07 18:46:05,295 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@215be132 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:05, skipping insertion in model container [2019-12-07 18:46:05,295 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:46:05" (1/1) ... [2019-12-07 18:46:05,300 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:46:05,326 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:46:05,509 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:46:05,514 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:46:05,554 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:46:05,567 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:46:05,567 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:05 WrapperNode [2019-12-07 18:46:05,567 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:46:05,567 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:46:05,568 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:46:05,568 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:46:05,573 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:05" (1/1) ... [2019-12-07 18:46:05,581 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:05" (1/1) ... [2019-12-07 18:46:05,611 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:46:05,612 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:46:05,612 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:46:05,612 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:46:05,618 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:05" (1/1) ... [2019-12-07 18:46:05,618 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:05" (1/1) ... [2019-12-07 18:46:05,622 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:05" (1/1) ... [2019-12-07 18:46:05,623 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:05" (1/1) ... [2019-12-07 18:46:05,634 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:05" (1/1) ... [2019-12-07 18:46:05,642 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:05" (1/1) ... [2019-12-07 18:46:05,645 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:05" (1/1) ... [2019-12-07 18:46:05,649 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:46:05,650 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:46:05,650 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:46:05,650 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:46:05,651 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:05" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:46:05,695 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:46:05,695 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:46:06,236 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:46:06,237 INFO L287 CfgBuilder]: Removed 119 assume(true) statements. [2019-12-07 18:46:06,238 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:46:06 BoogieIcfgContainer [2019-12-07 18:46:06,238 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:46:06,238 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 18:46:06,238 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 18:46:06,240 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 18:46:06,240 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 06:46:05" (1/3) ... [2019-12-07 18:46:06,241 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@f83391c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:46:06, skipping insertion in model container [2019-12-07 18:46:06,241 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:46:05" (2/3) ... [2019-12-07 18:46:06,241 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@f83391c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:46:06, skipping insertion in model container [2019-12-07 18:46:06,241 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:46:06" (3/3) ... [2019-12-07 18:46:06,242 INFO L109 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby.4_2.ufo.BOUNDED-10.pals.c [2019-12-07 18:46:06,248 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 18:46:06,253 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 23 error locations. [2019-12-07 18:46:06,261 INFO L249 AbstractCegarLoop]: Starting to check reachability of 23 error locations. [2019-12-07 18:46:06,279 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 18:46:06,279 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 18:46:06,279 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 18:46:06,279 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:46:06,279 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:46:06,280 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 18:46:06,280 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:46:06,280 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 18:46:06,297 INFO L276 IsEmpty]: Start isEmpty. Operand 293 states. [2019-12-07 18:46:06,302 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 18:46:06,302 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:06,303 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:06,304 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:06,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:06,308 INFO L82 PathProgramCache]: Analyzing trace with hash 211735483, now seen corresponding path program 1 times [2019-12-07 18:46:06,313 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:06,313 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [895285617] [2019-12-07 18:46:06,314 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:06,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:06,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:06,447 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [895285617] [2019-12-07 18:46:06,448 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:06,448 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:46:06,449 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [736134104] [2019-12-07 18:46:06,452 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:46:06,452 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:06,460 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:46:06,461 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:46:06,462 INFO L87 Difference]: Start difference. First operand 293 states. Second operand 3 states. [2019-12-07 18:46:06,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:06,521 INFO L93 Difference]: Finished difference Result 572 states and 892 transitions. [2019-12-07 18:46:06,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:46:06,523 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 31 [2019-12-07 18:46:06,523 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:06,533 INFO L225 Difference]: With dead ends: 572 [2019-12-07 18:46:06,533 INFO L226 Difference]: Without dead ends: 289 [2019-12-07 18:46:06,536 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:46:06,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 289 states. [2019-12-07 18:46:06,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 289 to 289. [2019-12-07 18:46:06,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 289 states. [2019-12-07 18:46:06,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 289 states to 289 states and 413 transitions. [2019-12-07 18:46:06,580 INFO L78 Accepts]: Start accepts. Automaton has 289 states and 413 transitions. Word has length 31 [2019-12-07 18:46:06,580 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:06,581 INFO L462 AbstractCegarLoop]: Abstraction has 289 states and 413 transitions. [2019-12-07 18:46:06,581 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:46:06,581 INFO L276 IsEmpty]: Start isEmpty. Operand 289 states and 413 transitions. [2019-12-07 18:46:06,582 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-12-07 18:46:06,583 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:06,583 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:06,583 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:06,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:06,584 INFO L82 PathProgramCache]: Analyzing trace with hash -1187444686, now seen corresponding path program 1 times [2019-12-07 18:46:06,584 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:06,584 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1117971841] [2019-12-07 18:46:06,584 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:06,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:06,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:06,697 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1117971841] [2019-12-07 18:46:06,698 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:06,698 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:46:06,698 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [207762623] [2019-12-07 18:46:06,699 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:46:06,699 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:06,699 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:46:06,699 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:46:06,699 INFO L87 Difference]: Start difference. First operand 289 states and 413 transitions. Second operand 3 states. [2019-12-07 18:46:06,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:06,738 INFO L93 Difference]: Finished difference Result 597 states and 861 transitions. [2019-12-07 18:46:06,739 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:46:06,739 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 42 [2019-12-07 18:46:06,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:06,741 INFO L225 Difference]: With dead ends: 597 [2019-12-07 18:46:06,741 INFO L226 Difference]: Without dead ends: 323 [2019-12-07 18:46:06,743 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:46:06,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 323 states. [2019-12-07 18:46:06,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 265. [2019-12-07 18:46:06,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 265 states. [2019-12-07 18:46:06,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 265 states to 265 states and 377 transitions. [2019-12-07 18:46:06,755 INFO L78 Accepts]: Start accepts. Automaton has 265 states and 377 transitions. Word has length 42 [2019-12-07 18:46:06,755 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:06,755 INFO L462 AbstractCegarLoop]: Abstraction has 265 states and 377 transitions. [2019-12-07 18:46:06,755 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:46:06,755 INFO L276 IsEmpty]: Start isEmpty. Operand 265 states and 377 transitions. [2019-12-07 18:46:06,756 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-12-07 18:46:06,757 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:06,757 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:06,757 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:06,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:06,757 INFO L82 PathProgramCache]: Analyzing trace with hash 1273755287, now seen corresponding path program 1 times [2019-12-07 18:46:06,757 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:06,757 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1488547845] [2019-12-07 18:46:06,758 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:06,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:06,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:06,812 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1488547845] [2019-12-07 18:46:06,812 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:06,812 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:46:06,813 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1959651333] [2019-12-07 18:46:06,813 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:46:06,813 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:06,813 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:46:06,814 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:46:06,814 INFO L87 Difference]: Start difference. First operand 265 states and 377 transitions. Second operand 3 states. [2019-12-07 18:46:06,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:06,842 INFO L93 Difference]: Finished difference Result 742 states and 1066 transitions. [2019-12-07 18:46:06,843 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:46:06,843 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-12-07 18:46:06,843 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:06,846 INFO L225 Difference]: With dead ends: 742 [2019-12-07 18:46:06,846 INFO L226 Difference]: Without dead ends: 492 [2019-12-07 18:46:06,847 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:46:06,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 492 states. [2019-12-07 18:46:06,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 492 to 300. [2019-12-07 18:46:06,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 300 states. [2019-12-07 18:46:06,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 300 states to 300 states and 429 transitions. [2019-12-07 18:46:06,864 INFO L78 Accepts]: Start accepts. Automaton has 300 states and 429 transitions. Word has length 49 [2019-12-07 18:46:06,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:06,865 INFO L462 AbstractCegarLoop]: Abstraction has 300 states and 429 transitions. [2019-12-07 18:46:06,865 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:46:06,865 INFO L276 IsEmpty]: Start isEmpty. Operand 300 states and 429 transitions. [2019-12-07 18:46:06,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2019-12-07 18:46:06,867 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:06,867 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:06,868 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:06,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:06,868 INFO L82 PathProgramCache]: Analyzing trace with hash -1910840580, now seen corresponding path program 1 times [2019-12-07 18:46:06,868 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:06,868 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [14869275] [2019-12-07 18:46:06,869 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:06,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:06,942 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:06,942 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [14869275] [2019-12-07 18:46:06,942 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:06,942 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:46:06,943 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497389185] [2019-12-07 18:46:06,943 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:46:06,943 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:06,943 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:46:06,944 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:46:06,944 INFO L87 Difference]: Start difference. First operand 300 states and 429 transitions. Second operand 5 states. [2019-12-07 18:46:07,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:07,119 INFO L93 Difference]: Finished difference Result 942 states and 1360 transitions. [2019-12-07 18:46:07,120 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:46:07,120 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2019-12-07 18:46:07,120 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:07,123 INFO L225 Difference]: With dead ends: 942 [2019-12-07 18:46:07,123 INFO L226 Difference]: Without dead ends: 657 [2019-12-07 18:46:07,124 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:46:07,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 657 states. [2019-12-07 18:46:07,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 657 to 386. [2019-12-07 18:46:07,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 386 states. [2019-12-07 18:46:07,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386 states to 386 states and 552 transitions. [2019-12-07 18:46:07,137 INFO L78 Accepts]: Start accepts. Automaton has 386 states and 552 transitions. Word has length 50 [2019-12-07 18:46:07,138 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:07,138 INFO L462 AbstractCegarLoop]: Abstraction has 386 states and 552 transitions. [2019-12-07 18:46:07,138 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:46:07,138 INFO L276 IsEmpty]: Start isEmpty. Operand 386 states and 552 transitions. [2019-12-07 18:46:07,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 18:46:07,139 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:07,140 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:07,140 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:07,140 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:07,140 INFO L82 PathProgramCache]: Analyzing trace with hash -1041102253, now seen corresponding path program 1 times [2019-12-07 18:46:07,141 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:07,141 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264863103] [2019-12-07 18:46:07,141 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:07,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:07,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:07,197 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [264863103] [2019-12-07 18:46:07,198 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:07,198 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:46:07,198 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760764413] [2019-12-07 18:46:07,198 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:46:07,198 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:07,199 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:46:07,199 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:46:07,199 INFO L87 Difference]: Start difference. First operand 386 states and 552 transitions. Second operand 5 states. [2019-12-07 18:46:07,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:07,368 INFO L93 Difference]: Finished difference Result 944 states and 1360 transitions. [2019-12-07 18:46:07,368 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:46:07,368 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-12-07 18:46:07,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:07,371 INFO L225 Difference]: With dead ends: 944 [2019-12-07 18:46:07,371 INFO L226 Difference]: Without dead ends: 659 [2019-12-07 18:46:07,372 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:46:07,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 659 states. [2019-12-07 18:46:07,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 659 to 390. [2019-12-07 18:46:07,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 390 states. [2019-12-07 18:46:07,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 390 states to 390 states and 556 transitions. [2019-12-07 18:46:07,384 INFO L78 Accepts]: Start accepts. Automaton has 390 states and 556 transitions. Word has length 51 [2019-12-07 18:46:07,384 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:07,384 INFO L462 AbstractCegarLoop]: Abstraction has 390 states and 556 transitions. [2019-12-07 18:46:07,384 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:46:07,384 INFO L276 IsEmpty]: Start isEmpty. Operand 390 states and 556 transitions. [2019-12-07 18:46:07,385 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-12-07 18:46:07,385 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:07,385 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:07,385 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:07,385 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:07,386 INFO L82 PathProgramCache]: Analyzing trace with hash -458607163, now seen corresponding path program 1 times [2019-12-07 18:46:07,386 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:07,386 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [684594781] [2019-12-07 18:46:07,386 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:07,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:07,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:07,441 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [684594781] [2019-12-07 18:46:07,442 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:07,442 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:46:07,442 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [967228407] [2019-12-07 18:46:07,442 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:46:07,442 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:07,442 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:46:07,442 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:46:07,443 INFO L87 Difference]: Start difference. First operand 390 states and 556 transitions. Second operand 4 states. [2019-12-07 18:46:07,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:07,569 INFO L93 Difference]: Finished difference Result 944 states and 1356 transitions. [2019-12-07 18:46:07,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:46:07,569 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 53 [2019-12-07 18:46:07,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:07,572 INFO L225 Difference]: With dead ends: 944 [2019-12-07 18:46:07,572 INFO L226 Difference]: Without dead ends: 659 [2019-12-07 18:46:07,573 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:46:07,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 659 states. [2019-12-07 18:46:07,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 659 to 390. [2019-12-07 18:46:07,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 390 states. [2019-12-07 18:46:07,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 390 states to 390 states and 554 transitions. [2019-12-07 18:46:07,585 INFO L78 Accepts]: Start accepts. Automaton has 390 states and 554 transitions. Word has length 53 [2019-12-07 18:46:07,585 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:07,585 INFO L462 AbstractCegarLoop]: Abstraction has 390 states and 554 transitions. [2019-12-07 18:46:07,585 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:46:07,585 INFO L276 IsEmpty]: Start isEmpty. Operand 390 states and 554 transitions. [2019-12-07 18:46:07,586 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-12-07 18:46:07,586 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:07,586 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:07,586 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:07,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:07,586 INFO L82 PathProgramCache]: Analyzing trace with hash 1789775306, now seen corresponding path program 1 times [2019-12-07 18:46:07,586 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:07,587 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1278773861] [2019-12-07 18:46:07,587 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:07,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:07,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:07,671 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1278773861] [2019-12-07 18:46:07,671 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:07,671 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:46:07,671 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1528273462] [2019-12-07 18:46:07,671 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:46:07,671 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:07,672 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:46:07,672 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:46:07,672 INFO L87 Difference]: Start difference. First operand 390 states and 554 transitions. Second operand 5 states. [2019-12-07 18:46:07,714 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:07,714 INFO L93 Difference]: Finished difference Result 776 states and 1117 transitions. [2019-12-07 18:46:07,715 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:46:07,715 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 54 [2019-12-07 18:46:07,715 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:07,718 INFO L225 Difference]: With dead ends: 776 [2019-12-07 18:46:07,718 INFO L226 Difference]: Without dead ends: 491 [2019-12-07 18:46:07,719 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:46:07,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 491 states. [2019-12-07 18:46:07,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 491 to 385. [2019-12-07 18:46:07,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 385 states. [2019-12-07 18:46:07,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 385 states to 385 states and 546 transitions. [2019-12-07 18:46:07,736 INFO L78 Accepts]: Start accepts. Automaton has 385 states and 546 transitions. Word has length 54 [2019-12-07 18:46:07,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:07,736 INFO L462 AbstractCegarLoop]: Abstraction has 385 states and 546 transitions. [2019-12-07 18:46:07,736 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:46:07,737 INFO L276 IsEmpty]: Start isEmpty. Operand 385 states and 546 transitions. [2019-12-07 18:46:07,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 18:46:07,737 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:07,737 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:07,737 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:07,737 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:07,738 INFO L82 PathProgramCache]: Analyzing trace with hash 1630366882, now seen corresponding path program 1 times [2019-12-07 18:46:07,738 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:07,738 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659916119] [2019-12-07 18:46:07,738 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:07,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:07,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:07,823 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1659916119] [2019-12-07 18:46:07,823 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:07,823 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:46:07,823 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [533455079] [2019-12-07 18:46:07,824 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:46:07,824 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:07,824 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:46:07,824 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:46:07,824 INFO L87 Difference]: Start difference. First operand 385 states and 546 transitions. Second operand 5 states. [2019-12-07 18:46:07,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:07,919 INFO L93 Difference]: Finished difference Result 807 states and 1166 transitions. [2019-12-07 18:46:07,919 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:46:07,919 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 58 [2019-12-07 18:46:07,920 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:07,922 INFO L225 Difference]: With dead ends: 807 [2019-12-07 18:46:07,923 INFO L226 Difference]: Without dead ends: 527 [2019-12-07 18:46:07,923 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:46:07,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states. [2019-12-07 18:46:07,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 355. [2019-12-07 18:46:07,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 355 states. [2019-12-07 18:46:07,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 355 states to 355 states and 500 transitions. [2019-12-07 18:46:07,943 INFO L78 Accepts]: Start accepts. Automaton has 355 states and 500 transitions. Word has length 58 [2019-12-07 18:46:07,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:07,944 INFO L462 AbstractCegarLoop]: Abstraction has 355 states and 500 transitions. [2019-12-07 18:46:07,944 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:46:07,944 INFO L276 IsEmpty]: Start isEmpty. Operand 355 states and 500 transitions. [2019-12-07 18:46:07,945 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-12-07 18:46:07,945 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:07,945 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:07,945 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:07,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:07,945 INFO L82 PathProgramCache]: Analyzing trace with hash 644191382, now seen corresponding path program 1 times [2019-12-07 18:46:07,946 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:07,946 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1712078325] [2019-12-07 18:46:07,946 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:07,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:08,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:08,038 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1712078325] [2019-12-07 18:46:08,038 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:08,038 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:46:08,038 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [144881731] [2019-12-07 18:46:08,039 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:46:08,039 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:08,039 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:46:08,039 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:46:08,039 INFO L87 Difference]: Start difference. First operand 355 states and 500 transitions. Second operand 5 states. [2019-12-07 18:46:08,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:08,145 INFO L93 Difference]: Finished difference Result 904 states and 1296 transitions. [2019-12-07 18:46:08,145 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:46:08,146 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 63 [2019-12-07 18:46:08,146 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:08,150 INFO L225 Difference]: With dead ends: 904 [2019-12-07 18:46:08,150 INFO L226 Difference]: Without dead ends: 654 [2019-12-07 18:46:08,151 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:46:08,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 654 states. [2019-12-07 18:46:08,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 654 to 325. [2019-12-07 18:46:08,170 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 325 states. [2019-12-07 18:46:08,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 325 states to 325 states and 454 transitions. [2019-12-07 18:46:08,171 INFO L78 Accepts]: Start accepts. Automaton has 325 states and 454 transitions. Word has length 63 [2019-12-07 18:46:08,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:08,172 INFO L462 AbstractCegarLoop]: Abstraction has 325 states and 454 transitions. [2019-12-07 18:46:08,172 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:46:08,172 INFO L276 IsEmpty]: Start isEmpty. Operand 325 states and 454 transitions. [2019-12-07 18:46:08,172 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:46:08,173 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:08,173 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:08,173 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:08,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:08,173 INFO L82 PathProgramCache]: Analyzing trace with hash 157991886, now seen corresponding path program 1 times [2019-12-07 18:46:08,173 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:08,174 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1287304644] [2019-12-07 18:46:08,174 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:08,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:08,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:08,275 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1287304644] [2019-12-07 18:46:08,275 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:08,275 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:46:08,275 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [332714167] [2019-12-07 18:46:08,275 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:46:08,276 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:08,276 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:46:08,276 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:46:08,276 INFO L87 Difference]: Start difference. First operand 325 states and 454 transitions. Second operand 6 states. [2019-12-07 18:46:08,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:08,437 INFO L93 Difference]: Finished difference Result 1105 states and 1564 transitions. [2019-12-07 18:46:08,438 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 18:46:08,438 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 68 [2019-12-07 18:46:08,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:08,442 INFO L225 Difference]: With dead ends: 1105 [2019-12-07 18:46:08,442 INFO L226 Difference]: Without dead ends: 885 [2019-12-07 18:46:08,443 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:46:08,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 885 states. [2019-12-07 18:46:08,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 885 to 364. [2019-12-07 18:46:08,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 364 states. [2019-12-07 18:46:08,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 364 states to 364 states and 508 transitions. [2019-12-07 18:46:08,461 INFO L78 Accepts]: Start accepts. Automaton has 364 states and 508 transitions. Word has length 68 [2019-12-07 18:46:08,461 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:08,461 INFO L462 AbstractCegarLoop]: Abstraction has 364 states and 508 transitions. [2019-12-07 18:46:08,461 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:46:08,461 INFO L276 IsEmpty]: Start isEmpty. Operand 364 states and 508 transitions. [2019-12-07 18:46:08,462 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-12-07 18:46:08,462 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:08,462 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:08,462 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:08,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:08,463 INFO L82 PathProgramCache]: Analyzing trace with hash -2134355609, now seen corresponding path program 1 times [2019-12-07 18:46:08,463 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:08,463 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1521735165] [2019-12-07 18:46:08,463 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:08,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:08,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:08,503 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1521735165] [2019-12-07 18:46:08,503 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:08,504 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:46:08,504 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1530435843] [2019-12-07 18:46:08,504 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:46:08,504 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:08,504 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:46:08,504 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:46:08,504 INFO L87 Difference]: Start difference. First operand 364 states and 508 transitions. Second operand 3 states. [2019-12-07 18:46:08,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:08,545 INFO L93 Difference]: Finished difference Result 662 states and 935 transitions. [2019-12-07 18:46:08,545 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:46:08,545 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 69 [2019-12-07 18:46:08,545 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:08,547 INFO L225 Difference]: With dead ends: 662 [2019-12-07 18:46:08,548 INFO L226 Difference]: Without dead ends: 442 [2019-12-07 18:46:08,548 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:46:08,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 442 states. [2019-12-07 18:46:08,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 442 to 360. [2019-12-07 18:46:08,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 360 states. [2019-12-07 18:46:08,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 360 states to 360 states and 501 transitions. [2019-12-07 18:46:08,564 INFO L78 Accepts]: Start accepts. Automaton has 360 states and 501 transitions. Word has length 69 [2019-12-07 18:46:08,564 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:08,564 INFO L462 AbstractCegarLoop]: Abstraction has 360 states and 501 transitions. [2019-12-07 18:46:08,564 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:46:08,564 INFO L276 IsEmpty]: Start isEmpty. Operand 360 states and 501 transitions. [2019-12-07 18:46:08,564 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:46:08,564 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:08,564 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:08,565 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:08,565 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:08,565 INFO L82 PathProgramCache]: Analyzing trace with hash 1585943340, now seen corresponding path program 1 times [2019-12-07 18:46:08,565 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:08,565 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [429766202] [2019-12-07 18:46:08,565 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:08,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:08,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:08,601 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [429766202] [2019-12-07 18:46:08,602 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:08,602 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:46:08,602 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [935386517] [2019-12-07 18:46:08,602 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:46:08,602 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:08,602 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:46:08,603 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:46:08,603 INFO L87 Difference]: Start difference. First operand 360 states and 501 transitions. Second operand 4 states. [2019-12-07 18:46:08,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:08,693 INFO L93 Difference]: Finished difference Result 953 states and 1330 transitions. [2019-12-07 18:46:08,693 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:46:08,693 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 72 [2019-12-07 18:46:08,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:08,696 INFO L225 Difference]: With dead ends: 953 [2019-12-07 18:46:08,696 INFO L226 Difference]: Without dead ends: 727 [2019-12-07 18:46:08,697 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:46:08,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 727 states. [2019-12-07 18:46:08,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 727 to 530. [2019-12-07 18:46:08,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 530 states. [2019-12-07 18:46:08,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 530 states to 530 states and 734 transitions. [2019-12-07 18:46:08,722 INFO L78 Accepts]: Start accepts. Automaton has 530 states and 734 transitions. Word has length 72 [2019-12-07 18:46:08,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:08,723 INFO L462 AbstractCegarLoop]: Abstraction has 530 states and 734 transitions. [2019-12-07 18:46:08,723 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:46:08,723 INFO L276 IsEmpty]: Start isEmpty. Operand 530 states and 734 transitions. [2019-12-07 18:46:08,723 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:46:08,723 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:08,723 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:08,724 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:08,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:08,724 INFO L82 PathProgramCache]: Analyzing trace with hash -2083950892, now seen corresponding path program 1 times [2019-12-07 18:46:08,724 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:08,724 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1583612117] [2019-12-07 18:46:08,724 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:08,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:08,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:08,756 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1583612117] [2019-12-07 18:46:08,756 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:08,756 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:46:08,756 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1093320965] [2019-12-07 18:46:08,757 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:46:08,757 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:08,757 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:46:08,757 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:46:08,757 INFO L87 Difference]: Start difference. First operand 530 states and 734 transitions. Second operand 3 states. [2019-12-07 18:46:08,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:08,781 INFO L93 Difference]: Finished difference Result 909 states and 1264 transitions. [2019-12-07 18:46:08,781 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:46:08,781 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-12-07 18:46:08,782 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:08,784 INFO L225 Difference]: With dead ends: 909 [2019-12-07 18:46:08,784 INFO L226 Difference]: Without dead ends: 530 [2019-12-07 18:46:08,784 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:46:08,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 530 states. [2019-12-07 18:46:08,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 530 to 530. [2019-12-07 18:46:08,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 530 states. [2019-12-07 18:46:08,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 530 states to 530 states and 730 transitions. [2019-12-07 18:46:08,808 INFO L78 Accepts]: Start accepts. Automaton has 530 states and 730 transitions. Word has length 72 [2019-12-07 18:46:08,808 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:08,808 INFO L462 AbstractCegarLoop]: Abstraction has 530 states and 730 transitions. [2019-12-07 18:46:08,808 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:46:08,808 INFO L276 IsEmpty]: Start isEmpty. Operand 530 states and 730 transitions. [2019-12-07 18:46:08,809 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:46:08,809 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:08,809 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:08,809 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:08,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:08,809 INFO L82 PathProgramCache]: Analyzing trace with hash 2070467794, now seen corresponding path program 1 times [2019-12-07 18:46:08,810 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:08,810 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [307588521] [2019-12-07 18:46:08,810 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:08,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:08,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:08,838 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [307588521] [2019-12-07 18:46:08,838 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:08,838 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:46:08,838 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [560693974] [2019-12-07 18:46:08,839 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:46:08,839 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:08,839 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:46:08,839 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:46:08,839 INFO L87 Difference]: Start difference. First operand 530 states and 730 transitions. Second operand 3 states. [2019-12-07 18:46:08,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:08,898 INFO L93 Difference]: Finished difference Result 1253 states and 1720 transitions. [2019-12-07 18:46:08,899 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:46:08,899 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-12-07 18:46:08,899 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:08,903 INFO L225 Difference]: With dead ends: 1253 [2019-12-07 18:46:08,903 INFO L226 Difference]: Without dead ends: 837 [2019-12-07 18:46:08,904 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:46:08,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 837 states. [2019-12-07 18:46:08,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 837 to 564. [2019-12-07 18:46:08,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 564 states. [2019-12-07 18:46:08,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 564 states to 564 states and 774 transitions. [2019-12-07 18:46:08,933 INFO L78 Accepts]: Start accepts. Automaton has 564 states and 774 transitions. Word has length 72 [2019-12-07 18:46:08,933 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:08,933 INFO L462 AbstractCegarLoop]: Abstraction has 564 states and 774 transitions. [2019-12-07 18:46:08,933 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:46:08,933 INFO L276 IsEmpty]: Start isEmpty. Operand 564 states and 774 transitions. [2019-12-07 18:46:08,934 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 18:46:08,934 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:08,934 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:08,934 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:08,934 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:08,934 INFO L82 PathProgramCache]: Analyzing trace with hash -1917205063, now seen corresponding path program 1 times [2019-12-07 18:46:08,935 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:08,935 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1354730550] [2019-12-07 18:46:08,935 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:08,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:09,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:09,025 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1354730550] [2019-12-07 18:46:09,025 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:09,026 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:46:09,026 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [640372836] [2019-12-07 18:46:09,026 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:46:09,026 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:09,026 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:46:09,027 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:46:09,027 INFO L87 Difference]: Start difference. First operand 564 states and 774 transitions. Second operand 6 states. [2019-12-07 18:46:09,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:09,257 INFO L93 Difference]: Finished difference Result 1770 states and 2483 transitions. [2019-12-07 18:46:09,258 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 18:46:09,258 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2019-12-07 18:46:09,258 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:09,264 INFO L225 Difference]: With dead ends: 1770 [2019-12-07 18:46:09,264 INFO L226 Difference]: Without dead ends: 1436 [2019-12-07 18:46:09,265 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:46:09,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1436 states. [2019-12-07 18:46:09,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1436 to 568. [2019-12-07 18:46:09,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 568 states. [2019-12-07 18:46:09,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 568 states to 568 states and 779 transitions. [2019-12-07 18:46:09,294 INFO L78 Accepts]: Start accepts. Automaton has 568 states and 779 transitions. Word has length 73 [2019-12-07 18:46:09,294 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:09,294 INFO L462 AbstractCegarLoop]: Abstraction has 568 states and 779 transitions. [2019-12-07 18:46:09,294 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:46:09,295 INFO L276 IsEmpty]: Start isEmpty. Operand 568 states and 779 transitions. [2019-12-07 18:46:09,295 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 18:46:09,295 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:09,295 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:09,295 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:09,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:09,296 INFO L82 PathProgramCache]: Analyzing trace with hash 197100160, now seen corresponding path program 1 times [2019-12-07 18:46:09,296 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:09,296 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [54215929] [2019-12-07 18:46:09,296 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:09,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:09,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:09,351 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [54215929] [2019-12-07 18:46:09,352 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:09,352 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:46:09,352 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1771805837] [2019-12-07 18:46:09,352 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:46:09,352 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:09,352 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:46:09,353 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:46:09,353 INFO L87 Difference]: Start difference. First operand 568 states and 779 transitions. Second operand 5 states. [2019-12-07 18:46:09,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:09,447 INFO L93 Difference]: Finished difference Result 888 states and 1239 transitions. [2019-12-07 18:46:09,447 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:46:09,447 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 73 [2019-12-07 18:46:09,447 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:09,450 INFO L225 Difference]: With dead ends: 888 [2019-12-07 18:46:09,450 INFO L226 Difference]: Without dead ends: 886 [2019-12-07 18:46:09,451 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:46:09,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 886 states. [2019-12-07 18:46:09,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 886 to 570. [2019-12-07 18:46:09,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 570 states. [2019-12-07 18:46:09,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 570 states to 570 states and 781 transitions. [2019-12-07 18:46:09,477 INFO L78 Accepts]: Start accepts. Automaton has 570 states and 781 transitions. Word has length 73 [2019-12-07 18:46:09,477 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:09,477 INFO L462 AbstractCegarLoop]: Abstraction has 570 states and 781 transitions. [2019-12-07 18:46:09,477 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:46:09,478 INFO L276 IsEmpty]: Start isEmpty. Operand 570 states and 781 transitions. [2019-12-07 18:46:09,478 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 18:46:09,478 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:09,478 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:09,478 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:09,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:09,479 INFO L82 PathProgramCache]: Analyzing trace with hash 2083582807, now seen corresponding path program 1 times [2019-12-07 18:46:09,479 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:09,479 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [617167534] [2019-12-07 18:46:09,479 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:09,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:09,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:09,546 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [617167534] [2019-12-07 18:46:09,546 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:09,546 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:46:09,546 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1371050350] [2019-12-07 18:46:09,547 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:46:09,547 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:09,547 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:46:09,547 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:46:09,547 INFO L87 Difference]: Start difference. First operand 570 states and 781 transitions. Second operand 6 states. [2019-12-07 18:46:09,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:09,866 INFO L93 Difference]: Finished difference Result 2037 states and 2828 transitions. [2019-12-07 18:46:09,867 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 18:46:09,867 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2019-12-07 18:46:09,867 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:09,876 INFO L225 Difference]: With dead ends: 2037 [2019-12-07 18:46:09,876 INFO L226 Difference]: Without dead ends: 1662 [2019-12-07 18:46:09,877 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:46:09,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1662 states. [2019-12-07 18:46:09,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1662 to 616. [2019-12-07 18:46:09,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 616 states. [2019-12-07 18:46:09,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 616 states to 616 states and 839 transitions. [2019-12-07 18:46:09,941 INFO L78 Accepts]: Start accepts. Automaton has 616 states and 839 transitions. Word has length 73 [2019-12-07 18:46:09,941 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:09,941 INFO L462 AbstractCegarLoop]: Abstraction has 616 states and 839 transitions. [2019-12-07 18:46:09,941 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:46:09,941 INFO L276 IsEmpty]: Start isEmpty. Operand 616 states and 839 transitions. [2019-12-07 18:46:09,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-12-07 18:46:09,942 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:09,942 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:09,942 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:09,942 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:09,943 INFO L82 PathProgramCache]: Analyzing trace with hash 1204676769, now seen corresponding path program 1 times [2019-12-07 18:46:09,943 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:09,943 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1023442532] [2019-12-07 18:46:09,943 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:09,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:10,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:10,025 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1023442532] [2019-12-07 18:46:10,025 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:10,025 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:46:10,025 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [213055376] [2019-12-07 18:46:10,025 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:46:10,026 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:10,026 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:46:10,026 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:46:10,026 INFO L87 Difference]: Start difference. First operand 616 states and 839 transitions. Second operand 6 states. [2019-12-07 18:46:10,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:10,343 INFO L93 Difference]: Finished difference Result 2364 states and 3261 transitions. [2019-12-07 18:46:10,343 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 18:46:10,343 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 74 [2019-12-07 18:46:10,343 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:10,351 INFO L225 Difference]: With dead ends: 2364 [2019-12-07 18:46:10,351 INFO L226 Difference]: Without dead ends: 1981 [2019-12-07 18:46:10,352 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:46:10,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1981 states. [2019-12-07 18:46:10,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1981 to 694. [2019-12-07 18:46:10,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 694 states. [2019-12-07 18:46:10,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 694 states to 694 states and 941 transitions. [2019-12-07 18:46:10,406 INFO L78 Accepts]: Start accepts. Automaton has 694 states and 941 transitions. Word has length 74 [2019-12-07 18:46:10,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:10,407 INFO L462 AbstractCegarLoop]: Abstraction has 694 states and 941 transitions. [2019-12-07 18:46:10,407 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:46:10,407 INFO L276 IsEmpty]: Start isEmpty. Operand 694 states and 941 transitions. [2019-12-07 18:46:10,407 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-12-07 18:46:10,407 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:10,407 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:10,408 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:10,408 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:10,408 INFO L82 PathProgramCache]: Analyzing trace with hash -217796256, now seen corresponding path program 1 times [2019-12-07 18:46:10,408 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:10,408 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [145636114] [2019-12-07 18:46:10,408 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:10,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:10,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:10,453 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [145636114] [2019-12-07 18:46:10,454 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:10,454 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:46:10,454 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [443023509] [2019-12-07 18:46:10,454 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:46:10,454 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:10,454 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:46:10,454 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:46:10,454 INFO L87 Difference]: Start difference. First operand 694 states and 941 transitions. Second operand 6 states. [2019-12-07 18:46:10,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:10,594 INFO L93 Difference]: Finished difference Result 1560 states and 2200 transitions. [2019-12-07 18:46:10,594 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 18:46:10,594 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 74 [2019-12-07 18:46:10,594 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:10,598 INFO L225 Difference]: With dead ends: 1560 [2019-12-07 18:46:10,598 INFO L226 Difference]: Without dead ends: 1160 [2019-12-07 18:46:10,599 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:46:10,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1160 states. [2019-12-07 18:46:10,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1160 to 700. [2019-12-07 18:46:10,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 700 states. [2019-12-07 18:46:10,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 700 states to 700 states and 947 transitions. [2019-12-07 18:46:10,656 INFO L78 Accepts]: Start accepts. Automaton has 700 states and 947 transitions. Word has length 74 [2019-12-07 18:46:10,656 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:10,656 INFO L462 AbstractCegarLoop]: Abstraction has 700 states and 947 transitions. [2019-12-07 18:46:10,656 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:46:10,656 INFO L276 IsEmpty]: Start isEmpty. Operand 700 states and 947 transitions. [2019-12-07 18:46:10,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-12-07 18:46:10,657 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:10,658 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:10,658 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:10,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:10,658 INFO L82 PathProgramCache]: Analyzing trace with hash -1278252476, now seen corresponding path program 1 times [2019-12-07 18:46:10,658 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:10,659 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [767636878] [2019-12-07 18:46:10,659 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:10,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:10,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:10,693 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [767636878] [2019-12-07 18:46:10,693 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:10,693 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:46:10,694 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1008610563] [2019-12-07 18:46:10,694 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:46:10,694 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:10,694 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:46:10,694 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:46:10,695 INFO L87 Difference]: Start difference. First operand 700 states and 947 transitions. Second operand 3 states. [2019-12-07 18:46:10,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:10,793 INFO L93 Difference]: Finished difference Result 1374 states and 1891 transitions. [2019-12-07 18:46:10,794 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:46:10,794 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 74 [2019-12-07 18:46:10,794 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:10,798 INFO L225 Difference]: With dead ends: 1374 [2019-12-07 18:46:10,798 INFO L226 Difference]: Without dead ends: 905 [2019-12-07 18:46:10,799 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:46:10,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 905 states. [2019-12-07 18:46:10,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 905 to 679. [2019-12-07 18:46:10,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 679 states. [2019-12-07 18:46:10,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 679 states to 679 states and 910 transitions. [2019-12-07 18:46:10,866 INFO L78 Accepts]: Start accepts. Automaton has 679 states and 910 transitions. Word has length 74 [2019-12-07 18:46:10,867 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:10,867 INFO L462 AbstractCegarLoop]: Abstraction has 679 states and 910 transitions. [2019-12-07 18:46:10,867 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:46:10,867 INFO L276 IsEmpty]: Start isEmpty. Operand 679 states and 910 transitions. [2019-12-07 18:46:10,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-12-07 18:46:10,867 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:10,868 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:10,868 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:10,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:10,868 INFO L82 PathProgramCache]: Analyzing trace with hash -1698648942, now seen corresponding path program 1 times [2019-12-07 18:46:10,868 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:10,868 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1051144427] [2019-12-07 18:46:10,868 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:10,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:10,902 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:10,903 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1051144427] [2019-12-07 18:46:10,903 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:10,903 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:46:10,903 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1033918822] [2019-12-07 18:46:10,903 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:46:10,904 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:10,904 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:46:10,904 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:46:10,904 INFO L87 Difference]: Start difference. First operand 679 states and 910 transitions. Second operand 4 states. [2019-12-07 18:46:11,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:11,051 INFO L93 Difference]: Finished difference Result 1744 states and 2350 transitions. [2019-12-07 18:46:11,052 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:46:11,052 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 75 [2019-12-07 18:46:11,052 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:11,058 INFO L225 Difference]: With dead ends: 1744 [2019-12-07 18:46:11,058 INFO L226 Difference]: Without dead ends: 1328 [2019-12-07 18:46:11,059 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:46:11,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1328 states. [2019-12-07 18:46:11,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1328 to 923. [2019-12-07 18:46:11,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 923 states. [2019-12-07 18:46:11,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 923 states to 923 states and 1237 transitions. [2019-12-07 18:46:11,118 INFO L78 Accepts]: Start accepts. Automaton has 923 states and 1237 transitions. Word has length 75 [2019-12-07 18:46:11,118 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:11,118 INFO L462 AbstractCegarLoop]: Abstraction has 923 states and 1237 transitions. [2019-12-07 18:46:11,118 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:46:11,118 INFO L276 IsEmpty]: Start isEmpty. Operand 923 states and 1237 transitions. [2019-12-07 18:46:11,119 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-12-07 18:46:11,119 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:11,119 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:11,119 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:11,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:11,120 INFO L82 PathProgramCache]: Analyzing trace with hash -1596781464, now seen corresponding path program 1 times [2019-12-07 18:46:11,120 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:11,120 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1641912748] [2019-12-07 18:46:11,120 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:11,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:11,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:11,150 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1641912748] [2019-12-07 18:46:11,150 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:11,150 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:46:11,150 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1315445026] [2019-12-07 18:46:11,151 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:46:11,151 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:11,151 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:46:11,151 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:46:11,151 INFO L87 Difference]: Start difference. First operand 923 states and 1237 transitions. Second operand 3 states. [2019-12-07 18:46:11,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:11,254 INFO L93 Difference]: Finished difference Result 1932 states and 2621 transitions. [2019-12-07 18:46:11,254 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:46:11,254 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 75 [2019-12-07 18:46:11,254 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:11,259 INFO L225 Difference]: With dead ends: 1932 [2019-12-07 18:46:11,259 INFO L226 Difference]: Without dead ends: 1327 [2019-12-07 18:46:11,260 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:46:11,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1327 states. [2019-12-07 18:46:11,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1327 to 877. [2019-12-07 18:46:11,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 877 states. [2019-12-07 18:46:11,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 877 states to 877 states and 1171 transitions. [2019-12-07 18:46:11,311 INFO L78 Accepts]: Start accepts. Automaton has 877 states and 1171 transitions. Word has length 75 [2019-12-07 18:46:11,312 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:11,312 INFO L462 AbstractCegarLoop]: Abstraction has 877 states and 1171 transitions. [2019-12-07 18:46:11,312 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:46:11,312 INFO L276 IsEmpty]: Start isEmpty. Operand 877 states and 1171 transitions. [2019-12-07 18:46:11,312 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-12-07 18:46:11,313 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:11,313 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:11,313 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:11,313 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:11,313 INFO L82 PathProgramCache]: Analyzing trace with hash -216337278, now seen corresponding path program 1 times [2019-12-07 18:46:11,313 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:11,313 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079428918] [2019-12-07 18:46:11,313 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:11,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:11,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:11,346 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2079428918] [2019-12-07 18:46:11,346 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:11,346 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:46:11,346 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [70325281] [2019-12-07 18:46:11,347 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:46:11,347 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:11,347 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:46:11,347 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:46:11,347 INFO L87 Difference]: Start difference. First operand 877 states and 1171 transitions. Second operand 4 states. [2019-12-07 18:46:11,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:11,490 INFO L93 Difference]: Finished difference Result 2042 states and 2724 transitions. [2019-12-07 18:46:11,490 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:46:11,490 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 75 [2019-12-07 18:46:11,490 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:11,495 INFO L225 Difference]: With dead ends: 2042 [2019-12-07 18:46:11,495 INFO L226 Difference]: Without dead ends: 1466 [2019-12-07 18:46:11,496 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:46:11,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1466 states. [2019-12-07 18:46:11,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1466 to 1169. [2019-12-07 18:46:11,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1169 states. [2019-12-07 18:46:11,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1169 states to 1169 states and 1551 transitions. [2019-12-07 18:46:11,576 INFO L78 Accepts]: Start accepts. Automaton has 1169 states and 1551 transitions. Word has length 75 [2019-12-07 18:46:11,576 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:11,576 INFO L462 AbstractCegarLoop]: Abstraction has 1169 states and 1551 transitions. [2019-12-07 18:46:11,576 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:46:11,576 INFO L276 IsEmpty]: Start isEmpty. Operand 1169 states and 1551 transitions. [2019-12-07 18:46:11,576 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2019-12-07 18:46:11,576 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:11,577 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:11,577 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:11,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:11,577 INFO L82 PathProgramCache]: Analyzing trace with hash -1065252519, now seen corresponding path program 1 times [2019-12-07 18:46:11,577 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:11,577 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1853604023] [2019-12-07 18:46:11,577 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:11,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:11,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:11,601 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1853604023] [2019-12-07 18:46:11,601 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:11,601 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:46:11,601 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [750198608] [2019-12-07 18:46:11,601 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:46:11,602 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:11,602 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:46:11,602 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:46:11,602 INFO L87 Difference]: Start difference. First operand 1169 states and 1551 transitions. Second operand 3 states. [2019-12-07 18:46:11,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:11,777 INFO L93 Difference]: Finished difference Result 2882 states and 3817 transitions. [2019-12-07 18:46:11,777 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:46:11,777 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 76 [2019-12-07 18:46:11,777 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:11,784 INFO L225 Difference]: With dead ends: 2882 [2019-12-07 18:46:11,784 INFO L226 Difference]: Without dead ends: 1956 [2019-12-07 18:46:11,785 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:46:11,786 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1956 states. [2019-12-07 18:46:11,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1956 to 1171. [2019-12-07 18:46:11,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1171 states. [2019-12-07 18:46:11,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1171 states to 1171 states and 1553 transitions. [2019-12-07 18:46:11,856 INFO L78 Accepts]: Start accepts. Automaton has 1171 states and 1553 transitions. Word has length 76 [2019-12-07 18:46:11,856 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:11,856 INFO L462 AbstractCegarLoop]: Abstraction has 1171 states and 1553 transitions. [2019-12-07 18:46:11,856 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:46:11,856 INFO L276 IsEmpty]: Start isEmpty. Operand 1171 states and 1553 transitions. [2019-12-07 18:46:11,857 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2019-12-07 18:46:11,857 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:11,857 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:11,857 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:11,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:11,857 INFO L82 PathProgramCache]: Analyzing trace with hash -2019206059, now seen corresponding path program 1 times [2019-12-07 18:46:11,857 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:11,857 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [343150936] [2019-12-07 18:46:11,857 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:11,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:11,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:11,897 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [343150936] [2019-12-07 18:46:11,897 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:11,897 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:46:11,898 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1986815889] [2019-12-07 18:46:11,898 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:46:11,898 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:11,898 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:46:11,898 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:46:11,898 INFO L87 Difference]: Start difference. First operand 1171 states and 1553 transitions. Second operand 4 states. [2019-12-07 18:46:12,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:12,010 INFO L93 Difference]: Finished difference Result 2437 states and 3225 transitions. [2019-12-07 18:46:12,010 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:46:12,010 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 77 [2019-12-07 18:46:12,010 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:12,015 INFO L225 Difference]: With dead ends: 2437 [2019-12-07 18:46:12,015 INFO L226 Difference]: Without dead ends: 1323 [2019-12-07 18:46:12,016 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:46:12,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1323 states. [2019-12-07 18:46:12,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1323 to 976. [2019-12-07 18:46:12,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 976 states. [2019-12-07 18:46:12,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 976 states to 976 states and 1289 transitions. [2019-12-07 18:46:12,083 INFO L78 Accepts]: Start accepts. Automaton has 976 states and 1289 transitions. Word has length 77 [2019-12-07 18:46:12,084 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:12,084 INFO L462 AbstractCegarLoop]: Abstraction has 976 states and 1289 transitions. [2019-12-07 18:46:12,084 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:46:12,084 INFO L276 IsEmpty]: Start isEmpty. Operand 976 states and 1289 transitions. [2019-12-07 18:46:12,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2019-12-07 18:46:12,084 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:12,084 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:12,085 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:12,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:12,085 INFO L82 PathProgramCache]: Analyzing trace with hash -113428458, now seen corresponding path program 1 times [2019-12-07 18:46:12,085 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:12,085 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1895879330] [2019-12-07 18:46:12,085 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:12,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:12,126 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:12,126 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1895879330] [2019-12-07 18:46:12,126 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:12,126 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:46:12,126 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1051157343] [2019-12-07 18:46:12,126 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:46:12,127 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:12,127 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:46:12,127 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:46:12,127 INFO L87 Difference]: Start difference. First operand 976 states and 1289 transitions. Second operand 4 states. [2019-12-07 18:46:12,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:12,248 INFO L93 Difference]: Finished difference Result 2242 states and 2971 transitions. [2019-12-07 18:46:12,248 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:46:12,248 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 78 [2019-12-07 18:46:12,248 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:12,253 INFO L225 Difference]: With dead ends: 2242 [2019-12-07 18:46:12,253 INFO L226 Difference]: Without dead ends: 1343 [2019-12-07 18:46:12,254 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:46:12,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1343 states. [2019-12-07 18:46:12,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1343 to 920. [2019-12-07 18:46:12,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 920 states. [2019-12-07 18:46:12,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 920 states to 920 states and 1209 transitions. [2019-12-07 18:46:12,342 INFO L78 Accepts]: Start accepts. Automaton has 920 states and 1209 transitions. Word has length 78 [2019-12-07 18:46:12,342 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:12,342 INFO L462 AbstractCegarLoop]: Abstraction has 920 states and 1209 transitions. [2019-12-07 18:46:12,342 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:46:12,343 INFO L276 IsEmpty]: Start isEmpty. Operand 920 states and 1209 transitions. [2019-12-07 18:46:12,344 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2019-12-07 18:46:12,344 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:12,344 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:12,344 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:12,344 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:12,345 INFO L82 PathProgramCache]: Analyzing trace with hash 831151167, now seen corresponding path program 1 times [2019-12-07 18:46:12,345 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:12,345 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256638595] [2019-12-07 18:46:12,345 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:12,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:12,568 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:12,568 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [256638595] [2019-12-07 18:46:12,568 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [635421059] [2019-12-07 18:46:12,568 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:12,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:12,681 INFO L264 TraceCheckSpWp]: Trace formula consists of 727 conjuncts, 9 conjunts are in the unsatisfiable core [2019-12-07 18:46:12,691 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:46:12,755 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-12-07 18:46:12,755 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-12-07 18:46:12,755 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-12-07 18:46:12,755 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [304270310] [2019-12-07 18:46:12,756 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:46:12,756 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:12,756 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:46:12,756 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:46:12,756 INFO L87 Difference]: Start difference. First operand 920 states and 1209 transitions. Second operand 6 states. [2019-12-07 18:46:13,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:13,012 INFO L93 Difference]: Finished difference Result 2836 states and 3898 transitions. [2019-12-07 18:46:13,012 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 18:46:13,012 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 122 [2019-12-07 18:46:13,012 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:13,020 INFO L225 Difference]: With dead ends: 2836 [2019-12-07 18:46:13,020 INFO L226 Difference]: Without dead ends: 2063 [2019-12-07 18:46:13,021 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 119 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2019-12-07 18:46:13,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2063 states. [2019-12-07 18:46:13,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2063 to 920. [2019-12-07 18:46:13,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 920 states. [2019-12-07 18:46:13,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 920 states to 920 states and 1206 transitions. [2019-12-07 18:46:13,096 INFO L78 Accepts]: Start accepts. Automaton has 920 states and 1206 transitions. Word has length 122 [2019-12-07 18:46:13,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:13,096 INFO L462 AbstractCegarLoop]: Abstraction has 920 states and 1206 transitions. [2019-12-07 18:46:13,096 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:46:13,096 INFO L276 IsEmpty]: Start isEmpty. Operand 920 states and 1206 transitions. [2019-12-07 18:46:13,097 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2019-12-07 18:46:13,098 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:13,098 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:13,298 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:13,299 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:13,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:13,299 INFO L82 PathProgramCache]: Analyzing trace with hash -1351562886, now seen corresponding path program 1 times [2019-12-07 18:46:13,299 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:13,299 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [634583587] [2019-12-07 18:46:13,299 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:13,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:13,513 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:13,513 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [634583587] [2019-12-07 18:46:13,514 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1637625154] [2019-12-07 18:46:13,514 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:13,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:13,622 INFO L264 TraceCheckSpWp]: Trace formula consists of 740 conjuncts, 8 conjunts are in the unsatisfiable core [2019-12-07 18:46:13,627 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:46:13,697 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-12-07 18:46:13,697 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-12-07 18:46:13,697 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-12-07 18:46:13,697 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1286406322] [2019-12-07 18:46:13,698 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:46:13,698 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:13,698 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:46:13,698 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=208, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:46:13,698 INFO L87 Difference]: Start difference. First operand 920 states and 1206 transitions. Second operand 6 states. [2019-12-07 18:46:13,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:13,991 INFO L93 Difference]: Finished difference Result 2541 states and 3449 transitions. [2019-12-07 18:46:13,991 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 18:46:13,992 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 126 [2019-12-07 18:46:13,992 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:13,995 INFO L225 Difference]: With dead ends: 2541 [2019-12-07 18:46:13,995 INFO L226 Difference]: Without dead ends: 1768 [2019-12-07 18:46:13,996 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 142 GetRequests, 123 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=56, Invalid=364, Unknown=0, NotChecked=0, Total=420 [2019-12-07 18:46:13,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1768 states. [2019-12-07 18:46:14,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1768 to 920. [2019-12-07 18:46:14,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 920 states. [2019-12-07 18:46:14,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 920 states to 920 states and 1203 transitions. [2019-12-07 18:46:14,068 INFO L78 Accepts]: Start accepts. Automaton has 920 states and 1203 transitions. Word has length 126 [2019-12-07 18:46:14,068 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:14,068 INFO L462 AbstractCegarLoop]: Abstraction has 920 states and 1203 transitions. [2019-12-07 18:46:14,068 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:46:14,068 INFO L276 IsEmpty]: Start isEmpty. Operand 920 states and 1203 transitions. [2019-12-07 18:46:14,070 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2019-12-07 18:46:14,070 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:14,070 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:14,270 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:14,271 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:14,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:14,271 INFO L82 PathProgramCache]: Analyzing trace with hash -1119292744, now seen corresponding path program 1 times [2019-12-07 18:46:14,272 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:14,272 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [179930299] [2019-12-07 18:46:14,272 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:14,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:14,474 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:14,474 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [179930299] [2019-12-07 18:46:14,475 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [99888540] [2019-12-07 18:46:14,475 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:14,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:14,585 INFO L264 TraceCheckSpWp]: Trace formula consists of 752 conjuncts, 12 conjunts are in the unsatisfiable core [2019-12-07 18:46:14,590 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:46:14,646 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-12-07 18:46:14,647 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-12-07 18:46:14,647 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-12-07 18:46:14,647 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [718080963] [2019-12-07 18:46:14,647 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:46:14,647 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:14,647 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:46:14,647 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:46:14,648 INFO L87 Difference]: Start difference. First operand 920 states and 1203 transitions. Second operand 6 states. [2019-12-07 18:46:14,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:14,959 INFO L93 Difference]: Finished difference Result 2927 states and 4004 transitions. [2019-12-07 18:46:14,960 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 18:46:14,960 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 129 [2019-12-07 18:46:14,960 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:14,963 INFO L225 Difference]: With dead ends: 2927 [2019-12-07 18:46:14,964 INFO L226 Difference]: Without dead ends: 2141 [2019-12-07 18:46:14,965 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 150 GetRequests, 129 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=79, Invalid=427, Unknown=0, NotChecked=0, Total=506 [2019-12-07 18:46:14,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2141 states. [2019-12-07 18:46:15,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2141 to 868. [2019-12-07 18:46:15,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 868 states. [2019-12-07 18:46:15,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 868 states to 868 states and 1125 transitions. [2019-12-07 18:46:15,041 INFO L78 Accepts]: Start accepts. Automaton has 868 states and 1125 transitions. Word has length 129 [2019-12-07 18:46:15,042 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:15,042 INFO L462 AbstractCegarLoop]: Abstraction has 868 states and 1125 transitions. [2019-12-07 18:46:15,042 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:46:15,042 INFO L276 IsEmpty]: Start isEmpty. Operand 868 states and 1125 transitions. [2019-12-07 18:46:15,044 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2019-12-07 18:46:15,044 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:15,044 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:15,244 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:15,245 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:15,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:15,246 INFO L82 PathProgramCache]: Analyzing trace with hash 406746349, now seen corresponding path program 1 times [2019-12-07 18:46:15,246 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:15,246 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [468343415] [2019-12-07 18:46:15,246 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:15,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:15,412 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:15,412 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [468343415] [2019-12-07 18:46:15,412 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1068067589] [2019-12-07 18:46:15,412 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:15,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:15,504 INFO L264 TraceCheckSpWp]: Trace formula consists of 753 conjuncts, 8 conjunts are in the unsatisfiable core [2019-12-07 18:46:15,507 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:46:15,568 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-12-07 18:46:15,569 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-12-07 18:46:15,569 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [10] total 15 [2019-12-07 18:46:15,569 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1641031949] [2019-12-07 18:46:15,569 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:46:15,569 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:15,569 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:46:15,569 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=181, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:46:15,570 INFO L87 Difference]: Start difference. First operand 868 states and 1125 transitions. Second operand 6 states. [2019-12-07 18:46:15,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:15,789 INFO L93 Difference]: Finished difference Result 2257 states and 3062 transitions. [2019-12-07 18:46:15,790 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 18:46:15,790 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 130 [2019-12-07 18:46:15,790 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:15,792 INFO L225 Difference]: With dead ends: 2257 [2019-12-07 18:46:15,792 INFO L226 Difference]: Without dead ends: 1550 [2019-12-07 18:46:15,793 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 144 GetRequests, 127 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=294, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:46:15,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1550 states. [2019-12-07 18:46:15,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1550 to 868. [2019-12-07 18:46:15,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 868 states. [2019-12-07 18:46:15,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 868 states to 868 states and 1124 transitions. [2019-12-07 18:46:15,860 INFO L78 Accepts]: Start accepts. Automaton has 868 states and 1124 transitions. Word has length 130 [2019-12-07 18:46:15,860 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:15,860 INFO L462 AbstractCegarLoop]: Abstraction has 868 states and 1124 transitions. [2019-12-07 18:46:15,860 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:46:15,860 INFO L276 IsEmpty]: Start isEmpty. Operand 868 states and 1124 transitions. [2019-12-07 18:46:15,861 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-12-07 18:46:15,861 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:15,861 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:16,062 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:16,063 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:16,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:16,063 INFO L82 PathProgramCache]: Analyzing trace with hash 590291048, now seen corresponding path program 1 times [2019-12-07 18:46:16,064 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:16,064 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [79928212] [2019-12-07 18:46:16,064 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:16,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:16,213 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:16,214 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [79928212] [2019-12-07 18:46:16,214 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [329521027] [2019-12-07 18:46:16,214 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:16,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:16,319 INFO L264 TraceCheckSpWp]: Trace formula consists of 767 conjuncts, 45 conjunts are in the unsatisfiable core [2019-12-07 18:46:16,322 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:46:16,547 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:16,548 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:46:16,548 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 20 [2019-12-07 18:46:16,548 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [826170393] [2019-12-07 18:46:16,548 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 18:46:16,549 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:16,549 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 18:46:16,549 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=354, Unknown=0, NotChecked=0, Total=420 [2019-12-07 18:46:16,549 INFO L87 Difference]: Start difference. First operand 868 states and 1124 transitions. Second operand 21 states. [2019-12-07 18:46:17,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:17,818 INFO L93 Difference]: Finished difference Result 2305 states and 3042 transitions. [2019-12-07 18:46:17,819 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 18:46:17,819 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 134 [2019-12-07 18:46:17,819 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:17,821 INFO L225 Difference]: With dead ends: 2305 [2019-12-07 18:46:17,821 INFO L226 Difference]: Without dead ends: 1604 [2019-12-07 18:46:17,822 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 166 GetRequests, 120 SyntacticMatches, 4 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 392 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=376, Invalid=1516, Unknown=0, NotChecked=0, Total=1892 [2019-12-07 18:46:17,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1604 states. [2019-12-07 18:46:17,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1604 to 1037. [2019-12-07 18:46:17,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1037 states. [2019-12-07 18:46:17,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1037 states to 1037 states and 1339 transitions. [2019-12-07 18:46:17,908 INFO L78 Accepts]: Start accepts. Automaton has 1037 states and 1339 transitions. Word has length 134 [2019-12-07 18:46:17,908 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:17,908 INFO L462 AbstractCegarLoop]: Abstraction has 1037 states and 1339 transitions. [2019-12-07 18:46:17,909 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 18:46:17,909 INFO L276 IsEmpty]: Start isEmpty. Operand 1037 states and 1339 transitions. [2019-12-07 18:46:17,910 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-12-07 18:46:17,910 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:17,910 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:18,110 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:18,111 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:18,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:18,111 INFO L82 PathProgramCache]: Analyzing trace with hash -1443102998, now seen corresponding path program 1 times [2019-12-07 18:46:18,111 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:18,112 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1600317820] [2019-12-07 18:46:18,112 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:18,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:18,149 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-12-07 18:46:18,149 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1600317820] [2019-12-07 18:46:18,149 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:18,149 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:46:18,149 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1242814536] [2019-12-07 18:46:18,149 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:46:18,149 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:18,149 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:46:18,150 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:46:18,150 INFO L87 Difference]: Start difference. First operand 1037 states and 1339 transitions. Second operand 4 states. [2019-12-07 18:46:18,347 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:18,347 INFO L93 Difference]: Finished difference Result 2513 states and 3271 transitions. [2019-12-07 18:46:18,348 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:46:18,348 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 134 [2019-12-07 18:46:18,348 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:18,350 INFO L225 Difference]: With dead ends: 2513 [2019-12-07 18:46:18,350 INFO L226 Difference]: Without dead ends: 1608 [2019-12-07 18:46:18,351 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:46:18,352 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1608 states. [2019-12-07 18:46:18,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1608 to 1069. [2019-12-07 18:46:18,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1069 states. [2019-12-07 18:46:18,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1069 states to 1069 states and 1367 transitions. [2019-12-07 18:46:18,458 INFO L78 Accepts]: Start accepts. Automaton has 1069 states and 1367 transitions. Word has length 134 [2019-12-07 18:46:18,458 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:18,458 INFO L462 AbstractCegarLoop]: Abstraction has 1069 states and 1367 transitions. [2019-12-07 18:46:18,458 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:46:18,458 INFO L276 IsEmpty]: Start isEmpty. Operand 1069 states and 1367 transitions. [2019-12-07 18:46:18,459 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-12-07 18:46:18,459 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:18,460 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:18,460 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:18,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:18,460 INFO L82 PathProgramCache]: Analyzing trace with hash -1719204498, now seen corresponding path program 1 times [2019-12-07 18:46:18,460 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:18,460 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1632970702] [2019-12-07 18:46:18,460 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:18,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:18,536 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-12-07 18:46:18,536 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1632970702] [2019-12-07 18:46:18,536 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:18,536 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:46:18,537 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [930784721] [2019-12-07 18:46:18,537 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:46:18,537 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:18,537 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:46:18,538 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:46:18,538 INFO L87 Difference]: Start difference. First operand 1069 states and 1367 transitions. Second operand 5 states. [2019-12-07 18:46:18,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:18,729 INFO L93 Difference]: Finished difference Result 1931 states and 2505 transitions. [2019-12-07 18:46:18,730 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:46:18,730 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 134 [2019-12-07 18:46:18,730 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:18,731 INFO L225 Difference]: With dead ends: 1931 [2019-12-07 18:46:18,731 INFO L226 Difference]: Without dead ends: 994 [2019-12-07 18:46:18,731 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:46:18,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 994 states. [2019-12-07 18:46:18,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 994 to 994. [2019-12-07 18:46:18,812 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 994 states. [2019-12-07 18:46:18,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 994 states to 994 states and 1278 transitions. [2019-12-07 18:46:18,813 INFO L78 Accepts]: Start accepts. Automaton has 994 states and 1278 transitions. Word has length 134 [2019-12-07 18:46:18,813 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:18,813 INFO L462 AbstractCegarLoop]: Abstraction has 994 states and 1278 transitions. [2019-12-07 18:46:18,813 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:46:18,813 INFO L276 IsEmpty]: Start isEmpty. Operand 994 states and 1278 transitions. [2019-12-07 18:46:18,814 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-12-07 18:46:18,814 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:18,815 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:18,815 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:18,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:18,815 INFO L82 PathProgramCache]: Analyzing trace with hash 1616018719, now seen corresponding path program 1 times [2019-12-07 18:46:18,815 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:18,815 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [297508326] [2019-12-07 18:46:18,815 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:18,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:18,924 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 16 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:18,924 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [297508326] [2019-12-07 18:46:18,924 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [975079233] [2019-12-07 18:46:18,924 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:19,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:19,023 INFO L264 TraceCheckSpWp]: Trace formula consists of 768 conjuncts, 47 conjunts are in the unsatisfiable core [2019-12-07 18:46:19,025 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:46:19,207 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 26 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:19,207 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:46:19,208 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 12] total 18 [2019-12-07 18:46:19,208 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [876423440] [2019-12-07 18:46:19,208 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 18:46:19,208 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:19,208 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 18:46:19,208 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:46:19,208 INFO L87 Difference]: Start difference. First operand 994 states and 1278 transitions. Second operand 19 states. [2019-12-07 18:46:22,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:22,120 INFO L93 Difference]: Finished difference Result 3827 states and 4980 transitions. [2019-12-07 18:46:22,120 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 85 states. [2019-12-07 18:46:22,120 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 135 [2019-12-07 18:46:22,120 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:22,124 INFO L225 Difference]: With dead ends: 3827 [2019-12-07 18:46:22,124 INFO L226 Difference]: Without dead ends: 3020 [2019-12-07 18:46:22,129 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 224 GetRequests, 121 SyntacticMatches, 4 SemanticMatches, 99 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3526 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1965, Invalid=8135, Unknown=0, NotChecked=0, Total=10100 [2019-12-07 18:46:22,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3020 states. [2019-12-07 18:46:22,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3020 to 1479. [2019-12-07 18:46:22,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1479 states. [2019-12-07 18:46:22,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1479 states to 1479 states and 1914 transitions. [2019-12-07 18:46:22,281 INFO L78 Accepts]: Start accepts. Automaton has 1479 states and 1914 transitions. Word has length 135 [2019-12-07 18:46:22,281 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:22,281 INFO L462 AbstractCegarLoop]: Abstraction has 1479 states and 1914 transitions. [2019-12-07 18:46:22,281 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 18:46:22,281 INFO L276 IsEmpty]: Start isEmpty. Operand 1479 states and 1914 transitions. [2019-12-07 18:46:22,283 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2019-12-07 18:46:22,283 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:22,283 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:22,483 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:22,483 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:22,484 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:22,484 INFO L82 PathProgramCache]: Analyzing trace with hash 1144223334, now seen corresponding path program 1 times [2019-12-07 18:46:22,484 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:22,484 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1002102332] [2019-12-07 18:46:22,484 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:22,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:22,515 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2019-12-07 18:46:22,516 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1002102332] [2019-12-07 18:46:22,516 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:22,516 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:46:22,516 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1185518552] [2019-12-07 18:46:22,516 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:46:22,516 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:22,516 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:46:22,516 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:46:22,516 INFO L87 Difference]: Start difference. First operand 1479 states and 1914 transitions. Second operand 4 states. [2019-12-07 18:46:22,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:22,688 INFO L93 Difference]: Finished difference Result 2656 states and 3470 transitions. [2019-12-07 18:46:22,688 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:46:22,688 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 136 [2019-12-07 18:46:22,688 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:22,689 INFO L225 Difference]: With dead ends: 2656 [2019-12-07 18:46:22,689 INFO L226 Difference]: Without dead ends: 1307 [2019-12-07 18:46:22,691 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:46:22,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1307 states. [2019-12-07 18:46:22,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1307 to 1307. [2019-12-07 18:46:22,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1307 states. [2019-12-07 18:46:22,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1307 states to 1307 states and 1679 transitions. [2019-12-07 18:46:22,845 INFO L78 Accepts]: Start accepts. Automaton has 1307 states and 1679 transitions. Word has length 136 [2019-12-07 18:46:22,845 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:22,845 INFO L462 AbstractCegarLoop]: Abstraction has 1307 states and 1679 transitions. [2019-12-07 18:46:22,845 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:46:22,845 INFO L276 IsEmpty]: Start isEmpty. Operand 1307 states and 1679 transitions. [2019-12-07 18:46:22,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2019-12-07 18:46:22,847 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:22,847 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:22,847 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:22,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:22,847 INFO L82 PathProgramCache]: Analyzing trace with hash 844297710, now seen corresponding path program 1 times [2019-12-07 18:46:22,847 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:22,847 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598236505] [2019-12-07 18:46:22,847 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:22,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:23,036 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:23,036 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1598236505] [2019-12-07 18:46:23,036 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [240039015] [2019-12-07 18:46:23,036 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:23,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:23,135 INFO L264 TraceCheckSpWp]: Trace formula consists of 779 conjuncts, 8 conjunts are in the unsatisfiable core [2019-12-07 18:46:23,137 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:46:23,195 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-12-07 18:46:23,195 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-12-07 18:46:23,195 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 16 [2019-12-07 18:46:23,195 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1481288252] [2019-12-07 18:46:23,195 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:46:23,195 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:23,196 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:46:23,196 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=208, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:46:23,196 INFO L87 Difference]: Start difference. First operand 1307 states and 1679 transitions. Second operand 6 states. [2019-12-07 18:46:23,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:23,603 INFO L93 Difference]: Finished difference Result 4085 states and 5399 transitions. [2019-12-07 18:46:23,603 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 18:46:23,603 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 137 [2019-12-07 18:46:23,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:23,605 INFO L225 Difference]: With dead ends: 4085 [2019-12-07 18:46:23,605 INFO L226 Difference]: Without dead ends: 2945 [2019-12-07 18:46:23,606 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 153 GetRequests, 134 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=56, Invalid=364, Unknown=0, NotChecked=0, Total=420 [2019-12-07 18:46:23,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2945 states. [2019-12-07 18:46:23,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2945 to 1307. [2019-12-07 18:46:23,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1307 states. [2019-12-07 18:46:23,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1307 states to 1307 states and 1677 transitions. [2019-12-07 18:46:23,735 INFO L78 Accepts]: Start accepts. Automaton has 1307 states and 1677 transitions. Word has length 137 [2019-12-07 18:46:23,735 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:23,735 INFO L462 AbstractCegarLoop]: Abstraction has 1307 states and 1677 transitions. [2019-12-07 18:46:23,735 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:46:23,735 INFO L276 IsEmpty]: Start isEmpty. Operand 1307 states and 1677 transitions. [2019-12-07 18:46:23,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2019-12-07 18:46:23,736 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:23,736 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:23,937 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:23,937 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:23,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:23,938 INFO L82 PathProgramCache]: Analyzing trace with hash 2032965332, now seen corresponding path program 1 times [2019-12-07 18:46:23,938 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:23,938 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [892287686] [2019-12-07 18:46:23,938 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:23,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:23,999 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-12-07 18:46:23,999 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [892287686] [2019-12-07 18:46:23,999 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:23,999 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:46:23,999 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1623099764] [2019-12-07 18:46:23,999 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:46:23,999 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:23,999 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:46:24,000 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:46:24,000 INFO L87 Difference]: Start difference. First operand 1307 states and 1677 transitions. Second operand 6 states. [2019-12-07 18:46:24,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:24,712 INFO L93 Difference]: Finished difference Result 6856 states and 8970 transitions. [2019-12-07 18:46:24,713 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 18:46:24,713 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 137 [2019-12-07 18:46:24,713 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:24,716 INFO L225 Difference]: With dead ends: 6856 [2019-12-07 18:46:24,716 INFO L226 Difference]: Without dead ends: 5736 [2019-12-07 18:46:24,718 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=66, Invalid=144, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:46:24,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5736 states. [2019-12-07 18:46:24,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5736 to 1649. [2019-12-07 18:46:24,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1649 states. [2019-12-07 18:46:24,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1649 states to 1649 states and 2077 transitions. [2019-12-07 18:46:24,891 INFO L78 Accepts]: Start accepts. Automaton has 1649 states and 2077 transitions. Word has length 137 [2019-12-07 18:46:24,891 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:24,891 INFO L462 AbstractCegarLoop]: Abstraction has 1649 states and 2077 transitions. [2019-12-07 18:46:24,891 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:46:24,891 INFO L276 IsEmpty]: Start isEmpty. Operand 1649 states and 2077 transitions. [2019-12-07 18:46:24,892 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 140 [2019-12-07 18:46:24,893 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:24,893 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:24,893 INFO L410 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:24,893 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:24,893 INFO L82 PathProgramCache]: Analyzing trace with hash -122865786, now seen corresponding path program 1 times [2019-12-07 18:46:24,893 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:24,893 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [45194925] [2019-12-07 18:46:24,893 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:24,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:25,138 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 15 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:25,138 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [45194925] [2019-12-07 18:46:25,138 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1432564165] [2019-12-07 18:46:25,139 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:25,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:25,236 INFO L264 TraceCheckSpWp]: Trace formula consists of 771 conjuncts, 25 conjunts are in the unsatisfiable core [2019-12-07 18:46:25,238 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:46:25,373 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 15 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:25,374 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:46:25,374 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 9] total 11 [2019-12-07 18:46:25,374 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [854481853] [2019-12-07 18:46:25,375 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 18:46:25,375 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:25,375 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 18:46:25,375 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=97, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:46:25,375 INFO L87 Difference]: Start difference. First operand 1649 states and 2077 transitions. Second operand 12 states. [2019-12-07 18:46:26,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:26,473 INFO L93 Difference]: Finished difference Result 4818 states and 6122 transitions. [2019-12-07 18:46:26,473 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-12-07 18:46:26,473 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 139 [2019-12-07 18:46:26,474 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:26,476 INFO L225 Difference]: With dead ends: 4818 [2019-12-07 18:46:26,476 INFO L226 Difference]: Without dead ends: 3356 [2019-12-07 18:46:26,477 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 167 GetRequests, 129 SyntacticMatches, 7 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 256 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=278, Invalid=778, Unknown=0, NotChecked=0, Total=1056 [2019-12-07 18:46:26,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3356 states. [2019-12-07 18:46:26,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3356 to 1680. [2019-12-07 18:46:26,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1680 states. [2019-12-07 18:46:26,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1680 states to 1680 states and 2116 transitions. [2019-12-07 18:46:26,654 INFO L78 Accepts]: Start accepts. Automaton has 1680 states and 2116 transitions. Word has length 139 [2019-12-07 18:46:26,654 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:26,654 INFO L462 AbstractCegarLoop]: Abstraction has 1680 states and 2116 transitions. [2019-12-07 18:46:26,655 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 18:46:26,655 INFO L276 IsEmpty]: Start isEmpty. Operand 1680 states and 2116 transitions. [2019-12-07 18:46:26,656 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2019-12-07 18:46:26,656 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:26,656 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:26,856 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:26,857 INFO L410 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:26,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:26,857 INFO L82 PathProgramCache]: Analyzing trace with hash -982040414, now seen corresponding path program 1 times [2019-12-07 18:46:26,858 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:26,858 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1620565818] [2019-12-07 18:46:26,858 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:26,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:27,039 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 33 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:27,039 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1620565818] [2019-12-07 18:46:27,039 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [257898863] [2019-12-07 18:46:27,040 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:27,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:27,135 INFO L264 TraceCheckSpWp]: Trace formula consists of 791 conjuncts, 14 conjunts are in the unsatisfiable core [2019-12-07 18:46:27,137 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:46:27,204 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 8 proven. 33 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:27,204 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:46:27,204 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 7] total 17 [2019-12-07 18:46:27,204 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1697410348] [2019-12-07 18:46:27,204 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 18:46:27,204 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:27,205 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 18:46:27,205 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2019-12-07 18:46:27,205 INFO L87 Difference]: Start difference. First operand 1680 states and 2116 transitions. Second operand 17 states. [2019-12-07 18:46:34,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:34,537 INFO L93 Difference]: Finished difference Result 8464 states and 10895 transitions. [2019-12-07 18:46:34,537 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 128 states. [2019-12-07 18:46:34,537 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 140 [2019-12-07 18:46:34,537 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:34,541 INFO L225 Difference]: With dead ends: 8464 [2019-12-07 18:46:34,541 INFO L226 Difference]: Without dead ends: 6971 [2019-12-07 18:46:34,547 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 298 GetRequests, 158 SyntacticMatches, 0 SemanticMatches, 140 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8040 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=3885, Invalid=16137, Unknown=0, NotChecked=0, Total=20022 [2019-12-07 18:46:34,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6971 states. [2019-12-07 18:46:34,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6971 to 2239. [2019-12-07 18:46:34,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2239 states. [2019-12-07 18:46:34,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2239 states to 2239 states and 2790 transitions. [2019-12-07 18:46:34,842 INFO L78 Accepts]: Start accepts. Automaton has 2239 states and 2790 transitions. Word has length 140 [2019-12-07 18:46:34,842 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:34,842 INFO L462 AbstractCegarLoop]: Abstraction has 2239 states and 2790 transitions. [2019-12-07 18:46:34,842 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 18:46:34,842 INFO L276 IsEmpty]: Start isEmpty. Operand 2239 states and 2790 transitions. [2019-12-07 18:46:34,843 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2019-12-07 18:46:34,843 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:34,843 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:35,044 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:35,044 INFO L410 AbstractCegarLoop]: === Iteration 40 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:35,045 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:35,045 INFO L82 PathProgramCache]: Analyzing trace with hash 1504281713, now seen corresponding path program 1 times [2019-12-07 18:46:35,045 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:35,045 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1411475584] [2019-12-07 18:46:35,046 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:35,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:35,154 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 24 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:35,154 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1411475584] [2019-12-07 18:46:35,154 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [589192834] [2019-12-07 18:46:35,154 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:35,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:35,259 INFO L264 TraceCheckSpWp]: Trace formula consists of 773 conjuncts, 18 conjunts are in the unsatisfiable core [2019-12-07 18:46:35,261 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:46:35,285 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 24 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:35,285 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:46:35,286 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 8 [2019-12-07 18:46:35,286 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [586584893] [2019-12-07 18:46:35,286 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 18:46:35,286 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:35,286 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 18:46:35,286 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:46:35,286 INFO L87 Difference]: Start difference. First operand 2239 states and 2790 transitions. Second operand 8 states. [2019-12-07 18:46:36,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:36,158 INFO L93 Difference]: Finished difference Result 7935 states and 10019 transitions. [2019-12-07 18:46:36,158 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 18:46:36,158 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 140 [2019-12-07 18:46:36,159 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:36,162 INFO L225 Difference]: With dead ends: 7935 [2019-12-07 18:46:36,162 INFO L226 Difference]: Without dead ends: 5946 [2019-12-07 18:46:36,164 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 166 GetRequests, 144 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 96 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=129, Invalid=423, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:46:36,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5946 states. [2019-12-07 18:46:36,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5946 to 3391. [2019-12-07 18:46:36,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3391 states. [2019-12-07 18:46:36,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3391 states to 3391 states and 4245 transitions. [2019-12-07 18:46:36,587 INFO L78 Accepts]: Start accepts. Automaton has 3391 states and 4245 transitions. Word has length 140 [2019-12-07 18:46:36,587 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:36,587 INFO L462 AbstractCegarLoop]: Abstraction has 3391 states and 4245 transitions. [2019-12-07 18:46:36,587 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 18:46:36,587 INFO L276 IsEmpty]: Start isEmpty. Operand 3391 states and 4245 transitions. [2019-12-07 18:46:36,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2019-12-07 18:46:36,589 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:36,589 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:36,790 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:36,790 INFO L410 AbstractCegarLoop]: === Iteration 41 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:36,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:36,791 INFO L82 PathProgramCache]: Analyzing trace with hash 1622723187, now seen corresponding path program 1 times [2019-12-07 18:46:36,791 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:36,791 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [344684121] [2019-12-07 18:46:36,791 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:36,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:36,849 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2019-12-07 18:46:36,849 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [344684121] [2019-12-07 18:46:36,850 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:36,850 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:46:36,850 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1467390416] [2019-12-07 18:46:36,850 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:46:36,850 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:36,850 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:46:36,850 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:46:36,850 INFO L87 Difference]: Start difference. First operand 3391 states and 4245 transitions. Second operand 4 states. [2019-12-07 18:46:37,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:37,205 INFO L93 Difference]: Finished difference Result 5881 states and 7429 transitions. [2019-12-07 18:46:37,205 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:46:37,205 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 140 [2019-12-07 18:46:37,206 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:37,207 INFO L225 Difference]: With dead ends: 5881 [2019-12-07 18:46:37,207 INFO L226 Difference]: Without dead ends: 2740 [2019-12-07 18:46:37,209 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:46:37,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2740 states. [2019-12-07 18:46:37,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2740 to 2728. [2019-12-07 18:46:37,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2728 states. [2019-12-07 18:46:37,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2728 states to 2728 states and 3407 transitions. [2019-12-07 18:46:37,513 INFO L78 Accepts]: Start accepts. Automaton has 2728 states and 3407 transitions. Word has length 140 [2019-12-07 18:46:37,513 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:37,514 INFO L462 AbstractCegarLoop]: Abstraction has 2728 states and 3407 transitions. [2019-12-07 18:46:37,514 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:46:37,514 INFO L276 IsEmpty]: Start isEmpty. Operand 2728 states and 3407 transitions. [2019-12-07 18:46:37,515 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2019-12-07 18:46:37,515 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:37,515 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:37,516 INFO L410 AbstractCegarLoop]: === Iteration 42 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:37,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:37,516 INFO L82 PathProgramCache]: Analyzing trace with hash -1882876842, now seen corresponding path program 1 times [2019-12-07 18:46:37,516 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:37,516 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514532790] [2019-12-07 18:46:37,516 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:37,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:37,588 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 24 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-12-07 18:46:37,588 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514532790] [2019-12-07 18:46:37,588 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:37,589 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:46:37,589 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1041759225] [2019-12-07 18:46:37,589 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:46:37,589 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:37,589 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:46:37,589 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:46:37,589 INFO L87 Difference]: Start difference. First operand 2728 states and 3407 transitions. Second operand 6 states. [2019-12-07 18:46:38,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:38,597 INFO L93 Difference]: Finished difference Result 9314 states and 11912 transitions. [2019-12-07 18:46:38,597 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 18:46:38,597 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 144 [2019-12-07 18:46:38,597 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:38,602 INFO L225 Difference]: With dead ends: 9314 [2019-12-07 18:46:38,602 INFO L226 Difference]: Without dead ends: 6856 [2019-12-07 18:46:38,604 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 9 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:46:38,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6856 states. [2019-12-07 18:46:38,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6856 to 2808. [2019-12-07 18:46:38,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2808 states. [2019-12-07 18:46:38,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2808 states to 2808 states and 3500 transitions. [2019-12-07 18:46:38,940 INFO L78 Accepts]: Start accepts. Automaton has 2808 states and 3500 transitions. Word has length 144 [2019-12-07 18:46:38,940 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:38,940 INFO L462 AbstractCegarLoop]: Abstraction has 2808 states and 3500 transitions. [2019-12-07 18:46:38,940 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:46:38,940 INFO L276 IsEmpty]: Start isEmpty. Operand 2808 states and 3500 transitions. [2019-12-07 18:46:38,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2019-12-07 18:46:38,942 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:38,942 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:38,942 INFO L410 AbstractCegarLoop]: === Iteration 43 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:38,942 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:38,942 INFO L82 PathProgramCache]: Analyzing trace with hash 27749283, now seen corresponding path program 1 times [2019-12-07 18:46:38,942 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:38,942 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425760470] [2019-12-07 18:46:38,942 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:38,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:38,969 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2019-12-07 18:46:38,969 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425760470] [2019-12-07 18:46:38,969 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:46:38,969 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:46:38,970 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [974865432] [2019-12-07 18:46:38,970 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:46:38,970 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:38,970 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:46:38,970 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:46:38,970 INFO L87 Difference]: Start difference. First operand 2808 states and 3500 transitions. Second operand 4 states. [2019-12-07 18:46:39,601 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:39,602 INFO L93 Difference]: Finished difference Result 7151 states and 8947 transitions. [2019-12-07 18:46:39,602 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:46:39,603 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 145 [2019-12-07 18:46:39,603 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:39,605 INFO L225 Difference]: With dead ends: 7151 [2019-12-07 18:46:39,605 INFO L226 Difference]: Without dead ends: 4491 [2019-12-07 18:46:39,607 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:46:39,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4491 states. [2019-12-07 18:46:39,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4491 to 2836. [2019-12-07 18:46:39,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2836 states. [2019-12-07 18:46:39,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2836 states to 2836 states and 3520 transitions. [2019-12-07 18:46:39,937 INFO L78 Accepts]: Start accepts. Automaton has 2836 states and 3520 transitions. Word has length 145 [2019-12-07 18:46:39,937 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:39,937 INFO L462 AbstractCegarLoop]: Abstraction has 2836 states and 3520 transitions. [2019-12-07 18:46:39,937 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:46:39,938 INFO L276 IsEmpty]: Start isEmpty. Operand 2836 states and 3520 transitions. [2019-12-07 18:46:39,939 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2019-12-07 18:46:39,939 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:39,939 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:39,940 INFO L410 AbstractCegarLoop]: === Iteration 44 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:39,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:39,940 INFO L82 PathProgramCache]: Analyzing trace with hash 1387605663, now seen corresponding path program 1 times [2019-12-07 18:46:39,940 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:39,940 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [922056507] [2019-12-07 18:46:39,940 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:39,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:40,001 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 41 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:40,001 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [922056507] [2019-12-07 18:46:40,001 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1541260297] [2019-12-07 18:46:40,001 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:40,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:40,097 INFO L264 TraceCheckSpWp]: Trace formula consists of 798 conjuncts, 5 conjunts are in the unsatisfiable core [2019-12-07 18:46:40,098 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:46:40,130 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2019-12-07 18:46:40,130 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-12-07 18:46:40,130 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [7] total 10 [2019-12-07 18:46:40,130 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [219471430] [2019-12-07 18:46:40,130 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:46:40,131 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:40,131 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:46:40,131 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:46:40,131 INFO L87 Difference]: Start difference. First operand 2836 states and 3520 transitions. Second operand 5 states. [2019-12-07 18:46:40,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:40,485 INFO L93 Difference]: Finished difference Result 5372 states and 6705 transitions. [2019-12-07 18:46:40,486 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:46:40,486 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 145 [2019-12-07 18:46:40,486 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:40,488 INFO L225 Difference]: With dead ends: 5372 [2019-12-07 18:46:40,488 INFO L226 Difference]: Without dead ends: 2615 [2019-12-07 18:46:40,490 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 151 GetRequests, 143 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:46:40,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2615 states. [2019-12-07 18:46:40,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2615 to 2615. [2019-12-07 18:46:40,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2615 states. [2019-12-07 18:46:40,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2615 states to 2615 states and 3261 transitions. [2019-12-07 18:46:40,793 INFO L78 Accepts]: Start accepts. Automaton has 2615 states and 3261 transitions. Word has length 145 [2019-12-07 18:46:40,793 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:40,794 INFO L462 AbstractCegarLoop]: Abstraction has 2615 states and 3261 transitions. [2019-12-07 18:46:40,794 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:46:40,794 INFO L276 IsEmpty]: Start isEmpty. Operand 2615 states and 3261 transitions. [2019-12-07 18:46:40,795 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2019-12-07 18:46:40,795 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:40,795 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:40,996 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:40,996 INFO L410 AbstractCegarLoop]: === Iteration 45 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:40,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:40,997 INFO L82 PathProgramCache]: Analyzing trace with hash 439953908, now seen corresponding path program 1 times [2019-12-07 18:46:40,997 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:40,997 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070837073] [2019-12-07 18:46:40,997 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:41,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:41,143 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 17 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:41,143 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1070837073] [2019-12-07 18:46:41,143 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [497199427] [2019-12-07 18:46:41,143 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:41,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:46:41,234 INFO L264 TraceCheckSpWp]: Trace formula consists of 787 conjuncts, 14 conjunts are in the unsatisfiable core [2019-12-07 18:46:41,236 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:46:41,285 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 17 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:46:41,286 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:46:41,286 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2019-12-07 18:46:41,286 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [175337817] [2019-12-07 18:46:41,286 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:46:41,286 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:46:41,286 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:46:41,286 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:46:41,286 INFO L87 Difference]: Start difference. First operand 2615 states and 3261 transitions. Second operand 7 states. [2019-12-07 18:46:42,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:46:42,302 INFO L93 Difference]: Finished difference Result 7727 states and 9807 transitions. [2019-12-07 18:46:42,302 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 18:46:42,302 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 145 [2019-12-07 18:46:42,302 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:46:42,306 INFO L225 Difference]: With dead ends: 7727 [2019-12-07 18:46:42,306 INFO L226 Difference]: Without dead ends: 5319 [2019-12-07 18:46:42,308 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 172 GetRequests, 150 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=138, Invalid=324, Unknown=0, NotChecked=0, Total=462 [2019-12-07 18:46:42,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5319 states. [2019-12-07 18:46:42,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5319 to 2615. [2019-12-07 18:46:42,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2615 states. [2019-12-07 18:46:42,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2615 states to 2615 states and 3237 transitions. [2019-12-07 18:46:42,629 INFO L78 Accepts]: Start accepts. Automaton has 2615 states and 3237 transitions. Word has length 145 [2019-12-07 18:46:42,629 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:46:42,629 INFO L462 AbstractCegarLoop]: Abstraction has 2615 states and 3237 transitions. [2019-12-07 18:46:42,629 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:46:42,629 INFO L276 IsEmpty]: Start isEmpty. Operand 2615 states and 3237 transitions. [2019-12-07 18:46:42,631 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2019-12-07 18:46:42,631 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:46:42,631 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:46:42,831 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:46:42,832 INFO L410 AbstractCegarLoop]: === Iteration 46 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:46:42,832 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:46:42,832 INFO L82 PathProgramCache]: Analyzing trace with hash -372990953, now seen corresponding path program 1 times [2019-12-07 18:46:42,832 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:46:42,833 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [696974188] [2019-12-07 18:46:42,833 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:46:42,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:46:42,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:46:42,950 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:46:42,950 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 18:46:43,063 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 06:46:43 BoogieIcfgContainer [2019-12-07 18:46:43,063 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 18:46:43,064 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:46:43,064 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:46:43,064 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:46:43,064 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:46:06" (3/4) ... [2019-12-07 18:46:43,066 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 18:46:43,179 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_1d0fe80c-a5dc-489d-a003-8faa1103dd07/bin/uautomizer/witness.graphml [2019-12-07 18:46:43,179 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:46:43,181 INFO L168 Benchmark]: Toolchain (without parser) took 37890.41 ms. Allocated memory was 1.0 GB in the beginning and 2.2 GB in the end (delta: 1.1 GB). Free memory was 943.5 MB in the beginning and 848.6 MB in the end (delta: 94.9 MB). Peak memory consumption was 1.2 GB. Max. memory is 11.5 GB. [2019-12-07 18:46:43,181 INFO L168 Benchmark]: CDTParser took 0.22 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:46:43,181 INFO L168 Benchmark]: CACSL2BoogieTranslator took 276.65 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 123.2 MB). Free memory was 943.5 MB in the beginning and 1.1 GB in the end (delta: -169.1 MB). Peak memory consumption was 24.3 MB. Max. memory is 11.5 GB. [2019-12-07 18:46:43,182 INFO L168 Benchmark]: Boogie Procedure Inliner took 44.03 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:46:43,182 INFO L168 Benchmark]: Boogie Preprocessor took 37.98 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:46:43,182 INFO L168 Benchmark]: RCFGBuilder took 587.88 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 89.3 MB). Peak memory consumption was 89.3 MB. Max. memory is 11.5 GB. [2019-12-07 18:46:43,182 INFO L168 Benchmark]: TraceAbstraction took 36825.18 ms. Allocated memory was 1.2 GB in the beginning and 2.2 GB in the end (delta: 1.0 GB). Free memory was 1.0 GB in the beginning and 907.3 MB in the end (delta: 105.3 MB). Peak memory consumption was 1.1 GB. Max. memory is 11.5 GB. [2019-12-07 18:46:43,183 INFO L168 Benchmark]: Witness Printer took 115.63 ms. Allocated memory is still 2.2 GB. Free memory was 907.3 MB in the beginning and 848.6 MB in the end (delta: 58.6 MB). Peak memory consumption was 58.6 MB. Max. memory is 11.5 GB. [2019-12-07 18:46:43,184 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.22 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 276.65 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 123.2 MB). Free memory was 943.5 MB in the beginning and 1.1 GB in the end (delta: -169.1 MB). Peak memory consumption was 24.3 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 44.03 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 37.98 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 587.88 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 89.3 MB). Peak memory consumption was 89.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 36825.18 ms. Allocated memory was 1.2 GB in the beginning and 2.2 GB in the end (delta: 1.0 GB). Free memory was 1.0 GB in the beginning and 907.3 MB in the end (delta: 105.3 MB). Peak memory consumption was 1.1 GB. Max. memory is 11.5 GB. * Witness Printer took 115.63 ms. Allocated memory is still 2.2 GB. Free memory was 907.3 MB in the beginning and 848.6 MB in the end (delta: 58.6 MB). Peak memory consumption was 58.6 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 662]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L69] msg_t nomsg = (msg_t )-1; [L70] port_t cs1 ; [L71] int8_t cs1_old ; [L72] int8_t cs1_new ; [L73] port_t cs2 ; [L74] int8_t cs2_old ; [L75] int8_t cs2_new ; [L76] port_t s1s2 ; [L77] int8_t s1s2_old ; [L78] int8_t s1s2_new ; [L79] port_t s1s1 ; [L80] int8_t s1s1_old ; [L81] int8_t s1s1_new ; [L82] port_t s2s1 ; [L83] int8_t s2s1_old ; [L84] int8_t s2s1_new ; [L85] port_t s2s2 ; [L86] int8_t s2s2_old ; [L87] int8_t s2s2_new ; [L88] port_t s1p ; [L89] int8_t s1p_old ; [L90] int8_t s1p_new ; [L91] port_t s2p ; [L92] int8_t s2p_old ; [L93] int8_t s2p_new ; [L96] _Bool side1Failed ; [L97] _Bool side2Failed ; [L98] msg_t side1_written ; [L99] msg_t side2_written ; [L102] static _Bool side1Failed_History_0 ; [L103] static _Bool side1Failed_History_1 ; [L104] static _Bool side1Failed_History_2 ; [L105] static _Bool side2Failed_History_0 ; [L106] static _Bool side2Failed_History_1 ; [L107] static _Bool side2Failed_History_2 ; [L108] static int8_t active_side_History_0 ; [L109] static int8_t active_side_History_1 ; [L110] static int8_t active_side_History_2 ; [L111] static msg_t manual_selection_History_0 ; [L112] static msg_t manual_selection_History_1 ; [L113] static msg_t manual_selection_History_2 ; [L463] void (*nodes[4])(void) = { & Console_task_each_pals_period, & Side1_activestandby_task_each_pals_period, & Side2_activestandby_task_each_pals_period, & Pendulum_prism_task_each_pals_period}; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=0, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L585] int c1 ; [L586] int i2 ; [L589] c1 = 0 [L590] side1Failed = __VERIFIER_nondet_bool() [L591] side2Failed = __VERIFIER_nondet_bool() [L592] side1_written = __VERIFIER_nondet_char() [L593] side2_written = __VERIFIER_nondet_char() [L594] side1Failed_History_0 = __VERIFIER_nondet_bool() [L595] side1Failed_History_1 = __VERIFIER_nondet_bool() [L596] side1Failed_History_2 = __VERIFIER_nondet_bool() [L597] side2Failed_History_0 = __VERIFIER_nondet_bool() [L598] side2Failed_History_1 = __VERIFIER_nondet_bool() [L599] side2Failed_History_2 = __VERIFIER_nondet_bool() [L600] active_side_History_0 = __VERIFIER_nondet_char() [L601] active_side_History_1 = __VERIFIER_nondet_char() [L602] active_side_History_2 = __VERIFIER_nondet_char() [L603] manual_selection_History_0 = __VERIFIER_nondet_char() [L604] manual_selection_History_1 = __VERIFIER_nondet_char() [L605] manual_selection_History_2 = __VERIFIER_nondet_char() [L239] COND FALSE !((int )side1Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L242] COND FALSE !((int )side2Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L245] COND FALSE !((int )active_side_History_0 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L248] COND FALSE !((int )manual_selection_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L251] COND FALSE !((int )side1Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L254] COND FALSE !((int )side2Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L257] COND FALSE !((int )active_side_History_1 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L260] COND FALSE !((int )manual_selection_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L263] COND FALSE !((int )side1Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L266] COND FALSE !((int )side2Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L269] COND FALSE !((int )active_side_History_2 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L272] COND FALSE !((int )manual_selection_History_2 != 0) [L275] return (1); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L606] i2 = init() [L608] cs1_old = nomsg [L609] cs1_new = nomsg [L610] cs2_old = nomsg [L611] cs2_new = nomsg [L612] s1s2_old = nomsg [L613] s1s2_new = nomsg [L614] s1s1_old = nomsg [L615] s1s1_new = nomsg [L616] s2s1_old = nomsg [L617] s2s1_new = nomsg [L618] s2s2_old = nomsg [L619] s2s2_new = nomsg [L620] s1p_old = nomsg [L621] s1p_new = nomsg [L622] s2p_old = nomsg [L623] s2p_new = nomsg [L624] i2 = 0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L625] COND TRUE i2 < 10 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND TRUE \read(side1Failed) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] EXPR nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L321] EXPR nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L321] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L322] EXPR nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L322] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L323] side1_written = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND TRUE (int )side1 == (int )side2 [L390] next_state = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] side2_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L450] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L451] COND FALSE !((int )side2 == 0) [L454] active_side = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-128, cs1_old=-1, cs2=0, cs2_new=-128, cs2_old=-1, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L631] cs1_old = cs1_new [L632] cs1_new = nomsg [L633] cs2_old = cs2_new [L634] cs2_new = nomsg [L635] s1s2_old = s1s2_new [L636] s1s2_new = nomsg [L637] s1s1_old = s1s1_new [L638] s1s1_new = nomsg [L639] s2s1_old = s2s1_new [L640] s2s1_new = nomsg [L641] s2s2_old = s2s2_new [L642] s2s2_new = nomsg [L643] s1p_old = s1p_new [L644] s1p_new = nomsg [L645] s2p_old = s2p_new [L646] s2p_new = nomsg [L466] int tmp ; [L467] msg_t tmp___0 ; [L468] _Bool tmp___1 ; [L469] _Bool tmp___2 ; [L470] _Bool tmp___3 ; [L471] _Bool tmp___4 ; [L472] int8_t tmp___5 ; [L473] _Bool tmp___6 ; [L474] _Bool tmp___7 ; [L475] _Bool tmp___8 ; [L476] int8_t tmp___9 ; [L477] _Bool tmp___10 ; [L478] _Bool tmp___11 ; [L479] _Bool tmp___12 ; [L480] msg_t tmp___13 ; [L481] _Bool tmp___14 ; [L482] _Bool tmp___15 ; [L483] _Bool tmp___16 ; [L484] _Bool tmp___17 ; [L485] int8_t tmp___18 ; [L486] int8_t tmp___19 ; [L487] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L490] COND FALSE !(! side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L493] COND TRUE ! side2Failed [L494] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L499] tmp___0 = read_manual_selection_history((unsigned char)1) [L500] COND TRUE ! tmp___0 [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L501] tmp___1 = read_side1_failed_history((unsigned char)1) [L502] COND TRUE ! tmp___1 [L130] COND TRUE (int )index == 0 [L131] return (side1Failed_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L503] tmp___2 = read_side1_failed_history((unsigned char)0) [L504] COND FALSE !(! tmp___2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L529] tmp___7 = read_side1_failed_history((unsigned char)1) [L530] COND FALSE !(\read(tmp___7)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L545] tmp___11 = read_side1_failed_history((unsigned char)1) [L546] COND TRUE ! tmp___11 [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L547] tmp___12 = read_side2_failed_history((unsigned char)1) [L548] COND FALSE !(\read(tmp___12)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L190] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L193] COND FALSE !((int )index == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L196] COND TRUE (int )index == 2 [L197] return (active_side_History_2); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L561] tmp___20 = read_active_side_history((unsigned char)2) [L562] COND FALSE !((int )tmp___20 > -2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L580] return (1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L647] c1 = check() [L660] COND FALSE !(! arg) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L649] i2 ++ VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-128, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L625] COND TRUE i2 < 10 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-1, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND TRUE \read(side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] EXPR nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L320] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L321] EXPR nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L321] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L322] EXPR nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L322] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L323] side1_written = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-128, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND FALSE !((int )side1 == (int )side2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L392] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L393] COND TRUE (int )side2 != (int )nomsg [L394] next_state = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] side2_written = next_state VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L450] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L451] COND TRUE (int )side2 == 0 [L452] active_side = (int8_t )2 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-128, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L631] cs1_old = cs1_new [L632] cs1_new = nomsg [L633] cs2_old = cs2_new [L634] cs2_new = nomsg [L635] s1s2_old = s1s2_new [L636] s1s2_new = nomsg [L637] s1s1_old = s1s1_new [L638] s1s1_new = nomsg [L639] s2s1_old = s2s1_new [L640] s2s1_new = nomsg [L641] s2s2_old = s2s2_new [L642] s2s2_new = nomsg [L643] s1p_old = s1p_new [L644] s1p_new = nomsg [L645] s2p_old = s2p_new [L646] s2p_new = nomsg [L466] int tmp ; [L467] msg_t tmp___0 ; [L468] _Bool tmp___1 ; [L469] _Bool tmp___2 ; [L470] _Bool tmp___3 ; [L471] _Bool tmp___4 ; [L472] int8_t tmp___5 ; [L473] _Bool tmp___6 ; [L474] _Bool tmp___7 ; [L475] _Bool tmp___8 ; [L476] int8_t tmp___9 ; [L477] _Bool tmp___10 ; [L478] _Bool tmp___11 ; [L479] _Bool tmp___12 ; [L480] msg_t tmp___13 ; [L481] _Bool tmp___14 ; [L482] _Bool tmp___15 ; [L483] _Bool tmp___16 ; [L484] _Bool tmp___17 ; [L485] int8_t tmp___18 ; [L486] int8_t tmp___19 ; [L487] int8_t tmp___20 ; VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L490] COND FALSE !(! side1Failed) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L493] COND TRUE ! side2Failed [L494] tmp = 1 VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L499] tmp___0 = read_manual_selection_history((unsigned char)1) [L500] COND FALSE !(! tmp___0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L529] tmp___7 = read_side1_failed_history((unsigned char)1) [L530] COND TRUE \read(tmp___7) [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L531] tmp___8 = read_side2_failed_history((unsigned char)1) [L532] COND TRUE ! tmp___8 [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L533] tmp___5 = read_active_side_history((unsigned char)0) [L534] COND FALSE !(! ((int )tmp___5 == 2)) [L160] COND TRUE (int )index == 0 [L161] return (side2Failed_History_0); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L537] tmp___6 = read_side2_failed_history((unsigned char)0) [L538] COND TRUE ! tmp___6 VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L539] COND TRUE ! ((int )side2_written == 1) [L540] return (0); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L647] c1 = check() [L660] COND TRUE ! arg VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L662] __VERIFIER_error() VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=-128, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 293 locations, 23 error locations. Result: UNSAFE, OverallTime: 36.6s, OverallIterations: 46, TraceHistogramMax: 2, AutomataDifference: 23.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 20637 SDtfs, 43165 SDslu, 53254 SDs, 0 SdLazy, 10392 SolverSat, 622 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 6.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2329 GetRequests, 1700 SyntacticMatches, 29 SemanticMatches, 600 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12786 ImplicationChecksByTransitivity, 8.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3391occurred in iteration=40, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 4.6s AutomataMinimizationTime, 45 MinimizatonAttempts, 39349 StatesRemovedByMinimization, 40 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.4s SsaConstructionTime, 1.3s SatisfiabilityAnalysisTime, 3.5s InterpolantComputationTime, 6060 NumberOfCodeBlocks, 6060 NumberOfCodeBlocksAsserted, 58 NumberOfCheckSat, 5858 ConstructedInterpolants, 0 QuantifiedInterpolants, 2923532 SizeOfPredicates, 60 NumberOfNonLiveVariables, 9206 ConjunctsInSsa, 213 ConjunctsInUnsatCore, 57 InterpolantComputations, 39 PerfectInterpolantSequences, 915/1156 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...