./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/podwr001_tso.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_a7c3c4b4-8785-433e-bdba-6b96778eab82/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_a7c3c4b4-8785-433e-bdba-6b96778eab82/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_a7c3c4b4-8785-433e-bdba-6b96778eab82/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_a7c3c4b4-8785-433e-bdba-6b96778eab82/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/podwr001_tso.oepc.i -s /tmp/vcloud-vcloud-master/worker/run_dir_a7c3c4b4-8785-433e-bdba-6b96778eab82/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_a7c3c4b4-8785-433e-bdba-6b96778eab82/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ab26b689afe9d6bc7724b720b01f16ae2403f0d3 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 17:39:25,831 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 17:39:25,832 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 17:39:25,840 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 17:39:25,840 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 17:39:25,841 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 17:39:25,842 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 17:39:25,843 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 17:39:25,844 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 17:39:25,845 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 17:39:25,845 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 17:39:25,846 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 17:39:25,846 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 17:39:25,847 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 17:39:25,848 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 17:39:25,849 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 17:39:25,849 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 17:39:25,850 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 17:39:25,851 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 17:39:25,853 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 17:39:25,854 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 17:39:25,854 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 17:39:25,855 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 17:39:25,855 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 17:39:25,857 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 17:39:25,857 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 17:39:25,857 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 17:39:25,858 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 17:39:25,858 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 17:39:25,859 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 17:39:25,859 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 17:39:25,859 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 17:39:25,860 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 17:39:25,860 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 17:39:25,861 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 17:39:25,861 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 17:39:25,861 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 17:39:25,861 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 17:39:25,861 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 17:39:25,862 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 17:39:25,862 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 17:39:25,863 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_a7c3c4b4-8785-433e-bdba-6b96778eab82/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 17:39:25,872 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 17:39:25,872 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 17:39:25,873 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 17:39:25,873 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 17:39:25,873 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 17:39:25,874 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 17:39:25,874 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 17:39:25,874 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 17:39:25,874 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 17:39:25,874 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 17:39:25,874 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 17:39:25,874 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 17:39:25,874 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 17:39:25,875 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 17:39:25,875 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 17:39:25,875 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 17:39:25,875 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 17:39:25,875 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 17:39:25,875 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 17:39:25,875 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 17:39:25,875 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 17:39:25,876 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:39:25,876 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 17:39:25,876 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 17:39:25,876 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 17:39:25,876 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 17:39:25,876 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 17:39:25,876 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 17:39:25,876 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 17:39:25,877 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_a7c3c4b4-8785-433e-bdba-6b96778eab82/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ab26b689afe9d6bc7724b720b01f16ae2403f0d3 [2019-12-07 17:39:25,976 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 17:39:25,987 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 17:39:25,990 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 17:39:25,991 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 17:39:25,991 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 17:39:25,992 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_a7c3c4b4-8785-433e-bdba-6b96778eab82/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/podwr001_tso.oepc.i [2019-12-07 17:39:26,039 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_a7c3c4b4-8785-433e-bdba-6b96778eab82/bin/uautomizer/data/8f9c92cbf/6a0d92c9f51341c4bc205cfa93f66655/FLAG59cf02eb8 [2019-12-07 17:39:26,399 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 17:39:26,399 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_a7c3c4b4-8785-433e-bdba-6b96778eab82/sv-benchmarks/c/pthread-wmm/podwr001_tso.oepc.i [2019-12-07 17:39:26,410 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_a7c3c4b4-8785-433e-bdba-6b96778eab82/bin/uautomizer/data/8f9c92cbf/6a0d92c9f51341c4bc205cfa93f66655/FLAG59cf02eb8 [2019-12-07 17:39:26,419 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_a7c3c4b4-8785-433e-bdba-6b96778eab82/bin/uautomizer/data/8f9c92cbf/6a0d92c9f51341c4bc205cfa93f66655 [2019-12-07 17:39:26,420 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 17:39:26,421 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 17:39:26,422 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 17:39:26,422 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 17:39:26,424 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 17:39:26,425 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:39:26" (1/1) ... [2019-12-07 17:39:26,427 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5a2ff042 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:39:26, skipping insertion in model container [2019-12-07 17:39:26,427 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:39:26" (1/1) ... [2019-12-07 17:39:26,432 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 17:39:26,461 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 17:39:26,719 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:39:26,726 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 17:39:26,768 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:39:26,812 INFO L208 MainTranslator]: Completed translation [2019-12-07 17:39:26,812 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:39:26 WrapperNode [2019-12-07 17:39:26,812 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 17:39:26,812 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 17:39:26,813 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 17:39:26,813 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 17:39:26,818 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:39:26" (1/1) ... [2019-12-07 17:39:26,831 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:39:26" (1/1) ... [2019-12-07 17:39:26,848 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 17:39:26,849 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 17:39:26,849 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 17:39:26,849 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 17:39:26,855 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:39:26" (1/1) ... [2019-12-07 17:39:26,855 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:39:26" (1/1) ... [2019-12-07 17:39:26,858 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:39:26" (1/1) ... [2019-12-07 17:39:26,858 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:39:26" (1/1) ... [2019-12-07 17:39:26,866 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:39:26" (1/1) ... [2019-12-07 17:39:26,869 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:39:26" (1/1) ... [2019-12-07 17:39:26,871 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:39:26" (1/1) ... [2019-12-07 17:39:26,875 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 17:39:26,875 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 17:39:26,875 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 17:39:26,875 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 17:39:26,876 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:39:26" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_a7c3c4b4-8785-433e-bdba-6b96778eab82/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:39:26,915 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 17:39:26,915 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 17:39:26,916 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 17:39:26,916 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 17:39:26,916 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 17:39:26,916 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 17:39:26,916 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 17:39:26,916 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 17:39:26,916 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 17:39:26,916 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 17:39:26,916 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 17:39:26,916 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 17:39:26,916 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 17:39:26,917 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 17:39:27,272 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 17:39:27,272 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 17:39:27,273 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:39:27 BoogieIcfgContainer [2019-12-07 17:39:27,273 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 17:39:27,273 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 17:39:27,273 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 17:39:27,275 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 17:39:27,275 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 05:39:26" (1/3) ... [2019-12-07 17:39:27,276 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@a063be8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:39:27, skipping insertion in model container [2019-12-07 17:39:27,276 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:39:26" (2/3) ... [2019-12-07 17:39:27,276 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@a063be8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:39:27, skipping insertion in model container [2019-12-07 17:39:27,276 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:39:27" (3/3) ... [2019-12-07 17:39:27,278 INFO L109 eAbstractionObserver]: Analyzing ICFG podwr001_tso.oepc.i [2019-12-07 17:39:27,284 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 17:39:27,284 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 17:39:27,289 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 17:39:27,290 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 17:39:27,317 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,317 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,318 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,318 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,318 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,318 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,318 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,319 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,319 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,319 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,319 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,319 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,320 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,320 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,320 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,320 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,320 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,321 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,321 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,321 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,321 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,321 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,321 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,322 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,322 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,322 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,322 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,322 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,322 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,323 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,323 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,323 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,323 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,323 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,324 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,324 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,324 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,324 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,324 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,325 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,325 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,325 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,325 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,325 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,325 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,326 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,326 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,326 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,326 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,326 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,326 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,326 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,326 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,326 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,326 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,327 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,327 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,327 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,327 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,327 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,327 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,328 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,328 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,328 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,329 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,329 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,329 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,329 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,329 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,330 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,330 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,330 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,330 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,330 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,331 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,331 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,331 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,331 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,331 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,331 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,332 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,332 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,332 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,332 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,332 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,332 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,333 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,333 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,333 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,333 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,333 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,333 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,334 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,334 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,334 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,334 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,334 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,334 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,335 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,335 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,335 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,335 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,335 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,335 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,336 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,336 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,336 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,336 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,336 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,336 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,337 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,337 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,337 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,337 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,337 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,337 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,338 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,338 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,338 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,338 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,338 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,338 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,339 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,339 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,339 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,339 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,339 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,339 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,340 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,340 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,340 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,340 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,340 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,340 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,341 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,341 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,341 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,341 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,341 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,341 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,342 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,342 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,342 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,342 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,342 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,342 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,343 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,343 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,343 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,343 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,343 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,343 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,344 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,344 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,344 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,344 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,344 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,344 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,345 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,345 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,345 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,345 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,345 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,345 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,345 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,346 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,346 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,346 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,346 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,346 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,346 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,347 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,347 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,347 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,347 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,347 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,347 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,348 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,348 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,348 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,348 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,348 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:39:27,363 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 17:39:27,379 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 17:39:27,379 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 17:39:27,380 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 17:39:27,380 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 17:39:27,380 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 17:39:27,380 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 17:39:27,380 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 17:39:27,380 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 17:39:27,390 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 176 places, 213 transitions [2019-12-07 17:39:27,392 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 176 places, 213 transitions [2019-12-07 17:39:27,458 INFO L134 PetriNetUnfolder]: 47/210 cut-off events. [2019-12-07 17:39:27,458 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 17:39:27,468 INFO L76 FinitePrefix]: Finished finitePrefix Result has 220 conditions, 210 events. 47/210 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 701 event pairs. 9/170 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 17:39:27,483 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 176 places, 213 transitions [2019-12-07 17:39:27,520 INFO L134 PetriNetUnfolder]: 47/210 cut-off events. [2019-12-07 17:39:27,520 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 17:39:27,526 INFO L76 FinitePrefix]: Finished finitePrefix Result has 220 conditions, 210 events. 47/210 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 701 event pairs. 9/170 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 17:39:27,541 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 19004 [2019-12-07 17:39:27,542 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 17:39:30,526 WARN L192 SmtUtils]: Spent 149.00 ms on a formula simplification. DAG size of input: 91 DAG size of output: 89 [2019-12-07 17:39:30,842 INFO L206 etLargeBlockEncoding]: Checked pairs total: 130045 [2019-12-07 17:39:30,842 INFO L214 etLargeBlockEncoding]: Total number of compositions: 121 [2019-12-07 17:39:30,845 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 95 places, 107 transitions [2019-12-07 17:39:50,416 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 126452 states. [2019-12-07 17:39:50,417 INFO L276 IsEmpty]: Start isEmpty. Operand 126452 states. [2019-12-07 17:39:50,421 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-12-07 17:39:50,421 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:39:50,422 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-12-07 17:39:50,422 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:39:50,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:39:50,426 INFO L82 PathProgramCache]: Analyzing trace with hash 913925, now seen corresponding path program 1 times [2019-12-07 17:39:50,431 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:39:50,431 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1240021694] [2019-12-07 17:39:50,431 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:39:50,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:39:50,567 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:39:50,567 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1240021694] [2019-12-07 17:39:50,568 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:39:50,568 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 17:39:50,569 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1406149810] [2019-12-07 17:39:50,572 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:39:50,572 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:39:50,580 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:39:50,581 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:39:50,582 INFO L87 Difference]: Start difference. First operand 126452 states. Second operand 3 states. [2019-12-07 17:39:51,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:39:51,349 INFO L93 Difference]: Finished difference Result 125570 states and 538788 transitions. [2019-12-07 17:39:51,349 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:39:51,350 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-12-07 17:39:51,350 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:39:51,966 INFO L225 Difference]: With dead ends: 125570 [2019-12-07 17:39:51,966 INFO L226 Difference]: Without dead ends: 111010 [2019-12-07 17:39:51,967 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:39:57,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111010 states. [2019-12-07 17:39:59,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111010 to 111010. [2019-12-07 17:39:59,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111010 states. [2019-12-07 17:39:59,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111010 states to 111010 states and 475060 transitions. [2019-12-07 17:39:59,702 INFO L78 Accepts]: Start accepts. Automaton has 111010 states and 475060 transitions. Word has length 3 [2019-12-07 17:39:59,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:39:59,703 INFO L462 AbstractCegarLoop]: Abstraction has 111010 states and 475060 transitions. [2019-12-07 17:39:59,703 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:39:59,703 INFO L276 IsEmpty]: Start isEmpty. Operand 111010 states and 475060 transitions. [2019-12-07 17:39:59,706 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 17:39:59,706 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:39:59,706 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:39:59,706 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:39:59,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:39:59,707 INFO L82 PathProgramCache]: Analyzing trace with hash -1753094800, now seen corresponding path program 1 times [2019-12-07 17:39:59,707 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:39:59,707 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [707998607] [2019-12-07 17:39:59,707 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:39:59,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:39:59,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:39:59,766 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [707998607] [2019-12-07 17:39:59,766 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:39:59,766 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:39:59,767 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1021959306] [2019-12-07 17:39:59,767 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:39:59,768 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:39:59,768 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:39:59,768 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:39:59,768 INFO L87 Difference]: Start difference. First operand 111010 states and 475060 transitions. Second operand 4 states. [2019-12-07 17:40:00,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:40:00,688 INFO L93 Difference]: Finished difference Result 172646 states and 710109 transitions. [2019-12-07 17:40:00,689 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:40:00,689 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 17:40:00,689 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:40:01,113 INFO L225 Difference]: With dead ends: 172646 [2019-12-07 17:40:01,113 INFO L226 Difference]: Without dead ends: 172548 [2019-12-07 17:40:01,114 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:40:06,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172548 states. [2019-12-07 17:40:10,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172548 to 158936. [2019-12-07 17:40:10,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158936 states. [2019-12-07 17:40:10,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158936 states to 158936 states and 661803 transitions. [2019-12-07 17:40:10,905 INFO L78 Accepts]: Start accepts. Automaton has 158936 states and 661803 transitions. Word has length 11 [2019-12-07 17:40:10,906 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:40:10,906 INFO L462 AbstractCegarLoop]: Abstraction has 158936 states and 661803 transitions. [2019-12-07 17:40:10,906 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:40:10,906 INFO L276 IsEmpty]: Start isEmpty. Operand 158936 states and 661803 transitions. [2019-12-07 17:40:10,911 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 17:40:10,911 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:40:10,911 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:40:10,912 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:40:10,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:40:10,912 INFO L82 PathProgramCache]: Analyzing trace with hash 216434073, now seen corresponding path program 1 times [2019-12-07 17:40:10,912 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:40:10,912 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815434388] [2019-12-07 17:40:10,912 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:40:10,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:40:10,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:40:10,961 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [815434388] [2019-12-07 17:40:10,962 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:40:10,962 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:40:10,962 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1800712798] [2019-12-07 17:40:10,962 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:40:10,962 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:40:10,962 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:40:10,962 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:40:10,962 INFO L87 Difference]: Start difference. First operand 158936 states and 661803 transitions. Second operand 4 states. [2019-12-07 17:40:12,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:40:12,124 INFO L93 Difference]: Finished difference Result 228902 states and 931210 transitions. [2019-12-07 17:40:12,124 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:40:12,124 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 17:40:12,125 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:40:12,729 INFO L225 Difference]: With dead ends: 228902 [2019-12-07 17:40:12,729 INFO L226 Difference]: Without dead ends: 228790 [2019-12-07 17:40:12,729 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:40:18,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228790 states. [2019-12-07 17:40:23,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228790 to 192327. [2019-12-07 17:40:23,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192327 states. [2019-12-07 17:40:24,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192327 states to 192327 states and 796272 transitions. [2019-12-07 17:40:24,509 INFO L78 Accepts]: Start accepts. Automaton has 192327 states and 796272 transitions. Word has length 13 [2019-12-07 17:40:24,510 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:40:24,510 INFO L462 AbstractCegarLoop]: Abstraction has 192327 states and 796272 transitions. [2019-12-07 17:40:24,510 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:40:24,510 INFO L276 IsEmpty]: Start isEmpty. Operand 192327 states and 796272 transitions. [2019-12-07 17:40:24,517 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 17:40:24,517 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:40:24,517 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:40:24,517 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:40:24,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:40:24,518 INFO L82 PathProgramCache]: Analyzing trace with hash -1948590504, now seen corresponding path program 1 times [2019-12-07 17:40:24,518 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:40:24,518 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1212593296] [2019-12-07 17:40:24,518 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:40:24,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:40:24,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:40:24,546 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1212593296] [2019-12-07 17:40:24,547 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:40:24,547 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:40:24,547 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1318262165] [2019-12-07 17:40:24,547 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:40:24,547 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:40:24,547 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:40:24,547 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:40:24,548 INFO L87 Difference]: Start difference. First operand 192327 states and 796272 transitions. Second operand 3 states. [2019-12-07 17:40:25,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:40:25,705 INFO L93 Difference]: Finished difference Result 280788 states and 1158875 transitions. [2019-12-07 17:40:25,706 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:40:25,706 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 16 [2019-12-07 17:40:25,706 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:40:26,459 INFO L225 Difference]: With dead ends: 280788 [2019-12-07 17:40:26,460 INFO L226 Difference]: Without dead ends: 280788 [2019-12-07 17:40:26,460 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:40:32,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 280788 states. [2019-12-07 17:40:39,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 280788 to 222888. [2019-12-07 17:40:39,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 222888 states. [2019-12-07 17:40:39,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222888 states to 222888 states and 926633 transitions. [2019-12-07 17:40:39,752 INFO L78 Accepts]: Start accepts. Automaton has 222888 states and 926633 transitions. Word has length 16 [2019-12-07 17:40:39,752 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:40:39,752 INFO L462 AbstractCegarLoop]: Abstraction has 222888 states and 926633 transitions. [2019-12-07 17:40:39,752 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:40:39,752 INFO L276 IsEmpty]: Start isEmpty. Operand 222888 states and 926633 transitions. [2019-12-07 17:40:39,758 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 17:40:39,758 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:40:39,759 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:40:39,759 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:40:39,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:40:39,759 INFO L82 PathProgramCache]: Analyzing trace with hash -1821591471, now seen corresponding path program 1 times [2019-12-07 17:40:39,759 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:40:39,759 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1138171978] [2019-12-07 17:40:39,759 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:40:40,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:40:40,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:40:40,175 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1138171978] [2019-12-07 17:40:40,175 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:40:40,175 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:40:40,175 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [825336149] [2019-12-07 17:40:40,176 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:40:40,176 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:40:40,176 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:40:40,176 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:40:40,176 INFO L87 Difference]: Start difference. First operand 222888 states and 926633 transitions. Second operand 5 states. [2019-12-07 17:40:41,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:40:41,734 INFO L93 Difference]: Finished difference Result 298473 states and 1226263 transitions. [2019-12-07 17:40:41,735 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 17:40:41,735 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 16 [2019-12-07 17:40:41,735 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:40:43,062 INFO L225 Difference]: With dead ends: 298473 [2019-12-07 17:40:43,062 INFO L226 Difference]: Without dead ends: 298473 [2019-12-07 17:40:43,062 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:40:49,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 298473 states. [2019-12-07 17:40:53,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 298473 to 237826. [2019-12-07 17:40:53,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 237826 states. [2019-12-07 17:40:54,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 237826 states to 237826 states and 988542 transitions. [2019-12-07 17:40:54,021 INFO L78 Accepts]: Start accepts. Automaton has 237826 states and 988542 transitions. Word has length 16 [2019-12-07 17:40:54,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:40:54,021 INFO L462 AbstractCegarLoop]: Abstraction has 237826 states and 988542 transitions. [2019-12-07 17:40:54,021 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:40:54,021 INFO L276 IsEmpty]: Start isEmpty. Operand 237826 states and 988542 transitions. [2019-12-07 17:40:54,035 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2019-12-07 17:40:54,035 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:40:54,035 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:40:54,035 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:40:54,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:40:54,035 INFO L82 PathProgramCache]: Analyzing trace with hash -504931817, now seen corresponding path program 1 times [2019-12-07 17:40:54,035 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:40:54,035 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1483616018] [2019-12-07 17:40:54,035 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:40:54,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:40:54,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:40:54,077 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1483616018] [2019-12-07 17:40:54,077 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:40:54,078 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:40:54,078 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2057919811] [2019-12-07 17:40:54,078 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:40:54,078 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:40:54,078 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:40:54,079 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:40:54,079 INFO L87 Difference]: Start difference. First operand 237826 states and 988542 transitions. Second operand 3 states. [2019-12-07 17:40:55,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:40:55,481 INFO L93 Difference]: Finished difference Result 237826 states and 978678 transitions. [2019-12-07 17:40:55,481 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:40:55,481 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 18 [2019-12-07 17:40:55,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:40:56,089 INFO L225 Difference]: With dead ends: 237826 [2019-12-07 17:40:56,090 INFO L226 Difference]: Without dead ends: 237826 [2019-12-07 17:40:56,090 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:41:04,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 237826 states. [2019-12-07 17:41:07,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 237826 to 234480. [2019-12-07 17:41:07,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 234480 states. [2019-12-07 17:41:08,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 234480 states to 234480 states and 966258 transitions. [2019-12-07 17:41:08,673 INFO L78 Accepts]: Start accepts. Automaton has 234480 states and 966258 transitions. Word has length 18 [2019-12-07 17:41:08,674 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:08,674 INFO L462 AbstractCegarLoop]: Abstraction has 234480 states and 966258 transitions. [2019-12-07 17:41:08,674 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:41:08,674 INFO L276 IsEmpty]: Start isEmpty. Operand 234480 states and 966258 transitions. [2019-12-07 17:41:08,684 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2019-12-07 17:41:08,684 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:08,684 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:08,684 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:08,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:08,684 INFO L82 PathProgramCache]: Analyzing trace with hash 138207619, now seen corresponding path program 1 times [2019-12-07 17:41:08,684 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:08,684 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1475646213] [2019-12-07 17:41:08,685 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:08,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:08,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:08,712 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1475646213] [2019-12-07 17:41:08,712 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:08,713 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:41:08,713 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1483401125] [2019-12-07 17:41:08,713 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:41:08,713 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:08,713 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:41:08,713 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:41:08,713 INFO L87 Difference]: Start difference. First operand 234480 states and 966258 transitions. Second operand 3 states. [2019-12-07 17:41:08,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:08,840 INFO L93 Difference]: Finished difference Result 42613 states and 138837 transitions. [2019-12-07 17:41:08,840 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:41:08,840 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 18 [2019-12-07 17:41:08,840 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:08,900 INFO L225 Difference]: With dead ends: 42613 [2019-12-07 17:41:08,900 INFO L226 Difference]: Without dead ends: 42613 [2019-12-07 17:41:08,900 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:41:09,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42613 states. [2019-12-07 17:41:09,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42613 to 42613. [2019-12-07 17:41:09,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42613 states. [2019-12-07 17:41:09,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42613 states to 42613 states and 138837 transitions. [2019-12-07 17:41:09,585 INFO L78 Accepts]: Start accepts. Automaton has 42613 states and 138837 transitions. Word has length 18 [2019-12-07 17:41:09,585 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:09,586 INFO L462 AbstractCegarLoop]: Abstraction has 42613 states and 138837 transitions. [2019-12-07 17:41:09,586 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:41:09,586 INFO L276 IsEmpty]: Start isEmpty. Operand 42613 states and 138837 transitions. [2019-12-07 17:41:09,591 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 17:41:09,592 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:09,592 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:09,592 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:09,592 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:09,592 INFO L82 PathProgramCache]: Analyzing trace with hash -187432510, now seen corresponding path program 1 times [2019-12-07 17:41:09,592 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:09,592 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1494619091] [2019-12-07 17:41:09,592 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:09,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:09,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:09,640 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1494619091] [2019-12-07 17:41:09,640 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:09,640 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:41:09,640 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1910353257] [2019-12-07 17:41:09,641 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:41:09,641 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:09,641 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:41:09,641 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:41:09,641 INFO L87 Difference]: Start difference. First operand 42613 states and 138837 transitions. Second operand 6 states. [2019-12-07 17:41:10,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:10,183 INFO L93 Difference]: Finished difference Result 65056 states and 205947 transitions. [2019-12-07 17:41:10,184 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 17:41:10,184 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2019-12-07 17:41:10,184 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:10,277 INFO L225 Difference]: With dead ends: 65056 [2019-12-07 17:41:10,277 INFO L226 Difference]: Without dead ends: 65042 [2019-12-07 17:41:10,277 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-12-07 17:41:10,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65042 states. [2019-12-07 17:41:11,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65042 to 42278. [2019-12-07 17:41:11,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42278 states. [2019-12-07 17:41:11,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42278 states to 42278 states and 137592 transitions. [2019-12-07 17:41:11,516 INFO L78 Accepts]: Start accepts. Automaton has 42278 states and 137592 transitions. Word has length 22 [2019-12-07 17:41:11,516 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:11,516 INFO L462 AbstractCegarLoop]: Abstraction has 42278 states and 137592 transitions. [2019-12-07 17:41:11,516 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:41:11,517 INFO L276 IsEmpty]: Start isEmpty. Operand 42278 states and 137592 transitions. [2019-12-07 17:41:11,526 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 17:41:11,526 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:11,526 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:11,526 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:11,526 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:11,526 INFO L82 PathProgramCache]: Analyzing trace with hash -200714255, now seen corresponding path program 1 times [2019-12-07 17:41:11,526 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:11,526 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2099484703] [2019-12-07 17:41:11,526 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:11,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:11,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:11,580 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2099484703] [2019-12-07 17:41:11,580 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:11,580 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:41:11,580 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [677880683] [2019-12-07 17:41:11,581 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:41:11,581 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:11,581 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:41:11,581 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:41:11,581 INFO L87 Difference]: Start difference. First operand 42278 states and 137592 transitions. Second operand 5 states. [2019-12-07 17:41:12,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:12,011 INFO L93 Difference]: Finished difference Result 59726 states and 189950 transitions. [2019-12-07 17:41:12,012 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 17:41:12,012 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 25 [2019-12-07 17:41:12,012 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:12,099 INFO L225 Difference]: With dead ends: 59726 [2019-12-07 17:41:12,099 INFO L226 Difference]: Without dead ends: 59700 [2019-12-07 17:41:12,099 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:41:12,342 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59700 states. [2019-12-07 17:41:12,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59700 to 50129. [2019-12-07 17:41:12,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50129 states. [2019-12-07 17:41:12,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50129 states to 50129 states and 162181 transitions. [2019-12-07 17:41:12,998 INFO L78 Accepts]: Start accepts. Automaton has 50129 states and 162181 transitions. Word has length 25 [2019-12-07 17:41:12,998 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:12,998 INFO L462 AbstractCegarLoop]: Abstraction has 50129 states and 162181 transitions. [2019-12-07 17:41:12,998 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:41:12,998 INFO L276 IsEmpty]: Start isEmpty. Operand 50129 states and 162181 transitions. [2019-12-07 17:41:13,013 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 17:41:13,014 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:13,014 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:13,014 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:13,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:13,014 INFO L82 PathProgramCache]: Analyzing trace with hash 611460705, now seen corresponding path program 1 times [2019-12-07 17:41:13,014 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:13,014 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [682750554] [2019-12-07 17:41:13,014 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:13,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:13,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:13,055 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [682750554] [2019-12-07 17:41:13,055 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:13,055 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:41:13,056 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1843260785] [2019-12-07 17:41:13,056 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:41:13,056 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:13,056 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:41:13,056 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:41:13,056 INFO L87 Difference]: Start difference. First operand 50129 states and 162181 transitions. Second operand 6 states. [2019-12-07 17:41:13,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:13,576 INFO L93 Difference]: Finished difference Result 71592 states and 224983 transitions. [2019-12-07 17:41:13,577 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 17:41:13,577 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 27 [2019-12-07 17:41:13,577 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:13,678 INFO L225 Difference]: With dead ends: 71592 [2019-12-07 17:41:13,678 INFO L226 Difference]: Without dead ends: 71508 [2019-12-07 17:41:13,678 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2019-12-07 17:41:14,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71508 states. [2019-12-07 17:41:14,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71508 to 53724. [2019-12-07 17:41:14,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53724 states. [2019-12-07 17:41:14,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53724 states to 53724 states and 172706 transitions. [2019-12-07 17:41:14,753 INFO L78 Accepts]: Start accepts. Automaton has 53724 states and 172706 transitions. Word has length 27 [2019-12-07 17:41:14,753 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:14,753 INFO L462 AbstractCegarLoop]: Abstraction has 53724 states and 172706 transitions. [2019-12-07 17:41:14,753 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:41:14,753 INFO L276 IsEmpty]: Start isEmpty. Operand 53724 states and 172706 transitions. [2019-12-07 17:41:14,773 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-12-07 17:41:14,773 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:14,773 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:14,773 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:14,773 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:14,774 INFO L82 PathProgramCache]: Analyzing trace with hash -969078927, now seen corresponding path program 1 times [2019-12-07 17:41:14,774 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:14,774 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1549074759] [2019-12-07 17:41:14,774 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:14,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:14,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:14,807 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1549074759] [2019-12-07 17:41:14,807 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:14,807 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:41:14,808 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707465127] [2019-12-07 17:41:14,808 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:41:14,808 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:14,808 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:41:14,808 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:41:14,808 INFO L87 Difference]: Start difference. First operand 53724 states and 172706 transitions. Second operand 4 states. [2019-12-07 17:41:14,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:14,872 INFO L93 Difference]: Finished difference Result 20754 states and 64022 transitions. [2019-12-07 17:41:14,873 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 17:41:14,873 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 29 [2019-12-07 17:41:14,873 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:14,897 INFO L225 Difference]: With dead ends: 20754 [2019-12-07 17:41:14,897 INFO L226 Difference]: Without dead ends: 20754 [2019-12-07 17:41:14,897 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:41:14,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20754 states. [2019-12-07 17:41:15,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20754 to 19543. [2019-12-07 17:41:15,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19543 states. [2019-12-07 17:41:15,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19543 states to 19543 states and 60338 transitions. [2019-12-07 17:41:15,179 INFO L78 Accepts]: Start accepts. Automaton has 19543 states and 60338 transitions. Word has length 29 [2019-12-07 17:41:15,179 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:15,179 INFO L462 AbstractCegarLoop]: Abstraction has 19543 states and 60338 transitions. [2019-12-07 17:41:15,179 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:41:15,179 INFO L276 IsEmpty]: Start isEmpty. Operand 19543 states and 60338 transitions. [2019-12-07 17:41:15,197 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 17:41:15,197 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:15,197 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:15,197 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:15,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:15,198 INFO L82 PathProgramCache]: Analyzing trace with hash -1170391984, now seen corresponding path program 1 times [2019-12-07 17:41:15,198 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:15,198 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1053606456] [2019-12-07 17:41:15,198 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:15,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:15,255 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:15,256 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1053606456] [2019-12-07 17:41:15,256 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:15,256 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:41:15,256 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [357541369] [2019-12-07 17:41:15,256 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:41:15,256 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:15,256 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:41:15,256 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:41:15,257 INFO L87 Difference]: Start difference. First operand 19543 states and 60338 transitions. Second operand 7 states. [2019-12-07 17:41:16,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:16,014 INFO L93 Difference]: Finished difference Result 27225 states and 81337 transitions. [2019-12-07 17:41:16,014 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 17:41:16,014 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 33 [2019-12-07 17:41:16,014 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:16,045 INFO L225 Difference]: With dead ends: 27225 [2019-12-07 17:41:16,045 INFO L226 Difference]: Without dead ends: 27225 [2019-12-07 17:41:16,046 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 59 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=90, Invalid=252, Unknown=0, NotChecked=0, Total=342 [2019-12-07 17:41:16,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27225 states. [2019-12-07 17:41:16,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27225 to 19532. [2019-12-07 17:41:16,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19532 states. [2019-12-07 17:41:16,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19532 states to 19532 states and 60108 transitions. [2019-12-07 17:41:16,375 INFO L78 Accepts]: Start accepts. Automaton has 19532 states and 60108 transitions. Word has length 33 [2019-12-07 17:41:16,376 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:16,376 INFO L462 AbstractCegarLoop]: Abstraction has 19532 states and 60108 transitions. [2019-12-07 17:41:16,376 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:41:16,376 INFO L276 IsEmpty]: Start isEmpty. Operand 19532 states and 60108 transitions. [2019-12-07 17:41:16,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-12-07 17:41:16,392 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:16,392 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:16,393 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:16,393 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:16,393 INFO L82 PathProgramCache]: Analyzing trace with hash 1293540528, now seen corresponding path program 1 times [2019-12-07 17:41:16,393 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:16,393 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [922287826] [2019-12-07 17:41:16,393 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:16,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:16,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:16,437 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [922287826] [2019-12-07 17:41:16,437 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:16,437 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:41:16,437 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1228583715] [2019-12-07 17:41:16,437 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:41:16,438 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:16,438 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:41:16,438 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:41:16,438 INFO L87 Difference]: Start difference. First operand 19532 states and 60108 transitions. Second operand 3 states. [2019-12-07 17:41:16,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:16,508 INFO L93 Difference]: Finished difference Result 18664 states and 56622 transitions. [2019-12-07 17:41:16,509 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:41:16,509 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 40 [2019-12-07 17:41:16,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:16,528 INFO L225 Difference]: With dead ends: 18664 [2019-12-07 17:41:16,528 INFO L226 Difference]: Without dead ends: 18664 [2019-12-07 17:41:16,529 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:41:16,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18664 states. [2019-12-07 17:41:16,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18664 to 18390. [2019-12-07 17:41:16,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18390 states. [2019-12-07 17:41:16,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18390 states to 18390 states and 55854 transitions. [2019-12-07 17:41:16,770 INFO L78 Accepts]: Start accepts. Automaton has 18390 states and 55854 transitions. Word has length 40 [2019-12-07 17:41:16,771 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:16,771 INFO L462 AbstractCegarLoop]: Abstraction has 18390 states and 55854 transitions. [2019-12-07 17:41:16,771 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:41:16,771 INFO L276 IsEmpty]: Start isEmpty. Operand 18390 states and 55854 transitions. [2019-12-07 17:41:16,786 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-12-07 17:41:16,786 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:16,786 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:16,786 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:16,786 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:16,786 INFO L82 PathProgramCache]: Analyzing trace with hash -448595313, now seen corresponding path program 1 times [2019-12-07 17:41:16,787 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:16,787 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [172045682] [2019-12-07 17:41:16,787 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:16,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:16,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:16,828 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [172045682] [2019-12-07 17:41:16,828 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:16,828 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:41:16,828 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [536470978] [2019-12-07 17:41:16,828 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:41:16,828 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:16,828 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:41:16,828 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:41:16,829 INFO L87 Difference]: Start difference. First operand 18390 states and 55854 transitions. Second operand 5 states. [2019-12-07 17:41:16,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:16,884 INFO L93 Difference]: Finished difference Result 16867 states and 52454 transitions. [2019-12-07 17:41:16,884 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:41:16,884 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 41 [2019-12-07 17:41:16,884 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:16,902 INFO L225 Difference]: With dead ends: 16867 [2019-12-07 17:41:16,903 INFO L226 Difference]: Without dead ends: 16867 [2019-12-07 17:41:16,903 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:41:16,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16867 states. [2019-12-07 17:41:17,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16867 to 15238. [2019-12-07 17:41:17,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15238 states. [2019-12-07 17:41:17,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15238 states to 15238 states and 47616 transitions. [2019-12-07 17:41:17,122 INFO L78 Accepts]: Start accepts. Automaton has 15238 states and 47616 transitions. Word has length 41 [2019-12-07 17:41:17,123 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:17,123 INFO L462 AbstractCegarLoop]: Abstraction has 15238 states and 47616 transitions. [2019-12-07 17:41:17,123 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:41:17,123 INFO L276 IsEmpty]: Start isEmpty. Operand 15238 states and 47616 transitions. [2019-12-07 17:41:17,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:41:17,137 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:17,137 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:17,137 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:17,137 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:17,137 INFO L82 PathProgramCache]: Analyzing trace with hash 1623524162, now seen corresponding path program 1 times [2019-12-07 17:41:17,137 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:17,138 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1840810702] [2019-12-07 17:41:17,138 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:17,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:17,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:17,178 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1840810702] [2019-12-07 17:41:17,178 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:17,178 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:41:17,178 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1845913750] [2019-12-07 17:41:17,178 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:41:17,178 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:17,179 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:41:17,179 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:41:17,179 INFO L87 Difference]: Start difference. First operand 15238 states and 47616 transitions. Second operand 3 states. [2019-12-07 17:41:17,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:17,266 INFO L93 Difference]: Finished difference Result 18380 states and 57153 transitions. [2019-12-07 17:41:17,266 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:41:17,267 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 17:41:17,267 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:17,287 INFO L225 Difference]: With dead ends: 18380 [2019-12-07 17:41:17,287 INFO L226 Difference]: Without dead ends: 18380 [2019-12-07 17:41:17,287 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:41:17,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18380 states. [2019-12-07 17:41:17,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18380 to 15494. [2019-12-07 17:41:17,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15494 states. [2019-12-07 17:41:17,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15494 states to 15494 states and 48492 transitions. [2019-12-07 17:41:17,538 INFO L78 Accepts]: Start accepts. Automaton has 15494 states and 48492 transitions. Word has length 66 [2019-12-07 17:41:17,539 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:17,539 INFO L462 AbstractCegarLoop]: Abstraction has 15494 states and 48492 transitions. [2019-12-07 17:41:17,539 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:41:17,539 INFO L276 IsEmpty]: Start isEmpty. Operand 15494 states and 48492 transitions. [2019-12-07 17:41:17,554 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:41:17,554 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:17,554 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:17,554 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:17,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:17,555 INFO L82 PathProgramCache]: Analyzing trace with hash 600429612, now seen corresponding path program 1 times [2019-12-07 17:41:17,555 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:17,555 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1238796717] [2019-12-07 17:41:17,555 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:17,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:17,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:17,616 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1238796717] [2019-12-07 17:41:17,617 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:17,617 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:41:17,617 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2012611053] [2019-12-07 17:41:17,617 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:41:17,617 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:17,617 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:41:17,618 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:41:17,618 INFO L87 Difference]: Start difference. First operand 15494 states and 48492 transitions. Second operand 4 states. [2019-12-07 17:41:17,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:17,719 INFO L93 Difference]: Finished difference Result 18353 states and 57063 transitions. [2019-12-07 17:41:17,719 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 17:41:17,719 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 67 [2019-12-07 17:41:17,720 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:17,738 INFO L225 Difference]: With dead ends: 18353 [2019-12-07 17:41:17,738 INFO L226 Difference]: Without dead ends: 18353 [2019-12-07 17:41:17,739 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:41:17,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18353 states. [2019-12-07 17:41:17,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18353 to 15150. [2019-12-07 17:41:17,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15150 states. [2019-12-07 17:41:17,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15150 states to 15150 states and 47431 transitions. [2019-12-07 17:41:17,972 INFO L78 Accepts]: Start accepts. Automaton has 15150 states and 47431 transitions. Word has length 67 [2019-12-07 17:41:17,972 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:17,972 INFO L462 AbstractCegarLoop]: Abstraction has 15150 states and 47431 transitions. [2019-12-07 17:41:17,972 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:41:17,973 INFO L276 IsEmpty]: Start isEmpty. Operand 15150 states and 47431 transitions. [2019-12-07 17:41:17,985 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:41:17,985 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:17,985 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:17,985 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:17,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:17,985 INFO L82 PathProgramCache]: Analyzing trace with hash 384042528, now seen corresponding path program 1 times [2019-12-07 17:41:17,986 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:17,986 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1236715379] [2019-12-07 17:41:17,986 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:18,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:18,125 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:18,125 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1236715379] [2019-12-07 17:41:18,125 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:18,125 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 17:41:18,125 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [463040691] [2019-12-07 17:41:18,126 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 17:41:18,126 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:18,126 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 17:41:18,126 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2019-12-07 17:41:18,126 INFO L87 Difference]: Start difference. First operand 15150 states and 47431 transitions. Second operand 10 states. [2019-12-07 17:41:19,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:19,321 INFO L93 Difference]: Finished difference Result 35073 states and 109582 transitions. [2019-12-07 17:41:19,321 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 17:41:19,321 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 67 [2019-12-07 17:41:19,321 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:19,347 INFO L225 Difference]: With dead ends: 35073 [2019-12-07 17:41:19,347 INFO L226 Difference]: Without dead ends: 24437 [2019-12-07 17:41:19,348 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 121 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=140, Invalid=562, Unknown=0, NotChecked=0, Total=702 [2019-12-07 17:41:19,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24437 states. [2019-12-07 17:41:19,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24437 to 18082. [2019-12-07 17:41:19,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18082 states. [2019-12-07 17:41:19,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18082 states to 18082 states and 56427 transitions. [2019-12-07 17:41:19,662 INFO L78 Accepts]: Start accepts. Automaton has 18082 states and 56427 transitions. Word has length 67 [2019-12-07 17:41:19,662 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:19,662 INFO L462 AbstractCegarLoop]: Abstraction has 18082 states and 56427 transitions. [2019-12-07 17:41:19,662 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 17:41:19,662 INFO L276 IsEmpty]: Start isEmpty. Operand 18082 states and 56427 transitions. [2019-12-07 17:41:19,677 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:41:19,677 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:19,677 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:19,678 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:19,678 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:19,678 INFO L82 PathProgramCache]: Analyzing trace with hash 1908292690, now seen corresponding path program 2 times [2019-12-07 17:41:19,678 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:19,678 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [303529359] [2019-12-07 17:41:19,678 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:19,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:19,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:19,835 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [303529359] [2019-12-07 17:41:19,836 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:19,836 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 17:41:19,836 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1176016613] [2019-12-07 17:41:19,836 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 17:41:19,836 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:19,836 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 17:41:19,837 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2019-12-07 17:41:19,837 INFO L87 Difference]: Start difference. First operand 18082 states and 56427 transitions. Second operand 10 states. [2019-12-07 17:41:20,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:20,861 INFO L93 Difference]: Finished difference Result 30588 states and 94940 transitions. [2019-12-07 17:41:20,861 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 17:41:20,861 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 67 [2019-12-07 17:41:20,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:20,894 INFO L225 Difference]: With dead ends: 30588 [2019-12-07 17:41:20,894 INFO L226 Difference]: Without dead ends: 26457 [2019-12-07 17:41:20,894 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=73, Invalid=269, Unknown=0, NotChecked=0, Total=342 [2019-12-07 17:41:20,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26457 states. [2019-12-07 17:41:21,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26457 to 18534. [2019-12-07 17:41:21,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18534 states. [2019-12-07 17:41:21,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18534 states to 18534 states and 57675 transitions. [2019-12-07 17:41:21,212 INFO L78 Accepts]: Start accepts. Automaton has 18534 states and 57675 transitions. Word has length 67 [2019-12-07 17:41:21,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:21,212 INFO L462 AbstractCegarLoop]: Abstraction has 18534 states and 57675 transitions. [2019-12-07 17:41:21,212 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 17:41:21,212 INFO L276 IsEmpty]: Start isEmpty. Operand 18534 states and 57675 transitions. [2019-12-07 17:41:21,228 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:41:21,228 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:21,228 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:21,228 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:21,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:21,228 INFO L82 PathProgramCache]: Analyzing trace with hash 993635084, now seen corresponding path program 3 times [2019-12-07 17:41:21,229 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:21,229 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070660339] [2019-12-07 17:41:21,229 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:21,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:21,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:21,346 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2070660339] [2019-12-07 17:41:21,346 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:21,346 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 17:41:21,346 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1333375547] [2019-12-07 17:41:21,347 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 17:41:21,347 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:21,347 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 17:41:21,347 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 17:41:21,347 INFO L87 Difference]: Start difference. First operand 18534 states and 57675 transitions. Second operand 11 states. [2019-12-07 17:41:22,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:22,427 INFO L93 Difference]: Finished difference Result 29036 states and 89939 transitions. [2019-12-07 17:41:22,428 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 17:41:22,428 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 67 [2019-12-07 17:41:22,428 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:22,457 INFO L225 Difference]: With dead ends: 29036 [2019-12-07 17:41:22,457 INFO L226 Difference]: Without dead ends: 25553 [2019-12-07 17:41:22,458 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 46 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=79, Invalid=341, Unknown=0, NotChecked=0, Total=420 [2019-12-07 17:41:22,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25553 states. [2019-12-07 17:41:22,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25553 to 18102. [2019-12-07 17:41:22,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18102 states. [2019-12-07 17:41:22,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18102 states to 18102 states and 56343 transitions. [2019-12-07 17:41:22,769 INFO L78 Accepts]: Start accepts. Automaton has 18102 states and 56343 transitions. Word has length 67 [2019-12-07 17:41:22,769 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:22,769 INFO L462 AbstractCegarLoop]: Abstraction has 18102 states and 56343 transitions. [2019-12-07 17:41:22,769 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 17:41:22,769 INFO L276 IsEmpty]: Start isEmpty. Operand 18102 states and 56343 transitions. [2019-12-07 17:41:22,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:41:22,784 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:22,785 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:22,785 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:22,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:22,785 INFO L82 PathProgramCache]: Analyzing trace with hash 397917466, now seen corresponding path program 4 times [2019-12-07 17:41:22,785 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:22,785 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760075961] [2019-12-07 17:41:22,785 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:22,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:23,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:23,796 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [760075961] [2019-12-07 17:41:23,796 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:23,796 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2019-12-07 17:41:23,796 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [621041324] [2019-12-07 17:41:23,796 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-12-07 17:41:23,797 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:23,797 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 17:41:23,797 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=444, Unknown=0, NotChecked=0, Total=506 [2019-12-07 17:41:23,797 INFO L87 Difference]: Start difference. First operand 18102 states and 56343 transitions. Second operand 23 states. [2019-12-07 17:41:29,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:29,194 INFO L93 Difference]: Finished difference Result 23916 states and 72568 transitions. [2019-12-07 17:41:29,195 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2019-12-07 17:41:29,195 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 67 [2019-12-07 17:41:29,195 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:29,217 INFO L225 Difference]: With dead ends: 23916 [2019-12-07 17:41:29,217 INFO L226 Difference]: Without dead ends: 21924 [2019-12-07 17:41:29,219 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 4 SyntacticMatches, 6 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 905 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=541, Invalid=3491, Unknown=0, NotChecked=0, Total=4032 [2019-12-07 17:41:29,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21924 states. [2019-12-07 17:41:29,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21924 to 20348. [2019-12-07 17:41:29,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20348 states. [2019-12-07 17:41:29,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20348 states to 20348 states and 62649 transitions. [2019-12-07 17:41:29,512 INFO L78 Accepts]: Start accepts. Automaton has 20348 states and 62649 transitions. Word has length 67 [2019-12-07 17:41:29,512 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:29,512 INFO L462 AbstractCegarLoop]: Abstraction has 20348 states and 62649 transitions. [2019-12-07 17:41:29,512 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-12-07 17:41:29,513 INFO L276 IsEmpty]: Start isEmpty. Operand 20348 states and 62649 transitions. [2019-12-07 17:41:29,530 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:41:29,530 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:29,530 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:29,530 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:29,530 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:29,531 INFO L82 PathProgramCache]: Analyzing trace with hash 68355254, now seen corresponding path program 5 times [2019-12-07 17:41:29,531 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:29,531 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [354668375] [2019-12-07 17:41:29,531 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:29,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:29,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:29,679 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [354668375] [2019-12-07 17:41:29,679 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:29,679 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 17:41:29,680 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1393915757] [2019-12-07 17:41:29,680 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 17:41:29,680 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:29,680 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 17:41:29,680 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=107, Unknown=0, NotChecked=0, Total=132 [2019-12-07 17:41:29,680 INFO L87 Difference]: Start difference. First operand 20348 states and 62649 transitions. Second operand 12 states. [2019-12-07 17:41:30,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:30,667 INFO L93 Difference]: Finished difference Result 28181 states and 85875 transitions. [2019-12-07 17:41:30,667 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-12-07 17:41:30,667 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 67 [2019-12-07 17:41:30,667 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:30,696 INFO L225 Difference]: With dead ends: 28181 [2019-12-07 17:41:30,696 INFO L226 Difference]: Without dead ends: 24934 [2019-12-07 17:41:30,696 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 76 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=111, Invalid=489, Unknown=0, NotChecked=0, Total=600 [2019-12-07 17:41:30,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24934 states. [2019-12-07 17:41:31,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24934 to 20546. [2019-12-07 17:41:31,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20546 states. [2019-12-07 17:41:31,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20546 states to 20546 states and 63158 transitions. [2019-12-07 17:41:31,034 INFO L78 Accepts]: Start accepts. Automaton has 20546 states and 63158 transitions. Word has length 67 [2019-12-07 17:41:31,034 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:31,034 INFO L462 AbstractCegarLoop]: Abstraction has 20546 states and 63158 transitions. [2019-12-07 17:41:31,034 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 17:41:31,034 INFO L276 IsEmpty]: Start isEmpty. Operand 20546 states and 63158 transitions. [2019-12-07 17:41:31,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:41:31,051 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:31,051 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:31,052 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:31,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:31,052 INFO L82 PathProgramCache]: Analyzing trace with hash 1803113718, now seen corresponding path program 6 times [2019-12-07 17:41:31,052 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:31,052 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [174477872] [2019-12-07 17:41:31,052 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:31,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:31,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:31,161 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [174477872] [2019-12-07 17:41:31,161 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:31,161 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 17:41:31,161 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [420757464] [2019-12-07 17:41:31,162 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 17:41:31,162 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:31,162 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 17:41:31,162 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2019-12-07 17:41:31,162 INFO L87 Difference]: Start difference. First operand 20546 states and 63158 transitions. Second operand 12 states. [2019-12-07 17:41:33,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:33,210 INFO L93 Difference]: Finished difference Result 26283 states and 79967 transitions. [2019-12-07 17:41:33,210 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 17:41:33,211 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 67 [2019-12-07 17:41:33,211 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:33,249 INFO L225 Difference]: With dead ends: 26283 [2019-12-07 17:41:33,249 INFO L226 Difference]: Without dead ends: 25068 [2019-12-07 17:41:33,249 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 43 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=84, Invalid=378, Unknown=0, NotChecked=0, Total=462 [2019-12-07 17:41:33,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25068 states. [2019-12-07 17:41:33,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25068 to 20408. [2019-12-07 17:41:33,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20408 states. [2019-12-07 17:41:33,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20408 states to 20408 states and 62794 transitions. [2019-12-07 17:41:33,574 INFO L78 Accepts]: Start accepts. Automaton has 20408 states and 62794 transitions. Word has length 67 [2019-12-07 17:41:33,574 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:33,574 INFO L462 AbstractCegarLoop]: Abstraction has 20408 states and 62794 transitions. [2019-12-07 17:41:33,575 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 17:41:33,575 INFO L276 IsEmpty]: Start isEmpty. Operand 20408 states and 62794 transitions. [2019-12-07 17:41:33,592 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:41:33,592 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:33,592 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:33,592 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:33,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:33,593 INFO L82 PathProgramCache]: Analyzing trace with hash 1857250972, now seen corresponding path program 7 times [2019-12-07 17:41:33,593 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:33,593 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627380865] [2019-12-07 17:41:33,593 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:33,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:34,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:34,212 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [627380865] [2019-12-07 17:41:34,212 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:34,212 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2019-12-07 17:41:34,213 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1338235148] [2019-12-07 17:41:34,213 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 17:41:34,213 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:34,213 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 17:41:34,213 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2019-12-07 17:41:34,213 INFO L87 Difference]: Start difference. First operand 20408 states and 62794 transitions. Second operand 21 states. [2019-12-07 17:41:41,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:41,489 INFO L93 Difference]: Finished difference Result 26860 states and 82121 transitions. [2019-12-07 17:41:41,489 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2019-12-07 17:41:41,489 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 67 [2019-12-07 17:41:41,490 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:41,522 INFO L225 Difference]: With dead ends: 26860 [2019-12-07 17:41:41,522 INFO L226 Difference]: Without dead ends: 25527 [2019-12-07 17:41:41,524 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 85 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2025 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=719, Invalid=6763, Unknown=0, NotChecked=0, Total=7482 [2019-12-07 17:41:41,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25527 states. [2019-12-07 17:41:41,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25527 to 22317. [2019-12-07 17:41:41,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22317 states. [2019-12-07 17:41:41,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22317 states to 22317 states and 68519 transitions. [2019-12-07 17:41:41,847 INFO L78 Accepts]: Start accepts. Automaton has 22317 states and 68519 transitions. Word has length 67 [2019-12-07 17:41:41,847 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:41,847 INFO L462 AbstractCegarLoop]: Abstraction has 22317 states and 68519 transitions. [2019-12-07 17:41:41,847 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 17:41:41,847 INFO L276 IsEmpty]: Start isEmpty. Operand 22317 states and 68519 transitions. [2019-12-07 17:41:41,866 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:41:41,866 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:41,866 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:41,867 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:41,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:41,867 INFO L82 PathProgramCache]: Analyzing trace with hash 2040469818, now seen corresponding path program 8 times [2019-12-07 17:41:41,867 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:41,867 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [297525392] [2019-12-07 17:41:41,867 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:41,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:42,255 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:42,255 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [297525392] [2019-12-07 17:41:42,255 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:42,255 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2019-12-07 17:41:42,255 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [958598298] [2019-12-07 17:41:42,255 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-12-07 17:41:42,256 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:42,256 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 17:41:42,256 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=315, Unknown=0, NotChecked=0, Total=380 [2019-12-07 17:41:42,256 INFO L87 Difference]: Start difference. First operand 22317 states and 68519 transitions. Second operand 20 states. [2019-12-07 17:41:47,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:47,549 INFO L93 Difference]: Finished difference Result 29681 states and 90180 transitions. [2019-12-07 17:41:47,550 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2019-12-07 17:41:47,550 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 67 [2019-12-07 17:41:47,551 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:47,590 INFO L225 Difference]: With dead ends: 29681 [2019-12-07 17:41:47,590 INFO L226 Difference]: Without dead ends: 25620 [2019-12-07 17:41:47,592 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 67 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 935 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=611, Invalid=3549, Unknown=0, NotChecked=0, Total=4160 [2019-12-07 17:41:47,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25620 states. [2019-12-07 17:41:47,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25620 to 21813. [2019-12-07 17:41:47,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21813 states. [2019-12-07 17:41:47,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21813 states to 21813 states and 66780 transitions. [2019-12-07 17:41:47,907 INFO L78 Accepts]: Start accepts. Automaton has 21813 states and 66780 transitions. Word has length 67 [2019-12-07 17:41:47,907 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:47,907 INFO L462 AbstractCegarLoop]: Abstraction has 21813 states and 66780 transitions. [2019-12-07 17:41:47,907 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-12-07 17:41:47,908 INFO L276 IsEmpty]: Start isEmpty. Operand 21813 states and 66780 transitions. [2019-12-07 17:41:47,926 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:41:47,926 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:47,926 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:47,926 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:47,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:47,926 INFO L82 PathProgramCache]: Analyzing trace with hash 1575321640, now seen corresponding path program 9 times [2019-12-07 17:41:47,926 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:47,927 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2055510063] [2019-12-07 17:41:47,927 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:47,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:48,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:48,448 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2055510063] [2019-12-07 17:41:48,448 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:48,449 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2019-12-07 17:41:48,449 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1139829794] [2019-12-07 17:41:48,449 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 17:41:48,449 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:48,449 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 17:41:48,449 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=360, Unknown=0, NotChecked=0, Total=420 [2019-12-07 17:41:48,449 INFO L87 Difference]: Start difference. First operand 21813 states and 66780 transitions. Second operand 21 states. [2019-12-07 17:41:57,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:57,630 INFO L93 Difference]: Finished difference Result 26588 states and 80106 transitions. [2019-12-07 17:41:57,630 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2019-12-07 17:41:57,631 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 67 [2019-12-07 17:41:57,631 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:57,660 INFO L225 Difference]: With dead ends: 26588 [2019-12-07 17:41:57,661 INFO L226 Difference]: Without dead ends: 25639 [2019-12-07 17:41:57,662 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 66 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 846 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=583, Invalid=3449, Unknown=0, NotChecked=0, Total=4032 [2019-12-07 17:41:57,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25639 states. [2019-12-07 17:41:58,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25639 to 21741. [2019-12-07 17:41:58,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21741 states. [2019-12-07 17:41:58,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21741 states to 21741 states and 66453 transitions. [2019-12-07 17:41:58,032 INFO L78 Accepts]: Start accepts. Automaton has 21741 states and 66453 transitions. Word has length 67 [2019-12-07 17:41:58,032 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:58,032 INFO L462 AbstractCegarLoop]: Abstraction has 21741 states and 66453 transitions. [2019-12-07 17:41:58,032 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 17:41:58,032 INFO L276 IsEmpty]: Start isEmpty. Operand 21741 states and 66453 transitions. [2019-12-07 17:41:58,050 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:41:58,051 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:58,051 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:58,051 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:58,051 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:58,051 INFO L82 PathProgramCache]: Analyzing trace with hash -190162996, now seen corresponding path program 10 times [2019-12-07 17:41:58,051 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:58,051 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1294568896] [2019-12-07 17:41:58,052 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:58,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:58,403 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:58,403 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1294568896] [2019-12-07 17:41:58,403 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:58,403 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2019-12-07 17:41:58,403 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1972047052] [2019-12-07 17:41:58,403 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 17:41:58,403 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:58,404 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 17:41:58,404 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=284, Unknown=0, NotChecked=0, Total=342 [2019-12-07 17:41:58,404 INFO L87 Difference]: Start difference. First operand 21741 states and 66453 transitions. Second operand 19 states. [2019-12-07 17:42:01,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:42:01,103 INFO L93 Difference]: Finished difference Result 28956 states and 86499 transitions. [2019-12-07 17:42:01,103 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2019-12-07 17:42:01,104 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 67 [2019-12-07 17:42:01,104 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:42:01,136 INFO L225 Difference]: With dead ends: 28956 [2019-12-07 17:42:01,137 INFO L226 Difference]: Without dead ends: 27298 [2019-12-07 17:42:01,138 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 923 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=566, Invalid=2974, Unknown=0, NotChecked=0, Total=3540 [2019-12-07 17:42:01,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27298 states. [2019-12-07 17:42:01,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27298 to 21999. [2019-12-07 17:42:01,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21999 states. [2019-12-07 17:42:01,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21999 states to 21999 states and 67164 transitions. [2019-12-07 17:42:01,477 INFO L78 Accepts]: Start accepts. Automaton has 21999 states and 67164 transitions. Word has length 67 [2019-12-07 17:42:01,477 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:42:01,477 INFO L462 AbstractCegarLoop]: Abstraction has 21999 states and 67164 transitions. [2019-12-07 17:42:01,477 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 17:42:01,477 INFO L276 IsEmpty]: Start isEmpty. Operand 21999 states and 67164 transitions. [2019-12-07 17:42:01,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:42:01,497 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:42:01,497 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:42:01,497 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:42:01,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:42:01,497 INFO L82 PathProgramCache]: Analyzing trace with hash 993470682, now seen corresponding path program 11 times [2019-12-07 17:42:01,497 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:42:01,497 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [697657835] [2019-12-07 17:42:01,498 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:42:01,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:42:02,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:42:02,045 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [697657835] [2019-12-07 17:42:02,045 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:42:02,045 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2019-12-07 17:42:02,045 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [64622144] [2019-12-07 17:42:02,045 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 17:42:02,045 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:42:02,046 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 17:42:02,046 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=353, Unknown=0, NotChecked=0, Total=420 [2019-12-07 17:42:02,046 INFO L87 Difference]: Start difference. First operand 21999 states and 67164 transitions. Second operand 21 states. [2019-12-07 17:42:06,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:42:06,971 INFO L93 Difference]: Finished difference Result 26160 states and 78970 transitions. [2019-12-07 17:42:06,971 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2019-12-07 17:42:06,971 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 67 [2019-12-07 17:42:06,971 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:42:06,999 INFO L225 Difference]: With dead ends: 26160 [2019-12-07 17:42:07,000 INFO L226 Difference]: Without dead ends: 25875 [2019-12-07 17:42:07,001 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 647 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=457, Invalid=2735, Unknown=0, NotChecked=0, Total=3192 [2019-12-07 17:42:07,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25875 states. [2019-12-07 17:42:07,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25875 to 21990. [2019-12-07 17:42:07,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21990 states. [2019-12-07 17:42:07,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21990 states to 21990 states and 67131 transitions. [2019-12-07 17:42:07,325 INFO L78 Accepts]: Start accepts. Automaton has 21990 states and 67131 transitions. Word has length 67 [2019-12-07 17:42:07,325 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:42:07,325 INFO L462 AbstractCegarLoop]: Abstraction has 21990 states and 67131 transitions. [2019-12-07 17:42:07,325 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 17:42:07,325 INFO L276 IsEmpty]: Start isEmpty. Operand 21990 states and 67131 transitions. [2019-12-07 17:42:07,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:42:07,345 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:42:07,345 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:42:07,345 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:42:07,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:42:07,346 INFO L82 PathProgramCache]: Analyzing trace with hash 1616492466, now seen corresponding path program 12 times [2019-12-07 17:42:07,346 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:42:07,346 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1566523091] [2019-12-07 17:42:07,346 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:42:07,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:42:07,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:42:07,879 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1566523091] [2019-12-07 17:42:07,879 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:42:07,879 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2019-12-07 17:42:07,879 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1542385527] [2019-12-07 17:42:07,879 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 17:42:07,879 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:42:07,879 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 17:42:07,880 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=352, Unknown=0, NotChecked=0, Total=420 [2019-12-07 17:42:07,880 INFO L87 Difference]: Start difference. First operand 21990 states and 67131 transitions. Second operand 21 states. [2019-12-07 17:42:14,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:42:14,004 INFO L93 Difference]: Finished difference Result 26142 states and 78904 transitions. [2019-12-07 17:42:14,005 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2019-12-07 17:42:14,005 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 67 [2019-12-07 17:42:14,005 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:42:14,035 INFO L225 Difference]: With dead ends: 26142 [2019-12-07 17:42:14,035 INFO L226 Difference]: Without dead ends: 25842 [2019-12-07 17:42:14,036 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 626 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=499, Invalid=2693, Unknown=0, NotChecked=0, Total=3192 [2019-12-07 17:42:14,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25842 states. [2019-12-07 17:42:14,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25842 to 21960. [2019-12-07 17:42:14,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21960 states. [2019-12-07 17:42:14,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21960 states to 21960 states and 67051 transitions. [2019-12-07 17:42:14,370 INFO L78 Accepts]: Start accepts. Automaton has 21960 states and 67051 transitions. Word has length 67 [2019-12-07 17:42:14,371 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:42:14,371 INFO L462 AbstractCegarLoop]: Abstraction has 21960 states and 67051 transitions. [2019-12-07 17:42:14,371 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 17:42:14,371 INFO L276 IsEmpty]: Start isEmpty. Operand 21960 states and 67051 transitions. [2019-12-07 17:42:14,391 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:42:14,391 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:42:14,391 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:42:14,392 INFO L410 AbstractCegarLoop]: === Iteration 29 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:42:14,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:42:14,392 INFO L82 PathProgramCache]: Analyzing trace with hash 1801969170, now seen corresponding path program 13 times [2019-12-07 17:42:14,392 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:42:14,392 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [692040822] [2019-12-07 17:42:14,392 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:42:14,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:42:14,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:42:14,806 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [692040822] [2019-12-07 17:42:14,806 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:42:14,806 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 17:42:14,806 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [141237704] [2019-12-07 17:42:14,807 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 17:42:14,807 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:42:14,807 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 17:42:14,807 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=250, Unknown=0, NotChecked=0, Total=306 [2019-12-07 17:42:14,807 INFO L87 Difference]: Start difference. First operand 21960 states and 67051 transitions. Second operand 18 states. [2019-12-07 17:42:19,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:42:19,225 INFO L93 Difference]: Finished difference Result 35142 states and 105332 transitions. [2019-12-07 17:42:19,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2019-12-07 17:42:19,226 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 67 [2019-12-07 17:42:19,226 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:42:19,261 INFO L225 Difference]: With dead ends: 35142 [2019-12-07 17:42:19,261 INFO L226 Difference]: Without dead ends: 30161 [2019-12-07 17:42:19,263 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 71 GetRequests, 0 SyntacticMatches, 4 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1418 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=680, Invalid=4012, Unknown=0, NotChecked=0, Total=4692 [2019-12-07 17:42:19,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30161 states. [2019-12-07 17:42:19,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30161 to 21964. [2019-12-07 17:42:19,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21964 states. [2019-12-07 17:42:19,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21964 states to 21964 states and 67071 transitions. [2019-12-07 17:42:19,628 INFO L78 Accepts]: Start accepts. Automaton has 21964 states and 67071 transitions. Word has length 67 [2019-12-07 17:42:19,628 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:42:19,628 INFO L462 AbstractCegarLoop]: Abstraction has 21964 states and 67071 transitions. [2019-12-07 17:42:19,628 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 17:42:19,628 INFO L276 IsEmpty]: Start isEmpty. Operand 21964 states and 67071 transitions. [2019-12-07 17:42:19,647 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:42:19,647 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:42:19,647 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:42:19,648 INFO L410 AbstractCegarLoop]: === Iteration 30 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:42:19,648 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:42:19,648 INFO L82 PathProgramCache]: Analyzing trace with hash -471224516, now seen corresponding path program 14 times [2019-12-07 17:42:19,648 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:42:19,648 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [44847778] [2019-12-07 17:42:19,648 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:42:19,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:42:19,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:42:19,756 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [44847778] [2019-12-07 17:42:19,756 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:42:19,756 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 17:42:19,756 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497290835] [2019-12-07 17:42:19,756 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 17:42:19,756 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:42:19,756 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 17:42:19,756 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2019-12-07 17:42:19,756 INFO L87 Difference]: Start difference. First operand 21964 states and 67071 transitions. Second operand 12 states. [2019-12-07 17:42:21,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:42:21,196 INFO L93 Difference]: Finished difference Result 30929 states and 93039 transitions. [2019-12-07 17:42:21,196 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 17:42:21,196 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 67 [2019-12-07 17:42:21,197 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:42:21,231 INFO L225 Difference]: With dead ends: 30929 [2019-12-07 17:42:21,231 INFO L226 Difference]: Without dead ends: 27029 [2019-12-07 17:42:21,231 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 128 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=150, Invalid=662, Unknown=0, NotChecked=0, Total=812 [2019-12-07 17:42:21,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27029 states. [2019-12-07 17:42:21,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27029 to 21232. [2019-12-07 17:42:21,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21232 states. [2019-12-07 17:42:21,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21232 states to 21232 states and 64832 transitions. [2019-12-07 17:42:21,567 INFO L78 Accepts]: Start accepts. Automaton has 21232 states and 64832 transitions. Word has length 67 [2019-12-07 17:42:21,567 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:42:21,568 INFO L462 AbstractCegarLoop]: Abstraction has 21232 states and 64832 transitions. [2019-12-07 17:42:21,568 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 17:42:21,568 INFO L276 IsEmpty]: Start isEmpty. Operand 21232 states and 64832 transitions. [2019-12-07 17:42:21,585 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:42:21,585 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:42:21,585 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:42:21,585 INFO L410 AbstractCegarLoop]: === Iteration 31 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:42:21,585 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:42:21,585 INFO L82 PathProgramCache]: Analyzing trace with hash -715209700, now seen corresponding path program 15 times [2019-12-07 17:42:21,586 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:42:21,586 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1622063710] [2019-12-07 17:42:21,586 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:42:21,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:42:22,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:42:22,372 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1622063710] [2019-12-07 17:42:22,372 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:42:22,372 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2019-12-07 17:42:22,372 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [80525559] [2019-12-07 17:42:22,373 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-12-07 17:42:22,373 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:42:22,373 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 17:42:22,373 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=92, Invalid=414, Unknown=0, NotChecked=0, Total=506 [2019-12-07 17:42:22,373 INFO L87 Difference]: Start difference. First operand 21232 states and 64832 transitions. Second operand 23 states. [2019-12-07 17:42:29,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:42:29,193 INFO L93 Difference]: Finished difference Result 24861 states and 74333 transitions. [2019-12-07 17:42:29,194 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2019-12-07 17:42:29,194 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 67 [2019-12-07 17:42:29,194 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:42:29,218 INFO L225 Difference]: With dead ends: 24861 [2019-12-07 17:42:29,218 INFO L226 Difference]: Without dead ends: 23378 [2019-12-07 17:42:29,219 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 782 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=467, Invalid=2613, Unknown=0, NotChecked=0, Total=3080 [2019-12-07 17:42:29,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23378 states. [2019-12-07 17:42:29,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23378 to 21313. [2019-12-07 17:42:29,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21313 states. [2019-12-07 17:42:29,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21313 states to 21313 states and 65018 transitions. [2019-12-07 17:42:29,526 INFO L78 Accepts]: Start accepts. Automaton has 21313 states and 65018 transitions. Word has length 67 [2019-12-07 17:42:29,527 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:42:29,527 INFO L462 AbstractCegarLoop]: Abstraction has 21313 states and 65018 transitions. [2019-12-07 17:42:29,527 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-12-07 17:42:29,527 INFO L276 IsEmpty]: Start isEmpty. Operand 21313 states and 65018 transitions. [2019-12-07 17:42:29,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:42:29,545 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:42:29,546 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:42:29,546 INFO L410 AbstractCegarLoop]: === Iteration 32 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:42:29,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:42:29,546 INFO L82 PathProgramCache]: Analyzing trace with hash 2074773522, now seen corresponding path program 16 times [2019-12-07 17:42:29,546 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:42:29,546 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [491699393] [2019-12-07 17:42:29,546 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:42:29,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:42:29,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:42:29,938 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [491699393] [2019-12-07 17:42:29,938 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:42:29,938 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 17:42:29,938 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [942760123] [2019-12-07 17:42:29,938 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 17:42:29,939 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:42:29,939 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 17:42:29,939 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=229, Unknown=0, NotChecked=0, Total=272 [2019-12-07 17:42:29,939 INFO L87 Difference]: Start difference. First operand 21313 states and 65018 transitions. Second operand 17 states. [2019-12-07 17:42:33,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:42:33,935 INFO L93 Difference]: Finished difference Result 32050 states and 98712 transitions. [2019-12-07 17:42:33,935 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2019-12-07 17:42:33,936 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 67 [2019-12-07 17:42:33,936 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:42:33,969 INFO L225 Difference]: With dead ends: 32050 [2019-12-07 17:42:33,969 INFO L226 Difference]: Without dead ends: 28790 [2019-12-07 17:42:33,970 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 2 SyntacticMatches, 4 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 733 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=452, Invalid=2518, Unknown=0, NotChecked=0, Total=2970 [2019-12-07 17:42:34,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28790 states. [2019-12-07 17:42:34,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28790 to 22906. [2019-12-07 17:42:34,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22906 states. [2019-12-07 17:42:34,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22906 states to 22906 states and 70231 transitions. [2019-12-07 17:42:34,358 INFO L78 Accepts]: Start accepts. Automaton has 22906 states and 70231 transitions. Word has length 67 [2019-12-07 17:42:34,358 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:42:34,358 INFO L462 AbstractCegarLoop]: Abstraction has 22906 states and 70231 transitions. [2019-12-07 17:42:34,358 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 17:42:34,358 INFO L276 IsEmpty]: Start isEmpty. Operand 22906 states and 70231 transitions. [2019-12-07 17:42:34,377 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:42:34,378 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:42:34,378 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:42:34,378 INFO L410 AbstractCegarLoop]: === Iteration 33 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:42:34,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:42:34,378 INFO L82 PathProgramCache]: Analyzing trace with hash -2036974928, now seen corresponding path program 17 times [2019-12-07 17:42:34,378 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:42:34,378 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1261250847] [2019-12-07 17:42:34,378 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:42:34,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:42:34,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:42:34,800 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1261250847] [2019-12-07 17:42:34,800 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:42:34,800 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2019-12-07 17:42:34,801 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992535305] [2019-12-07 17:42:34,801 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-12-07 17:42:34,801 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:42:34,801 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 17:42:34,801 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=321, Unknown=0, NotChecked=0, Total=380 [2019-12-07 17:42:34,801 INFO L87 Difference]: Start difference. First operand 22906 states and 70231 transitions. Second operand 20 states. [2019-12-07 17:42:38,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:42:38,114 INFO L93 Difference]: Finished difference Result 25013 states and 76042 transitions. [2019-12-07 17:42:38,114 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2019-12-07 17:42:38,114 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 67 [2019-12-07 17:42:38,114 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:42:38,139 INFO L225 Difference]: With dead ends: 25013 [2019-12-07 17:42:38,139 INFO L226 Difference]: Without dead ends: 23745 [2019-12-07 17:42:38,140 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 461 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=358, Invalid=2092, Unknown=0, NotChecked=0, Total=2450 [2019-12-07 17:42:38,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23745 states. [2019-12-07 17:42:38,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23745 to 22964. [2019-12-07 17:42:38,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22964 states. [2019-12-07 17:42:38,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22964 states to 22964 states and 70372 transitions. [2019-12-07 17:42:38,459 INFO L78 Accepts]: Start accepts. Automaton has 22964 states and 70372 transitions. Word has length 67 [2019-12-07 17:42:38,459 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:42:38,459 INFO L462 AbstractCegarLoop]: Abstraction has 22964 states and 70372 transitions. [2019-12-07 17:42:38,460 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-12-07 17:42:38,460 INFO L276 IsEmpty]: Start isEmpty. Operand 22964 states and 70372 transitions. [2019-12-07 17:42:38,479 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:42:38,479 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:42:38,479 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:42:38,479 INFO L410 AbstractCegarLoop]: === Iteration 34 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:42:38,480 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:42:38,480 INFO L82 PathProgramCache]: Analyzing trace with hash -1738993652, now seen corresponding path program 18 times [2019-12-07 17:42:38,480 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:42:38,480 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [129268892] [2019-12-07 17:42:38,480 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:42:38,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:42:38,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:42:38,920 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [129268892] [2019-12-07 17:42:38,920 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:42:38,920 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2019-12-07 17:42:38,921 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1537809416] [2019-12-07 17:42:38,921 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 17:42:38,921 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:42:38,921 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 17:42:38,921 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=291, Unknown=0, NotChecked=0, Total=342 [2019-12-07 17:42:38,921 INFO L87 Difference]: Start difference. First operand 22964 states and 70372 transitions. Second operand 19 states. [2019-12-07 17:42:42,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:42:42,182 INFO L93 Difference]: Finished difference Result 30563 states and 93625 transitions. [2019-12-07 17:42:42,182 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2019-12-07 17:42:42,182 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 67 [2019-12-07 17:42:42,182 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:42:42,213 INFO L225 Difference]: With dead ends: 30563 [2019-12-07 17:42:42,213 INFO L226 Difference]: Without dead ends: 29167 [2019-12-07 17:42:42,214 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 630 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=369, Invalid=2387, Unknown=0, NotChecked=0, Total=2756 [2019-12-07 17:42:42,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29167 states. [2019-12-07 17:42:42,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29167 to 22774. [2019-12-07 17:42:42,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22774 states. [2019-12-07 17:42:42,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22774 states to 22774 states and 69840 transitions. [2019-12-07 17:42:42,578 INFO L78 Accepts]: Start accepts. Automaton has 22774 states and 69840 transitions. Word has length 67 [2019-12-07 17:42:42,578 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:42:42,578 INFO L462 AbstractCegarLoop]: Abstraction has 22774 states and 69840 transitions. [2019-12-07 17:42:42,578 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 17:42:42,579 INFO L276 IsEmpty]: Start isEmpty. Operand 22774 states and 69840 transitions. [2019-12-07 17:42:42,599 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:42:42,599 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:42:42,599 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:42:42,600 INFO L410 AbstractCegarLoop]: === Iteration 35 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:42:42,600 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:42:42,600 INFO L82 PathProgramCache]: Analyzing trace with hash -259023592, now seen corresponding path program 19 times [2019-12-07 17:42:42,600 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:42:42,600 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [232816282] [2019-12-07 17:42:42,600 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:42:42,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:42:42,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:42:42,861 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [232816282] [2019-12-07 17:42:42,861 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:42:42,861 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 17:42:42,861 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1059587756] [2019-12-07 17:42:42,861 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 17:42:42,861 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:42:42,862 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 17:42:42,862 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=229, Unknown=0, NotChecked=0, Total=272 [2019-12-07 17:42:42,862 INFO L87 Difference]: Start difference. First operand 22774 states and 69840 transitions. Second operand 17 states. [2019-12-07 17:42:45,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:42:45,271 INFO L93 Difference]: Finished difference Result 24549 states and 74593 transitions. [2019-12-07 17:42:45,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2019-12-07 17:42:45,272 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 67 [2019-12-07 17:42:45,272 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:42:45,296 INFO L225 Difference]: With dead ends: 24549 [2019-12-07 17:42:45,296 INFO L226 Difference]: Without dead ends: 23526 [2019-12-07 17:42:45,297 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 257 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=213, Invalid=1193, Unknown=0, NotChecked=0, Total=1406 [2019-12-07 17:42:45,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23526 states. [2019-12-07 17:42:45,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23526 to 22749. [2019-12-07 17:42:45,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22749 states. [2019-12-07 17:42:45,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22749 states to 22749 states and 69761 transitions. [2019-12-07 17:42:45,620 INFO L78 Accepts]: Start accepts. Automaton has 22749 states and 69761 transitions. Word has length 67 [2019-12-07 17:42:45,620 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:42:45,620 INFO L462 AbstractCegarLoop]: Abstraction has 22749 states and 69761 transitions. [2019-12-07 17:42:45,620 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 17:42:45,621 INFO L276 IsEmpty]: Start isEmpty. Operand 22749 states and 69761 transitions. [2019-12-07 17:42:45,641 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:42:45,641 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:42:45,641 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:42:45,642 INFO L410 AbstractCegarLoop]: === Iteration 36 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:42:45,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:42:45,642 INFO L82 PathProgramCache]: Analyzing trace with hash 1651619638, now seen corresponding path program 20 times [2019-12-07 17:42:45,642 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:42:45,642 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1804058384] [2019-12-07 17:42:45,642 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:42:45,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:42:45,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:42:45,747 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1804058384] [2019-12-07 17:42:45,747 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:42:45,747 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 17:42:45,747 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1532040832] [2019-12-07 17:42:45,747 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 17:42:45,747 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:42:45,747 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 17:42:45,747 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2019-12-07 17:42:45,747 INFO L87 Difference]: Start difference. First operand 22749 states and 69761 transitions. Second operand 12 states. [2019-12-07 17:42:47,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:42:47,059 INFO L93 Difference]: Finished difference Result 30961 states and 93415 transitions. [2019-12-07 17:42:47,059 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-12-07 17:42:47,059 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 67 [2019-12-07 17:42:47,059 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:42:47,092 INFO L225 Difference]: With dead ends: 30961 [2019-12-07 17:42:47,092 INFO L226 Difference]: Without dead ends: 28644 [2019-12-07 17:42:47,093 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 206 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=196, Invalid=926, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 17:42:47,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28644 states. [2019-12-07 17:42:47,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28644 to 22248. [2019-12-07 17:42:47,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22248 states. [2019-12-07 17:42:47,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22248 states to 22248 states and 68393 transitions. [2019-12-07 17:42:47,474 INFO L78 Accepts]: Start accepts. Automaton has 22248 states and 68393 transitions. Word has length 67 [2019-12-07 17:42:47,474 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:42:47,474 INFO L462 AbstractCegarLoop]: Abstraction has 22248 states and 68393 transitions. [2019-12-07 17:42:47,474 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 17:42:47,474 INFO L276 IsEmpty]: Start isEmpty. Operand 22248 states and 68393 transitions. [2019-12-07 17:42:47,494 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:42:47,494 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:42:47,494 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:42:47,494 INFO L410 AbstractCegarLoop]: === Iteration 37 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:42:47,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:42:47,495 INFO L82 PathProgramCache]: Analyzing trace with hash -1867129146, now seen corresponding path program 21 times [2019-12-07 17:42:47,495 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:42:47,495 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [596976883] [2019-12-07 17:42:47,495 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:42:47,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:42:47,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:42:47,552 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [596976883] [2019-12-07 17:42:47,552 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:42:47,553 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:42:47,553 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1129836445] [2019-12-07 17:42:47,553 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:42:47,553 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:42:47,553 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:42:47,553 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:42:47,553 INFO L87 Difference]: Start difference. First operand 22248 states and 68393 transitions. Second operand 6 states. [2019-12-07 17:42:47,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:42:47,835 INFO L93 Difference]: Finished difference Result 49336 states and 150713 transitions. [2019-12-07 17:42:47,835 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 17:42:47,835 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 67 [2019-12-07 17:42:47,835 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:42:47,881 INFO L225 Difference]: With dead ends: 49336 [2019-12-07 17:42:47,881 INFO L226 Difference]: Without dead ends: 39666 [2019-12-07 17:42:47,881 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-12-07 17:42:47,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39666 states. [2019-12-07 17:42:48,275 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39666 to 22393. [2019-12-07 17:42:48,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22393 states. [2019-12-07 17:42:48,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22393 states to 22393 states and 68561 transitions. [2019-12-07 17:42:48,311 INFO L78 Accepts]: Start accepts. Automaton has 22393 states and 68561 transitions. Word has length 67 [2019-12-07 17:42:48,311 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:42:48,311 INFO L462 AbstractCegarLoop]: Abstraction has 22393 states and 68561 transitions. [2019-12-07 17:42:48,311 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:42:48,311 INFO L276 IsEmpty]: Start isEmpty. Operand 22393 states and 68561 transitions. [2019-12-07 17:42:48,329 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:42:48,329 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:42:48,330 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:42:48,330 INFO L410 AbstractCegarLoop]: === Iteration 38 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:42:48,330 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:42:48,330 INFO L82 PathProgramCache]: Analyzing trace with hash -1154306208, now seen corresponding path program 22 times [2019-12-07 17:42:48,330 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:42:48,330 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1752804140] [2019-12-07 17:42:48,330 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:42:48,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:42:48,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:42:48,397 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:42:48,397 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 17:42:48,400 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [895] [895] ULTIMATE.startENTRY-->L822: Formula: (let ((.cse0 (store |v_#valid_62| 0 0))) (and (= 0 v_~z$flush_delayed~0_27) (= 0 v_~x~0_129) (= 0 v_~__unbuffered_p1_EAX~0_44) (= 0 |v_ULTIMATE.start_main_~#t1579~0.offset_17|) (= v_~weak$$choice2~0_125 0) (= v_~z$read_delayed_var~0.offset_6 0) (= v_~z$r_buff0_thd1~0_274 0) (= |v_#NULL.offset_7| 0) (= v_~z$mem_tmp~0_16 0) (= v_~z$r_buff1_thd0~0_203 0) (= v_~main$tmp_guard1~0_48 0) (= |v_#valid_60| (store .cse0 |v_ULTIMATE.start_main_~#t1579~0.base_23| 1)) (= 0 v_~z$r_buff0_thd3~0_416) (= v_~z$w_buff1_used~0_618 0) (< 0 |v_#StackHeapBarrier_17|) (= 0 v_~__unbuffered_p2_EAX~0_39) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1579~0.base_23| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1579~0.base_23|) |v_ULTIMATE.start_main_~#t1579~0.offset_17| 0)) |v_#memory_int_17|) (= v_~z$r_buff0_thd0~0_208 0) (= v_~z$read_delayed_var~0.base_6 0) (= v_~z$w_buff1~0_350 0) (= v_~z$w_buff0_used~0_900 0) (= 0 v_~__unbuffered_p0_EAX~0_137) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1579~0.base_23|)) (= v_~z$read_delayed~0_7 0) (= v_~z$r_buff1_thd2~0_170 0) (= 0 |v_#NULL.base_7|) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t1579~0.base_23|) (= 0 v_~z$r_buff1_thd3~0_300) (= v_~z$r_buff1_thd1~0_166 0) (= (store |v_#length_22| |v_ULTIMATE.start_main_~#t1579~0.base_23| 4) |v_#length_21|) (= v_~z$w_buff0~0_454 0) (= 0 v_~weak$$choice0~0_13) (= v_~z~0_160 0) (= v_~main$tmp_guard0~0_24 0) (= 0 v_~__unbuffered_cnt~0_97) (= v_~z$r_buff0_thd2~0_191 0) (= v_~y~0_31 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_62|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_170, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_29|, #NULL.offset=|v_#NULL.offset_7|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_69|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_175|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_81|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_208, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_137, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_44, #length=|v_#length_21|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_39, ULTIMATE.start_main_~#t1580~0.base=|v_ULTIMATE.start_main_~#t1580~0.base_19|, ~z$mem_tmp~0=v_~z$mem_tmp~0_16, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_7|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_618, ~z$flush_delayed~0=v_~z$flush_delayed~0_27, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_166, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_6, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_416, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_97, ~x~0=v_~x~0_129, ULTIMATE.start_main_~#t1580~0.offset=|v_ULTIMATE.start_main_~#t1580~0.offset_12|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ~z$w_buff1~0=v_~z$w_buff1~0_350, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_48, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_37|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_6, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_52|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_203, ULTIMATE.start_main_~#t1579~0.base=|v_ULTIMATE.start_main_~#t1579~0.base_23|, ~y~0=v_~y~0_31, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_191, ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_21|, ULTIMATE.start_main_~#t1581~0.base=|v_ULTIMATE.start_main_~#t1581~0.base_17|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_900, ~z$w_buff0~0=v_~z$w_buff0~0_454, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_8|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_300, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, #NULL.base=|v_#NULL.base_7|, ULTIMATE.start_main_~#t1581~0.offset=|v_ULTIMATE.start_main_~#t1581~0.offset_14|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_22|, #valid=|v_#valid_60|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_~#t1579~0.offset=|v_ULTIMATE.start_main_~#t1579~0.offset_17|, ~z~0=v_~z~0_160, ~weak$$choice2~0=v_~weak$$choice2~0_125, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_274} AuxVars[] AssignedVars[~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ~__unbuffered_p0_EAX~0, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t1580~0.base, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet45, ~z$w_buff1_used~0, ~z$flush_delayed~0, ~weak$$choice0~0, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_~#t1580~0.offset, ~z$read_delayed~0, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ULTIMATE.start_main_~#t1579~0.base, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet46, ULTIMATE.start_main_~#t1581~0.base, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~nondet44, ~z$r_buff1_thd3~0, ~main$tmp_guard0~0, #NULL.base, ULTIMATE.start_main_~#t1581~0.offset, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_~#t1579~0.offset, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 17:42:48,400 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [874] [874] L822-1-->L824: Formula: (and (= 0 |v_ULTIMATE.start_main_~#t1580~0.offset_9|) (not (= |v_ULTIMATE.start_main_~#t1580~0.base_11| 0)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1580~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1580~0.base_11|) |v_ULTIMATE.start_main_~#t1580~0.offset_9| 1)) |v_#memory_int_13|) (= |v_#valid_38| (store |v_#valid_39| |v_ULTIMATE.start_main_~#t1580~0.base_11| 1)) (= 0 (select |v_#valid_39| |v_ULTIMATE.start_main_~#t1580~0.base_11|)) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1580~0.base_11| 4)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1580~0.base_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_~#t1580~0.offset=|v_ULTIMATE.start_main_~#t1580~0.offset_9|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_6|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_13|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1580~0.base=|v_ULTIMATE.start_main_~#t1580~0.base_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1580~0.offset, ULTIMATE.start_main_#t~nondet44, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1580~0.base] because there is no mapped edge [2019-12-07 17:42:48,400 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L4-->L746: Formula: (and (= v_~z$r_buff0_thd2~0_29 v_~z$r_buff1_thd2~0_21) (= v_~__unbuffered_p0_EAX~0_8 v_~x~0_8) (= v_~z$r_buff0_thd0~0_28 v_~z$r_buff1_thd0~0_16) (= v_~z$r_buff0_thd1~0_26 1) (not (= v_P0Thread1of1ForFork1___VERIFIER_assert_~expression_18 0)) (= v_~z$r_buff0_thd1~0_27 v_~z$r_buff1_thd1~0_15) (= v_~z$r_buff0_thd3~0_67 v_~z$r_buff1_thd3~0_43)) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_28, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_67, P0Thread1of1ForFork1___VERIFIER_assert_~expression=v_P0Thread1of1ForFork1___VERIFIER_assert_~expression_18, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_27, ~x~0=v_~x~0_8, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_29} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_8, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_28, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_43, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_16, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_21, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_15, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_67, P0Thread1of1ForFork1___VERIFIER_assert_~expression=v_P0Thread1of1ForFork1___VERIFIER_assert_~expression_18, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_26, ~x~0=v_~x~0_8, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_29} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, ~z$r_buff1_thd3~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 17:42:48,402 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [833] [833] L766-2-->L766-4: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In386598775 256) 0)) (.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In386598775 256)))) (or (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In386598775 |P1Thread1of1ForFork2_#t~ite9_Out386598775|)) (and (= ~z~0_In386598775 |P1Thread1of1ForFork2_#t~ite9_Out386598775|) (or .cse1 .cse0)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In386598775, ~z$w_buff1_used~0=~z$w_buff1_used~0_In386598775, ~z$w_buff1~0=~z$w_buff1~0_In386598775, ~z~0=~z~0_In386598775} OutVars{P1Thread1of1ForFork2_#t~ite9=|P1Thread1of1ForFork2_#t~ite9_Out386598775|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In386598775, ~z$w_buff1_used~0=~z$w_buff1_used~0_In386598775, ~z$w_buff1~0=~z$w_buff1~0_In386598775, ~z~0=~z~0_In386598775} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite9] because there is no mapped edge [2019-12-07 17:42:48,402 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [752] [752] L766-4-->L767: Formula: (= v_~z~0_16 |v_P1Thread1of1ForFork2_#t~ite9_6|) InVars {P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_6|} OutVars{P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_5|, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_5|, ~z~0=v_~z~0_16} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite10, ~z~0] because there is no mapped edge [2019-12-07 17:42:48,402 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [871] [871] L824-1-->L826: Formula: (and (= (select |v_#valid_37| |v_ULTIMATE.start_main_~#t1581~0.base_13|) 0) (= (store |v_#valid_37| |v_ULTIMATE.start_main_~#t1581~0.base_13| 1) |v_#valid_36|) (not (= 0 |v_ULTIMATE.start_main_~#t1581~0.base_13|)) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1581~0.base_13| 4)) (= |v_ULTIMATE.start_main_~#t1581~0.offset_11| 0) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t1581~0.base_13|) (= |v_#memory_int_11| (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t1581~0.base_13| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t1581~0.base_13|) |v_ULTIMATE.start_main_~#t1581~0.offset_11| 2)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_37|, #memory_int=|v_#memory_int_12|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t1581~0.base=|v_ULTIMATE.start_main_~#t1581~0.base_13|, ULTIMATE.start_main_~#t1581~0.offset=|v_ULTIMATE.start_main_~#t1581~0.offset_11|, #valid=|v_#valid_36|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_5|, #memory_int=|v_#memory_int_11|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1581~0.base, ULTIMATE.start_main_~#t1581~0.offset, #valid, ULTIMATE.start_main_#t~nondet45, #memory_int, #length] because there is no mapped edge [2019-12-07 17:42:48,402 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L767-->L767-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-16581287 256))) (.cse1 (= (mod ~z$r_buff0_thd2~0_In-16581287 256) 0))) (or (and (not .cse0) (= 0 |P1Thread1of1ForFork2_#t~ite11_Out-16581287|) (not .cse1)) (and (= ~z$w_buff0_used~0_In-16581287 |P1Thread1of1ForFork2_#t~ite11_Out-16581287|) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-16581287, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-16581287} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-16581287, P1Thread1of1ForFork2_#t~ite11=|P1Thread1of1ForFork2_#t~ite11_Out-16581287|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-16581287} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-12-07 17:42:48,402 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] L768-->L768-2: Formula: (let ((.cse2 (= 0 (mod ~z$w_buff0_used~0_In-1592832274 256))) (.cse3 (= 0 (mod ~z$r_buff0_thd2~0_In-1592832274 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In-1592832274 256) 0)) (.cse1 (= 0 (mod ~z$r_buff1_thd2~0_In-1592832274 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork2_#t~ite12_Out-1592832274| 0)) (and (= |P1Thread1of1ForFork2_#t~ite12_Out-1592832274| ~z$w_buff1_used~0_In-1592832274) (or .cse2 .cse3) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1592832274, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1592832274, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1592832274, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1592832274} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1592832274, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1592832274, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1592832274, P1Thread1of1ForFork2_#t~ite12=|P1Thread1of1ForFork2_#t~ite12_Out-1592832274|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1592832274} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite12] because there is no mapped edge [2019-12-07 17:42:48,404 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [842] [842] L769-->L769-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In2005253206 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In2005253206 256)))) (or (and (not .cse0) (= |P1Thread1of1ForFork2_#t~ite13_Out2005253206| 0) (not .cse1)) (and (or .cse1 .cse0) (= ~z$r_buff0_thd2~0_In2005253206 |P1Thread1of1ForFork2_#t~ite13_Out2005253206|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In2005253206, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In2005253206} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In2005253206, P1Thread1of1ForFork2_#t~ite13=|P1Thread1of1ForFork2_#t~ite13_Out2005253206|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In2005253206} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite13] because there is no mapped edge [2019-12-07 17:42:48,405 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [875] [875] L790-->L790-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In-647140950 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite26_Out-647140950| ~z$w_buff0_used~0_In-647140950) (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In-647140950 256) 0))) (or (and .cse0 (= 0 (mod ~z$w_buff1_used~0_In-647140950 256))) (and .cse0 (= (mod ~z$r_buff1_thd3~0_In-647140950 256) 0)) (= (mod ~z$w_buff0_used~0_In-647140950 256) 0))) .cse1 (= |P2Thread1of1ForFork0_#t~ite26_Out-647140950| |P2Thread1of1ForFork0_#t~ite27_Out-647140950|)) (and (= |P2Thread1of1ForFork0_#t~ite27_Out-647140950| ~z$w_buff0_used~0_In-647140950) (= |P2Thread1of1ForFork0_#t~ite26_In-647140950| |P2Thread1of1ForFork0_#t~ite26_Out-647140950|) (not .cse1)))) InVars {P2Thread1of1ForFork0_#t~ite26=|P2Thread1of1ForFork0_#t~ite26_In-647140950|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-647140950, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-647140950, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-647140950, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-647140950, ~weak$$choice2~0=~weak$$choice2~0_In-647140950} OutVars{P2Thread1of1ForFork0_#t~ite26=|P2Thread1of1ForFork0_#t~ite26_Out-647140950|, P2Thread1of1ForFork0_#t~ite27=|P2Thread1of1ForFork0_#t~ite27_Out-647140950|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-647140950, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-647140950, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-647140950, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-647140950, ~weak$$choice2~0=~weak$$choice2~0_In-647140950} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite26, P2Thread1of1ForFork0_#t~ite27] because there is no mapped edge [2019-12-07 17:42:48,406 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [810] [810] L792-->L793: Formula: (and (= v_~z$r_buff0_thd3~0_99 v_~z$r_buff0_thd3~0_100) (not (= 0 (mod v_~weak$$choice2~0_30 256)))) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_100, ~weak$$choice2~0=v_~weak$$choice2~0_30} OutVars{P2Thread1of1ForFork0_#t~ite33=|v_P2Thread1of1ForFork0_#t~ite33_7|, P2Thread1of1ForFork0_#t~ite32=|v_P2Thread1of1ForFork0_#t~ite32_9|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_99, P2Thread1of1ForFork0_#t~ite31=|v_P2Thread1of1ForFork0_#t~ite31_6|, ~weak$$choice2~0=v_~weak$$choice2~0_30} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite33, P2Thread1of1ForFork0_#t~ite32, ~z$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite31] because there is no mapped edge [2019-12-07 17:42:48,407 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [828] [828] L747-->L747-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In1041155812 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In1041155812 256)))) (or (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In1041155812 |P0Thread1of1ForFork1_#t~ite5_Out1041155812|)) (and (not .cse1) (= 0 |P0Thread1of1ForFork1_#t~ite5_Out1041155812|) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1041155812, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1041155812} OutVars{P0Thread1of1ForFork1_#t~ite5=|P0Thread1of1ForFork1_#t~ite5_Out1041155812|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1041155812, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1041155812} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite5] because there is no mapped edge [2019-12-07 17:42:48,408 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [814] [814] L795-->L799: Formula: (and (not (= (mod v_~z$flush_delayed~0_8 256) 0)) (= 0 v_~z$flush_delayed~0_7) (= v_~z~0_50 v_~z$mem_tmp~0_5)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_5, ~z$flush_delayed~0=v_~z$flush_delayed~0_8} OutVars{P2Thread1of1ForFork0_#t~ite37=|v_P2Thread1of1ForFork0_#t~ite37_5|, ~z$mem_tmp~0=v_~z$mem_tmp~0_5, ~z$flush_delayed~0=v_~z$flush_delayed~0_7, ~z~0=v_~z~0_50} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite37, ~z$flush_delayed~0, ~z~0] because there is no mapped edge [2019-12-07 17:42:48,408 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [827] [827] L799-2-->L799-5: Formula: (let ((.cse0 (= |P2Thread1of1ForFork0_#t~ite38_Out-535386570| |P2Thread1of1ForFork0_#t~ite39_Out-535386570|)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-535386570 256))) (.cse2 (= (mod ~z$r_buff1_thd3~0_In-535386570 256) 0))) (or (and .cse0 (not .cse1) (= |P2Thread1of1ForFork0_#t~ite38_Out-535386570| ~z$w_buff1~0_In-535386570) (not .cse2)) (and .cse0 (or .cse1 .cse2) (= |P2Thread1of1ForFork0_#t~ite38_Out-535386570| ~z~0_In-535386570)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-535386570, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-535386570, ~z$w_buff1~0=~z$w_buff1~0_In-535386570, ~z~0=~z~0_In-535386570} OutVars{P2Thread1of1ForFork0_#t~ite39=|P2Thread1of1ForFork0_#t~ite39_Out-535386570|, P2Thread1of1ForFork0_#t~ite38=|P2Thread1of1ForFork0_#t~ite38_Out-535386570|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-535386570, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-535386570, ~z$w_buff1~0=~z$w_buff1~0_In-535386570, ~z~0=~z~0_In-535386570} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite39, P2Thread1of1ForFork0_#t~ite38] because there is no mapped edge [2019-12-07 17:42:48,408 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L800-->L800-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-988525752 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-988525752 256) 0))) (or (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork0_#t~ite40_Out-988525752| 0)) (and (or .cse1 .cse0) (= ~z$w_buff0_used~0_In-988525752 |P2Thread1of1ForFork0_#t~ite40_Out-988525752|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-988525752, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-988525752} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-988525752, P2Thread1of1ForFork0_#t~ite40=|P2Thread1of1ForFork0_#t~ite40_Out-988525752|, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-988525752} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite40] because there is no mapped edge [2019-12-07 17:42:48,409 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [836] [836] L801-->L801-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In-254870859 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-254870859 256) 0)) (.cse3 (= (mod ~z$w_buff1_used~0_In-254870859 256) 0)) (.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In-254870859 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork0_#t~ite41_Out-254870859|)) (and (or .cse0 .cse1) (or .cse3 .cse2) (= ~z$w_buff1_used~0_In-254870859 |P2Thread1of1ForFork0_#t~ite41_Out-254870859|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-254870859, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-254870859, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-254870859, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-254870859} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-254870859, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-254870859, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-254870859, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-254870859, P2Thread1of1ForFork0_#t~ite41=|P2Thread1of1ForFork0_#t~ite41_Out-254870859|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite41] because there is no mapped edge [2019-12-07 17:42:48,409 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [824] [824] L802-->L802-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In1375098561 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In1375098561 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite42_Out1375098561| ~z$r_buff0_thd3~0_In1375098561) (or .cse0 .cse1)) (and (= |P2Thread1of1ForFork0_#t~ite42_Out1375098561| 0) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1375098561, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1375098561} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1375098561, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1375098561, P2Thread1of1ForFork0_#t~ite42=|P2Thread1of1ForFork0_#t~ite42_Out1375098561|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite42] because there is no mapped edge [2019-12-07 17:42:48,410 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [846] [846] L803-->L803-2: Formula: (let ((.cse2 (= (mod ~z$r_buff0_thd3~0_In-1101784427 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-1101784427 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-1101784427 256))) (.cse1 (= (mod ~z$r_buff1_thd3~0_In-1101784427 256) 0))) (or (and (or .cse0 .cse1) (= ~z$r_buff1_thd3~0_In-1101784427 |P2Thread1of1ForFork0_#t~ite43_Out-1101784427|) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1))) (= 0 |P2Thread1of1ForFork0_#t~ite43_Out-1101784427|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1101784427, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1101784427, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1101784427, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1101784427} OutVars{P2Thread1of1ForFork0_#t~ite43=|P2Thread1of1ForFork0_#t~ite43_Out-1101784427|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1101784427, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1101784427, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1101784427, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1101784427} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite43] because there is no mapped edge [2019-12-07 17:42:48,410 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [859] [859] L803-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= (+ v_~__unbuffered_cnt~0_49 1) v_~__unbuffered_cnt~0_48) (= v_~z$r_buff1_thd3~0_143 |v_P2Thread1of1ForFork0_#t~ite43_28|) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_28|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_49} OutVars{P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_27|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_143, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_48, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#res.base, P2Thread1of1ForFork0_#t~ite43, ~z$r_buff1_thd3~0, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 17:42:48,410 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [847] [847] L748-->L748-2: Formula: (let ((.cse1 (= (mod ~z$r_buff1_thd1~0_In760265765 256) 0)) (.cse0 (= (mod ~z$w_buff1_used~0_In760265765 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In760265765 256) 0)) (.cse2 (= 0 (mod ~z$r_buff0_thd1~0_In760265765 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork1_#t~ite6_Out760265765|)) (and (or .cse1 .cse0) (= ~z$w_buff1_used~0_In760265765 |P0Thread1of1ForFork1_#t~ite6_Out760265765|) (or .cse3 .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In760265765, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In760265765, ~z$w_buff1_used~0=~z$w_buff1_used~0_In760265765, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In760265765} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In760265765, P0Thread1of1ForFork1_#t~ite6=|P0Thread1of1ForFork1_#t~ite6_Out760265765|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In760265765, ~z$w_buff1_used~0=~z$w_buff1_used~0_In760265765, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In760265765} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite6] because there is no mapped edge [2019-12-07 17:42:48,410 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [845] [845] L749-->L750: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In1903474534 256) 0)) (.cse2 (= ~z$r_buff0_thd1~0_Out1903474534 ~z$r_buff0_thd1~0_In1903474534)) (.cse0 (= (mod ~z$r_buff0_thd1~0_In1903474534 256) 0))) (or (and (not .cse0) (= 0 ~z$r_buff0_thd1~0_Out1903474534) (not .cse1)) (and .cse2 .cse1) (and .cse2 .cse0))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1903474534, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1903474534} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1903474534, P0Thread1of1ForFork1_#t~ite7=|P0Thread1of1ForFork1_#t~ite7_Out1903474534|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out1903474534} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 17:42:48,410 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [840] [840] L750-->L750-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd1~0_In260823075 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In260823075 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In260823075 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd1~0_In260823075 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P0Thread1of1ForFork1_#t~ite8_Out260823075| ~z$r_buff1_thd1~0_In260823075)) (and (= 0 |P0Thread1of1ForFork1_#t~ite8_Out260823075|) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In260823075, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In260823075, ~z$w_buff1_used~0=~z$w_buff1_used~0_In260823075, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In260823075} OutVars{P0Thread1of1ForFork1_#t~ite8=|P0Thread1of1ForFork1_#t~ite8_Out260823075|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In260823075, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In260823075, ~z$w_buff1_used~0=~z$w_buff1_used~0_In260823075, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In260823075} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 17:42:48,410 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [866] [866] L750-2-->P0EXIT: Formula: (and (= v_~z$r_buff1_thd1~0_100 |v_P0Thread1of1ForFork1_#t~ite8_42|) (= 0 |v_P0Thread1of1ForFork1_#res.base_3|) (= 0 |v_P0Thread1of1ForFork1_#res.offset_3|) (= (+ v_~__unbuffered_cnt~0_67 1) v_~__unbuffered_cnt~0_66)) InVars {P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_42|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67} OutVars{P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_41|, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_100, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8, P0Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd1~0, P0Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 17:42:48,411 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [837] [837] L770-->L770-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff1_used~0_In1825162012 256))) (.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In1825162012 256))) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In1825162012 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd2~0_In1825162012 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P1Thread1of1ForFork2_#t~ite14_Out1825162012| ~z$r_buff1_thd2~0_In1825162012)) (and (= |P1Thread1of1ForFork2_#t~ite14_Out1825162012| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1825162012, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1825162012, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1825162012, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1825162012} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1825162012, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1825162012, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1825162012, P1Thread1of1ForFork2_#t~ite14=|P1Thread1of1ForFork2_#t~ite14_Out1825162012|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1825162012} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite14] because there is no mapped edge [2019-12-07 17:42:48,411 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [872] [872] L770-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= v_~z$r_buff1_thd2~0_120 |v_P1Thread1of1ForFork2_#t~ite14_32|) (= v_~__unbuffered_cnt~0_76 (+ v_~__unbuffered_cnt~0_77 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_77, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_32|} OutVars{P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_120, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_76, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_31|, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#t~ite14, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 17:42:48,411 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L826-1-->L832: Formula: (and (= v_~main$tmp_guard0~0_7 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_6|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet46, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 17:42:48,411 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] L832-2-->L832-5: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite48_Out439139011| |ULTIMATE.start_main_#t~ite47_Out439139011|)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In439139011 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In439139011 256) 0))) (or (and .cse0 (not .cse1) (= |ULTIMATE.start_main_#t~ite47_Out439139011| ~z$w_buff1~0_In439139011) (not .cse2)) (and .cse0 (or .cse1 .cse2) (= |ULTIMATE.start_main_#t~ite47_Out439139011| ~z~0_In439139011)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In439139011, ~z$w_buff1_used~0=~z$w_buff1_used~0_In439139011, ~z$w_buff1~0=~z$w_buff1~0_In439139011, ~z~0=~z~0_In439139011} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In439139011, ULTIMATE.start_main_#t~ite47=|ULTIMATE.start_main_#t~ite47_Out439139011|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In439139011, ~z$w_buff1~0=~z$w_buff1~0_In439139011, ULTIMATE.start_main_#t~ite48=|ULTIMATE.start_main_#t~ite48_Out439139011|, ~z~0=~z~0_In439139011} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 17:42:48,412 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [839] [839] L833-->L833-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-24977062 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In-24977062 256)))) (or (and (= ~z$w_buff0_used~0_In-24977062 |ULTIMATE.start_main_#t~ite49_Out-24977062|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite49_Out-24977062| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-24977062, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-24977062} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-24977062, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-24977062, ULTIMATE.start_main_#t~ite49=|ULTIMATE.start_main_#t~ite49_Out-24977062|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite49] because there is no mapped edge [2019-12-07 17:42:48,412 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [830] [830] L834-->L834-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In10111743 256))) (.cse1 (= (mod ~z$r_buff0_thd0~0_In10111743 256) 0)) (.cse3 (= 0 (mod ~z$r_buff1_thd0~0_In10111743 256))) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In10111743 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite50_Out10111743|)) (and (= ~z$w_buff1_used~0_In10111743 |ULTIMATE.start_main_#t~ite50_Out10111743|) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In10111743, ~z$w_buff0_used~0=~z$w_buff0_used~0_In10111743, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In10111743, ~z$w_buff1_used~0=~z$w_buff1_used~0_In10111743} OutVars{ULTIMATE.start_main_#t~ite50=|ULTIMATE.start_main_#t~ite50_Out10111743|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In10111743, ~z$w_buff0_used~0=~z$w_buff0_used~0_In10111743, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In10111743, ~z$w_buff1_used~0=~z$w_buff1_used~0_In10111743} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite50] because there is no mapped edge [2019-12-07 17:42:48,412 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [821] [821] L835-->L835-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-380531429 256) 0)) (.cse1 (= (mod ~z$r_buff0_thd0~0_In-380531429 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite51_Out-380531429|) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= ~z$r_buff0_thd0~0_In-380531429 |ULTIMATE.start_main_#t~ite51_Out-380531429|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-380531429, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-380531429} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-380531429, ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_Out-380531429|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-380531429} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite51] because there is no mapped edge [2019-12-07 17:42:48,413 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [834] [834] L836-->L836-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff1_thd0~0_In-1799265621 256))) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-1799265621 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In-1799265621 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-1799265621 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite52_Out-1799265621|)) (and (or .cse3 .cse2) (= ~z$r_buff1_thd0~0_In-1799265621 |ULTIMATE.start_main_#t~ite52_Out-1799265621|) (or .cse1 .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1799265621, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1799265621, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1799265621, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1799265621} OutVars{ULTIMATE.start_main_#t~ite52=|ULTIMATE.start_main_#t~ite52_Out-1799265621|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1799265621, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1799265621, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1799265621, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1799265621} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52] because there is no mapped edge [2019-12-07 17:42:48,413 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [879] [879] L836-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_~main$tmp_guard1~0_20 (ite (= 0 (ite (not (and (= 0 v_~__unbuffered_p1_EAX~0_25) (= 0 v_~__unbuffered_p0_EAX~0_99) (= 0 v_~__unbuffered_p2_EAX~0_26))) 1 0)) 0 1)) (= v_ULTIMATE.start___VERIFIER_assert_~expression_19 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_13|) (= v_~z$r_buff1_thd0~0_143 |v_ULTIMATE.start_main_#t~ite52_43|) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_13| (mod v_~main$tmp_guard1~0_20 256)) (= v_ULTIMATE.start___VERIFIER_assert_~expression_19 0)) InVars {~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_99, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_43|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_25, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_26} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_99, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_42|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_19, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_25, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_143, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_20, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_26, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 17:42:48,465 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 05:42:48 BasicIcfg [2019-12-07 17:42:48,466 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 17:42:48,466 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 17:42:48,466 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 17:42:48,466 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 17:42:48,467 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:39:27" (3/4) ... [2019-12-07 17:42:48,468 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 17:42:48,469 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [895] [895] ULTIMATE.startENTRY-->L822: Formula: (let ((.cse0 (store |v_#valid_62| 0 0))) (and (= 0 v_~z$flush_delayed~0_27) (= 0 v_~x~0_129) (= 0 v_~__unbuffered_p1_EAX~0_44) (= 0 |v_ULTIMATE.start_main_~#t1579~0.offset_17|) (= v_~weak$$choice2~0_125 0) (= v_~z$read_delayed_var~0.offset_6 0) (= v_~z$r_buff0_thd1~0_274 0) (= |v_#NULL.offset_7| 0) (= v_~z$mem_tmp~0_16 0) (= v_~z$r_buff1_thd0~0_203 0) (= v_~main$tmp_guard1~0_48 0) (= |v_#valid_60| (store .cse0 |v_ULTIMATE.start_main_~#t1579~0.base_23| 1)) (= 0 v_~z$r_buff0_thd3~0_416) (= v_~z$w_buff1_used~0_618 0) (< 0 |v_#StackHeapBarrier_17|) (= 0 v_~__unbuffered_p2_EAX~0_39) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1579~0.base_23| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1579~0.base_23|) |v_ULTIMATE.start_main_~#t1579~0.offset_17| 0)) |v_#memory_int_17|) (= v_~z$r_buff0_thd0~0_208 0) (= v_~z$read_delayed_var~0.base_6 0) (= v_~z$w_buff1~0_350 0) (= v_~z$w_buff0_used~0_900 0) (= 0 v_~__unbuffered_p0_EAX~0_137) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1579~0.base_23|)) (= v_~z$read_delayed~0_7 0) (= v_~z$r_buff1_thd2~0_170 0) (= 0 |v_#NULL.base_7|) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t1579~0.base_23|) (= 0 v_~z$r_buff1_thd3~0_300) (= v_~z$r_buff1_thd1~0_166 0) (= (store |v_#length_22| |v_ULTIMATE.start_main_~#t1579~0.base_23| 4) |v_#length_21|) (= v_~z$w_buff0~0_454 0) (= 0 v_~weak$$choice0~0_13) (= v_~z~0_160 0) (= v_~main$tmp_guard0~0_24 0) (= 0 v_~__unbuffered_cnt~0_97) (= v_~z$r_buff0_thd2~0_191 0) (= v_~y~0_31 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_62|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_170, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_29|, #NULL.offset=|v_#NULL.offset_7|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_69|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_175|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_81|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_208, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_137, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_44, #length=|v_#length_21|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_39, ULTIMATE.start_main_~#t1580~0.base=|v_ULTIMATE.start_main_~#t1580~0.base_19|, ~z$mem_tmp~0=v_~z$mem_tmp~0_16, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_7|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_618, ~z$flush_delayed~0=v_~z$flush_delayed~0_27, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_166, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_6, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_416, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_97, ~x~0=v_~x~0_129, ULTIMATE.start_main_~#t1580~0.offset=|v_ULTIMATE.start_main_~#t1580~0.offset_12|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ~z$w_buff1~0=v_~z$w_buff1~0_350, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_48, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_37|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_6, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_52|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_203, ULTIMATE.start_main_~#t1579~0.base=|v_ULTIMATE.start_main_~#t1579~0.base_23|, ~y~0=v_~y~0_31, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_191, ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_21|, ULTIMATE.start_main_~#t1581~0.base=|v_ULTIMATE.start_main_~#t1581~0.base_17|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_900, ~z$w_buff0~0=v_~z$w_buff0~0_454, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_8|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_300, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, #NULL.base=|v_#NULL.base_7|, ULTIMATE.start_main_~#t1581~0.offset=|v_ULTIMATE.start_main_~#t1581~0.offset_14|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_22|, #valid=|v_#valid_60|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_~#t1579~0.offset=|v_ULTIMATE.start_main_~#t1579~0.offset_17|, ~z~0=v_~z~0_160, ~weak$$choice2~0=v_~weak$$choice2~0_125, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_274} AuxVars[] AssignedVars[~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ~__unbuffered_p0_EAX~0, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t1580~0.base, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet45, ~z$w_buff1_used~0, ~z$flush_delayed~0, ~weak$$choice0~0, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_~#t1580~0.offset, ~z$read_delayed~0, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ULTIMATE.start_main_~#t1579~0.base, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet46, ULTIMATE.start_main_~#t1581~0.base, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~nondet44, ~z$r_buff1_thd3~0, ~main$tmp_guard0~0, #NULL.base, ULTIMATE.start_main_~#t1581~0.offset, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_~#t1579~0.offset, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 17:42:48,469 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [874] [874] L822-1-->L824: Formula: (and (= 0 |v_ULTIMATE.start_main_~#t1580~0.offset_9|) (not (= |v_ULTIMATE.start_main_~#t1580~0.base_11| 0)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1580~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1580~0.base_11|) |v_ULTIMATE.start_main_~#t1580~0.offset_9| 1)) |v_#memory_int_13|) (= |v_#valid_38| (store |v_#valid_39| |v_ULTIMATE.start_main_~#t1580~0.base_11| 1)) (= 0 (select |v_#valid_39| |v_ULTIMATE.start_main_~#t1580~0.base_11|)) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1580~0.base_11| 4)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1580~0.base_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_~#t1580~0.offset=|v_ULTIMATE.start_main_~#t1580~0.offset_9|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_6|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_13|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1580~0.base=|v_ULTIMATE.start_main_~#t1580~0.base_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1580~0.offset, ULTIMATE.start_main_#t~nondet44, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1580~0.base] because there is no mapped edge [2019-12-07 17:42:48,469 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L4-->L746: Formula: (and (= v_~z$r_buff0_thd2~0_29 v_~z$r_buff1_thd2~0_21) (= v_~__unbuffered_p0_EAX~0_8 v_~x~0_8) (= v_~z$r_buff0_thd0~0_28 v_~z$r_buff1_thd0~0_16) (= v_~z$r_buff0_thd1~0_26 1) (not (= v_P0Thread1of1ForFork1___VERIFIER_assert_~expression_18 0)) (= v_~z$r_buff0_thd1~0_27 v_~z$r_buff1_thd1~0_15) (= v_~z$r_buff0_thd3~0_67 v_~z$r_buff1_thd3~0_43)) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_28, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_67, P0Thread1of1ForFork1___VERIFIER_assert_~expression=v_P0Thread1of1ForFork1___VERIFIER_assert_~expression_18, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_27, ~x~0=v_~x~0_8, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_29} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_8, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_28, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_43, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_16, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_21, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_15, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_67, P0Thread1of1ForFork1___VERIFIER_assert_~expression=v_P0Thread1of1ForFork1___VERIFIER_assert_~expression_18, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_26, ~x~0=v_~x~0_8, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_29} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, ~z$r_buff1_thd3~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 17:42:48,470 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [833] [833] L766-2-->L766-4: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In386598775 256) 0)) (.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In386598775 256)))) (or (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In386598775 |P1Thread1of1ForFork2_#t~ite9_Out386598775|)) (and (= ~z~0_In386598775 |P1Thread1of1ForFork2_#t~ite9_Out386598775|) (or .cse1 .cse0)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In386598775, ~z$w_buff1_used~0=~z$w_buff1_used~0_In386598775, ~z$w_buff1~0=~z$w_buff1~0_In386598775, ~z~0=~z~0_In386598775} OutVars{P1Thread1of1ForFork2_#t~ite9=|P1Thread1of1ForFork2_#t~ite9_Out386598775|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In386598775, ~z$w_buff1_used~0=~z$w_buff1_used~0_In386598775, ~z$w_buff1~0=~z$w_buff1~0_In386598775, ~z~0=~z~0_In386598775} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite9] because there is no mapped edge [2019-12-07 17:42:48,470 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [752] [752] L766-4-->L767: Formula: (= v_~z~0_16 |v_P1Thread1of1ForFork2_#t~ite9_6|) InVars {P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_6|} OutVars{P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_5|, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_5|, ~z~0=v_~z~0_16} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite10, ~z~0] because there is no mapped edge [2019-12-07 17:42:48,470 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [871] [871] L824-1-->L826: Formula: (and (= (select |v_#valid_37| |v_ULTIMATE.start_main_~#t1581~0.base_13|) 0) (= (store |v_#valid_37| |v_ULTIMATE.start_main_~#t1581~0.base_13| 1) |v_#valid_36|) (not (= 0 |v_ULTIMATE.start_main_~#t1581~0.base_13|)) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1581~0.base_13| 4)) (= |v_ULTIMATE.start_main_~#t1581~0.offset_11| 0) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t1581~0.base_13|) (= |v_#memory_int_11| (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t1581~0.base_13| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t1581~0.base_13|) |v_ULTIMATE.start_main_~#t1581~0.offset_11| 2)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_37|, #memory_int=|v_#memory_int_12|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t1581~0.base=|v_ULTIMATE.start_main_~#t1581~0.base_13|, ULTIMATE.start_main_~#t1581~0.offset=|v_ULTIMATE.start_main_~#t1581~0.offset_11|, #valid=|v_#valid_36|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_5|, #memory_int=|v_#memory_int_11|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1581~0.base, ULTIMATE.start_main_~#t1581~0.offset, #valid, ULTIMATE.start_main_#t~nondet45, #memory_int, #length] because there is no mapped edge [2019-12-07 17:42:48,470 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L767-->L767-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-16581287 256))) (.cse1 (= (mod ~z$r_buff0_thd2~0_In-16581287 256) 0))) (or (and (not .cse0) (= 0 |P1Thread1of1ForFork2_#t~ite11_Out-16581287|) (not .cse1)) (and (= ~z$w_buff0_used~0_In-16581287 |P1Thread1of1ForFork2_#t~ite11_Out-16581287|) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-16581287, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-16581287} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-16581287, P1Thread1of1ForFork2_#t~ite11=|P1Thread1of1ForFork2_#t~ite11_Out-16581287|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-16581287} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-12-07 17:42:48,471 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] L768-->L768-2: Formula: (let ((.cse2 (= 0 (mod ~z$w_buff0_used~0_In-1592832274 256))) (.cse3 (= 0 (mod ~z$r_buff0_thd2~0_In-1592832274 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In-1592832274 256) 0)) (.cse1 (= 0 (mod ~z$r_buff1_thd2~0_In-1592832274 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork2_#t~ite12_Out-1592832274| 0)) (and (= |P1Thread1of1ForFork2_#t~ite12_Out-1592832274| ~z$w_buff1_used~0_In-1592832274) (or .cse2 .cse3) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1592832274, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1592832274, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1592832274, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1592832274} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1592832274, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1592832274, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1592832274, P1Thread1of1ForFork2_#t~ite12=|P1Thread1of1ForFork2_#t~ite12_Out-1592832274|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1592832274} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite12] because there is no mapped edge [2019-12-07 17:42:48,473 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [842] [842] L769-->L769-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In2005253206 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In2005253206 256)))) (or (and (not .cse0) (= |P1Thread1of1ForFork2_#t~ite13_Out2005253206| 0) (not .cse1)) (and (or .cse1 .cse0) (= ~z$r_buff0_thd2~0_In2005253206 |P1Thread1of1ForFork2_#t~ite13_Out2005253206|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In2005253206, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In2005253206} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In2005253206, P1Thread1of1ForFork2_#t~ite13=|P1Thread1of1ForFork2_#t~ite13_Out2005253206|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In2005253206} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite13] because there is no mapped edge [2019-12-07 17:42:48,474 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [875] [875] L790-->L790-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In-647140950 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite26_Out-647140950| ~z$w_buff0_used~0_In-647140950) (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In-647140950 256) 0))) (or (and .cse0 (= 0 (mod ~z$w_buff1_used~0_In-647140950 256))) (and .cse0 (= (mod ~z$r_buff1_thd3~0_In-647140950 256) 0)) (= (mod ~z$w_buff0_used~0_In-647140950 256) 0))) .cse1 (= |P2Thread1of1ForFork0_#t~ite26_Out-647140950| |P2Thread1of1ForFork0_#t~ite27_Out-647140950|)) (and (= |P2Thread1of1ForFork0_#t~ite27_Out-647140950| ~z$w_buff0_used~0_In-647140950) (= |P2Thread1of1ForFork0_#t~ite26_In-647140950| |P2Thread1of1ForFork0_#t~ite26_Out-647140950|) (not .cse1)))) InVars {P2Thread1of1ForFork0_#t~ite26=|P2Thread1of1ForFork0_#t~ite26_In-647140950|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-647140950, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-647140950, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-647140950, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-647140950, ~weak$$choice2~0=~weak$$choice2~0_In-647140950} OutVars{P2Thread1of1ForFork0_#t~ite26=|P2Thread1of1ForFork0_#t~ite26_Out-647140950|, P2Thread1of1ForFork0_#t~ite27=|P2Thread1of1ForFork0_#t~ite27_Out-647140950|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-647140950, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-647140950, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-647140950, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-647140950, ~weak$$choice2~0=~weak$$choice2~0_In-647140950} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite26, P2Thread1of1ForFork0_#t~ite27] because there is no mapped edge [2019-12-07 17:42:48,475 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [810] [810] L792-->L793: Formula: (and (= v_~z$r_buff0_thd3~0_99 v_~z$r_buff0_thd3~0_100) (not (= 0 (mod v_~weak$$choice2~0_30 256)))) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_100, ~weak$$choice2~0=v_~weak$$choice2~0_30} OutVars{P2Thread1of1ForFork0_#t~ite33=|v_P2Thread1of1ForFork0_#t~ite33_7|, P2Thread1of1ForFork0_#t~ite32=|v_P2Thread1of1ForFork0_#t~ite32_9|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_99, P2Thread1of1ForFork0_#t~ite31=|v_P2Thread1of1ForFork0_#t~ite31_6|, ~weak$$choice2~0=v_~weak$$choice2~0_30} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite33, P2Thread1of1ForFork0_#t~ite32, ~z$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite31] because there is no mapped edge [2019-12-07 17:42:48,476 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [828] [828] L747-->L747-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In1041155812 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In1041155812 256)))) (or (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In1041155812 |P0Thread1of1ForFork1_#t~ite5_Out1041155812|)) (and (not .cse1) (= 0 |P0Thread1of1ForFork1_#t~ite5_Out1041155812|) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1041155812, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1041155812} OutVars{P0Thread1of1ForFork1_#t~ite5=|P0Thread1of1ForFork1_#t~ite5_Out1041155812|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1041155812, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1041155812} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite5] because there is no mapped edge [2019-12-07 17:42:48,476 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [814] [814] L795-->L799: Formula: (and (not (= (mod v_~z$flush_delayed~0_8 256) 0)) (= 0 v_~z$flush_delayed~0_7) (= v_~z~0_50 v_~z$mem_tmp~0_5)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_5, ~z$flush_delayed~0=v_~z$flush_delayed~0_8} OutVars{P2Thread1of1ForFork0_#t~ite37=|v_P2Thread1of1ForFork0_#t~ite37_5|, ~z$mem_tmp~0=v_~z$mem_tmp~0_5, ~z$flush_delayed~0=v_~z$flush_delayed~0_7, ~z~0=v_~z~0_50} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite37, ~z$flush_delayed~0, ~z~0] because there is no mapped edge [2019-12-07 17:42:48,476 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [827] [827] L799-2-->L799-5: Formula: (let ((.cse0 (= |P2Thread1of1ForFork0_#t~ite38_Out-535386570| |P2Thread1of1ForFork0_#t~ite39_Out-535386570|)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-535386570 256))) (.cse2 (= (mod ~z$r_buff1_thd3~0_In-535386570 256) 0))) (or (and .cse0 (not .cse1) (= |P2Thread1of1ForFork0_#t~ite38_Out-535386570| ~z$w_buff1~0_In-535386570) (not .cse2)) (and .cse0 (or .cse1 .cse2) (= |P2Thread1of1ForFork0_#t~ite38_Out-535386570| ~z~0_In-535386570)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-535386570, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-535386570, ~z$w_buff1~0=~z$w_buff1~0_In-535386570, ~z~0=~z~0_In-535386570} OutVars{P2Thread1of1ForFork0_#t~ite39=|P2Thread1of1ForFork0_#t~ite39_Out-535386570|, P2Thread1of1ForFork0_#t~ite38=|P2Thread1of1ForFork0_#t~ite38_Out-535386570|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-535386570, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-535386570, ~z$w_buff1~0=~z$w_buff1~0_In-535386570, ~z~0=~z~0_In-535386570} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite39, P2Thread1of1ForFork0_#t~ite38] because there is no mapped edge [2019-12-07 17:42:48,477 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L800-->L800-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-988525752 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-988525752 256) 0))) (or (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork0_#t~ite40_Out-988525752| 0)) (and (or .cse1 .cse0) (= ~z$w_buff0_used~0_In-988525752 |P2Thread1of1ForFork0_#t~ite40_Out-988525752|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-988525752, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-988525752} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-988525752, P2Thread1of1ForFork0_#t~ite40=|P2Thread1of1ForFork0_#t~ite40_Out-988525752|, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-988525752} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite40] because there is no mapped edge [2019-12-07 17:42:48,477 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [836] [836] L801-->L801-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In-254870859 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-254870859 256) 0)) (.cse3 (= (mod ~z$w_buff1_used~0_In-254870859 256) 0)) (.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In-254870859 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork0_#t~ite41_Out-254870859|)) (and (or .cse0 .cse1) (or .cse3 .cse2) (= ~z$w_buff1_used~0_In-254870859 |P2Thread1of1ForFork0_#t~ite41_Out-254870859|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-254870859, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-254870859, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-254870859, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-254870859} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-254870859, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-254870859, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-254870859, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-254870859, P2Thread1of1ForFork0_#t~ite41=|P2Thread1of1ForFork0_#t~ite41_Out-254870859|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite41] because there is no mapped edge [2019-12-07 17:42:48,477 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [824] [824] L802-->L802-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In1375098561 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In1375098561 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite42_Out1375098561| ~z$r_buff0_thd3~0_In1375098561) (or .cse0 .cse1)) (and (= |P2Thread1of1ForFork0_#t~ite42_Out1375098561| 0) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1375098561, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1375098561} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1375098561, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1375098561, P2Thread1of1ForFork0_#t~ite42=|P2Thread1of1ForFork0_#t~ite42_Out1375098561|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite42] because there is no mapped edge [2019-12-07 17:42:48,478 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [846] [846] L803-->L803-2: Formula: (let ((.cse2 (= (mod ~z$r_buff0_thd3~0_In-1101784427 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-1101784427 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-1101784427 256))) (.cse1 (= (mod ~z$r_buff1_thd3~0_In-1101784427 256) 0))) (or (and (or .cse0 .cse1) (= ~z$r_buff1_thd3~0_In-1101784427 |P2Thread1of1ForFork0_#t~ite43_Out-1101784427|) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1))) (= 0 |P2Thread1of1ForFork0_#t~ite43_Out-1101784427|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1101784427, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1101784427, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1101784427, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1101784427} OutVars{P2Thread1of1ForFork0_#t~ite43=|P2Thread1of1ForFork0_#t~ite43_Out-1101784427|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1101784427, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1101784427, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1101784427, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1101784427} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite43] because there is no mapped edge [2019-12-07 17:42:48,478 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [859] [859] L803-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= (+ v_~__unbuffered_cnt~0_49 1) v_~__unbuffered_cnt~0_48) (= v_~z$r_buff1_thd3~0_143 |v_P2Thread1of1ForFork0_#t~ite43_28|) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_28|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_49} OutVars{P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_27|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_143, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_48, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#res.base, P2Thread1of1ForFork0_#t~ite43, ~z$r_buff1_thd3~0, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 17:42:48,478 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [847] [847] L748-->L748-2: Formula: (let ((.cse1 (= (mod ~z$r_buff1_thd1~0_In760265765 256) 0)) (.cse0 (= (mod ~z$w_buff1_used~0_In760265765 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In760265765 256) 0)) (.cse2 (= 0 (mod ~z$r_buff0_thd1~0_In760265765 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork1_#t~ite6_Out760265765|)) (and (or .cse1 .cse0) (= ~z$w_buff1_used~0_In760265765 |P0Thread1of1ForFork1_#t~ite6_Out760265765|) (or .cse3 .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In760265765, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In760265765, ~z$w_buff1_used~0=~z$w_buff1_used~0_In760265765, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In760265765} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In760265765, P0Thread1of1ForFork1_#t~ite6=|P0Thread1of1ForFork1_#t~ite6_Out760265765|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In760265765, ~z$w_buff1_used~0=~z$w_buff1_used~0_In760265765, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In760265765} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite6] because there is no mapped edge [2019-12-07 17:42:48,478 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [845] [845] L749-->L750: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In1903474534 256) 0)) (.cse2 (= ~z$r_buff0_thd1~0_Out1903474534 ~z$r_buff0_thd1~0_In1903474534)) (.cse0 (= (mod ~z$r_buff0_thd1~0_In1903474534 256) 0))) (or (and (not .cse0) (= 0 ~z$r_buff0_thd1~0_Out1903474534) (not .cse1)) (and .cse2 .cse1) (and .cse2 .cse0))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1903474534, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1903474534} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1903474534, P0Thread1of1ForFork1_#t~ite7=|P0Thread1of1ForFork1_#t~ite7_Out1903474534|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out1903474534} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 17:42:48,478 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [840] [840] L750-->L750-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd1~0_In260823075 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In260823075 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In260823075 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd1~0_In260823075 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P0Thread1of1ForFork1_#t~ite8_Out260823075| ~z$r_buff1_thd1~0_In260823075)) (and (= 0 |P0Thread1of1ForFork1_#t~ite8_Out260823075|) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In260823075, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In260823075, ~z$w_buff1_used~0=~z$w_buff1_used~0_In260823075, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In260823075} OutVars{P0Thread1of1ForFork1_#t~ite8=|P0Thread1of1ForFork1_#t~ite8_Out260823075|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In260823075, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In260823075, ~z$w_buff1_used~0=~z$w_buff1_used~0_In260823075, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In260823075} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 17:42:48,478 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [866] [866] L750-2-->P0EXIT: Formula: (and (= v_~z$r_buff1_thd1~0_100 |v_P0Thread1of1ForFork1_#t~ite8_42|) (= 0 |v_P0Thread1of1ForFork1_#res.base_3|) (= 0 |v_P0Thread1of1ForFork1_#res.offset_3|) (= (+ v_~__unbuffered_cnt~0_67 1) v_~__unbuffered_cnt~0_66)) InVars {P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_42|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67} OutVars{P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_41|, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_100, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8, P0Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd1~0, P0Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 17:42:48,479 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [837] [837] L770-->L770-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff1_used~0_In1825162012 256))) (.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In1825162012 256))) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In1825162012 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd2~0_In1825162012 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P1Thread1of1ForFork2_#t~ite14_Out1825162012| ~z$r_buff1_thd2~0_In1825162012)) (and (= |P1Thread1of1ForFork2_#t~ite14_Out1825162012| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1825162012, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1825162012, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1825162012, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1825162012} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1825162012, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1825162012, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1825162012, P1Thread1of1ForFork2_#t~ite14=|P1Thread1of1ForFork2_#t~ite14_Out1825162012|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1825162012} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite14] because there is no mapped edge [2019-12-07 17:42:48,479 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [872] [872] L770-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= v_~z$r_buff1_thd2~0_120 |v_P1Thread1of1ForFork2_#t~ite14_32|) (= v_~__unbuffered_cnt~0_76 (+ v_~__unbuffered_cnt~0_77 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_77, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_32|} OutVars{P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_120, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_76, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_31|, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#t~ite14, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 17:42:48,479 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L826-1-->L832: Formula: (and (= v_~main$tmp_guard0~0_7 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_6|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet46, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 17:42:48,479 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] L832-2-->L832-5: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite48_Out439139011| |ULTIMATE.start_main_#t~ite47_Out439139011|)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In439139011 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In439139011 256) 0))) (or (and .cse0 (not .cse1) (= |ULTIMATE.start_main_#t~ite47_Out439139011| ~z$w_buff1~0_In439139011) (not .cse2)) (and .cse0 (or .cse1 .cse2) (= |ULTIMATE.start_main_#t~ite47_Out439139011| ~z~0_In439139011)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In439139011, ~z$w_buff1_used~0=~z$w_buff1_used~0_In439139011, ~z$w_buff1~0=~z$w_buff1~0_In439139011, ~z~0=~z~0_In439139011} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In439139011, ULTIMATE.start_main_#t~ite47=|ULTIMATE.start_main_#t~ite47_Out439139011|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In439139011, ~z$w_buff1~0=~z$w_buff1~0_In439139011, ULTIMATE.start_main_#t~ite48=|ULTIMATE.start_main_#t~ite48_Out439139011|, ~z~0=~z~0_In439139011} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 17:42:48,480 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [839] [839] L833-->L833-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-24977062 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In-24977062 256)))) (or (and (= ~z$w_buff0_used~0_In-24977062 |ULTIMATE.start_main_#t~ite49_Out-24977062|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite49_Out-24977062| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-24977062, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-24977062} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-24977062, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-24977062, ULTIMATE.start_main_#t~ite49=|ULTIMATE.start_main_#t~ite49_Out-24977062|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite49] because there is no mapped edge [2019-12-07 17:42:48,480 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [830] [830] L834-->L834-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In10111743 256))) (.cse1 (= (mod ~z$r_buff0_thd0~0_In10111743 256) 0)) (.cse3 (= 0 (mod ~z$r_buff1_thd0~0_In10111743 256))) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In10111743 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite50_Out10111743|)) (and (= ~z$w_buff1_used~0_In10111743 |ULTIMATE.start_main_#t~ite50_Out10111743|) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In10111743, ~z$w_buff0_used~0=~z$w_buff0_used~0_In10111743, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In10111743, ~z$w_buff1_used~0=~z$w_buff1_used~0_In10111743} OutVars{ULTIMATE.start_main_#t~ite50=|ULTIMATE.start_main_#t~ite50_Out10111743|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In10111743, ~z$w_buff0_used~0=~z$w_buff0_used~0_In10111743, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In10111743, ~z$w_buff1_used~0=~z$w_buff1_used~0_In10111743} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite50] because there is no mapped edge [2019-12-07 17:42:48,481 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [821] [821] L835-->L835-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-380531429 256) 0)) (.cse1 (= (mod ~z$r_buff0_thd0~0_In-380531429 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite51_Out-380531429|) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= ~z$r_buff0_thd0~0_In-380531429 |ULTIMATE.start_main_#t~ite51_Out-380531429|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-380531429, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-380531429} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-380531429, ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_Out-380531429|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-380531429} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite51] because there is no mapped edge [2019-12-07 17:42:48,481 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [834] [834] L836-->L836-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff1_thd0~0_In-1799265621 256))) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-1799265621 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In-1799265621 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-1799265621 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite52_Out-1799265621|)) (and (or .cse3 .cse2) (= ~z$r_buff1_thd0~0_In-1799265621 |ULTIMATE.start_main_#t~ite52_Out-1799265621|) (or .cse1 .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1799265621, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1799265621, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1799265621, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1799265621} OutVars{ULTIMATE.start_main_#t~ite52=|ULTIMATE.start_main_#t~ite52_Out-1799265621|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1799265621, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1799265621, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1799265621, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1799265621} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52] because there is no mapped edge [2019-12-07 17:42:48,481 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [879] [879] L836-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_~main$tmp_guard1~0_20 (ite (= 0 (ite (not (and (= 0 v_~__unbuffered_p1_EAX~0_25) (= 0 v_~__unbuffered_p0_EAX~0_99) (= 0 v_~__unbuffered_p2_EAX~0_26))) 1 0)) 0 1)) (= v_ULTIMATE.start___VERIFIER_assert_~expression_19 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_13|) (= v_~z$r_buff1_thd0~0_143 |v_ULTIMATE.start_main_#t~ite52_43|) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_13| (mod v_~main$tmp_guard1~0_20 256)) (= v_ULTIMATE.start___VERIFIER_assert_~expression_19 0)) InVars {~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_99, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_43|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_25, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_26} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_99, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_42|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_19, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_25, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_143, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_20, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_26, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 17:42:48,536 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_a7c3c4b4-8785-433e-bdba-6b96778eab82/bin/uautomizer/witness.graphml [2019-12-07 17:42:48,537 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 17:42:48,538 INFO L168 Benchmark]: Toolchain (without parser) took 202116.38 ms. Allocated memory was 1.0 GB in the beginning and 7.4 GB in the end (delta: 6.3 GB). Free memory was 944.7 MB in the beginning and 3.5 GB in the end (delta: -2.5 GB). Peak memory consumption was 3.8 GB. Max. memory is 11.5 GB. [2019-12-07 17:42:48,538 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 964.0 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 17:42:48,538 INFO L168 Benchmark]: CACSL2BoogieTranslator took 390.18 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 73.9 MB). Free memory was 944.7 MB in the beginning and 1.0 GB in the end (delta: -99.6 MB). Peak memory consumption was 19.5 MB. Max. memory is 11.5 GB. [2019-12-07 17:42:48,538 INFO L168 Benchmark]: Boogie Procedure Inliner took 36.12 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 17:42:48,539 INFO L168 Benchmark]: Boogie Preprocessor took 26.03 ms. Allocated memory is still 1.1 GB. Free memory is still 1.0 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 17:42:48,539 INFO L168 Benchmark]: RCFGBuilder took 397.95 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 983.7 MB in the end (delta: 55.2 MB). Peak memory consumption was 55.2 MB. Max. memory is 11.5 GB. [2019-12-07 17:42:48,539 INFO L168 Benchmark]: TraceAbstraction took 201192.26 ms. Allocated memory was 1.1 GB in the beginning and 7.4 GB in the end (delta: 6.3 GB). Free memory was 978.4 MB in the beginning and 3.5 GB in the end (delta: -2.5 GB). Peak memory consumption was 3.7 GB. Max. memory is 11.5 GB. [2019-12-07 17:42:48,539 INFO L168 Benchmark]: Witness Printer took 70.67 ms. Allocated memory is still 7.4 GB. Free memory was 3.5 GB in the beginning and 3.5 GB in the end (delta: 48.0 MB). Peak memory consumption was 48.0 MB. Max. memory is 11.5 GB. [2019-12-07 17:42:48,541 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 964.0 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 390.18 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 73.9 MB). Free memory was 944.7 MB in the beginning and 1.0 GB in the end (delta: -99.6 MB). Peak memory consumption was 19.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 36.12 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.03 ms. Allocated memory is still 1.1 GB. Free memory is still 1.0 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 397.95 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 983.7 MB in the end (delta: 55.2 MB). Peak memory consumption was 55.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 201192.26 ms. Allocated memory was 1.1 GB in the beginning and 7.4 GB in the end (delta: 6.3 GB). Free memory was 978.4 MB in the beginning and 3.5 GB in the end (delta: -2.5 GB). Peak memory consumption was 3.7 GB. Max. memory is 11.5 GB. * Witness Printer took 70.67 ms. Allocated memory is still 7.4 GB. Free memory was 3.5 GB in the beginning and 3.5 GB in the end (delta: 48.0 MB). Peak memory consumption was 48.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.4s, 176 ProgramPointsBefore, 95 ProgramPointsAfterwards, 213 TransitionsBefore, 107 TransitionsAfterwards, 19004 CoEnabledTransitionPairs, 12 FixpointIterations, 33 TrivialSequentialCompositions, 55 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 33 ConcurrentYvCompositions, 29 ChoiceCompositions, 7276 VarBasedMoverChecksPositive, 432 VarBasedMoverChecksNegative, 272 SemBasedMoverChecksPositive, 254 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.1s, 0 MoverChecksTotal, 130045 CheckedPairsTotal, 121 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L822] FCALL, FORK 0 pthread_create(&t1579, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L731] 1 z$w_buff1 = z$w_buff0 [L732] 1 z$w_buff0 = 1 [L733] 1 z$w_buff1_used = z$w_buff0_used [L734] 1 z$w_buff0_used = (_Bool)1 [L746] EXPR 1 z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L824] FCALL, FORK 0 pthread_create(&t1580, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L760] 2 x = 1 [L763] 2 __unbuffered_p1_EAX = y VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L766] 2 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L767] 2 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used [L826] FCALL, FORK 0 pthread_create(&t1581, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used=0, z$w_buff1=0, z$w_buff1_used=0] [L780] 3 y = 1 [L783] 3 weak$$choice0 = __VERIFIER_nondet_bool() [L784] 3 weak$$choice2 = __VERIFIER_nondet_bool() [L785] 3 z$flush_delayed = weak$$choice2 [L786] 3 z$mem_tmp = z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=7, x=1, y=1, z=0, z$flush_delayed=7, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used=0, z$w_buff1=0, z$w_buff1_used=0] [L787] EXPR 3 !z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1) VAL [!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=7, x=1, y=1, z=0, z$flush_delayed=7, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used=0, z$w_buff1=0, z$w_buff1_used=0] [L787] 3 z = !z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1) [L788] EXPR 3 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=7, weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff0))=1, x=1, y=1, z=0, z$flush_delayed=7, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used=0, z$w_buff1=0, z$w_buff1_used=0] [L768] 2 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used [L788] 3 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff0)) [L789] EXPR 3 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff1 : z$w_buff1)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=7, weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff1 : z$w_buff1))=0, x=1, y=1, z=0, z$flush_delayed=7, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2=0, z$w_buff1=0, z$w_buff1_used=0] [L789] 3 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff1 : z$w_buff1)) [L790] 3 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used)) [L791] EXPR 3 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=7, weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=0, z$flush_delayed=7, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2=0, z$w_buff1=0, z$w_buff1_used=0] [L791] 3 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L793] EXPR 3 weak$$choice2 ? z$r_buff1_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff1_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=7, weak$$choice2 ? z$r_buff1_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff1_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=0, z$flush_delayed=7, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2=0, z$w_buff1=0, z$w_buff1_used=0] [L793] 3 z$r_buff1_thd3 = weak$$choice2 ? z$r_buff1_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff1_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L794] 3 __unbuffered_p2_EAX = z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=7, x=1, y=1, z=0, z$flush_delayed=7, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2=0, z$w_buff1=0, z$w_buff1_used=0] [L746] 1 z = z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) [L747] 1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used [L799] EXPR 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=7, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2=0, z$w_buff1=0, z$w_buff1_used=0] [L799] 3 z = z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) [L800] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L801] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L802] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L748] 1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used [L769] 2 z$r_buff0_thd2 = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 [L832] EXPR 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=7, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L832] 0 z = z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) [L833] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L834] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L835] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 167 locations, 2 error locations. Result: UNSAFE, OverallTime: 201.0s, OverallIterations: 38, TraceHistogramMax: 1, AutomataDifference: 89.7s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 10254 SDtfs, 14406 SDslu, 53660 SDs, 0 SdLazy, 80935 SolverSat, 1272 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 50.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1096 GetRequests, 65 SyntacticMatches, 44 SemanticMatches, 987 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11941 ImplicationChecksByTransitivity, 20.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=237826occurred in iteration=5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 78.6s AutomataMinimizationTime, 37 MinimizatonAttempts, 348880 StatesRemovedByMinimization, 35 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.7s SatisfiabilityAnalysisTime, 7.5s InterpolantComputationTime, 1919 NumberOfCodeBlocks, 1919 NumberOfCodeBlocksAsserted, 38 NumberOfCheckSat, 1815 ConstructedInterpolants, 0 QuantifiedInterpolants, 1025525 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 37 InterpolantComputations, 37 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...