./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe001_pso.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_ce97f955-5c2b-4ad2-9018-d826432996c1/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_ce97f955-5c2b-4ad2-9018-d826432996c1/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_ce97f955-5c2b-4ad2-9018-d826432996c1/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_ce97f955-5c2b-4ad2-9018-d826432996c1/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe001_pso.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_ce97f955-5c2b-4ad2-9018-d826432996c1/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_ce97f955-5c2b-4ad2-9018-d826432996c1/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0c49be60bd9a91389863f36bfa2611725e3a4208 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:51:31,599 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:51:31,600 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:51:31,608 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:51:31,608 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:51:31,609 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:51:31,610 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:51:31,611 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:51:31,613 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:51:31,613 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:51:31,614 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:51:31,615 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:51:31,615 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:51:31,616 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:51:31,616 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:51:31,617 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:51:31,618 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:51:31,618 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:51:31,620 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:51:31,621 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:51:31,623 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:51:31,623 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:51:31,624 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:51:31,624 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:51:31,626 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:51:31,626 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:51:31,627 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:51:31,627 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:51:31,627 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:51:31,628 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:51:31,628 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:51:31,629 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:51:31,629 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:51:31,629 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:51:31,630 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:51:31,630 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:51:31,631 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:51:31,631 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:51:31,631 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:51:31,631 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:51:31,632 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:51:31,632 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_ce97f955-5c2b-4ad2-9018-d826432996c1/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 18:51:31,641 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:51:31,641 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:51:31,642 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:51:31,642 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:51:31,642 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:51:31,642 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:51:31,643 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:51:31,643 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:51:31,643 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:51:31,643 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:51:31,643 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 18:51:31,643 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 18:51:31,643 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 18:51:31,643 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:51:31,643 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:51:31,643 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:51:31,644 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 18:51:31,644 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:51:31,644 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:51:31,644 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 18:51:31,644 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 18:51:31,644 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:51:31,644 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:51:31,644 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 18:51:31,645 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 18:51:31,645 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:51:31,645 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 18:51:31,645 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 18:51:31,645 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:51:31,645 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_ce97f955-5c2b-4ad2-9018-d826432996c1/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0c49be60bd9a91389863f36bfa2611725e3a4208 [2019-12-07 18:51:31,747 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:51:31,757 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:51:31,760 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:51:31,761 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:51:31,761 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:51:31,762 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_ce97f955-5c2b-4ad2-9018-d826432996c1/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe001_pso.opt.i [2019-12-07 18:51:31,805 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_ce97f955-5c2b-4ad2-9018-d826432996c1/bin/uautomizer/data/e2a41200d/2a7386955fb64563b3066f8a222840c4/FLAG8c4a97c7b [2019-12-07 18:51:32,269 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:51:32,270 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_ce97f955-5c2b-4ad2-9018-d826432996c1/sv-benchmarks/c/pthread-wmm/safe001_pso.opt.i [2019-12-07 18:51:32,279 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_ce97f955-5c2b-4ad2-9018-d826432996c1/bin/uautomizer/data/e2a41200d/2a7386955fb64563b3066f8a222840c4/FLAG8c4a97c7b [2019-12-07 18:51:32,597 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_ce97f955-5c2b-4ad2-9018-d826432996c1/bin/uautomizer/data/e2a41200d/2a7386955fb64563b3066f8a222840c4 [2019-12-07 18:51:32,603 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:51:32,606 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:51:32,608 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:51:32,609 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:51:32,616 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:51:32,618 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:51:32" (1/1) ... [2019-12-07 18:51:32,624 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@296938c1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:51:32, skipping insertion in model container [2019-12-07 18:51:32,625 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:51:32" (1/1) ... [2019-12-07 18:51:32,641 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:51:32,714 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:51:32,974 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:51:32,981 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:51:33,021 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:51:33,066 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:51:33,066 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:51:33 WrapperNode [2019-12-07 18:51:33,066 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:51:33,067 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:51:33,067 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:51:33,067 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:51:33,072 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:51:33" (1/1) ... [2019-12-07 18:51:33,085 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:51:33" (1/1) ... [2019-12-07 18:51:33,105 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:51:33,106 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:51:33,106 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:51:33,106 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:51:33,112 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:51:33" (1/1) ... [2019-12-07 18:51:33,112 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:51:33" (1/1) ... [2019-12-07 18:51:33,116 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:51:33" (1/1) ... [2019-12-07 18:51:33,116 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:51:33" (1/1) ... [2019-12-07 18:51:33,123 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:51:33" (1/1) ... [2019-12-07 18:51:33,126 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:51:33" (1/1) ... [2019-12-07 18:51:33,128 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:51:33" (1/1) ... [2019-12-07 18:51:33,132 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:51:33,132 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:51:33,132 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:51:33,132 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:51:33,133 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:51:33" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_ce97f955-5c2b-4ad2-9018-d826432996c1/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:51:33,172 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 18:51:33,172 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 18:51:33,173 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 18:51:33,173 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 18:51:33,173 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 18:51:33,173 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 18:51:33,173 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 18:51:33,173 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 18:51:33,173 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 18:51:33,173 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 18:51:33,173 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 18:51:33,173 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:51:33,173 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:51:33,175 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 18:51:33,548 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:51:33,548 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 18:51:33,549 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:51:33 BoogieIcfgContainer [2019-12-07 18:51:33,549 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:51:33,550 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 18:51:33,550 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 18:51:33,552 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 18:51:33,552 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 06:51:32" (1/3) ... [2019-12-07 18:51:33,553 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2a7c11b5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:51:33, skipping insertion in model container [2019-12-07 18:51:33,553 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:51:33" (2/3) ... [2019-12-07 18:51:33,553 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2a7c11b5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:51:33, skipping insertion in model container [2019-12-07 18:51:33,553 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:51:33" (3/3) ... [2019-12-07 18:51:33,555 INFO L109 eAbstractionObserver]: Analyzing ICFG safe001_pso.opt.i [2019-12-07 18:51:33,561 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 18:51:33,561 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 18:51:33,567 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 18:51:33,568 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 18:51:33,595 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,595 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,595 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,595 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,596 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,596 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,596 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,596 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,596 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,596 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,596 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,596 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,597 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,597 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,597 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,597 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,597 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,597 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,597 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,597 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,597 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,598 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,598 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,598 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,598 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,598 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,598 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,598 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,599 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,599 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,599 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,600 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,600 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,600 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,600 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,600 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,600 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,600 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,601 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,601 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,601 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,601 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,601 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,602 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,602 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,602 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,602 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,602 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,603 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,603 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,603 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,603 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,603 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,603 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,603 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,604 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,604 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,604 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,604 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,604 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,604 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,604 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,604 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,604 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,605 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,605 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,605 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,605 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,605 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,606 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,606 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,606 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,606 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,606 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,607 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,607 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,607 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,607 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,607 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,607 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,607 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,608 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,608 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,608 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,608 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,608 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,608 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,608 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,609 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,609 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,609 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,609 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,609 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,609 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:51:33,620 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 18:51:33,633 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 18:51:33,633 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 18:51:33,633 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 18:51:33,633 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:51:33,633 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:51:33,633 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 18:51:33,634 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:51:33,634 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 18:51:33,646 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 174 places, 211 transitions [2019-12-07 18:51:33,647 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 174 places, 211 transitions [2019-12-07 18:51:33,711 INFO L134 PetriNetUnfolder]: 47/208 cut-off events. [2019-12-07 18:51:33,712 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:51:33,721 INFO L76 FinitePrefix]: Finished finitePrefix Result has 218 conditions, 208 events. 47/208 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 572 event pairs. 9/168 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 18:51:33,735 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 174 places, 211 transitions [2019-12-07 18:51:33,771 INFO L134 PetriNetUnfolder]: 47/208 cut-off events. [2019-12-07 18:51:33,771 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:51:33,777 INFO L76 FinitePrefix]: Finished finitePrefix Result has 218 conditions, 208 events. 47/208 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 572 event pairs. 9/168 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 18:51:33,792 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 17074 [2019-12-07 18:51:33,792 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 18:51:36,632 WARN L192 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 85 [2019-12-07 18:51:36,727 INFO L206 etLargeBlockEncoding]: Checked pairs total: 78277 [2019-12-07 18:51:36,727 INFO L214 etLargeBlockEncoding]: Total number of compositions: 111 [2019-12-07 18:51:36,729 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 94 places, 106 transitions [2019-12-07 18:51:50,116 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 107408 states. [2019-12-07 18:51:50,118 INFO L276 IsEmpty]: Start isEmpty. Operand 107408 states. [2019-12-07 18:51:50,122 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-12-07 18:51:50,122 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:51:50,122 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-12-07 18:51:50,123 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:51:50,126 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:51:50,126 INFO L82 PathProgramCache]: Analyzing trace with hash 809703812, now seen corresponding path program 1 times [2019-12-07 18:51:50,132 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:51:50,132 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [635674667] [2019-12-07 18:51:50,132 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:51:50,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:51:50,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:51:50,273 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [635674667] [2019-12-07 18:51:50,274 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:51:50,274 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:51:50,274 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1248209000] [2019-12-07 18:51:50,277 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:51:50,277 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:51:50,286 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:51:50,286 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:51:50,288 INFO L87 Difference]: Start difference. First operand 107408 states. Second operand 3 states. [2019-12-07 18:51:50,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:51:50,995 INFO L93 Difference]: Finished difference Result 107108 states and 460900 transitions. [2019-12-07 18:51:50,995 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:51:50,996 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 5 [2019-12-07 18:51:50,997 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:51:51,603 INFO L225 Difference]: With dead ends: 107108 [2019-12-07 18:51:51,603 INFO L226 Difference]: Without dead ends: 104924 [2019-12-07 18:51:51,604 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:51:56,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104924 states. [2019-12-07 18:51:57,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104924 to 104924. [2019-12-07 18:51:57,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 104924 states. [2019-12-07 18:51:58,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104924 states to 104924 states and 451982 transitions. [2019-12-07 18:51:58,114 INFO L78 Accepts]: Start accepts. Automaton has 104924 states and 451982 transitions. Word has length 5 [2019-12-07 18:51:58,114 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:51:58,114 INFO L462 AbstractCegarLoop]: Abstraction has 104924 states and 451982 transitions. [2019-12-07 18:51:58,114 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:51:58,114 INFO L276 IsEmpty]: Start isEmpty. Operand 104924 states and 451982 transitions. [2019-12-07 18:51:58,117 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 18:51:58,117 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:51:58,117 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:51:58,117 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:51:58,117 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:51:58,117 INFO L82 PathProgramCache]: Analyzing trace with hash 2105056515, now seen corresponding path program 1 times [2019-12-07 18:51:58,117 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:51:58,118 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [14074534] [2019-12-07 18:51:58,118 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:51:58,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:51:58,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:51:58,188 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [14074534] [2019-12-07 18:51:58,188 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:51:58,188 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:51:58,188 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [105246495] [2019-12-07 18:51:58,190 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:51:58,190 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:51:58,190 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:51:58,190 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:51:58,190 INFO L87 Difference]: Start difference. First operand 104924 states and 451982 transitions. Second operand 4 states. [2019-12-07 18:51:59,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:51:59,201 INFO L93 Difference]: Finished difference Result 168606 states and 697152 transitions. [2019-12-07 18:51:59,201 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:51:59,201 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 18:51:59,201 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:51:59,693 INFO L225 Difference]: With dead ends: 168606 [2019-12-07 18:51:59,694 INFO L226 Difference]: Without dead ends: 168557 [2019-12-07 18:51:59,694 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:52:03,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 168557 states. [2019-12-07 18:52:07,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 168557 to 152629. [2019-12-07 18:52:07,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 152629 states. [2019-12-07 18:52:07,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152629 states to 152629 states and 638547 transitions. [2019-12-07 18:52:07,979 INFO L78 Accepts]: Start accepts. Automaton has 152629 states and 638547 transitions. Word has length 11 [2019-12-07 18:52:07,979 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:07,979 INFO L462 AbstractCegarLoop]: Abstraction has 152629 states and 638547 transitions. [2019-12-07 18:52:07,979 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:52:07,979 INFO L276 IsEmpty]: Start isEmpty. Operand 152629 states and 638547 transitions. [2019-12-07 18:52:07,983 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:52:07,983 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:07,984 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:07,984 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:07,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:07,984 INFO L82 PathProgramCache]: Analyzing trace with hash 2027270657, now seen corresponding path program 1 times [2019-12-07 18:52:07,984 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:07,984 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53807245] [2019-12-07 18:52:07,984 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:08,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:08,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:08,054 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [53807245] [2019-12-07 18:52:08,054 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:08,054 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:52:08,055 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [664185425] [2019-12-07 18:52:08,055 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:52:08,055 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:08,055 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:52:08,055 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:52:08,055 INFO L87 Difference]: Start difference. First operand 152629 states and 638547 transitions. Second operand 4 states. [2019-12-07 18:52:09,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:09,554 INFO L93 Difference]: Finished difference Result 217678 states and 889823 transitions. [2019-12-07 18:52:09,555 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:52:09,555 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 18:52:09,555 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:10,102 INFO L225 Difference]: With dead ends: 217678 [2019-12-07 18:52:10,102 INFO L226 Difference]: Without dead ends: 217615 [2019-12-07 18:52:10,103 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:52:14,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217615 states. [2019-12-07 18:52:19,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217615 to 183279. [2019-12-07 18:52:19,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 183279 states. [2019-12-07 18:52:20,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183279 states to 183279 states and 761454 transitions. [2019-12-07 18:52:20,361 INFO L78 Accepts]: Start accepts. Automaton has 183279 states and 761454 transitions. Word has length 13 [2019-12-07 18:52:20,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:20,362 INFO L462 AbstractCegarLoop]: Abstraction has 183279 states and 761454 transitions. [2019-12-07 18:52:20,362 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:52:20,362 INFO L276 IsEmpty]: Start isEmpty. Operand 183279 states and 761454 transitions. [2019-12-07 18:52:20,364 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:52:20,364 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:20,364 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:20,365 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:20,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:20,365 INFO L82 PathProgramCache]: Analyzing trace with hash 1789207667, now seen corresponding path program 1 times [2019-12-07 18:52:20,365 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:20,365 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739179030] [2019-12-07 18:52:20,365 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:20,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:20,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:20,399 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1739179030] [2019-12-07 18:52:20,399 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:20,399 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:52:20,399 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1628975605] [2019-12-07 18:52:20,400 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:52:20,400 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:20,400 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:52:20,400 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:20,400 INFO L87 Difference]: Start difference. First operand 183279 states and 761454 transitions. Second operand 3 states. [2019-12-07 18:52:20,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:20,512 INFO L93 Difference]: Finished difference Result 36985 states and 120640 transitions. [2019-12-07 18:52:20,513 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:52:20,513 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 13 [2019-12-07 18:52:20,513 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:20,570 INFO L225 Difference]: With dead ends: 36985 [2019-12-07 18:52:20,571 INFO L226 Difference]: Without dead ends: 36985 [2019-12-07 18:52:20,571 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:20,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36985 states. [2019-12-07 18:52:21,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36985 to 36985. [2019-12-07 18:52:21,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36985 states. [2019-12-07 18:52:21,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36985 states to 36985 states and 120640 transitions. [2019-12-07 18:52:21,169 INFO L78 Accepts]: Start accepts. Automaton has 36985 states and 120640 transitions. Word has length 13 [2019-12-07 18:52:21,169 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:21,169 INFO L462 AbstractCegarLoop]: Abstraction has 36985 states and 120640 transitions. [2019-12-07 18:52:21,170 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:52:21,170 INFO L276 IsEmpty]: Start isEmpty. Operand 36985 states and 120640 transitions. [2019-12-07 18:52:21,172 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 18:52:21,172 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:21,172 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:21,173 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:21,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:21,173 INFO L82 PathProgramCache]: Analyzing trace with hash 1405830784, now seen corresponding path program 1 times [2019-12-07 18:52:21,173 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:21,173 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733732783] [2019-12-07 18:52:21,173 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:21,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:21,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:21,243 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1733732783] [2019-12-07 18:52:21,243 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:21,243 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:52:21,243 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [182177956] [2019-12-07 18:52:21,243 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:52:21,243 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:21,243 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:52:21,243 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:52:21,243 INFO L87 Difference]: Start difference. First operand 36985 states and 120640 transitions. Second operand 5 states. [2019-12-07 18:52:21,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:21,733 INFO L93 Difference]: Finished difference Result 50257 states and 160609 transitions. [2019-12-07 18:52:21,733 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:52:21,733 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 18:52:21,733 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:21,809 INFO L225 Difference]: With dead ends: 50257 [2019-12-07 18:52:21,809 INFO L226 Difference]: Without dead ends: 50244 [2019-12-07 18:52:21,809 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:52:22,004 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50244 states. [2019-12-07 18:52:22,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50244 to 37328. [2019-12-07 18:52:22,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37328 states. [2019-12-07 18:52:22,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37328 states to 37328 states and 121606 transitions. [2019-12-07 18:52:22,536 INFO L78 Accepts]: Start accepts. Automaton has 37328 states and 121606 transitions. Word has length 19 [2019-12-07 18:52:22,536 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:22,536 INFO L462 AbstractCegarLoop]: Abstraction has 37328 states and 121606 transitions. [2019-12-07 18:52:22,536 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:52:22,536 INFO L276 IsEmpty]: Start isEmpty. Operand 37328 states and 121606 transitions. [2019-12-07 18:52:22,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 18:52:22,544 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:22,544 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:22,544 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:22,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:22,545 INFO L82 PathProgramCache]: Analyzing trace with hash -1721998258, now seen corresponding path program 1 times [2019-12-07 18:52:22,545 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:22,545 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1378990091] [2019-12-07 18:52:22,545 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:22,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:22,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:22,583 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1378990091] [2019-12-07 18:52:22,583 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:22,583 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:52:22,583 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1145665642] [2019-12-07 18:52:22,584 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:52:22,584 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:22,584 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:52:22,584 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:52:22,584 INFO L87 Difference]: Start difference. First operand 37328 states and 121606 transitions. Second operand 4 states. [2019-12-07 18:52:22,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:22,916 INFO L93 Difference]: Finished difference Result 7104 states and 19431 transitions. [2019-12-07 18:52:22,916 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:52:22,916 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 25 [2019-12-07 18:52:22,917 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:22,922 INFO L225 Difference]: With dead ends: 7104 [2019-12-07 18:52:22,922 INFO L226 Difference]: Without dead ends: 7104 [2019-12-07 18:52:22,923 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:52:22,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7104 states. [2019-12-07 18:52:22,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7104 to 6992. [2019-12-07 18:52:22,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6992 states. [2019-12-07 18:52:23,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6992 states to 6992 states and 19111 transitions. [2019-12-07 18:52:23,003 INFO L78 Accepts]: Start accepts. Automaton has 6992 states and 19111 transitions. Word has length 25 [2019-12-07 18:52:23,003 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:23,003 INFO L462 AbstractCegarLoop]: Abstraction has 6992 states and 19111 transitions. [2019-12-07 18:52:23,003 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:52:23,003 INFO L276 IsEmpty]: Start isEmpty. Operand 6992 states and 19111 transitions. [2019-12-07 18:52:23,010 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 18:52:23,010 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:23,010 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:23,010 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:23,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:23,011 INFO L82 PathProgramCache]: Analyzing trace with hash 2138974623, now seen corresponding path program 1 times [2019-12-07 18:52:23,011 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:23,011 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1178241046] [2019-12-07 18:52:23,011 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:23,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:23,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:23,055 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1178241046] [2019-12-07 18:52:23,055 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:23,055 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:52:23,055 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1438525159] [2019-12-07 18:52:23,056 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:52:23,056 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:23,056 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:52:23,056 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:52:23,056 INFO L87 Difference]: Start difference. First operand 6992 states and 19111 transitions. Second operand 5 states. [2019-12-07 18:52:23,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:23,084 INFO L93 Difference]: Finished difference Result 5024 states and 14421 transitions. [2019-12-07 18:52:23,085 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:52:23,085 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 37 [2019-12-07 18:52:23,085 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:23,091 INFO L225 Difference]: With dead ends: 5024 [2019-12-07 18:52:23,091 INFO L226 Difference]: Without dead ends: 5024 [2019-12-07 18:52:23,091 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:52:23,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5024 states. [2019-12-07 18:52:23,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5024 to 4660. [2019-12-07 18:52:23,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4660 states. [2019-12-07 18:52:23,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4660 states to 4660 states and 13437 transitions. [2019-12-07 18:52:23,169 INFO L78 Accepts]: Start accepts. Automaton has 4660 states and 13437 transitions. Word has length 37 [2019-12-07 18:52:23,169 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:23,169 INFO L462 AbstractCegarLoop]: Abstraction has 4660 states and 13437 transitions. [2019-12-07 18:52:23,169 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:52:23,169 INFO L276 IsEmpty]: Start isEmpty. Operand 4660 states and 13437 transitions. [2019-12-07 18:52:23,176 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:52:23,176 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:23,176 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:23,176 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:23,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:23,177 INFO L82 PathProgramCache]: Analyzing trace with hash 1030638940, now seen corresponding path program 1 times [2019-12-07 18:52:23,177 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:23,177 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1301832693] [2019-12-07 18:52:23,177 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:23,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:23,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:23,226 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1301832693] [2019-12-07 18:52:23,226 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:23,227 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:52:23,227 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1750342894] [2019-12-07 18:52:23,227 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:52:23,227 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:23,227 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:52:23,228 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:23,228 INFO L87 Difference]: Start difference. First operand 4660 states and 13437 transitions. Second operand 3 states. [2019-12-07 18:52:23,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:23,268 INFO L93 Difference]: Finished difference Result 4669 states and 13450 transitions. [2019-12-07 18:52:23,269 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:52:23,269 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 18:52:23,269 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:23,274 INFO L225 Difference]: With dead ends: 4669 [2019-12-07 18:52:23,274 INFO L226 Difference]: Without dead ends: 4669 [2019-12-07 18:52:23,274 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:23,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4669 states. [2019-12-07 18:52:23,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4669 to 4665. [2019-12-07 18:52:23,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4665 states. [2019-12-07 18:52:23,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4665 states to 4665 states and 13446 transitions. [2019-12-07 18:52:23,333 INFO L78 Accepts]: Start accepts. Automaton has 4665 states and 13446 transitions. Word has length 65 [2019-12-07 18:52:23,333 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:23,333 INFO L462 AbstractCegarLoop]: Abstraction has 4665 states and 13446 transitions. [2019-12-07 18:52:23,333 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:52:23,333 INFO L276 IsEmpty]: Start isEmpty. Operand 4665 states and 13446 transitions. [2019-12-07 18:52:23,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:52:23,340 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:23,340 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:23,340 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:23,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:23,340 INFO L82 PathProgramCache]: Analyzing trace with hash 1902070617, now seen corresponding path program 1 times [2019-12-07 18:52:23,340 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:23,340 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [263816634] [2019-12-07 18:52:23,341 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:23,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:23,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:23,393 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [263816634] [2019-12-07 18:52:23,393 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:23,394 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:52:23,394 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1124802812] [2019-12-07 18:52:23,394 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:52:23,394 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:23,394 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:52:23,395 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:23,395 INFO L87 Difference]: Start difference. First operand 4665 states and 13446 transitions. Second operand 3 states. [2019-12-07 18:52:23,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:23,436 INFO L93 Difference]: Finished difference Result 4669 states and 13441 transitions. [2019-12-07 18:52:23,437 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:52:23,437 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 18:52:23,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:23,442 INFO L225 Difference]: With dead ends: 4669 [2019-12-07 18:52:23,443 INFO L226 Difference]: Without dead ends: 4669 [2019-12-07 18:52:23,443 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:23,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4669 states. [2019-12-07 18:52:23,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4669 to 4665. [2019-12-07 18:52:23,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4665 states. [2019-12-07 18:52:23,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4665 states to 4665 states and 13437 transitions. [2019-12-07 18:52:23,503 INFO L78 Accepts]: Start accepts. Automaton has 4665 states and 13437 transitions. Word has length 65 [2019-12-07 18:52:23,503 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:23,503 INFO L462 AbstractCegarLoop]: Abstraction has 4665 states and 13437 transitions. [2019-12-07 18:52:23,503 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:52:23,503 INFO L276 IsEmpty]: Start isEmpty. Operand 4665 states and 13437 transitions. [2019-12-07 18:52:23,508 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:52:23,509 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:23,509 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:23,509 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:23,509 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:23,509 INFO L82 PathProgramCache]: Analyzing trace with hash 1892358751, now seen corresponding path program 1 times [2019-12-07 18:52:23,509 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:23,509 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1156673956] [2019-12-07 18:52:23,509 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:23,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:23,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:23,566 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1156673956] [2019-12-07 18:52:23,566 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:23,566 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:52:23,566 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [509215965] [2019-12-07 18:52:23,567 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:52:23,567 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:23,567 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:52:23,567 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:23,567 INFO L87 Difference]: Start difference. First operand 4665 states and 13437 transitions. Second operand 3 states. [2019-12-07 18:52:23,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:23,585 INFO L93 Difference]: Finished difference Result 4665 states and 13233 transitions. [2019-12-07 18:52:23,585 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:52:23,585 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 18:52:23,585 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:23,589 INFO L225 Difference]: With dead ends: 4665 [2019-12-07 18:52:23,589 INFO L226 Difference]: Without dead ends: 4665 [2019-12-07 18:52:23,589 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:23,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4665 states. [2019-12-07 18:52:23,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4665 to 4665. [2019-12-07 18:52:23,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4665 states. [2019-12-07 18:52:23,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4665 states to 4665 states and 13233 transitions. [2019-12-07 18:52:23,644 INFO L78 Accepts]: Start accepts. Automaton has 4665 states and 13233 transitions. Word has length 65 [2019-12-07 18:52:23,644 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:23,644 INFO L462 AbstractCegarLoop]: Abstraction has 4665 states and 13233 transitions. [2019-12-07 18:52:23,644 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:52:23,645 INFO L276 IsEmpty]: Start isEmpty. Operand 4665 states and 13233 transitions. [2019-12-07 18:52:23,650 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 18:52:23,650 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:23,650 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:23,650 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:23,650 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:23,650 INFO L82 PathProgramCache]: Analyzing trace with hash 1887448171, now seen corresponding path program 1 times [2019-12-07 18:52:23,650 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:23,651 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [393857836] [2019-12-07 18:52:23,651 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:23,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:23,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:23,723 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [393857836] [2019-12-07 18:52:23,723 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:23,724 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:52:23,724 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [480601976] [2019-12-07 18:52:23,724 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:52:23,724 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:23,724 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:52:23,724 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:52:23,725 INFO L87 Difference]: Start difference. First operand 4665 states and 13233 transitions. Second operand 5 states. [2019-12-07 18:52:23,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:23,906 INFO L93 Difference]: Finished difference Result 7071 states and 19930 transitions. [2019-12-07 18:52:23,906 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:52:23,906 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 66 [2019-12-07 18:52:23,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:23,914 INFO L225 Difference]: With dead ends: 7071 [2019-12-07 18:52:23,914 INFO L226 Difference]: Without dead ends: 7071 [2019-12-07 18:52:23,914 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:52:23,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7071 states. [2019-12-07 18:52:23,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7071 to 5806. [2019-12-07 18:52:23,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5806 states. [2019-12-07 18:52:24,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5806 states to 5806 states and 16512 transitions. [2019-12-07 18:52:24,001 INFO L78 Accepts]: Start accepts. Automaton has 5806 states and 16512 transitions. Word has length 66 [2019-12-07 18:52:24,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:24,001 INFO L462 AbstractCegarLoop]: Abstraction has 5806 states and 16512 transitions. [2019-12-07 18:52:24,002 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:52:24,002 INFO L276 IsEmpty]: Start isEmpty. Operand 5806 states and 16512 transitions. [2019-12-07 18:52:24,008 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 18:52:24,009 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:24,009 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:24,009 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:24,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:24,009 INFO L82 PathProgramCache]: Analyzing trace with hash 284491425, now seen corresponding path program 2 times [2019-12-07 18:52:24,009 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:24,009 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364251490] [2019-12-07 18:52:24,009 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:24,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:24,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:24,101 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364251490] [2019-12-07 18:52:24,101 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:24,101 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:52:24,101 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [106116424] [2019-12-07 18:52:24,101 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:52:24,101 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:24,102 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:52:24,102 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:52:24,102 INFO L87 Difference]: Start difference. First operand 5806 states and 16512 transitions. Second operand 7 states. [2019-12-07 18:52:24,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:24,202 INFO L93 Difference]: Finished difference Result 12454 states and 35648 transitions. [2019-12-07 18:52:24,203 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:52:24,203 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 66 [2019-12-07 18:52:24,203 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:24,210 INFO L225 Difference]: With dead ends: 12454 [2019-12-07 18:52:24,210 INFO L226 Difference]: Without dead ends: 7038 [2019-12-07 18:52:24,210 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:52:24,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7038 states. [2019-12-07 18:52:24,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7038 to 5374. [2019-12-07 18:52:24,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5374 states. [2019-12-07 18:52:24,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5374 states to 5374 states and 15303 transitions. [2019-12-07 18:52:24,283 INFO L78 Accepts]: Start accepts. Automaton has 5374 states and 15303 transitions. Word has length 66 [2019-12-07 18:52:24,283 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:24,283 INFO L462 AbstractCegarLoop]: Abstraction has 5374 states and 15303 transitions. [2019-12-07 18:52:24,283 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:52:24,283 INFO L276 IsEmpty]: Start isEmpty. Operand 5374 states and 15303 transitions. [2019-12-07 18:52:24,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 18:52:24,289 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:24,289 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:24,290 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:24,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:24,290 INFO L82 PathProgramCache]: Analyzing trace with hash 1151214921, now seen corresponding path program 3 times [2019-12-07 18:52:24,290 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:24,290 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1250677411] [2019-12-07 18:52:24,290 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:24,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:24,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:24,369 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1250677411] [2019-12-07 18:52:24,369 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:24,369 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:52:24,369 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1704208526] [2019-12-07 18:52:24,370 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:52:24,370 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:24,370 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:52:24,370 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:52:24,370 INFO L87 Difference]: Start difference. First operand 5374 states and 15303 transitions. Second operand 6 states. [2019-12-07 18:52:24,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:24,442 INFO L93 Difference]: Finished difference Result 8799 states and 25152 transitions. [2019-12-07 18:52:24,442 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:52:24,442 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 66 [2019-12-07 18:52:24,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:24,446 INFO L225 Difference]: With dead ends: 8799 [2019-12-07 18:52:24,446 INFO L226 Difference]: Without dead ends: 4138 [2019-12-07 18:52:24,446 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:52:24,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4138 states. [2019-12-07 18:52:24,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4138 to 3574. [2019-12-07 18:52:24,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3574 states. [2019-12-07 18:52:24,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3574 states to 3574 states and 10191 transitions. [2019-12-07 18:52:24,491 INFO L78 Accepts]: Start accepts. Automaton has 3574 states and 10191 transitions. Word has length 66 [2019-12-07 18:52:24,491 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:24,491 INFO L462 AbstractCegarLoop]: Abstraction has 3574 states and 10191 transitions. [2019-12-07 18:52:24,491 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:52:24,492 INFO L276 IsEmpty]: Start isEmpty. Operand 3574 states and 10191 transitions. [2019-12-07 18:52:24,496 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 18:52:24,496 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:24,496 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:24,496 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:24,496 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:24,496 INFO L82 PathProgramCache]: Analyzing trace with hash 799304253, now seen corresponding path program 4 times [2019-12-07 18:52:24,496 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:24,496 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [396238803] [2019-12-07 18:52:24,497 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:24,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:24,564 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:24,565 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [396238803] [2019-12-07 18:52:24,565 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:24,565 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:52:24,565 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1469416673] [2019-12-07 18:52:24,565 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:52:24,566 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:24,566 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:52:24,566 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:52:24,566 INFO L87 Difference]: Start difference. First operand 3574 states and 10191 transitions. Second operand 5 states. [2019-12-07 18:52:24,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:24,746 INFO L93 Difference]: Finished difference Result 5303 states and 14970 transitions. [2019-12-07 18:52:24,746 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:52:24,746 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 66 [2019-12-07 18:52:24,747 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:24,751 INFO L225 Difference]: With dead ends: 5303 [2019-12-07 18:52:24,751 INFO L226 Difference]: Without dead ends: 5303 [2019-12-07 18:52:24,751 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:52:24,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5303 states. [2019-12-07 18:52:24,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5303 to 4163. [2019-12-07 18:52:24,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4163 states. [2019-12-07 18:52:24,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4163 states to 4163 states and 11890 transitions. [2019-12-07 18:52:24,806 INFO L78 Accepts]: Start accepts. Automaton has 4163 states and 11890 transitions. Word has length 66 [2019-12-07 18:52:24,806 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:24,806 INFO L462 AbstractCegarLoop]: Abstraction has 4163 states and 11890 transitions. [2019-12-07 18:52:24,806 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:52:24,806 INFO L276 IsEmpty]: Start isEmpty. Operand 4163 states and 11890 transitions. [2019-12-07 18:52:24,811 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 18:52:24,811 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:24,811 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:24,811 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:24,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:24,811 INFO L82 PathProgramCache]: Analyzing trace with hash 1690997639, now seen corresponding path program 5 times [2019-12-07 18:52:24,811 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:24,812 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [792430018] [2019-12-07 18:52:24,812 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:24,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:24,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:24,882 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [792430018] [2019-12-07 18:52:24,882 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:24,883 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:52:24,883 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1055196670] [2019-12-07 18:52:24,883 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:52:24,883 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:24,883 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:52:24,883 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:52:24,884 INFO L87 Difference]: Start difference. First operand 4163 states and 11890 transitions. Second operand 6 states. [2019-12-07 18:52:25,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:25,116 INFO L93 Difference]: Finished difference Result 5738 states and 16107 transitions. [2019-12-07 18:52:25,116 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 18:52:25,116 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 66 [2019-12-07 18:52:25,117 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:25,121 INFO L225 Difference]: With dead ends: 5738 [2019-12-07 18:52:25,121 INFO L226 Difference]: Without dead ends: 5738 [2019-12-07 18:52:25,121 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:52:25,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5738 states. [2019-12-07 18:52:25,173 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5738 to 4254. [2019-12-07 18:52:25,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4254 states. [2019-12-07 18:52:25,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4254 states to 4254 states and 12143 transitions. [2019-12-07 18:52:25,179 INFO L78 Accepts]: Start accepts. Automaton has 4254 states and 12143 transitions. Word has length 66 [2019-12-07 18:52:25,179 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:25,179 INFO L462 AbstractCegarLoop]: Abstraction has 4254 states and 12143 transitions. [2019-12-07 18:52:25,179 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:52:25,179 INFO L276 IsEmpty]: Start isEmpty. Operand 4254 states and 12143 transitions. [2019-12-07 18:52:25,183 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 18:52:25,184 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:25,184 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:25,184 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:25,184 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:25,184 INFO L82 PathProgramCache]: Analyzing trace with hash -1243763205, now seen corresponding path program 6 times [2019-12-07 18:52:25,184 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:25,184 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [544466358] [2019-12-07 18:52:25,184 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:25,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:25,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:25,311 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [544466358] [2019-12-07 18:52:25,311 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:25,311 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 18:52:25,311 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [401514035] [2019-12-07 18:52:25,311 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 18:52:25,311 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:25,311 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 18:52:25,311 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:52:25,312 INFO L87 Difference]: Start difference. First operand 4254 states and 12143 transitions. Second operand 10 states. [2019-12-07 18:52:25,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:25,903 INFO L93 Difference]: Finished difference Result 7329 states and 19975 transitions. [2019-12-07 18:52:25,903 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 18:52:25,903 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 66 [2019-12-07 18:52:25,904 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:25,909 INFO L225 Difference]: With dead ends: 7329 [2019-12-07 18:52:25,909 INFO L226 Difference]: Without dead ends: 7329 [2019-12-07 18:52:25,909 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 9 SyntacticMatches, 3 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 68 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=108, Invalid=312, Unknown=0, NotChecked=0, Total=420 [2019-12-07 18:52:25,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7329 states. [2019-12-07 18:52:25,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7329 to 3543. [2019-12-07 18:52:25,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3543 states. [2019-12-07 18:52:25,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3543 states to 3543 states and 9841 transitions. [2019-12-07 18:52:25,967 INFO L78 Accepts]: Start accepts. Automaton has 3543 states and 9841 transitions. Word has length 66 [2019-12-07 18:52:25,967 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:25,967 INFO L462 AbstractCegarLoop]: Abstraction has 3543 states and 9841 transitions. [2019-12-07 18:52:25,968 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 18:52:25,968 INFO L276 IsEmpty]: Start isEmpty. Operand 3543 states and 9841 transitions. [2019-12-07 18:52:25,971 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 18:52:25,971 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:25,971 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:25,972 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:25,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:25,972 INFO L82 PathProgramCache]: Analyzing trace with hash -1958263493, now seen corresponding path program 7 times [2019-12-07 18:52:25,972 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:25,972 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807386295] [2019-12-07 18:52:25,972 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:25,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:26,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:26,004 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1807386295] [2019-12-07 18:52:26,004 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:26,004 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:52:26,004 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2135981290] [2019-12-07 18:52:26,004 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:52:26,004 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:26,004 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:52:26,005 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:26,005 INFO L87 Difference]: Start difference. First operand 3543 states and 9841 transitions. Second operand 3 states. [2019-12-07 18:52:26,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:26,037 INFO L93 Difference]: Finished difference Result 3543 states and 9840 transitions. [2019-12-07 18:52:26,037 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:52:26,037 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 18:52:26,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:26,040 INFO L225 Difference]: With dead ends: 3543 [2019-12-07 18:52:26,040 INFO L226 Difference]: Without dead ends: 3543 [2019-12-07 18:52:26,040 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:26,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3543 states. [2019-12-07 18:52:26,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3543 to 2581. [2019-12-07 18:52:26,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2581 states. [2019-12-07 18:52:26,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2581 states to 2581 states and 7228 transitions. [2019-12-07 18:52:26,078 INFO L78 Accepts]: Start accepts. Automaton has 2581 states and 7228 transitions. Word has length 66 [2019-12-07 18:52:26,078 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:26,078 INFO L462 AbstractCegarLoop]: Abstraction has 2581 states and 7228 transitions. [2019-12-07 18:52:26,078 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:52:26,078 INFO L276 IsEmpty]: Start isEmpty. Operand 2581 states and 7228 transitions. [2019-12-07 18:52:26,081 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:52:26,081 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:26,082 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:26,082 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:26,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:26,082 INFO L82 PathProgramCache]: Analyzing trace with hash -247337982, now seen corresponding path program 1 times [2019-12-07 18:52:26,082 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:26,082 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464535666] [2019-12-07 18:52:26,082 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:26,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:26,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:26,112 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1464535666] [2019-12-07 18:52:26,112 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:26,112 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:52:26,113 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1969792134] [2019-12-07 18:52:26,113 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:52:26,113 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:26,113 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:52:26,113 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:26,113 INFO L87 Difference]: Start difference. First operand 2581 states and 7228 transitions. Second operand 3 states. [2019-12-07 18:52:26,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:26,124 INFO L93 Difference]: Finished difference Result 2320 states and 6398 transitions. [2019-12-07 18:52:26,124 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:52:26,124 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 18:52:26,124 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:26,126 INFO L225 Difference]: With dead ends: 2320 [2019-12-07 18:52:26,126 INFO L226 Difference]: Without dead ends: 2320 [2019-12-07 18:52:26,126 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:52:26,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2320 states. [2019-12-07 18:52:26,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2320 to 2152. [2019-12-07 18:52:26,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2152 states. [2019-12-07 18:52:26,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2152 states to 2152 states and 5946 transitions. [2019-12-07 18:52:26,153 INFO L78 Accepts]: Start accepts. Automaton has 2152 states and 5946 transitions. Word has length 67 [2019-12-07 18:52:26,153 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:26,153 INFO L462 AbstractCegarLoop]: Abstraction has 2152 states and 5946 transitions. [2019-12-07 18:52:26,153 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:52:26,154 INFO L276 IsEmpty]: Start isEmpty. Operand 2152 states and 5946 transitions. [2019-12-07 18:52:26,156 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:52:26,156 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:26,156 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:26,156 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:26,156 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:26,156 INFO L82 PathProgramCache]: Analyzing trace with hash -1259160564, now seen corresponding path program 1 times [2019-12-07 18:52:26,156 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:26,157 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1236174570] [2019-12-07 18:52:26,157 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:26,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:52:26,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:52:26,230 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:52:26,230 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 18:52:26,233 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] ULTIMATE.startENTRY-->L805: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= |v_#valid_53| (store .cse0 |v_ULTIMATE.start_main_~#t1810~0.base_20| 1)) (= 0 v_~x~0_194) (= 0 v_~x$r_buff0_thd2~0_213) (= 0 v_~weak$$choice0~0_14) (= v_~x$mem_tmp~0_19 0) (= 0 v_~x$w_buff0~0_268) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t1810~0.base_20| 4)) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t1810~0.base_20|) (= 0 v_~x$r_buff1_thd2~0_212) (= v_~x$r_buff1_thd0~0_297 0) (< 0 |v_#StackHeapBarrier_17|) (= 0 v_~x$read_delayed_var~0.base_7) (= v_~x$r_buff1_thd1~0_187 0) (= |v_ULTIMATE.start_main_~#t1810~0.offset_17| 0) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1810~0.base_20| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1810~0.base_20|) |v_ULTIMATE.start_main_~#t1810~0.offset_17| 0)) |v_#memory_int_21|) (= v_~x$r_buff0_thd0~0_372 0) (= v_~y~0_143 0) (= 0 v_~x$read_delayed~0_6) (= v_~__unbuffered_cnt~0_155 0) (= 0 v_~x$w_buff1~0_230) (= 0 |v_#NULL.base_4|) (= 0 v_~__unbuffered_p0_EAX~0_24) (= 0 v_~x$r_buff1_thd3~0_195) (= 0 v_~x$r_buff0_thd3~0_123) (= |v_#NULL.offset_4| 0) (= 0 v_~x$w_buff1_used~0_504) (= 0 v_~x$read_delayed_var~0.offset_7) (= (select .cse0 |v_ULTIMATE.start_main_~#t1810~0.base_20|) 0) (= v_~x$r_buff0_thd1~0_120 0) (= 0 v_~__unbuffered_p2_EAX~0_22) (= v_~x$flush_delayed~0_34 0) (= v_~main$tmp_guard0~0_24 0) (= v_~weak$$choice2~0_110 0) (= 0 v_~x$w_buff0_used~0_807) (= v_~main$tmp_guard1~0_22 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_22|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_21|, ~x$w_buff0~0=v_~x$w_buff0~0_268, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_27|, ~x$flush_delayed~0=v_~x$flush_delayed~0_34, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_39|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_29|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_45|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_187, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_123, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_50|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_36|, ULTIMATE.start_main_~#t1810~0.offset=|v_ULTIMATE.start_main_~#t1810~0.offset_17|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_45|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_32|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_24, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_22, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_372, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_37|, ~x$w_buff1~0=v_~x$w_buff1~0_230, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_504, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_212, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_48|, ULTIMATE.start_main_~#t1811~0.base=|v_ULTIMATE.start_main_~#t1811~0.base_21|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_111|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_7, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_~#t1810~0.base=|v_ULTIMATE.start_main_~#t1810~0.base_20|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_155, ~x~0=v_~x~0_194, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_120, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_33|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_31|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_29|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_195, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_22, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_125|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_17|, ~x$mem_tmp~0=v_~x$mem_tmp~0_19, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_25|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_31|, ULTIMATE.start_main_~#t1812~0.base=|v_ULTIMATE.start_main_~#t1812~0.base_20|, ~y~0=v_~y~0_143, ULTIMATE.start_main_~#t1811~0.offset=|v_ULTIMATE.start_main_~#t1811~0.offset_17|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_10|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_23|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_25|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_48|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_297, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_213, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_59|, ULTIMATE.start_main_~#t1812~0.offset=|v_ULTIMATE.start_main_~#t1812~0.offset_16|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_38|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_807, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_32|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_7, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_21|, ~weak$$choice2~0=v_~weak$$choice2~0_110, ~x$read_delayed~0=v_~x$read_delayed~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ~x$w_buff0~0, ULTIMATE.start_main_#t~ite28, ~x$flush_delayed~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ~x$r_buff1_thd1~0, ~x$r_buff0_thd3~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_~#t1810~0.offset, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~__unbuffered_p0_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ~x$w_buff1~0, ULTIMATE.start_main_#t~ite35, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_~#t1811~0.base, ULTIMATE.start_main_#t~ite33, ~x$read_delayed_var~0.base, ~weak$$choice0~0, ULTIMATE.start_main_~#t1810~0.base, ULTIMATE.start_main_#t~ite40, ~__unbuffered_cnt~0, ~x~0, ~x$r_buff0_thd1~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~x$r_buff1_thd3~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~x$mem_tmp~0, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ULTIMATE.start_main_~#t1812~0.base, ~y~0, ULTIMATE.start_main_~#t1811~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_~#t1812~0.offset, #NULL.base, ULTIMATE.start_main_#t~ite34, ~x$w_buff0_used~0, ULTIMATE.start_main_#t~ite41, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_#res, #valid, #memory_int, ~weak$$choice2~0, ~x$read_delayed~0] because there is no mapped edge [2019-12-07 18:52:26,233 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L805-1-->L807: Formula: (and (not (= |v_ULTIMATE.start_main_~#t1811~0.base_11| 0)) (= (store |v_#valid_32| |v_ULTIMATE.start_main_~#t1811~0.base_11| 1) |v_#valid_31|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1811~0.base_11| 4)) (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t1811~0.base_11|)) (= |v_ULTIMATE.start_main_~#t1811~0.offset_10| 0) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1811~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1811~0.base_11|) |v_ULTIMATE.start_main_~#t1811~0.offset_10| 1)) |v_#memory_int_13|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1811~0.base_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_6|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1811~0.base=|v_ULTIMATE.start_main_~#t1811~0.base_11|, ULTIMATE.start_main_~#t1811~0.offset=|v_ULTIMATE.start_main_~#t1811~0.offset_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1811~0.base, ULTIMATE.start_main_~#t1811~0.offset] because there is no mapped edge [2019-12-07 18:52:26,233 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L807-1-->L809: Formula: (and (= 0 (select |v_#valid_28| |v_ULTIMATE.start_main_~#t1812~0.base_9|)) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t1812~0.base_9|) (= (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t1812~0.base_9| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t1812~0.base_9|) |v_ULTIMATE.start_main_~#t1812~0.offset_8| 2)) |v_#memory_int_9|) (not (= 0 |v_ULTIMATE.start_main_~#t1812~0.base_9|)) (= |v_#valid_27| (store |v_#valid_28| |v_ULTIMATE.start_main_~#t1812~0.base_9| 1)) (= |v_ULTIMATE.start_main_~#t1812~0.offset_8| 0) (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t1812~0.base_9| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_28|, #memory_int=|v_#memory_int_10|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_27|, #memory_int=|v_#memory_int_9|, ULTIMATE.start_main_~#t1812~0.base=|v_ULTIMATE.start_main_~#t1812~0.base_9|, #length=|v_#length_13|, ULTIMATE.start_main_~#t1812~0.offset=|v_ULTIMATE.start_main_~#t1812~0.offset_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, ULTIMATE.start_main_~#t1812~0.base, #length, ULTIMATE.start_main_~#t1812~0.offset] because there is no mapped edge [2019-12-07 18:52:26,234 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] P1ENTRY-->L4-3: Formula: (and (not (= 0 v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11)) (= v_P1Thread1of1ForFork1_~arg.offset_9 |v_P1Thread1of1ForFork1_#in~arg.offset_11|) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9| v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11) (= 1 v_~x$w_buff0_used~0_98) (= 2 v_~x$w_buff0~0_31) (= v_P1Thread1of1ForFork1_~arg.base_9 |v_P1Thread1of1ForFork1_#in~arg.base_11|) (= v_~x$w_buff1_used~0_55 v_~x$w_buff0_used~0_99) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9| (ite (not (and (not (= (mod v_~x$w_buff0_used~0_98 256) 0)) (not (= 0 (mod v_~x$w_buff1_used~0_55 256))))) 1 0)) (= v_~x$w_buff0~0_32 v_~x$w_buff1~0_21)) InVars {~x$w_buff0~0=v_~x$w_buff0~0_32, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_11|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_11|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_99} OutVars{P1Thread1of1ForFork1___VERIFIER_assert_~expression=v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11, ~x$w_buff0~0=v_~x$w_buff0~0_31, P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_9, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression=|v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9|, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_9, ~x$w_buff1~0=v_~x$w_buff1~0_21, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_11|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_11|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_55, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_98} AuxVars[] AssignedVars[P1Thread1of1ForFork1___VERIFIER_assert_~expression, ~x$w_buff0~0, P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression, P1Thread1of1ForFork1_~arg.base, ~x$w_buff1~0, ~x$w_buff1_used~0, ~x$w_buff0_used~0] because there is no mapped edge [2019-12-07 18:52:26,235 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L782-2-->L782-4: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff1_used~0_In1095061724 256))) (.cse0 (= 0 (mod ~x$r_buff1_thd3~0_In1095061724 256)))) (or (and (or .cse0 .cse1) (= ~x~0_In1095061724 |P2Thread1of1ForFork2_#t~ite15_Out1095061724|)) (and (not .cse1) (= |P2Thread1of1ForFork2_#t~ite15_Out1095061724| ~x$w_buff1~0_In1095061724) (not .cse0)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In1095061724, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1095061724, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1095061724, ~x~0=~x~0_In1095061724} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out1095061724|, ~x$w_buff1~0=~x$w_buff1~0_In1095061724, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1095061724, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1095061724, ~x~0=~x~0_In1095061724} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 18:52:26,235 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L782-4-->L783: Formula: (= v_~x~0_20 |v_P2Thread1of1ForFork2_#t~ite15_10|) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_10|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_9|, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_5|, ~x~0=v_~x~0_20} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, P2Thread1of1ForFork2_#t~ite16, ~x~0] because there is no mapped edge [2019-12-07 18:52:26,235 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L783-->L783-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In-908373812 256))) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In-908373812 256)))) (or (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In-908373812 |P2Thread1of1ForFork2_#t~ite17_Out-908373812|)) (and (not .cse0) (not .cse1) (= 0 |P2Thread1of1ForFork2_#t~ite17_Out-908373812|)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-908373812, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-908373812} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-908373812, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out-908373812|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-908373812} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 18:52:26,235 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L784-->L784-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff1_thd3~0_In-650695679 256))) (.cse0 (= 0 (mod ~x$w_buff1_used~0_In-650695679 256))) (.cse3 (= (mod ~x$w_buff0_used~0_In-650695679 256) 0)) (.cse2 (= 0 (mod ~x$r_buff0_thd3~0_In-650695679 256)))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite18_Out-650695679|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse3 .cse2) (= ~x$w_buff1_used~0_In-650695679 |P2Thread1of1ForFork2_#t~ite18_Out-650695679|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-650695679, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-650695679, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-650695679, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-650695679} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-650695679, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-650695679, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-650695679, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-650695679|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-650695679} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 18:52:26,236 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L733-2-->L733-5: Formula: (let ((.cse0 (= |P0Thread1of1ForFork0_#t~ite4_Out-1623345393| |P0Thread1of1ForFork0_#t~ite3_Out-1623345393|)) (.cse2 (= (mod ~x$r_buff1_thd1~0_In-1623345393 256) 0)) (.cse1 (= (mod ~x$w_buff1_used~0_In-1623345393 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite3_Out-1623345393| ~x~0_In-1623345393) .cse0 (or .cse1 .cse2)) (and .cse0 (= ~x$w_buff1~0_In-1623345393 |P0Thread1of1ForFork0_#t~ite3_Out-1623345393|) (not .cse2) (not .cse1)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-1623345393, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1623345393, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1623345393, ~x~0=~x~0_In-1623345393} OutVars{P0Thread1of1ForFork0_#t~ite3=|P0Thread1of1ForFork0_#t~ite3_Out-1623345393|, P0Thread1of1ForFork0_#t~ite4=|P0Thread1of1ForFork0_#t~ite4_Out-1623345393|, ~x$w_buff1~0=~x$w_buff1~0_In-1623345393, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1623345393, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1623345393, ~x~0=~x~0_In-1623345393} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite3, P0Thread1of1ForFork0_#t~ite4] because there is no mapped edge [2019-12-07 18:52:26,236 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [774] [774] L734-->L734-2: Formula: (let ((.cse0 (= (mod ~x$r_buff0_thd1~0_In-798918919 256) 0)) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In-798918919 256)))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite5_Out-798918919| 0)) (and (= ~x$w_buff0_used~0_In-798918919 |P0Thread1of1ForFork0_#t~ite5_Out-798918919|) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-798918919, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-798918919} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-798918919|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-798918919, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-798918919} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 18:52:26,236 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L735-->L735-2: Formula: (let ((.cse3 (= 0 (mod ~x$w_buff0_used~0_In119740061 256))) (.cse2 (= (mod ~x$r_buff0_thd1~0_In119740061 256) 0)) (.cse0 (= (mod ~x$r_buff1_thd1~0_In119740061 256) 0)) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In119740061 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork0_#t~ite6_Out119740061|)) (and (= ~x$w_buff1_used~0_In119740061 |P0Thread1of1ForFork0_#t~ite6_Out119740061|) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In119740061, ~x$w_buff1_used~0=~x$w_buff1_used~0_In119740061, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In119740061, ~x$w_buff0_used~0=~x$w_buff0_used~0_In119740061} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out119740061|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In119740061, ~x$w_buff1_used~0=~x$w_buff1_used~0_In119740061, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In119740061, ~x$w_buff0_used~0=~x$w_buff0_used~0_In119740061} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 18:52:26,236 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L785-->L785-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In-1542421039 256))) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In-1542421039 256)))) (or (and (or .cse0 .cse1) (= ~x$r_buff0_thd3~0_In-1542421039 |P2Thread1of1ForFork2_#t~ite19_Out-1542421039|)) (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork2_#t~ite19_Out-1542421039| 0)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1542421039, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1542421039} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1542421039, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-1542421039|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1542421039} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 18:52:26,237 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L786-->L786-2: Formula: (let ((.cse3 (= 0 (mod ~x$r_buff0_thd3~0_In-1080119250 256))) (.cse2 (= (mod ~x$w_buff0_used~0_In-1080119250 256) 0)) (.cse0 (= (mod ~x$w_buff1_used~0_In-1080119250 256) 0)) (.cse1 (= (mod ~x$r_buff1_thd3~0_In-1080119250 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~x$r_buff1_thd3~0_In-1080119250 |P2Thread1of1ForFork2_#t~ite20_Out-1080119250|)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= 0 |P2Thread1of1ForFork2_#t~ite20_Out-1080119250|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1080119250, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1080119250, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1080119250, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1080119250} OutVars{P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-1080119250|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1080119250, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1080119250, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1080119250, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1080119250} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 18:52:26,237 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L786-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74) (= |v_P2Thread1of1ForFork2_#t~ite20_52| v_~x$r_buff1_thd3~0_147)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_52|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_51|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_147, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~x$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 18:52:26,237 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L736-->L736-2: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In-1954027416 256) 0)) (.cse0 (= (mod ~x$r_buff0_thd1~0_In-1954027416 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite7_Out-1954027416| 0) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |P0Thread1of1ForFork0_#t~ite7_Out-1954027416| ~x$r_buff0_thd1~0_In-1954027416)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1954027416, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1954027416} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1954027416, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out-1954027416|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1954027416} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-12-07 18:52:26,238 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L737-->L737-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff1_thd1~0_In-1041113883 256))) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In-1041113883 256))) (.cse2 (= 0 (mod ~x$r_buff0_thd1~0_In-1041113883 256))) (.cse3 (= 0 (mod ~x$w_buff0_used~0_In-1041113883 256)))) (or (and (= 0 |P0Thread1of1ForFork0_#t~ite8_Out-1041113883|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (= |P0Thread1of1ForFork0_#t~ite8_Out-1041113883| ~x$r_buff1_thd1~0_In-1041113883) (or .cse2 .cse3)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1041113883, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1041113883, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1041113883, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1041113883} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1041113883, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-1041113883|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1041113883, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1041113883, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1041113883} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 18:52:26,238 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L737-2-->P0EXIT: Formula: (and (= v_~x$r_buff1_thd1~0_61 |v_P0Thread1of1ForFork0_#t~ite8_24|) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_45 1) v_~__unbuffered_cnt~0_44)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_45} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_23|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_44, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_61} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, ~x$r_buff1_thd1~0] because there is no mapped edge [2019-12-07 18:52:26,238 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L763-->L763-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff0_thd2~0_In-915202456 256))) (.cse1 (= (mod ~x$w_buff0_used~0_In-915202456 256) 0))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out-915202456| 0)) (and (= ~x$w_buff0_used~0_In-915202456 |P1Thread1of1ForFork1_#t~ite11_Out-915202456|) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-915202456, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-915202456} OutVars{P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out-915202456|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-915202456, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-915202456} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 18:52:26,238 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L764-->L764-2: Formula: (let ((.cse3 (= 0 (mod ~x$w_buff0_used~0_In-665035206 256))) (.cse2 (= (mod ~x$r_buff0_thd2~0_In-665035206 256) 0)) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In-665035206 256))) (.cse0 (= (mod ~x$r_buff1_thd2~0_In-665035206 256) 0))) (or (and (= |P1Thread1of1ForFork1_#t~ite12_Out-665035206| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse1 .cse0) (= |P1Thread1of1ForFork1_#t~ite12_Out-665035206| ~x$w_buff1_used~0_In-665035206)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-665035206, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-665035206, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-665035206, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-665035206} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-665035206, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-665035206, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-665035206|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-665035206, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-665035206} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 18:52:26,239 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L765-->L766: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In2071219688 256))) (.cse2 (= ~x$r_buff0_thd2~0_Out2071219688 ~x$r_buff0_thd2~0_In2071219688)) (.cse1 (= (mod ~x$r_buff0_thd2~0_In2071219688 256) 0))) (or (and (not .cse0) (= ~x$r_buff0_thd2~0_Out2071219688 0) (not .cse1)) (and .cse2 .cse0) (and .cse2 .cse1))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2071219688, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2071219688} OutVars{P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out2071219688|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out2071219688, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2071219688} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-12-07 18:52:26,239 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L766-->L766-2: Formula: (let ((.cse3 (= 0 (mod ~x$r_buff1_thd2~0_In-705960470 256))) (.cse2 (= (mod ~x$w_buff1_used~0_In-705960470 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In-705960470 256))) (.cse1 (= (mod ~x$r_buff0_thd2~0_In-705960470 256) 0))) (or (and (= |P1Thread1of1ForFork1_#t~ite14_Out-705960470| ~x$r_buff1_thd2~0_In-705960470) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= |P1Thread1of1ForFork1_#t~ite14_Out-705960470| 0)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-705960470, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-705960470, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-705960470, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-705960470} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-705960470, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-705960470, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-705960470, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-705960470|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-705960470} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 18:52:26,239 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L766-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0) (= v_~x$r_buff1_thd2~0_162 |v_P1Thread1of1ForFork1_#t~ite14_40|) (= (+ v_~__unbuffered_cnt~0_93 1) v_~__unbuffered_cnt~0_92)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_93, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_40|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_162, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_92, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_39|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 18:52:26,239 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L809-1-->L815: Formula: (and (= v_~main$tmp_guard0~0_6 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= 0 (mod v_~main$tmp_guard0~0_6 256)))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:52:26,239 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L815-2-->L815-5: Formula: (let ((.cse2 (= |ULTIMATE.start_main_#t~ite25_Out552553393| |ULTIMATE.start_main_#t~ite24_Out552553393|)) (.cse0 (= (mod ~x$r_buff1_thd0~0_In552553393 256) 0)) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In552553393 256)))) (or (and (= |ULTIMATE.start_main_#t~ite24_Out552553393| ~x$w_buff1~0_In552553393) (not .cse0) (not .cse1) .cse2) (and (= ~x~0_In552553393 |ULTIMATE.start_main_#t~ite24_Out552553393|) .cse2 (or .cse0 .cse1)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In552553393, ~x$w_buff1_used~0=~x$w_buff1_used~0_In552553393, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In552553393, ~x~0=~x~0_In552553393} OutVars{~x$w_buff1~0=~x$w_buff1~0_In552553393, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out552553393|, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out552553393|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In552553393, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In552553393, ~x~0=~x~0_In552553393} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 18:52:26,239 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L816-->L816-2: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In-1688068347 256) 0)) (.cse0 (= (mod ~x$r_buff0_thd0~0_In-1688068347 256) 0))) (or (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In-1688068347 |ULTIMATE.start_main_#t~ite26_Out-1688068347|)) (and (= |ULTIMATE.start_main_#t~ite26_Out-1688068347| 0) (not .cse1) (not .cse0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1688068347, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1688068347} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1688068347, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-1688068347|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1688068347} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 18:52:26,240 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L817-->L817-2: Formula: (let ((.cse3 (= (mod ~x$r_buff0_thd0~0_In1484705826 256) 0)) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In1484705826 256))) (.cse1 (= (mod ~x$w_buff1_used~0_In1484705826 256) 0)) (.cse0 (= (mod ~x$r_buff1_thd0~0_In1484705826 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite27_Out1484705826| ~x$w_buff1_used~0_In1484705826)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0))) (= |ULTIMATE.start_main_#t~ite27_Out1484705826| 0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1484705826, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1484705826, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1484705826, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1484705826} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1484705826, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1484705826, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out1484705826|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1484705826, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1484705826} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 18:52:26,240 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L818-->L818-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-1322811465 256))) (.cse0 (= 0 (mod ~x$r_buff0_thd0~0_In-1322811465 256)))) (or (and (= 0 |ULTIMATE.start_main_#t~ite28_Out-1322811465|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~x$r_buff0_thd0~0_In-1322811465 |ULTIMATE.start_main_#t~ite28_Out-1322811465|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1322811465, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1322811465} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1322811465, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out-1322811465|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1322811465} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 18:52:26,240 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L819-->L819-2: Formula: (let ((.cse3 (= (mod ~x$r_buff1_thd0~0_In817237809 256) 0)) (.cse2 (= (mod ~x$w_buff1_used~0_In817237809 256) 0)) (.cse1 (= (mod ~x$r_buff0_thd0~0_In817237809 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In817237809 256)))) (or (and (= ~x$r_buff1_thd0~0_In817237809 |ULTIMATE.start_main_#t~ite29_Out817237809|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |ULTIMATE.start_main_#t~ite29_Out817237809| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In817237809, ~x$w_buff1_used~0=~x$w_buff1_used~0_In817237809, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In817237809, ~x$w_buff0_used~0=~x$w_buff0_used~0_In817237809} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In817237809, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out817237809|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In817237809, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In817237809, ~x$w_buff0_used~0=~x$w_buff0_used~0_In817237809} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 18:52:26,243 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L831-->L832: Formula: (and (= v_~x$r_buff0_thd0~0_112 v_~x$r_buff0_thd0~0_111) (not (= (mod v_~weak$$choice2~0_23 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_112, ~weak$$choice2~0=v_~weak$$choice2~0_23} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_111, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_6|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_10|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_6|, ~weak$$choice2~0=v_~weak$$choice2~0_23} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 18:52:26,243 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L834-->L837-1: Formula: (and (= (mod v_~main$tmp_guard1~0_13 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (not (= (mod v_~x$flush_delayed~0_23 256) 0)) (= v_~x$mem_tmp~0_13 v_~x~0_153) (= v_~x$flush_delayed~0_22 0)) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_23, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_13, ~x$mem_tmp~0=v_~x$mem_tmp~0_13} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_18|, ~x$flush_delayed~0=v_~x$flush_delayed~0_22, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_13, ~x$mem_tmp~0=v_~x$mem_tmp~0_13, ~x~0=v_~x~0_153, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ~x$flush_delayed~0, ~x~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:52:26,243 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L837-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:52:26,292 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 06:52:26 BasicIcfg [2019-12-07 18:52:26,292 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 18:52:26,292 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:52:26,292 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:52:26,293 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:52:26,293 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:51:33" (3/4) ... [2019-12-07 18:52:26,294 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 18:52:26,295 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] ULTIMATE.startENTRY-->L805: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= |v_#valid_53| (store .cse0 |v_ULTIMATE.start_main_~#t1810~0.base_20| 1)) (= 0 v_~x~0_194) (= 0 v_~x$r_buff0_thd2~0_213) (= 0 v_~weak$$choice0~0_14) (= v_~x$mem_tmp~0_19 0) (= 0 v_~x$w_buff0~0_268) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t1810~0.base_20| 4)) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t1810~0.base_20|) (= 0 v_~x$r_buff1_thd2~0_212) (= v_~x$r_buff1_thd0~0_297 0) (< 0 |v_#StackHeapBarrier_17|) (= 0 v_~x$read_delayed_var~0.base_7) (= v_~x$r_buff1_thd1~0_187 0) (= |v_ULTIMATE.start_main_~#t1810~0.offset_17| 0) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1810~0.base_20| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1810~0.base_20|) |v_ULTIMATE.start_main_~#t1810~0.offset_17| 0)) |v_#memory_int_21|) (= v_~x$r_buff0_thd0~0_372 0) (= v_~y~0_143 0) (= 0 v_~x$read_delayed~0_6) (= v_~__unbuffered_cnt~0_155 0) (= 0 v_~x$w_buff1~0_230) (= 0 |v_#NULL.base_4|) (= 0 v_~__unbuffered_p0_EAX~0_24) (= 0 v_~x$r_buff1_thd3~0_195) (= 0 v_~x$r_buff0_thd3~0_123) (= |v_#NULL.offset_4| 0) (= 0 v_~x$w_buff1_used~0_504) (= 0 v_~x$read_delayed_var~0.offset_7) (= (select .cse0 |v_ULTIMATE.start_main_~#t1810~0.base_20|) 0) (= v_~x$r_buff0_thd1~0_120 0) (= 0 v_~__unbuffered_p2_EAX~0_22) (= v_~x$flush_delayed~0_34 0) (= v_~main$tmp_guard0~0_24 0) (= v_~weak$$choice2~0_110 0) (= 0 v_~x$w_buff0_used~0_807) (= v_~main$tmp_guard1~0_22 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_22|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_21|, ~x$w_buff0~0=v_~x$w_buff0~0_268, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_27|, ~x$flush_delayed~0=v_~x$flush_delayed~0_34, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_39|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_29|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_45|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_187, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_123, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_50|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_36|, ULTIMATE.start_main_~#t1810~0.offset=|v_ULTIMATE.start_main_~#t1810~0.offset_17|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_45|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_32|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_24, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_22, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_372, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_37|, ~x$w_buff1~0=v_~x$w_buff1~0_230, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_504, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_212, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_48|, ULTIMATE.start_main_~#t1811~0.base=|v_ULTIMATE.start_main_~#t1811~0.base_21|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_111|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_7, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_~#t1810~0.base=|v_ULTIMATE.start_main_~#t1810~0.base_20|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_155, ~x~0=v_~x~0_194, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_120, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_33|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_31|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_29|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_195, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_22, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_125|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_17|, ~x$mem_tmp~0=v_~x$mem_tmp~0_19, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_25|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_31|, ULTIMATE.start_main_~#t1812~0.base=|v_ULTIMATE.start_main_~#t1812~0.base_20|, ~y~0=v_~y~0_143, ULTIMATE.start_main_~#t1811~0.offset=|v_ULTIMATE.start_main_~#t1811~0.offset_17|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_10|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_23|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_25|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_48|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_297, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_213, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_59|, ULTIMATE.start_main_~#t1812~0.offset=|v_ULTIMATE.start_main_~#t1812~0.offset_16|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_38|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_807, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_32|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_7, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_21|, ~weak$$choice2~0=v_~weak$$choice2~0_110, ~x$read_delayed~0=v_~x$read_delayed~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ~x$w_buff0~0, ULTIMATE.start_main_#t~ite28, ~x$flush_delayed~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ~x$r_buff1_thd1~0, ~x$r_buff0_thd3~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_~#t1810~0.offset, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~__unbuffered_p0_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ~x$w_buff1~0, ULTIMATE.start_main_#t~ite35, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_~#t1811~0.base, ULTIMATE.start_main_#t~ite33, ~x$read_delayed_var~0.base, ~weak$$choice0~0, ULTIMATE.start_main_~#t1810~0.base, ULTIMATE.start_main_#t~ite40, ~__unbuffered_cnt~0, ~x~0, ~x$r_buff0_thd1~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~x$r_buff1_thd3~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~x$mem_tmp~0, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ULTIMATE.start_main_~#t1812~0.base, ~y~0, ULTIMATE.start_main_~#t1811~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_~#t1812~0.offset, #NULL.base, ULTIMATE.start_main_#t~ite34, ~x$w_buff0_used~0, ULTIMATE.start_main_#t~ite41, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_#res, #valid, #memory_int, ~weak$$choice2~0, ~x$read_delayed~0] because there is no mapped edge [2019-12-07 18:52:26,295 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L805-1-->L807: Formula: (and (not (= |v_ULTIMATE.start_main_~#t1811~0.base_11| 0)) (= (store |v_#valid_32| |v_ULTIMATE.start_main_~#t1811~0.base_11| 1) |v_#valid_31|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1811~0.base_11| 4)) (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t1811~0.base_11|)) (= |v_ULTIMATE.start_main_~#t1811~0.offset_10| 0) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1811~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1811~0.base_11|) |v_ULTIMATE.start_main_~#t1811~0.offset_10| 1)) |v_#memory_int_13|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1811~0.base_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_6|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1811~0.base=|v_ULTIMATE.start_main_~#t1811~0.base_11|, ULTIMATE.start_main_~#t1811~0.offset=|v_ULTIMATE.start_main_~#t1811~0.offset_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1811~0.base, ULTIMATE.start_main_~#t1811~0.offset] because there is no mapped edge [2019-12-07 18:52:26,295 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L807-1-->L809: Formula: (and (= 0 (select |v_#valid_28| |v_ULTIMATE.start_main_~#t1812~0.base_9|)) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t1812~0.base_9|) (= (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t1812~0.base_9| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t1812~0.base_9|) |v_ULTIMATE.start_main_~#t1812~0.offset_8| 2)) |v_#memory_int_9|) (not (= 0 |v_ULTIMATE.start_main_~#t1812~0.base_9|)) (= |v_#valid_27| (store |v_#valid_28| |v_ULTIMATE.start_main_~#t1812~0.base_9| 1)) (= |v_ULTIMATE.start_main_~#t1812~0.offset_8| 0) (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t1812~0.base_9| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_28|, #memory_int=|v_#memory_int_10|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_27|, #memory_int=|v_#memory_int_9|, ULTIMATE.start_main_~#t1812~0.base=|v_ULTIMATE.start_main_~#t1812~0.base_9|, #length=|v_#length_13|, ULTIMATE.start_main_~#t1812~0.offset=|v_ULTIMATE.start_main_~#t1812~0.offset_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, ULTIMATE.start_main_~#t1812~0.base, #length, ULTIMATE.start_main_~#t1812~0.offset] because there is no mapped edge [2019-12-07 18:52:26,295 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] P1ENTRY-->L4-3: Formula: (and (not (= 0 v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11)) (= v_P1Thread1of1ForFork1_~arg.offset_9 |v_P1Thread1of1ForFork1_#in~arg.offset_11|) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9| v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11) (= 1 v_~x$w_buff0_used~0_98) (= 2 v_~x$w_buff0~0_31) (= v_P1Thread1of1ForFork1_~arg.base_9 |v_P1Thread1of1ForFork1_#in~arg.base_11|) (= v_~x$w_buff1_used~0_55 v_~x$w_buff0_used~0_99) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9| (ite (not (and (not (= (mod v_~x$w_buff0_used~0_98 256) 0)) (not (= 0 (mod v_~x$w_buff1_used~0_55 256))))) 1 0)) (= v_~x$w_buff0~0_32 v_~x$w_buff1~0_21)) InVars {~x$w_buff0~0=v_~x$w_buff0~0_32, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_11|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_11|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_99} OutVars{P1Thread1of1ForFork1___VERIFIER_assert_~expression=v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11, ~x$w_buff0~0=v_~x$w_buff0~0_31, P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_9, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression=|v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9|, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_9, ~x$w_buff1~0=v_~x$w_buff1~0_21, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_11|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_11|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_55, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_98} AuxVars[] AssignedVars[P1Thread1of1ForFork1___VERIFIER_assert_~expression, ~x$w_buff0~0, P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression, P1Thread1of1ForFork1_~arg.base, ~x$w_buff1~0, ~x$w_buff1_used~0, ~x$w_buff0_used~0] because there is no mapped edge [2019-12-07 18:52:26,296 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L782-2-->L782-4: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff1_used~0_In1095061724 256))) (.cse0 (= 0 (mod ~x$r_buff1_thd3~0_In1095061724 256)))) (or (and (or .cse0 .cse1) (= ~x~0_In1095061724 |P2Thread1of1ForFork2_#t~ite15_Out1095061724|)) (and (not .cse1) (= |P2Thread1of1ForFork2_#t~ite15_Out1095061724| ~x$w_buff1~0_In1095061724) (not .cse0)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In1095061724, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1095061724, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1095061724, ~x~0=~x~0_In1095061724} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out1095061724|, ~x$w_buff1~0=~x$w_buff1~0_In1095061724, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1095061724, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1095061724, ~x~0=~x~0_In1095061724} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 18:52:26,296 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L782-4-->L783: Formula: (= v_~x~0_20 |v_P2Thread1of1ForFork2_#t~ite15_10|) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_10|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_9|, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_5|, ~x~0=v_~x~0_20} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, P2Thread1of1ForFork2_#t~ite16, ~x~0] because there is no mapped edge [2019-12-07 18:52:26,296 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L783-->L783-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In-908373812 256))) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In-908373812 256)))) (or (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In-908373812 |P2Thread1of1ForFork2_#t~ite17_Out-908373812|)) (and (not .cse0) (not .cse1) (= 0 |P2Thread1of1ForFork2_#t~ite17_Out-908373812|)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-908373812, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-908373812} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-908373812, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out-908373812|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-908373812} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 18:52:26,297 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L784-->L784-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff1_thd3~0_In-650695679 256))) (.cse0 (= 0 (mod ~x$w_buff1_used~0_In-650695679 256))) (.cse3 (= (mod ~x$w_buff0_used~0_In-650695679 256) 0)) (.cse2 (= 0 (mod ~x$r_buff0_thd3~0_In-650695679 256)))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite18_Out-650695679|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse3 .cse2) (= ~x$w_buff1_used~0_In-650695679 |P2Thread1of1ForFork2_#t~ite18_Out-650695679|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-650695679, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-650695679, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-650695679, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-650695679} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-650695679, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-650695679, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-650695679, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-650695679|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-650695679} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 18:52:26,297 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L733-2-->L733-5: Formula: (let ((.cse0 (= |P0Thread1of1ForFork0_#t~ite4_Out-1623345393| |P0Thread1of1ForFork0_#t~ite3_Out-1623345393|)) (.cse2 (= (mod ~x$r_buff1_thd1~0_In-1623345393 256) 0)) (.cse1 (= (mod ~x$w_buff1_used~0_In-1623345393 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite3_Out-1623345393| ~x~0_In-1623345393) .cse0 (or .cse1 .cse2)) (and .cse0 (= ~x$w_buff1~0_In-1623345393 |P0Thread1of1ForFork0_#t~ite3_Out-1623345393|) (not .cse2) (not .cse1)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-1623345393, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1623345393, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1623345393, ~x~0=~x~0_In-1623345393} OutVars{P0Thread1of1ForFork0_#t~ite3=|P0Thread1of1ForFork0_#t~ite3_Out-1623345393|, P0Thread1of1ForFork0_#t~ite4=|P0Thread1of1ForFork0_#t~ite4_Out-1623345393|, ~x$w_buff1~0=~x$w_buff1~0_In-1623345393, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1623345393, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1623345393, ~x~0=~x~0_In-1623345393} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite3, P0Thread1of1ForFork0_#t~ite4] because there is no mapped edge [2019-12-07 18:52:26,297 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [774] [774] L734-->L734-2: Formula: (let ((.cse0 (= (mod ~x$r_buff0_thd1~0_In-798918919 256) 0)) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In-798918919 256)))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite5_Out-798918919| 0)) (and (= ~x$w_buff0_used~0_In-798918919 |P0Thread1of1ForFork0_#t~ite5_Out-798918919|) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-798918919, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-798918919} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-798918919|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-798918919, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-798918919} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 18:52:26,297 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L735-->L735-2: Formula: (let ((.cse3 (= 0 (mod ~x$w_buff0_used~0_In119740061 256))) (.cse2 (= (mod ~x$r_buff0_thd1~0_In119740061 256) 0)) (.cse0 (= (mod ~x$r_buff1_thd1~0_In119740061 256) 0)) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In119740061 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork0_#t~ite6_Out119740061|)) (and (= ~x$w_buff1_used~0_In119740061 |P0Thread1of1ForFork0_#t~ite6_Out119740061|) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In119740061, ~x$w_buff1_used~0=~x$w_buff1_used~0_In119740061, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In119740061, ~x$w_buff0_used~0=~x$w_buff0_used~0_In119740061} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out119740061|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In119740061, ~x$w_buff1_used~0=~x$w_buff1_used~0_In119740061, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In119740061, ~x$w_buff0_used~0=~x$w_buff0_used~0_In119740061} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 18:52:26,298 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L785-->L785-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In-1542421039 256))) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In-1542421039 256)))) (or (and (or .cse0 .cse1) (= ~x$r_buff0_thd3~0_In-1542421039 |P2Thread1of1ForFork2_#t~ite19_Out-1542421039|)) (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork2_#t~ite19_Out-1542421039| 0)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1542421039, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1542421039} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1542421039, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-1542421039|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1542421039} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 18:52:26,298 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L786-->L786-2: Formula: (let ((.cse3 (= 0 (mod ~x$r_buff0_thd3~0_In-1080119250 256))) (.cse2 (= (mod ~x$w_buff0_used~0_In-1080119250 256) 0)) (.cse0 (= (mod ~x$w_buff1_used~0_In-1080119250 256) 0)) (.cse1 (= (mod ~x$r_buff1_thd3~0_In-1080119250 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~x$r_buff1_thd3~0_In-1080119250 |P2Thread1of1ForFork2_#t~ite20_Out-1080119250|)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= 0 |P2Thread1of1ForFork2_#t~ite20_Out-1080119250|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1080119250, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1080119250, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1080119250, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1080119250} OutVars{P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-1080119250|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1080119250, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1080119250, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1080119250, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1080119250} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 18:52:26,298 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L786-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74) (= |v_P2Thread1of1ForFork2_#t~ite20_52| v_~x$r_buff1_thd3~0_147)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_52|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_51|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_147, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~x$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 18:52:26,298 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L736-->L736-2: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In-1954027416 256) 0)) (.cse0 (= (mod ~x$r_buff0_thd1~0_In-1954027416 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite7_Out-1954027416| 0) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |P0Thread1of1ForFork0_#t~ite7_Out-1954027416| ~x$r_buff0_thd1~0_In-1954027416)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1954027416, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1954027416} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1954027416, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out-1954027416|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1954027416} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-12-07 18:52:26,299 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L737-->L737-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff1_thd1~0_In-1041113883 256))) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In-1041113883 256))) (.cse2 (= 0 (mod ~x$r_buff0_thd1~0_In-1041113883 256))) (.cse3 (= 0 (mod ~x$w_buff0_used~0_In-1041113883 256)))) (or (and (= 0 |P0Thread1of1ForFork0_#t~ite8_Out-1041113883|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (= |P0Thread1of1ForFork0_#t~ite8_Out-1041113883| ~x$r_buff1_thd1~0_In-1041113883) (or .cse2 .cse3)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1041113883, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1041113883, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1041113883, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1041113883} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1041113883, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-1041113883|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1041113883, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1041113883, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1041113883} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 18:52:26,299 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L737-2-->P0EXIT: Formula: (and (= v_~x$r_buff1_thd1~0_61 |v_P0Thread1of1ForFork0_#t~ite8_24|) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_45 1) v_~__unbuffered_cnt~0_44)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_45} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_23|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_44, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_61} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, ~x$r_buff1_thd1~0] because there is no mapped edge [2019-12-07 18:52:26,299 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L763-->L763-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff0_thd2~0_In-915202456 256))) (.cse1 (= (mod ~x$w_buff0_used~0_In-915202456 256) 0))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out-915202456| 0)) (and (= ~x$w_buff0_used~0_In-915202456 |P1Thread1of1ForFork1_#t~ite11_Out-915202456|) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-915202456, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-915202456} OutVars{P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out-915202456|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-915202456, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-915202456} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 18:52:26,299 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L764-->L764-2: Formula: (let ((.cse3 (= 0 (mod ~x$w_buff0_used~0_In-665035206 256))) (.cse2 (= (mod ~x$r_buff0_thd2~0_In-665035206 256) 0)) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In-665035206 256))) (.cse0 (= (mod ~x$r_buff1_thd2~0_In-665035206 256) 0))) (or (and (= |P1Thread1of1ForFork1_#t~ite12_Out-665035206| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse1 .cse0) (= |P1Thread1of1ForFork1_#t~ite12_Out-665035206| ~x$w_buff1_used~0_In-665035206)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-665035206, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-665035206, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-665035206, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-665035206} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-665035206, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-665035206, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-665035206|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-665035206, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-665035206} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 18:52:26,300 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L765-->L766: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In2071219688 256))) (.cse2 (= ~x$r_buff0_thd2~0_Out2071219688 ~x$r_buff0_thd2~0_In2071219688)) (.cse1 (= (mod ~x$r_buff0_thd2~0_In2071219688 256) 0))) (or (and (not .cse0) (= ~x$r_buff0_thd2~0_Out2071219688 0) (not .cse1)) (and .cse2 .cse0) (and .cse2 .cse1))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2071219688, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2071219688} OutVars{P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out2071219688|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out2071219688, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2071219688} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-12-07 18:52:26,300 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L766-->L766-2: Formula: (let ((.cse3 (= 0 (mod ~x$r_buff1_thd2~0_In-705960470 256))) (.cse2 (= (mod ~x$w_buff1_used~0_In-705960470 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In-705960470 256))) (.cse1 (= (mod ~x$r_buff0_thd2~0_In-705960470 256) 0))) (or (and (= |P1Thread1of1ForFork1_#t~ite14_Out-705960470| ~x$r_buff1_thd2~0_In-705960470) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= |P1Thread1of1ForFork1_#t~ite14_Out-705960470| 0)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-705960470, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-705960470, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-705960470, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-705960470} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-705960470, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-705960470, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-705960470, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-705960470|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-705960470} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 18:52:26,300 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L766-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0) (= v_~x$r_buff1_thd2~0_162 |v_P1Thread1of1ForFork1_#t~ite14_40|) (= (+ v_~__unbuffered_cnt~0_93 1) v_~__unbuffered_cnt~0_92)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_93, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_40|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_162, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_92, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_39|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 18:52:26,300 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L809-1-->L815: Formula: (and (= v_~main$tmp_guard0~0_6 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= 0 (mod v_~main$tmp_guard0~0_6 256)))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:52:26,300 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L815-2-->L815-5: Formula: (let ((.cse2 (= |ULTIMATE.start_main_#t~ite25_Out552553393| |ULTIMATE.start_main_#t~ite24_Out552553393|)) (.cse0 (= (mod ~x$r_buff1_thd0~0_In552553393 256) 0)) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In552553393 256)))) (or (and (= |ULTIMATE.start_main_#t~ite24_Out552553393| ~x$w_buff1~0_In552553393) (not .cse0) (not .cse1) .cse2) (and (= ~x~0_In552553393 |ULTIMATE.start_main_#t~ite24_Out552553393|) .cse2 (or .cse0 .cse1)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In552553393, ~x$w_buff1_used~0=~x$w_buff1_used~0_In552553393, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In552553393, ~x~0=~x~0_In552553393} OutVars{~x$w_buff1~0=~x$w_buff1~0_In552553393, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out552553393|, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out552553393|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In552553393, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In552553393, ~x~0=~x~0_In552553393} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 18:52:26,300 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L816-->L816-2: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In-1688068347 256) 0)) (.cse0 (= (mod ~x$r_buff0_thd0~0_In-1688068347 256) 0))) (or (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In-1688068347 |ULTIMATE.start_main_#t~ite26_Out-1688068347|)) (and (= |ULTIMATE.start_main_#t~ite26_Out-1688068347| 0) (not .cse1) (not .cse0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1688068347, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1688068347} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1688068347, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-1688068347|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1688068347} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 18:52:26,301 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L817-->L817-2: Formula: (let ((.cse3 (= (mod ~x$r_buff0_thd0~0_In1484705826 256) 0)) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In1484705826 256))) (.cse1 (= (mod ~x$w_buff1_used~0_In1484705826 256) 0)) (.cse0 (= (mod ~x$r_buff1_thd0~0_In1484705826 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite27_Out1484705826| ~x$w_buff1_used~0_In1484705826)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0))) (= |ULTIMATE.start_main_#t~ite27_Out1484705826| 0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1484705826, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1484705826, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1484705826, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1484705826} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1484705826, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1484705826, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out1484705826|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1484705826, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1484705826} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 18:52:26,301 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L818-->L818-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-1322811465 256))) (.cse0 (= 0 (mod ~x$r_buff0_thd0~0_In-1322811465 256)))) (or (and (= 0 |ULTIMATE.start_main_#t~ite28_Out-1322811465|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~x$r_buff0_thd0~0_In-1322811465 |ULTIMATE.start_main_#t~ite28_Out-1322811465|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1322811465, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1322811465} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1322811465, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out-1322811465|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1322811465} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 18:52:26,301 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L819-->L819-2: Formula: (let ((.cse3 (= (mod ~x$r_buff1_thd0~0_In817237809 256) 0)) (.cse2 (= (mod ~x$w_buff1_used~0_In817237809 256) 0)) (.cse1 (= (mod ~x$r_buff0_thd0~0_In817237809 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In817237809 256)))) (or (and (= ~x$r_buff1_thd0~0_In817237809 |ULTIMATE.start_main_#t~ite29_Out817237809|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |ULTIMATE.start_main_#t~ite29_Out817237809| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In817237809, ~x$w_buff1_used~0=~x$w_buff1_used~0_In817237809, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In817237809, ~x$w_buff0_used~0=~x$w_buff0_used~0_In817237809} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In817237809, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out817237809|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In817237809, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In817237809, ~x$w_buff0_used~0=~x$w_buff0_used~0_In817237809} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 18:52:26,304 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L831-->L832: Formula: (and (= v_~x$r_buff0_thd0~0_112 v_~x$r_buff0_thd0~0_111) (not (= (mod v_~weak$$choice2~0_23 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_112, ~weak$$choice2~0=v_~weak$$choice2~0_23} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_111, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_6|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_10|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_6|, ~weak$$choice2~0=v_~weak$$choice2~0_23} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 18:52:26,304 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L834-->L837-1: Formula: (and (= (mod v_~main$tmp_guard1~0_13 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (not (= (mod v_~x$flush_delayed~0_23 256) 0)) (= v_~x$mem_tmp~0_13 v_~x~0_153) (= v_~x$flush_delayed~0_22 0)) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_23, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_13, ~x$mem_tmp~0=v_~x$mem_tmp~0_13} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_18|, ~x$flush_delayed~0=v_~x$flush_delayed~0_22, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_13, ~x$mem_tmp~0=v_~x$mem_tmp~0_13, ~x~0=v_~x~0_153, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ~x$flush_delayed~0, ~x~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:52:26,304 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L837-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:52:26,356 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_ce97f955-5c2b-4ad2-9018-d826432996c1/bin/uautomizer/witness.graphml [2019-12-07 18:52:26,356 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:52:26,357 INFO L168 Benchmark]: Toolchain (without parser) took 53752.37 ms. Allocated memory was 1.0 GB in the beginning and 6.8 GB in the end (delta: 5.7 GB). Free memory was 934.0 MB in the beginning and 2.9 GB in the end (delta: -2.0 GB). Peak memory consumption was 3.8 GB. Max. memory is 11.5 GB. [2019-12-07 18:52:26,357 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:52:26,357 INFO L168 Benchmark]: CACSL2BoogieTranslator took 458.25 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 99.1 MB). Free memory was 934.0 MB in the beginning and 1.1 GB in the end (delta: -136.9 MB). Peak memory consumption was 23.6 MB. Max. memory is 11.5 GB. [2019-12-07 18:52:26,358 INFO L168 Benchmark]: Boogie Procedure Inliner took 38.62 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:52:26,358 INFO L168 Benchmark]: Boogie Preprocessor took 26.15 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:52:26,358 INFO L168 Benchmark]: RCFGBuilder took 417.13 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.4 MB). Peak memory consumption was 55.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:52:26,358 INFO L168 Benchmark]: TraceAbstraction took 52742.36 ms. Allocated memory was 1.1 GB in the beginning and 6.8 GB in the end (delta: 5.6 GB). Free memory was 1.0 GB in the beginning and 2.9 GB in the end (delta: -1.9 GB). Peak memory consumption was 3.7 GB. Max. memory is 11.5 GB. [2019-12-07 18:52:26,358 INFO L168 Benchmark]: Witness Printer took 63.44 ms. Allocated memory is still 6.8 GB. Free memory was 2.9 GB in the beginning and 2.9 GB in the end (delta: 14.8 MB). Peak memory consumption was 14.8 MB. Max. memory is 11.5 GB. [2019-12-07 18:52:26,360 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 458.25 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 99.1 MB). Free memory was 934.0 MB in the beginning and 1.1 GB in the end (delta: -136.9 MB). Peak memory consumption was 23.6 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 38.62 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.15 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 417.13 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.4 MB). Peak memory consumption was 55.4 MB. Max. memory is 11.5 GB. * TraceAbstraction took 52742.36 ms. Allocated memory was 1.1 GB in the beginning and 6.8 GB in the end (delta: 5.6 GB). Free memory was 1.0 GB in the beginning and 2.9 GB in the end (delta: -1.9 GB). Peak memory consumption was 3.7 GB. Max. memory is 11.5 GB. * Witness Printer took 63.44 ms. Allocated memory is still 6.8 GB. Free memory was 2.9 GB in the beginning and 2.9 GB in the end (delta: 14.8 MB). Peak memory consumption was 14.8 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.0s, 174 ProgramPointsBefore, 94 ProgramPointsAfterwards, 211 TransitionsBefore, 106 TransitionsAfterwards, 17074 CoEnabledTransitionPairs, 7 FixpointIterations, 31 TrivialSequentialCompositions, 43 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 37 ConcurrentYvCompositions, 29 ChoiceCompositions, 6159 VarBasedMoverChecksPositive, 253 VarBasedMoverChecksNegative, 78 SemBasedMoverChecksPositive, 250 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.8s, 0 MoverChecksTotal, 78277 CheckedPairsTotal, 111 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L805] FCALL, FORK 0 pthread_create(&t1810, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L807] FCALL, FORK 0 pthread_create(&t1811, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L809] FCALL, FORK 0 pthread_create(&t1812, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L752] 2 x$r_buff1_thd0 = x$r_buff0_thd0 [L753] 2 x$r_buff1_thd1 = x$r_buff0_thd1 [L754] 2 x$r_buff1_thd2 = x$r_buff0_thd2 [L755] 2 x$r_buff1_thd3 = x$r_buff0_thd3 [L756] 2 x$r_buff0_thd2 = (_Bool)1 [L759] 2 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L776] 3 __unbuffered_p2_EAX = y [L779] 3 y = 2 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L727] 1 __unbuffered_p0_EAX = y [L730] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L782] 3 x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd3 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L733] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L783] 3 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$w_buff0_used [L733] 1 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L734] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L784] 3 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd3 || x$w_buff1_used && x$r_buff1_thd3 ? (_Bool)0 : x$w_buff1_used [L785] 3 x$r_buff0_thd3 = x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$r_buff0_thd3 [L762] EXPR 2 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L735] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L736] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L762] 2 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L763] 2 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L764] 2 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L815] EXPR 0 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L815] 0 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L816] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L817] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L818] 0 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L819] 0 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L822] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L823] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L824] 0 x$flush_delayed = weak$$choice2 [L825] 0 x$mem_tmp = x VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L826] EXPR 0 !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L826] 0 x = !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) [L827] EXPR 0 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L827] 0 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) [L828] EXPR 0 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L828] 0 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) [L829] EXPR 0 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L829] 0 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) [L830] EXPR 0 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L830] 0 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L832] EXPR 0 weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L832] 0 x$r_buff1_thd0 = weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L833] 0 main$tmp_guard1 = !(x == 2 && y == 2 && __unbuffered_p0_EAX == 2 && __unbuffered_p2_EAX == 1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 165 locations, 2 error locations. Result: UNSAFE, OverallTime: 52.5s, OverallIterations: 19, TraceHistogramMax: 1, AutomataDifference: 7.5s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 2527 SDtfs, 2010 SDslu, 4347 SDs, 0 SdLazy, 2508 SolverSat, 110 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 120 GetRequests, 32 SyntacticMatches, 16 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 79 ImplicationChecksByTransitivity, 0.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=183279occurred in iteration=3, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 27.1s AutomataMinimizationTime, 18 MinimizatonAttempts, 74697 StatesRemovedByMinimization, 15 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 0.7s InterpolantComputationTime, 915 NumberOfCodeBlocks, 915 NumberOfCodeBlocksAsserted, 19 NumberOfCheckSat, 829 ConstructedInterpolants, 0 QuantifiedInterpolants, 158874 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 18 InterpolantComputations, 18 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...