./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe001_rmo.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_dded0f1c-e543-47fa-8557-549916ecea08/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_dded0f1c-e543-47fa-8557-549916ecea08/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_dded0f1c-e543-47fa-8557-549916ecea08/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_dded0f1c-e543-47fa-8557-549916ecea08/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe001_rmo.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_dded0f1c-e543-47fa-8557-549916ecea08/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_dded0f1c-e543-47fa-8557-549916ecea08/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 08443d31ebe478b4c74a8992db9e7945c162a284 .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 15:19:36,321 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 15:19:36,322 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 15:19:36,329 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 15:19:36,330 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 15:19:36,330 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 15:19:36,331 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 15:19:36,333 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 15:19:36,334 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 15:19:36,335 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 15:19:36,336 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 15:19:36,336 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 15:19:36,337 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 15:19:36,337 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 15:19:36,338 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 15:19:36,339 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 15:19:36,339 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 15:19:36,340 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 15:19:36,341 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 15:19:36,343 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 15:19:36,344 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 15:19:36,345 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 15:19:36,346 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 15:19:36,346 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 15:19:36,348 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 15:19:36,348 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 15:19:36,348 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 15:19:36,349 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 15:19:36,349 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 15:19:36,350 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 15:19:36,350 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 15:19:36,350 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 15:19:36,351 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 15:19:36,351 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 15:19:36,352 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 15:19:36,352 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 15:19:36,352 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 15:19:36,353 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 15:19:36,353 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 15:19:36,353 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 15:19:36,354 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 15:19:36,354 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_dded0f1c-e543-47fa-8557-549916ecea08/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 15:19:36,364 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 15:19:36,364 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 15:19:36,365 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 15:19:36,365 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 15:19:36,365 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 15:19:36,365 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 15:19:36,365 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 15:19:36,365 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 15:19:36,365 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 15:19:36,366 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 15:19:36,366 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 15:19:36,366 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 15:19:36,366 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 15:19:36,366 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 15:19:36,366 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 15:19:36,366 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 15:19:36,366 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 15:19:36,367 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 15:19:36,367 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 15:19:36,367 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 15:19:36,367 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 15:19:36,367 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 15:19:36,367 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 15:19:36,367 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 15:19:36,368 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 15:19:36,368 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 15:19:36,368 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 15:19:36,368 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 15:19:36,368 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 15:19:36,368 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_dded0f1c-e543-47fa-8557-549916ecea08/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 08443d31ebe478b4c74a8992db9e7945c162a284 [2019-12-07 15:19:36,474 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 15:19:36,484 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 15:19:36,487 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 15:19:36,488 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 15:19:36,488 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 15:19:36,489 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_dded0f1c-e543-47fa-8557-549916ecea08/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe001_rmo.opt.i [2019-12-07 15:19:36,535 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_dded0f1c-e543-47fa-8557-549916ecea08/bin/uautomizer/data/43414d59d/c9a7309b90d04b07b465bfa150b55264/FLAG9267fb1ca [2019-12-07 15:19:36,948 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 15:19:36,949 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_dded0f1c-e543-47fa-8557-549916ecea08/sv-benchmarks/c/pthread-wmm/safe001_rmo.opt.i [2019-12-07 15:19:36,961 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_dded0f1c-e543-47fa-8557-549916ecea08/bin/uautomizer/data/43414d59d/c9a7309b90d04b07b465bfa150b55264/FLAG9267fb1ca [2019-12-07 15:19:37,296 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_dded0f1c-e543-47fa-8557-549916ecea08/bin/uautomizer/data/43414d59d/c9a7309b90d04b07b465bfa150b55264 [2019-12-07 15:19:37,298 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 15:19:37,299 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 15:19:37,299 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 15:19:37,299 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 15:19:37,301 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 15:19:37,302 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 03:19:37" (1/1) ... [2019-12-07 15:19:37,304 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@49c89d2f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:19:37, skipping insertion in model container [2019-12-07 15:19:37,304 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 03:19:37" (1/1) ... [2019-12-07 15:19:37,308 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 15:19:37,337 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 15:19:37,584 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 15:19:37,593 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 15:19:37,649 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 15:19:37,700 INFO L208 MainTranslator]: Completed translation [2019-12-07 15:19:37,700 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:19:37 WrapperNode [2019-12-07 15:19:37,700 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 15:19:37,701 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 15:19:37,701 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 15:19:37,701 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 15:19:37,707 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:19:37" (1/1) ... [2019-12-07 15:19:37,726 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:19:37" (1/1) ... [2019-12-07 15:19:37,755 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 15:19:37,756 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 15:19:37,756 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 15:19:37,756 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 15:19:37,764 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:19:37" (1/1) ... [2019-12-07 15:19:37,764 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:19:37" (1/1) ... [2019-12-07 15:19:37,769 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:19:37" (1/1) ... [2019-12-07 15:19:37,770 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:19:37" (1/1) ... [2019-12-07 15:19:37,779 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:19:37" (1/1) ... [2019-12-07 15:19:37,782 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:19:37" (1/1) ... [2019-12-07 15:19:37,785 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:19:37" (1/1) ... [2019-12-07 15:19:37,788 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 15:19:37,789 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 15:19:37,789 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 15:19:37,789 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 15:19:37,789 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:19:37" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_dded0f1c-e543-47fa-8557-549916ecea08/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 15:19:37,829 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 15:19:37,829 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 15:19:37,829 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 15:19:37,829 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 15:19:37,829 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 15:19:37,829 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 15:19:37,829 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 15:19:37,829 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 15:19:37,830 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 15:19:37,830 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 15:19:37,830 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 15:19:37,830 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 15:19:37,830 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 15:19:37,831 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 15:19:38,203 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 15:19:38,204 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 15:19:38,204 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 03:19:38 BoogieIcfgContainer [2019-12-07 15:19:38,205 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 15:19:38,205 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 15:19:38,205 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 15:19:38,207 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 15:19:38,207 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 03:19:37" (1/3) ... [2019-12-07 15:19:38,208 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@474c5b16 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 03:19:38, skipping insertion in model container [2019-12-07 15:19:38,208 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:19:37" (2/3) ... [2019-12-07 15:19:38,208 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@474c5b16 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 03:19:38, skipping insertion in model container [2019-12-07 15:19:38,208 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 03:19:38" (3/3) ... [2019-12-07 15:19:38,209 INFO L109 eAbstractionObserver]: Analyzing ICFG safe001_rmo.opt.i [2019-12-07 15:19:38,216 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 15:19:38,216 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 15:19:38,221 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 15:19:38,221 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 15:19:38,245 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,245 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,245 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,245 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,245 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,246 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,246 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,246 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,246 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,246 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,246 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,246 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,246 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,246 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,247 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,247 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,247 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,247 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,247 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,247 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,247 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,247 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,247 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,248 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,248 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,248 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,248 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,248 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,248 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,248 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,249 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,249 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,249 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,249 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,249 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,249 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,249 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,250 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,250 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,250 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,250 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,250 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,250 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,250 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,251 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,251 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,251 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,251 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,251 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,251 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,251 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,251 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,252 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,252 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,252 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,252 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,252 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,252 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,252 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,252 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,252 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,253 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,253 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,253 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,253 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,253 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,253 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,253 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,253 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,254 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,254 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,254 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,254 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,254 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,254 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,254 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,255 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,255 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,255 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,255 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,255 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,255 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,255 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,255 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,255 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,256 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,256 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,256 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,256 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,256 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,256 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,256 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,256 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,256 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:19:38,268 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 15:19:38,280 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 15:19:38,280 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 15:19:38,280 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 15:19:38,280 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 15:19:38,280 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 15:19:38,280 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 15:19:38,281 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 15:19:38,281 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 15:19:38,292 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 174 places, 211 transitions [2019-12-07 15:19:38,293 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 174 places, 211 transitions [2019-12-07 15:19:38,360 INFO L134 PetriNetUnfolder]: 47/208 cut-off events. [2019-12-07 15:19:38,360 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 15:19:38,370 INFO L76 FinitePrefix]: Finished finitePrefix Result has 218 conditions, 208 events. 47/208 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 572 event pairs. 9/168 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 15:19:38,385 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 174 places, 211 transitions [2019-12-07 15:19:38,413 INFO L134 PetriNetUnfolder]: 47/208 cut-off events. [2019-12-07 15:19:38,414 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 15:19:38,418 INFO L76 FinitePrefix]: Finished finitePrefix Result has 218 conditions, 208 events. 47/208 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 572 event pairs. 9/168 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 15:19:38,433 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 17074 [2019-12-07 15:19:38,433 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 15:19:41,218 WARN L192 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 85 [2019-12-07 15:19:41,305 INFO L206 etLargeBlockEncoding]: Checked pairs total: 78277 [2019-12-07 15:19:41,306 INFO L214 etLargeBlockEncoding]: Total number of compositions: 111 [2019-12-07 15:19:41,308 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 94 places, 106 transitions [2019-12-07 15:19:54,805 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 107408 states. [2019-12-07 15:19:54,807 INFO L276 IsEmpty]: Start isEmpty. Operand 107408 states. [2019-12-07 15:19:54,812 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-12-07 15:19:54,812 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:19:54,813 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-12-07 15:19:54,813 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:19:54,818 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:19:54,819 INFO L82 PathProgramCache]: Analyzing trace with hash 809703812, now seen corresponding path program 1 times [2019-12-07 15:19:54,824 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:19:54,825 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [15176891] [2019-12-07 15:19:54,825 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:19:54,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:19:54,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:19:54,971 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [15176891] [2019-12-07 15:19:54,972 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:19:54,972 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 15:19:54,972 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [259474198] [2019-12-07 15:19:54,975 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:19:54,976 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:19:54,984 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:19:54,985 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:19:54,986 INFO L87 Difference]: Start difference. First operand 107408 states. Second operand 3 states. [2019-12-07 15:19:55,677 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:19:55,677 INFO L93 Difference]: Finished difference Result 107108 states and 460900 transitions. [2019-12-07 15:19:55,678 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:19:55,679 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 5 [2019-12-07 15:19:55,679 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:19:56,460 INFO L225 Difference]: With dead ends: 107108 [2019-12-07 15:19:56,461 INFO L226 Difference]: Without dead ends: 104924 [2019-12-07 15:19:56,461 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:19:59,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104924 states. [2019-12-07 15:20:01,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104924 to 104924. [2019-12-07 15:20:01,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 104924 states. [2019-12-07 15:20:01,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104924 states to 104924 states and 451982 transitions. [2019-12-07 15:20:01,515 INFO L78 Accepts]: Start accepts. Automaton has 104924 states and 451982 transitions. Word has length 5 [2019-12-07 15:20:01,515 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:20:01,515 INFO L462 AbstractCegarLoop]: Abstraction has 104924 states and 451982 transitions. [2019-12-07 15:20:01,515 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:20:01,516 INFO L276 IsEmpty]: Start isEmpty. Operand 104924 states and 451982 transitions. [2019-12-07 15:20:01,518 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 15:20:01,518 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:20:01,518 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:20:01,518 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:20:01,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:20:01,519 INFO L82 PathProgramCache]: Analyzing trace with hash 2105056515, now seen corresponding path program 1 times [2019-12-07 15:20:01,519 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:20:01,519 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1100344847] [2019-12-07 15:20:01,519 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:20:01,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:20:01,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:20:01,579 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1100344847] [2019-12-07 15:20:01,580 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:20:01,580 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:20:01,580 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1328202099] [2019-12-07 15:20:01,581 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 15:20:01,581 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:20:01,581 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 15:20:01,581 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:20:01,581 INFO L87 Difference]: Start difference. First operand 104924 states and 451982 transitions. Second operand 4 states. [2019-12-07 15:20:04,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:20:04,734 INFO L93 Difference]: Finished difference Result 168606 states and 697152 transitions. [2019-12-07 15:20:04,735 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 15:20:04,735 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 15:20:04,735 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:20:05,225 INFO L225 Difference]: With dead ends: 168606 [2019-12-07 15:20:05,225 INFO L226 Difference]: Without dead ends: 168557 [2019-12-07 15:20:05,226 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:20:09,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 168557 states. [2019-12-07 15:20:11,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 168557 to 152629. [2019-12-07 15:20:11,175 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 152629 states. [2019-12-07 15:20:11,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152629 states to 152629 states and 638547 transitions. [2019-12-07 15:20:11,588 INFO L78 Accepts]: Start accepts. Automaton has 152629 states and 638547 transitions. Word has length 11 [2019-12-07 15:20:11,588 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:20:11,589 INFO L462 AbstractCegarLoop]: Abstraction has 152629 states and 638547 transitions. [2019-12-07 15:20:11,589 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 15:20:11,589 INFO L276 IsEmpty]: Start isEmpty. Operand 152629 states and 638547 transitions. [2019-12-07 15:20:11,593 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 15:20:11,594 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:20:11,594 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:20:11,594 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:20:11,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:20:11,594 INFO L82 PathProgramCache]: Analyzing trace with hash 2027270657, now seen corresponding path program 1 times [2019-12-07 15:20:11,594 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:20:11,594 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [534387] [2019-12-07 15:20:11,595 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:20:11,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:20:11,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:20:11,642 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [534387] [2019-12-07 15:20:11,642 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:20:11,642 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:20:11,642 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81965378] [2019-12-07 15:20:11,643 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 15:20:11,643 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:20:11,643 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 15:20:11,643 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:20:11,643 INFO L87 Difference]: Start difference. First operand 152629 states and 638547 transitions. Second operand 4 states. [2019-12-07 15:20:12,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:20:12,828 INFO L93 Difference]: Finished difference Result 217678 states and 889823 transitions. [2019-12-07 15:20:12,829 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 15:20:12,829 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 15:20:12,829 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:20:13,972 INFO L225 Difference]: With dead ends: 217678 [2019-12-07 15:20:13,972 INFO L226 Difference]: Without dead ends: 217615 [2019-12-07 15:20:13,972 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:20:18,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217615 states. [2019-12-07 15:20:23,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217615 to 183279. [2019-12-07 15:20:23,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 183279 states. [2019-12-07 15:20:23,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183279 states to 183279 states and 761454 transitions. [2019-12-07 15:20:23,917 INFO L78 Accepts]: Start accepts. Automaton has 183279 states and 761454 transitions. Word has length 13 [2019-12-07 15:20:23,918 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:20:23,918 INFO L462 AbstractCegarLoop]: Abstraction has 183279 states and 761454 transitions. [2019-12-07 15:20:23,918 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 15:20:23,919 INFO L276 IsEmpty]: Start isEmpty. Operand 183279 states and 761454 transitions. [2019-12-07 15:20:23,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 15:20:23,921 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:20:23,921 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:20:23,921 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:20:23,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:20:23,922 INFO L82 PathProgramCache]: Analyzing trace with hash 1789207667, now seen corresponding path program 1 times [2019-12-07 15:20:23,922 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:20:23,922 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1717763336] [2019-12-07 15:20:23,922 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:20:23,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:20:23,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:20:23,972 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1717763336] [2019-12-07 15:20:23,972 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:20:23,972 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:20:23,972 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1196643145] [2019-12-07 15:20:23,973 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 15:20:23,973 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:20:23,973 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 15:20:23,973 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:20:23,973 INFO L87 Difference]: Start difference. First operand 183279 states and 761454 transitions. Second operand 4 states. [2019-12-07 15:20:25,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:20:25,127 INFO L93 Difference]: Finished difference Result 228772 states and 941089 transitions. [2019-12-07 15:20:25,127 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 15:20:25,127 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 15:20:25,127 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:20:25,702 INFO L225 Difference]: With dead ends: 228772 [2019-12-07 15:20:25,702 INFO L226 Difference]: Without dead ends: 228772 [2019-12-07 15:20:25,702 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:20:30,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228772 states. [2019-12-07 15:20:36,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228772 to 193424. [2019-12-07 15:20:36,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 193424 states. [2019-12-07 15:20:36,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193424 states to 193424 states and 803706 transitions. [2019-12-07 15:20:36,900 INFO L78 Accepts]: Start accepts. Automaton has 193424 states and 803706 transitions. Word has length 13 [2019-12-07 15:20:36,901 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:20:36,901 INFO L462 AbstractCegarLoop]: Abstraction has 193424 states and 803706 transitions. [2019-12-07 15:20:36,901 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 15:20:36,901 INFO L276 IsEmpty]: Start isEmpty. Operand 193424 states and 803706 transitions. [2019-12-07 15:20:36,914 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 15:20:36,914 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:20:36,914 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:20:36,915 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:20:36,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:20:36,915 INFO L82 PathProgramCache]: Analyzing trace with hash 1405830784, now seen corresponding path program 1 times [2019-12-07 15:20:36,915 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:20:36,915 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1660454323] [2019-12-07 15:20:36,915 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:20:36,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:20:36,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:20:36,988 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1660454323] [2019-12-07 15:20:36,988 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:20:36,988 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 15:20:36,988 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1608986214] [2019-12-07 15:20:36,988 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:20:36,988 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:20:36,988 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:20:36,989 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:20:36,989 INFO L87 Difference]: Start difference. First operand 193424 states and 803706 transitions. Second operand 6 states. [2019-12-07 15:20:38,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:20:38,959 INFO L93 Difference]: Finished difference Result 306795 states and 1235310 transitions. [2019-12-07 15:20:38,960 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 15:20:38,960 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 19 [2019-12-07 15:20:38,960 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:20:39,718 INFO L225 Difference]: With dead ends: 306795 [2019-12-07 15:20:39,718 INFO L226 Difference]: Without dead ends: 306697 [2019-12-07 15:20:39,718 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=71, Unknown=0, NotChecked=0, Total=110 [2019-12-07 15:20:45,277 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 306697 states. [2019-12-07 15:20:49,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 306697 to 204176. [2019-12-07 15:20:49,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 204176 states. [2019-12-07 15:20:49,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204176 states to 204176 states and 845949 transitions. [2019-12-07 15:20:49,752 INFO L78 Accepts]: Start accepts. Automaton has 204176 states and 845949 transitions. Word has length 19 [2019-12-07 15:20:49,753 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:20:49,753 INFO L462 AbstractCegarLoop]: Abstraction has 204176 states and 845949 transitions. [2019-12-07 15:20:49,753 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:20:49,753 INFO L276 IsEmpty]: Start isEmpty. Operand 204176 states and 845949 transitions. [2019-12-07 15:20:49,764 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 15:20:49,764 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:20:49,765 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:20:49,765 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:20:49,765 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:20:49,765 INFO L82 PathProgramCache]: Analyzing trace with hash 1167767794, now seen corresponding path program 1 times [2019-12-07 15:20:49,765 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:20:49,765 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [137284106] [2019-12-07 15:20:49,765 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:20:49,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:20:49,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:20:49,808 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [137284106] [2019-12-07 15:20:49,808 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:20:49,808 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:20:49,808 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1837063639] [2019-12-07 15:20:49,809 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:20:49,809 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:20:49,809 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:20:49,809 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:20:49,809 INFO L87 Difference]: Start difference. First operand 204176 states and 845949 transitions. Second operand 5 states. [2019-12-07 15:20:51,415 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:20:51,415 INFO L93 Difference]: Finished difference Result 299515 states and 1215179 transitions. [2019-12-07 15:20:51,415 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 15:20:51,415 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 15:20:51,416 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:20:55,008 INFO L225 Difference]: With dead ends: 299515 [2019-12-07 15:20:55,009 INFO L226 Difference]: Without dead ends: 299452 [2019-12-07 15:20:55,009 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:21:00,236 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 299452 states. [2019-12-07 15:21:03,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 299452 to 222544. [2019-12-07 15:21:03,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 222544 states. [2019-12-07 15:21:04,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222544 states to 222544 states and 918353 transitions. [2019-12-07 15:21:04,641 INFO L78 Accepts]: Start accepts. Automaton has 222544 states and 918353 transitions. Word has length 19 [2019-12-07 15:21:04,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:21:04,641 INFO L462 AbstractCegarLoop]: Abstraction has 222544 states and 918353 transitions. [2019-12-07 15:21:04,641 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:21:04,641 INFO L276 IsEmpty]: Start isEmpty. Operand 222544 states and 918353 transitions. [2019-12-07 15:21:04,651 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 15:21:04,652 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:21:04,652 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:21:04,652 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:21:04,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:21:04,652 INFO L82 PathProgramCache]: Analyzing trace with hash -159037504, now seen corresponding path program 2 times [2019-12-07 15:21:04,652 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:21:04,652 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [351250070] [2019-12-07 15:21:04,653 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:21:04,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:21:04,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:21:04,709 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [351250070] [2019-12-07 15:21:04,709 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:21:04,710 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:21:04,710 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1953285027] [2019-12-07 15:21:04,710 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:21:04,710 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:21:04,710 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:21:04,710 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:21:04,710 INFO L87 Difference]: Start difference. First operand 222544 states and 918353 transitions. Second operand 5 states. [2019-12-07 15:21:06,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:21:06,448 INFO L93 Difference]: Finished difference Result 306165 states and 1239611 transitions. [2019-12-07 15:21:06,448 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 15:21:06,448 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 15:21:06,448 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:21:07,756 INFO L225 Difference]: With dead ends: 306165 [2019-12-07 15:21:07,756 INFO L226 Difference]: Without dead ends: 306074 [2019-12-07 15:21:07,756 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:21:15,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 306074 states. [2019-12-07 15:21:19,352 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 306074 to 216265. [2019-12-07 15:21:19,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 216265 states. [2019-12-07 15:21:19,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 216265 states to 216265 states and 893275 transitions. [2019-12-07 15:21:19,968 INFO L78 Accepts]: Start accepts. Automaton has 216265 states and 893275 transitions. Word has length 19 [2019-12-07 15:21:19,969 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:21:19,969 INFO L462 AbstractCegarLoop]: Abstraction has 216265 states and 893275 transitions. [2019-12-07 15:21:19,969 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:21:19,969 INFO L276 IsEmpty]: Start isEmpty. Operand 216265 states and 893275 transitions. [2019-12-07 15:21:19,981 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 15:21:19,981 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:21:19,981 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:21:19,981 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:21:19,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:21:19,982 INFO L82 PathProgramCache]: Analyzing trace with hash 1572236508, now seen corresponding path program 1 times [2019-12-07 15:21:19,982 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:21:19,982 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1298707819] [2019-12-07 15:21:19,982 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:21:19,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:21:20,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:21:20,032 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1298707819] [2019-12-07 15:21:20,032 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:21:20,032 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 15:21:20,032 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1634052923] [2019-12-07 15:21:20,032 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:21:20,032 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:21:20,033 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:21:20,033 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:21:20,033 INFO L87 Difference]: Start difference. First operand 216265 states and 893275 transitions. Second operand 6 states. [2019-12-07 15:21:22,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:21:22,174 INFO L93 Difference]: Finished difference Result 315951 states and 1278566 transitions. [2019-12-07 15:21:22,175 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 15:21:22,175 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 19 [2019-12-07 15:21:22,175 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:21:22,942 INFO L225 Difference]: With dead ends: 315951 [2019-12-07 15:21:22,942 INFO L226 Difference]: Without dead ends: 315951 [2019-12-07 15:21:22,943 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=71, Unknown=0, NotChecked=0, Total=110 [2019-12-07 15:21:28,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 315951 states. [2019-12-07 15:21:32,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 315951 to 226037. [2019-12-07 15:21:32,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226037 states. [2019-12-07 15:21:33,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226037 states to 226037 states and 931835 transitions. [2019-12-07 15:21:33,036 INFO L78 Accepts]: Start accepts. Automaton has 226037 states and 931835 transitions. Word has length 19 [2019-12-07 15:21:33,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:21:33,036 INFO L462 AbstractCegarLoop]: Abstraction has 226037 states and 931835 transitions. [2019-12-07 15:21:33,036 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:21:33,036 INFO L276 IsEmpty]: Start isEmpty. Operand 226037 states and 931835 transitions. [2019-12-07 15:21:33,049 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 15:21:33,049 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:21:33,049 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:21:33,049 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:21:33,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:21:33,049 INFO L82 PathProgramCache]: Analyzing trace with hash -1878693572, now seen corresponding path program 2 times [2019-12-07 15:21:33,050 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:21:33,050 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2054383312] [2019-12-07 15:21:33,050 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:21:33,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:21:33,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:21:33,082 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2054383312] [2019-12-07 15:21:33,082 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:21:33,082 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:21:33,083 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2144447516] [2019-12-07 15:21:33,083 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:21:33,083 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:21:33,083 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:21:33,083 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:21:33,083 INFO L87 Difference]: Start difference. First operand 226037 states and 931835 transitions. Second operand 5 states. [2019-12-07 15:21:35,212 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:21:35,212 INFO L93 Difference]: Finished difference Result 322388 states and 1308191 transitions. [2019-12-07 15:21:35,212 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 15:21:35,213 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 15:21:35,213 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:21:39,267 INFO L225 Difference]: With dead ends: 322388 [2019-12-07 15:21:39,267 INFO L226 Difference]: Without dead ends: 322325 [2019-12-07 15:21:39,268 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:21:44,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322325 states. [2019-12-07 15:21:48,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322325 to 231837. [2019-12-07 15:21:48,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 231837 states. [2019-12-07 15:21:49,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 231837 states to 231837 states and 956389 transitions. [2019-12-07 15:21:49,052 INFO L78 Accepts]: Start accepts. Automaton has 231837 states and 956389 transitions. Word has length 19 [2019-12-07 15:21:49,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:21:49,053 INFO L462 AbstractCegarLoop]: Abstraction has 231837 states and 956389 transitions. [2019-12-07 15:21:49,053 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:21:49,053 INFO L276 IsEmpty]: Start isEmpty. Operand 231837 states and 956389 transitions. [2019-12-07 15:21:49,104 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 15:21:49,104 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:21:49,104 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:21:49,104 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:21:49,105 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:21:49,105 INFO L82 PathProgramCache]: Analyzing trace with hash -983276005, now seen corresponding path program 1 times [2019-12-07 15:21:49,105 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:21:49,105 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [966121761] [2019-12-07 15:21:49,105 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:21:49,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:21:49,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:21:49,168 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [966121761] [2019-12-07 15:21:49,168 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:21:49,168 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 15:21:49,168 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1179594048] [2019-12-07 15:21:49,168 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 15:21:49,168 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:21:49,168 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 15:21:49,168 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 15:21:49,169 INFO L87 Difference]: Start difference. First operand 231837 states and 956389 transitions. Second operand 7 states. [2019-12-07 15:21:51,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:21:51,992 INFO L93 Difference]: Finished difference Result 363566 states and 1470501 transitions. [2019-12-07 15:21:51,992 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 15:21:51,992 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 25 [2019-12-07 15:21:51,993 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:21:52,900 INFO L225 Difference]: With dead ends: 363566 [2019-12-07 15:21:52,900 INFO L226 Difference]: Without dead ends: 363566 [2019-12-07 15:21:52,900 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 78 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=117, Invalid=303, Unknown=0, NotChecked=0, Total=420 [2019-12-07 15:21:59,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 363566 states. [2019-12-07 15:22:03,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 363566 to 228323. [2019-12-07 15:22:03,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228323 states. [2019-12-07 15:22:04,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228323 states to 228323 states and 943087 transitions. [2019-12-07 15:22:04,226 INFO L78 Accepts]: Start accepts. Automaton has 228323 states and 943087 transitions. Word has length 25 [2019-12-07 15:22:04,226 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:22:04,226 INFO L462 AbstractCegarLoop]: Abstraction has 228323 states and 943087 transitions. [2019-12-07 15:22:04,227 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 15:22:04,227 INFO L276 IsEmpty]: Start isEmpty. Operand 228323 states and 943087 transitions. [2019-12-07 15:22:04,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 15:22:04,270 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:22:04,270 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:22:04,270 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:22:04,270 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:22:04,270 INFO L82 PathProgramCache]: Analyzing trace with hash -139238789, now seen corresponding path program 2 times [2019-12-07 15:22:04,271 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:22:04,271 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1102809943] [2019-12-07 15:22:04,271 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:22:04,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:22:04,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:22:04,330 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1102809943] [2019-12-07 15:22:04,330 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:22:04,330 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 15:22:04,330 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [137481613] [2019-12-07 15:22:04,330 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:22:04,330 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:22:04,331 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:22:04,331 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:22:04,331 INFO L87 Difference]: Start difference. First operand 228323 states and 943087 transitions. Second operand 6 states. [2019-12-07 15:22:06,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:22:06,496 INFO L93 Difference]: Finished difference Result 272978 states and 1114694 transitions. [2019-12-07 15:22:06,496 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 15:22:06,496 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2019-12-07 15:22:06,496 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:22:07,194 INFO L225 Difference]: With dead ends: 272978 [2019-12-07 15:22:07,194 INFO L226 Difference]: Without dead ends: 272838 [2019-12-07 15:22:07,195 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=81, Invalid=191, Unknown=0, NotChecked=0, Total=272 [2019-12-07 15:22:14,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 272838 states. [2019-12-07 15:22:18,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 272838 to 191175. [2019-12-07 15:22:18,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 191175 states. [2019-12-07 15:22:18,651 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191175 states to 191175 states and 792620 transitions. [2019-12-07 15:22:18,651 INFO L78 Accepts]: Start accepts. Automaton has 191175 states and 792620 transitions. Word has length 25 [2019-12-07 15:22:18,652 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:22:18,652 INFO L462 AbstractCegarLoop]: Abstraction has 191175 states and 792620 transitions. [2019-12-07 15:22:18,652 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:22:18,652 INFO L276 IsEmpty]: Start isEmpty. Operand 191175 states and 792620 transitions. [2019-12-07 15:22:18,710 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 15:22:18,710 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:22:18,710 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:22:18,710 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:22:18,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:22:18,710 INFO L82 PathProgramCache]: Analyzing trace with hash -588293342, now seen corresponding path program 1 times [2019-12-07 15:22:18,710 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:22:18,711 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1607114051] [2019-12-07 15:22:18,711 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:22:18,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:22:18,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:22:18,736 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1607114051] [2019-12-07 15:22:18,736 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:22:18,736 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:22:18,736 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [329597792] [2019-12-07 15:22:18,736 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:22:18,737 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:22:18,737 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:22:18,737 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:22:18,737 INFO L87 Difference]: Start difference. First operand 191175 states and 792620 transitions. Second operand 3 states. [2019-12-07 15:22:20,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:22:20,198 INFO L93 Difference]: Finished difference Result 229453 states and 953212 transitions. [2019-12-07 15:22:20,198 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:22:20,198 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 15:22:20,198 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:22:20,767 INFO L225 Difference]: With dead ends: 229453 [2019-12-07 15:22:20,767 INFO L226 Difference]: Without dead ends: 229453 [2019-12-07 15:22:20,767 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:22:25,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 229453 states. [2019-12-07 15:22:28,301 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 229453 to 215231. [2019-12-07 15:22:28,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 215231 states. [2019-12-07 15:22:29,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215231 states to 215231 states and 897051 transitions. [2019-12-07 15:22:29,238 INFO L78 Accepts]: Start accepts. Automaton has 215231 states and 897051 transitions. Word has length 27 [2019-12-07 15:22:29,238 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:22:29,239 INFO L462 AbstractCegarLoop]: Abstraction has 215231 states and 897051 transitions. [2019-12-07 15:22:29,239 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:22:29,239 INFO L276 IsEmpty]: Start isEmpty. Operand 215231 states and 897051 transitions. [2019-12-07 15:22:29,300 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 15:22:29,300 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:22:29,300 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:22:29,300 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:22:29,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:22:29,300 INFO L82 PathProgramCache]: Analyzing trace with hash -455574437, now seen corresponding path program 1 times [2019-12-07 15:22:29,300 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:22:29,300 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1336406552] [2019-12-07 15:22:29,301 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:22:29,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:22:29,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:22:29,324 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1336406552] [2019-12-07 15:22:29,324 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:22:29,324 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:22:29,324 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2043150146] [2019-12-07 15:22:29,324 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:22:29,324 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:22:29,324 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:22:29,324 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:22:29,325 INFO L87 Difference]: Start difference. First operand 215231 states and 897051 transitions. Second operand 3 states. [2019-12-07 15:22:29,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:22:29,446 INFO L93 Difference]: Finished difference Result 44393 states and 145223 transitions. [2019-12-07 15:22:29,447 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:22:29,447 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 15:22:29,447 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:22:29,506 INFO L225 Difference]: With dead ends: 44393 [2019-12-07 15:22:29,506 INFO L226 Difference]: Without dead ends: 44393 [2019-12-07 15:22:29,506 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:22:29,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44393 states. [2019-12-07 15:22:30,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44393 to 44393. [2019-12-07 15:22:30,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44393 states. [2019-12-07 15:22:30,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44393 states to 44393 states and 145223 transitions. [2019-12-07 15:22:30,191 INFO L78 Accepts]: Start accepts. Automaton has 44393 states and 145223 transitions. Word has length 27 [2019-12-07 15:22:30,191 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:22:30,191 INFO L462 AbstractCegarLoop]: Abstraction has 44393 states and 145223 transitions. [2019-12-07 15:22:30,191 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:22:30,192 INFO L276 IsEmpty]: Start isEmpty. Operand 44393 states and 145223 transitions. [2019-12-07 15:22:30,208 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2019-12-07 15:22:30,208 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:22:30,208 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:22:30,208 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:22:30,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:22:30,208 INFO L82 PathProgramCache]: Analyzing trace with hash 1697210614, now seen corresponding path program 1 times [2019-12-07 15:22:30,209 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:22:30,209 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1303674572] [2019-12-07 15:22:30,209 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:22:30,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:22:30,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:22:30,254 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1303674572] [2019-12-07 15:22:30,254 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:22:30,255 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:22:30,255 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [978466774] [2019-12-07 15:22:30,255 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 15:22:30,255 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:22:30,255 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 15:22:30,256 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:22:30,256 INFO L87 Difference]: Start difference. First operand 44393 states and 145223 transitions. Second operand 4 states. [2019-12-07 15:22:30,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:22:30,282 INFO L93 Difference]: Finished difference Result 7906 states and 21265 transitions. [2019-12-07 15:22:30,282 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 15:22:30,283 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 39 [2019-12-07 15:22:30,283 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:22:30,289 INFO L225 Difference]: With dead ends: 7906 [2019-12-07 15:22:30,289 INFO L226 Difference]: Without dead ends: 7906 [2019-12-07 15:22:30,289 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:22:30,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7906 states. [2019-12-07 15:22:30,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7906 to 7794. [2019-12-07 15:22:30,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7794 states. [2019-12-07 15:22:30,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7794 states to 7794 states and 20945 transitions. [2019-12-07 15:22:30,376 INFO L78 Accepts]: Start accepts. Automaton has 7794 states and 20945 transitions. Word has length 39 [2019-12-07 15:22:30,376 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:22:30,376 INFO L462 AbstractCegarLoop]: Abstraction has 7794 states and 20945 transitions. [2019-12-07 15:22:30,376 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 15:22:30,376 INFO L276 IsEmpty]: Start isEmpty. Operand 7794 states and 20945 transitions. [2019-12-07 15:22:30,381 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 15:22:30,381 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:22:30,382 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:22:30,382 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:22:30,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:22:30,382 INFO L82 PathProgramCache]: Analyzing trace with hash -994376569, now seen corresponding path program 1 times [2019-12-07 15:22:30,382 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:22:30,382 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1914343357] [2019-12-07 15:22:30,382 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:22:30,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:22:30,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:22:30,432 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1914343357] [2019-12-07 15:22:30,432 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:22:30,433 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 15:22:30,433 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1420136642] [2019-12-07 15:22:30,433 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:22:30,433 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:22:30,433 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:22:30,433 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:22:30,434 INFO L87 Difference]: Start difference. First operand 7794 states and 20945 transitions. Second operand 5 states. [2019-12-07 15:22:30,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:22:30,461 INFO L93 Difference]: Finished difference Result 5050 states and 14454 transitions. [2019-12-07 15:22:30,461 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 15:22:30,461 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-12-07 15:22:30,461 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:22:30,467 INFO L225 Difference]: With dead ends: 5050 [2019-12-07 15:22:30,467 INFO L226 Difference]: Without dead ends: 5050 [2019-12-07 15:22:30,468 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:22:30,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5050 states. [2019-12-07 15:22:30,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5050 to 4686. [2019-12-07 15:22:30,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4686 states. [2019-12-07 15:22:30,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4686 states to 4686 states and 13470 transitions. [2019-12-07 15:22:30,531 INFO L78 Accepts]: Start accepts. Automaton has 4686 states and 13470 transitions. Word has length 51 [2019-12-07 15:22:30,532 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:22:30,532 INFO L462 AbstractCegarLoop]: Abstraction has 4686 states and 13470 transitions. [2019-12-07 15:22:30,532 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:22:30,532 INFO L276 IsEmpty]: Start isEmpty. Operand 4686 states and 13470 transitions. [2019-12-07 15:22:30,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 15:22:30,535 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:22:30,535 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:22:30,535 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:22:30,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:22:30,535 INFO L82 PathProgramCache]: Analyzing trace with hash 1902070617, now seen corresponding path program 1 times [2019-12-07 15:22:30,535 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:22:30,535 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [739373278] [2019-12-07 15:22:30,536 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:22:30,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:22:30,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:22:30,565 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [739373278] [2019-12-07 15:22:30,565 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:22:30,566 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:22:30,566 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1973182708] [2019-12-07 15:22:30,566 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:22:30,566 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:22:30,566 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:22:30,566 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:22:30,566 INFO L87 Difference]: Start difference. First operand 4686 states and 13470 transitions. Second operand 3 states. [2019-12-07 15:22:30,601 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:22:30,602 INFO L93 Difference]: Finished difference Result 4690 states and 13463 transitions. [2019-12-07 15:22:30,602 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:22:30,602 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 15:22:30,602 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:22:30,606 INFO L225 Difference]: With dead ends: 4690 [2019-12-07 15:22:30,606 INFO L226 Difference]: Without dead ends: 4690 [2019-12-07 15:22:30,607 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:22:30,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4690 states. [2019-12-07 15:22:30,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4690 to 4682. [2019-12-07 15:22:30,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4682 states. [2019-12-07 15:22:30,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4682 states to 4682 states and 13455 transitions. [2019-12-07 15:22:30,661 INFO L78 Accepts]: Start accepts. Automaton has 4682 states and 13455 transitions. Word has length 65 [2019-12-07 15:22:30,662 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:22:30,662 INFO L462 AbstractCegarLoop]: Abstraction has 4682 states and 13455 transitions. [2019-12-07 15:22:30,662 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:22:30,662 INFO L276 IsEmpty]: Start isEmpty. Operand 4682 states and 13455 transitions. [2019-12-07 15:22:30,665 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 15:22:30,665 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:22:30,665 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:22:30,666 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:22:30,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:22:30,666 INFO L82 PathProgramCache]: Analyzing trace with hash 1892358751, now seen corresponding path program 1 times [2019-12-07 15:22:30,666 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:22:30,666 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [304630748] [2019-12-07 15:22:30,666 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:22:30,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:22:30,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:22:30,719 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [304630748] [2019-12-07 15:22:30,719 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:22:30,720 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 15:22:30,720 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1817766] [2019-12-07 15:22:30,720 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:22:30,720 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:22:30,720 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:22:30,720 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:22:30,720 INFO L87 Difference]: Start difference. First operand 4682 states and 13455 transitions. Second operand 6 states. [2019-12-07 15:22:31,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:22:31,014 INFO L93 Difference]: Finished difference Result 8786 states and 25107 transitions. [2019-12-07 15:22:31,014 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 15:22:31,015 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 65 [2019-12-07 15:22:31,015 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:22:31,024 INFO L225 Difference]: With dead ends: 8786 [2019-12-07 15:22:31,024 INFO L226 Difference]: Without dead ends: 8786 [2019-12-07 15:22:31,024 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:22:31,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8786 states. [2019-12-07 15:22:31,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8786 to 5995. [2019-12-07 15:22:31,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5995 states. [2019-12-07 15:22:31,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5995 states to 5995 states and 17174 transitions. [2019-12-07 15:22:31,403 INFO L78 Accepts]: Start accepts. Automaton has 5995 states and 17174 transitions. Word has length 65 [2019-12-07 15:22:31,403 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:22:31,404 INFO L462 AbstractCegarLoop]: Abstraction has 5995 states and 17174 transitions. [2019-12-07 15:22:31,404 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:22:31,404 INFO L276 IsEmpty]: Start isEmpty. Operand 5995 states and 17174 transitions. [2019-12-07 15:22:31,407 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 15:22:31,407 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:22:31,408 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:22:31,408 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:22:31,408 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:22:31,408 INFO L82 PathProgramCache]: Analyzing trace with hash -191494421, now seen corresponding path program 2 times [2019-12-07 15:22:31,408 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:22:31,408 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [533098893] [2019-12-07 15:22:31,408 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:22:31,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:22:31,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:22:31,461 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [533098893] [2019-12-07 15:22:31,461 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:22:31,461 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 15:22:31,461 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2053845034] [2019-12-07 15:22:31,461 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:22:31,462 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:22:31,462 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:22:31,462 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:22:31,462 INFO L87 Difference]: Start difference. First operand 5995 states and 17174 transitions. Second operand 5 states. [2019-12-07 15:22:31,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:22:31,665 INFO L93 Difference]: Finished difference Result 8521 states and 24141 transitions. [2019-12-07 15:22:31,665 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 15:22:31,665 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 65 [2019-12-07 15:22:31,665 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:22:31,672 INFO L225 Difference]: With dead ends: 8521 [2019-12-07 15:22:31,672 INFO L226 Difference]: Without dead ends: 8521 [2019-12-07 15:22:31,672 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 15:22:31,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8521 states. [2019-12-07 15:22:31,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8521 to 6771. [2019-12-07 15:22:31,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6771 states. [2019-12-07 15:22:31,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6771 states to 6771 states and 19440 transitions. [2019-12-07 15:22:31,760 INFO L78 Accepts]: Start accepts. Automaton has 6771 states and 19440 transitions. Word has length 65 [2019-12-07 15:22:31,760 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:22:31,760 INFO L462 AbstractCegarLoop]: Abstraction has 6771 states and 19440 transitions. [2019-12-07 15:22:31,760 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:22:31,760 INFO L276 IsEmpty]: Start isEmpty. Operand 6771 states and 19440 transitions. [2019-12-07 15:22:31,765 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 15:22:31,765 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:22:31,765 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:22:31,765 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:22:31,765 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:22:31,765 INFO L82 PathProgramCache]: Analyzing trace with hash 147719209, now seen corresponding path program 3 times [2019-12-07 15:22:31,765 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:22:31,766 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [833513039] [2019-12-07 15:22:31,766 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:22:31,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:22:31,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:22:31,802 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [833513039] [2019-12-07 15:22:31,802 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:22:31,803 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:22:31,803 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [749667036] [2019-12-07 15:22:31,803 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:22:31,803 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:22:31,803 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:22:31,803 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:22:31,803 INFO L87 Difference]: Start difference. First operand 6771 states and 19440 transitions. Second operand 3 states. [2019-12-07 15:22:31,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:22:31,820 INFO L93 Difference]: Finished difference Result 5663 states and 15971 transitions. [2019-12-07 15:22:31,821 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:22:31,821 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 15:22:31,821 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:22:31,825 INFO L225 Difference]: With dead ends: 5663 [2019-12-07 15:22:31,825 INFO L226 Difference]: Without dead ends: 5663 [2019-12-07 15:22:31,825 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:22:31,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5663 states. [2019-12-07 15:22:31,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5663 to 5523. [2019-12-07 15:22:31,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5523 states. [2019-12-07 15:22:31,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5523 states to 5523 states and 15585 transitions. [2019-12-07 15:22:31,889 INFO L78 Accepts]: Start accepts. Automaton has 5523 states and 15585 transitions. Word has length 65 [2019-12-07 15:22:31,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:22:31,889 INFO L462 AbstractCegarLoop]: Abstraction has 5523 states and 15585 transitions. [2019-12-07 15:22:31,889 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:22:31,889 INFO L276 IsEmpty]: Start isEmpty. Operand 5523 states and 15585 transitions. [2019-12-07 15:22:31,892 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 15:22:31,892 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:22:31,892 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:22:31,893 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:22:31,893 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:22:31,893 INFO L82 PathProgramCache]: Analyzing trace with hash 284491425, now seen corresponding path program 1 times [2019-12-07 15:22:31,893 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:22:31,893 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1433601366] [2019-12-07 15:22:31,893 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:22:31,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:22:31,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:22:31,926 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1433601366] [2019-12-07 15:22:31,926 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:22:31,926 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:22:31,926 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [608636557] [2019-12-07 15:22:31,926 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:22:31,926 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:22:31,927 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:22:31,927 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:22:31,927 INFO L87 Difference]: Start difference. First operand 5523 states and 15585 transitions. Second operand 3 states. [2019-12-07 15:22:31,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:22:31,963 INFO L93 Difference]: Finished difference Result 5523 states and 15584 transitions. [2019-12-07 15:22:31,964 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:22:31,964 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 15:22:31,964 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:22:31,970 INFO L225 Difference]: With dead ends: 5523 [2019-12-07 15:22:31,970 INFO L226 Difference]: Without dead ends: 5523 [2019-12-07 15:22:31,970 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:22:31,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5523 states. [2019-12-07 15:22:32,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5523 to 4836. [2019-12-07 15:22:32,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4836 states. [2019-12-07 15:22:32,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4836 states to 4836 states and 13729 transitions. [2019-12-07 15:22:32,033 INFO L78 Accepts]: Start accepts. Automaton has 4836 states and 13729 transitions. Word has length 66 [2019-12-07 15:22:32,033 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:22:32,033 INFO L462 AbstractCegarLoop]: Abstraction has 4836 states and 13729 transitions. [2019-12-07 15:22:32,033 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:22:32,033 INFO L276 IsEmpty]: Start isEmpty. Operand 4836 states and 13729 transitions. [2019-12-07 15:22:32,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 15:22:32,037 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:22:32,037 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:22:32,037 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:22:32,037 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:22:32,037 INFO L82 PathProgramCache]: Analyzing trace with hash 486159966, now seen corresponding path program 1 times [2019-12-07 15:22:32,037 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:22:32,037 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2090900698] [2019-12-07 15:22:32,038 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:22:32,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:22:32,108 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:22:32,108 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2090900698] [2019-12-07 15:22:32,108 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:22:32,108 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 15:22:32,109 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [205227056] [2019-12-07 15:22:32,109 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:22:32,109 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:22:32,109 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:22:32,109 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:22:32,109 INFO L87 Difference]: Start difference. First operand 4836 states and 13729 transitions. Second operand 6 states. [2019-12-07 15:22:32,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:22:32,161 INFO L93 Difference]: Finished difference Result 7803 states and 22141 transitions. [2019-12-07 15:22:32,161 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 15:22:32,161 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 67 [2019-12-07 15:22:32,161 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:22:32,164 INFO L225 Difference]: With dead ends: 7803 [2019-12-07 15:22:32,164 INFO L226 Difference]: Without dead ends: 3791 [2019-12-07 15:22:32,165 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:22:32,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3791 states. [2019-12-07 15:22:32,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3791 to 3791. [2019-12-07 15:22:32,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3791 states. [2019-12-07 15:22:32,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3791 states to 3791 states and 10720 transitions. [2019-12-07 15:22:32,208 INFO L78 Accepts]: Start accepts. Automaton has 3791 states and 10720 transitions. Word has length 67 [2019-12-07 15:22:32,208 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:22:32,208 INFO L462 AbstractCegarLoop]: Abstraction has 3791 states and 10720 transitions. [2019-12-07 15:22:32,208 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:22:32,208 INFO L276 IsEmpty]: Start isEmpty. Operand 3791 states and 10720 transitions. [2019-12-07 15:22:32,211 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 15:22:32,211 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:22:32,211 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:22:32,211 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:22:32,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:22:32,211 INFO L82 PathProgramCache]: Analyzing trace with hash -1374987048, now seen corresponding path program 2 times [2019-12-07 15:22:32,211 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:22:32,211 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [892984654] [2019-12-07 15:22:32,212 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:22:32,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:22:32,287 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:22:32,288 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [892984654] [2019-12-07 15:22:32,288 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:22:32,288 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 15:22:32,288 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2137959082] [2019-12-07 15:22:32,288 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:22:32,288 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:22:32,288 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:22:32,288 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:22:32,288 INFO L87 Difference]: Start difference. First operand 3791 states and 10720 transitions. Second operand 6 states. [2019-12-07 15:22:32,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:22:32,344 INFO L93 Difference]: Finished difference Result 6062 states and 17286 transitions. [2019-12-07 15:22:32,344 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 15:22:32,345 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 67 [2019-12-07 15:22:32,345 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:22:32,347 INFO L225 Difference]: With dead ends: 6062 [2019-12-07 15:22:32,347 INFO L226 Difference]: Without dead ends: 2467 [2019-12-07 15:22:32,347 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:22:32,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2467 states. [2019-12-07 15:22:32,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2467 to 2467. [2019-12-07 15:22:32,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2467 states. [2019-12-07 15:22:32,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2467 states to 2467 states and 7137 transitions. [2019-12-07 15:22:32,381 INFO L78 Accepts]: Start accepts. Automaton has 2467 states and 7137 transitions. Word has length 67 [2019-12-07 15:22:32,381 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:22:32,381 INFO L462 AbstractCegarLoop]: Abstraction has 2467 states and 7137 transitions. [2019-12-07 15:22:32,381 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:22:32,381 INFO L276 IsEmpty]: Start isEmpty. Operand 2467 states and 7137 transitions. [2019-12-07 15:22:32,383 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 15:22:32,383 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:22:32,383 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:22:32,384 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:22:32,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:22:32,384 INFO L82 PathProgramCache]: Analyzing trace with hash -247337982, now seen corresponding path program 3 times [2019-12-07 15:22:32,384 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:22:32,384 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [958141608] [2019-12-07 15:22:32,384 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:22:32,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:22:32,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:22:32,462 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [958141608] [2019-12-07 15:22:32,462 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:22:32,462 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 15:22:32,462 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1048179510] [2019-12-07 15:22:32,462 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 15:22:32,462 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:22:32,463 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 15:22:32,463 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-12-07 15:22:32,463 INFO L87 Difference]: Start difference. First operand 2467 states and 7137 transitions. Second operand 8 states. [2019-12-07 15:22:32,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:22:32,842 INFO L93 Difference]: Finished difference Result 4272 states and 12104 transitions. [2019-12-07 15:22:32,842 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 15:22:32,842 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 67 [2019-12-07 15:22:32,842 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:22:32,845 INFO L225 Difference]: With dead ends: 4272 [2019-12-07 15:22:32,845 INFO L226 Difference]: Without dead ends: 4272 [2019-12-07 15:22:32,846 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=65, Unknown=0, NotChecked=0, Total=90 [2019-12-07 15:22:32,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4272 states. [2019-12-07 15:22:32,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4272 to 2504. [2019-12-07 15:22:32,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2504 states. [2019-12-07 15:22:32,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2504 states to 2504 states and 7253 transitions. [2019-12-07 15:22:32,887 INFO L78 Accepts]: Start accepts. Automaton has 2504 states and 7253 transitions. Word has length 67 [2019-12-07 15:22:32,887 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:22:32,887 INFO L462 AbstractCegarLoop]: Abstraction has 2504 states and 7253 transitions. [2019-12-07 15:22:32,887 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 15:22:32,887 INFO L276 IsEmpty]: Start isEmpty. Operand 2504 states and 7253 transitions. [2019-12-07 15:22:32,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 15:22:32,889 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:22:32,889 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:22:32,889 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:22:32,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:22:32,890 INFO L82 PathProgramCache]: Analyzing trace with hash -2047410026, now seen corresponding path program 4 times [2019-12-07 15:22:32,890 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:22:32,890 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598394257] [2019-12-07 15:22:32,890 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:22:32,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:22:32,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:22:32,917 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1598394257] [2019-12-07 15:22:32,917 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:22:32,917 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:22:32,917 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1272568907] [2019-12-07 15:22:32,917 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:22:32,917 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:22:32,917 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:22:32,918 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:22:32,918 INFO L87 Difference]: Start difference. First operand 2504 states and 7253 transitions. Second operand 3 states. [2019-12-07 15:22:32,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:22:32,928 INFO L93 Difference]: Finished difference Result 2200 states and 6194 transitions. [2019-12-07 15:22:32,929 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:22:32,929 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 15:22:32,929 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:22:32,930 INFO L225 Difference]: With dead ends: 2200 [2019-12-07 15:22:32,930 INFO L226 Difference]: Without dead ends: 2200 [2019-12-07 15:22:32,931 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:22:32,941 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2200 states. [2019-12-07 15:22:32,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2200 to 2200. [2019-12-07 15:22:32,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2200 states. [2019-12-07 15:22:32,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2200 states to 2200 states and 6194 transitions. [2019-12-07 15:22:32,958 INFO L78 Accepts]: Start accepts. Automaton has 2200 states and 6194 transitions. Word has length 67 [2019-12-07 15:22:32,958 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:22:32,958 INFO L462 AbstractCegarLoop]: Abstraction has 2200 states and 6194 transitions. [2019-12-07 15:22:32,958 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:22:32,958 INFO L276 IsEmpty]: Start isEmpty. Operand 2200 states and 6194 transitions. [2019-12-07 15:22:32,960 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 15:22:32,960 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:22:32,960 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:22:32,960 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:22:32,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:22:32,960 INFO L82 PathProgramCache]: Analyzing trace with hash -1259160564, now seen corresponding path program 1 times [2019-12-07 15:22:32,960 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:22:32,960 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [477961061] [2019-12-07 15:22:32,960 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:22:32,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 15:22:32,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 15:22:33,032 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 15:22:33,032 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 15:22:33,034 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] ULTIMATE.startENTRY-->L805: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= 0 v_~x~0_194) (= 0 v_~x$r_buff0_thd2~0_213) (= 0 v_~weak$$choice0~0_14) (= v_~x$mem_tmp~0_19 0) (= 0 v_~x$w_buff0~0_268) (= (select .cse0 |v_ULTIMATE.start_main_~#t1816~0.base_20|) 0) (= 0 v_~x$r_buff1_thd2~0_212) (= v_~x$r_buff1_thd0~0_297 0) (< 0 |v_#StackHeapBarrier_17|) (= 0 v_~x$read_delayed_var~0.base_7) (= 0 |v_ULTIMATE.start_main_~#t1816~0.offset_17|) (= v_~x$r_buff1_thd1~0_187 0) (= v_~x$r_buff0_thd0~0_372 0) (= v_~y~0_143 0) (= 0 v_~x$read_delayed~0_6) (= v_~__unbuffered_cnt~0_155 0) (= 0 v_~x$w_buff1~0_230) (= 0 |v_#NULL.base_4|) (= 0 v_~__unbuffered_p0_EAX~0_24) (= 0 v_~x$r_buff1_thd3~0_195) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1816~0.base_20| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1816~0.base_20|) |v_ULTIMATE.start_main_~#t1816~0.offset_17| 0)) |v_#memory_int_21|) (= (store |v_#length_26| |v_ULTIMATE.start_main_~#t1816~0.base_20| 4) |v_#length_25|) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t1816~0.base_20|) (= 0 v_~x$r_buff0_thd3~0_123) (= |v_#NULL.offset_4| 0) (= 0 v_~x$w_buff1_used~0_504) (= 0 v_~x$read_delayed_var~0.offset_7) (= v_~x$r_buff0_thd1~0_120 0) (= 0 v_~__unbuffered_p2_EAX~0_22) (= v_~x$flush_delayed~0_34 0) (= v_~main$tmp_guard0~0_24 0) (= v_~weak$$choice2~0_110 0) (= 0 v_~x$w_buff0_used~0_807) (= |v_#valid_53| (store .cse0 |v_ULTIMATE.start_main_~#t1816~0.base_20| 1)) (= v_~main$tmp_guard1~0_22 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_22|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_21|, ~x$w_buff0~0=v_~x$w_buff0~0_268, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_27|, ~x$flush_delayed~0=v_~x$flush_delayed~0_34, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_39|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_29|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_45|, ULTIMATE.start_main_~#t1818~0.offset=|v_ULTIMATE.start_main_~#t1818~0.offset_16|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_187, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_123, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_50|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_36|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_45|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_32|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_24, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_22, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_372, ULTIMATE.start_main_~#t1816~0.offset=|v_ULTIMATE.start_main_~#t1816~0.offset_17|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_37|, ULTIMATE.start_main_~#t1817~0.base=|v_ULTIMATE.start_main_~#t1817~0.base_21|, ~x$w_buff1~0=v_~x$w_buff1~0_230, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_504, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_212, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_48|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_111|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_7, ULTIMATE.start_main_~#t1816~0.base=|v_ULTIMATE.start_main_~#t1816~0.base_20|, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_32|, ULTIMATE.start_main_~#t1817~0.offset=|v_ULTIMATE.start_main_~#t1817~0.offset_17|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_155, ~x~0=v_~x~0_194, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_120, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_33|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_31|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_29|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_195, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_22, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_125|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_17|, ~x$mem_tmp~0=v_~x$mem_tmp~0_19, ULTIMATE.start_main_~#t1818~0.base=|v_ULTIMATE.start_main_~#t1818~0.base_20|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_25|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_31|, ~y~0=v_~y~0_143, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_10|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_23|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_25|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_48|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_297, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_213, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_59|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_38|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_807, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_32|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_7, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_21|, ~weak$$choice2~0=v_~weak$$choice2~0_110, ~x$read_delayed~0=v_~x$read_delayed~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ~x$w_buff0~0, ULTIMATE.start_main_#t~ite28, ~x$flush_delayed~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_~#t1818~0.offset, ~x$r_buff1_thd1~0, ~x$r_buff0_thd3~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~__unbuffered_p0_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~x$r_buff0_thd0~0, ULTIMATE.start_main_~#t1816~0.offset, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_~#t1817~0.base, ~x$w_buff1~0, ULTIMATE.start_main_#t~ite35, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~x$read_delayed_var~0.base, ULTIMATE.start_main_~#t1816~0.base, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_~#t1817~0.offset, ~__unbuffered_cnt~0, ~x~0, ~x$r_buff0_thd1~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~x$r_buff1_thd3~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~x$mem_tmp~0, ULTIMATE.start_main_~#t1818~0.base, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ~y~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~x$w_buff0_used~0, ULTIMATE.start_main_#t~ite41, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_#res, #valid, #memory_int, ~weak$$choice2~0, ~x$read_delayed~0] because there is no mapped edge [2019-12-07 15:22:33,035 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L805-1-->L807: Formula: (and (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t1817~0.base_11| 1)) (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t1817~0.base_11|)) (not (= 0 |v_ULTIMATE.start_main_~#t1817~0.base_11|)) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1817~0.base_11| 4)) (= 0 |v_ULTIMATE.start_main_~#t1817~0.offset_10|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1817~0.base_11|) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1817~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1817~0.base_11|) |v_ULTIMATE.start_main_~#t1817~0.offset_10| 1)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_6|, ULTIMATE.start_main_~#t1817~0.offset=|v_ULTIMATE.start_main_~#t1817~0.offset_10|, ULTIMATE.start_main_~#t1817~0.base=|v_ULTIMATE.start_main_~#t1817~0.base_11|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t1817~0.offset, ULTIMATE.start_main_~#t1817~0.base, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 15:22:33,035 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L807-1-->L809: Formula: (and (= 0 (select |v_#valid_28| |v_ULTIMATE.start_main_~#t1818~0.base_9|)) (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t1818~0.base_9| 4)) (not (= 0 |v_ULTIMATE.start_main_~#t1818~0.base_9|)) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t1818~0.base_9|) (= |v_#memory_int_9| (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t1818~0.base_9| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t1818~0.base_9|) |v_ULTIMATE.start_main_~#t1818~0.offset_8| 2))) (= |v_ULTIMATE.start_main_~#t1818~0.offset_8| 0) (= (store |v_#valid_28| |v_ULTIMATE.start_main_~#t1818~0.base_9| 1) |v_#valid_27|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_28|, #memory_int=|v_#memory_int_10|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_27|, #memory_int=|v_#memory_int_9|, ULTIMATE.start_main_~#t1818~0.offset=|v_ULTIMATE.start_main_~#t1818~0.offset_8|, #length=|v_#length_13|, ULTIMATE.start_main_~#t1818~0.base=|v_ULTIMATE.start_main_~#t1818~0.base_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, ULTIMATE.start_main_~#t1818~0.offset, #length, ULTIMATE.start_main_~#t1818~0.base] because there is no mapped edge [2019-12-07 15:22:33,035 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] P1ENTRY-->L4-3: Formula: (and (not (= 0 v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11)) (= v_P1Thread1of1ForFork1_~arg.offset_9 |v_P1Thread1of1ForFork1_#in~arg.offset_11|) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9| v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11) (= 1 v_~x$w_buff0_used~0_98) (= 2 v_~x$w_buff0~0_31) (= v_P1Thread1of1ForFork1_~arg.base_9 |v_P1Thread1of1ForFork1_#in~arg.base_11|) (= v_~x$w_buff1_used~0_55 v_~x$w_buff0_used~0_99) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9| (ite (not (and (not (= (mod v_~x$w_buff0_used~0_98 256) 0)) (not (= 0 (mod v_~x$w_buff1_used~0_55 256))))) 1 0)) (= v_~x$w_buff0~0_32 v_~x$w_buff1~0_21)) InVars {~x$w_buff0~0=v_~x$w_buff0~0_32, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_11|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_11|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_99} OutVars{P1Thread1of1ForFork1___VERIFIER_assert_~expression=v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11, ~x$w_buff0~0=v_~x$w_buff0~0_31, P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_9, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression=|v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9|, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_9, ~x$w_buff1~0=v_~x$w_buff1~0_21, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_11|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_11|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_55, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_98} AuxVars[] AssignedVars[P1Thread1of1ForFork1___VERIFIER_assert_~expression, ~x$w_buff0~0, P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression, P1Thread1of1ForFork1_~arg.base, ~x$w_buff1~0, ~x$w_buff1_used~0, ~x$w_buff0_used~0] because there is no mapped edge [2019-12-07 15:22:33,037 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L782-2-->L782-4: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff1_thd3~0_In-1164815147 256))) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In-1164815147 256)))) (or (and (not .cse0) (= |P2Thread1of1ForFork2_#t~ite15_Out-1164815147| ~x$w_buff1~0_In-1164815147) (not .cse1)) (and (or .cse0 .cse1) (= ~x~0_In-1164815147 |P2Thread1of1ForFork2_#t~ite15_Out-1164815147|)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-1164815147, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1164815147, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1164815147, ~x~0=~x~0_In-1164815147} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-1164815147|, ~x$w_buff1~0=~x$w_buff1~0_In-1164815147, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1164815147, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1164815147, ~x~0=~x~0_In-1164815147} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 15:22:33,037 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L782-4-->L783: Formula: (= v_~x~0_20 |v_P2Thread1of1ForFork2_#t~ite15_10|) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_10|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_9|, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_5|, ~x~0=v_~x~0_20} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, P2Thread1of1ForFork2_#t~ite16, ~x~0] because there is no mapped edge [2019-12-07 15:22:33,037 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L783-->L783-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In955074735 256))) (.cse0 (= (mod ~x$r_buff0_thd3~0_In955074735 256) 0))) (or (and (not .cse0) (= |P2Thread1of1ForFork2_#t~ite17_Out955074735| 0) (not .cse1)) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork2_#t~ite17_Out955074735| ~x$w_buff0_used~0_In955074735)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In955074735, ~x$w_buff0_used~0=~x$w_buff0_used~0_In955074735} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In955074735, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out955074735|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In955074735} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 15:22:33,037 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L784-->L784-2: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In811517323 256) 0)) (.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In811517323 256))) (.cse3 (= 0 (mod ~x$r_buff1_thd3~0_In811517323 256))) (.cse2 (= (mod ~x$w_buff1_used~0_In811517323 256) 0))) (or (and (= ~x$w_buff1_used~0_In811517323 |P2Thread1of1ForFork2_#t~ite18_Out811517323|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork2_#t~ite18_Out811517323|) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In811517323, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In811517323, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In811517323, ~x$w_buff0_used~0=~x$w_buff0_used~0_In811517323} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In811517323, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In811517323, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In811517323, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out811517323|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In811517323} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 15:22:33,037 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L733-2-->L733-5: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff1_thd1~0_In1602004791 256))) (.cse0 (= |P0Thread1of1ForFork0_#t~ite4_Out1602004791| |P0Thread1of1ForFork0_#t~ite3_Out1602004791|)) (.cse2 (= 0 (mod ~x$w_buff1_used~0_In1602004791 256)))) (or (and .cse0 (= ~x~0_In1602004791 |P0Thread1of1ForFork0_#t~ite3_Out1602004791|) (or .cse1 .cse2)) (and (not .cse1) .cse0 (not .cse2) (= ~x$w_buff1~0_In1602004791 |P0Thread1of1ForFork0_#t~ite3_Out1602004791|)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In1602004791, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1602004791, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In1602004791, ~x~0=~x~0_In1602004791} OutVars{P0Thread1of1ForFork0_#t~ite3=|P0Thread1of1ForFork0_#t~ite3_Out1602004791|, P0Thread1of1ForFork0_#t~ite4=|P0Thread1of1ForFork0_#t~ite4_Out1602004791|, ~x$w_buff1~0=~x$w_buff1~0_In1602004791, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1602004791, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In1602004791, ~x~0=~x~0_In1602004791} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite3, P0Thread1of1ForFork0_#t~ite4] because there is no mapped edge [2019-12-07 15:22:33,038 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [774] [774] L734-->L734-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-421503027 256))) (.cse0 (= 0 (mod ~x$r_buff0_thd1~0_In-421503027 256)))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite5_Out-421503027| 0)) (and (or .cse1 .cse0) (= |P0Thread1of1ForFork0_#t~ite5_Out-421503027| ~x$w_buff0_used~0_In-421503027)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-421503027, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-421503027} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-421503027|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-421503027, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-421503027} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 15:22:33,038 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L735-->L735-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd1~0_In-873733677 256))) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In-873733677 256))) (.cse3 (= 0 (mod ~x$r_buff1_thd1~0_In-873733677 256))) (.cse2 (= (mod ~x$w_buff1_used~0_In-873733677 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite6_Out-873733677| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P0Thread1of1ForFork0_#t~ite6_Out-873733677| ~x$w_buff1_used~0_In-873733677) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-873733677, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-873733677, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-873733677, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-873733677} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out-873733677|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-873733677, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-873733677, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-873733677, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-873733677} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 15:22:33,038 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L785-->L785-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd3~0_In-1439509374 256))) (.cse0 (= (mod ~x$w_buff0_used~0_In-1439509374 256) 0))) (or (and (or .cse0 .cse1) (= ~x$r_buff0_thd3~0_In-1439509374 |P2Thread1of1ForFork2_#t~ite19_Out-1439509374|)) (and (= 0 |P2Thread1of1ForFork2_#t~ite19_Out-1439509374|) (not .cse1) (not .cse0)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1439509374, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1439509374} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1439509374, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-1439509374|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1439509374} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 15:22:33,038 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L786-->L786-2: Formula: (let ((.cse3 (= 0 (mod ~x$r_buff0_thd3~0_In-1726924583 256))) (.cse2 (= (mod ~x$w_buff0_used~0_In-1726924583 256) 0)) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In-1726924583 256))) (.cse0 (= 0 (mod ~x$r_buff1_thd3~0_In-1726924583 256)))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite20_Out-1726924583| ~x$r_buff1_thd3~0_In-1726924583) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0))) (= 0 |P2Thread1of1ForFork2_#t~ite20_Out-1726924583|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1726924583, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1726924583, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1726924583, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1726924583} OutVars{P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-1726924583|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1726924583, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1726924583, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1726924583, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1726924583} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 15:22:33,039 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L786-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74) (= |v_P2Thread1of1ForFork2_#t~ite20_52| v_~x$r_buff1_thd3~0_147)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_52|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_51|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_147, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~x$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 15:22:33,039 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L736-->L736-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In-977152172 256))) (.cse1 (= 0 (mod ~x$r_buff0_thd1~0_In-977152172 256)))) (or (and (= ~x$r_buff0_thd1~0_In-977152172 |P0Thread1of1ForFork0_#t~ite7_Out-977152172|) (or .cse0 .cse1)) (and (not .cse0) (= 0 |P0Thread1of1ForFork0_#t~ite7_Out-977152172|) (not .cse1)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-977152172, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-977152172} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-977152172, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out-977152172|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-977152172} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-12-07 15:22:33,039 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L737-->L737-2: Formula: (let ((.cse1 (= (mod ~x$w_buff1_used~0_In-983752334 256) 0)) (.cse0 (= (mod ~x$r_buff1_thd1~0_In-983752334 256) 0)) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In-983752334 256))) (.cse3 (= 0 (mod ~x$r_buff0_thd1~0_In-983752334 256)))) (or (and (= 0 |P0Thread1of1ForFork0_#t~ite8_Out-983752334|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~x$r_buff1_thd1~0_In-983752334 |P0Thread1of1ForFork0_#t~ite8_Out-983752334|) (or .cse1 .cse0) (or .cse2 .cse3)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-983752334, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-983752334, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-983752334, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-983752334} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-983752334, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-983752334|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-983752334, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-983752334, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-983752334} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 15:22:33,039 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L737-2-->P0EXIT: Formula: (and (= v_~x$r_buff1_thd1~0_61 |v_P0Thread1of1ForFork0_#t~ite8_24|) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_45 1) v_~__unbuffered_cnt~0_44)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_45} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_23|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_44, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_61} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, ~x$r_buff1_thd1~0] because there is no mapped edge [2019-12-07 15:22:33,040 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L763-->L763-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In1289651265 256))) (.cse1 (= 0 (mod ~x$r_buff0_thd2~0_In1289651265 256)))) (or (and (= ~x$w_buff0_used~0_In1289651265 |P1Thread1of1ForFork1_#t~ite11_Out1289651265|) (or .cse0 .cse1)) (and (= 0 |P1Thread1of1ForFork1_#t~ite11_Out1289651265|) (not .cse0) (not .cse1)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1289651265, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1289651265} OutVars{P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out1289651265|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1289651265, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1289651265} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 15:22:33,040 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L764-->L764-2: Formula: (let ((.cse2 (= 0 (mod ~x$w_buff0_used~0_In2045602810 256))) (.cse3 (= 0 (mod ~x$r_buff0_thd2~0_In2045602810 256))) (.cse1 (= 0 (mod ~x$r_buff1_thd2~0_In2045602810 256))) (.cse0 (= (mod ~x$w_buff1_used~0_In2045602810 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork1_#t~ite12_Out2045602810|)) (and (= ~x$w_buff1_used~0_In2045602810 |P1Thread1of1ForFork1_#t~ite12_Out2045602810|) (or .cse2 .cse3) (or .cse1 .cse0)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In2045602810, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In2045602810, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2045602810, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2045602810} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In2045602810, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In2045602810, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out2045602810|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2045602810, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2045602810} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 15:22:33,040 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L765-->L766: Formula: (let ((.cse1 (= ~x$r_buff0_thd2~0_Out1611600846 ~x$r_buff0_thd2~0_In1611600846)) (.cse2 (= 0 (mod ~x$r_buff0_thd2~0_In1611600846 256))) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In1611600846 256)))) (or (and .cse0 .cse1) (and .cse2 .cse1) (and (not .cse2) (= ~x$r_buff0_thd2~0_Out1611600846 0) (not .cse0)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1611600846, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1611600846} OutVars{P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out1611600846|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out1611600846, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1611600846} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-12-07 15:22:33,040 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L766-->L766-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff1_used~0_In1617870127 256))) (.cse1 (= 0 (mod ~x$r_buff1_thd2~0_In1617870127 256))) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In1617870127 256))) (.cse3 (= 0 (mod ~x$r_buff0_thd2~0_In1617870127 256)))) (or (and (= |P1Thread1of1ForFork1_#t~ite14_Out1617870127| ~x$r_buff1_thd2~0_In1617870127) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork1_#t~ite14_Out1617870127| 0)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In1617870127, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1617870127, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1617870127, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1617870127} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In1617870127, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1617870127, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1617870127, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out1617870127|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1617870127} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 15:22:33,041 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L766-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0) (= v_~x$r_buff1_thd2~0_162 |v_P1Thread1of1ForFork1_#t~ite14_40|) (= (+ v_~__unbuffered_cnt~0_93 1) v_~__unbuffered_cnt~0_92)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_93, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_40|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_162, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_92, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_39|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 15:22:33,041 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L809-1-->L815: Formula: (and (= v_~main$tmp_guard0~0_6 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= 0 (mod v_~main$tmp_guard0~0_6 256)))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 15:22:33,041 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L815-2-->L815-5: Formula: (let ((.cse2 (= (mod ~x$r_buff1_thd0~0_In1854309493 256) 0)) (.cse0 (= 0 (mod ~x$w_buff1_used~0_In1854309493 256))) (.cse1 (= |ULTIMATE.start_main_#t~ite24_Out1854309493| |ULTIMATE.start_main_#t~ite25_Out1854309493|))) (or (and (= |ULTIMATE.start_main_#t~ite24_Out1854309493| ~x$w_buff1~0_In1854309493) (not .cse0) .cse1 (not .cse2)) (and (or .cse2 .cse0) .cse1 (= |ULTIMATE.start_main_#t~ite24_Out1854309493| ~x~0_In1854309493)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In1854309493, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1854309493, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1854309493, ~x~0=~x~0_In1854309493} OutVars{~x$w_buff1~0=~x$w_buff1~0_In1854309493, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out1854309493|, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out1854309493|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1854309493, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1854309493, ~x~0=~x~0_In1854309493} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 15:22:33,041 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L816-->L816-2: Formula: (let ((.cse0 (= (mod ~x$r_buff0_thd0~0_In-351401773 256) 0)) (.cse1 (= (mod ~x$w_buff0_used~0_In-351401773 256) 0))) (or (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In-351401773 |ULTIMATE.start_main_#t~ite26_Out-351401773|)) (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite26_Out-351401773|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-351401773, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-351401773} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-351401773, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-351401773|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-351401773} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 15:22:33,042 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L817-->L817-2: Formula: (let ((.cse0 (= (mod ~x$r_buff0_thd0~0_In1642485235 256) 0)) (.cse1 (= (mod ~x$w_buff0_used~0_In1642485235 256) 0)) (.cse2 (= (mod ~x$r_buff1_thd0~0_In1642485235 256) 0)) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In1642485235 256)))) (or (and (= |ULTIMATE.start_main_#t~ite27_Out1642485235| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (= ~x$w_buff1_used~0_In1642485235 |ULTIMATE.start_main_#t~ite27_Out1642485235|) (or .cse2 .cse3)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1642485235, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1642485235, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1642485235, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1642485235} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1642485235, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1642485235, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out1642485235|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1642485235, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1642485235} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 15:22:33,042 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L818-->L818-2: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In-1015885778 256) 0)) (.cse0 (= 0 (mod ~x$r_buff0_thd0~0_In-1015885778 256)))) (or (and (= |ULTIMATE.start_main_#t~ite28_Out-1015885778| ~x$r_buff0_thd0~0_In-1015885778) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite28_Out-1015885778| 0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1015885778, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1015885778} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1015885778, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out-1015885778|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1015885778} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 15:22:33,042 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L819-->L819-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In998426978 256))) (.cse0 (= (mod ~x$r_buff0_thd0~0_In998426978 256) 0)) (.cse3 (= (mod ~x$w_buff1_used~0_In998426978 256) 0)) (.cse2 (= 0 (mod ~x$r_buff1_thd0~0_In998426978 256)))) (or (and (= |ULTIMATE.start_main_#t~ite29_Out998426978| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~x$r_buff1_thd0~0_In998426978 |ULTIMATE.start_main_#t~ite29_Out998426978|) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In998426978, ~x$w_buff1_used~0=~x$w_buff1_used~0_In998426978, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In998426978, ~x$w_buff0_used~0=~x$w_buff0_used~0_In998426978} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In998426978, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out998426978|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In998426978, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In998426978, ~x$w_buff0_used~0=~x$w_buff0_used~0_In998426978} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 15:22:33,045 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L831-->L832: Formula: (and (= v_~x$r_buff0_thd0~0_112 v_~x$r_buff0_thd0~0_111) (not (= (mod v_~weak$$choice2~0_23 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_112, ~weak$$choice2~0=v_~weak$$choice2~0_23} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_111, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_6|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_10|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_6|, ~weak$$choice2~0=v_~weak$$choice2~0_23} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 15:22:33,045 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L834-->L837-1: Formula: (and (= (mod v_~main$tmp_guard1~0_13 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (not (= (mod v_~x$flush_delayed~0_23 256) 0)) (= v_~x$mem_tmp~0_13 v_~x~0_153) (= v_~x$flush_delayed~0_22 0)) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_23, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_13, ~x$mem_tmp~0=v_~x$mem_tmp~0_13} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_18|, ~x$flush_delayed~0=v_~x$flush_delayed~0_22, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_13, ~x$mem_tmp~0=v_~x$mem_tmp~0_13, ~x~0=v_~x~0_153, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ~x$flush_delayed~0, ~x~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 15:22:33,045 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L837-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 15:22:33,097 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 03:22:33 BasicIcfg [2019-12-07 15:22:33,097 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 15:22:33,097 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 15:22:33,097 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 15:22:33,097 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 15:22:33,098 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 03:19:38" (3/4) ... [2019-12-07 15:22:33,099 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 15:22:33,099 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] ULTIMATE.startENTRY-->L805: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= 0 v_~x~0_194) (= 0 v_~x$r_buff0_thd2~0_213) (= 0 v_~weak$$choice0~0_14) (= v_~x$mem_tmp~0_19 0) (= 0 v_~x$w_buff0~0_268) (= (select .cse0 |v_ULTIMATE.start_main_~#t1816~0.base_20|) 0) (= 0 v_~x$r_buff1_thd2~0_212) (= v_~x$r_buff1_thd0~0_297 0) (< 0 |v_#StackHeapBarrier_17|) (= 0 v_~x$read_delayed_var~0.base_7) (= 0 |v_ULTIMATE.start_main_~#t1816~0.offset_17|) (= v_~x$r_buff1_thd1~0_187 0) (= v_~x$r_buff0_thd0~0_372 0) (= v_~y~0_143 0) (= 0 v_~x$read_delayed~0_6) (= v_~__unbuffered_cnt~0_155 0) (= 0 v_~x$w_buff1~0_230) (= 0 |v_#NULL.base_4|) (= 0 v_~__unbuffered_p0_EAX~0_24) (= 0 v_~x$r_buff1_thd3~0_195) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1816~0.base_20| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1816~0.base_20|) |v_ULTIMATE.start_main_~#t1816~0.offset_17| 0)) |v_#memory_int_21|) (= (store |v_#length_26| |v_ULTIMATE.start_main_~#t1816~0.base_20| 4) |v_#length_25|) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t1816~0.base_20|) (= 0 v_~x$r_buff0_thd3~0_123) (= |v_#NULL.offset_4| 0) (= 0 v_~x$w_buff1_used~0_504) (= 0 v_~x$read_delayed_var~0.offset_7) (= v_~x$r_buff0_thd1~0_120 0) (= 0 v_~__unbuffered_p2_EAX~0_22) (= v_~x$flush_delayed~0_34 0) (= v_~main$tmp_guard0~0_24 0) (= v_~weak$$choice2~0_110 0) (= 0 v_~x$w_buff0_used~0_807) (= |v_#valid_53| (store .cse0 |v_ULTIMATE.start_main_~#t1816~0.base_20| 1)) (= v_~main$tmp_guard1~0_22 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_22|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_21|, ~x$w_buff0~0=v_~x$w_buff0~0_268, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_27|, ~x$flush_delayed~0=v_~x$flush_delayed~0_34, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_39|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_29|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_45|, ULTIMATE.start_main_~#t1818~0.offset=|v_ULTIMATE.start_main_~#t1818~0.offset_16|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_187, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_123, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_50|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_36|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_45|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_32|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_24, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_22, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_372, ULTIMATE.start_main_~#t1816~0.offset=|v_ULTIMATE.start_main_~#t1816~0.offset_17|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_37|, ULTIMATE.start_main_~#t1817~0.base=|v_ULTIMATE.start_main_~#t1817~0.base_21|, ~x$w_buff1~0=v_~x$w_buff1~0_230, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_504, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_212, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_48|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_111|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_7, ULTIMATE.start_main_~#t1816~0.base=|v_ULTIMATE.start_main_~#t1816~0.base_20|, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_32|, ULTIMATE.start_main_~#t1817~0.offset=|v_ULTIMATE.start_main_~#t1817~0.offset_17|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_155, ~x~0=v_~x~0_194, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_120, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_33|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_31|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_29|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_195, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_22, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_125|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_17|, ~x$mem_tmp~0=v_~x$mem_tmp~0_19, ULTIMATE.start_main_~#t1818~0.base=|v_ULTIMATE.start_main_~#t1818~0.base_20|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_25|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_31|, ~y~0=v_~y~0_143, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_10|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_23|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_25|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_48|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_297, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_213, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_59|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_38|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_807, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_32|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_7, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_21|, ~weak$$choice2~0=v_~weak$$choice2~0_110, ~x$read_delayed~0=v_~x$read_delayed~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ~x$w_buff0~0, ULTIMATE.start_main_#t~ite28, ~x$flush_delayed~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_~#t1818~0.offset, ~x$r_buff1_thd1~0, ~x$r_buff0_thd3~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~__unbuffered_p0_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~x$r_buff0_thd0~0, ULTIMATE.start_main_~#t1816~0.offset, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_~#t1817~0.base, ~x$w_buff1~0, ULTIMATE.start_main_#t~ite35, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~x$read_delayed_var~0.base, ULTIMATE.start_main_~#t1816~0.base, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_~#t1817~0.offset, ~__unbuffered_cnt~0, ~x~0, ~x$r_buff0_thd1~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~x$r_buff1_thd3~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~x$mem_tmp~0, ULTIMATE.start_main_~#t1818~0.base, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ~y~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~x$w_buff0_used~0, ULTIMATE.start_main_#t~ite41, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_#res, #valid, #memory_int, ~weak$$choice2~0, ~x$read_delayed~0] because there is no mapped edge [2019-12-07 15:22:33,100 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L805-1-->L807: Formula: (and (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t1817~0.base_11| 1)) (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t1817~0.base_11|)) (not (= 0 |v_ULTIMATE.start_main_~#t1817~0.base_11|)) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1817~0.base_11| 4)) (= 0 |v_ULTIMATE.start_main_~#t1817~0.offset_10|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1817~0.base_11|) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1817~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1817~0.base_11|) |v_ULTIMATE.start_main_~#t1817~0.offset_10| 1)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_6|, ULTIMATE.start_main_~#t1817~0.offset=|v_ULTIMATE.start_main_~#t1817~0.offset_10|, ULTIMATE.start_main_~#t1817~0.base=|v_ULTIMATE.start_main_~#t1817~0.base_11|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t1817~0.offset, ULTIMATE.start_main_~#t1817~0.base, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 15:22:33,100 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L807-1-->L809: Formula: (and (= 0 (select |v_#valid_28| |v_ULTIMATE.start_main_~#t1818~0.base_9|)) (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t1818~0.base_9| 4)) (not (= 0 |v_ULTIMATE.start_main_~#t1818~0.base_9|)) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t1818~0.base_9|) (= |v_#memory_int_9| (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t1818~0.base_9| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t1818~0.base_9|) |v_ULTIMATE.start_main_~#t1818~0.offset_8| 2))) (= |v_ULTIMATE.start_main_~#t1818~0.offset_8| 0) (= (store |v_#valid_28| |v_ULTIMATE.start_main_~#t1818~0.base_9| 1) |v_#valid_27|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_28|, #memory_int=|v_#memory_int_10|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_27|, #memory_int=|v_#memory_int_9|, ULTIMATE.start_main_~#t1818~0.offset=|v_ULTIMATE.start_main_~#t1818~0.offset_8|, #length=|v_#length_13|, ULTIMATE.start_main_~#t1818~0.base=|v_ULTIMATE.start_main_~#t1818~0.base_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, ULTIMATE.start_main_~#t1818~0.offset, #length, ULTIMATE.start_main_~#t1818~0.base] because there is no mapped edge [2019-12-07 15:22:33,100 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] P1ENTRY-->L4-3: Formula: (and (not (= 0 v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11)) (= v_P1Thread1of1ForFork1_~arg.offset_9 |v_P1Thread1of1ForFork1_#in~arg.offset_11|) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9| v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11) (= 1 v_~x$w_buff0_used~0_98) (= 2 v_~x$w_buff0~0_31) (= v_P1Thread1of1ForFork1_~arg.base_9 |v_P1Thread1of1ForFork1_#in~arg.base_11|) (= v_~x$w_buff1_used~0_55 v_~x$w_buff0_used~0_99) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9| (ite (not (and (not (= (mod v_~x$w_buff0_used~0_98 256) 0)) (not (= 0 (mod v_~x$w_buff1_used~0_55 256))))) 1 0)) (= v_~x$w_buff0~0_32 v_~x$w_buff1~0_21)) InVars {~x$w_buff0~0=v_~x$w_buff0~0_32, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_11|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_11|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_99} OutVars{P1Thread1of1ForFork1___VERIFIER_assert_~expression=v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11, ~x$w_buff0~0=v_~x$w_buff0~0_31, P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_9, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression=|v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9|, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_9, ~x$w_buff1~0=v_~x$w_buff1~0_21, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_11|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_11|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_55, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_98} AuxVars[] AssignedVars[P1Thread1of1ForFork1___VERIFIER_assert_~expression, ~x$w_buff0~0, P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression, P1Thread1of1ForFork1_~arg.base, ~x$w_buff1~0, ~x$w_buff1_used~0, ~x$w_buff0_used~0] because there is no mapped edge [2019-12-07 15:22:33,101 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L782-2-->L782-4: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff1_thd3~0_In-1164815147 256))) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In-1164815147 256)))) (or (and (not .cse0) (= |P2Thread1of1ForFork2_#t~ite15_Out-1164815147| ~x$w_buff1~0_In-1164815147) (not .cse1)) (and (or .cse0 .cse1) (= ~x~0_In-1164815147 |P2Thread1of1ForFork2_#t~ite15_Out-1164815147|)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-1164815147, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1164815147, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1164815147, ~x~0=~x~0_In-1164815147} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-1164815147|, ~x$w_buff1~0=~x$w_buff1~0_In-1164815147, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1164815147, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1164815147, ~x~0=~x~0_In-1164815147} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 15:22:33,101 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L782-4-->L783: Formula: (= v_~x~0_20 |v_P2Thread1of1ForFork2_#t~ite15_10|) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_10|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_9|, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_5|, ~x~0=v_~x~0_20} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, P2Thread1of1ForFork2_#t~ite16, ~x~0] because there is no mapped edge [2019-12-07 15:22:33,101 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L783-->L783-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In955074735 256))) (.cse0 (= (mod ~x$r_buff0_thd3~0_In955074735 256) 0))) (or (and (not .cse0) (= |P2Thread1of1ForFork2_#t~ite17_Out955074735| 0) (not .cse1)) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork2_#t~ite17_Out955074735| ~x$w_buff0_used~0_In955074735)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In955074735, ~x$w_buff0_used~0=~x$w_buff0_used~0_In955074735} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In955074735, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out955074735|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In955074735} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 15:22:33,102 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L784-->L784-2: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In811517323 256) 0)) (.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In811517323 256))) (.cse3 (= 0 (mod ~x$r_buff1_thd3~0_In811517323 256))) (.cse2 (= (mod ~x$w_buff1_used~0_In811517323 256) 0))) (or (and (= ~x$w_buff1_used~0_In811517323 |P2Thread1of1ForFork2_#t~ite18_Out811517323|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork2_#t~ite18_Out811517323|) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In811517323, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In811517323, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In811517323, ~x$w_buff0_used~0=~x$w_buff0_used~0_In811517323} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In811517323, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In811517323, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In811517323, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out811517323|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In811517323} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 15:22:33,102 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L733-2-->L733-5: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff1_thd1~0_In1602004791 256))) (.cse0 (= |P0Thread1of1ForFork0_#t~ite4_Out1602004791| |P0Thread1of1ForFork0_#t~ite3_Out1602004791|)) (.cse2 (= 0 (mod ~x$w_buff1_used~0_In1602004791 256)))) (or (and .cse0 (= ~x~0_In1602004791 |P0Thread1of1ForFork0_#t~ite3_Out1602004791|) (or .cse1 .cse2)) (and (not .cse1) .cse0 (not .cse2) (= ~x$w_buff1~0_In1602004791 |P0Thread1of1ForFork0_#t~ite3_Out1602004791|)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In1602004791, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1602004791, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In1602004791, ~x~0=~x~0_In1602004791} OutVars{P0Thread1of1ForFork0_#t~ite3=|P0Thread1of1ForFork0_#t~ite3_Out1602004791|, P0Thread1of1ForFork0_#t~ite4=|P0Thread1of1ForFork0_#t~ite4_Out1602004791|, ~x$w_buff1~0=~x$w_buff1~0_In1602004791, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1602004791, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In1602004791, ~x~0=~x~0_In1602004791} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite3, P0Thread1of1ForFork0_#t~ite4] because there is no mapped edge [2019-12-07 15:22:33,102 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [774] [774] L734-->L734-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-421503027 256))) (.cse0 (= 0 (mod ~x$r_buff0_thd1~0_In-421503027 256)))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite5_Out-421503027| 0)) (and (or .cse1 .cse0) (= |P0Thread1of1ForFork0_#t~ite5_Out-421503027| ~x$w_buff0_used~0_In-421503027)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-421503027, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-421503027} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-421503027|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-421503027, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-421503027} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 15:22:33,102 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L735-->L735-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd1~0_In-873733677 256))) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In-873733677 256))) (.cse3 (= 0 (mod ~x$r_buff1_thd1~0_In-873733677 256))) (.cse2 (= (mod ~x$w_buff1_used~0_In-873733677 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite6_Out-873733677| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P0Thread1of1ForFork0_#t~ite6_Out-873733677| ~x$w_buff1_used~0_In-873733677) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-873733677, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-873733677, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-873733677, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-873733677} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out-873733677|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-873733677, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-873733677, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-873733677, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-873733677} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 15:22:33,102 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L785-->L785-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd3~0_In-1439509374 256))) (.cse0 (= (mod ~x$w_buff0_used~0_In-1439509374 256) 0))) (or (and (or .cse0 .cse1) (= ~x$r_buff0_thd3~0_In-1439509374 |P2Thread1of1ForFork2_#t~ite19_Out-1439509374|)) (and (= 0 |P2Thread1of1ForFork2_#t~ite19_Out-1439509374|) (not .cse1) (not .cse0)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1439509374, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1439509374} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1439509374, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-1439509374|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1439509374} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 15:22:33,103 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L786-->L786-2: Formula: (let ((.cse3 (= 0 (mod ~x$r_buff0_thd3~0_In-1726924583 256))) (.cse2 (= (mod ~x$w_buff0_used~0_In-1726924583 256) 0)) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In-1726924583 256))) (.cse0 (= 0 (mod ~x$r_buff1_thd3~0_In-1726924583 256)))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite20_Out-1726924583| ~x$r_buff1_thd3~0_In-1726924583) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0))) (= 0 |P2Thread1of1ForFork2_#t~ite20_Out-1726924583|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1726924583, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1726924583, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1726924583, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1726924583} OutVars{P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-1726924583|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1726924583, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1726924583, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1726924583, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1726924583} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 15:22:33,103 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L786-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74) (= |v_P2Thread1of1ForFork2_#t~ite20_52| v_~x$r_buff1_thd3~0_147)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_52|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_51|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_147, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~x$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 15:22:33,103 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L736-->L736-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In-977152172 256))) (.cse1 (= 0 (mod ~x$r_buff0_thd1~0_In-977152172 256)))) (or (and (= ~x$r_buff0_thd1~0_In-977152172 |P0Thread1of1ForFork0_#t~ite7_Out-977152172|) (or .cse0 .cse1)) (and (not .cse0) (= 0 |P0Thread1of1ForFork0_#t~ite7_Out-977152172|) (not .cse1)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-977152172, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-977152172} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-977152172, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out-977152172|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-977152172} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-12-07 15:22:33,104 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L737-->L737-2: Formula: (let ((.cse1 (= (mod ~x$w_buff1_used~0_In-983752334 256) 0)) (.cse0 (= (mod ~x$r_buff1_thd1~0_In-983752334 256) 0)) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In-983752334 256))) (.cse3 (= 0 (mod ~x$r_buff0_thd1~0_In-983752334 256)))) (or (and (= 0 |P0Thread1of1ForFork0_#t~ite8_Out-983752334|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~x$r_buff1_thd1~0_In-983752334 |P0Thread1of1ForFork0_#t~ite8_Out-983752334|) (or .cse1 .cse0) (or .cse2 .cse3)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-983752334, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-983752334, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-983752334, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-983752334} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-983752334, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-983752334|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-983752334, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-983752334, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-983752334} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 15:22:33,104 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L737-2-->P0EXIT: Formula: (and (= v_~x$r_buff1_thd1~0_61 |v_P0Thread1of1ForFork0_#t~ite8_24|) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_45 1) v_~__unbuffered_cnt~0_44)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_45} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_23|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_44, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_61} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, ~x$r_buff1_thd1~0] because there is no mapped edge [2019-12-07 15:22:33,104 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L763-->L763-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In1289651265 256))) (.cse1 (= 0 (mod ~x$r_buff0_thd2~0_In1289651265 256)))) (or (and (= ~x$w_buff0_used~0_In1289651265 |P1Thread1of1ForFork1_#t~ite11_Out1289651265|) (or .cse0 .cse1)) (and (= 0 |P1Thread1of1ForFork1_#t~ite11_Out1289651265|) (not .cse0) (not .cse1)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1289651265, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1289651265} OutVars{P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out1289651265|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1289651265, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1289651265} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 15:22:33,104 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L764-->L764-2: Formula: (let ((.cse2 (= 0 (mod ~x$w_buff0_used~0_In2045602810 256))) (.cse3 (= 0 (mod ~x$r_buff0_thd2~0_In2045602810 256))) (.cse1 (= 0 (mod ~x$r_buff1_thd2~0_In2045602810 256))) (.cse0 (= (mod ~x$w_buff1_used~0_In2045602810 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork1_#t~ite12_Out2045602810|)) (and (= ~x$w_buff1_used~0_In2045602810 |P1Thread1of1ForFork1_#t~ite12_Out2045602810|) (or .cse2 .cse3) (or .cse1 .cse0)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In2045602810, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In2045602810, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2045602810, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2045602810} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In2045602810, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In2045602810, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out2045602810|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2045602810, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2045602810} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 15:22:33,104 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L765-->L766: Formula: (let ((.cse1 (= ~x$r_buff0_thd2~0_Out1611600846 ~x$r_buff0_thd2~0_In1611600846)) (.cse2 (= 0 (mod ~x$r_buff0_thd2~0_In1611600846 256))) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In1611600846 256)))) (or (and .cse0 .cse1) (and .cse2 .cse1) (and (not .cse2) (= ~x$r_buff0_thd2~0_Out1611600846 0) (not .cse0)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1611600846, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1611600846} OutVars{P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out1611600846|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out1611600846, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1611600846} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-12-07 15:22:33,105 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L766-->L766-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff1_used~0_In1617870127 256))) (.cse1 (= 0 (mod ~x$r_buff1_thd2~0_In1617870127 256))) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In1617870127 256))) (.cse3 (= 0 (mod ~x$r_buff0_thd2~0_In1617870127 256)))) (or (and (= |P1Thread1of1ForFork1_#t~ite14_Out1617870127| ~x$r_buff1_thd2~0_In1617870127) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork1_#t~ite14_Out1617870127| 0)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In1617870127, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1617870127, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1617870127, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1617870127} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In1617870127, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1617870127, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1617870127, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out1617870127|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1617870127} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 15:22:33,105 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L766-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0) (= v_~x$r_buff1_thd2~0_162 |v_P1Thread1of1ForFork1_#t~ite14_40|) (= (+ v_~__unbuffered_cnt~0_93 1) v_~__unbuffered_cnt~0_92)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_93, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_40|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_162, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_92, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_39|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 15:22:33,105 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L809-1-->L815: Formula: (and (= v_~main$tmp_guard0~0_6 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= 0 (mod v_~main$tmp_guard0~0_6 256)))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 15:22:33,105 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L815-2-->L815-5: Formula: (let ((.cse2 (= (mod ~x$r_buff1_thd0~0_In1854309493 256) 0)) (.cse0 (= 0 (mod ~x$w_buff1_used~0_In1854309493 256))) (.cse1 (= |ULTIMATE.start_main_#t~ite24_Out1854309493| |ULTIMATE.start_main_#t~ite25_Out1854309493|))) (or (and (= |ULTIMATE.start_main_#t~ite24_Out1854309493| ~x$w_buff1~0_In1854309493) (not .cse0) .cse1 (not .cse2)) (and (or .cse2 .cse0) .cse1 (= |ULTIMATE.start_main_#t~ite24_Out1854309493| ~x~0_In1854309493)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In1854309493, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1854309493, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1854309493, ~x~0=~x~0_In1854309493} OutVars{~x$w_buff1~0=~x$w_buff1~0_In1854309493, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out1854309493|, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out1854309493|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1854309493, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1854309493, ~x~0=~x~0_In1854309493} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 15:22:33,105 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L816-->L816-2: Formula: (let ((.cse0 (= (mod ~x$r_buff0_thd0~0_In-351401773 256) 0)) (.cse1 (= (mod ~x$w_buff0_used~0_In-351401773 256) 0))) (or (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In-351401773 |ULTIMATE.start_main_#t~ite26_Out-351401773|)) (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite26_Out-351401773|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-351401773, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-351401773} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-351401773, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-351401773|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-351401773} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 15:22:33,106 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L817-->L817-2: Formula: (let ((.cse0 (= (mod ~x$r_buff0_thd0~0_In1642485235 256) 0)) (.cse1 (= (mod ~x$w_buff0_used~0_In1642485235 256) 0)) (.cse2 (= (mod ~x$r_buff1_thd0~0_In1642485235 256) 0)) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In1642485235 256)))) (or (and (= |ULTIMATE.start_main_#t~ite27_Out1642485235| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (= ~x$w_buff1_used~0_In1642485235 |ULTIMATE.start_main_#t~ite27_Out1642485235|) (or .cse2 .cse3)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1642485235, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1642485235, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1642485235, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1642485235} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1642485235, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1642485235, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out1642485235|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1642485235, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1642485235} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 15:22:33,106 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L818-->L818-2: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In-1015885778 256) 0)) (.cse0 (= 0 (mod ~x$r_buff0_thd0~0_In-1015885778 256)))) (or (and (= |ULTIMATE.start_main_#t~ite28_Out-1015885778| ~x$r_buff0_thd0~0_In-1015885778) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite28_Out-1015885778| 0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1015885778, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1015885778} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1015885778, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out-1015885778|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1015885778} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 15:22:33,106 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L819-->L819-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In998426978 256))) (.cse0 (= (mod ~x$r_buff0_thd0~0_In998426978 256) 0)) (.cse3 (= (mod ~x$w_buff1_used~0_In998426978 256) 0)) (.cse2 (= 0 (mod ~x$r_buff1_thd0~0_In998426978 256)))) (or (and (= |ULTIMATE.start_main_#t~ite29_Out998426978| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~x$r_buff1_thd0~0_In998426978 |ULTIMATE.start_main_#t~ite29_Out998426978|) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In998426978, ~x$w_buff1_used~0=~x$w_buff1_used~0_In998426978, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In998426978, ~x$w_buff0_used~0=~x$w_buff0_used~0_In998426978} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In998426978, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out998426978|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In998426978, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In998426978, ~x$w_buff0_used~0=~x$w_buff0_used~0_In998426978} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 15:22:33,109 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L831-->L832: Formula: (and (= v_~x$r_buff0_thd0~0_112 v_~x$r_buff0_thd0~0_111) (not (= (mod v_~weak$$choice2~0_23 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_112, ~weak$$choice2~0=v_~weak$$choice2~0_23} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_111, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_6|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_10|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_6|, ~weak$$choice2~0=v_~weak$$choice2~0_23} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 15:22:33,109 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L834-->L837-1: Formula: (and (= (mod v_~main$tmp_guard1~0_13 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (not (= (mod v_~x$flush_delayed~0_23 256) 0)) (= v_~x$mem_tmp~0_13 v_~x~0_153) (= v_~x$flush_delayed~0_22 0)) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_23, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_13, ~x$mem_tmp~0=v_~x$mem_tmp~0_13} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_18|, ~x$flush_delayed~0=v_~x$flush_delayed~0_22, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_13, ~x$mem_tmp~0=v_~x$mem_tmp~0_13, ~x~0=v_~x~0_153, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ~x$flush_delayed~0, ~x~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 15:22:33,109 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L837-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 15:22:33,161 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_dded0f1c-e543-47fa-8557-549916ecea08/bin/uautomizer/witness.graphml [2019-12-07 15:22:33,161 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 15:22:33,162 INFO L168 Benchmark]: Toolchain (without parser) took 175863.62 ms. Allocated memory was 1.0 GB in the beginning and 8.8 GB in the end (delta: 7.7 GB). Free memory was 940.7 MB in the beginning and 3.6 GB in the end (delta: -2.7 GB). Peak memory consumption was 5.1 GB. Max. memory is 11.5 GB. [2019-12-07 15:22:33,162 INFO L168 Benchmark]: CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 964.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 15:22:33,163 INFO L168 Benchmark]: CACSL2BoogieTranslator took 401.18 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 112.2 MB). Free memory was 940.7 MB in the beginning and 1.1 GB in the end (delta: -139.2 MB). Peak memory consumption was 28.1 MB. Max. memory is 11.5 GB. [2019-12-07 15:22:33,163 INFO L168 Benchmark]: Boogie Procedure Inliner took 55.05 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2019-12-07 15:22:33,163 INFO L168 Benchmark]: Boogie Preprocessor took 32.60 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2019-12-07 15:22:33,163 INFO L168 Benchmark]: RCFGBuilder took 415.96 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.6 MB). Peak memory consumption was 55.6 MB. Max. memory is 11.5 GB. [2019-12-07 15:22:33,164 INFO L168 Benchmark]: TraceAbstraction took 174891.99 ms. Allocated memory was 1.1 GB in the beginning and 8.8 GB in the end (delta: 7.6 GB). Free memory was 1.0 GB in the beginning and 3.6 GB in the end (delta: -2.6 GB). Peak memory consumption was 5.0 GB. Max. memory is 11.5 GB. [2019-12-07 15:22:33,164 INFO L168 Benchmark]: Witness Printer took 63.83 ms. Allocated memory is still 8.8 GB. Free memory was 3.6 GB in the beginning and 3.6 GB in the end (delta: 37.7 MB). Peak memory consumption was 37.7 MB. Max. memory is 11.5 GB. [2019-12-07 15:22:33,165 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 964.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 401.18 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 112.2 MB). Free memory was 940.7 MB in the beginning and 1.1 GB in the end (delta: -139.2 MB). Peak memory consumption was 28.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 55.05 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 32.60 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 415.96 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.6 MB). Peak memory consumption was 55.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 174891.99 ms. Allocated memory was 1.1 GB in the beginning and 8.8 GB in the end (delta: 7.6 GB). Free memory was 1.0 GB in the beginning and 3.6 GB in the end (delta: -2.6 GB). Peak memory consumption was 5.0 GB. Max. memory is 11.5 GB. * Witness Printer took 63.83 ms. Allocated memory is still 8.8 GB. Free memory was 3.6 GB in the beginning and 3.6 GB in the end (delta: 37.7 MB). Peak memory consumption was 37.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.0s, 174 ProgramPointsBefore, 94 ProgramPointsAfterwards, 211 TransitionsBefore, 106 TransitionsAfterwards, 17074 CoEnabledTransitionPairs, 7 FixpointIterations, 31 TrivialSequentialCompositions, 43 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 37 ConcurrentYvCompositions, 29 ChoiceCompositions, 6159 VarBasedMoverChecksPositive, 253 VarBasedMoverChecksNegative, 78 SemBasedMoverChecksPositive, 250 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.8s, 0 MoverChecksTotal, 78277 CheckedPairsTotal, 111 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L805] FCALL, FORK 0 pthread_create(&t1816, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L807] FCALL, FORK 0 pthread_create(&t1817, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L809] FCALL, FORK 0 pthread_create(&t1818, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L752] 2 x$r_buff1_thd0 = x$r_buff0_thd0 [L753] 2 x$r_buff1_thd1 = x$r_buff0_thd1 [L754] 2 x$r_buff1_thd2 = x$r_buff0_thd2 [L755] 2 x$r_buff1_thd3 = x$r_buff0_thd3 [L756] 2 x$r_buff0_thd2 = (_Bool)1 [L759] 2 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L776] 3 __unbuffered_p2_EAX = y [L779] 3 y = 2 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L727] 1 __unbuffered_p0_EAX = y [L730] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L782] 3 x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd3 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L733] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L783] 3 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$w_buff0_used [L733] 1 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L734] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L784] 3 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd3 || x$w_buff1_used && x$r_buff1_thd3 ? (_Bool)0 : x$w_buff1_used [L785] 3 x$r_buff0_thd3 = x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$r_buff0_thd3 [L762] EXPR 2 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L735] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L736] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L762] 2 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L763] 2 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L764] 2 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L815] EXPR 0 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L815] 0 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L816] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L817] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L818] 0 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L819] 0 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L822] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L823] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L824] 0 x$flush_delayed = weak$$choice2 [L825] 0 x$mem_tmp = x VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L826] EXPR 0 !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L826] 0 x = !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) [L827] EXPR 0 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L827] 0 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) [L828] EXPR 0 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L828] 0 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) [L829] EXPR 0 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L829] 0 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) [L830] EXPR 0 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L830] 0 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L832] EXPR 0 weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L832] 0 x$r_buff1_thd0 = weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L833] 0 main$tmp_guard1 = !(x == 2 && y == 2 && __unbuffered_p0_EAX == 2 && __unbuffered_p2_EAX == 1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 165 locations, 2 error locations. Result: UNSAFE, OverallTime: 174.7s, OverallIterations: 25, TraceHistogramMax: 1, AutomataDifference: 39.2s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 4530 SDtfs, 3759 SDslu, 8419 SDs, 0 SdLazy, 5673 SolverSat, 199 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 4.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 184 GetRequests, 35 SyntacticMatches, 21 SemanticMatches, 128 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 167 ImplicationChecksByTransitivity, 0.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=231837occurred in iteration=9, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 117.1s AutomataMinimizationTime, 24 MinimizatonAttempts, 774000 StatesRemovedByMinimization, 19 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 0.8s InterpolantComputationTime, 993 NumberOfCodeBlocks, 993 NumberOfCodeBlocksAsserted, 25 NumberOfCheckSat, 901 ConstructedInterpolants, 0 QuantifiedInterpolants, 108415 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 24 InterpolantComputations, 24 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...