./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe004_rmo.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_5bb58e17-e56b-4cc0-8c9a-c47783342971/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_5bb58e17-e56b-4cc0-8c9a-c47783342971/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_5bb58e17-e56b-4cc0-8c9a-c47783342971/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_5bb58e17-e56b-4cc0-8c9a-c47783342971/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe004_rmo.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_5bb58e17-e56b-4cc0-8c9a-c47783342971/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_5bb58e17-e56b-4cc0-8c9a-c47783342971/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 73704224f15e258f32f07c3947d9d6e93159608f .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 15:32:04,333 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 15:32:04,334 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 15:32:04,343 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 15:32:04,343 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 15:32:04,344 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 15:32:04,345 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 15:32:04,347 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 15:32:04,349 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 15:32:04,350 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 15:32:04,350 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 15:32:04,352 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 15:32:04,352 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 15:32:04,353 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 15:32:04,353 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 15:32:04,354 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 15:32:04,355 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 15:32:04,356 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 15:32:04,357 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 15:32:04,359 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 15:32:04,360 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 15:32:04,361 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 15:32:04,362 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 15:32:04,363 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 15:32:04,365 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 15:32:04,365 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 15:32:04,365 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 15:32:04,366 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 15:32:04,366 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 15:32:04,367 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 15:32:04,367 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 15:32:04,368 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 15:32:04,369 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 15:32:04,369 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 15:32:04,370 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 15:32:04,370 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 15:32:04,371 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 15:32:04,371 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 15:32:04,371 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 15:32:04,371 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 15:32:04,372 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 15:32:04,372 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_5bb58e17-e56b-4cc0-8c9a-c47783342971/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 15:32:04,384 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 15:32:04,385 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 15:32:04,385 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 15:32:04,386 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 15:32:04,386 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 15:32:04,386 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 15:32:04,386 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 15:32:04,386 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 15:32:04,387 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 15:32:04,387 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 15:32:04,387 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 15:32:04,387 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 15:32:04,387 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 15:32:04,388 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 15:32:04,388 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 15:32:04,388 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 15:32:04,388 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 15:32:04,388 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 15:32:04,389 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 15:32:04,389 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 15:32:04,389 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 15:32:04,389 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 15:32:04,389 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 15:32:04,390 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 15:32:04,390 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 15:32:04,390 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 15:32:04,390 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 15:32:04,390 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 15:32:04,390 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 15:32:04,391 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_5bb58e17-e56b-4cc0-8c9a-c47783342971/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 73704224f15e258f32f07c3947d9d6e93159608f [2019-12-07 15:32:04,493 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 15:32:04,501 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 15:32:04,503 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 15:32:04,505 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 15:32:04,505 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 15:32:04,506 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_5bb58e17-e56b-4cc0-8c9a-c47783342971/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe004_rmo.opt.i [2019-12-07 15:32:04,550 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_5bb58e17-e56b-4cc0-8c9a-c47783342971/bin/uautomizer/data/d4d8b54a3/cda2fca74e844b4c9b5cf58c5202dfc1/FLAGb9eaf53ce [2019-12-07 15:32:04,918 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 15:32:04,918 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_5bb58e17-e56b-4cc0-8c9a-c47783342971/sv-benchmarks/c/pthread-wmm/safe004_rmo.opt.i [2019-12-07 15:32:04,928 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_5bb58e17-e56b-4cc0-8c9a-c47783342971/bin/uautomizer/data/d4d8b54a3/cda2fca74e844b4c9b5cf58c5202dfc1/FLAGb9eaf53ce [2019-12-07 15:32:04,939 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_5bb58e17-e56b-4cc0-8c9a-c47783342971/bin/uautomizer/data/d4d8b54a3/cda2fca74e844b4c9b5cf58c5202dfc1 [2019-12-07 15:32:04,942 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 15:32:04,943 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 15:32:04,944 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 15:32:04,944 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 15:32:04,947 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 15:32:04,948 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 03:32:04" (1/1) ... [2019-12-07 15:32:04,950 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@551fb3cf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:32:04, skipping insertion in model container [2019-12-07 15:32:04,950 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 03:32:04" (1/1) ... [2019-12-07 15:32:04,957 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 15:32:04,991 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 15:32:05,263 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 15:32:05,271 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 15:32:05,315 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 15:32:05,361 INFO L208 MainTranslator]: Completed translation [2019-12-07 15:32:05,361 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:32:05 WrapperNode [2019-12-07 15:32:05,362 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 15:32:05,362 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 15:32:05,362 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 15:32:05,362 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 15:32:05,368 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:32:05" (1/1) ... [2019-12-07 15:32:05,382 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:32:05" (1/1) ... [2019-12-07 15:32:05,404 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 15:32:05,404 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 15:32:05,405 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 15:32:05,405 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 15:32:05,411 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:32:05" (1/1) ... [2019-12-07 15:32:05,411 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:32:05" (1/1) ... [2019-12-07 15:32:05,414 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:32:05" (1/1) ... [2019-12-07 15:32:05,415 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:32:05" (1/1) ... [2019-12-07 15:32:05,422 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:32:05" (1/1) ... [2019-12-07 15:32:05,425 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:32:05" (1/1) ... [2019-12-07 15:32:05,427 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:32:05" (1/1) ... [2019-12-07 15:32:05,431 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 15:32:05,431 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 15:32:05,431 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 15:32:05,431 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 15:32:05,432 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:32:05" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_5bb58e17-e56b-4cc0-8c9a-c47783342971/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 15:32:05,471 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 15:32:05,472 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 15:32:05,472 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 15:32:05,472 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 15:32:05,472 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 15:32:05,472 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 15:32:05,472 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 15:32:05,472 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 15:32:05,472 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 15:32:05,472 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 15:32:05,472 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 15:32:05,473 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 15:32:05,473 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 15:32:05,474 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 15:32:05,841 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 15:32:05,842 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 15:32:05,842 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 03:32:05 BoogieIcfgContainer [2019-12-07 15:32:05,843 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 15:32:05,843 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 15:32:05,844 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 15:32:05,845 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 15:32:05,846 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 03:32:04" (1/3) ... [2019-12-07 15:32:05,846 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@33365e61 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 03:32:05, skipping insertion in model container [2019-12-07 15:32:05,847 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:32:05" (2/3) ... [2019-12-07 15:32:05,847 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@33365e61 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 03:32:05, skipping insertion in model container [2019-12-07 15:32:05,847 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 03:32:05" (3/3) ... [2019-12-07 15:32:05,848 INFO L109 eAbstractionObserver]: Analyzing ICFG safe004_rmo.opt.i [2019-12-07 15:32:05,855 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 15:32:05,855 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 15:32:05,861 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 15:32:05,861 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 15:32:05,888 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,888 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,888 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,888 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,888 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,889 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,889 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,889 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,889 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,889 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,889 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,889 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,890 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,890 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,890 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,890 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,890 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,890 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,890 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,890 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,891 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,891 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,891 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,891 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,891 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,891 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,891 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,892 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,892 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,892 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,893 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,893 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,893 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,893 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,893 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,893 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,893 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,894 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,894 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,894 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,894 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,894 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,895 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,895 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,895 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,895 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,896 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,896 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,896 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,896 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,896 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,896 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,896 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,897 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,897 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,897 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,897 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,897 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,897 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,897 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,897 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,897 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,898 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,898 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,898 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,898 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,898 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,898 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,899 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,899 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,899 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,899 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,899 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,899 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,900 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,900 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,900 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,900 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,900 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,900 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,900 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,901 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,901 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,901 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,901 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,901 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,901 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,902 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,902 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,902 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,902 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,902 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,902 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,902 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:32:05,913 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 15:32:05,925 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 15:32:05,926 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 15:32:05,926 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 15:32:05,926 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 15:32:05,926 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 15:32:05,926 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 15:32:05,926 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 15:32:05,926 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 15:32:05,938 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 174 places, 211 transitions [2019-12-07 15:32:05,940 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 174 places, 211 transitions [2019-12-07 15:32:06,005 INFO L134 PetriNetUnfolder]: 47/208 cut-off events. [2019-12-07 15:32:06,005 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 15:32:06,015 INFO L76 FinitePrefix]: Finished finitePrefix Result has 218 conditions, 208 events. 47/208 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 572 event pairs. 9/168 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 15:32:06,030 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 174 places, 211 transitions [2019-12-07 15:32:06,060 INFO L134 PetriNetUnfolder]: 47/208 cut-off events. [2019-12-07 15:32:06,060 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 15:32:06,065 INFO L76 FinitePrefix]: Finished finitePrefix Result has 218 conditions, 208 events. 47/208 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 572 event pairs. 9/168 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 15:32:06,081 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 17074 [2019-12-07 15:32:06,082 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 15:32:08,877 WARN L192 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 85 [2019-12-07 15:32:08,964 INFO L206 etLargeBlockEncoding]: Checked pairs total: 78277 [2019-12-07 15:32:08,964 INFO L214 etLargeBlockEncoding]: Total number of compositions: 111 [2019-12-07 15:32:08,967 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 94 places, 106 transitions [2019-12-07 15:32:21,731 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 107408 states. [2019-12-07 15:32:21,732 INFO L276 IsEmpty]: Start isEmpty. Operand 107408 states. [2019-12-07 15:32:21,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-12-07 15:32:21,737 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:32:21,738 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-12-07 15:32:21,738 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:32:21,742 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:32:21,742 INFO L82 PathProgramCache]: Analyzing trace with hash 809703812, now seen corresponding path program 1 times [2019-12-07 15:32:21,748 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:32:21,748 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [828081290] [2019-12-07 15:32:21,748 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:32:21,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:32:21,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:32:21,894 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [828081290] [2019-12-07 15:32:21,895 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:32:21,895 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 15:32:21,896 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1983848215] [2019-12-07 15:32:21,899 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:32:21,899 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:32:21,908 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:32:21,908 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:32:21,909 INFO L87 Difference]: Start difference. First operand 107408 states. Second operand 3 states. [2019-12-07 15:32:22,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:32:22,733 INFO L93 Difference]: Finished difference Result 107108 states and 460900 transitions. [2019-12-07 15:32:22,734 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:32:22,735 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 5 [2019-12-07 15:32:22,735 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:32:23,224 INFO L225 Difference]: With dead ends: 107108 [2019-12-07 15:32:23,225 INFO L226 Difference]: Without dead ends: 104924 [2019-12-07 15:32:23,225 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:32:26,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104924 states. [2019-12-07 15:32:27,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104924 to 104924. [2019-12-07 15:32:27,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 104924 states. [2019-12-07 15:32:30,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104924 states to 104924 states and 451982 transitions. [2019-12-07 15:32:30,293 INFO L78 Accepts]: Start accepts. Automaton has 104924 states and 451982 transitions. Word has length 5 [2019-12-07 15:32:30,293 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:32:30,294 INFO L462 AbstractCegarLoop]: Abstraction has 104924 states and 451982 transitions. [2019-12-07 15:32:30,294 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:32:30,294 INFO L276 IsEmpty]: Start isEmpty. Operand 104924 states and 451982 transitions. [2019-12-07 15:32:30,296 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 15:32:30,296 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:32:30,296 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:32:30,296 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:32:30,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:32:30,296 INFO L82 PathProgramCache]: Analyzing trace with hash 2105056515, now seen corresponding path program 1 times [2019-12-07 15:32:30,296 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:32:30,296 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1238511550] [2019-12-07 15:32:30,296 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:32:30,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:32:30,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:32:30,357 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1238511550] [2019-12-07 15:32:30,357 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:32:30,357 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:32:30,357 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1687933233] [2019-12-07 15:32:30,358 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 15:32:30,358 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:32:30,358 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 15:32:30,358 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:32:30,359 INFO L87 Difference]: Start difference. First operand 104924 states and 451982 transitions. Second operand 4 states. [2019-12-07 15:32:31,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:32:31,284 INFO L93 Difference]: Finished difference Result 168606 states and 697152 transitions. [2019-12-07 15:32:31,285 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 15:32:31,285 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 15:32:31,285 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:32:31,775 INFO L225 Difference]: With dead ends: 168606 [2019-12-07 15:32:31,775 INFO L226 Difference]: Without dead ends: 168557 [2019-12-07 15:32:31,776 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:32:35,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 168557 states. [2019-12-07 15:32:37,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 168557 to 152629. [2019-12-07 15:32:37,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 152629 states. [2019-12-07 15:32:38,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152629 states to 152629 states and 638547 transitions. [2019-12-07 15:32:38,637 INFO L78 Accepts]: Start accepts. Automaton has 152629 states and 638547 transitions. Word has length 11 [2019-12-07 15:32:38,637 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:32:38,637 INFO L462 AbstractCegarLoop]: Abstraction has 152629 states and 638547 transitions. [2019-12-07 15:32:38,638 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 15:32:38,638 INFO L276 IsEmpty]: Start isEmpty. Operand 152629 states and 638547 transitions. [2019-12-07 15:32:38,642 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 15:32:38,642 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:32:38,642 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:32:38,642 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:32:38,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:32:38,642 INFO L82 PathProgramCache]: Analyzing trace with hash 2027270657, now seen corresponding path program 1 times [2019-12-07 15:32:38,642 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:32:38,643 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1350614443] [2019-12-07 15:32:38,643 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:32:38,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:32:38,686 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:32:38,687 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1350614443] [2019-12-07 15:32:38,687 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:32:38,687 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:32:38,687 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [259775971] [2019-12-07 15:32:38,687 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 15:32:38,687 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:32:38,687 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 15:32:38,688 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:32:38,688 INFO L87 Difference]: Start difference. First operand 152629 states and 638547 transitions. Second operand 4 states. [2019-12-07 15:32:39,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:32:39,792 INFO L93 Difference]: Finished difference Result 217678 states and 889823 transitions. [2019-12-07 15:32:39,793 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 15:32:39,793 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 15:32:39,793 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:32:40,337 INFO L225 Difference]: With dead ends: 217678 [2019-12-07 15:32:40,337 INFO L226 Difference]: Without dead ends: 217615 [2019-12-07 15:32:40,338 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:32:46,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217615 states. [2019-12-07 15:32:49,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217615 to 183279. [2019-12-07 15:32:49,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 183279 states. [2019-12-07 15:32:49,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183279 states to 183279 states and 761454 transitions. [2019-12-07 15:32:49,878 INFO L78 Accepts]: Start accepts. Automaton has 183279 states and 761454 transitions. Word has length 13 [2019-12-07 15:32:49,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:32:49,879 INFO L462 AbstractCegarLoop]: Abstraction has 183279 states and 761454 transitions. [2019-12-07 15:32:49,880 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 15:32:49,880 INFO L276 IsEmpty]: Start isEmpty. Operand 183279 states and 761454 transitions. [2019-12-07 15:32:49,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 15:32:49,882 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:32:49,882 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:32:49,883 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:32:49,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:32:49,883 INFO L82 PathProgramCache]: Analyzing trace with hash 1789207667, now seen corresponding path program 1 times [2019-12-07 15:32:49,883 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:32:49,883 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [42702554] [2019-12-07 15:32:49,883 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:32:49,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:32:49,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:32:49,931 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [42702554] [2019-12-07 15:32:49,932 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:32:49,932 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:32:49,932 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1071598177] [2019-12-07 15:32:49,932 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 15:32:49,932 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:32:49,933 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 15:32:49,933 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:32:49,933 INFO L87 Difference]: Start difference. First operand 183279 states and 761454 transitions. Second operand 4 states. [2019-12-07 15:32:51,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:32:51,496 INFO L93 Difference]: Finished difference Result 228772 states and 941089 transitions. [2019-12-07 15:32:51,497 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 15:32:51,497 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 15:32:51,497 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:32:52,092 INFO L225 Difference]: With dead ends: 228772 [2019-12-07 15:32:52,092 INFO L226 Difference]: Without dead ends: 228772 [2019-12-07 15:32:52,092 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:32:56,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228772 states. [2019-12-07 15:33:02,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228772 to 193424. [2019-12-07 15:33:02,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 193424 states. [2019-12-07 15:33:02,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193424 states to 193424 states and 803706 transitions. [2019-12-07 15:33:02,980 INFO L78 Accepts]: Start accepts. Automaton has 193424 states and 803706 transitions. Word has length 13 [2019-12-07 15:33:02,980 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:33:02,980 INFO L462 AbstractCegarLoop]: Abstraction has 193424 states and 803706 transitions. [2019-12-07 15:33:02,980 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 15:33:02,980 INFO L276 IsEmpty]: Start isEmpty. Operand 193424 states and 803706 transitions. [2019-12-07 15:33:02,993 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 15:33:02,993 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:33:02,993 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:33:02,993 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:33:02,993 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:33:02,993 INFO L82 PathProgramCache]: Analyzing trace with hash 1405830784, now seen corresponding path program 1 times [2019-12-07 15:33:02,993 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:33:02,994 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [724806329] [2019-12-07 15:33:02,994 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:33:03,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:33:03,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:33:03,041 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [724806329] [2019-12-07 15:33:03,041 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:33:03,041 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:33:03,041 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1531526438] [2019-12-07 15:33:03,041 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:33:03,041 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:33:03,042 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:33:03,042 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:33:03,042 INFO L87 Difference]: Start difference. First operand 193424 states and 803706 transitions. Second operand 5 states. [2019-12-07 15:33:04,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:33:04,667 INFO L93 Difference]: Finished difference Result 284752 states and 1156454 transitions. [2019-12-07 15:33:04,668 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 15:33:04,668 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 15:33:04,668 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:33:05,383 INFO L225 Difference]: With dead ends: 284752 [2019-12-07 15:33:05,383 INFO L226 Difference]: Without dead ends: 284612 [2019-12-07 15:33:05,384 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:33:10,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284612 states. [2019-12-07 15:33:14,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284612 to 212401. [2019-12-07 15:33:14,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 212401 states. [2019-12-07 15:33:15,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212401 states to 212401 states and 878348 transitions. [2019-12-07 15:33:15,202 INFO L78 Accepts]: Start accepts. Automaton has 212401 states and 878348 transitions. Word has length 19 [2019-12-07 15:33:15,202 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:33:15,202 INFO L462 AbstractCegarLoop]: Abstraction has 212401 states and 878348 transitions. [2019-12-07 15:33:15,202 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:33:15,202 INFO L276 IsEmpty]: Start isEmpty. Operand 212401 states and 878348 transitions. [2019-12-07 15:33:15,214 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 15:33:15,214 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:33:15,214 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:33:15,214 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:33:15,214 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:33:15,214 INFO L82 PathProgramCache]: Analyzing trace with hash 1167767794, now seen corresponding path program 1 times [2019-12-07 15:33:15,215 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:33:15,215 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2036022828] [2019-12-07 15:33:15,215 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:33:15,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:33:15,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:33:15,268 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2036022828] [2019-12-07 15:33:15,268 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:33:15,268 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:33:15,268 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [282765714] [2019-12-07 15:33:15,269 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:33:15,269 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:33:15,269 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:33:15,269 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:33:15,269 INFO L87 Difference]: Start difference. First operand 212401 states and 878348 transitions. Second operand 5 states. [2019-12-07 15:33:16,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:33:16,869 INFO L93 Difference]: Finished difference Result 308783 states and 1251594 transitions. [2019-12-07 15:33:16,870 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 15:33:16,870 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 15:33:16,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:33:17,647 INFO L225 Difference]: With dead ends: 308783 [2019-12-07 15:33:17,647 INFO L226 Difference]: Without dead ends: 308720 [2019-12-07 15:33:17,647 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:33:25,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 308720 states. [2019-12-07 15:33:29,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 308720 to 216265. [2019-12-07 15:33:29,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 216265 states. [2019-12-07 15:33:29,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 216265 states to 216265 states and 893275 transitions. [2019-12-07 15:33:29,910 INFO L78 Accepts]: Start accepts. Automaton has 216265 states and 893275 transitions. Word has length 19 [2019-12-07 15:33:29,911 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:33:29,911 INFO L462 AbstractCegarLoop]: Abstraction has 216265 states and 893275 transitions. [2019-12-07 15:33:29,911 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:33:29,911 INFO L276 IsEmpty]: Start isEmpty. Operand 216265 states and 893275 transitions. [2019-12-07 15:33:29,922 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 15:33:29,922 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:33:29,922 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:33:29,922 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:33:29,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:33:29,922 INFO L82 PathProgramCache]: Analyzing trace with hash 1572236508, now seen corresponding path program 1 times [2019-12-07 15:33:29,923 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:33:29,923 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [84326843] [2019-12-07 15:33:29,923 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:33:29,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:33:29,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:33:29,989 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [84326843] [2019-12-07 15:33:29,989 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:33:29,990 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 15:33:29,990 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [637385863] [2019-12-07 15:33:29,990 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:33:29,990 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:33:29,990 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:33:29,990 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:33:29,991 INFO L87 Difference]: Start difference. First operand 216265 states and 893275 transitions. Second operand 6 states. [2019-12-07 15:33:32,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:33:32,150 INFO L93 Difference]: Finished difference Result 315951 states and 1278566 transitions. [2019-12-07 15:33:32,151 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 15:33:32,151 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 19 [2019-12-07 15:33:32,151 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:33:32,921 INFO L225 Difference]: With dead ends: 315951 [2019-12-07 15:33:32,921 INFO L226 Difference]: Without dead ends: 315951 [2019-12-07 15:33:32,922 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=71, Unknown=0, NotChecked=0, Total=110 [2019-12-07 15:33:38,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 315951 states. [2019-12-07 15:33:45,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 315951 to 226037. [2019-12-07 15:33:45,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226037 states. [2019-12-07 15:33:46,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226037 states to 226037 states and 931835 transitions. [2019-12-07 15:33:46,359 INFO L78 Accepts]: Start accepts. Automaton has 226037 states and 931835 transitions. Word has length 19 [2019-12-07 15:33:46,360 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:33:46,360 INFO L462 AbstractCegarLoop]: Abstraction has 226037 states and 931835 transitions. [2019-12-07 15:33:46,360 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:33:46,360 INFO L276 IsEmpty]: Start isEmpty. Operand 226037 states and 931835 transitions. [2019-12-07 15:33:46,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 15:33:46,371 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:33:46,371 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:33:46,371 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:33:46,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:33:46,371 INFO L82 PathProgramCache]: Analyzing trace with hash -1878693572, now seen corresponding path program 2 times [2019-12-07 15:33:46,371 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:33:46,371 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915737688] [2019-12-07 15:33:46,371 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:33:46,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:33:46,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:33:46,417 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1915737688] [2019-12-07 15:33:46,417 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:33:46,417 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:33:46,417 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2051640873] [2019-12-07 15:33:46,417 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:33:46,417 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:33:46,417 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:33:46,418 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:33:46,418 INFO L87 Difference]: Start difference. First operand 226037 states and 931835 transitions. Second operand 5 states. [2019-12-07 15:33:48,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:33:48,278 INFO L93 Difference]: Finished difference Result 322388 states and 1308191 transitions. [2019-12-07 15:33:48,279 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 15:33:48,279 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 15:33:48,279 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:33:49,088 INFO L225 Difference]: With dead ends: 322388 [2019-12-07 15:33:49,088 INFO L226 Difference]: Without dead ends: 322325 [2019-12-07 15:33:49,088 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:33:54,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322325 states. [2019-12-07 15:33:58,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322325 to 231837. [2019-12-07 15:33:58,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 231837 states. [2019-12-07 15:33:59,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 231837 states to 231837 states and 956389 transitions. [2019-12-07 15:33:59,348 INFO L78 Accepts]: Start accepts. Automaton has 231837 states and 956389 transitions. Word has length 19 [2019-12-07 15:33:59,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:33:59,348 INFO L462 AbstractCegarLoop]: Abstraction has 231837 states and 956389 transitions. [2019-12-07 15:33:59,348 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:33:59,349 INFO L276 IsEmpty]: Start isEmpty. Operand 231837 states and 956389 transitions. [2019-12-07 15:33:59,397 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 15:33:59,397 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:33:59,397 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:33:59,397 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:33:59,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:33:59,397 INFO L82 PathProgramCache]: Analyzing trace with hash -983276005, now seen corresponding path program 1 times [2019-12-07 15:33:59,397 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:33:59,397 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552766033] [2019-12-07 15:33:59,398 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:33:59,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:33:59,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:33:59,474 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [552766033] [2019-12-07 15:33:59,475 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:33:59,475 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 15:33:59,475 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1098046407] [2019-12-07 15:33:59,475 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 15:33:59,475 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:33:59,475 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 15:33:59,476 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 15:33:59,476 INFO L87 Difference]: Start difference. First operand 231837 states and 956389 transitions. Second operand 7 states. [2019-12-07 15:34:04,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:34:04,700 INFO L93 Difference]: Finished difference Result 363566 states and 1470501 transitions. [2019-12-07 15:34:04,701 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 15:34:04,701 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 25 [2019-12-07 15:34:04,701 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:34:05,578 INFO L225 Difference]: With dead ends: 363566 [2019-12-07 15:34:05,578 INFO L226 Difference]: Without dead ends: 363566 [2019-12-07 15:34:05,579 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 78 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=117, Invalid=303, Unknown=0, NotChecked=0, Total=420 [2019-12-07 15:34:11,405 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 363566 states. [2019-12-07 15:34:15,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 363566 to 228323. [2019-12-07 15:34:15,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228323 states. [2019-12-07 15:34:16,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228323 states to 228323 states and 943087 transitions. [2019-12-07 15:34:16,466 INFO L78 Accepts]: Start accepts. Automaton has 228323 states and 943087 transitions. Word has length 25 [2019-12-07 15:34:16,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:34:16,467 INFO L462 AbstractCegarLoop]: Abstraction has 228323 states and 943087 transitions. [2019-12-07 15:34:16,467 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 15:34:16,467 INFO L276 IsEmpty]: Start isEmpty. Operand 228323 states and 943087 transitions. [2019-12-07 15:34:16,510 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 15:34:16,510 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:34:16,510 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:34:16,510 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:34:16,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:34:16,510 INFO L82 PathProgramCache]: Analyzing trace with hash -139238789, now seen corresponding path program 2 times [2019-12-07 15:34:16,510 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:34:16,511 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1620690122] [2019-12-07 15:34:16,511 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:34:16,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:34:16,555 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:34:16,555 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1620690122] [2019-12-07 15:34:16,555 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:34:16,555 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 15:34:16,555 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [442318807] [2019-12-07 15:34:16,555 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:34:16,555 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:34:16,556 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:34:16,556 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:34:16,556 INFO L87 Difference]: Start difference. First operand 228323 states and 943087 transitions. Second operand 6 states. [2019-12-07 15:34:18,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:34:18,311 INFO L93 Difference]: Finished difference Result 272978 states and 1114694 transitions. [2019-12-07 15:34:18,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 15:34:18,312 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2019-12-07 15:34:18,312 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:34:19,538 INFO L225 Difference]: With dead ends: 272978 [2019-12-07 15:34:19,538 INFO L226 Difference]: Without dead ends: 272838 [2019-12-07 15:34:19,538 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=81, Invalid=191, Unknown=0, NotChecked=0, Total=272 [2019-12-07 15:34:24,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 272838 states. [2019-12-07 15:34:27,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 272838 to 191175. [2019-12-07 15:34:27,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 191175 states. [2019-12-07 15:34:28,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191175 states to 191175 states and 792620 transitions. [2019-12-07 15:34:28,366 INFO L78 Accepts]: Start accepts. Automaton has 191175 states and 792620 transitions. Word has length 25 [2019-12-07 15:34:28,366 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:34:28,366 INFO L462 AbstractCegarLoop]: Abstraction has 191175 states and 792620 transitions. [2019-12-07 15:34:28,366 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:34:28,366 INFO L276 IsEmpty]: Start isEmpty. Operand 191175 states and 792620 transitions. [2019-12-07 15:34:28,423 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 15:34:28,424 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:34:28,424 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:34:28,424 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:34:28,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:34:28,424 INFO L82 PathProgramCache]: Analyzing trace with hash -588293342, now seen corresponding path program 1 times [2019-12-07 15:34:28,424 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:34:28,424 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [469784565] [2019-12-07 15:34:28,424 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:34:28,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:34:28,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:34:28,449 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [469784565] [2019-12-07 15:34:28,449 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:34:28,449 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:34:28,449 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [417417520] [2019-12-07 15:34:28,449 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:34:28,449 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:34:28,449 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:34:28,449 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:34:28,449 INFO L87 Difference]: Start difference. First operand 191175 states and 792620 transitions. Second operand 3 states. [2019-12-07 15:34:29,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:34:29,482 INFO L93 Difference]: Finished difference Result 229453 states and 953212 transitions. [2019-12-07 15:34:29,482 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:34:29,482 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 15:34:29,483 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:34:30,081 INFO L225 Difference]: With dead ends: 229453 [2019-12-07 15:34:30,081 INFO L226 Difference]: Without dead ends: 229453 [2019-12-07 15:34:30,081 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:34:36,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 229453 states. [2019-12-07 15:34:39,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 229453 to 215231. [2019-12-07 15:34:39,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 215231 states. [2019-12-07 15:34:40,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215231 states to 215231 states and 897051 transitions. [2019-12-07 15:34:40,399 INFO L78 Accepts]: Start accepts. Automaton has 215231 states and 897051 transitions. Word has length 27 [2019-12-07 15:34:40,399 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:34:40,399 INFO L462 AbstractCegarLoop]: Abstraction has 215231 states and 897051 transitions. [2019-12-07 15:34:40,399 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:34:40,399 INFO L276 IsEmpty]: Start isEmpty. Operand 215231 states and 897051 transitions. [2019-12-07 15:34:40,456 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 15:34:40,456 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:34:40,456 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:34:40,456 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:34:40,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:34:40,456 INFO L82 PathProgramCache]: Analyzing trace with hash -455574437, now seen corresponding path program 1 times [2019-12-07 15:34:40,456 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:34:40,457 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1716463700] [2019-12-07 15:34:40,457 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:34:40,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:34:40,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:34:40,477 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1716463700] [2019-12-07 15:34:40,477 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:34:40,477 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:34:40,477 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1575537948] [2019-12-07 15:34:40,477 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:34:40,478 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:34:40,478 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:34:40,478 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:34:40,478 INFO L87 Difference]: Start difference. First operand 215231 states and 897051 transitions. Second operand 3 states. [2019-12-07 15:34:40,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:34:40,598 INFO L93 Difference]: Finished difference Result 44393 states and 145223 transitions. [2019-12-07 15:34:40,598 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:34:40,598 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 15:34:40,598 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:34:40,659 INFO L225 Difference]: With dead ends: 44393 [2019-12-07 15:34:40,659 INFO L226 Difference]: Without dead ends: 44393 [2019-12-07 15:34:40,660 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:34:40,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44393 states. [2019-12-07 15:34:41,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44393 to 44393. [2019-12-07 15:34:41,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44393 states. [2019-12-07 15:34:41,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44393 states to 44393 states and 145223 transitions. [2019-12-07 15:34:41,664 INFO L78 Accepts]: Start accepts. Automaton has 44393 states and 145223 transitions. Word has length 27 [2019-12-07 15:34:41,664 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:34:41,665 INFO L462 AbstractCegarLoop]: Abstraction has 44393 states and 145223 transitions. [2019-12-07 15:34:41,665 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:34:41,665 INFO L276 IsEmpty]: Start isEmpty. Operand 44393 states and 145223 transitions. [2019-12-07 15:34:41,680 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2019-12-07 15:34:41,680 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:34:41,680 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:34:41,680 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:34:41,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:34:41,680 INFO L82 PathProgramCache]: Analyzing trace with hash 1697210614, now seen corresponding path program 1 times [2019-12-07 15:34:41,680 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:34:41,681 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421221657] [2019-12-07 15:34:41,681 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:34:41,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:34:41,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:34:41,712 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [421221657] [2019-12-07 15:34:41,713 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:34:41,713 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:34:41,713 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2011018090] [2019-12-07 15:34:41,713 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 15:34:41,713 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:34:41,713 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 15:34:41,713 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:34:41,714 INFO L87 Difference]: Start difference. First operand 44393 states and 145223 transitions. Second operand 4 states. [2019-12-07 15:34:41,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:34:41,741 INFO L93 Difference]: Finished difference Result 7906 states and 21265 transitions. [2019-12-07 15:34:41,741 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 15:34:41,741 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 39 [2019-12-07 15:34:41,741 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:34:41,748 INFO L225 Difference]: With dead ends: 7906 [2019-12-07 15:34:41,748 INFO L226 Difference]: Without dead ends: 7906 [2019-12-07 15:34:41,748 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:34:41,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7906 states. [2019-12-07 15:34:41,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7906 to 7794. [2019-12-07 15:34:41,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7794 states. [2019-12-07 15:34:41,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7794 states to 7794 states and 20945 transitions. [2019-12-07 15:34:41,834 INFO L78 Accepts]: Start accepts. Automaton has 7794 states and 20945 transitions. Word has length 39 [2019-12-07 15:34:41,834 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:34:41,834 INFO L462 AbstractCegarLoop]: Abstraction has 7794 states and 20945 transitions. [2019-12-07 15:34:41,834 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 15:34:41,835 INFO L276 IsEmpty]: Start isEmpty. Operand 7794 states and 20945 transitions. [2019-12-07 15:34:41,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 15:34:41,839 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:34:41,839 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:34:41,840 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:34:41,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:34:41,840 INFO L82 PathProgramCache]: Analyzing trace with hash -994376569, now seen corresponding path program 1 times [2019-12-07 15:34:41,840 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:34:41,840 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1362333707] [2019-12-07 15:34:41,840 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:34:41,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:34:41,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:34:41,883 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1362333707] [2019-12-07 15:34:41,883 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:34:41,884 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 15:34:41,884 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [393689476] [2019-12-07 15:34:41,884 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:34:41,884 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:34:41,884 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:34:41,885 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:34:41,885 INFO L87 Difference]: Start difference. First operand 7794 states and 20945 transitions. Second operand 5 states. [2019-12-07 15:34:41,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:34:41,915 INFO L93 Difference]: Finished difference Result 5050 states and 14454 transitions. [2019-12-07 15:34:41,915 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 15:34:41,915 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-12-07 15:34:41,916 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:34:41,920 INFO L225 Difference]: With dead ends: 5050 [2019-12-07 15:34:41,920 INFO L226 Difference]: Without dead ends: 5050 [2019-12-07 15:34:41,920 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:34:41,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5050 states. [2019-12-07 15:34:41,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5050 to 4686. [2019-12-07 15:34:41,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4686 states. [2019-12-07 15:34:41,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4686 states to 4686 states and 13470 transitions. [2019-12-07 15:34:41,981 INFO L78 Accepts]: Start accepts. Automaton has 4686 states and 13470 transitions. Word has length 51 [2019-12-07 15:34:41,981 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:34:41,981 INFO L462 AbstractCegarLoop]: Abstraction has 4686 states and 13470 transitions. [2019-12-07 15:34:41,981 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:34:41,981 INFO L276 IsEmpty]: Start isEmpty. Operand 4686 states and 13470 transitions. [2019-12-07 15:34:41,984 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 15:34:41,984 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:34:41,985 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:34:41,985 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:34:41,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:34:41,985 INFO L82 PathProgramCache]: Analyzing trace with hash 1902070617, now seen corresponding path program 1 times [2019-12-07 15:34:41,985 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:34:41,985 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1990756061] [2019-12-07 15:34:41,985 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:34:41,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:34:42,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:34:42,017 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1990756061] [2019-12-07 15:34:42,018 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:34:42,018 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:34:42,018 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1047904506] [2019-12-07 15:34:42,018 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:34:42,018 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:34:42,018 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:34:42,018 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:34:42,018 INFO L87 Difference]: Start difference. First operand 4686 states and 13470 transitions. Second operand 3 states. [2019-12-07 15:34:42,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:34:42,055 INFO L93 Difference]: Finished difference Result 4690 states and 13463 transitions. [2019-12-07 15:34:42,055 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:34:42,055 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 15:34:42,056 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:34:42,059 INFO L225 Difference]: With dead ends: 4690 [2019-12-07 15:34:42,059 INFO L226 Difference]: Without dead ends: 4690 [2019-12-07 15:34:42,060 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:34:42,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4690 states. [2019-12-07 15:34:42,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4690 to 4682. [2019-12-07 15:34:42,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4682 states. [2019-12-07 15:34:42,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4682 states to 4682 states and 13455 transitions. [2019-12-07 15:34:42,113 INFO L78 Accepts]: Start accepts. Automaton has 4682 states and 13455 transitions. Word has length 65 [2019-12-07 15:34:42,113 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:34:42,113 INFO L462 AbstractCegarLoop]: Abstraction has 4682 states and 13455 transitions. [2019-12-07 15:34:42,113 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:34:42,113 INFO L276 IsEmpty]: Start isEmpty. Operand 4682 states and 13455 transitions. [2019-12-07 15:34:42,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 15:34:42,116 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:34:42,116 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:34:42,117 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:34:42,117 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:34:42,117 INFO L82 PathProgramCache]: Analyzing trace with hash 1892358751, now seen corresponding path program 1 times [2019-12-07 15:34:42,117 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:34:42,117 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [566540589] [2019-12-07 15:34:42,117 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:34:42,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:34:42,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:34:42,175 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [566540589] [2019-12-07 15:34:42,175 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:34:42,175 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 15:34:42,175 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1787442193] [2019-12-07 15:34:42,175 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:34:42,176 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:34:42,176 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:34:42,176 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:34:42,176 INFO L87 Difference]: Start difference. First operand 4682 states and 13455 transitions. Second operand 6 states. [2019-12-07 15:34:42,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:34:42,459 INFO L93 Difference]: Finished difference Result 8786 states and 25107 transitions. [2019-12-07 15:34:42,459 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 15:34:42,459 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 65 [2019-12-07 15:34:42,459 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:34:42,467 INFO L225 Difference]: With dead ends: 8786 [2019-12-07 15:34:42,467 INFO L226 Difference]: Without dead ends: 8786 [2019-12-07 15:34:42,467 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:34:42,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8786 states. [2019-12-07 15:34:42,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8786 to 5995. [2019-12-07 15:34:42,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5995 states. [2019-12-07 15:34:42,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5995 states to 5995 states and 17174 transitions. [2019-12-07 15:34:42,557 INFO L78 Accepts]: Start accepts. Automaton has 5995 states and 17174 transitions. Word has length 65 [2019-12-07 15:34:42,557 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:34:42,557 INFO L462 AbstractCegarLoop]: Abstraction has 5995 states and 17174 transitions. [2019-12-07 15:34:42,557 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:34:42,557 INFO L276 IsEmpty]: Start isEmpty. Operand 5995 states and 17174 transitions. [2019-12-07 15:34:42,561 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 15:34:42,561 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:34:42,561 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:34:42,561 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:34:42,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:34:42,562 INFO L82 PathProgramCache]: Analyzing trace with hash -191494421, now seen corresponding path program 2 times [2019-12-07 15:34:42,562 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:34:42,562 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296974896] [2019-12-07 15:34:42,562 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:34:42,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:34:42,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:34:42,621 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1296974896] [2019-12-07 15:34:42,621 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:34:42,621 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 15:34:42,621 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [124974132] [2019-12-07 15:34:42,621 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:34:42,622 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:34:42,622 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:34:42,622 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:34:42,622 INFO L87 Difference]: Start difference. First operand 5995 states and 17174 transitions. Second operand 5 states. [2019-12-07 15:34:42,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:34:42,828 INFO L93 Difference]: Finished difference Result 8521 states and 24141 transitions. [2019-12-07 15:34:42,828 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 15:34:42,828 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 65 [2019-12-07 15:34:42,828 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:34:42,835 INFO L225 Difference]: With dead ends: 8521 [2019-12-07 15:34:42,835 INFO L226 Difference]: Without dead ends: 8521 [2019-12-07 15:34:42,835 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 15:34:42,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8521 states. [2019-12-07 15:34:42,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8521 to 6771. [2019-12-07 15:34:42,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6771 states. [2019-12-07 15:34:42,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6771 states to 6771 states and 19440 transitions. [2019-12-07 15:34:42,923 INFO L78 Accepts]: Start accepts. Automaton has 6771 states and 19440 transitions. Word has length 65 [2019-12-07 15:34:42,923 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:34:42,923 INFO L462 AbstractCegarLoop]: Abstraction has 6771 states and 19440 transitions. [2019-12-07 15:34:42,923 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:34:42,923 INFO L276 IsEmpty]: Start isEmpty. Operand 6771 states and 19440 transitions. [2019-12-07 15:34:42,928 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 15:34:42,928 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:34:42,928 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:34:42,928 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:34:42,928 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:34:42,928 INFO L82 PathProgramCache]: Analyzing trace with hash 147719209, now seen corresponding path program 3 times [2019-12-07 15:34:42,928 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:34:42,928 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1309038361] [2019-12-07 15:34:42,928 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:34:42,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:34:42,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:34:42,960 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1309038361] [2019-12-07 15:34:42,961 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:34:42,961 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:34:42,961 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [591396686] [2019-12-07 15:34:42,961 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:34:42,961 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:34:42,961 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:34:42,961 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:34:42,961 INFO L87 Difference]: Start difference. First operand 6771 states and 19440 transitions. Second operand 3 states. [2019-12-07 15:34:42,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:34:42,979 INFO L93 Difference]: Finished difference Result 5663 states and 15971 transitions. [2019-12-07 15:34:42,979 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:34:42,980 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 15:34:42,980 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:34:42,984 INFO L225 Difference]: With dead ends: 5663 [2019-12-07 15:34:42,984 INFO L226 Difference]: Without dead ends: 5663 [2019-12-07 15:34:42,985 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:34:43,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5663 states. [2019-12-07 15:34:43,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5663 to 5523. [2019-12-07 15:34:43,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5523 states. [2019-12-07 15:34:43,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5523 states to 5523 states and 15585 transitions. [2019-12-07 15:34:43,049 INFO L78 Accepts]: Start accepts. Automaton has 5523 states and 15585 transitions. Word has length 65 [2019-12-07 15:34:43,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:34:43,050 INFO L462 AbstractCegarLoop]: Abstraction has 5523 states and 15585 transitions. [2019-12-07 15:34:43,050 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:34:43,050 INFO L276 IsEmpty]: Start isEmpty. Operand 5523 states and 15585 transitions. [2019-12-07 15:34:43,053 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 15:34:43,053 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:34:43,053 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:34:43,053 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:34:43,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:34:43,053 INFO L82 PathProgramCache]: Analyzing trace with hash 284491425, now seen corresponding path program 1 times [2019-12-07 15:34:43,054 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:34:43,054 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [74268551] [2019-12-07 15:34:43,054 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:34:43,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:34:43,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:34:43,137 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [74268551] [2019-12-07 15:34:43,137 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:34:43,137 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 15:34:43,137 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [993657699] [2019-12-07 15:34:43,137 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 15:34:43,137 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:34:43,137 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 15:34:43,138 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 15:34:43,138 INFO L87 Difference]: Start difference. First operand 5523 states and 15585 transitions. Second operand 7 states. [2019-12-07 15:34:43,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:34:43,293 INFO L93 Difference]: Finished difference Result 18657 states and 53001 transitions. [2019-12-07 15:34:43,293 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 15:34:43,294 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 66 [2019-12-07 15:34:43,294 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:34:43,303 INFO L225 Difference]: With dead ends: 18657 [2019-12-07 15:34:43,303 INFO L226 Difference]: Without dead ends: 11288 [2019-12-07 15:34:43,304 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=55, Invalid=101, Unknown=0, NotChecked=0, Total=156 [2019-12-07 15:34:43,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11288 states. [2019-12-07 15:34:43,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11288 to 5523. [2019-12-07 15:34:43,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5523 states. [2019-12-07 15:34:43,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5523 states to 5523 states and 15520 transitions. [2019-12-07 15:34:43,401 INFO L78 Accepts]: Start accepts. Automaton has 5523 states and 15520 transitions. Word has length 66 [2019-12-07 15:34:43,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:34:43,402 INFO L462 AbstractCegarLoop]: Abstraction has 5523 states and 15520 transitions. [2019-12-07 15:34:43,402 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 15:34:43,402 INFO L276 IsEmpty]: Start isEmpty. Operand 5523 states and 15520 transitions. [2019-12-07 15:34:43,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 15:34:43,405 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:34:43,405 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:34:43,406 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:34:43,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:34:43,406 INFO L82 PathProgramCache]: Analyzing trace with hash -1438113561, now seen corresponding path program 2 times [2019-12-07 15:34:43,406 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:34:43,406 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427588389] [2019-12-07 15:34:43,406 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:34:43,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:34:43,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:34:43,479 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [427588389] [2019-12-07 15:34:43,479 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:34:43,479 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 15:34:43,480 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [958037933] [2019-12-07 15:34:43,480 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:34:43,480 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:34:43,480 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:34:43,480 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:34:43,480 INFO L87 Difference]: Start difference. First operand 5523 states and 15520 transitions. Second operand 6 states. [2019-12-07 15:34:43,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:34:43,756 INFO L93 Difference]: Finished difference Result 7367 states and 20477 transitions. [2019-12-07 15:34:43,757 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 15:34:43,757 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 66 [2019-12-07 15:34:43,757 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:34:43,763 INFO L225 Difference]: With dead ends: 7367 [2019-12-07 15:34:43,763 INFO L226 Difference]: Without dead ends: 7367 [2019-12-07 15:34:43,763 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:34:43,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7367 states. [2019-12-07 15:34:43,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7367 to 6104. [2019-12-07 15:34:43,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6104 states. [2019-12-07 15:34:43,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6104 states to 6104 states and 17145 transitions. [2019-12-07 15:34:43,840 INFO L78 Accepts]: Start accepts. Automaton has 6104 states and 17145 transitions. Word has length 66 [2019-12-07 15:34:43,840 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:34:43,840 INFO L462 AbstractCegarLoop]: Abstraction has 6104 states and 17145 transitions. [2019-12-07 15:34:43,840 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:34:43,840 INFO L276 IsEmpty]: Start isEmpty. Operand 6104 states and 17145 transitions. [2019-12-07 15:34:43,844 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 15:34:43,844 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:34:43,844 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:34:43,844 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:34:43,844 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:34:43,844 INFO L82 PathProgramCache]: Analyzing trace with hash 490304069, now seen corresponding path program 3 times [2019-12-07 15:34:43,844 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:34:43,844 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1735114012] [2019-12-07 15:34:43,845 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:34:43,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:34:44,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:34:44,119 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1735114012] [2019-12-07 15:34:44,119 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:34:44,119 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 15:34:44,119 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1119833281] [2019-12-07 15:34:44,120 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:34:44,120 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:34:44,120 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:34:44,120 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:34:44,120 INFO L87 Difference]: Start difference. First operand 6104 states and 17145 transitions. Second operand 6 states. [2019-12-07 15:34:44,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:34:44,423 INFO L93 Difference]: Finished difference Result 8274 states and 22928 transitions. [2019-12-07 15:34:44,423 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 15:34:44,424 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 66 [2019-12-07 15:34:44,424 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:34:44,430 INFO L225 Difference]: With dead ends: 8274 [2019-12-07 15:34:44,431 INFO L226 Difference]: Without dead ends: 8274 [2019-12-07 15:34:44,431 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2019-12-07 15:34:44,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8274 states. [2019-12-07 15:34:44,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8274 to 6762. [2019-12-07 15:34:44,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6762 states. [2019-12-07 15:34:44,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6762 states to 6762 states and 18864 transitions. [2019-12-07 15:34:44,521 INFO L78 Accepts]: Start accepts. Automaton has 6762 states and 18864 transitions. Word has length 66 [2019-12-07 15:34:44,521 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:34:44,521 INFO L462 AbstractCegarLoop]: Abstraction has 6762 states and 18864 transitions. [2019-12-07 15:34:44,521 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:34:44,521 INFO L276 IsEmpty]: Start isEmpty. Operand 6762 states and 18864 transitions. [2019-12-07 15:34:44,525 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 15:34:44,526 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:34:44,526 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:34:44,526 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:34:44,526 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:34:44,526 INFO L82 PathProgramCache]: Analyzing trace with hash -1405133371, now seen corresponding path program 4 times [2019-12-07 15:34:44,526 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:34:44,526 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1311565987] [2019-12-07 15:34:44,526 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:34:44,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:34:44,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:34:44,584 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1311565987] [2019-12-07 15:34:44,585 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:34:44,585 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 15:34:44,585 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [115376534] [2019-12-07 15:34:44,585 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 15:34:44,585 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:34:44,585 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 15:34:44,585 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 15:34:44,585 INFO L87 Difference]: Start difference. First operand 6762 states and 18864 transitions. Second operand 7 states. [2019-12-07 15:34:45,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:34:45,024 INFO L93 Difference]: Finished difference Result 9540 states and 26269 transitions. [2019-12-07 15:34:45,024 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 15:34:45,024 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 66 [2019-12-07 15:34:45,024 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:34:45,031 INFO L225 Difference]: With dead ends: 9540 [2019-12-07 15:34:45,031 INFO L226 Difference]: Without dead ends: 9540 [2019-12-07 15:34:45,032 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 9 SyntacticMatches, 2 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=55, Invalid=155, Unknown=0, NotChecked=0, Total=210 [2019-12-07 15:34:45,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9540 states. [2019-12-07 15:34:45,126 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9540 to 6846. [2019-12-07 15:34:45,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6846 states. [2019-12-07 15:34:45,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6846 states to 6846 states and 19090 transitions. [2019-12-07 15:34:45,135 INFO L78 Accepts]: Start accepts. Automaton has 6846 states and 19090 transitions. Word has length 66 [2019-12-07 15:34:45,135 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:34:45,135 INFO L462 AbstractCegarLoop]: Abstraction has 6846 states and 19090 transitions. [2019-12-07 15:34:45,135 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 15:34:45,135 INFO L276 IsEmpty]: Start isEmpty. Operand 6846 states and 19090 transitions. [2019-12-07 15:34:45,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 15:34:45,139 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:34:45,140 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:34:45,140 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:34:45,140 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:34:45,140 INFO L82 PathProgramCache]: Analyzing trace with hash 501840945, now seen corresponding path program 5 times [2019-12-07 15:34:45,140 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:34:45,140 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1247558305] [2019-12-07 15:34:45,140 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:34:45,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:34:45,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:34:45,179 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1247558305] [2019-12-07 15:34:45,180 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:34:45,180 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:34:45,180 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2131089567] [2019-12-07 15:34:45,180 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:34:45,180 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:34:45,180 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:34:45,180 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:34:45,180 INFO L87 Difference]: Start difference. First operand 6846 states and 19090 transitions. Second operand 3 states. [2019-12-07 15:34:45,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:34:45,217 INFO L93 Difference]: Finished difference Result 6846 states and 19089 transitions. [2019-12-07 15:34:45,218 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:34:45,218 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 15:34:45,218 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:34:45,223 INFO L225 Difference]: With dead ends: 6846 [2019-12-07 15:34:45,223 INFO L226 Difference]: Without dead ends: 6846 [2019-12-07 15:34:45,223 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:34:45,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6846 states. [2019-12-07 15:34:45,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6846 to 5396. [2019-12-07 15:34:45,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5396 states. [2019-12-07 15:34:45,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5396 states to 5396 states and 15110 transitions. [2019-12-07 15:34:45,289 INFO L78 Accepts]: Start accepts. Automaton has 5396 states and 15110 transitions. Word has length 66 [2019-12-07 15:34:45,289 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:34:45,289 INFO L462 AbstractCegarLoop]: Abstraction has 5396 states and 15110 transitions. [2019-12-07 15:34:45,289 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:34:45,289 INFO L276 IsEmpty]: Start isEmpty. Operand 5396 states and 15110 transitions. [2019-12-07 15:34:45,292 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 15:34:45,292 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:34:45,292 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:34:45,292 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:34:45,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:34:45,293 INFO L82 PathProgramCache]: Analyzing trace with hash -1374987048, now seen corresponding path program 1 times [2019-12-07 15:34:45,293 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:34:45,293 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558348444] [2019-12-07 15:34:45,293 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:34:45,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:34:45,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:34:45,328 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [558348444] [2019-12-07 15:34:45,328 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:34:45,328 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:34:45,328 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1356814370] [2019-12-07 15:34:45,329 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:34:45,329 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:34:45,329 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:34:45,329 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:34:45,329 INFO L87 Difference]: Start difference. First operand 5396 states and 15110 transitions. Second operand 3 states. [2019-12-07 15:34:45,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:34:45,345 INFO L93 Difference]: Finished difference Result 4969 states and 13714 transitions. [2019-12-07 15:34:45,345 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:34:45,346 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 15:34:45,346 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:34:45,349 INFO L225 Difference]: With dead ends: 4969 [2019-12-07 15:34:45,350 INFO L226 Difference]: Without dead ends: 4969 [2019-12-07 15:34:45,350 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:34:45,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4969 states. [2019-12-07 15:34:45,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4969 to 4689. [2019-12-07 15:34:45,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4689 states. [2019-12-07 15:34:45,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4689 states to 4689 states and 12942 transitions. [2019-12-07 15:34:45,405 INFO L78 Accepts]: Start accepts. Automaton has 4689 states and 12942 transitions. Word has length 67 [2019-12-07 15:34:45,405 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:34:45,405 INFO L462 AbstractCegarLoop]: Abstraction has 4689 states and 12942 transitions. [2019-12-07 15:34:45,406 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:34:45,406 INFO L276 IsEmpty]: Start isEmpty. Operand 4689 states and 12942 transitions. [2019-12-07 15:34:45,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 15:34:45,409 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:34:45,409 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:34:45,409 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:34:45,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:34:45,409 INFO L82 PathProgramCache]: Analyzing trace with hash 942277324, now seen corresponding path program 1 times [2019-12-07 15:34:45,409 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:34:45,409 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [52385460] [2019-12-07 15:34:45,409 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:34:45,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:34:45,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:34:45,474 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [52385460] [2019-12-07 15:34:45,474 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:34:45,474 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 15:34:45,475 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1127135110] [2019-12-07 15:34:45,475 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:34:45,475 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:34:45,475 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:34:45,475 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:34:45,475 INFO L87 Difference]: Start difference. First operand 4689 states and 12942 transitions. Second operand 6 states. [2019-12-07 15:34:45,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:34:45,537 INFO L93 Difference]: Finished difference Result 7861 states and 21688 transitions. [2019-12-07 15:34:45,538 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 15:34:45,538 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 68 [2019-12-07 15:34:45,538 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:34:45,540 INFO L225 Difference]: With dead ends: 7861 [2019-12-07 15:34:45,541 INFO L226 Difference]: Without dead ends: 3374 [2019-12-07 15:34:45,541 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 15:34:45,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3374 states. [2019-12-07 15:34:45,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3374 to 2819. [2019-12-07 15:34:45,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2819 states. [2019-12-07 15:34:45,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2819 states to 2819 states and 7667 transitions. [2019-12-07 15:34:45,577 INFO L78 Accepts]: Start accepts. Automaton has 2819 states and 7667 transitions. Word has length 68 [2019-12-07 15:34:45,577 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:34:45,577 INFO L462 AbstractCegarLoop]: Abstraction has 2819 states and 7667 transitions. [2019-12-07 15:34:45,577 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:34:45,577 INFO L276 IsEmpty]: Start isEmpty. Operand 2819 states and 7667 transitions. [2019-12-07 15:34:45,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 15:34:45,579 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:34:45,579 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:34:45,579 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:34:45,579 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:34:45,580 INFO L82 PathProgramCache]: Analyzing trace with hash -213601006, now seen corresponding path program 2 times [2019-12-07 15:34:45,580 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:34:45,580 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1910416094] [2019-12-07 15:34:45,580 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:34:45,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:34:45,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:34:45,655 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1910416094] [2019-12-07 15:34:45,655 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:34:45,655 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 15:34:45,655 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1924676018] [2019-12-07 15:34:45,656 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 15:34:45,656 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:34:45,656 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 15:34:45,656 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2019-12-07 15:34:45,656 INFO L87 Difference]: Start difference. First operand 2819 states and 7667 transitions. Second operand 7 states. [2019-12-07 15:34:45,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:34:45,712 INFO L93 Difference]: Finished difference Result 4936 states and 13582 transitions. [2019-12-07 15:34:45,712 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 15:34:45,712 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 68 [2019-12-07 15:34:45,712 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:34:45,714 INFO L225 Difference]: With dead ends: 4936 [2019-12-07 15:34:45,714 INFO L226 Difference]: Without dead ends: 2158 [2019-12-07 15:34:45,714 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2019-12-07 15:34:45,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2158 states. [2019-12-07 15:34:45,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2158 to 1771. [2019-12-07 15:34:45,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1771 states. [2019-12-07 15:34:45,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1771 states to 1771 states and 4877 transitions. [2019-12-07 15:34:45,738 INFO L78 Accepts]: Start accepts. Automaton has 1771 states and 4877 transitions. Word has length 68 [2019-12-07 15:34:45,738 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:34:45,738 INFO L462 AbstractCegarLoop]: Abstraction has 1771 states and 4877 transitions. [2019-12-07 15:34:45,738 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 15:34:45,738 INFO L276 IsEmpty]: Start isEmpty. Operand 1771 states and 4877 transitions. [2019-12-07 15:34:45,739 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 15:34:45,739 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:34:45,739 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:34:45,739 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:34:45,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:34:45,739 INFO L82 PathProgramCache]: Analyzing trace with hash -1259160564, now seen corresponding path program 3 times [2019-12-07 15:34:45,739 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:34:45,740 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [985203073] [2019-12-07 15:34:45,740 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:34:45,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 15:34:45,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 15:34:45,822 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 15:34:45,822 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 15:34:45,825 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] ULTIMATE.startENTRY-->L805: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= 0 v_~x~0_194) (= 0 v_~x$r_buff0_thd2~0_213) (= 0 v_~weak$$choice0~0_14) (= v_~x$mem_tmp~0_19 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t1888~0.base_20|) (= |v_#memory_int_21| (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1888~0.base_20| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1888~0.base_20|) |v_ULTIMATE.start_main_~#t1888~0.offset_17| 0))) (= 0 v_~x$w_buff0~0_268) (= 0 v_~x$r_buff1_thd2~0_212) (= v_~x$r_buff1_thd0~0_297 0) (< 0 |v_#StackHeapBarrier_17|) (= 0 v_~x$read_delayed_var~0.base_7) (= v_~x$r_buff1_thd1~0_187 0) (= v_~__unbuffered_p2_EBX~0_22 0) (= v_~x$r_buff0_thd0~0_372 0) (= 0 v_~x$read_delayed~0_6) (= v_~__unbuffered_cnt~0_155 0) (= 0 v_~x$w_buff1~0_230) (= 0 |v_#NULL.base_4|) (= 0 v_~x$r_buff1_thd3~0_195) (= 0 v_~x$r_buff0_thd3~0_123) (= |v_#NULL.offset_4| 0) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t1888~0.base_20| 4)) (= 0 v_~x$w_buff1_used~0_504) (= 0 v_~x$read_delayed_var~0.offset_7) (= v_~x$r_buff0_thd1~0_120 0) (= 0 |v_ULTIMATE.start_main_~#t1888~0.offset_17|) (= |v_#valid_53| (store .cse0 |v_ULTIMATE.start_main_~#t1888~0.base_20| 1)) (= 0 v_~__unbuffered_p2_EAX~0_22) (= v_~x$flush_delayed~0_34 0) (= v_~main$tmp_guard0~0_24 0) (= v_~weak$$choice2~0_110 0) (= v_~y~0_136 0) (= 0 v_~x$w_buff0_used~0_807) (= (select .cse0 |v_ULTIMATE.start_main_~#t1888~0.base_20|) 0) (= v_~main$tmp_guard1~0_22 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_22|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_21|, ~x$w_buff0~0=v_~x$w_buff0~0_268, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_27|, ~x$flush_delayed~0=v_~x$flush_delayed~0_34, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_39|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_29|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_45|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_187, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_123, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_50|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_36|, ULTIMATE.start_main_~#t1890~0.offset=|v_ULTIMATE.start_main_~#t1890~0.offset_16|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_45|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_32|, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_22, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_372, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_22, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_37|, ~x$w_buff1~0=v_~x$w_buff1~0_230, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_504, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_212, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_48|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_111|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_7, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_155, ~x~0=v_~x~0_194, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_120, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_33|, ULTIMATE.start_main_~#t1888~0.base=|v_ULTIMATE.start_main_~#t1888~0.base_20|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_31|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_29|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_195, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_22, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_125|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_17|, ~x$mem_tmp~0=v_~x$mem_tmp~0_19, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_25|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_31|, ~y~0=v_~y~0_136, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_10|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_23|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_25|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_48|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, ULTIMATE.start_main_~#t1888~0.offset=|v_ULTIMATE.start_main_~#t1888~0.offset_17|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_297, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_213, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_59|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_38|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_807, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_32|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_7, ULTIMATE.start_main_~#t1890~0.base=|v_ULTIMATE.start_main_~#t1890~0.base_20|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_21|, ULTIMATE.start_main_~#t1889~0.offset=|v_ULTIMATE.start_main_~#t1889~0.offset_17|, ~weak$$choice2~0=v_~weak$$choice2~0_110, ULTIMATE.start_main_~#t1889~0.base=|v_ULTIMATE.start_main_~#t1889~0.base_21|, ~x$read_delayed~0=v_~x$read_delayed~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ~x$w_buff0~0, ULTIMATE.start_main_#t~ite28, ~x$flush_delayed~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ~x$r_buff1_thd1~0, ~x$r_buff0_thd3~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_~#t1890~0.offset, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, #length, ~__unbuffered_p2_EAX~0, ~x$r_buff0_thd0~0, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ~x$w_buff1~0, ULTIMATE.start_main_#t~ite35, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~x$read_delayed_var~0.base, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~__unbuffered_cnt~0, ~x~0, ~x$r_buff0_thd1~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_~#t1888~0.base, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~x$r_buff1_thd3~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~x$mem_tmp~0, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ~y~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_~#t1888~0.offset, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~x$w_buff0_used~0, ULTIMATE.start_main_#t~ite41, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_~#t1890~0.base, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_~#t1889~0.offset, ~weak$$choice2~0, ULTIMATE.start_main_~#t1889~0.base, ~x$read_delayed~0] because there is no mapped edge [2019-12-07 15:34:45,825 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L805-1-->L807: Formula: (and (not (= |v_ULTIMATE.start_main_~#t1889~0.base_11| 0)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1889~0.base_11|) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1889~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1889~0.base_11|) |v_ULTIMATE.start_main_~#t1889~0.offset_10| 1)) |v_#memory_int_13|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1889~0.base_11| 4)) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t1889~0.base_11| 1)) (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t1889~0.base_11|)) (= 0 |v_ULTIMATE.start_main_~#t1889~0.offset_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_6|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t1889~0.offset=|v_ULTIMATE.start_main_~#t1889~0.offset_10|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1889~0.base=|v_ULTIMATE.start_main_~#t1889~0.base_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, #valid, #memory_int, ULTIMATE.start_main_~#t1889~0.offset, #length, ULTIMATE.start_main_~#t1889~0.base] because there is no mapped edge [2019-12-07 15:34:45,826 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L807-1-->L809: Formula: (and (= (select |v_#valid_28| |v_ULTIMATE.start_main_~#t1890~0.base_9|) 0) (= (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t1890~0.base_9| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t1890~0.base_9|) |v_ULTIMATE.start_main_~#t1890~0.offset_8| 2)) |v_#memory_int_9|) (not (= 0 |v_ULTIMATE.start_main_~#t1890~0.base_9|)) (= |v_#valid_27| (store |v_#valid_28| |v_ULTIMATE.start_main_~#t1890~0.base_9| 1)) (= (store |v_#length_14| |v_ULTIMATE.start_main_~#t1890~0.base_9| 4) |v_#length_13|) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t1890~0.base_9|) (= 0 |v_ULTIMATE.start_main_~#t1890~0.offset_8|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_28|, #memory_int=|v_#memory_int_10|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, ULTIMATE.start_main_~#t1890~0.base=|v_ULTIMATE.start_main_~#t1890~0.base_9|, #valid=|v_#valid_27|, #memory_int=|v_#memory_int_9|, #length=|v_#length_13|, ULTIMATE.start_main_~#t1890~0.offset=|v_ULTIMATE.start_main_~#t1890~0.offset_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_~#t1890~0.base, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1890~0.offset] because there is no mapped edge [2019-12-07 15:34:45,826 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] P1ENTRY-->L4-3: Formula: (and (not (= 0 v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11)) (= v_P1Thread1of1ForFork1_~arg.offset_9 |v_P1Thread1of1ForFork1_#in~arg.offset_11|) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9| v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11) (= 1 v_~x$w_buff0_used~0_98) (= 2 v_~x$w_buff0~0_31) (= v_P1Thread1of1ForFork1_~arg.base_9 |v_P1Thread1of1ForFork1_#in~arg.base_11|) (= v_~x$w_buff1_used~0_55 v_~x$w_buff0_used~0_99) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9| (ite (not (and (not (= (mod v_~x$w_buff0_used~0_98 256) 0)) (not (= 0 (mod v_~x$w_buff1_used~0_55 256))))) 1 0)) (= v_~x$w_buff0~0_32 v_~x$w_buff1~0_21)) InVars {~x$w_buff0~0=v_~x$w_buff0~0_32, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_11|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_11|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_99} OutVars{P1Thread1of1ForFork1___VERIFIER_assert_~expression=v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11, ~x$w_buff0~0=v_~x$w_buff0~0_31, P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_9, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression=|v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9|, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_9, ~x$w_buff1~0=v_~x$w_buff1~0_21, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_11|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_11|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_55, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_98} AuxVars[] AssignedVars[P1Thread1of1ForFork1___VERIFIER_assert_~expression, ~x$w_buff0~0, P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression, P1Thread1of1ForFork1_~arg.base, ~x$w_buff1~0, ~x$w_buff1_used~0, ~x$w_buff0_used~0] because there is no mapped edge [2019-12-07 15:34:45,828 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L782-2-->L782-4: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff1_thd3~0_In1645016918 256))) (.cse1 (= (mod ~x$w_buff1_used~0_In1645016918 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite15_Out1645016918| ~x~0_In1645016918)) (and (not .cse0) (= |P2Thread1of1ForFork2_#t~ite15_Out1645016918| ~x$w_buff1~0_In1645016918) (not .cse1)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In1645016918, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1645016918, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1645016918, ~x~0=~x~0_In1645016918} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out1645016918|, ~x$w_buff1~0=~x$w_buff1~0_In1645016918, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1645016918, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1645016918, ~x~0=~x~0_In1645016918} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 15:34:45,828 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L782-4-->L783: Formula: (= v_~x~0_20 |v_P2Thread1of1ForFork2_#t~ite15_10|) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_10|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_9|, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_5|, ~x~0=v_~x~0_20} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, P2Thread1of1ForFork2_#t~ite16, ~x~0] because there is no mapped edge [2019-12-07 15:34:45,828 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L783-->L783-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In1595319598 256) 0)) (.cse1 (= 0 (mod ~x$r_buff0_thd3~0_In1595319598 256)))) (or (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In1595319598 |P2Thread1of1ForFork2_#t~ite17_Out1595319598|)) (and (= |P2Thread1of1ForFork2_#t~ite17_Out1595319598| 0) (not .cse0) (not .cse1)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1595319598, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1595319598} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1595319598, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out1595319598|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1595319598} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 15:34:45,828 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L784-->L784-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In1587938580 256) 0)) (.cse1 (= (mod ~x$r_buff0_thd3~0_In1587938580 256) 0)) (.cse3 (= 0 (mod ~x$r_buff1_thd3~0_In1587938580 256))) (.cse2 (= (mod ~x$w_buff1_used~0_In1587938580 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite18_Out1587938580|)) (and (or .cse0 .cse1) (or .cse3 .cse2) (= ~x$w_buff1_used~0_In1587938580 |P2Thread1of1ForFork2_#t~ite18_Out1587938580|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In1587938580, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1587938580, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1587938580, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1587938580} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In1587938580, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1587938580, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1587938580, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out1587938580|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1587938580} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 15:34:45,828 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L733-2-->L733-5: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff1_thd1~0_In-2007067274 256))) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In-2007067274 256))) (.cse2 (= |P0Thread1of1ForFork0_#t~ite4_Out-2007067274| |P0Thread1of1ForFork0_#t~ite3_Out-2007067274|))) (or (and (or .cse0 .cse1) .cse2 (= |P0Thread1of1ForFork0_#t~ite3_Out-2007067274| ~x~0_In-2007067274)) (and (not .cse0) (not .cse1) (= ~x$w_buff1~0_In-2007067274 |P0Thread1of1ForFork0_#t~ite3_Out-2007067274|) .cse2))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-2007067274, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-2007067274, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-2007067274, ~x~0=~x~0_In-2007067274} OutVars{P0Thread1of1ForFork0_#t~ite3=|P0Thread1of1ForFork0_#t~ite3_Out-2007067274|, P0Thread1of1ForFork0_#t~ite4=|P0Thread1of1ForFork0_#t~ite4_Out-2007067274|, ~x$w_buff1~0=~x$w_buff1~0_In-2007067274, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-2007067274, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-2007067274, ~x~0=~x~0_In-2007067274} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite3, P0Thread1of1ForFork0_#t~ite4] because there is no mapped edge [2019-12-07 15:34:45,829 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [774] [774] L734-->L734-2: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd1~0_In-286546178 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In-286546178 256)))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite5_Out-286546178| 0)) (and (or .cse1 .cse0) (= ~x$w_buff0_used~0_In-286546178 |P0Thread1of1ForFork0_#t~ite5_Out-286546178|)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-286546178, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-286546178} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-286546178|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-286546178, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-286546178} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 15:34:45,829 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L735-->L735-2: Formula: (let ((.cse1 (= (mod ~x$r_buff1_thd1~0_In-284324625 256) 0)) (.cse0 (= 0 (mod ~x$w_buff1_used~0_In-284324625 256))) (.cse3 (= (mod ~x$r_buff0_thd1~0_In-284324625 256) 0)) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In-284324625 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite6_Out-284324625| 0)) (and (or .cse1 .cse0) (= |P0Thread1of1ForFork0_#t~ite6_Out-284324625| ~x$w_buff1_used~0_In-284324625) (or .cse3 .cse2)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-284324625, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-284324625, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-284324625, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-284324625} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out-284324625|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-284324625, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-284324625, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-284324625, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-284324625} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 15:34:45,829 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L785-->L785-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-1328237857 256))) (.cse0 (= (mod ~x$r_buff0_thd3~0_In-1328237857 256) 0))) (or (and (not .cse0) (= 0 |P2Thread1of1ForFork2_#t~ite19_Out-1328237857|) (not .cse1)) (and (= ~x$r_buff0_thd3~0_In-1328237857 |P2Thread1of1ForFork2_#t~ite19_Out-1328237857|) (or .cse1 .cse0)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1328237857, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1328237857} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1328237857, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-1328237857|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1328237857} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 15:34:45,830 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L786-->L786-2: Formula: (let ((.cse0 (= (mod ~x$w_buff1_used~0_In-1701378672 256) 0)) (.cse1 (= (mod ~x$r_buff1_thd3~0_In-1701378672 256) 0)) (.cse2 (= 0 (mod ~x$r_buff0_thd3~0_In-1701378672 256))) (.cse3 (= (mod ~x$w_buff0_used~0_In-1701378672 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite20_Out-1701378672| ~x$r_buff1_thd3~0_In-1701378672) (or .cse2 .cse3)) (and (= |P2Thread1of1ForFork2_#t~ite20_Out-1701378672| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1701378672, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1701378672, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1701378672, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1701378672} OutVars{P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-1701378672|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1701378672, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1701378672, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1701378672, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1701378672} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 15:34:45,830 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L786-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74) (= |v_P2Thread1of1ForFork2_#t~ite20_52| v_~x$r_buff1_thd3~0_147)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_52|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_51|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_147, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~x$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 15:34:45,830 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L736-->L736-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In-265656019 256) 0)) (.cse1 (= (mod ~x$r_buff0_thd1~0_In-265656019 256) 0))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite7_Out-265656019| 0)) (and (or .cse0 .cse1) (= |P0Thread1of1ForFork0_#t~ite7_Out-265656019| ~x$r_buff0_thd1~0_In-265656019)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-265656019, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-265656019} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-265656019, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out-265656019|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-265656019} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-12-07 15:34:45,830 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L737-->L737-2: Formula: (let ((.cse3 (= 0 (mod ~x$r_buff0_thd1~0_In-2125069599 256))) (.cse2 (= (mod ~x$w_buff0_used~0_In-2125069599 256) 0)) (.cse0 (= 0 (mod ~x$r_buff1_thd1~0_In-2125069599 256))) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In-2125069599 256)))) (or (and (= |P0Thread1of1ForFork0_#t~ite8_Out-2125069599| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse0 .cse1) (= |P0Thread1of1ForFork0_#t~ite8_Out-2125069599| ~x$r_buff1_thd1~0_In-2125069599)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-2125069599, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-2125069599, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-2125069599, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-2125069599} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-2125069599, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-2125069599|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-2125069599, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-2125069599, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-2125069599} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 15:34:45,830 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L737-2-->P0EXIT: Formula: (and (= v_~x$r_buff1_thd1~0_61 |v_P0Thread1of1ForFork0_#t~ite8_24|) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_45 1) v_~__unbuffered_cnt~0_44)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_45} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_23|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_44, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_61} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, ~x$r_buff1_thd1~0] because there is no mapped edge [2019-12-07 15:34:45,831 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L763-->L763-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff0_thd2~0_In1827442122 256))) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In1827442122 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite11_Out1827442122|)) (and (= ~x$w_buff0_used~0_In1827442122 |P1Thread1of1ForFork1_#t~ite11_Out1827442122|) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1827442122, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1827442122} OutVars{P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out1827442122|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1827442122, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1827442122} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 15:34:45,831 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L764-->L764-2: Formula: (let ((.cse2 (= (mod ~x$w_buff1_used~0_In-380112145 256) 0)) (.cse3 (= 0 (mod ~x$r_buff1_thd2~0_In-380112145 256))) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In-380112145 256))) (.cse0 (= 0 (mod ~x$r_buff0_thd2~0_In-380112145 256)))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite12_Out-380112145| ~x$w_buff1_used~0_In-380112145) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |P1Thread1of1ForFork1_#t~ite12_Out-380112145| 0)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-380112145, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-380112145, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-380112145, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-380112145} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-380112145, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-380112145, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-380112145|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-380112145, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-380112145} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 15:34:45,831 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L765-->L766: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In1344326865 256) 0)) (.cse2 (= ~x$r_buff0_thd2~0_Out1344326865 ~x$r_buff0_thd2~0_In1344326865)) (.cse0 (= (mod ~x$r_buff0_thd2~0_In1344326865 256) 0))) (or (and (= ~x$r_buff0_thd2~0_Out1344326865 0) (not .cse0) (not .cse1)) (and .cse1 .cse2) (and .cse2 .cse0))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1344326865, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1344326865} OutVars{P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out1344326865|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out1344326865, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1344326865} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-12-07 15:34:45,831 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L766-->L766-2: Formula: (let ((.cse2 (= 0 (mod ~x$w_buff1_used~0_In-1308236788 256))) (.cse3 (= (mod ~x$r_buff1_thd2~0_In-1308236788 256) 0)) (.cse1 (= (mod ~x$w_buff0_used~0_In-1308236788 256) 0)) (.cse0 (= (mod ~x$r_buff0_thd2~0_In-1308236788 256) 0))) (or (and (= ~x$r_buff1_thd2~0_In-1308236788 |P1Thread1of1ForFork1_#t~ite14_Out-1308236788|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |P1Thread1of1ForFork1_#t~ite14_Out-1308236788|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1308236788, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1308236788, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1308236788, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1308236788} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-1308236788, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1308236788, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1308236788, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-1308236788|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1308236788} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 15:34:45,832 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L766-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0) (= v_~x$r_buff1_thd2~0_162 |v_P1Thread1of1ForFork1_#t~ite14_40|) (= (+ v_~__unbuffered_cnt~0_93 1) v_~__unbuffered_cnt~0_92)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_93, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_40|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_162, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_92, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_39|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 15:34:45,832 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L809-1-->L815: Formula: (and (= v_~main$tmp_guard0~0_6 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= 0 (mod v_~main$tmp_guard0~0_6 256)))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 15:34:45,832 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L815-2-->L815-5: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite24_Out703209588| |ULTIMATE.start_main_#t~ite25_Out703209588|)) (.cse1 (= 0 (mod ~x$r_buff1_thd0~0_In703209588 256))) (.cse2 (= 0 (mod ~x$w_buff1_used~0_In703209588 256)))) (or (and .cse0 (not .cse1) (not .cse2) (= |ULTIMATE.start_main_#t~ite24_Out703209588| ~x$w_buff1~0_In703209588)) (and .cse0 (or .cse1 .cse2) (= ~x~0_In703209588 |ULTIMATE.start_main_#t~ite24_Out703209588|)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In703209588, ~x$w_buff1_used~0=~x$w_buff1_used~0_In703209588, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In703209588, ~x~0=~x~0_In703209588} OutVars{~x$w_buff1~0=~x$w_buff1~0_In703209588, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out703209588|, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out703209588|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In703209588, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In703209588, ~x~0=~x~0_In703209588} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 15:34:45,832 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L816-->L816-2: Formula: (let ((.cse0 (= (mod ~x$r_buff0_thd0~0_In-1856517497 256) 0)) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In-1856517497 256)))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite26_Out-1856517497|)) (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In-1856517497 |ULTIMATE.start_main_#t~ite26_Out-1856517497|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1856517497, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1856517497} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1856517497, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-1856517497|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1856517497} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 15:34:45,833 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L817-->L817-2: Formula: (let ((.cse2 (= 0 (mod ~x$r_buff1_thd0~0_In-191140352 256))) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In-191140352 256))) (.cse1 (= (mod ~x$r_buff0_thd0~0_In-191140352 256) 0)) (.cse0 (= (mod ~x$w_buff0_used~0_In-191140352 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite27_Out-191140352| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (or .cse1 .cse0) (= ~x$w_buff1_used~0_In-191140352 |ULTIMATE.start_main_#t~ite27_Out-191140352|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-191140352, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-191140352, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-191140352, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-191140352} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-191140352, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-191140352, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-191140352|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-191140352, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-191140352} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 15:34:45,833 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L818-->L818-2: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In529469846 256) 0)) (.cse0 (= (mod ~x$r_buff0_thd0~0_In529469846 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite28_Out529469846|)) (and (= ~x$r_buff0_thd0~0_In529469846 |ULTIMATE.start_main_#t~ite28_Out529469846|) (or .cse1 .cse0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In529469846, ~x$w_buff0_used~0=~x$w_buff0_used~0_In529469846} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In529469846, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out529469846|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In529469846} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 15:34:45,833 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L819-->L819-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In1475788147 256))) (.cse0 (= (mod ~x$r_buff0_thd0~0_In1475788147 256) 0)) (.cse2 (= (mod ~x$r_buff1_thd0~0_In1475788147 256) 0)) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In1475788147 256)))) (or (and (or .cse0 .cse1) (= ~x$r_buff1_thd0~0_In1475788147 |ULTIMATE.start_main_#t~ite29_Out1475788147|) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite29_Out1475788147|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1475788147, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1475788147, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1475788147, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1475788147} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1475788147, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out1475788147|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1475788147, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1475788147, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1475788147} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 15:34:45,836 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L831-->L832: Formula: (and (= v_~x$r_buff0_thd0~0_112 v_~x$r_buff0_thd0~0_111) (not (= (mod v_~weak$$choice2~0_23 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_112, ~weak$$choice2~0=v_~weak$$choice2~0_23} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_111, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_6|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_10|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_6|, ~weak$$choice2~0=v_~weak$$choice2~0_23} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 15:34:45,836 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L834-->L837-1: Formula: (and (= (mod v_~main$tmp_guard1~0_13 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (not (= (mod v_~x$flush_delayed~0_23 256) 0)) (= v_~x$mem_tmp~0_13 v_~x~0_153) (= v_~x$flush_delayed~0_22 0)) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_23, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_13, ~x$mem_tmp~0=v_~x$mem_tmp~0_13} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_18|, ~x$flush_delayed~0=v_~x$flush_delayed~0_22, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_13, ~x$mem_tmp~0=v_~x$mem_tmp~0_13, ~x~0=v_~x~0_153, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ~x$flush_delayed~0, ~x~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 15:34:45,836 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L837-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 15:34:45,905 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 03:34:45 BasicIcfg [2019-12-07 15:34:45,905 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 15:34:45,905 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 15:34:45,905 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 15:34:45,906 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 15:34:45,906 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 03:32:05" (3/4) ... [2019-12-07 15:34:45,908 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 15:34:45,908 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] ULTIMATE.startENTRY-->L805: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= 0 v_~x~0_194) (= 0 v_~x$r_buff0_thd2~0_213) (= 0 v_~weak$$choice0~0_14) (= v_~x$mem_tmp~0_19 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t1888~0.base_20|) (= |v_#memory_int_21| (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1888~0.base_20| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1888~0.base_20|) |v_ULTIMATE.start_main_~#t1888~0.offset_17| 0))) (= 0 v_~x$w_buff0~0_268) (= 0 v_~x$r_buff1_thd2~0_212) (= v_~x$r_buff1_thd0~0_297 0) (< 0 |v_#StackHeapBarrier_17|) (= 0 v_~x$read_delayed_var~0.base_7) (= v_~x$r_buff1_thd1~0_187 0) (= v_~__unbuffered_p2_EBX~0_22 0) (= v_~x$r_buff0_thd0~0_372 0) (= 0 v_~x$read_delayed~0_6) (= v_~__unbuffered_cnt~0_155 0) (= 0 v_~x$w_buff1~0_230) (= 0 |v_#NULL.base_4|) (= 0 v_~x$r_buff1_thd3~0_195) (= 0 v_~x$r_buff0_thd3~0_123) (= |v_#NULL.offset_4| 0) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t1888~0.base_20| 4)) (= 0 v_~x$w_buff1_used~0_504) (= 0 v_~x$read_delayed_var~0.offset_7) (= v_~x$r_buff0_thd1~0_120 0) (= 0 |v_ULTIMATE.start_main_~#t1888~0.offset_17|) (= |v_#valid_53| (store .cse0 |v_ULTIMATE.start_main_~#t1888~0.base_20| 1)) (= 0 v_~__unbuffered_p2_EAX~0_22) (= v_~x$flush_delayed~0_34 0) (= v_~main$tmp_guard0~0_24 0) (= v_~weak$$choice2~0_110 0) (= v_~y~0_136 0) (= 0 v_~x$w_buff0_used~0_807) (= (select .cse0 |v_ULTIMATE.start_main_~#t1888~0.base_20|) 0) (= v_~main$tmp_guard1~0_22 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_22|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_21|, ~x$w_buff0~0=v_~x$w_buff0~0_268, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_27|, ~x$flush_delayed~0=v_~x$flush_delayed~0_34, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_39|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_29|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_45|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_187, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_123, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_50|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_36|, ULTIMATE.start_main_~#t1890~0.offset=|v_ULTIMATE.start_main_~#t1890~0.offset_16|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_45|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_32|, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_22, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_372, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_22, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_37|, ~x$w_buff1~0=v_~x$w_buff1~0_230, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_504, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_212, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_48|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_111|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_7, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_155, ~x~0=v_~x~0_194, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_120, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_33|, ULTIMATE.start_main_~#t1888~0.base=|v_ULTIMATE.start_main_~#t1888~0.base_20|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_31|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_29|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_195, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_22, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_125|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_17|, ~x$mem_tmp~0=v_~x$mem_tmp~0_19, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_25|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_31|, ~y~0=v_~y~0_136, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_10|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_23|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_25|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_48|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, ULTIMATE.start_main_~#t1888~0.offset=|v_ULTIMATE.start_main_~#t1888~0.offset_17|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_297, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_213, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_59|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_38|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_807, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_32|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_7, ULTIMATE.start_main_~#t1890~0.base=|v_ULTIMATE.start_main_~#t1890~0.base_20|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_21|, ULTIMATE.start_main_~#t1889~0.offset=|v_ULTIMATE.start_main_~#t1889~0.offset_17|, ~weak$$choice2~0=v_~weak$$choice2~0_110, ULTIMATE.start_main_~#t1889~0.base=|v_ULTIMATE.start_main_~#t1889~0.base_21|, ~x$read_delayed~0=v_~x$read_delayed~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ~x$w_buff0~0, ULTIMATE.start_main_#t~ite28, ~x$flush_delayed~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ~x$r_buff1_thd1~0, ~x$r_buff0_thd3~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_~#t1890~0.offset, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, #length, ~__unbuffered_p2_EAX~0, ~x$r_buff0_thd0~0, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ~x$w_buff1~0, ULTIMATE.start_main_#t~ite35, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~x$read_delayed_var~0.base, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~__unbuffered_cnt~0, ~x~0, ~x$r_buff0_thd1~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_~#t1888~0.base, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~x$r_buff1_thd3~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~x$mem_tmp~0, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ~y~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_~#t1888~0.offset, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~x$w_buff0_used~0, ULTIMATE.start_main_#t~ite41, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_~#t1890~0.base, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_~#t1889~0.offset, ~weak$$choice2~0, ULTIMATE.start_main_~#t1889~0.base, ~x$read_delayed~0] because there is no mapped edge [2019-12-07 15:34:45,909 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L805-1-->L807: Formula: (and (not (= |v_ULTIMATE.start_main_~#t1889~0.base_11| 0)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1889~0.base_11|) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1889~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1889~0.base_11|) |v_ULTIMATE.start_main_~#t1889~0.offset_10| 1)) |v_#memory_int_13|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1889~0.base_11| 4)) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t1889~0.base_11| 1)) (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t1889~0.base_11|)) (= 0 |v_ULTIMATE.start_main_~#t1889~0.offset_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_6|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t1889~0.offset=|v_ULTIMATE.start_main_~#t1889~0.offset_10|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1889~0.base=|v_ULTIMATE.start_main_~#t1889~0.base_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, #valid, #memory_int, ULTIMATE.start_main_~#t1889~0.offset, #length, ULTIMATE.start_main_~#t1889~0.base] because there is no mapped edge [2019-12-07 15:34:45,909 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L807-1-->L809: Formula: (and (= (select |v_#valid_28| |v_ULTIMATE.start_main_~#t1890~0.base_9|) 0) (= (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t1890~0.base_9| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t1890~0.base_9|) |v_ULTIMATE.start_main_~#t1890~0.offset_8| 2)) |v_#memory_int_9|) (not (= 0 |v_ULTIMATE.start_main_~#t1890~0.base_9|)) (= |v_#valid_27| (store |v_#valid_28| |v_ULTIMATE.start_main_~#t1890~0.base_9| 1)) (= (store |v_#length_14| |v_ULTIMATE.start_main_~#t1890~0.base_9| 4) |v_#length_13|) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t1890~0.base_9|) (= 0 |v_ULTIMATE.start_main_~#t1890~0.offset_8|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_28|, #memory_int=|v_#memory_int_10|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, ULTIMATE.start_main_~#t1890~0.base=|v_ULTIMATE.start_main_~#t1890~0.base_9|, #valid=|v_#valid_27|, #memory_int=|v_#memory_int_9|, #length=|v_#length_13|, ULTIMATE.start_main_~#t1890~0.offset=|v_ULTIMATE.start_main_~#t1890~0.offset_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_~#t1890~0.base, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1890~0.offset] because there is no mapped edge [2019-12-07 15:34:45,910 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] P1ENTRY-->L4-3: Formula: (and (not (= 0 v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11)) (= v_P1Thread1of1ForFork1_~arg.offset_9 |v_P1Thread1of1ForFork1_#in~arg.offset_11|) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9| v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11) (= 1 v_~x$w_buff0_used~0_98) (= 2 v_~x$w_buff0~0_31) (= v_P1Thread1of1ForFork1_~arg.base_9 |v_P1Thread1of1ForFork1_#in~arg.base_11|) (= v_~x$w_buff1_used~0_55 v_~x$w_buff0_used~0_99) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9| (ite (not (and (not (= (mod v_~x$w_buff0_used~0_98 256) 0)) (not (= 0 (mod v_~x$w_buff1_used~0_55 256))))) 1 0)) (= v_~x$w_buff0~0_32 v_~x$w_buff1~0_21)) InVars {~x$w_buff0~0=v_~x$w_buff0~0_32, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_11|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_11|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_99} OutVars{P1Thread1of1ForFork1___VERIFIER_assert_~expression=v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11, ~x$w_buff0~0=v_~x$w_buff0~0_31, P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_9, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression=|v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9|, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_9, ~x$w_buff1~0=v_~x$w_buff1~0_21, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_11|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_11|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_55, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_98} AuxVars[] AssignedVars[P1Thread1of1ForFork1___VERIFIER_assert_~expression, ~x$w_buff0~0, P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression, P1Thread1of1ForFork1_~arg.base, ~x$w_buff1~0, ~x$w_buff1_used~0, ~x$w_buff0_used~0] because there is no mapped edge [2019-12-07 15:34:45,911 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L782-2-->L782-4: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff1_thd3~0_In1645016918 256))) (.cse1 (= (mod ~x$w_buff1_used~0_In1645016918 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite15_Out1645016918| ~x~0_In1645016918)) (and (not .cse0) (= |P2Thread1of1ForFork2_#t~ite15_Out1645016918| ~x$w_buff1~0_In1645016918) (not .cse1)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In1645016918, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1645016918, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1645016918, ~x~0=~x~0_In1645016918} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out1645016918|, ~x$w_buff1~0=~x$w_buff1~0_In1645016918, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1645016918, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1645016918, ~x~0=~x~0_In1645016918} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 15:34:45,911 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L782-4-->L783: Formula: (= v_~x~0_20 |v_P2Thread1of1ForFork2_#t~ite15_10|) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_10|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_9|, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_5|, ~x~0=v_~x~0_20} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, P2Thread1of1ForFork2_#t~ite16, ~x~0] because there is no mapped edge [2019-12-07 15:34:45,911 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L783-->L783-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In1595319598 256) 0)) (.cse1 (= 0 (mod ~x$r_buff0_thd3~0_In1595319598 256)))) (or (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In1595319598 |P2Thread1of1ForFork2_#t~ite17_Out1595319598|)) (and (= |P2Thread1of1ForFork2_#t~ite17_Out1595319598| 0) (not .cse0) (not .cse1)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1595319598, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1595319598} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1595319598, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out1595319598|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1595319598} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 15:34:45,912 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L784-->L784-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In1587938580 256) 0)) (.cse1 (= (mod ~x$r_buff0_thd3~0_In1587938580 256) 0)) (.cse3 (= 0 (mod ~x$r_buff1_thd3~0_In1587938580 256))) (.cse2 (= (mod ~x$w_buff1_used~0_In1587938580 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite18_Out1587938580|)) (and (or .cse0 .cse1) (or .cse3 .cse2) (= ~x$w_buff1_used~0_In1587938580 |P2Thread1of1ForFork2_#t~ite18_Out1587938580|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In1587938580, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1587938580, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1587938580, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1587938580} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In1587938580, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1587938580, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1587938580, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out1587938580|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1587938580} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 15:34:45,912 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L733-2-->L733-5: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff1_thd1~0_In-2007067274 256))) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In-2007067274 256))) (.cse2 (= |P0Thread1of1ForFork0_#t~ite4_Out-2007067274| |P0Thread1of1ForFork0_#t~ite3_Out-2007067274|))) (or (and (or .cse0 .cse1) .cse2 (= |P0Thread1of1ForFork0_#t~ite3_Out-2007067274| ~x~0_In-2007067274)) (and (not .cse0) (not .cse1) (= ~x$w_buff1~0_In-2007067274 |P0Thread1of1ForFork0_#t~ite3_Out-2007067274|) .cse2))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-2007067274, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-2007067274, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-2007067274, ~x~0=~x~0_In-2007067274} OutVars{P0Thread1of1ForFork0_#t~ite3=|P0Thread1of1ForFork0_#t~ite3_Out-2007067274|, P0Thread1of1ForFork0_#t~ite4=|P0Thread1of1ForFork0_#t~ite4_Out-2007067274|, ~x$w_buff1~0=~x$w_buff1~0_In-2007067274, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-2007067274, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-2007067274, ~x~0=~x~0_In-2007067274} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite3, P0Thread1of1ForFork0_#t~ite4] because there is no mapped edge [2019-12-07 15:34:45,912 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [774] [774] L734-->L734-2: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd1~0_In-286546178 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In-286546178 256)))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite5_Out-286546178| 0)) (and (or .cse1 .cse0) (= ~x$w_buff0_used~0_In-286546178 |P0Thread1of1ForFork0_#t~ite5_Out-286546178|)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-286546178, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-286546178} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-286546178|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-286546178, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-286546178} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 15:34:45,913 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L735-->L735-2: Formula: (let ((.cse1 (= (mod ~x$r_buff1_thd1~0_In-284324625 256) 0)) (.cse0 (= 0 (mod ~x$w_buff1_used~0_In-284324625 256))) (.cse3 (= (mod ~x$r_buff0_thd1~0_In-284324625 256) 0)) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In-284324625 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite6_Out-284324625| 0)) (and (or .cse1 .cse0) (= |P0Thread1of1ForFork0_#t~ite6_Out-284324625| ~x$w_buff1_used~0_In-284324625) (or .cse3 .cse2)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-284324625, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-284324625, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-284324625, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-284324625} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out-284324625|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-284324625, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-284324625, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-284324625, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-284324625} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 15:34:45,913 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L785-->L785-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-1328237857 256))) (.cse0 (= (mod ~x$r_buff0_thd3~0_In-1328237857 256) 0))) (or (and (not .cse0) (= 0 |P2Thread1of1ForFork2_#t~ite19_Out-1328237857|) (not .cse1)) (and (= ~x$r_buff0_thd3~0_In-1328237857 |P2Thread1of1ForFork2_#t~ite19_Out-1328237857|) (or .cse1 .cse0)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1328237857, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1328237857} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1328237857, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-1328237857|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1328237857} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 15:34:45,914 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L786-->L786-2: Formula: (let ((.cse0 (= (mod ~x$w_buff1_used~0_In-1701378672 256) 0)) (.cse1 (= (mod ~x$r_buff1_thd3~0_In-1701378672 256) 0)) (.cse2 (= 0 (mod ~x$r_buff0_thd3~0_In-1701378672 256))) (.cse3 (= (mod ~x$w_buff0_used~0_In-1701378672 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite20_Out-1701378672| ~x$r_buff1_thd3~0_In-1701378672) (or .cse2 .cse3)) (and (= |P2Thread1of1ForFork2_#t~ite20_Out-1701378672| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1701378672, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1701378672, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1701378672, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1701378672} OutVars{P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-1701378672|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1701378672, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1701378672, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1701378672, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1701378672} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 15:34:45,914 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L786-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74) (= |v_P2Thread1of1ForFork2_#t~ite20_52| v_~x$r_buff1_thd3~0_147)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_52|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_51|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_147, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~x$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 15:34:45,915 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L736-->L736-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In-265656019 256) 0)) (.cse1 (= (mod ~x$r_buff0_thd1~0_In-265656019 256) 0))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite7_Out-265656019| 0)) (and (or .cse0 .cse1) (= |P0Thread1of1ForFork0_#t~ite7_Out-265656019| ~x$r_buff0_thd1~0_In-265656019)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-265656019, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-265656019} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-265656019, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out-265656019|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-265656019} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-12-07 15:34:45,915 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L737-->L737-2: Formula: (let ((.cse3 (= 0 (mod ~x$r_buff0_thd1~0_In-2125069599 256))) (.cse2 (= (mod ~x$w_buff0_used~0_In-2125069599 256) 0)) (.cse0 (= 0 (mod ~x$r_buff1_thd1~0_In-2125069599 256))) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In-2125069599 256)))) (or (and (= |P0Thread1of1ForFork0_#t~ite8_Out-2125069599| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse0 .cse1) (= |P0Thread1of1ForFork0_#t~ite8_Out-2125069599| ~x$r_buff1_thd1~0_In-2125069599)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-2125069599, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-2125069599, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-2125069599, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-2125069599} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-2125069599, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-2125069599|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-2125069599, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-2125069599, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-2125069599} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 15:34:45,915 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L737-2-->P0EXIT: Formula: (and (= v_~x$r_buff1_thd1~0_61 |v_P0Thread1of1ForFork0_#t~ite8_24|) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_45 1) v_~__unbuffered_cnt~0_44)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_45} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_23|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_44, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_61} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, ~x$r_buff1_thd1~0] because there is no mapped edge [2019-12-07 15:34:45,916 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L763-->L763-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff0_thd2~0_In1827442122 256))) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In1827442122 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite11_Out1827442122|)) (and (= ~x$w_buff0_used~0_In1827442122 |P1Thread1of1ForFork1_#t~ite11_Out1827442122|) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1827442122, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1827442122} OutVars{P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out1827442122|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1827442122, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1827442122} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 15:34:45,916 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L764-->L764-2: Formula: (let ((.cse2 (= (mod ~x$w_buff1_used~0_In-380112145 256) 0)) (.cse3 (= 0 (mod ~x$r_buff1_thd2~0_In-380112145 256))) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In-380112145 256))) (.cse0 (= 0 (mod ~x$r_buff0_thd2~0_In-380112145 256)))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite12_Out-380112145| ~x$w_buff1_used~0_In-380112145) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |P1Thread1of1ForFork1_#t~ite12_Out-380112145| 0)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-380112145, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-380112145, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-380112145, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-380112145} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-380112145, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-380112145, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-380112145|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-380112145, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-380112145} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 15:34:45,917 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L765-->L766: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In1344326865 256) 0)) (.cse2 (= ~x$r_buff0_thd2~0_Out1344326865 ~x$r_buff0_thd2~0_In1344326865)) (.cse0 (= (mod ~x$r_buff0_thd2~0_In1344326865 256) 0))) (or (and (= ~x$r_buff0_thd2~0_Out1344326865 0) (not .cse0) (not .cse1)) (and .cse1 .cse2) (and .cse2 .cse0))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1344326865, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1344326865} OutVars{P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out1344326865|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out1344326865, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1344326865} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-12-07 15:34:45,917 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L766-->L766-2: Formula: (let ((.cse2 (= 0 (mod ~x$w_buff1_used~0_In-1308236788 256))) (.cse3 (= (mod ~x$r_buff1_thd2~0_In-1308236788 256) 0)) (.cse1 (= (mod ~x$w_buff0_used~0_In-1308236788 256) 0)) (.cse0 (= (mod ~x$r_buff0_thd2~0_In-1308236788 256) 0))) (or (and (= ~x$r_buff1_thd2~0_In-1308236788 |P1Thread1of1ForFork1_#t~ite14_Out-1308236788|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |P1Thread1of1ForFork1_#t~ite14_Out-1308236788|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1308236788, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1308236788, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1308236788, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1308236788} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-1308236788, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1308236788, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1308236788, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-1308236788|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1308236788} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 15:34:45,917 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L766-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0) (= v_~x$r_buff1_thd2~0_162 |v_P1Thread1of1ForFork1_#t~ite14_40|) (= (+ v_~__unbuffered_cnt~0_93 1) v_~__unbuffered_cnt~0_92)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_93, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_40|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_162, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_92, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_39|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 15:34:45,917 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L809-1-->L815: Formula: (and (= v_~main$tmp_guard0~0_6 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= 0 (mod v_~main$tmp_guard0~0_6 256)))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 15:34:45,917 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L815-2-->L815-5: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite24_Out703209588| |ULTIMATE.start_main_#t~ite25_Out703209588|)) (.cse1 (= 0 (mod ~x$r_buff1_thd0~0_In703209588 256))) (.cse2 (= 0 (mod ~x$w_buff1_used~0_In703209588 256)))) (or (and .cse0 (not .cse1) (not .cse2) (= |ULTIMATE.start_main_#t~ite24_Out703209588| ~x$w_buff1~0_In703209588)) (and .cse0 (or .cse1 .cse2) (= ~x~0_In703209588 |ULTIMATE.start_main_#t~ite24_Out703209588|)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In703209588, ~x$w_buff1_used~0=~x$w_buff1_used~0_In703209588, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In703209588, ~x~0=~x~0_In703209588} OutVars{~x$w_buff1~0=~x$w_buff1~0_In703209588, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out703209588|, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out703209588|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In703209588, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In703209588, ~x~0=~x~0_In703209588} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 15:34:45,917 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L816-->L816-2: Formula: (let ((.cse0 (= (mod ~x$r_buff0_thd0~0_In-1856517497 256) 0)) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In-1856517497 256)))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite26_Out-1856517497|)) (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In-1856517497 |ULTIMATE.start_main_#t~ite26_Out-1856517497|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1856517497, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1856517497} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1856517497, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-1856517497|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1856517497} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 15:34:45,918 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L817-->L817-2: Formula: (let ((.cse2 (= 0 (mod ~x$r_buff1_thd0~0_In-191140352 256))) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In-191140352 256))) (.cse1 (= (mod ~x$r_buff0_thd0~0_In-191140352 256) 0)) (.cse0 (= (mod ~x$w_buff0_used~0_In-191140352 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite27_Out-191140352| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (or .cse1 .cse0) (= ~x$w_buff1_used~0_In-191140352 |ULTIMATE.start_main_#t~ite27_Out-191140352|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-191140352, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-191140352, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-191140352, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-191140352} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-191140352, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-191140352, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-191140352|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-191140352, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-191140352} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 15:34:45,918 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L818-->L818-2: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In529469846 256) 0)) (.cse0 (= (mod ~x$r_buff0_thd0~0_In529469846 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite28_Out529469846|)) (and (= ~x$r_buff0_thd0~0_In529469846 |ULTIMATE.start_main_#t~ite28_Out529469846|) (or .cse1 .cse0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In529469846, ~x$w_buff0_used~0=~x$w_buff0_used~0_In529469846} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In529469846, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out529469846|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In529469846} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 15:34:45,918 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L819-->L819-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In1475788147 256))) (.cse0 (= (mod ~x$r_buff0_thd0~0_In1475788147 256) 0)) (.cse2 (= (mod ~x$r_buff1_thd0~0_In1475788147 256) 0)) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In1475788147 256)))) (or (and (or .cse0 .cse1) (= ~x$r_buff1_thd0~0_In1475788147 |ULTIMATE.start_main_#t~ite29_Out1475788147|) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite29_Out1475788147|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1475788147, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1475788147, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1475788147, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1475788147} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1475788147, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out1475788147|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1475788147, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1475788147, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1475788147} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 15:34:45,921 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L831-->L832: Formula: (and (= v_~x$r_buff0_thd0~0_112 v_~x$r_buff0_thd0~0_111) (not (= (mod v_~weak$$choice2~0_23 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_112, ~weak$$choice2~0=v_~weak$$choice2~0_23} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_111, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_6|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_10|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_6|, ~weak$$choice2~0=v_~weak$$choice2~0_23} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 15:34:45,921 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L834-->L837-1: Formula: (and (= (mod v_~main$tmp_guard1~0_13 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (not (= (mod v_~x$flush_delayed~0_23 256) 0)) (= v_~x$mem_tmp~0_13 v_~x~0_153) (= v_~x$flush_delayed~0_22 0)) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_23, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_13, ~x$mem_tmp~0=v_~x$mem_tmp~0_13} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_18|, ~x$flush_delayed~0=v_~x$flush_delayed~0_22, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_13, ~x$mem_tmp~0=v_~x$mem_tmp~0_13, ~x~0=v_~x~0_153, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ~x$flush_delayed~0, ~x~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 15:34:45,921 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L837-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 15:34:45,993 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_5bb58e17-e56b-4cc0-8c9a-c47783342971/bin/uautomizer/witness.graphml [2019-12-07 15:34:45,993 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 15:34:45,994 INFO L168 Benchmark]: Toolchain (without parser) took 161051.14 ms. Allocated memory was 1.0 GB in the beginning and 8.4 GB in the end (delta: 7.4 GB). Free memory was 943.5 MB in the beginning and 4.9 GB in the end (delta: -4.0 GB). Peak memory consumption was 3.4 GB. Max. memory is 11.5 GB. [2019-12-07 15:34:45,995 INFO L168 Benchmark]: CDTParser took 0.20 ms. Allocated memory is still 1.0 GB. Free memory is still 963.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 15:34:45,995 INFO L168 Benchmark]: CACSL2BoogieTranslator took 417.88 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 110.1 MB). Free memory was 943.5 MB in the beginning and 1.1 GB in the end (delta: -137.0 MB). Peak memory consumption was 18.1 MB. Max. memory is 11.5 GB. [2019-12-07 15:34:45,995 INFO L168 Benchmark]: Boogie Procedure Inliner took 42.13 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 15:34:45,996 INFO L168 Benchmark]: Boogie Preprocessor took 26.37 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 15:34:45,996 INFO L168 Benchmark]: RCFGBuilder took 411.67 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 49.8 MB). Peak memory consumption was 49.8 MB. Max. memory is 11.5 GB. [2019-12-07 15:34:45,996 INFO L168 Benchmark]: TraceAbstraction took 160061.70 ms. Allocated memory was 1.1 GB in the beginning and 8.4 GB in the end (delta: 7.3 GB). Free memory was 1.0 GB in the beginning and 5.0 GB in the end (delta: -4.0 GB). Peak memory consumption was 3.3 GB. Max. memory is 11.5 GB. [2019-12-07 15:34:45,997 INFO L168 Benchmark]: Witness Printer took 87.46 ms. Allocated memory is still 8.4 GB. Free memory was 5.0 GB in the beginning and 4.9 GB in the end (delta: 37.7 MB). Peak memory consumption was 37.7 MB. Max. memory is 11.5 GB. [2019-12-07 15:34:45,999 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20 ms. Allocated memory is still 1.0 GB. Free memory is still 963.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 417.88 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 110.1 MB). Free memory was 943.5 MB in the beginning and 1.1 GB in the end (delta: -137.0 MB). Peak memory consumption was 18.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 42.13 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.37 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 411.67 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 49.8 MB). Peak memory consumption was 49.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 160061.70 ms. Allocated memory was 1.1 GB in the beginning and 8.4 GB in the end (delta: 7.3 GB). Free memory was 1.0 GB in the beginning and 5.0 GB in the end (delta: -4.0 GB). Peak memory consumption was 3.3 GB. Max. memory is 11.5 GB. * Witness Printer took 87.46 ms. Allocated memory is still 8.4 GB. Free memory was 5.0 GB in the beginning and 4.9 GB in the end (delta: 37.7 MB). Peak memory consumption was 37.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.0s, 174 ProgramPointsBefore, 94 ProgramPointsAfterwards, 211 TransitionsBefore, 106 TransitionsAfterwards, 17074 CoEnabledTransitionPairs, 7 FixpointIterations, 31 TrivialSequentialCompositions, 43 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 37 ConcurrentYvCompositions, 29 ChoiceCompositions, 6159 VarBasedMoverChecksPositive, 253 VarBasedMoverChecksNegative, 78 SemBasedMoverChecksPositive, 250 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.8s, 0 MoverChecksTotal, 78277 CheckedPairsTotal, 111 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L805] FCALL, FORK 0 pthread_create(&t1888, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L807] FCALL, FORK 0 pthread_create(&t1889, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L809] FCALL, FORK 0 pthread_create(&t1890, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L752] 2 x$r_buff1_thd0 = x$r_buff0_thd0 [L753] 2 x$r_buff1_thd1 = x$r_buff0_thd1 [L754] 2 x$r_buff1_thd2 = x$r_buff0_thd2 [L755] 2 x$r_buff1_thd3 = x$r_buff0_thd3 [L756] 2 x$r_buff0_thd2 = (_Bool)1 [L759] 2 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L776] 3 __unbuffered_p2_EAX = y [L779] 3 __unbuffered_p2_EBX = y VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=1, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L727] 1 y = 2 [L730] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L782] 3 x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd3 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L733] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L783] 3 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$w_buff0_used [L733] 1 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L734] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L784] 3 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd3 || x$w_buff1_used && x$r_buff1_thd3 ? (_Bool)0 : x$w_buff1_used [L785] 3 x$r_buff0_thd3 = x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$r_buff0_thd3 [L762] EXPR 2 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L735] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L736] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L762] 2 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L763] 2 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L764] 2 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L815] EXPR 0 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L815] 0 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L816] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L817] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L818] 0 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L819] 0 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L822] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L823] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L824] 0 x$flush_delayed = weak$$choice2 [L825] 0 x$mem_tmp = x VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L826] EXPR 0 !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L826] 0 x = !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) [L827] EXPR 0 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L827] 0 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) [L828] EXPR 0 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L828] 0 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) [L829] EXPR 0 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L829] 0 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) [L830] EXPR 0 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L830] 0 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L832] EXPR 0 weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L832] 0 x$r_buff1_thd0 = weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L833] 0 main$tmp_guard1 = !(x == 2 && y == 2 && __unbuffered_p2_EAX == 1 && __unbuffered_p2_EBX == 1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 165 locations, 2 error locations. Result: UNSAFE, OverallTime: 159.8s, OverallIterations: 27, TraceHistogramMax: 1, AutomataDifference: 29.8s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 4791 SDtfs, 4150 SDslu, 9585 SDs, 0 SdLazy, 6093 SolverSat, 234 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 225 GetRequests, 53 SyntacticMatches, 24 SemanticMatches, 148 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 199 ImplicationChecksByTransitivity, 1.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=231837occurred in iteration=8, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 112.1s AutomataMinimizationTime, 26 MinimizatonAttempts, 680879 StatesRemovedByMinimization, 24 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.1s InterpolantComputationTime, 1173 NumberOfCodeBlocks, 1173 NumberOfCodeBlocksAsserted, 27 NumberOfCheckSat, 1079 ConstructedInterpolants, 0 QuantifiedInterpolants, 169709 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 26 InterpolantComputations, 26 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...