./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe008_power.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_57bfe568-ae69-47d7-84bc-665d4a4878cc/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_57bfe568-ae69-47d7-84bc-665d4a4878cc/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_57bfe568-ae69-47d7-84bc-665d4a4878cc/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_57bfe568-ae69-47d7-84bc-665d4a4878cc/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe008_power.oepc.i -s /tmp/vcloud-vcloud-master/worker/run_dir_57bfe568-ae69-47d7-84bc-665d4a4878cc/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_57bfe568-ae69-47d7-84bc-665d4a4878cc/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d04ba6e80c9f8fef6c7718b88aecbd0204c5adf9 .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 11:52:17,781 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 11:52:17,783 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 11:52:17,792 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 11:52:17,792 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 11:52:17,793 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 11:52:17,794 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 11:52:17,796 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 11:52:17,798 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 11:52:17,799 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 11:52:17,799 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 11:52:17,800 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 11:52:17,801 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 11:52:17,802 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 11:52:17,802 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 11:52:17,803 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 11:52:17,804 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 11:52:17,805 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 11:52:17,807 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 11:52:17,808 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 11:52:17,810 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 11:52:17,811 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 11:52:17,812 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 11:52:17,812 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 11:52:17,814 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 11:52:17,815 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 11:52:17,815 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 11:52:17,815 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 11:52:17,816 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 11:52:17,817 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 11:52:17,817 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 11:52:17,817 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 11:52:17,818 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 11:52:17,818 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 11:52:17,819 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 11:52:17,819 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 11:52:17,820 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 11:52:17,820 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 11:52:17,820 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 11:52:17,821 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 11:52:17,821 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 11:52:17,822 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_57bfe568-ae69-47d7-84bc-665d4a4878cc/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 11:52:17,834 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 11:52:17,834 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 11:52:17,835 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 11:52:17,835 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 11:52:17,835 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 11:52:17,835 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 11:52:17,835 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 11:52:17,835 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 11:52:17,836 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 11:52:17,836 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 11:52:17,836 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 11:52:17,836 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 11:52:17,836 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 11:52:17,836 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 11:52:17,837 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 11:52:17,837 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 11:52:17,837 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 11:52:17,837 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 11:52:17,837 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 11:52:17,837 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 11:52:17,837 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 11:52:17,838 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 11:52:17,838 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 11:52:17,838 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 11:52:17,838 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 11:52:17,838 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 11:52:17,838 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 11:52:17,838 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 11:52:17,838 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 11:52:17,838 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_57bfe568-ae69-47d7-84bc-665d4a4878cc/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d04ba6e80c9f8fef6c7718b88aecbd0204c5adf9 [2019-12-07 11:52:17,948 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 11:52:17,957 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 11:52:17,959 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 11:52:17,960 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 11:52:17,960 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 11:52:17,961 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_57bfe568-ae69-47d7-84bc-665d4a4878cc/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe008_power.oepc.i [2019-12-07 11:52:17,998 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_57bfe568-ae69-47d7-84bc-665d4a4878cc/bin/uautomizer/data/c0dc9169c/480c4caaafc74587b59b9987e8ba1e4c/FLAGb4c0aa753 [2019-12-07 11:52:18,435 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 11:52:18,435 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_57bfe568-ae69-47d7-84bc-665d4a4878cc/sv-benchmarks/c/pthread-wmm/safe008_power.oepc.i [2019-12-07 11:52:18,445 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_57bfe568-ae69-47d7-84bc-665d4a4878cc/bin/uautomizer/data/c0dc9169c/480c4caaafc74587b59b9987e8ba1e4c/FLAGb4c0aa753 [2019-12-07 11:52:18,453 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_57bfe568-ae69-47d7-84bc-665d4a4878cc/bin/uautomizer/data/c0dc9169c/480c4caaafc74587b59b9987e8ba1e4c [2019-12-07 11:52:18,455 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 11:52:18,456 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 11:52:18,457 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 11:52:18,457 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 11:52:18,459 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 11:52:18,460 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 11:52:18" (1/1) ... [2019-12-07 11:52:18,462 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4158e818 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:52:18, skipping insertion in model container [2019-12-07 11:52:18,462 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 11:52:18" (1/1) ... [2019-12-07 11:52:18,467 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 11:52:18,498 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 11:52:18,790 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 11:52:18,799 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 11:52:18,852 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 11:52:18,900 INFO L208 MainTranslator]: Completed translation [2019-12-07 11:52:18,900 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:52:18 WrapperNode [2019-12-07 11:52:18,900 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 11:52:18,901 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 11:52:18,901 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 11:52:18,901 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 11:52:18,907 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:52:18" (1/1) ... [2019-12-07 11:52:18,925 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:52:18" (1/1) ... [2019-12-07 11:52:18,953 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 11:52:18,953 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 11:52:18,953 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 11:52:18,953 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 11:52:18,960 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:52:18" (1/1) ... [2019-12-07 11:52:18,960 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:52:18" (1/1) ... [2019-12-07 11:52:18,964 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:52:18" (1/1) ... [2019-12-07 11:52:18,965 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:52:18" (1/1) ... [2019-12-07 11:52:18,974 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:52:18" (1/1) ... [2019-12-07 11:52:18,979 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:52:18" (1/1) ... [2019-12-07 11:52:18,982 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:52:18" (1/1) ... [2019-12-07 11:52:18,987 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 11:52:18,987 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 11:52:18,987 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 11:52:18,987 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 11:52:18,988 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:52:18" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_57bfe568-ae69-47d7-84bc-665d4a4878cc/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 11:52:19,032 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 11:52:19,032 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 11:52:19,032 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 11:52:19,032 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 11:52:19,032 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 11:52:19,032 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 11:52:19,032 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 11:52:19,032 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 11:52:19,033 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 11:52:19,033 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 11:52:19,033 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 11:52:19,033 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 11:52:19,033 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 11:52:19,034 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 11:52:19,399 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 11:52:19,399 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 11:52:19,400 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 11:52:19 BoogieIcfgContainer [2019-12-07 11:52:19,400 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 11:52:19,401 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 11:52:19,401 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 11:52:19,403 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 11:52:19,403 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 11:52:18" (1/3) ... [2019-12-07 11:52:19,403 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7d3eb9cf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 11:52:19, skipping insertion in model container [2019-12-07 11:52:19,404 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:52:18" (2/3) ... [2019-12-07 11:52:19,404 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7d3eb9cf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 11:52:19, skipping insertion in model container [2019-12-07 11:52:19,404 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 11:52:19" (3/3) ... [2019-12-07 11:52:19,405 INFO L109 eAbstractionObserver]: Analyzing ICFG safe008_power.oepc.i [2019-12-07 11:52:19,411 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 11:52:19,412 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 11:52:19,416 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 11:52:19,417 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 11:52:19,440 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,440 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,441 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,441 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,441 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,441 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,441 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,441 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,441 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,442 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,442 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,442 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,442 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,442 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,442 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,442 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,442 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,443 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,443 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,443 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,443 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,443 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,443 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,443 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,443 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,443 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,444 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,444 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,444 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,444 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,444 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,444 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,444 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,444 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,445 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,445 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,445 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,445 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,445 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,445 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,445 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,445 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,446 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,446 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,446 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,446 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,446 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,446 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,446 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,446 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,447 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,447 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,447 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,447 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,447 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,447 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,447 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,447 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,447 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,447 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,448 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,448 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,448 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,448 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,448 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,448 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,448 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,448 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,449 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,449 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,449 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,449 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,449 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,449 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,449 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,449 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,449 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,450 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,450 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,450 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,450 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,450 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,450 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,450 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,450 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,450 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,451 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,451 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,451 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,451 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,451 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,451 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,451 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,451 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:52:19,462 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 11:52:19,475 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 11:52:19,475 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 11:52:19,475 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 11:52:19,475 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 11:52:19,475 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 11:52:19,475 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 11:52:19,475 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 11:52:19,475 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 11:52:19,486 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 175 places, 212 transitions [2019-12-07 11:52:19,488 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 175 places, 212 transitions [2019-12-07 11:52:19,540 INFO L134 PetriNetUnfolder]: 47/209 cut-off events. [2019-12-07 11:52:19,540 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 11:52:19,552 INFO L76 FinitePrefix]: Finished finitePrefix Result has 219 conditions, 209 events. 47/209 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 585 event pairs. 9/169 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 11:52:19,567 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 175 places, 212 transitions [2019-12-07 11:52:19,596 INFO L134 PetriNetUnfolder]: 47/209 cut-off events. [2019-12-07 11:52:19,596 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 11:52:19,601 INFO L76 FinitePrefix]: Finished finitePrefix Result has 219 conditions, 209 events. 47/209 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 585 event pairs. 9/169 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 11:52:19,615 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 17114 [2019-12-07 11:52:19,616 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 11:52:22,357 WARN L192 SmtUtils]: Spent 147.00 ms on a formula simplification. DAG size of input: 89 DAG size of output: 87 [2019-12-07 11:52:22,449 INFO L206 etLargeBlockEncoding]: Checked pairs total: 80053 [2019-12-07 11:52:22,449 INFO L214 etLargeBlockEncoding]: Total number of compositions: 112 [2019-12-07 11:52:22,452 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 95 places, 106 transitions [2019-12-07 11:52:37,319 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 115670 states. [2019-12-07 11:52:37,320 INFO L276 IsEmpty]: Start isEmpty. Operand 115670 states. [2019-12-07 11:52:37,324 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-12-07 11:52:37,324 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:52:37,325 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-12-07 11:52:37,325 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:52:37,328 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:52:37,329 INFO L82 PathProgramCache]: Analyzing trace with hash 846448, now seen corresponding path program 1 times [2019-12-07 11:52:37,334 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:52:37,334 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227198532] [2019-12-07 11:52:37,334 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:52:37,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:52:37,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:52:37,476 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1227198532] [2019-12-07 11:52:37,477 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:52:37,477 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 11:52:37,477 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1498710810] [2019-12-07 11:52:37,480 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:52:37,480 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:52:37,489 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:52:37,490 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:52:37,491 INFO L87 Difference]: Start difference. First operand 115670 states. Second operand 3 states. [2019-12-07 11:52:38,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:52:38,296 INFO L93 Difference]: Finished difference Result 115182 states and 492924 transitions. [2019-12-07 11:52:38,296 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:52:38,297 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-12-07 11:52:38,298 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:52:38,784 INFO L225 Difference]: With dead ends: 115182 [2019-12-07 11:52:38,784 INFO L226 Difference]: Without dead ends: 112830 [2019-12-07 11:52:38,785 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:52:43,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112830 states. [2019-12-07 11:52:45,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112830 to 112830. [2019-12-07 11:52:45,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112830 states. [2019-12-07 11:52:45,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112830 states to 112830 states and 483320 transitions. [2019-12-07 11:52:45,474 INFO L78 Accepts]: Start accepts. Automaton has 112830 states and 483320 transitions. Word has length 3 [2019-12-07 11:52:45,475 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:52:45,475 INFO L462 AbstractCegarLoop]: Abstraction has 112830 states and 483320 transitions. [2019-12-07 11:52:45,475 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:52:45,475 INFO L276 IsEmpty]: Start isEmpty. Operand 112830 states and 483320 transitions. [2019-12-07 11:52:45,478 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 11:52:45,478 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:52:45,479 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:52:45,479 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:52:45,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:52:45,479 INFO L82 PathProgramCache]: Analyzing trace with hash -939919620, now seen corresponding path program 1 times [2019-12-07 11:52:45,479 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:52:45,479 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2145280808] [2019-12-07 11:52:45,479 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:52:45,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:52:45,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:52:45,539 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2145280808] [2019-12-07 11:52:45,539 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:52:45,539 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:52:45,539 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [27585737] [2019-12-07 11:52:45,540 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 11:52:45,540 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:52:45,540 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 11:52:45,541 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 11:52:45,541 INFO L87 Difference]: Start difference. First operand 112830 states and 483320 transitions. Second operand 4 states. [2019-12-07 11:52:46,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:52:46,489 INFO L93 Difference]: Finished difference Result 176302 states and 727515 transitions. [2019-12-07 11:52:46,489 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 11:52:46,489 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 11:52:46,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:52:47,314 INFO L225 Difference]: With dead ends: 176302 [2019-12-07 11:52:47,314 INFO L226 Difference]: Without dead ends: 176253 [2019-12-07 11:52:47,315 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:52:53,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176253 states. [2019-12-07 11:52:55,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176253 to 159436. [2019-12-07 11:52:55,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159436 states. [2019-12-07 11:52:55,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159436 states to 159436 states and 665691 transitions. [2019-12-07 11:52:55,892 INFO L78 Accepts]: Start accepts. Automaton has 159436 states and 665691 transitions. Word has length 11 [2019-12-07 11:52:55,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:52:55,892 INFO L462 AbstractCegarLoop]: Abstraction has 159436 states and 665691 transitions. [2019-12-07 11:52:55,892 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 11:52:55,893 INFO L276 IsEmpty]: Start isEmpty. Operand 159436 states and 665691 transitions. [2019-12-07 11:52:55,897 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 11:52:55,897 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:52:55,897 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:52:55,897 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:52:55,897 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:52:55,897 INFO L82 PathProgramCache]: Analyzing trace with hash 670018080, now seen corresponding path program 1 times [2019-12-07 11:52:55,897 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:52:55,897 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1961798754] [2019-12-07 11:52:55,898 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:52:55,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:52:55,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:52:55,941 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1961798754] [2019-12-07 11:52:55,941 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:52:55,942 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:52:55,942 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1841577849] [2019-12-07 11:52:55,942 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 11:52:55,942 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:52:55,942 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 11:52:55,942 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 11:52:55,942 INFO L87 Difference]: Start difference. First operand 159436 states and 665691 transitions. Second operand 4 states. [2019-12-07 11:52:57,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:52:57,541 INFO L93 Difference]: Finished difference Result 228428 states and 932375 transitions. [2019-12-07 11:52:57,541 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 11:52:57,542 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 11:52:57,542 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:52:58,104 INFO L225 Difference]: With dead ends: 228428 [2019-12-07 11:52:58,104 INFO L226 Difference]: Without dead ends: 228365 [2019-12-07 11:52:58,104 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:53:05,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228365 states. [2019-12-07 11:53:07,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228365 to 192396. [2019-12-07 11:53:07,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192396 states. [2019-12-07 11:53:08,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192396 states to 192396 states and 797806 transitions. [2019-12-07 11:53:08,291 INFO L78 Accepts]: Start accepts. Automaton has 192396 states and 797806 transitions. Word has length 13 [2019-12-07 11:53:08,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:53:08,292 INFO L462 AbstractCegarLoop]: Abstraction has 192396 states and 797806 transitions. [2019-12-07 11:53:08,292 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 11:53:08,292 INFO L276 IsEmpty]: Start isEmpty. Operand 192396 states and 797806 transitions. [2019-12-07 11:53:08,294 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 11:53:08,294 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:53:08,295 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:53:08,295 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:53:08,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:53:08,295 INFO L82 PathProgramCache]: Analyzing trace with hash -293312110, now seen corresponding path program 1 times [2019-12-07 11:53:08,295 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:53:08,295 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1870742727] [2019-12-07 11:53:08,295 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:53:08,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:53:08,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:53:08,335 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1870742727] [2019-12-07 11:53:08,335 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:53:08,335 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:53:08,335 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [308994217] [2019-12-07 11:53:08,335 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 11:53:08,335 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:53:08,335 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 11:53:08,336 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 11:53:08,336 INFO L87 Difference]: Start difference. First operand 192396 states and 797806 transitions. Second operand 4 states. [2019-12-07 11:53:09,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:53:09,976 INFO L93 Difference]: Finished difference Result 240534 states and 988069 transitions. [2019-12-07 11:53:09,976 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 11:53:09,976 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 11:53:09,977 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:53:10,584 INFO L225 Difference]: With dead ends: 240534 [2019-12-07 11:53:10,584 INFO L226 Difference]: Without dead ends: 240534 [2019-12-07 11:53:10,585 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:53:15,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 240534 states. [2019-12-07 11:53:18,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 240534 to 203638. [2019-12-07 11:53:18,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203638 states. [2019-12-07 11:53:19,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203638 states to 203638 states and 844577 transitions. [2019-12-07 11:53:19,557 INFO L78 Accepts]: Start accepts. Automaton has 203638 states and 844577 transitions. Word has length 13 [2019-12-07 11:53:19,557 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:53:19,557 INFO L462 AbstractCegarLoop]: Abstraction has 203638 states and 844577 transitions. [2019-12-07 11:53:19,557 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 11:53:19,557 INFO L276 IsEmpty]: Start isEmpty. Operand 203638 states and 844577 transitions. [2019-12-07 11:53:19,577 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 11:53:19,577 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:53:19,577 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:53:19,577 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:53:19,578 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:53:19,578 INFO L82 PathProgramCache]: Analyzing trace with hash 1303088540, now seen corresponding path program 1 times [2019-12-07 11:53:19,578 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:53:19,578 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [265444149] [2019-12-07 11:53:19,578 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:53:19,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:53:19,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:53:19,626 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [265444149] [2019-12-07 11:53:19,626 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:53:19,626 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:53:19,626 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1935870229] [2019-12-07 11:53:19,627 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:53:19,627 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:53:19,627 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:53:19,627 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:53:19,627 INFO L87 Difference]: Start difference. First operand 203638 states and 844577 transitions. Second operand 5 states. [2019-12-07 11:53:21,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:53:21,178 INFO L93 Difference]: Finished difference Result 300567 states and 1220027 transitions. [2019-12-07 11:53:21,179 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 11:53:21,179 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 11:53:21,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:53:24,931 INFO L225 Difference]: With dead ends: 300567 [2019-12-07 11:53:24,932 INFO L226 Difference]: Without dead ends: 300504 [2019-12-07 11:53:24,932 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 11:53:30,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 300504 states. [2019-12-07 11:53:33,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 300504 to 216214. [2019-12-07 11:53:33,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 216214 states. [2019-12-07 11:53:34,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 216214 states to 216214 states and 891891 transitions. [2019-12-07 11:53:34,658 INFO L78 Accepts]: Start accepts. Automaton has 216214 states and 891891 transitions. Word has length 19 [2019-12-07 11:53:34,659 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:53:34,659 INFO L462 AbstractCegarLoop]: Abstraction has 216214 states and 891891 transitions. [2019-12-07 11:53:34,659 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:53:34,659 INFO L276 IsEmpty]: Start isEmpty. Operand 216214 states and 891891 transitions. [2019-12-07 11:53:34,673 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 11:53:34,673 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:53:34,673 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:53:34,673 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:53:34,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:53:34,674 INFO L82 PathProgramCache]: Analyzing trace with hash -2105368373, now seen corresponding path program 1 times [2019-12-07 11:53:34,674 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:53:34,674 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [418362251] [2019-12-07 11:53:34,674 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:53:34,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:53:34,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:53:34,734 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [418362251] [2019-12-07 11:53:34,735 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:53:34,735 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:53:34,735 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [366925524] [2019-12-07 11:53:34,735 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:53:34,736 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:53:34,736 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:53:34,736 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:53:34,736 INFO L87 Difference]: Start difference. First operand 216214 states and 891891 transitions. Second operand 5 states. [2019-12-07 11:53:36,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:53:36,459 INFO L93 Difference]: Finished difference Result 326371 states and 1320375 transitions. [2019-12-07 11:53:36,460 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 11:53:36,460 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 11:53:36,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:53:37,823 INFO L225 Difference]: With dead ends: 326371 [2019-12-07 11:53:37,824 INFO L226 Difference]: Without dead ends: 326224 [2019-12-07 11:53:37,824 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 11:53:43,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 326224 states. [2019-12-07 11:53:48,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 326224 to 227768. [2019-12-07 11:53:48,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 227768 states. [2019-12-07 11:53:48,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227768 states to 227768 states and 938858 transitions. [2019-12-07 11:53:48,729 INFO L78 Accepts]: Start accepts. Automaton has 227768 states and 938858 transitions. Word has length 19 [2019-12-07 11:53:48,729 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:53:48,729 INFO L462 AbstractCegarLoop]: Abstraction has 227768 states and 938858 transitions. [2019-12-07 11:53:48,729 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:53:48,729 INFO L276 IsEmpty]: Start isEmpty. Operand 227768 states and 938858 transitions. [2019-12-07 11:53:48,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 11:53:48,743 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:53:48,743 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:53:48,743 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:53:48,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:53:48,743 INFO L82 PathProgramCache]: Analyzing trace with hash 550593021, now seen corresponding path program 1 times [2019-12-07 11:53:48,743 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:53:48,744 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [385613364] [2019-12-07 11:53:48,744 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:53:48,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:53:48,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:53:48,788 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [385613364] [2019-12-07 11:53:48,789 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:53:48,789 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:53:48,789 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [500590605] [2019-12-07 11:53:48,789 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:53:48,789 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:53:48,789 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:53:48,789 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:53:48,789 INFO L87 Difference]: Start difference. First operand 227768 states and 938858 transitions. Second operand 5 states. [2019-12-07 11:53:52,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:53:52,374 INFO L93 Difference]: Finished difference Result 330156 states and 1338658 transitions. [2019-12-07 11:53:52,375 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 11:53:52,375 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 11:53:52,375 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:53:53,212 INFO L225 Difference]: With dead ends: 330156 [2019-12-07 11:53:53,213 INFO L226 Difference]: Without dead ends: 330093 [2019-12-07 11:53:53,213 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 11:53:59,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 330093 states. [2019-12-07 11:54:03,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 330093 to 245714. [2019-12-07 11:54:03,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 245714 states. [2019-12-07 11:54:03,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245714 states to 245714 states and 1011495 transitions. [2019-12-07 11:54:03,978 INFO L78 Accepts]: Start accepts. Automaton has 245714 states and 1011495 transitions. Word has length 19 [2019-12-07 11:54:03,979 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:03,979 INFO L462 AbstractCegarLoop]: Abstraction has 245714 states and 1011495 transitions. [2019-12-07 11:54:03,979 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:54:03,979 INFO L276 IsEmpty]: Start isEmpty. Operand 245714 states and 1011495 transitions. [2019-12-07 11:54:04,039 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 11:54:04,039 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:04,039 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:04,040 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:04,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:04,040 INFO L82 PathProgramCache]: Analyzing trace with hash 956366417, now seen corresponding path program 1 times [2019-12-07 11:54:04,040 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:04,040 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1888769237] [2019-12-07 11:54:04,040 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:04,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:04,068 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:04,068 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1888769237] [2019-12-07 11:54:04,068 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:04,069 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:54:04,069 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1161788920] [2019-12-07 11:54:04,069 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:54:04,069 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:04,069 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:54:04,070 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:54:04,070 INFO L87 Difference]: Start difference. First operand 245714 states and 1011495 transitions. Second operand 3 states. [2019-12-07 11:54:04,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:04,199 INFO L93 Difference]: Finished difference Result 45181 states and 145439 transitions. [2019-12-07 11:54:04,200 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:54:04,200 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-12-07 11:54:04,200 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:04,262 INFO L225 Difference]: With dead ends: 45181 [2019-12-07 11:54:04,262 INFO L226 Difference]: Without dead ends: 45181 [2019-12-07 11:54:04,262 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:54:04,449 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45181 states. [2019-12-07 11:54:05,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45181 to 45181. [2019-12-07 11:54:05,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45181 states. [2019-12-07 11:54:05,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45181 states to 45181 states and 145439 transitions. [2019-12-07 11:54:05,273 INFO L78 Accepts]: Start accepts. Automaton has 45181 states and 145439 transitions. Word has length 25 [2019-12-07 11:54:05,273 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:05,273 INFO L462 AbstractCegarLoop]: Abstraction has 45181 states and 145439 transitions. [2019-12-07 11:54:05,273 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:54:05,273 INFO L276 IsEmpty]: Start isEmpty. Operand 45181 states and 145439 transitions. [2019-12-07 11:54:05,286 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 11:54:05,287 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:05,287 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:05,287 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:05,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:05,287 INFO L82 PathProgramCache]: Analyzing trace with hash 1277795975, now seen corresponding path program 1 times [2019-12-07 11:54:05,287 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:05,287 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53777351] [2019-12-07 11:54:05,287 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:05,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:05,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:05,320 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [53777351] [2019-12-07 11:54:05,321 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:05,321 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:54:05,321 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2048166283] [2019-12-07 11:54:05,321 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 11:54:05,321 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:05,322 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 11:54:05,322 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 11:54:05,322 INFO L87 Difference]: Start difference. First operand 45181 states and 145439 transitions. Second operand 4 states. [2019-12-07 11:54:05,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:05,350 INFO L93 Difference]: Finished difference Result 9017 states and 24304 transitions. [2019-12-07 11:54:05,350 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 11:54:05,350 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 31 [2019-12-07 11:54:05,350 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:05,358 INFO L225 Difference]: With dead ends: 9017 [2019-12-07 11:54:05,358 INFO L226 Difference]: Without dead ends: 9017 [2019-12-07 11:54:05,358 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 11:54:05,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9017 states. [2019-12-07 11:54:05,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9017 to 8849. [2019-12-07 11:54:05,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8849 states. [2019-12-07 11:54:05,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8849 states to 8849 states and 23824 transitions. [2019-12-07 11:54:05,454 INFO L78 Accepts]: Start accepts. Automaton has 8849 states and 23824 transitions. Word has length 31 [2019-12-07 11:54:05,455 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:05,455 INFO L462 AbstractCegarLoop]: Abstraction has 8849 states and 23824 transitions. [2019-12-07 11:54:05,455 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 11:54:05,455 INFO L276 IsEmpty]: Start isEmpty. Operand 8849 states and 23824 transitions. [2019-12-07 11:54:05,460 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 11:54:05,460 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:05,460 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:05,460 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:05,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:05,461 INFO L82 PathProgramCache]: Analyzing trace with hash -1041968244, now seen corresponding path program 1 times [2019-12-07 11:54:05,461 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:05,461 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [680301553] [2019-12-07 11:54:05,461 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:05,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:05,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:05,511 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [680301553] [2019-12-07 11:54:05,511 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:05,511 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 11:54:05,511 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [974884064] [2019-12-07 11:54:05,512 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 11:54:05,512 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:05,512 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 11:54:05,512 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 11:54:05,512 INFO L87 Difference]: Start difference. First operand 8849 states and 23824 transitions. Second operand 6 states. [2019-12-07 11:54:05,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:05,931 INFO L93 Difference]: Finished difference Result 9814 states and 25974 transitions. [2019-12-07 11:54:05,932 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 11:54:05,932 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 37 [2019-12-07 11:54:05,932 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:05,940 INFO L225 Difference]: With dead ends: 9814 [2019-12-07 11:54:05,940 INFO L226 Difference]: Without dead ends: 9814 [2019-12-07 11:54:05,940 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=47, Invalid=109, Unknown=0, NotChecked=0, Total=156 [2019-12-07 11:54:05,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9814 states. [2019-12-07 11:54:06,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9814 to 7837. [2019-12-07 11:54:06,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7837 states. [2019-12-07 11:54:06,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7837 states to 7837 states and 21112 transitions. [2019-12-07 11:54:06,034 INFO L78 Accepts]: Start accepts. Automaton has 7837 states and 21112 transitions. Word has length 37 [2019-12-07 11:54:06,034 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:06,034 INFO L462 AbstractCegarLoop]: Abstraction has 7837 states and 21112 transitions. [2019-12-07 11:54:06,034 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 11:54:06,034 INFO L276 IsEmpty]: Start isEmpty. Operand 7837 states and 21112 transitions. [2019-12-07 11:54:06,039 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 11:54:06,039 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:06,040 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:06,040 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:06,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:06,040 INFO L82 PathProgramCache]: Analyzing trace with hash -118101162, now seen corresponding path program 1 times [2019-12-07 11:54:06,040 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:06,040 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1116611736] [2019-12-07 11:54:06,041 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:06,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:06,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:06,093 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1116611736] [2019-12-07 11:54:06,093 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:06,093 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 11:54:06,093 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2095246200] [2019-12-07 11:54:06,094 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:54:06,094 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:06,094 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:54:06,094 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:54:06,094 INFO L87 Difference]: Start difference. First operand 7837 states and 21112 transitions. Second operand 5 states. [2019-12-07 11:54:06,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:06,118 INFO L93 Difference]: Finished difference Result 5331 states and 15289 transitions. [2019-12-07 11:54:06,118 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 11:54:06,118 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-12-07 11:54:06,119 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:06,123 INFO L225 Difference]: With dead ends: 5331 [2019-12-07 11:54:06,123 INFO L226 Difference]: Without dead ends: 5331 [2019-12-07 11:54:06,123 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:54:06,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5331 states. [2019-12-07 11:54:06,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5331 to 4967. [2019-12-07 11:54:06,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4967 states. [2019-12-07 11:54:06,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4967 states to 4967 states and 14305 transitions. [2019-12-07 11:54:06,183 INFO L78 Accepts]: Start accepts. Automaton has 4967 states and 14305 transitions. Word has length 51 [2019-12-07 11:54:06,183 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:06,183 INFO L462 AbstractCegarLoop]: Abstraction has 4967 states and 14305 transitions. [2019-12-07 11:54:06,183 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:54:06,183 INFO L276 IsEmpty]: Start isEmpty. Operand 4967 states and 14305 transitions. [2019-12-07 11:54:06,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 11:54:06,186 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:06,187 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:06,187 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:06,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:06,187 INFO L82 PathProgramCache]: Analyzing trace with hash -1019045356, now seen corresponding path program 1 times [2019-12-07 11:54:06,187 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:06,187 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [521169829] [2019-12-07 11:54:06,187 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:06,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:06,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:06,244 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [521169829] [2019-12-07 11:54:06,244 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:06,244 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 11:54:06,244 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1632601202] [2019-12-07 11:54:06,244 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:54:06,245 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:06,245 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:54:06,245 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:54:06,245 INFO L87 Difference]: Start difference. First operand 4967 states and 14305 transitions. Second operand 5 states. [2019-12-07 11:54:06,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:06,425 INFO L93 Difference]: Finished difference Result 7558 states and 21570 transitions. [2019-12-07 11:54:06,426 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 11:54:06,426 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 65 [2019-12-07 11:54:06,426 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:06,432 INFO L225 Difference]: With dead ends: 7558 [2019-12-07 11:54:06,433 INFO L226 Difference]: Without dead ends: 7558 [2019-12-07 11:54:06,433 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 11:54:06,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7558 states. [2019-12-07 11:54:06,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7558 to 6659. [2019-12-07 11:54:06,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6659 states. [2019-12-07 11:54:06,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6659 states to 6659 states and 19091 transitions. [2019-12-07 11:54:06,515 INFO L78 Accepts]: Start accepts. Automaton has 6659 states and 19091 transitions. Word has length 65 [2019-12-07 11:54:06,515 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:06,515 INFO L462 AbstractCegarLoop]: Abstraction has 6659 states and 19091 transitions. [2019-12-07 11:54:06,515 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:54:06,516 INFO L276 IsEmpty]: Start isEmpty. Operand 6659 states and 19091 transitions. [2019-12-07 11:54:06,520 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 11:54:06,520 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:06,521 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:06,521 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:06,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:06,521 INFO L82 PathProgramCache]: Analyzing trace with hash -613444874, now seen corresponding path program 2 times [2019-12-07 11:54:06,521 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:06,521 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [625214148] [2019-12-07 11:54:06,521 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:06,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:06,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:06,581 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [625214148] [2019-12-07 11:54:06,581 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:06,582 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:54:06,582 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414935895] [2019-12-07 11:54:06,582 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:54:06,582 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:06,582 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:54:06,582 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:54:06,582 INFO L87 Difference]: Start difference. First operand 6659 states and 19091 transitions. Second operand 3 states. [2019-12-07 11:54:06,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:06,603 INFO L93 Difference]: Finished difference Result 6289 states and 17750 transitions. [2019-12-07 11:54:06,604 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:54:06,604 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 11:54:06,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:06,609 INFO L225 Difference]: With dead ends: 6289 [2019-12-07 11:54:06,609 INFO L226 Difference]: Without dead ends: 6289 [2019-12-07 11:54:06,609 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:54:06,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6289 states. [2019-12-07 11:54:06,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6289 to 6133. [2019-12-07 11:54:06,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6133 states. [2019-12-07 11:54:06,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6133 states to 6133 states and 17320 transitions. [2019-12-07 11:54:06,680 INFO L78 Accepts]: Start accepts. Automaton has 6133 states and 17320 transitions. Word has length 65 [2019-12-07 11:54:06,680 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:06,680 INFO L462 AbstractCegarLoop]: Abstraction has 6133 states and 17320 transitions. [2019-12-07 11:54:06,680 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:54:06,680 INFO L276 IsEmpty]: Start isEmpty. Operand 6133 states and 17320 transitions. [2019-12-07 11:54:06,685 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 11:54:06,685 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:06,685 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:06,685 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:06,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:06,685 INFO L82 PathProgramCache]: Analyzing trace with hash 223341978, now seen corresponding path program 1 times [2019-12-07 11:54:06,685 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:06,686 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807607495] [2019-12-07 11:54:06,686 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:06,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:06,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:06,739 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1807607495] [2019-12-07 11:54:06,739 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:06,739 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 11:54:06,739 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1550312618] [2019-12-07 11:54:06,739 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:54:06,739 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:06,739 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:54:06,740 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:54:06,740 INFO L87 Difference]: Start difference. First operand 6133 states and 17320 transitions. Second operand 5 states. [2019-12-07 11:54:06,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:06,931 INFO L93 Difference]: Finished difference Result 8712 states and 24399 transitions. [2019-12-07 11:54:06,932 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 11:54:06,932 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 66 [2019-12-07 11:54:06,932 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:06,939 INFO L225 Difference]: With dead ends: 8712 [2019-12-07 11:54:06,939 INFO L226 Difference]: Without dead ends: 8712 [2019-12-07 11:54:06,939 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 11:54:06,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8712 states. [2019-12-07 11:54:07,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8712 to 6784. [2019-12-07 11:54:07,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6784 states. [2019-12-07 11:54:07,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6784 states to 6784 states and 19209 transitions. [2019-12-07 11:54:07,024 INFO L78 Accepts]: Start accepts. Automaton has 6784 states and 19209 transitions. Word has length 66 [2019-12-07 11:54:07,024 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:07,024 INFO L462 AbstractCegarLoop]: Abstraction has 6784 states and 19209 transitions. [2019-12-07 11:54:07,024 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:54:07,024 INFO L276 IsEmpty]: Start isEmpty. Operand 6784 states and 19209 transitions. [2019-12-07 11:54:07,029 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 11:54:07,029 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:07,029 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:07,029 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:07,029 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:07,030 INFO L82 PathProgramCache]: Analyzing trace with hash -446701502, now seen corresponding path program 2 times [2019-12-07 11:54:07,030 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:07,030 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963168945] [2019-12-07 11:54:07,030 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:07,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:07,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:07,130 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1963168945] [2019-12-07 11:54:07,130 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:07,130 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 11:54:07,130 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1910583172] [2019-12-07 11:54:07,131 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 11:54:07,131 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:07,131 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 11:54:07,131 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-12-07 11:54:07,131 INFO L87 Difference]: Start difference. First operand 6784 states and 19209 transitions. Second operand 8 states. [2019-12-07 11:54:07,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:07,753 INFO L93 Difference]: Finished difference Result 9669 states and 27034 transitions. [2019-12-07 11:54:07,753 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 11:54:07,753 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 66 [2019-12-07 11:54:07,753 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:07,761 INFO L225 Difference]: With dead ends: 9669 [2019-12-07 11:54:07,761 INFO L226 Difference]: Without dead ends: 9669 [2019-12-07 11:54:07,761 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 7 SyntacticMatches, 3 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 102 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=110, Invalid=396, Unknown=0, NotChecked=0, Total=506 [2019-12-07 11:54:07,786 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9669 states. [2019-12-07 11:54:07,849 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9669 to 7660. [2019-12-07 11:54:07,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7660 states. [2019-12-07 11:54:07,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7660 states to 7660 states and 21627 transitions. [2019-12-07 11:54:07,859 INFO L78 Accepts]: Start accepts. Automaton has 7660 states and 21627 transitions. Word has length 66 [2019-12-07 11:54:07,859 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:07,859 INFO L462 AbstractCegarLoop]: Abstraction has 7660 states and 21627 transitions. [2019-12-07 11:54:07,859 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 11:54:07,859 INFO L276 IsEmpty]: Start isEmpty. Operand 7660 states and 21627 transitions. [2019-12-07 11:54:07,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 11:54:07,865 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:07,865 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:07,865 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:07,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:07,865 INFO L82 PathProgramCache]: Analyzing trace with hash -1773910720, now seen corresponding path program 3 times [2019-12-07 11:54:07,865 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:07,866 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1831179235] [2019-12-07 11:54:07,866 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:07,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:07,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:07,927 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1831179235] [2019-12-07 11:54:07,927 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:07,928 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 11:54:07,928 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1255888206] [2019-12-07 11:54:07,928 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 11:54:07,928 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:07,928 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 11:54:07,928 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 11:54:07,929 INFO L87 Difference]: Start difference. First operand 7660 states and 21627 transitions. Second operand 7 states. [2019-12-07 11:54:08,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:08,777 INFO L93 Difference]: Finished difference Result 11165 states and 31397 transitions. [2019-12-07 11:54:08,778 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 11:54:08,779 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 66 [2019-12-07 11:54:08,779 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:08,800 INFO L225 Difference]: With dead ends: 11165 [2019-12-07 11:54:08,800 INFO L226 Difference]: Without dead ends: 11165 [2019-12-07 11:54:08,801 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 11 SyntacticMatches, 2 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=72, Invalid=200, Unknown=0, NotChecked=0, Total=272 [2019-12-07 11:54:08,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11165 states. [2019-12-07 11:54:08,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11165 to 7854. [2019-12-07 11:54:08,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7854 states. [2019-12-07 11:54:08,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7854 states to 7854 states and 22182 transitions. [2019-12-07 11:54:08,917 INFO L78 Accepts]: Start accepts. Automaton has 7854 states and 22182 transitions. Word has length 66 [2019-12-07 11:54:08,917 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:08,917 INFO L462 AbstractCegarLoop]: Abstraction has 7854 states and 22182 transitions. [2019-12-07 11:54:08,917 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 11:54:08,917 INFO L276 IsEmpty]: Start isEmpty. Operand 7854 states and 22182 transitions. [2019-12-07 11:54:08,924 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 11:54:08,924 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:08,924 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:08,924 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:08,925 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:08,925 INFO L82 PathProgramCache]: Analyzing trace with hash -1320128202, now seen corresponding path program 4 times [2019-12-07 11:54:08,925 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:08,925 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [38771465] [2019-12-07 11:54:08,925 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:08,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:08,964 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:08,964 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [38771465] [2019-12-07 11:54:08,964 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:08,964 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:54:08,965 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [52471830] [2019-12-07 11:54:08,965 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:54:08,965 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:08,965 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:54:08,965 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:54:08,965 INFO L87 Difference]: Start difference. First operand 7854 states and 22182 transitions. Second operand 3 states. [2019-12-07 11:54:09,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:09,006 INFO L93 Difference]: Finished difference Result 7853 states and 22180 transitions. [2019-12-07 11:54:09,006 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:54:09,006 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 11:54:09,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:09,013 INFO L225 Difference]: With dead ends: 7853 [2019-12-07 11:54:09,013 INFO L226 Difference]: Without dead ends: 7853 [2019-12-07 11:54:09,013 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:54:09,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7853 states. [2019-12-07 11:54:09,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7853 to 5420. [2019-12-07 11:54:09,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5420 states. [2019-12-07 11:54:09,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5420 states to 5420 states and 15417 transitions. [2019-12-07 11:54:09,088 INFO L78 Accepts]: Start accepts. Automaton has 5420 states and 15417 transitions. Word has length 66 [2019-12-07 11:54:09,088 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:09,088 INFO L462 AbstractCegarLoop]: Abstraction has 5420 states and 15417 transitions. [2019-12-07 11:54:09,088 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:54:09,089 INFO L276 IsEmpty]: Start isEmpty. Operand 5420 states and 15417 transitions. [2019-12-07 11:54:09,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 11:54:09,092 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:09,093 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:09,093 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:09,093 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:09,093 INFO L82 PathProgramCache]: Analyzing trace with hash -361266720, now seen corresponding path program 1 times [2019-12-07 11:54:09,093 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:09,093 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1473585086] [2019-12-07 11:54:09,093 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:09,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:09,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:09,263 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1473585086] [2019-12-07 11:54:09,263 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:09,263 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 11:54:09,264 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [803271347] [2019-12-07 11:54:09,264 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 11:54:09,264 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:09,264 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 11:54:09,264 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2019-12-07 11:54:09,264 INFO L87 Difference]: Start difference. First operand 5420 states and 15417 transitions. Second operand 13 states. [2019-12-07 11:54:09,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:09,756 INFO L93 Difference]: Finished difference Result 12265 states and 34865 transitions. [2019-12-07 11:54:09,756 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 11:54:09,757 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 67 [2019-12-07 11:54:09,757 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:09,762 INFO L225 Difference]: With dead ends: 12265 [2019-12-07 11:54:09,762 INFO L226 Difference]: Without dead ends: 6299 [2019-12-07 11:54:09,762 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 87 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=145, Invalid=455, Unknown=0, NotChecked=0, Total=600 [2019-12-07 11:54:09,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6299 states. [2019-12-07 11:54:09,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6299 to 5129. [2019-12-07 11:54:09,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5129 states. [2019-12-07 11:54:09,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5129 states to 5129 states and 14540 transitions. [2019-12-07 11:54:09,824 INFO L78 Accepts]: Start accepts. Automaton has 5129 states and 14540 transitions. Word has length 67 [2019-12-07 11:54:09,824 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:09,824 INFO L462 AbstractCegarLoop]: Abstraction has 5129 states and 14540 transitions. [2019-12-07 11:54:09,824 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 11:54:09,824 INFO L276 IsEmpty]: Start isEmpty. Operand 5129 states and 14540 transitions. [2019-12-07 11:54:09,827 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 11:54:09,827 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:09,827 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:09,827 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:09,827 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:09,827 INFO L82 PathProgramCache]: Analyzing trace with hash 1374418208, now seen corresponding path program 2 times [2019-12-07 11:54:09,828 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:09,828 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2060249380] [2019-12-07 11:54:09,828 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:09,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:09,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:09,871 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2060249380] [2019-12-07 11:54:09,871 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:09,871 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:54:09,871 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [936533651] [2019-12-07 11:54:09,872 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:54:09,872 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:09,872 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:54:09,872 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:54:09,872 INFO L87 Difference]: Start difference. First operand 5129 states and 14540 transitions. Second operand 3 states. [2019-12-07 11:54:09,889 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:09,889 INFO L93 Difference]: Finished difference Result 4739 states and 13191 transitions. [2019-12-07 11:54:09,889 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:54:09,889 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 11:54:09,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:09,893 INFO L225 Difference]: With dead ends: 4739 [2019-12-07 11:54:09,893 INFO L226 Difference]: Without dead ends: 4739 [2019-12-07 11:54:09,893 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:54:09,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4739 states. [2019-12-07 11:54:09,948 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4739 to 4174. [2019-12-07 11:54:09,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4174 states. [2019-12-07 11:54:09,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4174 states to 4174 states and 11624 transitions. [2019-12-07 11:54:09,953 INFO L78 Accepts]: Start accepts. Automaton has 4174 states and 11624 transitions. Word has length 67 [2019-12-07 11:54:09,953 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:09,953 INFO L462 AbstractCegarLoop]: Abstraction has 4174 states and 11624 transitions. [2019-12-07 11:54:09,953 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:54:09,953 INFO L276 IsEmpty]: Start isEmpty. Operand 4174 states and 11624 transitions. [2019-12-07 11:54:09,955 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:54:09,955 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:09,955 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:09,955 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:09,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:09,956 INFO L82 PathProgramCache]: Analyzing trace with hash -1090372922, now seen corresponding path program 1 times [2019-12-07 11:54:09,956 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:09,956 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514033598] [2019-12-07 11:54:09,956 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:09,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:10,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:10,317 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514033598] [2019-12-07 11:54:10,317 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:10,317 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2019-12-07 11:54:10,317 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [126898776] [2019-12-07 11:54:10,318 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 11:54:10,318 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:10,318 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 11:54:10,318 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=293, Unknown=0, NotChecked=0, Total=342 [2019-12-07 11:54:10,318 INFO L87 Difference]: Start difference. First operand 4174 states and 11624 transitions. Second operand 19 states. [2019-12-07 11:54:12,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:12,671 INFO L93 Difference]: Finished difference Result 13607 states and 37459 transitions. [2019-12-07 11:54:12,672 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2019-12-07 11:54:12,672 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 68 [2019-12-07 11:54:12,672 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:12,682 INFO L225 Difference]: With dead ends: 13607 [2019-12-07 11:54:12,682 INFO L226 Difference]: Without dead ends: 12788 [2019-12-07 11:54:12,683 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 868 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=476, Invalid=2830, Unknown=0, NotChecked=0, Total=3306 [2019-12-07 11:54:12,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12788 states. [2019-12-07 11:54:12,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12788 to 5822. [2019-12-07 11:54:12,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5822 states. [2019-12-07 11:54:12,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5822 states to 5822 states and 16133 transitions. [2019-12-07 11:54:12,784 INFO L78 Accepts]: Start accepts. Automaton has 5822 states and 16133 transitions. Word has length 68 [2019-12-07 11:54:12,784 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:12,784 INFO L462 AbstractCegarLoop]: Abstraction has 5822 states and 16133 transitions. [2019-12-07 11:54:12,784 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 11:54:12,784 INFO L276 IsEmpty]: Start isEmpty. Operand 5822 states and 16133 transitions. [2019-12-07 11:54:12,789 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:54:12,789 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:12,789 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:12,789 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:12,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:12,789 INFO L82 PathProgramCache]: Analyzing trace with hash -1311051616, now seen corresponding path program 2 times [2019-12-07 11:54:12,789 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:12,789 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [513934322] [2019-12-07 11:54:12,789 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:12,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:13,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:13,155 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [513934322] [2019-12-07 11:54:13,155 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:13,155 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 11:54:13,156 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1155873424] [2019-12-07 11:54:13,156 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 11:54:13,156 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:13,156 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 11:54:13,156 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=259, Unknown=0, NotChecked=0, Total=306 [2019-12-07 11:54:13,156 INFO L87 Difference]: Start difference. First operand 5822 states and 16133 transitions. Second operand 18 states. [2019-12-07 11:54:14,551 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:14,551 INFO L93 Difference]: Finished difference Result 12950 states and 35655 transitions. [2019-12-07 11:54:14,551 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-12-07 11:54:14,552 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 68 [2019-12-07 11:54:14,552 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:14,562 INFO L225 Difference]: With dead ends: 12950 [2019-12-07 11:54:14,562 INFO L226 Difference]: Without dead ends: 12925 [2019-12-07 11:54:14,563 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 1 SyntacticMatches, 4 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 374 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=275, Invalid=1447, Unknown=0, NotChecked=0, Total=1722 [2019-12-07 11:54:14,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12925 states. [2019-12-07 11:54:14,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12925 to 5868. [2019-12-07 11:54:14,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5868 states. [2019-12-07 11:54:14,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5868 states to 5868 states and 16264 transitions. [2019-12-07 11:54:14,665 INFO L78 Accepts]: Start accepts. Automaton has 5868 states and 16264 transitions. Word has length 68 [2019-12-07 11:54:14,665 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:14,665 INFO L462 AbstractCegarLoop]: Abstraction has 5868 states and 16264 transitions. [2019-12-07 11:54:14,665 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 11:54:14,665 INFO L276 IsEmpty]: Start isEmpty. Operand 5868 states and 16264 transitions. [2019-12-07 11:54:14,669 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:54:14,669 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:14,669 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:14,669 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:14,669 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:14,669 INFO L82 PathProgramCache]: Analyzing trace with hash 209870412, now seen corresponding path program 3 times [2019-12-07 11:54:14,669 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:14,669 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415012895] [2019-12-07 11:54:14,669 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:14,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:14,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:14,980 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1415012895] [2019-12-07 11:54:14,980 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:14,980 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2019-12-07 11:54:14,980 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1082795900] [2019-12-07 11:54:14,981 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 11:54:14,981 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:14,981 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 11:54:14,981 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=291, Unknown=0, NotChecked=0, Total=342 [2019-12-07 11:54:14,981 INFO L87 Difference]: Start difference. First operand 5868 states and 16264 transitions. Second operand 19 states. [2019-12-07 11:54:16,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:16,818 INFO L93 Difference]: Finished difference Result 15725 states and 42974 transitions. [2019-12-07 11:54:16,818 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-12-07 11:54:16,818 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 68 [2019-12-07 11:54:16,818 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:16,830 INFO L225 Difference]: With dead ends: 15725 [2019-12-07 11:54:16,830 INFO L226 Difference]: Without dead ends: 15006 [2019-12-07 11:54:16,831 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 646 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=406, Invalid=2246, Unknown=0, NotChecked=0, Total=2652 [2019-12-07 11:54:16,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15006 states. [2019-12-07 11:54:16,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15006 to 6085. [2019-12-07 11:54:16,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6085 states. [2019-12-07 11:54:16,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6085 states to 6085 states and 16887 transitions. [2019-12-07 11:54:16,943 INFO L78 Accepts]: Start accepts. Automaton has 6085 states and 16887 transitions. Word has length 68 [2019-12-07 11:54:16,943 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:16,943 INFO L462 AbstractCegarLoop]: Abstraction has 6085 states and 16887 transitions. [2019-12-07 11:54:16,943 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 11:54:16,943 INFO L276 IsEmpty]: Start isEmpty. Operand 6085 states and 16887 transitions. [2019-12-07 11:54:16,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:54:16,947 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:16,947 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:16,947 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:16,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:16,948 INFO L82 PathProgramCache]: Analyzing trace with hash 1592868418, now seen corresponding path program 4 times [2019-12-07 11:54:16,948 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:16,948 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [446038140] [2019-12-07 11:54:16,948 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:16,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:17,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:17,099 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [446038140] [2019-12-07 11:54:17,099 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:17,099 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 11:54:17,099 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [96846044] [2019-12-07 11:54:17,099 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 11:54:17,099 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:17,099 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 11:54:17,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=129, Unknown=0, NotChecked=0, Total=156 [2019-12-07 11:54:17,100 INFO L87 Difference]: Start difference. First operand 6085 states and 16887 transitions. Second operand 13 states. [2019-12-07 11:54:17,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:17,540 INFO L93 Difference]: Finished difference Result 10386 states and 28626 transitions. [2019-12-07 11:54:17,541 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 11:54:17,541 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 68 [2019-12-07 11:54:17,541 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:17,548 INFO L225 Difference]: With dead ends: 10386 [2019-12-07 11:54:17,548 INFO L226 Difference]: Without dead ends: 9867 [2019-12-07 11:54:17,549 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 150 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=185, Invalid=685, Unknown=0, NotChecked=0, Total=870 [2019-12-07 11:54:17,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9867 states. [2019-12-07 11:54:17,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9867 to 6167. [2019-12-07 11:54:17,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6167 states. [2019-12-07 11:54:17,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6167 states to 6167 states and 17107 transitions. [2019-12-07 11:54:17,632 INFO L78 Accepts]: Start accepts. Automaton has 6167 states and 17107 transitions. Word has length 68 [2019-12-07 11:54:17,632 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:17,632 INFO L462 AbstractCegarLoop]: Abstraction has 6167 states and 17107 transitions. [2019-12-07 11:54:17,632 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 11:54:17,632 INFO L276 IsEmpty]: Start isEmpty. Operand 6167 states and 17107 transitions. [2019-12-07 11:54:17,636 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:54:17,636 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:17,636 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:17,636 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:17,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:17,636 INFO L82 PathProgramCache]: Analyzing trace with hash -526111866, now seen corresponding path program 5 times [2019-12-07 11:54:17,636 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:17,636 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [961568706] [2019-12-07 11:54:17,637 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:17,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:18,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:18,005 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [961568706] [2019-12-07 11:54:18,005 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:18,005 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2019-12-07 11:54:18,005 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [203958638] [2019-12-07 11:54:18,005 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-12-07 11:54:18,005 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:18,005 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 11:54:18,006 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=323, Unknown=0, NotChecked=0, Total=380 [2019-12-07 11:54:18,006 INFO L87 Difference]: Start difference. First operand 6167 states and 17107 transitions. Second operand 20 states. [2019-12-07 11:54:21,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:21,985 INFO L93 Difference]: Finished difference Result 14889 states and 40976 transitions. [2019-12-07 11:54:21,986 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-12-07 11:54:21,986 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 68 [2019-12-07 11:54:21,987 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:22,017 INFO L225 Difference]: With dead ends: 14889 [2019-12-07 11:54:22,017 INFO L226 Difference]: Without dead ends: 14864 [2019-12-07 11:54:22,019 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 659 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=469, Invalid=2287, Unknown=0, NotChecked=0, Total=2756 [2019-12-07 11:54:22,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14864 states. [2019-12-07 11:54:22,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14864 to 6263. [2019-12-07 11:54:22,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6263 states. [2019-12-07 11:54:22,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6263 states to 6263 states and 17379 transitions. [2019-12-07 11:54:22,139 INFO L78 Accepts]: Start accepts. Automaton has 6263 states and 17379 transitions. Word has length 68 [2019-12-07 11:54:22,139 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:22,139 INFO L462 AbstractCegarLoop]: Abstraction has 6263 states and 17379 transitions. [2019-12-07 11:54:22,139 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-12-07 11:54:22,139 INFO L276 IsEmpty]: Start isEmpty. Operand 6263 states and 17379 transitions. [2019-12-07 11:54:22,144 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:54:22,144 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:22,144 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:22,144 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:22,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:22,144 INFO L82 PathProgramCache]: Analyzing trace with hash -450226916, now seen corresponding path program 6 times [2019-12-07 11:54:22,144 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:22,145 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434011867] [2019-12-07 11:54:22,145 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:22,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:22,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:22,463 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [434011867] [2019-12-07 11:54:22,463 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:22,463 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2019-12-07 11:54:22,463 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1250592156] [2019-12-07 11:54:22,463 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 11:54:22,463 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:22,463 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 11:54:22,464 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=292, Unknown=0, NotChecked=0, Total=342 [2019-12-07 11:54:22,464 INFO L87 Difference]: Start difference. First operand 6263 states and 17379 transitions. Second operand 19 states. [2019-12-07 11:54:25,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:25,689 INFO L93 Difference]: Finished difference Result 18299 states and 49967 transitions. [2019-12-07 11:54:25,690 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-12-07 11:54:25,691 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 68 [2019-12-07 11:54:25,691 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:25,715 INFO L225 Difference]: With dead ends: 18299 [2019-12-07 11:54:25,715 INFO L226 Difference]: Without dead ends: 17580 [2019-12-07 11:54:25,716 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 842 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=524, Invalid=2782, Unknown=0, NotChecked=0, Total=3306 [2019-12-07 11:54:25,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17580 states. [2019-12-07 11:54:25,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17580 to 6496. [2019-12-07 11:54:25,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6496 states. [2019-12-07 11:54:25,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6496 states to 6496 states and 18063 transitions. [2019-12-07 11:54:25,847 INFO L78 Accepts]: Start accepts. Automaton has 6496 states and 18063 transitions. Word has length 68 [2019-12-07 11:54:25,847 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:25,847 INFO L462 AbstractCegarLoop]: Abstraction has 6496 states and 18063 transitions. [2019-12-07 11:54:25,847 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 11:54:25,847 INFO L276 IsEmpty]: Start isEmpty. Operand 6496 states and 18063 transitions. [2019-12-07 11:54:25,852 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:54:25,852 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:25,852 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:25,852 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:25,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:25,853 INFO L82 PathProgramCache]: Analyzing trace with hash 932771090, now seen corresponding path program 7 times [2019-12-07 11:54:25,853 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:25,853 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [587369742] [2019-12-07 11:54:25,853 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:25,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:26,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:26,045 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [587369742] [2019-12-07 11:54:26,045 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:26,045 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 11:54:26,046 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1675066890] [2019-12-07 11:54:26,046 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 11:54:26,046 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:26,046 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 11:54:26,046 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=173, Unknown=0, NotChecked=0, Total=210 [2019-12-07 11:54:26,046 INFO L87 Difference]: Start difference. First operand 6496 states and 18063 transitions. Second operand 15 states. [2019-12-07 11:54:26,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:26,683 INFO L93 Difference]: Finished difference Result 13937 states and 38653 transitions. [2019-12-07 11:54:26,684 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-12-07 11:54:26,684 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 68 [2019-12-07 11:54:26,684 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:26,694 INFO L225 Difference]: With dead ends: 13937 [2019-12-07 11:54:26,694 INFO L226 Difference]: Without dead ends: 12906 [2019-12-07 11:54:26,695 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 308 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=310, Invalid=1172, Unknown=0, NotChecked=0, Total=1482 [2019-12-07 11:54:26,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12906 states. [2019-12-07 11:54:26,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12906 to 6193. [2019-12-07 11:54:26,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6193 states. [2019-12-07 11:54:26,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6193 states to 6193 states and 17165 transitions. [2019-12-07 11:54:26,795 INFO L78 Accepts]: Start accepts. Automaton has 6193 states and 17165 transitions. Word has length 68 [2019-12-07 11:54:26,795 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:26,795 INFO L462 AbstractCegarLoop]: Abstraction has 6193 states and 17165 transitions. [2019-12-07 11:54:26,795 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 11:54:26,796 INFO L276 IsEmpty]: Start isEmpty. Operand 6193 states and 17165 transitions. [2019-12-07 11:54:26,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:54:26,800 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:26,800 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:26,800 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:26,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:26,800 INFO L82 PathProgramCache]: Analyzing trace with hash -1379923308, now seen corresponding path program 8 times [2019-12-07 11:54:26,800 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:26,800 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1613820910] [2019-12-07 11:54:26,800 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:26,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:27,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:27,179 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1613820910] [2019-12-07 11:54:27,179 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:27,180 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2019-12-07 11:54:27,180 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1380214821] [2019-12-07 11:54:27,180 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 11:54:27,180 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:27,180 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 11:54:27,180 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=361, Unknown=0, NotChecked=0, Total=420 [2019-12-07 11:54:27,180 INFO L87 Difference]: Start difference. First operand 6193 states and 17165 transitions. Second operand 21 states. [2019-12-07 11:54:32,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:32,855 INFO L93 Difference]: Finished difference Result 17034 states and 46688 transitions. [2019-12-07 11:54:32,856 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2019-12-07 11:54:32,856 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 68 [2019-12-07 11:54:32,856 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:32,870 INFO L225 Difference]: With dead ends: 17034 [2019-12-07 11:54:32,870 INFO L226 Difference]: Without dead ends: 16885 [2019-12-07 11:54:32,871 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1147 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=656, Invalid=3634, Unknown=0, NotChecked=0, Total=4290 [2019-12-07 11:54:32,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16885 states. [2019-12-07 11:54:32,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16885 to 6232. [2019-12-07 11:54:32,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6232 states. [2019-12-07 11:54:32,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6232 states to 6232 states and 17322 transitions. [2019-12-07 11:54:32,993 INFO L78 Accepts]: Start accepts. Automaton has 6232 states and 17322 transitions. Word has length 68 [2019-12-07 11:54:32,993 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:32,993 INFO L462 AbstractCegarLoop]: Abstraction has 6232 states and 17322 transitions. [2019-12-07 11:54:32,993 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 11:54:32,993 INFO L276 IsEmpty]: Start isEmpty. Operand 6232 states and 17322 transitions. [2019-12-07 11:54:32,998 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:54:32,998 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:32,998 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:32,998 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:32,998 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:32,998 INFO L82 PathProgramCache]: Analyzing trace with hash 556311610, now seen corresponding path program 9 times [2019-12-07 11:54:32,998 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:32,998 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [63434700] [2019-12-07 11:54:32,999 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:33,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:33,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:33,358 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [63434700] [2019-12-07 11:54:33,358 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:33,358 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2019-12-07 11:54:33,359 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [485867519] [2019-12-07 11:54:33,359 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-12-07 11:54:33,359 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:33,359 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 11:54:33,359 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=326, Unknown=0, NotChecked=0, Total=380 [2019-12-07 11:54:33,359 INFO L87 Difference]: Start difference. First operand 6232 states and 17322 transitions. Second operand 20 states. [2019-12-07 11:54:39,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:39,859 INFO L93 Difference]: Finished difference Result 20055 states and 54701 transitions. [2019-12-07 11:54:39,860 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2019-12-07 11:54:39,861 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 68 [2019-12-07 11:54:39,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:39,894 INFO L225 Difference]: With dead ends: 20055 [2019-12-07 11:54:39,894 INFO L226 Difference]: Without dead ends: 19866 [2019-12-07 11:54:39,896 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 3 SyntacticMatches, 4 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1601 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=762, Invalid=4788, Unknown=0, NotChecked=0, Total=5550 [2019-12-07 11:54:39,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19866 states. [2019-12-07 11:54:40,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19866 to 6426. [2019-12-07 11:54:40,039 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6426 states. [2019-12-07 11:54:40,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6426 states to 6426 states and 17881 transitions. [2019-12-07 11:54:40,047 INFO L78 Accepts]: Start accepts. Automaton has 6426 states and 17881 transitions. Word has length 68 [2019-12-07 11:54:40,047 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:40,047 INFO L462 AbstractCegarLoop]: Abstraction has 6426 states and 17881 transitions. [2019-12-07 11:54:40,047 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-12-07 11:54:40,047 INFO L276 IsEmpty]: Start isEmpty. Operand 6426 states and 17881 transitions. [2019-12-07 11:54:40,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:54:40,051 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:40,051 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:40,051 INFO L410 AbstractCegarLoop]: === Iteration 29 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:40,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:40,052 INFO L82 PathProgramCache]: Analyzing trace with hash 261877780, now seen corresponding path program 10 times [2019-12-07 11:54:40,052 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:40,052 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1065330520] [2019-12-07 11:54:40,052 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:40,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:40,381 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:40,381 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1065330520] [2019-12-07 11:54:40,381 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:40,381 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2019-12-07 11:54:40,381 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1906703480] [2019-12-07 11:54:40,382 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-12-07 11:54:40,382 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:40,382 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 11:54:40,382 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2019-12-07 11:54:40,382 INFO L87 Difference]: Start difference. First operand 6426 states and 17881 transitions. Second operand 20 states. [2019-12-07 11:54:43,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:43,740 INFO L93 Difference]: Finished difference Result 19303 states and 52756 transitions. [2019-12-07 11:54:43,740 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2019-12-07 11:54:43,741 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 68 [2019-12-07 11:54:43,741 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:43,755 INFO L225 Difference]: With dead ends: 19303 [2019-12-07 11:54:43,755 INFO L226 Difference]: Without dead ends: 18534 [2019-12-07 11:54:43,756 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 66 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1054 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=594, Invalid=3312, Unknown=0, NotChecked=0, Total=3906 [2019-12-07 11:54:43,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18534 states. [2019-12-07 11:54:43,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18534 to 6595. [2019-12-07 11:54:43,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6595 states. [2019-12-07 11:54:43,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6595 states to 6595 states and 18386 transitions. [2019-12-07 11:54:43,890 INFO L78 Accepts]: Start accepts. Automaton has 6595 states and 18386 transitions. Word has length 68 [2019-12-07 11:54:43,890 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:43,891 INFO L462 AbstractCegarLoop]: Abstraction has 6595 states and 18386 transitions. [2019-12-07 11:54:43,891 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-12-07 11:54:43,891 INFO L276 IsEmpty]: Start isEmpty. Operand 6595 states and 18386 transitions. [2019-12-07 11:54:43,895 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:54:43,895 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:43,895 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:43,895 INFO L410 AbstractCegarLoop]: === Iteration 30 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:43,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:43,896 INFO L82 PathProgramCache]: Analyzing trace with hash -133778180, now seen corresponding path program 11 times [2019-12-07 11:54:43,896 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:43,896 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1828892821] [2019-12-07 11:54:43,896 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:43,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:54:44,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:54:44,050 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1828892821] [2019-12-07 11:54:44,051 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:54:44,051 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 11:54:44,051 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1738723095] [2019-12-07 11:54:44,051 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 11:54:44,051 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:54:44,051 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 11:54:44,051 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=147, Unknown=0, NotChecked=0, Total=182 [2019-12-07 11:54:44,052 INFO L87 Difference]: Start difference. First operand 6595 states and 18386 transitions. Second operand 14 states. [2019-12-07 11:54:44,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:54:44,444 INFO L93 Difference]: Finished difference Result 8985 states and 24753 transitions. [2019-12-07 11:54:44,444 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-12-07 11:54:44,444 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 68 [2019-12-07 11:54:44,444 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:54:44,451 INFO L225 Difference]: With dead ends: 8985 [2019-12-07 11:54:44,451 INFO L226 Difference]: Without dead ends: 8478 [2019-12-07 11:54:44,451 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 164 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=195, Invalid=735, Unknown=0, NotChecked=0, Total=930 [2019-12-07 11:54:44,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8478 states. [2019-12-07 11:54:44,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8478 to 5476. [2019-12-07 11:54:44,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5476 states. [2019-12-07 11:54:44,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5476 states to 5476 states and 15095 transitions. [2019-12-07 11:54:44,524 INFO L78 Accepts]: Start accepts. Automaton has 5476 states and 15095 transitions. Word has length 68 [2019-12-07 11:54:44,524 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:54:44,524 INFO L462 AbstractCegarLoop]: Abstraction has 5476 states and 15095 transitions. [2019-12-07 11:54:44,524 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 11:54:44,524 INFO L276 IsEmpty]: Start isEmpty. Operand 5476 states and 15095 transitions. [2019-12-07 11:54:44,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:54:44,527 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:54:44,528 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:54:44,528 INFO L410 AbstractCegarLoop]: === Iteration 31 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:54:44,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:54:44,528 INFO L82 PathProgramCache]: Analyzing trace with hash 2056032048, now seen corresponding path program 12 times [2019-12-07 11:54:44,528 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:54:44,528 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [5476475] [2019-12-07 11:54:44,528 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:54:44,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 11:54:44,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 11:54:44,590 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 11:54:44,590 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 11:54:44,592 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [827] [827] ULTIMATE.startENTRY-->L807: Formula: (let ((.cse0 (store |v_#valid_66| 0 0))) (and (= 0 v_~__unbuffered_p2_EAX~0_40) (= |v_ULTIMATE.start_main_~#t1961~0.offset_17| 0) (= v_~z$r_buff1_thd0~0_289 0) (= v_~z$r_buff0_thd1~0_194 0) (= v_~z$mem_tmp~0_22 0) (= v_~z$w_buff0~0_192 0) (= 0 v_~weak$$choice0~0_14) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t1961~0.base_23|) (= v_~z~0_201 0) (= 0 v_~__unbuffered_p1_EAX~0_42) (= v_~y~0_14 0) (= v_~main$tmp_guard1~0_48 0) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t1961~0.base_23| 4)) (= |v_#NULL.offset_3| 0) (= v_~z$w_buff0_used~0_745 0) (= v_~z$r_buff0_thd0~0_352 0) (= 0 v_~z$r_buff0_thd3~0_106) (= v_~z$w_buff1_used~0_381 0) (= v_~main$tmp_guard0~0_23 0) (= v_~z$read_delayed_var~0.offset_7 0) (< 0 |v_#StackHeapBarrier_18|) (= v_~z$r_buff1_thd1~0_172 0) (= v_~__unbuffered_cnt~0_156 0) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$read_delayed~0_7 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1961~0.base_23|)) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1961~0.base_23| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1961~0.base_23|) |v_ULTIMATE.start_main_~#t1961~0.offset_17| 0)) |v_#memory_int_23|) (= 0 v_~z$flush_delayed~0_41) (= |v_#valid_64| (store .cse0 |v_ULTIMATE.start_main_~#t1961~0.base_23| 1)) (= v_~z$w_buff1~0_171 0) (= 0 v_~x~0_113) (= 0 |v_#NULL.base_3|) (= v_~weak$$choice2~0_111 0) (= v_~z$r_buff0_thd2~0_100 0) (= v_~z$r_buff1_thd2~0_185 0) (= 0 v_~z$r_buff1_thd3~0_186))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_66|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_20|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_26|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_185, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_34|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_27|, #NULL.offset=|v_#NULL.offset_3|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_24|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_72|, ULTIMATE.start_main_~#t1961~0.offset=|v_ULTIMATE.start_main_~#t1961~0.offset_17|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_42|, ULTIMATE.start_main_~#t1963~0.base=|v_ULTIMATE.start_main_~#t1963~0.base_20|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_24|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_72|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_35|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_352, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_42, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_40, ~z$mem_tmp~0=v_~z$mem_tmp~0_22, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_28|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_41|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_381, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_39|, ~z$flush_delayed~0=v_~z$flush_delayed~0_41, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_74|, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_149|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_172, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_106, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_156, ~x~0=v_~x~0_113, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_20|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_32|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_25|, ~z$w_buff1~0=v_~z$w_buff1~0_171, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_48, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_32|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_28|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_260|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_40|, ULTIMATE.start_main_~#t1963~0.offset=|v_ULTIMATE.start_main_~#t1963~0.offset_16|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_74|, ULTIMATE.start_main_~#t1962~0.base=|v_ULTIMATE.start_main_~#t1962~0.base_21|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_289, ~y~0=v_~y~0_14, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_100, ULTIMATE.start_main_~#t1961~0.base=|v_ULTIMATE.start_main_~#t1961~0.base_23|, ULTIMATE.start_main_~#t1962~0.offset=|v_ULTIMATE.start_main_~#t1962~0.offset_16|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_8|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_745, ~z$w_buff0~0=v_~z$w_buff0~0_192, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_186, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_24|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_44|, #NULL.base=|v_#NULL.base_3|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_41|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_149|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_23|, ~z~0=v_~z~0_201, ~weak$$choice2~0=v_~weak$$choice2~0_111, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_194} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_~#t1961~0.offset, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_~#t1963~0.base, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t1963~0.offset, ULTIMATE.start_main_#t~ite51, ULTIMATE.start_main_~#t1962~0.base, ~z$r_buff1_thd0~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_~#t1961~0.base, ULTIMATE.start_main_~#t1962~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 11:54:44,593 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L807-1-->L809: Formula: (and (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1962~0.base_11| 4)) (= |v_#memory_int_15| (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1962~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1962~0.base_11|) |v_ULTIMATE.start_main_~#t1962~0.offset_10| 1))) (not (= |v_ULTIMATE.start_main_~#t1962~0.base_11| 0)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1962~0.base_11|) (= 0 |v_ULTIMATE.start_main_~#t1962~0.offset_10|) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t1962~0.base_11|)) (= |v_#valid_35| (store |v_#valid_36| |v_ULTIMATE.start_main_~#t1962~0.base_11| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t1962~0.offset=|v_ULTIMATE.start_main_~#t1962~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, ULTIMATE.start_main_~#t1962~0.base=|v_ULTIMATE.start_main_~#t1962~0.base_11|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_15|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1962~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t1962~0.base, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 11:54:44,593 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] P0ENTRY-->L4-3: Formula: (and (= v_~z$w_buff0~0_42 v_~z$w_buff1~0_28) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 0)) (= v_P0Thread1of1ForFork0_~arg.offset_6 |v_P0Thread1of1ForFork0_#in~arg.offset_8|) (= |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| (ite (not (and (not (= 0 (mod v_~z$w_buff1_used~0_97 256))) (not (= (mod v_~z$w_buff0_used~0_206 256) 0)))) 1 0)) (= v_~z$w_buff0_used~0_207 v_~z$w_buff1_used~0_97) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~z$w_buff0_used~0_206 1) (= v_P0Thread1of1ForFork0_~arg.base_6 |v_P0Thread1of1ForFork0_#in~arg.base_8|) (= 2 v_~z$w_buff0~0_41)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_207, ~z$w_buff0~0=v_~z$w_buff0~0_42, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_206, ~z$w_buff0~0=v_~z$w_buff0~0_41, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_97, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|, ~z$w_buff1~0=v_~z$w_buff1~0_28, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_6, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_6} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 11:54:44,593 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L809-1-->L811: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t1963~0.base_12|)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1963~0.base_12| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1963~0.base_12|) |v_ULTIMATE.start_main_~#t1963~0.offset_10| 2)) |v_#memory_int_13|) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t1963~0.base_12| 1)) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1963~0.base_12|) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1963~0.base_12| 4)) (= (select |v_#valid_32| |v_ULTIMATE.start_main_~#t1963~0.base_12|) 0) (= 0 |v_ULTIMATE.start_main_~#t1963~0.offset_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t1963~0.offset=|v_ULTIMATE.start_main_~#t1963~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, #length=|v_#length_15|, ULTIMATE.start_main_~#t1963~0.base=|v_ULTIMATE.start_main_~#t1963~0.base_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1963~0.offset, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1963~0.base] because there is no mapped edge [2019-12-07 11:54:44,594 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L745-->L745-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In1807221492 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd1~0_In1807221492 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |P0Thread1of1ForFork0_#t~ite5_Out1807221492|)) (and (or .cse1 .cse0) (= |P0Thread1of1ForFork0_#t~ite5_Out1807221492| ~z$w_buff0_used~0_In1807221492)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1807221492, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1807221492} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out1807221492|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1807221492, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1807221492} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 11:54:44,594 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L746-->L746-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In954187119 256))) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In954187119 256))) (.cse2 (= (mod ~z$r_buff1_thd1~0_In954187119 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In954187119 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork0_#t~ite6_Out954187119|)) (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In954187119 |P0Thread1of1ForFork0_#t~ite6_Out954187119|) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In954187119, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In954187119, ~z$w_buff1_used~0=~z$w_buff1_used~0_In954187119, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In954187119} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out954187119|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In954187119, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In954187119, ~z$w_buff1_used~0=~z$w_buff1_used~0_In954187119, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In954187119} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 11:54:44,595 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L747-->L748: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In1877484671 256) 0)) (.cse2 (= ~z$r_buff0_thd1~0_In1877484671 ~z$r_buff0_thd1~0_Out1877484671)) (.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In1877484671 256)))) (or (and (not .cse0) (= 0 ~z$r_buff0_thd1~0_Out1877484671) (not .cse1)) (and .cse2 .cse1) (and .cse2 .cse0))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1877484671, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1877484671} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1877484671, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out1877484671|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out1877484671} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 11:54:44,595 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L748-->L748-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd1~0_In1553217812 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In1553217812 256))) (.cse3 (= 0 (mod ~z$r_buff0_thd1~0_In1553217812 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In1553217812 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite8_Out1553217812| 0)) (and (= |P0Thread1of1ForFork0_#t~ite8_Out1553217812| ~z$r_buff1_thd1~0_In1553217812) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1553217812, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1553217812, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1553217812, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1553217812} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1553217812, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out1553217812|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1553217812, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1553217812, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1553217812} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 11:54:44,595 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L748-2-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_66 1) v_~__unbuffered_cnt~0_65) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_64 |v_P0Thread1of1ForFork0_#t~ite8_42|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_42|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_41|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_64, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_65} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 11:54:44,595 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L764-2-->L764-4: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd2~0_In876127696 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In876127696 256) 0))) (or (and (= ~z~0_In876127696 |P1Thread1of1ForFork1_#t~ite9_Out876127696|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In876127696 |P1Thread1of1ForFork1_#t~ite9_Out876127696|)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In876127696, ~z$w_buff1_used~0=~z$w_buff1_used~0_In876127696, ~z$w_buff1~0=~z$w_buff1~0_In876127696, ~z~0=~z~0_In876127696} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out876127696|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In876127696, ~z$w_buff1_used~0=~z$w_buff1_used~0_In876127696, ~z$w_buff1~0=~z$w_buff1~0_In876127696, ~z~0=~z~0_In876127696} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-12-07 11:54:44,596 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L764-4-->L765: Formula: (= v_~z~0_33 |v_P1Thread1of1ForFork1_#t~ite9_14|) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_14|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_13|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_19|, ~z~0=v_~z~0_33} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~z~0] because there is no mapped edge [2019-12-07 11:54:44,596 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L765-->L765-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-2081310766 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In-2081310766 256)))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out-2081310766| ~z$w_buff0_used~0_In-2081310766)) (and (= |P1Thread1of1ForFork1_#t~ite11_Out-2081310766| 0) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-2081310766, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-2081310766} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-2081310766, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out-2081310766|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-2081310766} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 11:54:44,596 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L784-2-->L784-4: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In448570537 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In448570537 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite15_Out448570537| ~z~0_In448570537) (or .cse0 .cse1)) (and (= |P2Thread1of1ForFork2_#t~ite15_Out448570537| ~z$w_buff1~0_In448570537) (not .cse1) (not .cse0)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In448570537, ~z$w_buff1_used~0=~z$w_buff1_used~0_In448570537, ~z$w_buff1~0=~z$w_buff1~0_In448570537, ~z~0=~z~0_In448570537} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out448570537|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In448570537, ~z$w_buff1_used~0=~z$w_buff1_used~0_In448570537, ~z$w_buff1~0=~z$w_buff1~0_In448570537, ~z~0=~z~0_In448570537} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 11:54:44,596 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L766-->L766-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd2~0_In-1842098164 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-1842098164 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1842098164 256))) (.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In-1842098164 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork1_#t~ite12_Out-1842098164| 0)) (and (or .cse3 .cse2) (= ~z$w_buff1_used~0_In-1842098164 |P1Thread1of1ForFork1_#t~ite12_Out-1842098164|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1842098164, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1842098164, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1842098164, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1842098164} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1842098164, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1842098164, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1842098164, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-1842098164|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1842098164} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 11:54:44,597 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L767-->L767-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In-714545331 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-714545331 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite13_Out-714545331|) (not .cse0) (not .cse1)) (and (= ~z$r_buff0_thd2~0_In-714545331 |P1Thread1of1ForFork1_#t~ite13_Out-714545331|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-714545331, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-714545331} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-714545331, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-714545331|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-714545331} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 11:54:44,597 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L784-4-->L785: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~z~0_45) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, ~z~0=v_~z~0_45, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_13|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~z~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 11:54:44,597 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L785-->L785-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In1243798173 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In1243798173 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite17_Out1243798173| ~z$w_buff0_used~0_In1243798173) (or .cse0 .cse1)) (and (not .cse0) (= |P2Thread1of1ForFork2_#t~ite17_Out1243798173| 0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1243798173, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1243798173} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1243798173, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1243798173, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out1243798173|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 11:54:44,597 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L786-->L786-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-620380793 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-620380793 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In-620380793 256))) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In-620380793 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite18_Out-620380793|)) (and (= ~z$w_buff1_used~0_In-620380793 |P2Thread1of1ForFork2_#t~ite18_Out-620380793|) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-620380793, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-620380793, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-620380793, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-620380793} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-620380793, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-620380793, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-620380793, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-620380793, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-620380793|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 11:54:44,598 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L787-->L787-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In1723599255 256) 0)) (.cse1 (= (mod ~z$r_buff0_thd3~0_In1723599255 256) 0))) (or (and (= ~z$r_buff0_thd3~0_In1723599255 |P2Thread1of1ForFork2_#t~ite19_Out1723599255|) (or .cse0 .cse1)) (and (not .cse0) (= 0 |P2Thread1of1ForFork2_#t~ite19_Out1723599255|) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1723599255, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1723599255} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1723599255, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1723599255, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out1723599255|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 11:54:44,598 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [769] [769] L788-->L788-2: Formula: (let ((.cse3 (= (mod ~z$w_buff0_used~0_In-991303083 256) 0)) (.cse2 (= 0 (mod ~z$r_buff0_thd3~0_In-991303083 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In-991303083 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd3~0_In-991303083 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite20_Out-991303083| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse1 .cse0) (= ~z$r_buff1_thd3~0_In-991303083 |P2Thread1of1ForFork2_#t~ite20_Out-991303083|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-991303083, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-991303083, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-991303083, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-991303083} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-991303083, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-991303083|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-991303083, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-991303083, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-991303083} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 11:54:44,598 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L788-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite20_32| v_~z$r_buff1_thd3~0_66) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_73 1) v_~__unbuffered_cnt~0_72)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_73} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_31|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_66, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 11:54:44,598 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L768-->L768-2: Formula: (let ((.cse2 (= (mod ~z$w_buff1_used~0_In812094092 256) 0)) (.cse3 (= 0 (mod ~z$r_buff1_thd2~0_In812094092 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In812094092 256))) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In812094092 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork1_#t~ite14_Out812094092|)) (and (or .cse2 .cse3) (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite14_Out812094092| ~z$r_buff1_thd2~0_In812094092)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In812094092, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In812094092, ~z$w_buff1_used~0=~z$w_buff1_used~0_In812094092, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In812094092} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In812094092, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In812094092, ~z$w_buff1_used~0=~z$w_buff1_used~0_In812094092, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out812094092|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In812094092} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 11:54:44,598 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L768-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_38 1) v_~__unbuffered_cnt~0_37) (= |v_P1Thread1of1ForFork1_#t~ite14_28| v_~z$r_buff1_thd2~0_54) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_28|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_54, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_37, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_27|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 11:54:44,599 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L811-1-->L817: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 11:54:44,599 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L817-2-->L817-4: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff1_used~0_In1860596809 256))) (.cse0 (= (mod ~z$r_buff1_thd0~0_In1860596809 256) 0))) (or (and (not .cse0) (= ~z$w_buff1~0_In1860596809 |ULTIMATE.start_main_#t~ite24_Out1860596809|) (not .cse1)) (and (= ~z~0_In1860596809 |ULTIMATE.start_main_#t~ite24_Out1860596809|) (or .cse1 .cse0)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1860596809, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1860596809, ~z$w_buff1~0=~z$w_buff1~0_In1860596809, ~z~0=~z~0_In1860596809} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1860596809, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out1860596809|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1860596809, ~z$w_buff1~0=~z$w_buff1~0_In1860596809, ~z~0=~z~0_In1860596809} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 11:54:44,599 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L817-4-->L818: Formula: (= v_~z~0_21 |v_ULTIMATE.start_main_#t~ite24_9|) InVars {ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_9|} OutVars{ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_8|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_12|, ~z~0=v_~z~0_21} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25, ~z~0] because there is no mapped edge [2019-12-07 11:54:44,599 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L818-->L818-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-204954029 256))) (.cse1 (= (mod ~z$r_buff0_thd0~0_In-204954029 256) 0))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite26_Out-204954029|) (not .cse1)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite26_Out-204954029| ~z$w_buff0_used~0_In-204954029)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-204954029, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-204954029} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-204954029, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-204954029, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-204954029|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 11:54:44,599 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L819-->L819-2: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd0~0_In254189217 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In254189217 256))) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In254189217 256))) (.cse2 (= (mod ~z$r_buff0_thd0~0_In254189217 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite27_Out254189217| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |ULTIMATE.start_main_#t~ite27_Out254189217| ~z$w_buff1_used~0_In254189217) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In254189217, ~z$w_buff0_used~0=~z$w_buff0_used~0_In254189217, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In254189217, ~z$w_buff1_used~0=~z$w_buff1_used~0_In254189217} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In254189217, ~z$w_buff0_used~0=~z$w_buff0_used~0_In254189217, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In254189217, ~z$w_buff1_used~0=~z$w_buff1_used~0_In254189217, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out254189217|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 11:54:44,600 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [780] [780] L820-->L820-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In1153511019 256))) (.cse0 (= (mod ~z$r_buff0_thd0~0_In1153511019 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite28_Out1153511019| ~z$r_buff0_thd0~0_In1153511019)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite28_Out1153511019| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1153511019, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1153511019} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1153511019, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out1153511019|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1153511019} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 11:54:44,600 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L821-->L821-2: Formula: (let ((.cse2 (= (mod ~z$r_buff1_thd0~0_In-469790921 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In-469790921 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In-469790921 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-469790921 256)))) (or (and (= ~z$r_buff1_thd0~0_In-469790921 |ULTIMATE.start_main_#t~ite29_Out-469790921|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |ULTIMATE.start_main_#t~ite29_Out-469790921| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-469790921, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-469790921, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-469790921, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-469790921} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-469790921, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-469790921|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-469790921, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-469790921, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-469790921} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 11:54:44,602 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L833-->L834: Formula: (and (= v_~z$r_buff0_thd0~0_167 v_~z$r_buff0_thd0~0_166) (not (= (mod v_~weak$$choice2~0_39 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_167, ~weak$$choice2~0=v_~weak$$choice2~0_39} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_166, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_10|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_11|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_8|, ~weak$$choice2~0=v_~weak$$choice2~0_39} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 11:54:44,603 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L836-->L4: Formula: (and (= v_~z$mem_tmp~0_13 v_~z~0_134) (= 0 v_~z$flush_delayed~0_22) (= (mod v_~main$tmp_guard1~0_32 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (not (= (mod v_~z$flush_delayed~0_23 256) 0))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_13, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_23} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_13, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_17|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_22, ~z~0=v_~z~0_134, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 11:54:44,603 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_13, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 11:54:44,656 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 11:54:44 BasicIcfg [2019-12-07 11:54:44,656 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 11:54:44,657 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 11:54:44,657 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 11:54:44,657 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 11:54:44,657 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 11:52:19" (3/4) ... [2019-12-07 11:54:44,659 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 11:54:44,659 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [827] [827] ULTIMATE.startENTRY-->L807: Formula: (let ((.cse0 (store |v_#valid_66| 0 0))) (and (= 0 v_~__unbuffered_p2_EAX~0_40) (= |v_ULTIMATE.start_main_~#t1961~0.offset_17| 0) (= v_~z$r_buff1_thd0~0_289 0) (= v_~z$r_buff0_thd1~0_194 0) (= v_~z$mem_tmp~0_22 0) (= v_~z$w_buff0~0_192 0) (= 0 v_~weak$$choice0~0_14) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t1961~0.base_23|) (= v_~z~0_201 0) (= 0 v_~__unbuffered_p1_EAX~0_42) (= v_~y~0_14 0) (= v_~main$tmp_guard1~0_48 0) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t1961~0.base_23| 4)) (= |v_#NULL.offset_3| 0) (= v_~z$w_buff0_used~0_745 0) (= v_~z$r_buff0_thd0~0_352 0) (= 0 v_~z$r_buff0_thd3~0_106) (= v_~z$w_buff1_used~0_381 0) (= v_~main$tmp_guard0~0_23 0) (= v_~z$read_delayed_var~0.offset_7 0) (< 0 |v_#StackHeapBarrier_18|) (= v_~z$r_buff1_thd1~0_172 0) (= v_~__unbuffered_cnt~0_156 0) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$read_delayed~0_7 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1961~0.base_23|)) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1961~0.base_23| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1961~0.base_23|) |v_ULTIMATE.start_main_~#t1961~0.offset_17| 0)) |v_#memory_int_23|) (= 0 v_~z$flush_delayed~0_41) (= |v_#valid_64| (store .cse0 |v_ULTIMATE.start_main_~#t1961~0.base_23| 1)) (= v_~z$w_buff1~0_171 0) (= 0 v_~x~0_113) (= 0 |v_#NULL.base_3|) (= v_~weak$$choice2~0_111 0) (= v_~z$r_buff0_thd2~0_100 0) (= v_~z$r_buff1_thd2~0_185 0) (= 0 v_~z$r_buff1_thd3~0_186))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_66|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_20|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_26|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_185, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_34|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_27|, #NULL.offset=|v_#NULL.offset_3|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_24|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_72|, ULTIMATE.start_main_~#t1961~0.offset=|v_ULTIMATE.start_main_~#t1961~0.offset_17|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_42|, ULTIMATE.start_main_~#t1963~0.base=|v_ULTIMATE.start_main_~#t1963~0.base_20|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_24|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_72|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_35|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_352, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_42, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_40, ~z$mem_tmp~0=v_~z$mem_tmp~0_22, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_28|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_41|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_381, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_39|, ~z$flush_delayed~0=v_~z$flush_delayed~0_41, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_74|, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_149|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_172, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_106, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_156, ~x~0=v_~x~0_113, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_20|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_32|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_25|, ~z$w_buff1~0=v_~z$w_buff1~0_171, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_48, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_32|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_28|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_260|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_40|, ULTIMATE.start_main_~#t1963~0.offset=|v_ULTIMATE.start_main_~#t1963~0.offset_16|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_74|, ULTIMATE.start_main_~#t1962~0.base=|v_ULTIMATE.start_main_~#t1962~0.base_21|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_289, ~y~0=v_~y~0_14, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_100, ULTIMATE.start_main_~#t1961~0.base=|v_ULTIMATE.start_main_~#t1961~0.base_23|, ULTIMATE.start_main_~#t1962~0.offset=|v_ULTIMATE.start_main_~#t1962~0.offset_16|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_8|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_745, ~z$w_buff0~0=v_~z$w_buff0~0_192, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_186, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_24|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_44|, #NULL.base=|v_#NULL.base_3|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_41|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_149|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_23|, ~z~0=v_~z~0_201, ~weak$$choice2~0=v_~weak$$choice2~0_111, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_194} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_~#t1961~0.offset, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_~#t1963~0.base, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t1963~0.offset, ULTIMATE.start_main_#t~ite51, ULTIMATE.start_main_~#t1962~0.base, ~z$r_buff1_thd0~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_~#t1961~0.base, ULTIMATE.start_main_~#t1962~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 11:54:44,659 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L807-1-->L809: Formula: (and (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1962~0.base_11| 4)) (= |v_#memory_int_15| (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1962~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1962~0.base_11|) |v_ULTIMATE.start_main_~#t1962~0.offset_10| 1))) (not (= |v_ULTIMATE.start_main_~#t1962~0.base_11| 0)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1962~0.base_11|) (= 0 |v_ULTIMATE.start_main_~#t1962~0.offset_10|) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t1962~0.base_11|)) (= |v_#valid_35| (store |v_#valid_36| |v_ULTIMATE.start_main_~#t1962~0.base_11| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t1962~0.offset=|v_ULTIMATE.start_main_~#t1962~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, ULTIMATE.start_main_~#t1962~0.base=|v_ULTIMATE.start_main_~#t1962~0.base_11|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_15|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1962~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t1962~0.base, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 11:54:44,660 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] P0ENTRY-->L4-3: Formula: (and (= v_~z$w_buff0~0_42 v_~z$w_buff1~0_28) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 0)) (= v_P0Thread1of1ForFork0_~arg.offset_6 |v_P0Thread1of1ForFork0_#in~arg.offset_8|) (= |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| (ite (not (and (not (= 0 (mod v_~z$w_buff1_used~0_97 256))) (not (= (mod v_~z$w_buff0_used~0_206 256) 0)))) 1 0)) (= v_~z$w_buff0_used~0_207 v_~z$w_buff1_used~0_97) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~z$w_buff0_used~0_206 1) (= v_P0Thread1of1ForFork0_~arg.base_6 |v_P0Thread1of1ForFork0_#in~arg.base_8|) (= 2 v_~z$w_buff0~0_41)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_207, ~z$w_buff0~0=v_~z$w_buff0~0_42, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_206, ~z$w_buff0~0=v_~z$w_buff0~0_41, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_97, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|, ~z$w_buff1~0=v_~z$w_buff1~0_28, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_6, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_6} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 11:54:44,660 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L809-1-->L811: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t1963~0.base_12|)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1963~0.base_12| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1963~0.base_12|) |v_ULTIMATE.start_main_~#t1963~0.offset_10| 2)) |v_#memory_int_13|) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t1963~0.base_12| 1)) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1963~0.base_12|) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1963~0.base_12| 4)) (= (select |v_#valid_32| |v_ULTIMATE.start_main_~#t1963~0.base_12|) 0) (= 0 |v_ULTIMATE.start_main_~#t1963~0.offset_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t1963~0.offset=|v_ULTIMATE.start_main_~#t1963~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, #length=|v_#length_15|, ULTIMATE.start_main_~#t1963~0.base=|v_ULTIMATE.start_main_~#t1963~0.base_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1963~0.offset, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1963~0.base] because there is no mapped edge [2019-12-07 11:54:44,660 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L745-->L745-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In1807221492 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd1~0_In1807221492 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |P0Thread1of1ForFork0_#t~ite5_Out1807221492|)) (and (or .cse1 .cse0) (= |P0Thread1of1ForFork0_#t~ite5_Out1807221492| ~z$w_buff0_used~0_In1807221492)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1807221492, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1807221492} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out1807221492|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1807221492, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1807221492} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 11:54:44,661 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L746-->L746-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In954187119 256))) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In954187119 256))) (.cse2 (= (mod ~z$r_buff1_thd1~0_In954187119 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In954187119 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork0_#t~ite6_Out954187119|)) (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In954187119 |P0Thread1of1ForFork0_#t~ite6_Out954187119|) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In954187119, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In954187119, ~z$w_buff1_used~0=~z$w_buff1_used~0_In954187119, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In954187119} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out954187119|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In954187119, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In954187119, ~z$w_buff1_used~0=~z$w_buff1_used~0_In954187119, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In954187119} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 11:54:44,661 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L747-->L748: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In1877484671 256) 0)) (.cse2 (= ~z$r_buff0_thd1~0_In1877484671 ~z$r_buff0_thd1~0_Out1877484671)) (.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In1877484671 256)))) (or (and (not .cse0) (= 0 ~z$r_buff0_thd1~0_Out1877484671) (not .cse1)) (and .cse2 .cse1) (and .cse2 .cse0))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1877484671, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1877484671} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1877484671, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out1877484671|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out1877484671} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 11:54:44,661 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L748-->L748-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd1~0_In1553217812 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In1553217812 256))) (.cse3 (= 0 (mod ~z$r_buff0_thd1~0_In1553217812 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In1553217812 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite8_Out1553217812| 0)) (and (= |P0Thread1of1ForFork0_#t~ite8_Out1553217812| ~z$r_buff1_thd1~0_In1553217812) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1553217812, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1553217812, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1553217812, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1553217812} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1553217812, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out1553217812|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1553217812, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1553217812, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1553217812} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 11:54:44,661 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L748-2-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_66 1) v_~__unbuffered_cnt~0_65) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_64 |v_P0Thread1of1ForFork0_#t~ite8_42|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_42|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_41|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_64, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_65} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 11:54:44,662 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L764-2-->L764-4: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd2~0_In876127696 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In876127696 256) 0))) (or (and (= ~z~0_In876127696 |P1Thread1of1ForFork1_#t~ite9_Out876127696|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In876127696 |P1Thread1of1ForFork1_#t~ite9_Out876127696|)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In876127696, ~z$w_buff1_used~0=~z$w_buff1_used~0_In876127696, ~z$w_buff1~0=~z$w_buff1~0_In876127696, ~z~0=~z~0_In876127696} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out876127696|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In876127696, ~z$w_buff1_used~0=~z$w_buff1_used~0_In876127696, ~z$w_buff1~0=~z$w_buff1~0_In876127696, ~z~0=~z~0_In876127696} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-12-07 11:54:44,662 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L764-4-->L765: Formula: (= v_~z~0_33 |v_P1Thread1of1ForFork1_#t~ite9_14|) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_14|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_13|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_19|, ~z~0=v_~z~0_33} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~z~0] because there is no mapped edge [2019-12-07 11:54:44,662 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L765-->L765-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-2081310766 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In-2081310766 256)))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out-2081310766| ~z$w_buff0_used~0_In-2081310766)) (and (= |P1Thread1of1ForFork1_#t~ite11_Out-2081310766| 0) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-2081310766, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-2081310766} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-2081310766, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out-2081310766|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-2081310766} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 11:54:44,663 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L784-2-->L784-4: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In448570537 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In448570537 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite15_Out448570537| ~z~0_In448570537) (or .cse0 .cse1)) (and (= |P2Thread1of1ForFork2_#t~ite15_Out448570537| ~z$w_buff1~0_In448570537) (not .cse1) (not .cse0)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In448570537, ~z$w_buff1_used~0=~z$w_buff1_used~0_In448570537, ~z$w_buff1~0=~z$w_buff1~0_In448570537, ~z~0=~z~0_In448570537} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out448570537|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In448570537, ~z$w_buff1_used~0=~z$w_buff1_used~0_In448570537, ~z$w_buff1~0=~z$w_buff1~0_In448570537, ~z~0=~z~0_In448570537} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 11:54:44,663 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L766-->L766-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd2~0_In-1842098164 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-1842098164 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1842098164 256))) (.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In-1842098164 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork1_#t~ite12_Out-1842098164| 0)) (and (or .cse3 .cse2) (= ~z$w_buff1_used~0_In-1842098164 |P1Thread1of1ForFork1_#t~ite12_Out-1842098164|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1842098164, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1842098164, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1842098164, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1842098164} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1842098164, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1842098164, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1842098164, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-1842098164|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1842098164} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 11:54:44,663 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L767-->L767-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In-714545331 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-714545331 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite13_Out-714545331|) (not .cse0) (not .cse1)) (and (= ~z$r_buff0_thd2~0_In-714545331 |P1Thread1of1ForFork1_#t~ite13_Out-714545331|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-714545331, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-714545331} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-714545331, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-714545331|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-714545331} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 11:54:44,663 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L784-4-->L785: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~z~0_45) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, ~z~0=v_~z~0_45, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_13|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~z~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 11:54:44,663 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L785-->L785-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In1243798173 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In1243798173 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite17_Out1243798173| ~z$w_buff0_used~0_In1243798173) (or .cse0 .cse1)) (and (not .cse0) (= |P2Thread1of1ForFork2_#t~ite17_Out1243798173| 0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1243798173, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1243798173} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1243798173, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1243798173, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out1243798173|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 11:54:44,663 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L786-->L786-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-620380793 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-620380793 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In-620380793 256))) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In-620380793 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite18_Out-620380793|)) (and (= ~z$w_buff1_used~0_In-620380793 |P2Thread1of1ForFork2_#t~ite18_Out-620380793|) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-620380793, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-620380793, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-620380793, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-620380793} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-620380793, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-620380793, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-620380793, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-620380793, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-620380793|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 11:54:44,664 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L787-->L787-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In1723599255 256) 0)) (.cse1 (= (mod ~z$r_buff0_thd3~0_In1723599255 256) 0))) (or (and (= ~z$r_buff0_thd3~0_In1723599255 |P2Thread1of1ForFork2_#t~ite19_Out1723599255|) (or .cse0 .cse1)) (and (not .cse0) (= 0 |P2Thread1of1ForFork2_#t~ite19_Out1723599255|) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1723599255, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1723599255} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1723599255, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1723599255, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out1723599255|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 11:54:44,664 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [769] [769] L788-->L788-2: Formula: (let ((.cse3 (= (mod ~z$w_buff0_used~0_In-991303083 256) 0)) (.cse2 (= 0 (mod ~z$r_buff0_thd3~0_In-991303083 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In-991303083 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd3~0_In-991303083 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite20_Out-991303083| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse1 .cse0) (= ~z$r_buff1_thd3~0_In-991303083 |P2Thread1of1ForFork2_#t~ite20_Out-991303083|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-991303083, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-991303083, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-991303083, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-991303083} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-991303083, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-991303083|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-991303083, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-991303083, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-991303083} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 11:54:44,664 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L788-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite20_32| v_~z$r_buff1_thd3~0_66) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_73 1) v_~__unbuffered_cnt~0_72)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_73} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_31|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_66, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 11:54:44,664 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L768-->L768-2: Formula: (let ((.cse2 (= (mod ~z$w_buff1_used~0_In812094092 256) 0)) (.cse3 (= 0 (mod ~z$r_buff1_thd2~0_In812094092 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In812094092 256))) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In812094092 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork1_#t~ite14_Out812094092|)) (and (or .cse2 .cse3) (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite14_Out812094092| ~z$r_buff1_thd2~0_In812094092)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In812094092, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In812094092, ~z$w_buff1_used~0=~z$w_buff1_used~0_In812094092, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In812094092} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In812094092, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In812094092, ~z$w_buff1_used~0=~z$w_buff1_used~0_In812094092, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out812094092|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In812094092} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 11:54:44,664 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L768-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_38 1) v_~__unbuffered_cnt~0_37) (= |v_P1Thread1of1ForFork1_#t~ite14_28| v_~z$r_buff1_thd2~0_54) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_28|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_54, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_37, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_27|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 11:54:44,664 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L811-1-->L817: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 11:54:44,665 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L817-2-->L817-4: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff1_used~0_In1860596809 256))) (.cse0 (= (mod ~z$r_buff1_thd0~0_In1860596809 256) 0))) (or (and (not .cse0) (= ~z$w_buff1~0_In1860596809 |ULTIMATE.start_main_#t~ite24_Out1860596809|) (not .cse1)) (and (= ~z~0_In1860596809 |ULTIMATE.start_main_#t~ite24_Out1860596809|) (or .cse1 .cse0)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1860596809, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1860596809, ~z$w_buff1~0=~z$w_buff1~0_In1860596809, ~z~0=~z~0_In1860596809} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1860596809, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out1860596809|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1860596809, ~z$w_buff1~0=~z$w_buff1~0_In1860596809, ~z~0=~z~0_In1860596809} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 11:54:44,665 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L817-4-->L818: Formula: (= v_~z~0_21 |v_ULTIMATE.start_main_#t~ite24_9|) InVars {ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_9|} OutVars{ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_8|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_12|, ~z~0=v_~z~0_21} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25, ~z~0] because there is no mapped edge [2019-12-07 11:54:44,665 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L818-->L818-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-204954029 256))) (.cse1 (= (mod ~z$r_buff0_thd0~0_In-204954029 256) 0))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite26_Out-204954029|) (not .cse1)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite26_Out-204954029| ~z$w_buff0_used~0_In-204954029)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-204954029, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-204954029} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-204954029, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-204954029, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-204954029|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 11:54:44,665 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L819-->L819-2: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd0~0_In254189217 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In254189217 256))) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In254189217 256))) (.cse2 (= (mod ~z$r_buff0_thd0~0_In254189217 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite27_Out254189217| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |ULTIMATE.start_main_#t~ite27_Out254189217| ~z$w_buff1_used~0_In254189217) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In254189217, ~z$w_buff0_used~0=~z$w_buff0_used~0_In254189217, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In254189217, ~z$w_buff1_used~0=~z$w_buff1_used~0_In254189217} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In254189217, ~z$w_buff0_used~0=~z$w_buff0_used~0_In254189217, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In254189217, ~z$w_buff1_used~0=~z$w_buff1_used~0_In254189217, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out254189217|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 11:54:44,665 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [780] [780] L820-->L820-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In1153511019 256))) (.cse0 (= (mod ~z$r_buff0_thd0~0_In1153511019 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite28_Out1153511019| ~z$r_buff0_thd0~0_In1153511019)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite28_Out1153511019| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1153511019, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1153511019} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1153511019, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out1153511019|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1153511019} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 11:54:44,666 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L821-->L821-2: Formula: (let ((.cse2 (= (mod ~z$r_buff1_thd0~0_In-469790921 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In-469790921 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In-469790921 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-469790921 256)))) (or (and (= ~z$r_buff1_thd0~0_In-469790921 |ULTIMATE.start_main_#t~ite29_Out-469790921|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |ULTIMATE.start_main_#t~ite29_Out-469790921| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-469790921, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-469790921, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-469790921, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-469790921} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-469790921, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-469790921|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-469790921, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-469790921, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-469790921} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 11:54:44,668 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L833-->L834: Formula: (and (= v_~z$r_buff0_thd0~0_167 v_~z$r_buff0_thd0~0_166) (not (= (mod v_~weak$$choice2~0_39 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_167, ~weak$$choice2~0=v_~weak$$choice2~0_39} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_166, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_10|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_11|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_8|, ~weak$$choice2~0=v_~weak$$choice2~0_39} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 11:54:44,668 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L836-->L4: Formula: (and (= v_~z$mem_tmp~0_13 v_~z~0_134) (= 0 v_~z$flush_delayed~0_22) (= (mod v_~main$tmp_guard1~0_32 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (not (= (mod v_~z$flush_delayed~0_23 256) 0))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_13, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_23} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_13, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_17|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_22, ~z~0=v_~z~0_134, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 11:54:44,669 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_13, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 11:54:44,721 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_57bfe568-ae69-47d7-84bc-665d4a4878cc/bin/uautomizer/witness.graphml [2019-12-07 11:54:44,721 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 11:54:44,722 INFO L168 Benchmark]: Toolchain (without parser) took 146266.03 ms. Allocated memory was 1.0 GB in the beginning and 7.3 GB in the end (delta: 6.3 GB). Free memory was 939.4 MB in the beginning and 3.0 GB in the end (delta: -2.1 GB). Peak memory consumption was 4.2 GB. Max. memory is 11.5 GB. [2019-12-07 11:54:44,722 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 960.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 11:54:44,723 INFO L168 Benchmark]: CACSL2BoogieTranslator took 443.70 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 101.7 MB). Free memory was 939.4 MB in the beginning and 1.1 GB in the end (delta: -129.9 MB). Peak memory consumption was 18.6 MB. Max. memory is 11.5 GB. [2019-12-07 11:54:44,723 INFO L168 Benchmark]: Boogie Procedure Inliner took 52.27 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 11:54:44,723 INFO L168 Benchmark]: Boogie Preprocessor took 33.57 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 11:54:44,723 INFO L168 Benchmark]: RCFGBuilder took 413.29 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 57.3 MB). Peak memory consumption was 57.3 MB. Max. memory is 11.5 GB. [2019-12-07 11:54:44,723 INFO L168 Benchmark]: TraceAbstraction took 145255.65 ms. Allocated memory was 1.1 GB in the beginning and 7.3 GB in the end (delta: 6.2 GB). Free memory was 1.0 GB in the beginning and 3.1 GB in the end (delta: -2.1 GB). Peak memory consumption was 4.1 GB. Max. memory is 11.5 GB. [2019-12-07 11:54:44,724 INFO L168 Benchmark]: Witness Printer took 64.41 ms. Allocated memory is still 7.3 GB. Free memory was 3.1 GB in the beginning and 3.0 GB in the end (delta: 39.0 MB). Peak memory consumption was 39.0 MB. Max. memory is 11.5 GB. [2019-12-07 11:54:44,725 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 960.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 443.70 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 101.7 MB). Free memory was 939.4 MB in the beginning and 1.1 GB in the end (delta: -129.9 MB). Peak memory consumption was 18.6 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 52.27 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 33.57 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 413.29 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 57.3 MB). Peak memory consumption was 57.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 145255.65 ms. Allocated memory was 1.1 GB in the beginning and 7.3 GB in the end (delta: 6.2 GB). Free memory was 1.0 GB in the beginning and 3.1 GB in the end (delta: -2.1 GB). Peak memory consumption was 4.1 GB. Max. memory is 11.5 GB. * Witness Printer took 64.41 ms. Allocated memory is still 7.3 GB. Free memory was 3.1 GB in the beginning and 3.0 GB in the end (delta: 39.0 MB). Peak memory consumption was 39.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 2.9s, 175 ProgramPointsBefore, 95 ProgramPointsAfterwards, 212 TransitionsBefore, 106 TransitionsAfterwards, 17114 CoEnabledTransitionPairs, 7 FixpointIterations, 32 TrivialSequentialCompositions, 46 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 34 ConcurrentYvCompositions, 30 ChoiceCompositions, 5490 VarBasedMoverChecksPositive, 229 VarBasedMoverChecksNegative, 63 SemBasedMoverChecksPositive, 239 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.7s, 0 MoverChecksTotal, 80053 CheckedPairsTotal, 112 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L807] FCALL, FORK 0 pthread_create(&t1961, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L734] 1 z$r_buff1_thd0 = z$r_buff0_thd0 [L735] 1 z$r_buff1_thd1 = z$r_buff0_thd1 [L736] 1 z$r_buff1_thd2 = z$r_buff0_thd2 [L737] 1 z$r_buff1_thd3 = z$r_buff0_thd3 [L738] 1 z$r_buff0_thd1 = (_Bool)1 [L741] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L744] EXPR 1 z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L809] FCALL, FORK 0 pthread_create(&t1962, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L744] 1 z = z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) [L745] 1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used [L746] 1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used [L811] FCALL, FORK 0 pthread_create(&t1963, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L758] 2 __unbuffered_p1_EAX = x [L761] 2 y = 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L764] 2 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L778] 3 __unbuffered_p2_EAX = y [L781] 3 z = 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=2] [L784] 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L765] 2 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used [L766] 2 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used [L767] 2 z$r_buff0_thd2 = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 [L785] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L786] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L787] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L817] 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L818] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L819] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L820] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L821] 0 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L824] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L825] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L826] 0 z$flush_delayed = weak$$choice2 [L827] 0 z$mem_tmp = z VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L828] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L828] 0 z = !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) [L829] EXPR 0 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L829] 0 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) [L830] EXPR 0 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L830] 0 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) [L831] EXPR 0 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L831] 0 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) [L832] EXPR 0 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L832] 0 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L834] EXPR 0 weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L834] 0 z$r_buff1_thd0 = weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L835] 0 main$tmp_guard1 = !(z == 2 && __unbuffered_p1_EAX == 1 && __unbuffered_p2_EAX == 1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 166 locations, 2 error locations. Result: UNSAFE, OverallTime: 145.1s, OverallIterations: 31, TraceHistogramMax: 1, AutomataDifference: 53.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 5629 SDtfs, 9995 SDslu, 27114 SDs, 0 SdLazy, 30294 SolverSat, 925 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 21.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 768 GetRequests, 58 SyntacticMatches, 46 SemanticMatches, 664 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8075 ImplicationChecksByTransitivity, 10.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=245714occurred in iteration=7, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 68.9s AutomataMinimizationTime, 30 MinimizatonAttempts, 463863 StatesRemovedByMinimization, 28 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 3.8s InterpolantComputationTime, 1585 NumberOfCodeBlocks, 1585 NumberOfCodeBlocksAsserted, 31 NumberOfCheckSat, 1487 ConstructedInterpolants, 0 QuantifiedInterpolants, 558136 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 30 InterpolantComputations, 30 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...