./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe008_pso.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_ca89a5d4-d47e-4115-bfe3-564cd367ca70/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_ca89a5d4-d47e-4115-bfe3-564cd367ca70/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_ca89a5d4-d47e-4115-bfe3-564cd367ca70/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_ca89a5d4-d47e-4115-bfe3-564cd367ca70/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe008_pso.oepc.i -s /tmp/vcloud-vcloud-master/worker/run_dir_ca89a5d4-d47e-4115-bfe3-564cd367ca70/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_ca89a5d4-d47e-4115-bfe3-564cd367ca70/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ecaaf2d0226b2c68e6adc16c076be39404c7a86b ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 11:47:19,844 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 11:47:19,846 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 11:47:19,853 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 11:47:19,853 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 11:47:19,854 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 11:47:19,855 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 11:47:19,856 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 11:47:19,858 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 11:47:19,858 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 11:47:19,859 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 11:47:19,860 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 11:47:19,860 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 11:47:19,861 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 11:47:19,861 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 11:47:19,862 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 11:47:19,863 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 11:47:19,863 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 11:47:19,864 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 11:47:19,866 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 11:47:19,867 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 11:47:19,868 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 11:47:19,868 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 11:47:19,869 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 11:47:19,870 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 11:47:19,871 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 11:47:19,871 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 11:47:19,871 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 11:47:19,872 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 11:47:19,872 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 11:47:19,872 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 11:47:19,873 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 11:47:19,873 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 11:47:19,873 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 11:47:19,874 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 11:47:19,874 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 11:47:19,875 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 11:47:19,875 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 11:47:19,875 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 11:47:19,875 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 11:47:19,876 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 11:47:19,876 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_ca89a5d4-d47e-4115-bfe3-564cd367ca70/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 11:47:19,886 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 11:47:19,886 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 11:47:19,887 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 11:47:19,887 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 11:47:19,887 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 11:47:19,887 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 11:47:19,887 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 11:47:19,887 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 11:47:19,888 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 11:47:19,888 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 11:47:19,888 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 11:47:19,888 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 11:47:19,888 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 11:47:19,888 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 11:47:19,888 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 11:47:19,889 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 11:47:19,889 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 11:47:19,889 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 11:47:19,889 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 11:47:19,889 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 11:47:19,889 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 11:47:19,889 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 11:47:19,890 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 11:47:19,890 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 11:47:19,890 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 11:47:19,890 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 11:47:19,890 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 11:47:19,890 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 11:47:19,890 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 11:47:19,890 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_ca89a5d4-d47e-4115-bfe3-564cd367ca70/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ecaaf2d0226b2c68e6adc16c076be39404c7a86b [2019-12-07 11:47:19,990 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 11:47:20,000 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 11:47:20,003 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 11:47:20,004 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 11:47:20,004 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 11:47:20,005 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_ca89a5d4-d47e-4115-bfe3-564cd367ca70/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe008_pso.oepc.i [2019-12-07 11:47:20,046 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_ca89a5d4-d47e-4115-bfe3-564cd367ca70/bin/uautomizer/data/b8a3f2c89/099edc02716941b49c25207d40ca71c0/FLAGb30085755 [2019-12-07 11:47:20,529 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 11:47:20,530 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_ca89a5d4-d47e-4115-bfe3-564cd367ca70/sv-benchmarks/c/pthread-wmm/safe008_pso.oepc.i [2019-12-07 11:47:20,540 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_ca89a5d4-d47e-4115-bfe3-564cd367ca70/bin/uautomizer/data/b8a3f2c89/099edc02716941b49c25207d40ca71c0/FLAGb30085755 [2019-12-07 11:47:21,026 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_ca89a5d4-d47e-4115-bfe3-564cd367ca70/bin/uautomizer/data/b8a3f2c89/099edc02716941b49c25207d40ca71c0 [2019-12-07 11:47:21,029 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 11:47:21,030 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 11:47:21,030 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 11:47:21,030 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 11:47:21,033 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 11:47:21,034 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 11:47:21" (1/1) ... [2019-12-07 11:47:21,035 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7f87f835 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:47:21, skipping insertion in model container [2019-12-07 11:47:21,036 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 11:47:21" (1/1) ... [2019-12-07 11:47:21,041 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 11:47:21,070 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 11:47:21,321 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 11:47:21,329 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 11:47:21,372 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 11:47:21,417 INFO L208 MainTranslator]: Completed translation [2019-12-07 11:47:21,418 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:47:21 WrapperNode [2019-12-07 11:47:21,418 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 11:47:21,418 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 11:47:21,418 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 11:47:21,418 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 11:47:21,424 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:47:21" (1/1) ... [2019-12-07 11:47:21,437 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:47:21" (1/1) ... [2019-12-07 11:47:21,461 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 11:47:21,461 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 11:47:21,461 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 11:47:21,461 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 11:47:21,471 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:47:21" (1/1) ... [2019-12-07 11:47:21,471 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:47:21" (1/1) ... [2019-12-07 11:47:21,475 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:47:21" (1/1) ... [2019-12-07 11:47:21,476 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:47:21" (1/1) ... [2019-12-07 11:47:21,483 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:47:21" (1/1) ... [2019-12-07 11:47:21,486 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:47:21" (1/1) ... [2019-12-07 11:47:21,489 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:47:21" (1/1) ... [2019-12-07 11:47:21,494 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 11:47:21,494 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 11:47:21,494 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 11:47:21,494 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 11:47:21,495 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:47:21" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_ca89a5d4-d47e-4115-bfe3-564cd367ca70/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 11:47:21,546 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 11:47:21,546 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 11:47:21,546 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 11:47:21,546 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 11:47:21,546 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 11:47:21,546 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 11:47:21,546 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 11:47:21,547 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 11:47:21,547 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 11:47:21,547 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 11:47:21,547 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 11:47:21,547 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 11:47:21,547 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 11:47:21,549 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 11:47:21,905 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 11:47:21,906 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 11:47:21,907 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 11:47:21 BoogieIcfgContainer [2019-12-07 11:47:21,907 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 11:47:21,907 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 11:47:21,907 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 11:47:21,909 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 11:47:21,909 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 11:47:21" (1/3) ... [2019-12-07 11:47:21,910 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1a95caad and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 11:47:21, skipping insertion in model container [2019-12-07 11:47:21,910 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:47:21" (2/3) ... [2019-12-07 11:47:21,911 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1a95caad and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 11:47:21, skipping insertion in model container [2019-12-07 11:47:21,911 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 11:47:21" (3/3) ... [2019-12-07 11:47:21,912 INFO L109 eAbstractionObserver]: Analyzing ICFG safe008_pso.oepc.i [2019-12-07 11:47:21,918 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 11:47:21,918 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 11:47:21,923 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 11:47:21,924 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 11:47:21,947 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,947 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,947 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,947 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,947 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,947 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,948 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,948 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,948 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,948 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,948 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,948 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,949 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,949 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,949 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,949 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,949 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,949 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,949 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,949 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,950 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,950 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,950 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,950 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,950 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,950 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,950 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,951 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,951 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,951 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,951 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,951 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,951 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,951 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,952 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,952 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,952 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,952 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,952 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,952 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,952 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,953 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,953 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,953 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,953 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,953 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,953 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,953 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,954 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,954 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,954 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,954 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,954 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,954 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,954 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,954 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,955 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,955 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,955 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,955 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,955 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,955 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,955 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,955 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,956 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,956 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,956 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,956 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,956 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,956 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,957 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,957 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,957 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,957 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,957 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,957 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,957 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,957 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,957 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,958 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,958 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,958 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,958 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,958 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,958 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,958 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,958 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,959 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,959 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,959 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,959 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,959 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,959 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,959 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:47:21,970 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 11:47:21,982 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 11:47:21,983 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 11:47:21,983 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 11:47:21,983 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 11:47:21,983 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 11:47:21,983 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 11:47:21,983 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 11:47:21,983 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 11:47:21,994 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 175 places, 212 transitions [2019-12-07 11:47:21,996 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 175 places, 212 transitions [2019-12-07 11:47:22,050 INFO L134 PetriNetUnfolder]: 47/209 cut-off events. [2019-12-07 11:47:22,050 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 11:47:22,060 INFO L76 FinitePrefix]: Finished finitePrefix Result has 219 conditions, 209 events. 47/209 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 585 event pairs. 9/169 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 11:47:22,074 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 175 places, 212 transitions [2019-12-07 11:47:22,104 INFO L134 PetriNetUnfolder]: 47/209 cut-off events. [2019-12-07 11:47:22,104 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 11:47:22,109 INFO L76 FinitePrefix]: Finished finitePrefix Result has 219 conditions, 209 events. 47/209 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 585 event pairs. 9/169 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 11:47:22,124 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 17114 [2019-12-07 11:47:22,125 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 11:47:24,950 WARN L192 SmtUtils]: Spent 135.00 ms on a formula simplification. DAG size of input: 89 DAG size of output: 87 [2019-12-07 11:47:25,032 INFO L206 etLargeBlockEncoding]: Checked pairs total: 80053 [2019-12-07 11:47:25,032 INFO L214 etLargeBlockEncoding]: Total number of compositions: 112 [2019-12-07 11:47:25,035 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 95 places, 106 transitions [2019-12-07 11:47:40,529 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 115670 states. [2019-12-07 11:47:40,531 INFO L276 IsEmpty]: Start isEmpty. Operand 115670 states. [2019-12-07 11:47:40,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-12-07 11:47:40,535 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:47:40,535 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-12-07 11:47:40,535 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:47:40,539 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:47:40,539 INFO L82 PathProgramCache]: Analyzing trace with hash 846448, now seen corresponding path program 1 times [2019-12-07 11:47:40,545 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:47:40,545 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1277137328] [2019-12-07 11:47:40,545 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:47:40,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:47:40,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:47:40,674 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1277137328] [2019-12-07 11:47:40,674 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:47:40,675 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 11:47:40,675 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1764095854] [2019-12-07 11:47:40,678 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:47:40,678 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:47:40,686 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:47:40,687 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:47:40,688 INFO L87 Difference]: Start difference. First operand 115670 states. Second operand 3 states. [2019-12-07 11:47:41,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:47:41,641 INFO L93 Difference]: Finished difference Result 115182 states and 492924 transitions. [2019-12-07 11:47:41,642 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:47:41,643 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-12-07 11:47:41,643 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:47:42,227 INFO L225 Difference]: With dead ends: 115182 [2019-12-07 11:47:42,228 INFO L226 Difference]: Without dead ends: 112830 [2019-12-07 11:47:42,229 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:47:47,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112830 states. [2019-12-07 11:47:48,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112830 to 112830. [2019-12-07 11:47:48,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112830 states. [2019-12-07 11:47:49,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112830 states to 112830 states and 483320 transitions. [2019-12-07 11:47:49,041 INFO L78 Accepts]: Start accepts. Automaton has 112830 states and 483320 transitions. Word has length 3 [2019-12-07 11:47:49,041 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:47:49,041 INFO L462 AbstractCegarLoop]: Abstraction has 112830 states and 483320 transitions. [2019-12-07 11:47:49,042 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:47:49,042 INFO L276 IsEmpty]: Start isEmpty. Operand 112830 states and 483320 transitions. [2019-12-07 11:47:49,045 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 11:47:49,045 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:47:49,045 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:47:49,046 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:47:49,046 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:47:49,046 INFO L82 PathProgramCache]: Analyzing trace with hash -939919620, now seen corresponding path program 1 times [2019-12-07 11:47:49,046 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:47:49,046 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083250249] [2019-12-07 11:47:49,046 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:47:49,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:47:49,116 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:47:49,116 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083250249] [2019-12-07 11:47:49,116 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:47:49,116 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:47:49,117 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1056859248] [2019-12-07 11:47:49,118 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 11:47:49,118 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:47:49,118 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 11:47:49,118 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 11:47:49,118 INFO L87 Difference]: Start difference. First operand 112830 states and 483320 transitions. Second operand 4 states. [2019-12-07 11:47:50,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:47:50,043 INFO L93 Difference]: Finished difference Result 176302 states and 727515 transitions. [2019-12-07 11:47:50,044 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 11:47:50,044 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 11:47:50,044 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:47:50,513 INFO L225 Difference]: With dead ends: 176302 [2019-12-07 11:47:50,513 INFO L226 Difference]: Without dead ends: 176253 [2019-12-07 11:47:50,514 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:47:54,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176253 states. [2019-12-07 11:47:58,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176253 to 159436. [2019-12-07 11:47:58,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159436 states. [2019-12-07 11:47:59,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159436 states to 159436 states and 665691 transitions. [2019-12-07 11:47:59,313 INFO L78 Accepts]: Start accepts. Automaton has 159436 states and 665691 transitions. Word has length 11 [2019-12-07 11:47:59,313 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:47:59,313 INFO L462 AbstractCegarLoop]: Abstraction has 159436 states and 665691 transitions. [2019-12-07 11:47:59,313 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 11:47:59,313 INFO L276 IsEmpty]: Start isEmpty. Operand 159436 states and 665691 transitions. [2019-12-07 11:47:59,317 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 11:47:59,317 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:47:59,317 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:47:59,317 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:47:59,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:47:59,317 INFO L82 PathProgramCache]: Analyzing trace with hash 670018080, now seen corresponding path program 1 times [2019-12-07 11:47:59,317 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:47:59,318 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [244292886] [2019-12-07 11:47:59,318 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:47:59,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:47:59,364 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:47:59,365 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [244292886] [2019-12-07 11:47:59,365 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:47:59,365 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:47:59,365 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1728740431] [2019-12-07 11:47:59,365 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 11:47:59,365 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:47:59,365 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 11:47:59,366 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 11:47:59,366 INFO L87 Difference]: Start difference. First operand 159436 states and 665691 transitions. Second operand 4 states. [2019-12-07 11:48:00,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:48:00,521 INFO L93 Difference]: Finished difference Result 228428 states and 932375 transitions. [2019-12-07 11:48:00,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 11:48:00,522 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 11:48:00,522 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:48:01,544 INFO L225 Difference]: With dead ends: 228428 [2019-12-07 11:48:01,544 INFO L226 Difference]: Without dead ends: 228365 [2019-12-07 11:48:01,544 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:48:06,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228365 states. [2019-12-07 11:48:11,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228365 to 192396. [2019-12-07 11:48:11,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192396 states. [2019-12-07 11:48:11,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192396 states to 192396 states and 797806 transitions. [2019-12-07 11:48:11,997 INFO L78 Accepts]: Start accepts. Automaton has 192396 states and 797806 transitions. Word has length 13 [2019-12-07 11:48:11,998 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:48:11,998 INFO L462 AbstractCegarLoop]: Abstraction has 192396 states and 797806 transitions. [2019-12-07 11:48:11,998 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 11:48:11,998 INFO L276 IsEmpty]: Start isEmpty. Operand 192396 states and 797806 transitions. [2019-12-07 11:48:12,000 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 11:48:12,000 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:48:12,000 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:48:12,000 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:48:12,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:48:12,001 INFO L82 PathProgramCache]: Analyzing trace with hash -293312110, now seen corresponding path program 1 times [2019-12-07 11:48:12,001 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:48:12,001 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266362880] [2019-12-07 11:48:12,001 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:48:12,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:48:12,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:48:12,053 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1266362880] [2019-12-07 11:48:12,053 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:48:12,053 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:48:12,053 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1841099154] [2019-12-07 11:48:12,053 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 11:48:12,054 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:48:12,054 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 11:48:12,054 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 11:48:12,054 INFO L87 Difference]: Start difference. First operand 192396 states and 797806 transitions. Second operand 4 states. [2019-12-07 11:48:13,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:48:13,621 INFO L93 Difference]: Finished difference Result 240534 states and 988069 transitions. [2019-12-07 11:48:13,621 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 11:48:13,622 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 11:48:13,622 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:48:14,222 INFO L225 Difference]: With dead ends: 240534 [2019-12-07 11:48:14,222 INFO L226 Difference]: Without dead ends: 240534 [2019-12-07 11:48:14,223 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:48:19,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 240534 states. [2019-12-07 11:48:22,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 240534 to 203638. [2019-12-07 11:48:22,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203638 states. [2019-12-07 11:48:23,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203638 states to 203638 states and 844577 transitions. [2019-12-07 11:48:23,201 INFO L78 Accepts]: Start accepts. Automaton has 203638 states and 844577 transitions. Word has length 13 [2019-12-07 11:48:23,201 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:48:23,201 INFO L462 AbstractCegarLoop]: Abstraction has 203638 states and 844577 transitions. [2019-12-07 11:48:23,202 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 11:48:23,202 INFO L276 IsEmpty]: Start isEmpty. Operand 203638 states and 844577 transitions. [2019-12-07 11:48:23,220 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 11:48:23,220 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:48:23,220 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:48:23,220 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:48:23,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:48:23,220 INFO L82 PathProgramCache]: Analyzing trace with hash 1303088540, now seen corresponding path program 1 times [2019-12-07 11:48:23,221 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:48:23,221 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530608247] [2019-12-07 11:48:23,221 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:48:23,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:48:23,287 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:48:23,287 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [530608247] [2019-12-07 11:48:23,287 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:48:23,287 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:48:23,287 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1324447303] [2019-12-07 11:48:23,287 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:48:23,288 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:48:23,288 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:48:23,288 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:48:23,288 INFO L87 Difference]: Start difference. First operand 203638 states and 844577 transitions. Second operand 5 states. [2019-12-07 11:48:27,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:48:27,724 INFO L93 Difference]: Finished difference Result 300567 states and 1220027 transitions. [2019-12-07 11:48:27,725 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 11:48:27,725 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 11:48:27,725 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:48:28,455 INFO L225 Difference]: With dead ends: 300567 [2019-12-07 11:48:28,455 INFO L226 Difference]: Without dead ends: 300504 [2019-12-07 11:48:28,455 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 11:48:34,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 300504 states. [2019-12-07 11:48:37,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 300504 to 216214. [2019-12-07 11:48:37,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 216214 states. [2019-12-07 11:48:38,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 216214 states to 216214 states and 891891 transitions. [2019-12-07 11:48:38,378 INFO L78 Accepts]: Start accepts. Automaton has 216214 states and 891891 transitions. Word has length 19 [2019-12-07 11:48:38,379 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:48:38,379 INFO L462 AbstractCegarLoop]: Abstraction has 216214 states and 891891 transitions. [2019-12-07 11:48:38,379 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:48:38,379 INFO L276 IsEmpty]: Start isEmpty. Operand 216214 states and 891891 transitions. [2019-12-07 11:48:38,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 11:48:38,392 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:48:38,392 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:48:38,392 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:48:38,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:48:38,392 INFO L82 PathProgramCache]: Analyzing trace with hash -2105368373, now seen corresponding path program 1 times [2019-12-07 11:48:38,393 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:48:38,393 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552099170] [2019-12-07 11:48:38,393 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:48:38,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:48:38,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:48:38,432 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [552099170] [2019-12-07 11:48:38,432 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:48:38,432 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:48:38,432 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [912345047] [2019-12-07 11:48:38,432 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:48:38,432 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:48:38,432 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:48:38,433 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:48:38,433 INFO L87 Difference]: Start difference. First operand 216214 states and 891891 transitions. Second operand 5 states. [2019-12-07 11:48:40,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:48:40,669 INFO L93 Difference]: Finished difference Result 326371 states and 1320375 transitions. [2019-12-07 11:48:40,669 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 11:48:40,669 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 11:48:40,670 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:48:41,430 INFO L225 Difference]: With dead ends: 326371 [2019-12-07 11:48:41,430 INFO L226 Difference]: Without dead ends: 326224 [2019-12-07 11:48:41,430 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 11:48:50,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 326224 states. [2019-12-07 11:48:53,699 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 326224 to 227768. [2019-12-07 11:48:53,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 227768 states. [2019-12-07 11:48:54,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227768 states to 227768 states and 938858 transitions. [2019-12-07 11:48:54,368 INFO L78 Accepts]: Start accepts. Automaton has 227768 states and 938858 transitions. Word has length 19 [2019-12-07 11:48:54,368 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:48:54,368 INFO L462 AbstractCegarLoop]: Abstraction has 227768 states and 938858 transitions. [2019-12-07 11:48:54,368 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:48:54,369 INFO L276 IsEmpty]: Start isEmpty. Operand 227768 states and 938858 transitions. [2019-12-07 11:48:54,382 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 11:48:54,382 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:48:54,382 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:48:54,382 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:48:54,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:48:54,383 INFO L82 PathProgramCache]: Analyzing trace with hash 550593021, now seen corresponding path program 1 times [2019-12-07 11:48:54,383 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:48:54,383 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [376531941] [2019-12-07 11:48:54,383 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:48:54,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:48:54,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:48:54,427 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [376531941] [2019-12-07 11:48:54,427 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:48:54,427 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:48:54,427 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1919581420] [2019-12-07 11:48:54,428 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:48:54,428 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:48:54,428 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:48:54,428 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:48:54,428 INFO L87 Difference]: Start difference. First operand 227768 states and 938858 transitions. Second operand 5 states. [2019-12-07 11:48:56,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:48:56,470 INFO L93 Difference]: Finished difference Result 330156 states and 1338658 transitions. [2019-12-07 11:48:56,471 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 11:48:56,471 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 11:48:56,471 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:48:57,852 INFO L225 Difference]: With dead ends: 330156 [2019-12-07 11:48:57,852 INFO L226 Difference]: Without dead ends: 330093 [2019-12-07 11:48:57,852 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 11:49:06,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 330093 states. [2019-12-07 11:49:10,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 330093 to 245714. [2019-12-07 11:49:10,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 245714 states. [2019-12-07 11:49:11,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245714 states to 245714 states and 1011495 transitions. [2019-12-07 11:49:11,134 INFO L78 Accepts]: Start accepts. Automaton has 245714 states and 1011495 transitions. Word has length 19 [2019-12-07 11:49:11,134 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:11,134 INFO L462 AbstractCegarLoop]: Abstraction has 245714 states and 1011495 transitions. [2019-12-07 11:49:11,134 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:49:11,135 INFO L276 IsEmpty]: Start isEmpty. Operand 245714 states and 1011495 transitions. [2019-12-07 11:49:11,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 11:49:11,195 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:11,195 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:11,195 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:11,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:11,195 INFO L82 PathProgramCache]: Analyzing trace with hash 956366417, now seen corresponding path program 1 times [2019-12-07 11:49:11,196 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:11,196 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981423904] [2019-12-07 11:49:11,196 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:11,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:49:11,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:49:11,246 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1981423904] [2019-12-07 11:49:11,246 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:49:11,247 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 11:49:11,247 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1186755103] [2019-12-07 11:49:11,247 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 11:49:11,247 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:49:11,247 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 11:49:11,248 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 11:49:11,248 INFO L87 Difference]: Start difference. First operand 245714 states and 1011495 transitions. Second operand 6 states. [2019-12-07 11:49:13,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:49:13,450 INFO L93 Difference]: Finished difference Result 293437 states and 1194200 transitions. [2019-12-07 11:49:13,451 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 11:49:13,451 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2019-12-07 11:49:13,451 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:49:14,191 INFO L225 Difference]: With dead ends: 293437 [2019-12-07 11:49:14,191 INFO L226 Difference]: Without dead ends: 293290 [2019-12-07 11:49:14,191 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=81, Invalid=191, Unknown=0, NotChecked=0, Total=272 [2019-12-07 11:49:20,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 293290 states. [2019-12-07 11:49:23,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 293290 to 203000. [2019-12-07 11:49:23,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203000 states. [2019-12-07 11:49:24,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203000 states to 203000 states and 839373 transitions. [2019-12-07 11:49:24,221 INFO L78 Accepts]: Start accepts. Automaton has 203000 states and 839373 transitions. Word has length 25 [2019-12-07 11:49:24,221 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:24,221 INFO L462 AbstractCegarLoop]: Abstraction has 203000 states and 839373 transitions. [2019-12-07 11:49:24,221 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 11:49:24,221 INFO L276 IsEmpty]: Start isEmpty. Operand 203000 states and 839373 transitions. [2019-12-07 11:49:24,295 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 11:49:24,295 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:24,295 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:24,295 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:24,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:24,295 INFO L82 PathProgramCache]: Analyzing trace with hash -826573092, now seen corresponding path program 1 times [2019-12-07 11:49:24,295 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:24,295 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1197106486] [2019-12-07 11:49:24,296 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:24,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:49:24,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:49:24,328 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1197106486] [2019-12-07 11:49:24,328 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:49:24,328 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:49:24,328 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [165114216] [2019-12-07 11:49:24,328 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:49:24,328 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:49:24,329 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:49:24,329 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:49:24,329 INFO L87 Difference]: Start difference. First operand 203000 states and 839373 transitions. Second operand 3 states. [2019-12-07 11:49:24,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:49:24,446 INFO L93 Difference]: Finished difference Result 41735 states and 134919 transitions. [2019-12-07 11:49:24,446 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:49:24,446 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 11:49:24,447 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:49:24,506 INFO L225 Difference]: With dead ends: 41735 [2019-12-07 11:49:24,506 INFO L226 Difference]: Without dead ends: 41735 [2019-12-07 11:49:24,506 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:49:24,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41735 states. [2019-12-07 11:49:25,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41735 to 41735. [2019-12-07 11:49:25,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41735 states. [2019-12-07 11:49:25,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41735 states to 41735 states and 134919 transitions. [2019-12-07 11:49:25,139 INFO L78 Accepts]: Start accepts. Automaton has 41735 states and 134919 transitions. Word has length 27 [2019-12-07 11:49:25,139 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:25,139 INFO L462 AbstractCegarLoop]: Abstraction has 41735 states and 134919 transitions. [2019-12-07 11:49:25,139 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:49:25,139 INFO L276 IsEmpty]: Start isEmpty. Operand 41735 states and 134919 transitions. [2019-12-07 11:49:25,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2019-12-07 11:49:25,158 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:25,158 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:25,158 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:25,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:25,158 INFO L82 PathProgramCache]: Analyzing trace with hash -181038669, now seen corresponding path program 1 times [2019-12-07 11:49:25,158 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:25,158 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793925221] [2019-12-07 11:49:25,159 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:25,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:49:25,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:49:25,192 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [793925221] [2019-12-07 11:49:25,192 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:49:25,193 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:49:25,193 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1097376186] [2019-12-07 11:49:25,193 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 11:49:25,193 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:49:25,193 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 11:49:25,194 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 11:49:25,194 INFO L87 Difference]: Start difference. First operand 41735 states and 134919 transitions. Second operand 4 states. [2019-12-07 11:49:25,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:49:25,231 INFO L93 Difference]: Finished difference Result 7949 states and 21432 transitions. [2019-12-07 11:49:25,232 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 11:49:25,232 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 39 [2019-12-07 11:49:25,232 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:49:25,239 INFO L225 Difference]: With dead ends: 7949 [2019-12-07 11:49:25,239 INFO L226 Difference]: Without dead ends: 7949 [2019-12-07 11:49:25,239 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 11:49:25,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7949 states. [2019-12-07 11:49:25,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7949 to 7837. [2019-12-07 11:49:25,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7837 states. [2019-12-07 11:49:25,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7837 states to 7837 states and 21112 transitions. [2019-12-07 11:49:25,327 INFO L78 Accepts]: Start accepts. Automaton has 7837 states and 21112 transitions. Word has length 39 [2019-12-07 11:49:25,327 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:25,327 INFO L462 AbstractCegarLoop]: Abstraction has 7837 states and 21112 transitions. [2019-12-07 11:49:25,328 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 11:49:25,328 INFO L276 IsEmpty]: Start isEmpty. Operand 7837 states and 21112 transitions. [2019-12-07 11:49:25,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 11:49:25,334 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:25,334 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:25,334 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:25,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:25,335 INFO L82 PathProgramCache]: Analyzing trace with hash -118101162, now seen corresponding path program 1 times [2019-12-07 11:49:25,335 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:25,335 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1698891778] [2019-12-07 11:49:25,335 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:25,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:49:25,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:49:25,397 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1698891778] [2019-12-07 11:49:25,397 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:49:25,397 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 11:49:25,397 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1079552999] [2019-12-07 11:49:25,397 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:49:25,398 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:49:25,398 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:49:25,398 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:49:25,398 INFO L87 Difference]: Start difference. First operand 7837 states and 21112 transitions. Second operand 5 states. [2019-12-07 11:49:25,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:49:25,422 INFO L93 Difference]: Finished difference Result 5331 states and 15289 transitions. [2019-12-07 11:49:25,422 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 11:49:25,422 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-12-07 11:49:25,423 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:49:25,427 INFO L225 Difference]: With dead ends: 5331 [2019-12-07 11:49:25,427 INFO L226 Difference]: Without dead ends: 5331 [2019-12-07 11:49:25,427 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:49:25,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5331 states. [2019-12-07 11:49:25,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5331 to 4967. [2019-12-07 11:49:25,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4967 states. [2019-12-07 11:49:25,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4967 states to 4967 states and 14305 transitions. [2019-12-07 11:49:25,486 INFO L78 Accepts]: Start accepts. Automaton has 4967 states and 14305 transitions. Word has length 51 [2019-12-07 11:49:25,487 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:25,487 INFO L462 AbstractCegarLoop]: Abstraction has 4967 states and 14305 transitions. [2019-12-07 11:49:25,487 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:49:25,487 INFO L276 IsEmpty]: Start isEmpty. Operand 4967 states and 14305 transitions. [2019-12-07 11:49:25,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 11:49:25,490 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:25,490 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:25,491 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:25,491 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:25,491 INFO L82 PathProgramCache]: Analyzing trace with hash -1019045356, now seen corresponding path program 1 times [2019-12-07 11:49:25,491 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:25,491 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [117279480] [2019-12-07 11:49:25,491 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:25,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:49:25,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:49:25,551 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [117279480] [2019-12-07 11:49:25,551 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:49:25,551 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 11:49:25,552 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [775570970] [2019-12-07 11:49:25,552 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:49:25,552 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:49:25,552 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:49:25,552 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:49:25,552 INFO L87 Difference]: Start difference. First operand 4967 states and 14305 transitions. Second operand 5 states. [2019-12-07 11:49:25,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:49:25,738 INFO L93 Difference]: Finished difference Result 7558 states and 21570 transitions. [2019-12-07 11:49:25,738 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 11:49:25,738 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 65 [2019-12-07 11:49:25,738 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:49:25,745 INFO L225 Difference]: With dead ends: 7558 [2019-12-07 11:49:25,745 INFO L226 Difference]: Without dead ends: 7558 [2019-12-07 11:49:25,745 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 11:49:25,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7558 states. [2019-12-07 11:49:25,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7558 to 6659. [2019-12-07 11:49:25,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6659 states. [2019-12-07 11:49:25,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6659 states to 6659 states and 19091 transitions. [2019-12-07 11:49:25,826 INFO L78 Accepts]: Start accepts. Automaton has 6659 states and 19091 transitions. Word has length 65 [2019-12-07 11:49:25,827 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:25,827 INFO L462 AbstractCegarLoop]: Abstraction has 6659 states and 19091 transitions. [2019-12-07 11:49:25,827 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:49:25,827 INFO L276 IsEmpty]: Start isEmpty. Operand 6659 states and 19091 transitions. [2019-12-07 11:49:26,145 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 11:49:26,145 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:26,146 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:26,146 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:26,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:26,146 INFO L82 PathProgramCache]: Analyzing trace with hash -613444874, now seen corresponding path program 2 times [2019-12-07 11:49:26,146 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:26,146 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2073945156] [2019-12-07 11:49:26,146 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:26,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:49:26,204 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:49:26,204 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2073945156] [2019-12-07 11:49:26,204 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:49:26,204 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:49:26,204 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1851509804] [2019-12-07 11:49:26,205 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:49:26,205 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:49:26,205 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:49:26,205 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:49:26,205 INFO L87 Difference]: Start difference. First operand 6659 states and 19091 transitions. Second operand 3 states. [2019-12-07 11:49:26,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:49:26,225 INFO L93 Difference]: Finished difference Result 6289 states and 17750 transitions. [2019-12-07 11:49:26,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:49:26,226 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 11:49:26,226 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:49:26,231 INFO L225 Difference]: With dead ends: 6289 [2019-12-07 11:49:26,231 INFO L226 Difference]: Without dead ends: 6289 [2019-12-07 11:49:26,232 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:49:26,250 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6289 states. [2019-12-07 11:49:26,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6289 to 6133. [2019-12-07 11:49:26,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6133 states. [2019-12-07 11:49:26,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6133 states to 6133 states and 17320 transitions. [2019-12-07 11:49:26,303 INFO L78 Accepts]: Start accepts. Automaton has 6133 states and 17320 transitions. Word has length 65 [2019-12-07 11:49:26,303 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:26,303 INFO L462 AbstractCegarLoop]: Abstraction has 6133 states and 17320 transitions. [2019-12-07 11:49:26,303 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:49:26,304 INFO L276 IsEmpty]: Start isEmpty. Operand 6133 states and 17320 transitions. [2019-12-07 11:49:26,308 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 11:49:26,308 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:26,308 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:26,308 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:26,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:26,308 INFO L82 PathProgramCache]: Analyzing trace with hash 223341978, now seen corresponding path program 1 times [2019-12-07 11:49:26,308 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:26,308 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857585670] [2019-12-07 11:49:26,308 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:26,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:49:26,361 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:49:26,361 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1857585670] [2019-12-07 11:49:26,361 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:49:26,361 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 11:49:26,361 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1051329148] [2019-12-07 11:49:26,361 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:49:26,362 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:49:26,362 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:49:26,362 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:49:26,362 INFO L87 Difference]: Start difference. First operand 6133 states and 17320 transitions. Second operand 5 states. [2019-12-07 11:49:26,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:49:26,556 INFO L93 Difference]: Finished difference Result 8712 states and 24399 transitions. [2019-12-07 11:49:26,556 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 11:49:26,556 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 66 [2019-12-07 11:49:26,557 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:49:26,566 INFO L225 Difference]: With dead ends: 8712 [2019-12-07 11:49:26,566 INFO L226 Difference]: Without dead ends: 8712 [2019-12-07 11:49:26,566 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 11:49:26,593 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8712 states. [2019-12-07 11:49:26,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8712 to 6784. [2019-12-07 11:49:26,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6784 states. [2019-12-07 11:49:26,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6784 states to 6784 states and 19209 transitions. [2019-12-07 11:49:26,656 INFO L78 Accepts]: Start accepts. Automaton has 6784 states and 19209 transitions. Word has length 66 [2019-12-07 11:49:26,657 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:26,657 INFO L462 AbstractCegarLoop]: Abstraction has 6784 states and 19209 transitions. [2019-12-07 11:49:26,657 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:49:26,657 INFO L276 IsEmpty]: Start isEmpty. Operand 6784 states and 19209 transitions. [2019-12-07 11:49:26,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 11:49:26,661 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:26,662 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:26,662 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:26,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:26,662 INFO L82 PathProgramCache]: Analyzing trace with hash -446701502, now seen corresponding path program 2 times [2019-12-07 11:49:26,662 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:26,662 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1467739524] [2019-12-07 11:49:26,662 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:26,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:49:26,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:49:26,736 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1467739524] [2019-12-07 11:49:26,736 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:49:26,736 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 11:49:26,736 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2134132490] [2019-12-07 11:49:26,736 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 11:49:26,737 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:49:26,737 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 11:49:26,737 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2019-12-07 11:49:26,737 INFO L87 Difference]: Start difference. First operand 6784 states and 19209 transitions. Second operand 8 states. [2019-12-07 11:49:27,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:49:27,348 INFO L93 Difference]: Finished difference Result 9669 states and 27034 transitions. [2019-12-07 11:49:27,349 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 11:49:27,349 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 66 [2019-12-07 11:49:27,349 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:49:27,356 INFO L225 Difference]: With dead ends: 9669 [2019-12-07 11:49:27,356 INFO L226 Difference]: Without dead ends: 9669 [2019-12-07 11:49:27,357 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 8 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 101 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=119, Invalid=433, Unknown=0, NotChecked=0, Total=552 [2019-12-07 11:49:27,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9669 states. [2019-12-07 11:49:27,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9669 to 7660. [2019-12-07 11:49:27,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7660 states. [2019-12-07 11:49:27,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7660 states to 7660 states and 21627 transitions. [2019-12-07 11:49:27,453 INFO L78 Accepts]: Start accepts. Automaton has 7660 states and 21627 transitions. Word has length 66 [2019-12-07 11:49:27,453 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:27,453 INFO L462 AbstractCegarLoop]: Abstraction has 7660 states and 21627 transitions. [2019-12-07 11:49:27,453 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 11:49:27,453 INFO L276 IsEmpty]: Start isEmpty. Operand 7660 states and 21627 transitions. [2019-12-07 11:49:27,458 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 11:49:27,459 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:27,459 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:27,459 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:27,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:27,459 INFO L82 PathProgramCache]: Analyzing trace with hash -1773910720, now seen corresponding path program 3 times [2019-12-07 11:49:27,459 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:27,459 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1491963683] [2019-12-07 11:49:27,459 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:27,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:49:27,525 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:49:27,525 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1491963683] [2019-12-07 11:49:27,525 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:49:27,525 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 11:49:27,526 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [181285278] [2019-12-07 11:49:27,526 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 11:49:27,526 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:49:27,526 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 11:49:27,526 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 11:49:27,527 INFO L87 Difference]: Start difference. First operand 7660 states and 21627 transitions. Second operand 6 states. [2019-12-07 11:49:27,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:49:27,590 INFO L93 Difference]: Finished difference Result 13602 states and 38369 transitions. [2019-12-07 11:49:27,590 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 11:49:27,590 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 66 [2019-12-07 11:49:27,590 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:49:27,596 INFO L225 Difference]: With dead ends: 13602 [2019-12-07 11:49:27,596 INFO L226 Difference]: Without dead ends: 7201 [2019-12-07 11:49:27,597 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2019-12-07 11:49:27,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7201 states. [2019-12-07 11:49:27,666 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7201 to 7201. [2019-12-07 11:49:27,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7201 states. [2019-12-07 11:49:27,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7201 states to 7201 states and 20274 transitions. [2019-12-07 11:49:27,675 INFO L78 Accepts]: Start accepts. Automaton has 7201 states and 20274 transitions. Word has length 66 [2019-12-07 11:49:27,675 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:27,675 INFO L462 AbstractCegarLoop]: Abstraction has 7201 states and 20274 transitions. [2019-12-07 11:49:27,675 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 11:49:27,675 INFO L276 IsEmpty]: Start isEmpty. Operand 7201 states and 20274 transitions. [2019-12-07 11:49:27,682 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 11:49:27,682 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:27,682 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:27,683 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:27,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:27,683 INFO L82 PathProgramCache]: Analyzing trace with hash 2091502336, now seen corresponding path program 4 times [2019-12-07 11:49:27,683 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:27,683 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [201664827] [2019-12-07 11:49:27,683 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:27,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:49:27,785 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:49:27,785 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [201664827] [2019-12-07 11:49:27,785 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:49:27,785 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 11:49:27,786 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1125275883] [2019-12-07 11:49:27,786 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 11:49:27,786 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:49:27,786 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 11:49:27,786 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2019-12-07 11:49:27,786 INFO L87 Difference]: Start difference. First operand 7201 states and 20274 transitions. Second operand 9 states. [2019-12-07 11:49:28,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:49:28,443 INFO L93 Difference]: Finished difference Result 12094 states and 33864 transitions. [2019-12-07 11:49:28,444 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 11:49:28,444 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 66 [2019-12-07 11:49:28,444 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:49:28,453 INFO L225 Difference]: With dead ends: 12094 [2019-12-07 11:49:28,453 INFO L226 Difference]: Without dead ends: 12094 [2019-12-07 11:49:28,453 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 10 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 69 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=96, Invalid=284, Unknown=0, NotChecked=0, Total=380 [2019-12-07 11:49:28,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12094 states. [2019-12-07 11:49:28,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12094 to 7390. [2019-12-07 11:49:28,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7390 states. [2019-12-07 11:49:28,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7390 states to 7390 states and 20814 transitions. [2019-12-07 11:49:28,561 INFO L78 Accepts]: Start accepts. Automaton has 7390 states and 20814 transitions. Word has length 66 [2019-12-07 11:49:28,561 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:28,562 INFO L462 AbstractCegarLoop]: Abstraction has 7390 states and 20814 transitions. [2019-12-07 11:49:28,562 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 11:49:28,562 INFO L276 IsEmpty]: Start isEmpty. Operand 7390 states and 20814 transitions. [2019-12-07 11:49:28,567 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 11:49:28,567 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:28,567 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:28,567 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:28,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:28,567 INFO L82 PathProgramCache]: Analyzing trace with hash -1951217226, now seen corresponding path program 5 times [2019-12-07 11:49:28,567 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:28,568 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [123083174] [2019-12-07 11:49:28,568 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:28,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:49:28,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:49:28,605 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [123083174] [2019-12-07 11:49:28,605 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:49:28,605 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:49:28,605 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1564197002] [2019-12-07 11:49:28,606 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:49:28,606 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:49:28,606 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:49:28,606 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:49:28,606 INFO L87 Difference]: Start difference. First operand 7390 states and 20814 transitions. Second operand 3 states. [2019-12-07 11:49:28,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:49:28,648 INFO L93 Difference]: Finished difference Result 7389 states and 20812 transitions. [2019-12-07 11:49:28,648 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:49:28,649 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 11:49:28,649 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:49:28,657 INFO L225 Difference]: With dead ends: 7389 [2019-12-07 11:49:28,657 INFO L226 Difference]: Without dead ends: 7389 [2019-12-07 11:49:28,657 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:49:28,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7389 states. [2019-12-07 11:49:28,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7389 to 5129. [2019-12-07 11:49:28,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5129 states. [2019-12-07 11:49:28,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5129 states to 5129 states and 14540 transitions. [2019-12-07 11:49:28,748 INFO L78 Accepts]: Start accepts. Automaton has 5129 states and 14540 transitions. Word has length 66 [2019-12-07 11:49:28,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:28,748 INFO L462 AbstractCegarLoop]: Abstraction has 5129 states and 14540 transitions. [2019-12-07 11:49:28,748 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:49:28,748 INFO L276 IsEmpty]: Start isEmpty. Operand 5129 states and 14540 transitions. [2019-12-07 11:49:28,752 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 11:49:28,752 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:28,752 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:28,752 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:28,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:28,752 INFO L82 PathProgramCache]: Analyzing trace with hash 1374418208, now seen corresponding path program 1 times [2019-12-07 11:49:28,752 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:28,752 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1637560860] [2019-12-07 11:49:28,753 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:28,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:49:28,785 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:49:28,785 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1637560860] [2019-12-07 11:49:28,785 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:49:28,785 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:49:28,785 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1847451311] [2019-12-07 11:49:28,786 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:49:28,786 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:49:28,786 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:49:28,786 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:49:28,786 INFO L87 Difference]: Start difference. First operand 5129 states and 14540 transitions. Second operand 3 states. [2019-12-07 11:49:28,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:49:28,802 INFO L93 Difference]: Finished difference Result 4739 states and 13191 transitions. [2019-12-07 11:49:28,802 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:49:28,803 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 11:49:28,803 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:49:28,806 INFO L225 Difference]: With dead ends: 4739 [2019-12-07 11:49:28,806 INFO L226 Difference]: Without dead ends: 4739 [2019-12-07 11:49:28,807 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:49:28,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4739 states. [2019-12-07 11:49:28,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4739 to 4174. [2019-12-07 11:49:28,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4174 states. [2019-12-07 11:49:28,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4174 states to 4174 states and 11624 transitions. [2019-12-07 11:49:28,859 INFO L78 Accepts]: Start accepts. Automaton has 4174 states and 11624 transitions. Word has length 67 [2019-12-07 11:49:28,859 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:28,859 INFO L462 AbstractCegarLoop]: Abstraction has 4174 states and 11624 transitions. [2019-12-07 11:49:28,859 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:49:28,859 INFO L276 IsEmpty]: Start isEmpty. Operand 4174 states and 11624 transitions. [2019-12-07 11:49:28,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:49:28,862 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:28,862 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:28,862 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:28,863 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:28,863 INFO L82 PathProgramCache]: Analyzing trace with hash -1090372922, now seen corresponding path program 1 times [2019-12-07 11:49:28,863 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:28,863 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [415704307] [2019-12-07 11:49:28,863 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:28,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:49:29,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:49:29,018 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [415704307] [2019-12-07 11:49:29,018 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:49:29,018 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 11:49:29,018 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2142343423] [2019-12-07 11:49:29,019 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 11:49:29,019 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:49:29,019 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 11:49:29,019 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=106, Unknown=0, NotChecked=0, Total=132 [2019-12-07 11:49:29,019 INFO L87 Difference]: Start difference. First operand 4174 states and 11624 transitions. Second operand 12 states. [2019-12-07 11:49:29,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:49:29,288 INFO L93 Difference]: Finished difference Result 7786 states and 21631 transitions. [2019-12-07 11:49:29,288 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 11:49:29,288 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 68 [2019-12-07 11:49:29,288 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:49:29,294 INFO L225 Difference]: With dead ends: 7786 [2019-12-07 11:49:29,294 INFO L226 Difference]: Without dead ends: 7027 [2019-12-07 11:49:29,295 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=72, Invalid=308, Unknown=0, NotChecked=0, Total=380 [2019-12-07 11:49:29,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7027 states. [2019-12-07 11:49:29,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7027 to 5351. [2019-12-07 11:49:29,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5351 states. [2019-12-07 11:49:29,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5351 states to 5351 states and 14810 transitions. [2019-12-07 11:49:29,362 INFO L78 Accepts]: Start accepts. Automaton has 5351 states and 14810 transitions. Word has length 68 [2019-12-07 11:49:29,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:29,362 INFO L462 AbstractCegarLoop]: Abstraction has 5351 states and 14810 transitions. [2019-12-07 11:49:29,363 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 11:49:29,363 INFO L276 IsEmpty]: Start isEmpty. Operand 5351 states and 14810 transitions. [2019-12-07 11:49:29,366 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:49:29,366 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:29,366 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:29,366 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:29,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:29,366 INFO L82 PathProgramCache]: Analyzing trace with hash -1311051616, now seen corresponding path program 2 times [2019-12-07 11:49:29,366 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:29,366 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1860219118] [2019-12-07 11:49:29,366 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:29,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:49:29,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:49:29,569 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1860219118] [2019-12-07 11:49:29,569 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:49:29,569 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 11:49:29,569 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1502435077] [2019-12-07 11:49:29,569 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 11:49:29,570 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:49:29,570 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 11:49:29,570 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=150, Unknown=0, NotChecked=0, Total=182 [2019-12-07 11:49:29,570 INFO L87 Difference]: Start difference. First operand 5351 states and 14810 transitions. Second operand 14 states. [2019-12-07 11:49:30,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:49:30,738 INFO L93 Difference]: Finished difference Result 8219 states and 22676 transitions. [2019-12-07 11:49:30,738 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 11:49:30,738 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 68 [2019-12-07 11:49:30,738 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:49:30,744 INFO L225 Difference]: With dead ends: 8219 [2019-12-07 11:49:30,744 INFO L226 Difference]: Without dead ends: 7712 [2019-12-07 11:49:30,745 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 153 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=202, Invalid=728, Unknown=0, NotChecked=0, Total=930 [2019-12-07 11:49:30,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7712 states. [2019-12-07 11:49:30,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7712 to 5640. [2019-12-07 11:49:30,812 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5640 states. [2019-12-07 11:49:30,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5640 states to 5640 states and 15625 transitions. [2019-12-07 11:49:30,818 INFO L78 Accepts]: Start accepts. Automaton has 5640 states and 15625 transitions. Word has length 68 [2019-12-07 11:49:30,818 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:30,818 INFO L462 AbstractCegarLoop]: Abstraction has 5640 states and 15625 transitions. [2019-12-07 11:49:30,818 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 11:49:30,819 INFO L276 IsEmpty]: Start isEmpty. Operand 5640 states and 15625 transitions. [2019-12-07 11:49:30,822 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:49:30,822 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:30,823 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:30,823 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:30,823 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:30,823 INFO L82 PathProgramCache]: Analyzing trace with hash -526111866, now seen corresponding path program 3 times [2019-12-07 11:49:30,823 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:30,823 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [631628675] [2019-12-07 11:49:30,823 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:30,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:49:31,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:49:31,267 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [631628675] [2019-12-07 11:49:31,267 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:49:31,267 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2019-12-07 11:49:31,268 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1231358261] [2019-12-07 11:49:31,268 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-12-07 11:49:31,268 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:49:31,268 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 11:49:31,268 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=323, Unknown=0, NotChecked=0, Total=380 [2019-12-07 11:49:31,268 INFO L87 Difference]: Start difference. First operand 5640 states and 15625 transitions. Second operand 20 states. [2019-12-07 11:49:33,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:49:33,209 INFO L93 Difference]: Finished difference Result 14157 states and 39309 transitions. [2019-12-07 11:49:33,209 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-12-07 11:49:33,209 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 68 [2019-12-07 11:49:33,209 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:49:33,221 INFO L225 Difference]: With dead ends: 14157 [2019-12-07 11:49:33,221 INFO L226 Difference]: Without dead ends: 14132 [2019-12-07 11:49:33,222 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 1 SyntacticMatches, 5 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 562 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=418, Invalid=2032, Unknown=0, NotChecked=0, Total=2450 [2019-12-07 11:49:33,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14132 states. [2019-12-07 11:49:33,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14132 to 5867. [2019-12-07 11:49:33,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5867 states. [2019-12-07 11:49:33,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5867 states to 5867 states and 16248 transitions. [2019-12-07 11:49:33,330 INFO L78 Accepts]: Start accepts. Automaton has 5867 states and 16248 transitions. Word has length 68 [2019-12-07 11:49:33,330 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:33,330 INFO L462 AbstractCegarLoop]: Abstraction has 5867 states and 16248 transitions. [2019-12-07 11:49:33,330 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-12-07 11:49:33,330 INFO L276 IsEmpty]: Start isEmpty. Operand 5867 states and 16248 transitions. [2019-12-07 11:49:33,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:49:33,334 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:33,334 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:33,334 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:33,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:33,334 INFO L82 PathProgramCache]: Analyzing trace with hash -450226916, now seen corresponding path program 4 times [2019-12-07 11:49:33,335 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:33,335 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775199101] [2019-12-07 11:49:33,335 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:33,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:49:33,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:49:33,535 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775199101] [2019-12-07 11:49:33,535 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:49:33,535 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 11:49:33,535 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1893941770] [2019-12-07 11:49:33,535 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 11:49:33,536 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:49:33,536 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 11:49:33,536 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=177, Unknown=0, NotChecked=0, Total=210 [2019-12-07 11:49:33,536 INFO L87 Difference]: Start difference. First operand 5867 states and 16248 transitions. Second operand 15 states. [2019-12-07 11:49:34,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:49:34,679 INFO L93 Difference]: Finished difference Result 14120 states and 38606 transitions. [2019-12-07 11:49:34,679 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2019-12-07 11:49:34,679 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 68 [2019-12-07 11:49:34,680 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:49:34,695 INFO L225 Difference]: With dead ends: 14120 [2019-12-07 11:49:34,695 INFO L226 Difference]: Without dead ends: 13281 [2019-12-07 11:49:34,697 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 433 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=350, Invalid=1630, Unknown=0, NotChecked=0, Total=1980 [2019-12-07 11:49:34,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13281 states. [2019-12-07 11:49:34,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13281 to 6096. [2019-12-07 11:49:34,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6096 states. [2019-12-07 11:49:34,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6096 states to 6096 states and 16936 transitions. [2019-12-07 11:49:34,802 INFO L78 Accepts]: Start accepts. Automaton has 6096 states and 16936 transitions. Word has length 68 [2019-12-07 11:49:34,802 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:34,802 INFO L462 AbstractCegarLoop]: Abstraction has 6096 states and 16936 transitions. [2019-12-07 11:49:34,802 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 11:49:34,802 INFO L276 IsEmpty]: Start isEmpty. Operand 6096 states and 16936 transitions. [2019-12-07 11:49:34,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:49:34,806 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:34,806 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:34,806 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:34,806 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:34,806 INFO L82 PathProgramCache]: Analyzing trace with hash 932771090, now seen corresponding path program 5 times [2019-12-07 11:49:34,807 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:34,807 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1486339760] [2019-12-07 11:49:34,807 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:34,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:49:35,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:49:35,189 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1486339760] [2019-12-07 11:49:35,189 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:49:35,189 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2019-12-07 11:49:35,189 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [113022887] [2019-12-07 11:49:35,190 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-12-07 11:49:35,190 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:49:35,190 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 11:49:35,190 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2019-12-07 11:49:35,190 INFO L87 Difference]: Start difference. First operand 6096 states and 16936 transitions. Second operand 20 states. [2019-12-07 11:49:40,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:49:40,248 INFO L93 Difference]: Finished difference Result 17746 states and 48604 transitions. [2019-12-07 11:49:40,249 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2019-12-07 11:49:40,249 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 68 [2019-12-07 11:49:40,249 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:49:40,272 INFO L225 Difference]: With dead ends: 17746 [2019-12-07 11:49:40,272 INFO L226 Difference]: Without dead ends: 17381 [2019-12-07 11:49:40,274 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 65 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1004 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=572, Invalid=3210, Unknown=0, NotChecked=0, Total=3782 [2019-12-07 11:49:40,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17381 states. [2019-12-07 11:49:40,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17381 to 6290. [2019-12-07 11:49:40,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6290 states. [2019-12-07 11:49:40,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6290 states to 6290 states and 17488 transitions. [2019-12-07 11:49:40,404 INFO L78 Accepts]: Start accepts. Automaton has 6290 states and 17488 transitions. Word has length 68 [2019-12-07 11:49:40,404 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:40,404 INFO L462 AbstractCegarLoop]: Abstraction has 6290 states and 17488 transitions. [2019-12-07 11:49:40,404 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-12-07 11:49:40,404 INFO L276 IsEmpty]: Start isEmpty. Operand 6290 states and 17488 transitions. [2019-12-07 11:49:40,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:49:40,409 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:40,409 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:40,409 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:40,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:40,409 INFO L82 PathProgramCache]: Analyzing trace with hash -1425961288, now seen corresponding path program 6 times [2019-12-07 11:49:40,409 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:40,409 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341945427] [2019-12-07 11:49:40,409 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:40,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:49:40,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:49:40,860 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1341945427] [2019-12-07 11:49:40,860 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:49:40,860 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2019-12-07 11:49:40,860 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [940453304] [2019-12-07 11:49:40,860 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 11:49:40,860 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:49:40,860 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 11:49:40,860 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=360, Unknown=0, NotChecked=0, Total=420 [2019-12-07 11:49:40,861 INFO L87 Difference]: Start difference. First operand 6290 states and 17488 transitions. Second operand 21 states. [2019-12-07 11:49:45,710 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:49:45,710 INFO L93 Difference]: Finished difference Result 18983 states and 52822 transitions. [2019-12-07 11:49:45,710 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2019-12-07 11:49:45,710 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 68 [2019-12-07 11:49:45,710 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:49:45,745 INFO L225 Difference]: With dead ends: 18983 [2019-12-07 11:49:45,745 INFO L226 Difference]: Without dead ends: 18698 [2019-12-07 11:49:45,747 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 85 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2327 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=943, Invalid=6539, Unknown=0, NotChecked=0, Total=7482 [2019-12-07 11:49:45,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18698 states. [2019-12-07 11:49:45,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18698 to 6454. [2019-12-07 11:49:45,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6454 states. [2019-12-07 11:49:45,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6454 states to 6454 states and 17978 transitions. [2019-12-07 11:49:45,873 INFO L78 Accepts]: Start accepts. Automaton has 6454 states and 17978 transitions. Word has length 68 [2019-12-07 11:49:45,873 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:45,873 INFO L462 AbstractCegarLoop]: Abstraction has 6454 states and 17978 transitions. [2019-12-07 11:49:45,873 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 11:49:45,873 INFO L276 IsEmpty]: Start isEmpty. Operand 6454 states and 17978 transitions. [2019-12-07 11:49:45,877 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:49:45,877 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:45,877 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:45,878 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:45,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:45,878 INFO L82 PathProgramCache]: Analyzing trace with hash 556311610, now seen corresponding path program 7 times [2019-12-07 11:49:45,878 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:45,878 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1865320301] [2019-12-07 11:49:45,878 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:45,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:49:46,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:49:46,010 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1865320301] [2019-12-07 11:49:46,010 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:49:46,010 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 11:49:46,010 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [460735611] [2019-12-07 11:49:46,011 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 11:49:46,011 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:49:46,011 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 11:49:46,011 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=147, Unknown=0, NotChecked=0, Total=182 [2019-12-07 11:49:46,011 INFO L87 Difference]: Start difference. First operand 6454 states and 17978 transitions. Second operand 14 states. [2019-12-07 11:49:46,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:49:46,466 INFO L93 Difference]: Finished difference Result 8998 states and 24785 transitions. [2019-12-07 11:49:46,466 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-12-07 11:49:46,466 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 68 [2019-12-07 11:49:46,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:49:46,473 INFO L225 Difference]: With dead ends: 8998 [2019-12-07 11:49:46,473 INFO L226 Difference]: Without dead ends: 8479 [2019-12-07 11:49:46,474 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 164 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=195, Invalid=735, Unknown=0, NotChecked=0, Total=930 [2019-12-07 11:49:46,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8479 states. [2019-12-07 11:49:46,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8479 to 5476. [2019-12-07 11:49:46,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5476 states. [2019-12-07 11:49:46,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5476 states to 5476 states and 15095 transitions. [2019-12-07 11:49:46,549 INFO L78 Accepts]: Start accepts. Automaton has 5476 states and 15095 transitions. Word has length 68 [2019-12-07 11:49:46,550 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:49:46,550 INFO L462 AbstractCegarLoop]: Abstraction has 5476 states and 15095 transitions. [2019-12-07 11:49:46,550 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 11:49:46,550 INFO L276 IsEmpty]: Start isEmpty. Operand 5476 states and 15095 transitions. [2019-12-07 11:49:46,553 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:49:46,553 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:49:46,553 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:49:46,553 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:49:46,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:49:46,553 INFO L82 PathProgramCache]: Analyzing trace with hash 2056032048, now seen corresponding path program 8 times [2019-12-07 11:49:46,553 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:49:46,554 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598456358] [2019-12-07 11:49:46,554 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:49:46,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 11:49:46,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 11:49:46,620 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 11:49:46,620 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 11:49:46,623 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [827] [827] ULTIMATE.startENTRY-->L807: Formula: (let ((.cse0 (store |v_#valid_66| 0 0))) (and (= 0 v_~__unbuffered_p2_EAX~0_40) (= v_~z$r_buff1_thd0~0_289 0) (= v_~z$r_buff0_thd1~0_194 0) (= v_~z$mem_tmp~0_22 0) (= v_~z$w_buff0~0_192 0) (= 0 v_~weak$$choice0~0_14) (= v_~z~0_201 0) (= 0 v_~__unbuffered_p1_EAX~0_42) (= v_~y~0_14 0) (= v_~main$tmp_guard1~0_48 0) (= |v_#NULL.offset_3| 0) (= v_~z$w_buff0_used~0_745 0) (= v_~z$r_buff0_thd0~0_352 0) (= 0 v_~z$r_buff0_thd3~0_106) (= 0 |v_ULTIMATE.start_main_~#t1967~0.offset_17|) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t1967~0.base_23| 4)) (= v_~z$w_buff1_used~0_381 0) (= v_~main$tmp_guard0~0_23 0) (= v_~z$read_delayed_var~0.offset_7 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1967~0.base_23|)) (= |v_#valid_64| (store .cse0 |v_ULTIMATE.start_main_~#t1967~0.base_23| 1)) (< 0 |v_#StackHeapBarrier_18|) (= v_~z$r_buff1_thd1~0_172 0) (= v_~__unbuffered_cnt~0_156 0) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$read_delayed~0_7 0) (= 0 v_~z$flush_delayed~0_41) (= v_~z$w_buff1~0_171 0) (= 0 v_~x~0_113) (= 0 |v_#NULL.base_3|) (= v_~weak$$choice2~0_111 0) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1967~0.base_23| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1967~0.base_23|) |v_ULTIMATE.start_main_~#t1967~0.offset_17| 0)) |v_#memory_int_23|) (= v_~z$r_buff0_thd2~0_100 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t1967~0.base_23|) (= v_~z$r_buff1_thd2~0_185 0) (= 0 v_~z$r_buff1_thd3~0_186))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_66|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_20|, ULTIMATE.start_main_~#t1967~0.offset=|v_ULTIMATE.start_main_~#t1967~0.offset_17|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_26|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_185, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_34|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_27|, #NULL.offset=|v_#NULL.offset_3|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_24|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_72|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_42|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_24|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_72|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_35|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_352, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_42, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_40, ~z$mem_tmp~0=v_~z$mem_tmp~0_22, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_28|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_41|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_381, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_39|, ~z$flush_delayed~0=v_~z$flush_delayed~0_41, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_74|, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_149|, ULTIMATE.start_main_~#t1969~0.base=|v_ULTIMATE.start_main_~#t1969~0.base_20|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_172, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_106, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_156, ~x~0=v_~x~0_113, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_20|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_32|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_25|, ~z$w_buff1~0=v_~z$w_buff1~0_171, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_48, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_32|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_28|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_260|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_40|, ULTIMATE.start_main_~#t1968~0.offset=|v_ULTIMATE.start_main_~#t1968~0.offset_16|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_74|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_289, ULTIMATE.start_main_~#t1968~0.base=|v_ULTIMATE.start_main_~#t1968~0.base_21|, ~y~0=v_~y~0_14, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_100, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_8|, ULTIMATE.start_main_~#t1967~0.base=|v_ULTIMATE.start_main_~#t1967~0.base_23|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_745, ~z$w_buff0~0=v_~z$w_buff0~0_192, ULTIMATE.start_main_~#t1969~0.offset=|v_ULTIMATE.start_main_~#t1969~0.offset_16|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_186, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_24|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_44|, #NULL.base=|v_#NULL.base_3|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_41|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_149|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_23|, ~z~0=v_~z~0_201, ~weak$$choice2~0=v_~weak$$choice2~0_111, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_194} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_~#t1967~0.offset, ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_~#t1969~0.base, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t1968~0.offset, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ULTIMATE.start_main_~#t1968~0.base, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t1967~0.base, ULTIMATE.start_main_#t~nondet23, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_~#t1969~0.offset, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 11:49:46,623 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L807-1-->L809: Formula: (and (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t1968~0.base_11|)) (= 0 |v_ULTIMATE.start_main_~#t1968~0.offset_10|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1968~0.base_11|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1968~0.base_11| 4)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1968~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1968~0.base_11|) |v_ULTIMATE.start_main_~#t1968~0.offset_10| 1)) |v_#memory_int_15|) (= |v_#valid_35| (store |v_#valid_36| |v_ULTIMATE.start_main_~#t1968~0.base_11| 1)) (not (= 0 |v_ULTIMATE.start_main_~#t1968~0.base_11|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t1968~0.offset=|v_ULTIMATE.start_main_~#t1968~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_~#t1968~0.base=|v_ULTIMATE.start_main_~#t1968~0.base_11|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1968~0.offset, ULTIMATE.start_main_#t~nondet21, #valid, #memory_int, ULTIMATE.start_main_~#t1968~0.base, #length] because there is no mapped edge [2019-12-07 11:49:46,623 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] P0ENTRY-->L4-3: Formula: (and (= v_~z$w_buff0~0_42 v_~z$w_buff1~0_28) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 0)) (= v_P0Thread1of1ForFork0_~arg.offset_6 |v_P0Thread1of1ForFork0_#in~arg.offset_8|) (= |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| (ite (not (and (not (= 0 (mod v_~z$w_buff1_used~0_97 256))) (not (= (mod v_~z$w_buff0_used~0_206 256) 0)))) 1 0)) (= v_~z$w_buff0_used~0_207 v_~z$w_buff1_used~0_97) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~z$w_buff0_used~0_206 1) (= v_P0Thread1of1ForFork0_~arg.base_6 |v_P0Thread1of1ForFork0_#in~arg.base_8|) (= 2 v_~z$w_buff0~0_41)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_207, ~z$w_buff0~0=v_~z$w_buff0~0_42, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_206, ~z$w_buff0~0=v_~z$w_buff0~0_41, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_97, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|, ~z$w_buff1~0=v_~z$w_buff1~0_28, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_6, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_6} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 11:49:46,624 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L809-1-->L811: Formula: (and (= |v_ULTIMATE.start_main_~#t1969~0.offset_10| 0) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1969~0.base_12| 4)) (not (= |v_ULTIMATE.start_main_~#t1969~0.base_12| 0)) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t1969~0.base_12| 1)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1969~0.base_12| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1969~0.base_12|) |v_ULTIMATE.start_main_~#t1969~0.offset_10| 2)) |v_#memory_int_13|) (= (select |v_#valid_32| |v_ULTIMATE.start_main_~#t1969~0.base_12|) 0) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1969~0.base_12|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_~#t1969~0.base=|v_ULTIMATE.start_main_~#t1969~0.base_12|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, ULTIMATE.start_main_~#t1969~0.offset=|v_ULTIMATE.start_main_~#t1969~0.offset_10|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1969~0.base, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_~#t1969~0.offset, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 11:49:46,624 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L745-->L745-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In1370562825 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd1~0_In1370562825 256)))) (or (and (or .cse0 .cse1) (= |P0Thread1of1ForFork0_#t~ite5_Out1370562825| ~z$w_buff0_used~0_In1370562825)) (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite5_Out1370562825| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1370562825, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1370562825} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out1370562825|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1370562825, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1370562825} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 11:49:46,624 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L746-->L746-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd1~0_In-1658359818 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-1658359818 256) 0)) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-1658359818 256))) (.cse3 (= 0 (mod ~z$r_buff1_thd1~0_In-1658359818 256)))) (or (and (= |P0Thread1of1ForFork0_#t~ite6_Out-1658359818| ~z$w_buff1_used~0_In-1658359818) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite6_Out-1658359818| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1658359818, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1658359818, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1658359818, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1658359818} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out-1658359818|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1658359818, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1658359818, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1658359818, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1658359818} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 11:49:46,625 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L747-->L748: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In443588409 256))) (.cse2 (= ~z$r_buff0_thd1~0_In443588409 ~z$r_buff0_thd1~0_Out443588409)) (.cse1 (= (mod ~z$r_buff0_thd1~0_In443588409 256) 0))) (or (and (= 0 ~z$r_buff0_thd1~0_Out443588409) (not .cse0) (not .cse1)) (and .cse0 .cse2) (and .cse2 .cse1))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In443588409, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In443588409} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In443588409, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out443588409|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out443588409} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 11:49:46,625 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L748-->L748-2: Formula: (let ((.cse3 (= (mod ~z$w_buff0_used~0_In677355443 256) 0)) (.cse2 (= (mod ~z$r_buff0_thd1~0_In677355443 256) 0)) (.cse0 (= 0 (mod ~z$r_buff1_thd1~0_In677355443 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In677355443 256) 0))) (or (and (or .cse0 .cse1) (= |P0Thread1of1ForFork0_#t~ite8_Out677355443| ~z$r_buff1_thd1~0_In677355443) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= |P0Thread1of1ForFork0_#t~ite8_Out677355443| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In677355443, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In677355443, ~z$w_buff1_used~0=~z$w_buff1_used~0_In677355443, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In677355443} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In677355443, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out677355443|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In677355443, ~z$w_buff1_used~0=~z$w_buff1_used~0_In677355443, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In677355443} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 11:49:46,625 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L748-2-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_66 1) v_~__unbuffered_cnt~0_65) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_64 |v_P0Thread1of1ForFork0_#t~ite8_42|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_42|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_41|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_64, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_65} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 11:49:46,626 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L764-2-->L764-4: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd2~0_In2098777025 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In2098777025 256)))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork1_#t~ite9_Out2098777025| ~z$w_buff1~0_In2098777025)) (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite9_Out2098777025| ~z~0_In2098777025)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In2098777025, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2098777025, ~z$w_buff1~0=~z$w_buff1~0_In2098777025, ~z~0=~z~0_In2098777025} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out2098777025|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In2098777025, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2098777025, ~z$w_buff1~0=~z$w_buff1~0_In2098777025, ~z~0=~z~0_In2098777025} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-12-07 11:49:46,626 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L764-4-->L765: Formula: (= v_~z~0_33 |v_P1Thread1of1ForFork1_#t~ite9_14|) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_14|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_13|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_19|, ~z~0=v_~z~0_33} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~z~0] because there is no mapped edge [2019-12-07 11:49:46,626 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L765-->L765-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-994691513 256) 0)) (.cse1 (= (mod ~z$r_buff0_thd2~0_In-994691513 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite11_Out-994691513|)) (and (= |P1Thread1of1ForFork1_#t~ite11_Out-994691513| ~z$w_buff0_used~0_In-994691513) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-994691513, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-994691513} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-994691513, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out-994691513|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-994691513} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 11:49:46,627 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L784-2-->L784-4: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In-601406374 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In-601406374 256) 0))) (or (and (= ~z$w_buff1~0_In-601406374 |P2Thread1of1ForFork2_#t~ite15_Out-601406374|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~z~0_In-601406374 |P2Thread1of1ForFork2_#t~ite15_Out-601406374|)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-601406374, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-601406374, ~z$w_buff1~0=~z$w_buff1~0_In-601406374, ~z~0=~z~0_In-601406374} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-601406374|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-601406374, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-601406374, ~z$w_buff1~0=~z$w_buff1~0_In-601406374, ~z~0=~z~0_In-601406374} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 11:49:46,627 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L766-->L766-2: Formula: (let ((.cse1 (= (mod ~z$r_buff1_thd2~0_In1524172528 256) 0)) (.cse0 (= (mod ~z$w_buff1_used~0_In1524172528 256) 0)) (.cse2 (= 0 (mod ~z$r_buff0_thd2~0_In1524172528 256))) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In1524172528 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out1524172528|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$w_buff1_used~0_In1524172528 |P1Thread1of1ForFork1_#t~ite12_Out1524172528|) (or .cse1 .cse0) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1524172528, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1524172528, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1524172528, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1524172528} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1524172528, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1524172528, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1524172528, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out1524172528|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1524172528} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 11:49:46,627 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L767-->L767-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In1451252199 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In1451252199 256)))) (or (and (or .cse0 .cse1) (= ~z$r_buff0_thd2~0_In1451252199 |P1Thread1of1ForFork1_#t~ite13_Out1451252199|)) (and (= 0 |P1Thread1of1ForFork1_#t~ite13_Out1451252199|) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1451252199, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1451252199} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1451252199, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out1451252199|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1451252199} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 11:49:46,627 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L784-4-->L785: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~z~0_45) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, ~z~0=v_~z~0_45, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_13|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~z~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 11:49:46,627 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L785-->L785-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-980421816 256))) (.cse1 (= (mod ~z$r_buff0_thd3~0_In-980421816 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite17_Out-980421816| 0) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite17_Out-980421816| ~z$w_buff0_used~0_In-980421816)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-980421816, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-980421816} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-980421816, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-980421816, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out-980421816|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 11:49:46,628 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L786-->L786-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In1328825479 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In1328825479 256))) (.cse2 (= (mod ~z$r_buff0_thd3~0_In1328825479 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In1328825479 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite18_Out1328825479| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$w_buff1_used~0_In1328825479 |P2Thread1of1ForFork2_#t~ite18_Out1328825479|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1328825479, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1328825479, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1328825479, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1328825479} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1328825479, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1328825479, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1328825479, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1328825479, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out1328825479|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 11:49:46,628 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L787-->L787-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In372275427 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In372275427 256)))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite19_Out372275427|) (not .cse0) (not .cse1)) (and (= |P2Thread1of1ForFork2_#t~ite19_Out372275427| ~z$r_buff0_thd3~0_In372275427) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In372275427, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In372275427} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In372275427, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In372275427, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out372275427|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 11:49:46,628 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [769] [769] L788-->L788-2: Formula: (let ((.cse3 (= (mod ~z$w_buff0_used~0_In1430851311 256) 0)) (.cse2 (= 0 (mod ~z$r_buff0_thd3~0_In1430851311 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In1430851311 256))) (.cse1 (= (mod ~z$r_buff1_thd3~0_In1430851311 256) 0))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite20_Out1430851311|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse0 .cse1) (= ~z$r_buff1_thd3~0_In1430851311 |P2Thread1of1ForFork2_#t~ite20_Out1430851311|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1430851311, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1430851311, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1430851311, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1430851311} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1430851311, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out1430851311|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1430851311, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1430851311, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1430851311} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 11:49:46,628 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L788-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite20_32| v_~z$r_buff1_thd3~0_66) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_73 1) v_~__unbuffered_cnt~0_72)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_73} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_31|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_66, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 11:49:46,628 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L768-->L768-2: Formula: (let ((.cse2 (= 0 (mod ~z$w_buff0_used~0_In-2081649921 256))) (.cse3 (= (mod ~z$r_buff0_thd2~0_In-2081649921 256) 0)) (.cse1 (= 0 (mod ~z$r_buff1_thd2~0_In-2081649921 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In-2081649921 256) 0))) (or (and (= ~z$r_buff1_thd2~0_In-2081649921 |P1Thread1of1ForFork1_#t~ite14_Out-2081649921|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |P1Thread1of1ForFork1_#t~ite14_Out-2081649921|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-2081649921, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-2081649921, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2081649921, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-2081649921} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-2081649921, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-2081649921, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2081649921, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-2081649921|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-2081649921} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 11:49:46,629 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L768-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_38 1) v_~__unbuffered_cnt~0_37) (= |v_P1Thread1of1ForFork1_#t~ite14_28| v_~z$r_buff1_thd2~0_54) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_28|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_54, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_37, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_27|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 11:49:46,629 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L811-1-->L817: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 11:49:46,629 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L817-2-->L817-4: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In-1976259077 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In-1976259077 256) 0))) (or (and (or .cse0 .cse1) (= ~z~0_In-1976259077 |ULTIMATE.start_main_#t~ite24_Out-1976259077|)) (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In-1976259077 |ULTIMATE.start_main_#t~ite24_Out-1976259077|)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1976259077, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1976259077, ~z$w_buff1~0=~z$w_buff1~0_In-1976259077, ~z~0=~z~0_In-1976259077} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1976259077, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-1976259077|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1976259077, ~z$w_buff1~0=~z$w_buff1~0_In-1976259077, ~z~0=~z~0_In-1976259077} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 11:49:46,629 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L817-4-->L818: Formula: (= v_~z~0_21 |v_ULTIMATE.start_main_#t~ite24_9|) InVars {ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_9|} OutVars{ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_8|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_12|, ~z~0=v_~z~0_21} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25, ~z~0] because there is no mapped edge [2019-12-07 11:49:46,629 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L818-->L818-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-1516803933 256))) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1516803933 256)))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite26_Out-1516803933|) (not .cse1)) (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In-1516803933 |ULTIMATE.start_main_#t~ite26_Out-1516803933|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1516803933, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1516803933} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1516803933, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1516803933, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-1516803933|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 11:49:46,629 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L819-->L819-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In-2085835221 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In-2085835221 256))) (.cse3 (= (mod ~z$r_buff0_thd0~0_In-2085835221 256) 0)) (.cse2 (= (mod ~z$w_buff0_used~0_In-2085835221 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite27_Out-2085835221| ~z$w_buff1_used~0_In-2085835221)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2))) (= |ULTIMATE.start_main_#t~ite27_Out-2085835221| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-2085835221, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-2085835221, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-2085835221, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2085835221} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-2085835221, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-2085835221, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-2085835221, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2085835221, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-2085835221|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 11:49:46,630 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [780] [780] L820-->L820-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In1540763738 256) 0)) (.cse0 (= (mod ~z$w_buff0_used~0_In1540763738 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite28_Out1540763738|)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite28_Out1540763738| ~z$r_buff0_thd0~0_In1540763738)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1540763738, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1540763738} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1540763738, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out1540763738|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1540763738} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 11:49:46,630 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L821-->L821-2: Formula: (let ((.cse2 (= (mod ~z$w_buff1_used~0_In929674980 256) 0)) (.cse3 (= 0 (mod ~z$r_buff1_thd0~0_In929674980 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In929674980 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd0~0_In929674980 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite29_Out929674980|)) (and (or .cse2 .cse3) (or .cse1 .cse0) (= ~z$r_buff1_thd0~0_In929674980 |ULTIMATE.start_main_#t~ite29_Out929674980|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In929674980, ~z$w_buff0_used~0=~z$w_buff0_used~0_In929674980, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In929674980, ~z$w_buff1_used~0=~z$w_buff1_used~0_In929674980} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In929674980, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out929674980|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In929674980, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In929674980, ~z$w_buff1_used~0=~z$w_buff1_used~0_In929674980} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 11:49:46,632 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L833-->L834: Formula: (and (= v_~z$r_buff0_thd0~0_167 v_~z$r_buff0_thd0~0_166) (not (= (mod v_~weak$$choice2~0_39 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_167, ~weak$$choice2~0=v_~weak$$choice2~0_39} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_166, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_10|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_11|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_8|, ~weak$$choice2~0=v_~weak$$choice2~0_39} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 11:49:46,633 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L836-->L4: Formula: (and (= v_~z$mem_tmp~0_13 v_~z~0_134) (= 0 v_~z$flush_delayed~0_22) (= (mod v_~main$tmp_guard1~0_32 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (not (= (mod v_~z$flush_delayed~0_23 256) 0))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_13, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_23} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_13, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_17|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_22, ~z~0=v_~z~0_134, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 11:49:46,633 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_13, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 11:49:46,690 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 11:49:46 BasicIcfg [2019-12-07 11:49:46,690 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 11:49:46,691 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 11:49:46,691 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 11:49:46,691 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 11:49:46,691 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 11:47:21" (3/4) ... [2019-12-07 11:49:46,693 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 11:49:46,693 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [827] [827] ULTIMATE.startENTRY-->L807: Formula: (let ((.cse0 (store |v_#valid_66| 0 0))) (and (= 0 v_~__unbuffered_p2_EAX~0_40) (= v_~z$r_buff1_thd0~0_289 0) (= v_~z$r_buff0_thd1~0_194 0) (= v_~z$mem_tmp~0_22 0) (= v_~z$w_buff0~0_192 0) (= 0 v_~weak$$choice0~0_14) (= v_~z~0_201 0) (= 0 v_~__unbuffered_p1_EAX~0_42) (= v_~y~0_14 0) (= v_~main$tmp_guard1~0_48 0) (= |v_#NULL.offset_3| 0) (= v_~z$w_buff0_used~0_745 0) (= v_~z$r_buff0_thd0~0_352 0) (= 0 v_~z$r_buff0_thd3~0_106) (= 0 |v_ULTIMATE.start_main_~#t1967~0.offset_17|) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t1967~0.base_23| 4)) (= v_~z$w_buff1_used~0_381 0) (= v_~main$tmp_guard0~0_23 0) (= v_~z$read_delayed_var~0.offset_7 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1967~0.base_23|)) (= |v_#valid_64| (store .cse0 |v_ULTIMATE.start_main_~#t1967~0.base_23| 1)) (< 0 |v_#StackHeapBarrier_18|) (= v_~z$r_buff1_thd1~0_172 0) (= v_~__unbuffered_cnt~0_156 0) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$read_delayed~0_7 0) (= 0 v_~z$flush_delayed~0_41) (= v_~z$w_buff1~0_171 0) (= 0 v_~x~0_113) (= 0 |v_#NULL.base_3|) (= v_~weak$$choice2~0_111 0) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1967~0.base_23| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1967~0.base_23|) |v_ULTIMATE.start_main_~#t1967~0.offset_17| 0)) |v_#memory_int_23|) (= v_~z$r_buff0_thd2~0_100 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t1967~0.base_23|) (= v_~z$r_buff1_thd2~0_185 0) (= 0 v_~z$r_buff1_thd3~0_186))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_66|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_20|, ULTIMATE.start_main_~#t1967~0.offset=|v_ULTIMATE.start_main_~#t1967~0.offset_17|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_26|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_185, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_34|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_27|, #NULL.offset=|v_#NULL.offset_3|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_24|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_72|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_42|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_24|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_72|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_35|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_352, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_42, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_40, ~z$mem_tmp~0=v_~z$mem_tmp~0_22, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_28|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_41|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_381, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_39|, ~z$flush_delayed~0=v_~z$flush_delayed~0_41, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_74|, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_149|, ULTIMATE.start_main_~#t1969~0.base=|v_ULTIMATE.start_main_~#t1969~0.base_20|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_172, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_106, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_156, ~x~0=v_~x~0_113, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_20|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_32|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_25|, ~z$w_buff1~0=v_~z$w_buff1~0_171, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_48, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_32|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_28|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_260|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_40|, ULTIMATE.start_main_~#t1968~0.offset=|v_ULTIMATE.start_main_~#t1968~0.offset_16|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_74|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_289, ULTIMATE.start_main_~#t1968~0.base=|v_ULTIMATE.start_main_~#t1968~0.base_21|, ~y~0=v_~y~0_14, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_100, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_8|, ULTIMATE.start_main_~#t1967~0.base=|v_ULTIMATE.start_main_~#t1967~0.base_23|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_745, ~z$w_buff0~0=v_~z$w_buff0~0_192, ULTIMATE.start_main_~#t1969~0.offset=|v_ULTIMATE.start_main_~#t1969~0.offset_16|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_186, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_24|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_44|, #NULL.base=|v_#NULL.base_3|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_41|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_149|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_23|, ~z~0=v_~z~0_201, ~weak$$choice2~0=v_~weak$$choice2~0_111, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_194} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_~#t1967~0.offset, ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_~#t1969~0.base, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t1968~0.offset, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ULTIMATE.start_main_~#t1968~0.base, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t1967~0.base, ULTIMATE.start_main_#t~nondet23, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_~#t1969~0.offset, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 11:49:46,694 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L807-1-->L809: Formula: (and (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t1968~0.base_11|)) (= 0 |v_ULTIMATE.start_main_~#t1968~0.offset_10|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1968~0.base_11|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1968~0.base_11| 4)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1968~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1968~0.base_11|) |v_ULTIMATE.start_main_~#t1968~0.offset_10| 1)) |v_#memory_int_15|) (= |v_#valid_35| (store |v_#valid_36| |v_ULTIMATE.start_main_~#t1968~0.base_11| 1)) (not (= 0 |v_ULTIMATE.start_main_~#t1968~0.base_11|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t1968~0.offset=|v_ULTIMATE.start_main_~#t1968~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_~#t1968~0.base=|v_ULTIMATE.start_main_~#t1968~0.base_11|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1968~0.offset, ULTIMATE.start_main_#t~nondet21, #valid, #memory_int, ULTIMATE.start_main_~#t1968~0.base, #length] because there is no mapped edge [2019-12-07 11:49:46,694 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] P0ENTRY-->L4-3: Formula: (and (= v_~z$w_buff0~0_42 v_~z$w_buff1~0_28) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 0)) (= v_P0Thread1of1ForFork0_~arg.offset_6 |v_P0Thread1of1ForFork0_#in~arg.offset_8|) (= |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| (ite (not (and (not (= 0 (mod v_~z$w_buff1_used~0_97 256))) (not (= (mod v_~z$w_buff0_used~0_206 256) 0)))) 1 0)) (= v_~z$w_buff0_used~0_207 v_~z$w_buff1_used~0_97) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~z$w_buff0_used~0_206 1) (= v_P0Thread1of1ForFork0_~arg.base_6 |v_P0Thread1of1ForFork0_#in~arg.base_8|) (= 2 v_~z$w_buff0~0_41)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_207, ~z$w_buff0~0=v_~z$w_buff0~0_42, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_206, ~z$w_buff0~0=v_~z$w_buff0~0_41, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_97, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|, ~z$w_buff1~0=v_~z$w_buff1~0_28, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_6, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_6} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 11:49:46,694 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L809-1-->L811: Formula: (and (= |v_ULTIMATE.start_main_~#t1969~0.offset_10| 0) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1969~0.base_12| 4)) (not (= |v_ULTIMATE.start_main_~#t1969~0.base_12| 0)) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t1969~0.base_12| 1)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1969~0.base_12| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1969~0.base_12|) |v_ULTIMATE.start_main_~#t1969~0.offset_10| 2)) |v_#memory_int_13|) (= (select |v_#valid_32| |v_ULTIMATE.start_main_~#t1969~0.base_12|) 0) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1969~0.base_12|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_~#t1969~0.base=|v_ULTIMATE.start_main_~#t1969~0.base_12|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, ULTIMATE.start_main_~#t1969~0.offset=|v_ULTIMATE.start_main_~#t1969~0.offset_10|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1969~0.base, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_~#t1969~0.offset, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 11:49:46,694 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L745-->L745-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In1370562825 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd1~0_In1370562825 256)))) (or (and (or .cse0 .cse1) (= |P0Thread1of1ForFork0_#t~ite5_Out1370562825| ~z$w_buff0_used~0_In1370562825)) (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite5_Out1370562825| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1370562825, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1370562825} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out1370562825|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1370562825, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1370562825} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 11:49:46,695 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L746-->L746-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd1~0_In-1658359818 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-1658359818 256) 0)) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-1658359818 256))) (.cse3 (= 0 (mod ~z$r_buff1_thd1~0_In-1658359818 256)))) (or (and (= |P0Thread1of1ForFork0_#t~ite6_Out-1658359818| ~z$w_buff1_used~0_In-1658359818) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite6_Out-1658359818| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1658359818, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1658359818, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1658359818, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1658359818} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out-1658359818|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1658359818, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1658359818, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1658359818, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1658359818} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 11:49:46,695 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L747-->L748: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In443588409 256))) (.cse2 (= ~z$r_buff0_thd1~0_In443588409 ~z$r_buff0_thd1~0_Out443588409)) (.cse1 (= (mod ~z$r_buff0_thd1~0_In443588409 256) 0))) (or (and (= 0 ~z$r_buff0_thd1~0_Out443588409) (not .cse0) (not .cse1)) (and .cse0 .cse2) (and .cse2 .cse1))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In443588409, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In443588409} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In443588409, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out443588409|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out443588409} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 11:49:46,695 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L748-->L748-2: Formula: (let ((.cse3 (= (mod ~z$w_buff0_used~0_In677355443 256) 0)) (.cse2 (= (mod ~z$r_buff0_thd1~0_In677355443 256) 0)) (.cse0 (= 0 (mod ~z$r_buff1_thd1~0_In677355443 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In677355443 256) 0))) (or (and (or .cse0 .cse1) (= |P0Thread1of1ForFork0_#t~ite8_Out677355443| ~z$r_buff1_thd1~0_In677355443) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= |P0Thread1of1ForFork0_#t~ite8_Out677355443| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In677355443, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In677355443, ~z$w_buff1_used~0=~z$w_buff1_used~0_In677355443, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In677355443} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In677355443, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out677355443|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In677355443, ~z$w_buff1_used~0=~z$w_buff1_used~0_In677355443, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In677355443} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 11:49:46,695 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L748-2-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_66 1) v_~__unbuffered_cnt~0_65) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_64 |v_P0Thread1of1ForFork0_#t~ite8_42|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_42|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_41|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_64, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_65} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 11:49:46,696 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L764-2-->L764-4: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd2~0_In2098777025 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In2098777025 256)))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork1_#t~ite9_Out2098777025| ~z$w_buff1~0_In2098777025)) (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite9_Out2098777025| ~z~0_In2098777025)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In2098777025, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2098777025, ~z$w_buff1~0=~z$w_buff1~0_In2098777025, ~z~0=~z~0_In2098777025} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out2098777025|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In2098777025, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2098777025, ~z$w_buff1~0=~z$w_buff1~0_In2098777025, ~z~0=~z~0_In2098777025} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-12-07 11:49:46,696 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L764-4-->L765: Formula: (= v_~z~0_33 |v_P1Thread1of1ForFork1_#t~ite9_14|) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_14|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_13|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_19|, ~z~0=v_~z~0_33} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~z~0] because there is no mapped edge [2019-12-07 11:49:46,696 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L765-->L765-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-994691513 256) 0)) (.cse1 (= (mod ~z$r_buff0_thd2~0_In-994691513 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite11_Out-994691513|)) (and (= |P1Thread1of1ForFork1_#t~ite11_Out-994691513| ~z$w_buff0_used~0_In-994691513) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-994691513, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-994691513} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-994691513, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out-994691513|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-994691513} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 11:49:46,697 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L784-2-->L784-4: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In-601406374 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In-601406374 256) 0))) (or (and (= ~z$w_buff1~0_In-601406374 |P2Thread1of1ForFork2_#t~ite15_Out-601406374|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~z~0_In-601406374 |P2Thread1of1ForFork2_#t~ite15_Out-601406374|)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-601406374, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-601406374, ~z$w_buff1~0=~z$w_buff1~0_In-601406374, ~z~0=~z~0_In-601406374} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-601406374|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-601406374, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-601406374, ~z$w_buff1~0=~z$w_buff1~0_In-601406374, ~z~0=~z~0_In-601406374} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 11:49:46,697 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L766-->L766-2: Formula: (let ((.cse1 (= (mod ~z$r_buff1_thd2~0_In1524172528 256) 0)) (.cse0 (= (mod ~z$w_buff1_used~0_In1524172528 256) 0)) (.cse2 (= 0 (mod ~z$r_buff0_thd2~0_In1524172528 256))) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In1524172528 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out1524172528|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$w_buff1_used~0_In1524172528 |P1Thread1of1ForFork1_#t~ite12_Out1524172528|) (or .cse1 .cse0) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1524172528, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1524172528, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1524172528, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1524172528} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1524172528, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1524172528, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1524172528, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out1524172528|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1524172528} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 11:49:46,697 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L767-->L767-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In1451252199 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In1451252199 256)))) (or (and (or .cse0 .cse1) (= ~z$r_buff0_thd2~0_In1451252199 |P1Thread1of1ForFork1_#t~ite13_Out1451252199|)) (and (= 0 |P1Thread1of1ForFork1_#t~ite13_Out1451252199|) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1451252199, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1451252199} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1451252199, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out1451252199|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1451252199} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 11:49:46,697 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L784-4-->L785: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~z~0_45) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, ~z~0=v_~z~0_45, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_13|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~z~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 11:49:46,697 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L785-->L785-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-980421816 256))) (.cse1 (= (mod ~z$r_buff0_thd3~0_In-980421816 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite17_Out-980421816| 0) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite17_Out-980421816| ~z$w_buff0_used~0_In-980421816)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-980421816, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-980421816} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-980421816, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-980421816, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out-980421816|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 11:49:46,698 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L786-->L786-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In1328825479 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In1328825479 256))) (.cse2 (= (mod ~z$r_buff0_thd3~0_In1328825479 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In1328825479 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite18_Out1328825479| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$w_buff1_used~0_In1328825479 |P2Thread1of1ForFork2_#t~ite18_Out1328825479|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1328825479, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1328825479, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1328825479, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1328825479} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1328825479, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1328825479, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1328825479, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1328825479, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out1328825479|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 11:49:46,698 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L787-->L787-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In372275427 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In372275427 256)))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite19_Out372275427|) (not .cse0) (not .cse1)) (and (= |P2Thread1of1ForFork2_#t~ite19_Out372275427| ~z$r_buff0_thd3~0_In372275427) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In372275427, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In372275427} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In372275427, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In372275427, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out372275427|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 11:49:46,698 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [769] [769] L788-->L788-2: Formula: (let ((.cse3 (= (mod ~z$w_buff0_used~0_In1430851311 256) 0)) (.cse2 (= 0 (mod ~z$r_buff0_thd3~0_In1430851311 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In1430851311 256))) (.cse1 (= (mod ~z$r_buff1_thd3~0_In1430851311 256) 0))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite20_Out1430851311|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse0 .cse1) (= ~z$r_buff1_thd3~0_In1430851311 |P2Thread1of1ForFork2_#t~ite20_Out1430851311|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1430851311, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1430851311, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1430851311, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1430851311} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1430851311, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out1430851311|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1430851311, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1430851311, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1430851311} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 11:49:46,698 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L788-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite20_32| v_~z$r_buff1_thd3~0_66) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_73 1) v_~__unbuffered_cnt~0_72)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_73} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_31|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_66, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 11:49:46,698 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L768-->L768-2: Formula: (let ((.cse2 (= 0 (mod ~z$w_buff0_used~0_In-2081649921 256))) (.cse3 (= (mod ~z$r_buff0_thd2~0_In-2081649921 256) 0)) (.cse1 (= 0 (mod ~z$r_buff1_thd2~0_In-2081649921 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In-2081649921 256) 0))) (or (and (= ~z$r_buff1_thd2~0_In-2081649921 |P1Thread1of1ForFork1_#t~ite14_Out-2081649921|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |P1Thread1of1ForFork1_#t~ite14_Out-2081649921|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-2081649921, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-2081649921, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2081649921, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-2081649921} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-2081649921, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-2081649921, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2081649921, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-2081649921|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-2081649921} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 11:49:46,698 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L768-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_38 1) v_~__unbuffered_cnt~0_37) (= |v_P1Thread1of1ForFork1_#t~ite14_28| v_~z$r_buff1_thd2~0_54) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_28|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_54, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_37, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_27|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 11:49:46,698 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L811-1-->L817: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 11:49:46,699 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L817-2-->L817-4: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In-1976259077 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In-1976259077 256) 0))) (or (and (or .cse0 .cse1) (= ~z~0_In-1976259077 |ULTIMATE.start_main_#t~ite24_Out-1976259077|)) (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In-1976259077 |ULTIMATE.start_main_#t~ite24_Out-1976259077|)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1976259077, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1976259077, ~z$w_buff1~0=~z$w_buff1~0_In-1976259077, ~z~0=~z~0_In-1976259077} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1976259077, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-1976259077|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1976259077, ~z$w_buff1~0=~z$w_buff1~0_In-1976259077, ~z~0=~z~0_In-1976259077} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 11:49:46,699 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L817-4-->L818: Formula: (= v_~z~0_21 |v_ULTIMATE.start_main_#t~ite24_9|) InVars {ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_9|} OutVars{ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_8|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_12|, ~z~0=v_~z~0_21} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25, ~z~0] because there is no mapped edge [2019-12-07 11:49:46,699 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L818-->L818-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-1516803933 256))) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1516803933 256)))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite26_Out-1516803933|) (not .cse1)) (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In-1516803933 |ULTIMATE.start_main_#t~ite26_Out-1516803933|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1516803933, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1516803933} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1516803933, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1516803933, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-1516803933|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 11:49:46,699 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L819-->L819-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In-2085835221 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In-2085835221 256))) (.cse3 (= (mod ~z$r_buff0_thd0~0_In-2085835221 256) 0)) (.cse2 (= (mod ~z$w_buff0_used~0_In-2085835221 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite27_Out-2085835221| ~z$w_buff1_used~0_In-2085835221)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2))) (= |ULTIMATE.start_main_#t~ite27_Out-2085835221| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-2085835221, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-2085835221, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-2085835221, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2085835221} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-2085835221, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-2085835221, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-2085835221, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2085835221, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-2085835221|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 11:49:46,699 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [780] [780] L820-->L820-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd0~0_In1540763738 256) 0)) (.cse0 (= (mod ~z$w_buff0_used~0_In1540763738 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite28_Out1540763738|)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite28_Out1540763738| ~z$r_buff0_thd0~0_In1540763738)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1540763738, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1540763738} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1540763738, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out1540763738|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1540763738} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 11:49:46,700 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L821-->L821-2: Formula: (let ((.cse2 (= (mod ~z$w_buff1_used~0_In929674980 256) 0)) (.cse3 (= 0 (mod ~z$r_buff1_thd0~0_In929674980 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In929674980 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd0~0_In929674980 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite29_Out929674980|)) (and (or .cse2 .cse3) (or .cse1 .cse0) (= ~z$r_buff1_thd0~0_In929674980 |ULTIMATE.start_main_#t~ite29_Out929674980|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In929674980, ~z$w_buff0_used~0=~z$w_buff0_used~0_In929674980, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In929674980, ~z$w_buff1_used~0=~z$w_buff1_used~0_In929674980} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In929674980, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out929674980|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In929674980, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In929674980, ~z$w_buff1_used~0=~z$w_buff1_used~0_In929674980} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 11:49:46,702 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L833-->L834: Formula: (and (= v_~z$r_buff0_thd0~0_167 v_~z$r_buff0_thd0~0_166) (not (= (mod v_~weak$$choice2~0_39 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_167, ~weak$$choice2~0=v_~weak$$choice2~0_39} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_166, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_10|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_11|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_8|, ~weak$$choice2~0=v_~weak$$choice2~0_39} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 11:49:46,703 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L836-->L4: Formula: (and (= v_~z$mem_tmp~0_13 v_~z~0_134) (= 0 v_~z$flush_delayed~0_22) (= (mod v_~main$tmp_guard1~0_32 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (not (= (mod v_~z$flush_delayed~0_23 256) 0))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_13, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_23} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_13, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_17|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_22, ~z~0=v_~z~0_134, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 11:49:46,703 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_13, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 11:49:46,758 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_ca89a5d4-d47e-4115-bfe3-564cd367ca70/bin/uautomizer/witness.graphml [2019-12-07 11:49:46,758 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 11:49:46,759 INFO L168 Benchmark]: Toolchain (without parser) took 145729.35 ms. Allocated memory was 1.0 GB in the beginning and 6.8 GB in the end (delta: 5.8 GB). Free memory was 939.7 MB in the beginning and 6.0 GB in the end (delta: -5.1 GB). Peak memory consumption was 701.7 MB. Max. memory is 11.5 GB. [2019-12-07 11:49:46,759 INFO L168 Benchmark]: CDTParser took 0.20 ms. Allocated memory is still 1.0 GB. Free memory is still 961.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 11:49:46,759 INFO L168 Benchmark]: CACSL2BoogieTranslator took 387.55 ms. Allocated memory is still 1.0 GB. Free memory was 939.7 MB in the beginning and 979.1 MB in the end (delta: -39.5 MB). Peak memory consumption was 17.8 MB. Max. memory is 11.5 GB. [2019-12-07 11:49:46,759 INFO L168 Benchmark]: Boogie Procedure Inliner took 42.88 ms. Allocated memory is still 1.0 GB. Free memory was 979.1 MB in the beginning and 973.8 MB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 11:49:46,760 INFO L168 Benchmark]: Boogie Preprocessor took 32.82 ms. Allocated memory is still 1.0 GB. Free memory is still 973.8 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 11:49:46,760 INFO L168 Benchmark]: RCFGBuilder took 412.44 ms. Allocated memory is still 1.0 GB. Free memory was 973.8 MB in the beginning and 919.1 MB in the end (delta: 54.6 MB). Peak memory consumption was 54.6 MB. Max. memory is 11.5 GB. [2019-12-07 11:49:46,760 INFO L168 Benchmark]: TraceAbstraction took 144783.29 ms. Allocated memory was 1.0 GB in the beginning and 6.8 GB in the end (delta: 5.8 GB). Free memory was 919.1 MB in the beginning and 6.0 GB in the end (delta: -5.1 GB). Peak memory consumption was 671.6 MB. Max. memory is 11.5 GB. [2019-12-07 11:49:46,760 INFO L168 Benchmark]: Witness Printer took 67.08 ms. Allocated memory is still 6.8 GB. Free memory was 6.0 GB in the beginning and 6.0 GB in the end (delta: 9.5 MB). Peak memory consumption was 9.5 MB. Max. memory is 11.5 GB. [2019-12-07 11:49:46,762 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20 ms. Allocated memory is still 1.0 GB. Free memory is still 961.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 387.55 ms. Allocated memory is still 1.0 GB. Free memory was 939.7 MB in the beginning and 979.1 MB in the end (delta: -39.5 MB). Peak memory consumption was 17.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 42.88 ms. Allocated memory is still 1.0 GB. Free memory was 979.1 MB in the beginning and 973.8 MB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 32.82 ms. Allocated memory is still 1.0 GB. Free memory is still 973.8 MB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 412.44 ms. Allocated memory is still 1.0 GB. Free memory was 973.8 MB in the beginning and 919.1 MB in the end (delta: 54.6 MB). Peak memory consumption was 54.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 144783.29 ms. Allocated memory was 1.0 GB in the beginning and 6.8 GB in the end (delta: 5.8 GB). Free memory was 919.1 MB in the beginning and 6.0 GB in the end (delta: -5.1 GB). Peak memory consumption was 671.6 MB. Max. memory is 11.5 GB. * Witness Printer took 67.08 ms. Allocated memory is still 6.8 GB. Free memory was 6.0 GB in the beginning and 6.0 GB in the end (delta: 9.5 MB). Peak memory consumption was 9.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.0s, 175 ProgramPointsBefore, 95 ProgramPointsAfterwards, 212 TransitionsBefore, 106 TransitionsAfterwards, 17114 CoEnabledTransitionPairs, 7 FixpointIterations, 32 TrivialSequentialCompositions, 46 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 34 ConcurrentYvCompositions, 30 ChoiceCompositions, 5490 VarBasedMoverChecksPositive, 229 VarBasedMoverChecksNegative, 63 SemBasedMoverChecksPositive, 239 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.8s, 0 MoverChecksTotal, 80053 CheckedPairsTotal, 112 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L807] FCALL, FORK 0 pthread_create(&t1967, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L734] 1 z$r_buff1_thd0 = z$r_buff0_thd0 [L735] 1 z$r_buff1_thd1 = z$r_buff0_thd1 [L736] 1 z$r_buff1_thd2 = z$r_buff0_thd2 [L737] 1 z$r_buff1_thd3 = z$r_buff0_thd3 [L738] 1 z$r_buff0_thd1 = (_Bool)1 [L741] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L744] EXPR 1 z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L809] FCALL, FORK 0 pthread_create(&t1968, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L744] 1 z = z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) [L745] 1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used [L746] 1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used [L811] FCALL, FORK 0 pthread_create(&t1969, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L758] 2 __unbuffered_p1_EAX = x [L761] 2 y = 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L764] 2 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L778] 3 __unbuffered_p2_EAX = y [L781] 3 z = 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=2] [L784] 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L765] 2 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used [L766] 2 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used [L767] 2 z$r_buff0_thd2 = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 [L785] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L786] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L787] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L817] 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L818] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L819] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L820] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L821] 0 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L824] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L825] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L826] 0 z$flush_delayed = weak$$choice2 [L827] 0 z$mem_tmp = z VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L828] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L828] 0 z = !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) [L829] EXPR 0 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L829] 0 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) [L830] EXPR 0 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L830] 0 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) [L831] EXPR 0 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L831] 0 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) [L832] EXPR 0 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L832] 0 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L834] EXPR 0 weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L834] 0 z$r_buff1_thd0 = weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L835] 0 main$tmp_guard1 = !(z == 2 && __unbuffered_p1_EAX == 1 && __unbuffered_p2_EAX == 1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 166 locations, 2 error locations. Result: UNSAFE, OverallTime: 144.6s, OverallIterations: 27, TraceHistogramMax: 1, AutomataDifference: 38.9s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 4810 SDtfs, 6341 SDslu, 18617 SDs, 0 SdLazy, 18371 SolverSat, 517 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 12.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 507 GetRequests, 55 SyntacticMatches, 29 SemanticMatches, 423 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4921 ImplicationChecksByTransitivity, 5.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=245714occurred in iteration=7, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 83.3s AutomataMinimizationTime, 26 MinimizatonAttempts, 505630 StatesRemovedByMinimization, 23 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 2.5s InterpolantComputationTime, 1310 NumberOfCodeBlocks, 1310 NumberOfCodeBlocksAsserted, 27 NumberOfCheckSat, 1216 ConstructedInterpolants, 0 QuantifiedInterpolants, 389982 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 26 InterpolantComputations, 26 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...