./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe008_pso.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_e0ce35dc-272f-4007-a337-749b3e0d3967/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_e0ce35dc-272f-4007-a337-749b3e0d3967/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_e0ce35dc-272f-4007-a337-749b3e0d3967/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_e0ce35dc-272f-4007-a337-749b3e0d3967/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe008_pso.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_e0ce35dc-272f-4007-a337-749b3e0d3967/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_e0ce35dc-272f-4007-a337-749b3e0d3967/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash f0dece396cd7469c799cbf4d57488b0c57de53d3 ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 16:23:12,289 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 16:23:12,291 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 16:23:12,299 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 16:23:12,299 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 16:23:12,300 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 16:23:12,301 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 16:23:12,302 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 16:23:12,304 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 16:23:12,304 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 16:23:12,305 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 16:23:12,306 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 16:23:12,306 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 16:23:12,307 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 16:23:12,307 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 16:23:12,308 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 16:23:12,309 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 16:23:12,310 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 16:23:12,311 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 16:23:12,313 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 16:23:12,314 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 16:23:12,315 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 16:23:12,316 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 16:23:12,316 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 16:23:12,318 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 16:23:12,318 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 16:23:12,318 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 16:23:12,319 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 16:23:12,319 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 16:23:12,320 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 16:23:12,320 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 16:23:12,321 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 16:23:12,321 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 16:23:12,321 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 16:23:12,322 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 16:23:12,322 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 16:23:12,323 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 16:23:12,323 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 16:23:12,323 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 16:23:12,324 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 16:23:12,324 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 16:23:12,325 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_e0ce35dc-272f-4007-a337-749b3e0d3967/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 16:23:12,336 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 16:23:12,336 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 16:23:12,337 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 16:23:12,337 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 16:23:12,338 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 16:23:12,338 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 16:23:12,338 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 16:23:12,338 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 16:23:12,338 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 16:23:12,338 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 16:23:12,338 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 16:23:12,338 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 16:23:12,339 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 16:23:12,339 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 16:23:12,339 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 16:23:12,339 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 16:23:12,339 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 16:23:12,339 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 16:23:12,340 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 16:23:12,340 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 16:23:12,340 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 16:23:12,340 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 16:23:12,340 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 16:23:12,340 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 16:23:12,340 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 16:23:12,340 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 16:23:12,341 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 16:23:12,341 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 16:23:12,341 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 16:23:12,341 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_e0ce35dc-272f-4007-a337-749b3e0d3967/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> f0dece396cd7469c799cbf4d57488b0c57de53d3 [2019-12-07 16:23:12,459 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 16:23:12,467 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 16:23:12,469 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 16:23:12,470 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 16:23:12,471 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 16:23:12,471 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_e0ce35dc-272f-4007-a337-749b3e0d3967/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe008_pso.opt.i [2019-12-07 16:23:12,509 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_e0ce35dc-272f-4007-a337-749b3e0d3967/bin/uautomizer/data/4ec9bdad5/063a2726fe034a34a0e847aef8d4675f/FLAG067127c62 [2019-12-07 16:23:12,909 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 16:23:12,909 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_e0ce35dc-272f-4007-a337-749b3e0d3967/sv-benchmarks/c/pthread-wmm/safe008_pso.opt.i [2019-12-07 16:23:12,919 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_e0ce35dc-272f-4007-a337-749b3e0d3967/bin/uautomizer/data/4ec9bdad5/063a2726fe034a34a0e847aef8d4675f/FLAG067127c62 [2019-12-07 16:23:12,928 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_e0ce35dc-272f-4007-a337-749b3e0d3967/bin/uautomizer/data/4ec9bdad5/063a2726fe034a34a0e847aef8d4675f [2019-12-07 16:23:12,930 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 16:23:12,930 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 16:23:12,931 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 16:23:12,931 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 16:23:12,934 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 16:23:12,935 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 04:23:12" (1/1) ... [2019-12-07 16:23:12,937 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3f8fae9c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:23:12, skipping insertion in model container [2019-12-07 16:23:12,937 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 04:23:12" (1/1) ... [2019-12-07 16:23:12,942 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 16:23:12,975 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 16:23:13,226 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 16:23:13,234 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 16:23:13,278 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 16:23:13,322 INFO L208 MainTranslator]: Completed translation [2019-12-07 16:23:13,323 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:23:13 WrapperNode [2019-12-07 16:23:13,323 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 16:23:13,323 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 16:23:13,324 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 16:23:13,324 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 16:23:13,329 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:23:13" (1/1) ... [2019-12-07 16:23:13,344 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:23:13" (1/1) ... [2019-12-07 16:23:13,366 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 16:23:13,366 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 16:23:13,366 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 16:23:13,366 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 16:23:13,373 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:23:13" (1/1) ... [2019-12-07 16:23:13,373 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:23:13" (1/1) ... [2019-12-07 16:23:13,376 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:23:13" (1/1) ... [2019-12-07 16:23:13,377 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:23:13" (1/1) ... [2019-12-07 16:23:13,383 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:23:13" (1/1) ... [2019-12-07 16:23:13,386 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:23:13" (1/1) ... [2019-12-07 16:23:13,389 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:23:13" (1/1) ... [2019-12-07 16:23:13,392 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 16:23:13,392 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 16:23:13,392 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 16:23:13,392 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 16:23:13,393 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:23:13" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_e0ce35dc-272f-4007-a337-749b3e0d3967/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 16:23:13,432 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 16:23:13,432 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 16:23:13,433 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 16:23:13,433 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 16:23:13,433 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 16:23:13,433 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 16:23:13,433 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 16:23:13,433 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 16:23:13,433 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 16:23:13,433 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 16:23:13,433 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 16:23:13,433 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 16:23:13,433 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 16:23:13,434 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 16:23:13,796 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 16:23:13,796 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 16:23:13,797 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:23:13 BoogieIcfgContainer [2019-12-07 16:23:13,797 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 16:23:13,798 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 16:23:13,798 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 16:23:13,799 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 16:23:13,800 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 04:23:12" (1/3) ... [2019-12-07 16:23:13,800 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5bc0c680 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 04:23:13, skipping insertion in model container [2019-12-07 16:23:13,800 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:23:13" (2/3) ... [2019-12-07 16:23:13,801 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5bc0c680 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 04:23:13, skipping insertion in model container [2019-12-07 16:23:13,801 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:23:13" (3/3) ... [2019-12-07 16:23:13,802 INFO L109 eAbstractionObserver]: Analyzing ICFG safe008_pso.opt.i [2019-12-07 16:23:13,808 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 16:23:13,808 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 16:23:13,813 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 16:23:13,814 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 16:23:13,837 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,838 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,838 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,838 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,838 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,838 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,838 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,838 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,839 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,839 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,839 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,839 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,839 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,839 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,839 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,839 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,840 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,840 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,840 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,840 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,840 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,840 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,840 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,840 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,840 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,841 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,841 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,841 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,841 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,841 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,841 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,841 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,841 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,841 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,842 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,842 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,842 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,842 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,842 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,842 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,842 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,842 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,843 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,843 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,843 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,843 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,843 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,843 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,843 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,843 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,843 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,844 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,844 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,844 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,844 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,844 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,844 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,844 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,844 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,844 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,845 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,845 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,845 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,845 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,845 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,845 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,845 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,845 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,846 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,846 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,846 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,846 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,846 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,846 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,846 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,846 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,846 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,847 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,847 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,847 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,847 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,847 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,847 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,847 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,847 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,847 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,847 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,848 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,848 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,848 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,848 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,848 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,848 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,848 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:23:13,859 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 16:23:13,871 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 16:23:13,871 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 16:23:13,872 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 16:23:13,872 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 16:23:13,872 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 16:23:13,872 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 16:23:13,872 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 16:23:13,872 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 16:23:13,883 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 175 places, 212 transitions [2019-12-07 16:23:13,884 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 175 places, 212 transitions [2019-12-07 16:23:13,939 INFO L134 PetriNetUnfolder]: 47/209 cut-off events. [2019-12-07 16:23:13,939 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 16:23:13,950 INFO L76 FinitePrefix]: Finished finitePrefix Result has 219 conditions, 209 events. 47/209 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 585 event pairs. 9/169 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 16:23:13,964 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 175 places, 212 transitions [2019-12-07 16:23:13,994 INFO L134 PetriNetUnfolder]: 47/209 cut-off events. [2019-12-07 16:23:13,994 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 16:23:13,999 INFO L76 FinitePrefix]: Finished finitePrefix Result has 219 conditions, 209 events. 47/209 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 585 event pairs. 9/169 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 16:23:14,012 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 17114 [2019-12-07 16:23:14,013 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 16:23:16,759 WARN L192 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 89 DAG size of output: 87 [2019-12-07 16:23:16,844 INFO L206 etLargeBlockEncoding]: Checked pairs total: 80053 [2019-12-07 16:23:16,844 INFO L214 etLargeBlockEncoding]: Total number of compositions: 112 [2019-12-07 16:23:16,846 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 95 places, 106 transitions [2019-12-07 16:23:31,485 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 115670 states. [2019-12-07 16:23:31,487 INFO L276 IsEmpty]: Start isEmpty. Operand 115670 states. [2019-12-07 16:23:31,491 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-12-07 16:23:31,491 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:23:31,491 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-12-07 16:23:31,492 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:23:31,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:23:31,495 INFO L82 PathProgramCache]: Analyzing trace with hash 846448, now seen corresponding path program 1 times [2019-12-07 16:23:31,501 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:23:31,501 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1013694813] [2019-12-07 16:23:31,501 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:23:31,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:23:31,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:23:31,629 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1013694813] [2019-12-07 16:23:31,630 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:23:31,630 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 16:23:31,631 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [993138859] [2019-12-07 16:23:31,633 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:23:31,634 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:23:31,642 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:23:31,643 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:23:31,644 INFO L87 Difference]: Start difference. First operand 115670 states. Second operand 3 states. [2019-12-07 16:23:32,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:23:32,485 INFO L93 Difference]: Finished difference Result 115182 states and 492924 transitions. [2019-12-07 16:23:32,485 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:23:32,486 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-12-07 16:23:32,487 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:23:33,099 INFO L225 Difference]: With dead ends: 115182 [2019-12-07 16:23:33,099 INFO L226 Difference]: Without dead ends: 112830 [2019-12-07 16:23:33,100 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:23:36,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112830 states. [2019-12-07 16:23:38,173 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112830 to 112830. [2019-12-07 16:23:38,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112830 states. [2019-12-07 16:23:38,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112830 states to 112830 states and 483320 transitions. [2019-12-07 16:23:38,746 INFO L78 Accepts]: Start accepts. Automaton has 112830 states and 483320 transitions. Word has length 3 [2019-12-07 16:23:38,746 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:23:38,746 INFO L462 AbstractCegarLoop]: Abstraction has 112830 states and 483320 transitions. [2019-12-07 16:23:38,746 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:23:38,746 INFO L276 IsEmpty]: Start isEmpty. Operand 112830 states and 483320 transitions. [2019-12-07 16:23:38,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 16:23:38,749 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:23:38,749 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:23:38,749 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:23:38,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:23:38,750 INFO L82 PathProgramCache]: Analyzing trace with hash -939919620, now seen corresponding path program 1 times [2019-12-07 16:23:38,750 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:23:38,750 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [766550400] [2019-12-07 16:23:38,750 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:23:38,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:23:38,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:23:38,816 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [766550400] [2019-12-07 16:23:38,817 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:23:38,817 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:23:38,817 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [447210448] [2019-12-07 16:23:38,818 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:23:38,818 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:23:38,818 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:23:38,818 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:23:38,818 INFO L87 Difference]: Start difference. First operand 112830 states and 483320 transitions. Second operand 4 states. [2019-12-07 16:23:39,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:23:39,749 INFO L93 Difference]: Finished difference Result 176302 states and 727515 transitions. [2019-12-07 16:23:39,750 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:23:39,750 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 16:23:39,750 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:23:42,581 INFO L225 Difference]: With dead ends: 176302 [2019-12-07 16:23:42,581 INFO L226 Difference]: Without dead ends: 176253 [2019-12-07 16:23:42,582 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:23:46,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176253 states. [2019-12-07 16:23:48,849 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176253 to 159436. [2019-12-07 16:23:48,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159436 states. [2019-12-07 16:23:49,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159436 states to 159436 states and 665691 transitions. [2019-12-07 16:23:49,300 INFO L78 Accepts]: Start accepts. Automaton has 159436 states and 665691 transitions. Word has length 11 [2019-12-07 16:23:49,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:23:49,300 INFO L462 AbstractCegarLoop]: Abstraction has 159436 states and 665691 transitions. [2019-12-07 16:23:49,300 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:23:49,301 INFO L276 IsEmpty]: Start isEmpty. Operand 159436 states and 665691 transitions. [2019-12-07 16:23:49,304 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 16:23:49,304 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:23:49,304 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:23:49,304 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:23:49,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:23:49,305 INFO L82 PathProgramCache]: Analyzing trace with hash 670018080, now seen corresponding path program 1 times [2019-12-07 16:23:49,305 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:23:49,305 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434756017] [2019-12-07 16:23:49,305 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:23:49,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:23:49,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:23:49,353 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [434756017] [2019-12-07 16:23:49,353 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:23:49,353 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:23:49,353 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [265511310] [2019-12-07 16:23:49,353 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:23:49,353 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:23:49,353 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:23:49,353 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:23:49,354 INFO L87 Difference]: Start difference. First operand 159436 states and 665691 transitions. Second operand 4 states. [2019-12-07 16:23:50,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:23:50,743 INFO L93 Difference]: Finished difference Result 228428 states and 932375 transitions. [2019-12-07 16:23:50,743 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:23:50,743 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 16:23:50,743 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:23:51,317 INFO L225 Difference]: With dead ends: 228428 [2019-12-07 16:23:51,317 INFO L226 Difference]: Without dead ends: 228365 [2019-12-07 16:23:51,318 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:23:58,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228365 states. [2019-12-07 16:24:00,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228365 to 192396. [2019-12-07 16:24:00,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192396 states. [2019-12-07 16:24:01,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192396 states to 192396 states and 797806 transitions. [2019-12-07 16:24:01,846 INFO L78 Accepts]: Start accepts. Automaton has 192396 states and 797806 transitions. Word has length 13 [2019-12-07 16:24:01,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:01,847 INFO L462 AbstractCegarLoop]: Abstraction has 192396 states and 797806 transitions. [2019-12-07 16:24:01,847 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:24:01,847 INFO L276 IsEmpty]: Start isEmpty. Operand 192396 states and 797806 transitions. [2019-12-07 16:24:01,849 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 16:24:01,849 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:01,849 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:01,849 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:01,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:01,849 INFO L82 PathProgramCache]: Analyzing trace with hash -293312110, now seen corresponding path program 1 times [2019-12-07 16:24:01,849 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:01,850 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1548550281] [2019-12-07 16:24:01,850 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:01,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:01,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:01,889 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1548550281] [2019-12-07 16:24:01,889 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:01,889 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:01,889 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [327915453] [2019-12-07 16:24:01,889 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:24:01,889 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:01,890 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:24:01,890 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:24:01,890 INFO L87 Difference]: Start difference. First operand 192396 states and 797806 transitions. Second operand 4 states. [2019-12-07 16:24:03,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:03,046 INFO L93 Difference]: Finished difference Result 240534 states and 988069 transitions. [2019-12-07 16:24:03,047 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:24:03,047 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 16:24:03,047 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:03,658 INFO L225 Difference]: With dead ends: 240534 [2019-12-07 16:24:03,658 INFO L226 Difference]: Without dead ends: 240534 [2019-12-07 16:24:03,659 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:24:08,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 240534 states. [2019-12-07 16:24:14,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 240534 to 203638. [2019-12-07 16:24:14,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203638 states. [2019-12-07 16:24:14,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203638 states to 203638 states and 844577 transitions. [2019-12-07 16:24:14,796 INFO L78 Accepts]: Start accepts. Automaton has 203638 states and 844577 transitions. Word has length 13 [2019-12-07 16:24:14,797 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:14,797 INFO L462 AbstractCegarLoop]: Abstraction has 203638 states and 844577 transitions. [2019-12-07 16:24:14,797 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:24:14,797 INFO L276 IsEmpty]: Start isEmpty. Operand 203638 states and 844577 transitions. [2019-12-07 16:24:14,816 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 16:24:14,816 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:14,816 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:14,816 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:14,817 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:14,817 INFO L82 PathProgramCache]: Analyzing trace with hash 1303088540, now seen corresponding path program 1 times [2019-12-07 16:24:14,817 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:14,817 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040528152] [2019-12-07 16:24:14,817 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:14,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:14,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:14,877 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1040528152] [2019-12-07 16:24:14,878 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:14,878 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:24:14,878 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1255282418] [2019-12-07 16:24:14,878 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:24:14,878 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:14,878 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:24:14,879 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:24:14,879 INFO L87 Difference]: Start difference. First operand 203638 states and 844577 transitions. Second operand 5 states. [2019-12-07 16:24:16,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:16,869 INFO L93 Difference]: Finished difference Result 300567 states and 1220027 transitions. [2019-12-07 16:24:16,870 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 16:24:16,870 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 16:24:16,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:17,601 INFO L225 Difference]: With dead ends: 300567 [2019-12-07 16:24:17,601 INFO L226 Difference]: Without dead ends: 300504 [2019-12-07 16:24:17,602 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 16:24:26,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 300504 states. [2019-12-07 16:24:29,173 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 300504 to 216214. [2019-12-07 16:24:29,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 216214 states. [2019-12-07 16:24:29,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 216214 states to 216214 states and 891891 transitions. [2019-12-07 16:24:29,815 INFO L78 Accepts]: Start accepts. Automaton has 216214 states and 891891 transitions. Word has length 19 [2019-12-07 16:24:29,815 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:29,815 INFO L462 AbstractCegarLoop]: Abstraction has 216214 states and 891891 transitions. [2019-12-07 16:24:29,815 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:24:29,815 INFO L276 IsEmpty]: Start isEmpty. Operand 216214 states and 891891 transitions. [2019-12-07 16:24:29,828 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 16:24:29,828 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:29,828 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:29,828 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:29,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:29,828 INFO L82 PathProgramCache]: Analyzing trace with hash -2105368373, now seen corresponding path program 1 times [2019-12-07 16:24:29,829 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:29,829 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1381039889] [2019-12-07 16:24:29,829 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:29,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:29,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:29,876 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1381039889] [2019-12-07 16:24:29,876 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:29,876 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:24:29,877 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [799307495] [2019-12-07 16:24:29,877 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:24:29,877 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:29,877 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:24:29,877 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:24:29,877 INFO L87 Difference]: Start difference. First operand 216214 states and 891891 transitions. Second operand 5 states. [2019-12-07 16:24:31,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:31,933 INFO L93 Difference]: Finished difference Result 326371 states and 1320375 transitions. [2019-12-07 16:24:31,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 16:24:31,934 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 16:24:31,934 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:32,741 INFO L225 Difference]: With dead ends: 326371 [2019-12-07 16:24:32,741 INFO L226 Difference]: Without dead ends: 326224 [2019-12-07 16:24:32,742 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 16:24:39,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 326224 states. [2019-12-07 16:24:43,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 326224 to 227768. [2019-12-07 16:24:43,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 227768 states. [2019-12-07 16:24:43,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227768 states to 227768 states and 938858 transitions. [2019-12-07 16:24:43,901 INFO L78 Accepts]: Start accepts. Automaton has 227768 states and 938858 transitions. Word has length 19 [2019-12-07 16:24:43,901 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:43,901 INFO L462 AbstractCegarLoop]: Abstraction has 227768 states and 938858 transitions. [2019-12-07 16:24:43,901 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:24:43,901 INFO L276 IsEmpty]: Start isEmpty. Operand 227768 states and 938858 transitions. [2019-12-07 16:24:43,914 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 16:24:43,915 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:43,915 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:43,915 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:43,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:43,915 INFO L82 PathProgramCache]: Analyzing trace with hash 550593021, now seen corresponding path program 1 times [2019-12-07 16:24:43,915 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:43,915 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1422073040] [2019-12-07 16:24:43,915 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:43,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:43,954 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:43,954 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1422073040] [2019-12-07 16:24:43,955 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:43,955 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:24:43,955 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [622860725] [2019-12-07 16:24:43,955 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:24:43,955 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:43,956 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:24:43,956 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:24:43,956 INFO L87 Difference]: Start difference. First operand 227768 states and 938858 transitions. Second operand 5 states. [2019-12-07 16:24:47,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:47,987 INFO L93 Difference]: Finished difference Result 330156 states and 1338658 transitions. [2019-12-07 16:24:47,988 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 16:24:47,988 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 16:24:47,988 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:48,806 INFO L225 Difference]: With dead ends: 330156 [2019-12-07 16:24:48,806 INFO L226 Difference]: Without dead ends: 330093 [2019-12-07 16:24:48,807 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 16:24:55,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 330093 states. [2019-12-07 16:24:58,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 330093 to 245714. [2019-12-07 16:24:58,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 245714 states. [2019-12-07 16:24:59,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245714 states to 245714 states and 1011495 transitions. [2019-12-07 16:24:59,397 INFO L78 Accepts]: Start accepts. Automaton has 245714 states and 1011495 transitions. Word has length 19 [2019-12-07 16:24:59,398 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:59,398 INFO L462 AbstractCegarLoop]: Abstraction has 245714 states and 1011495 transitions. [2019-12-07 16:24:59,398 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:24:59,398 INFO L276 IsEmpty]: Start isEmpty. Operand 245714 states and 1011495 transitions. [2019-12-07 16:24:59,458 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 16:24:59,458 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:59,458 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:59,458 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:59,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:59,458 INFO L82 PathProgramCache]: Analyzing trace with hash 956366417, now seen corresponding path program 1 times [2019-12-07 16:24:59,458 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:59,459 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416037223] [2019-12-07 16:24:59,459 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:59,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:59,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:59,500 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [416037223] [2019-12-07 16:24:59,500 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:59,500 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:24:59,501 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1954520320] [2019-12-07 16:24:59,501 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:24:59,501 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:59,501 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:24:59,501 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:24:59,501 INFO L87 Difference]: Start difference. First operand 245714 states and 1011495 transitions. Second operand 6 states. [2019-12-07 16:25:01,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:01,734 INFO L93 Difference]: Finished difference Result 293437 states and 1194200 transitions. [2019-12-07 16:25:01,735 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 16:25:01,735 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2019-12-07 16:25:01,735 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:02,482 INFO L225 Difference]: With dead ends: 293437 [2019-12-07 16:25:02,482 INFO L226 Difference]: Without dead ends: 293290 [2019-12-07 16:25:02,482 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=81, Invalid=191, Unknown=0, NotChecked=0, Total=272 [2019-12-07 16:25:11,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 293290 states. [2019-12-07 16:25:14,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 293290 to 203000. [2019-12-07 16:25:14,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203000 states. [2019-12-07 16:25:14,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203000 states to 203000 states and 839373 transitions. [2019-12-07 16:25:14,664 INFO L78 Accepts]: Start accepts. Automaton has 203000 states and 839373 transitions. Word has length 25 [2019-12-07 16:25:14,664 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:14,664 INFO L462 AbstractCegarLoop]: Abstraction has 203000 states and 839373 transitions. [2019-12-07 16:25:14,664 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:25:14,664 INFO L276 IsEmpty]: Start isEmpty. Operand 203000 states and 839373 transitions. [2019-12-07 16:25:14,733 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 16:25:14,734 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:14,734 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:14,734 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:14,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:14,734 INFO L82 PathProgramCache]: Analyzing trace with hash -826573092, now seen corresponding path program 1 times [2019-12-07 16:25:14,734 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:14,734 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1819025221] [2019-12-07 16:25:14,734 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:14,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:14,759 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:14,759 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1819025221] [2019-12-07 16:25:14,760 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:14,760 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:25:14,760 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1460561691] [2019-12-07 16:25:14,760 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:25:14,760 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:14,760 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:25:14,760 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:25:14,761 INFO L87 Difference]: Start difference. First operand 203000 states and 839373 transitions. Second operand 3 states. [2019-12-07 16:25:14,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:14,879 INFO L93 Difference]: Finished difference Result 41735 states and 134919 transitions. [2019-12-07 16:25:14,879 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:25:14,880 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 16:25:14,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:14,937 INFO L225 Difference]: With dead ends: 41735 [2019-12-07 16:25:14,937 INFO L226 Difference]: Without dead ends: 41735 [2019-12-07 16:25:14,937 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:25:15,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41735 states. [2019-12-07 16:25:15,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41735 to 41735. [2019-12-07 16:25:15,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41735 states. [2019-12-07 16:25:15,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41735 states to 41735 states and 134919 transitions. [2019-12-07 16:25:15,863 INFO L78 Accepts]: Start accepts. Automaton has 41735 states and 134919 transitions. Word has length 27 [2019-12-07 16:25:15,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:15,863 INFO L462 AbstractCegarLoop]: Abstraction has 41735 states and 134919 transitions. [2019-12-07 16:25:15,863 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:25:15,863 INFO L276 IsEmpty]: Start isEmpty. Operand 41735 states and 134919 transitions. [2019-12-07 16:25:15,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2019-12-07 16:25:15,882 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:15,882 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:15,882 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:15,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:15,882 INFO L82 PathProgramCache]: Analyzing trace with hash -181038669, now seen corresponding path program 1 times [2019-12-07 16:25:15,882 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:15,883 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1412268989] [2019-12-07 16:25:15,883 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:15,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:15,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:15,917 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1412268989] [2019-12-07 16:25:15,918 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:15,918 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:25:15,918 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [517646580] [2019-12-07 16:25:15,918 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:25:15,918 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:15,918 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:25:15,918 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:25:15,919 INFO L87 Difference]: Start difference. First operand 41735 states and 134919 transitions. Second operand 4 states. [2019-12-07 16:25:15,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:15,952 INFO L93 Difference]: Finished difference Result 7949 states and 21432 transitions. [2019-12-07 16:25:15,952 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 16:25:15,952 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 39 [2019-12-07 16:25:15,952 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:15,961 INFO L225 Difference]: With dead ends: 7949 [2019-12-07 16:25:15,961 INFO L226 Difference]: Without dead ends: 7949 [2019-12-07 16:25:15,962 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:25:15,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7949 states. [2019-12-07 16:25:16,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7949 to 7837. [2019-12-07 16:25:16,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7837 states. [2019-12-07 16:25:16,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7837 states to 7837 states and 21112 transitions. [2019-12-07 16:25:16,050 INFO L78 Accepts]: Start accepts. Automaton has 7837 states and 21112 transitions. Word has length 39 [2019-12-07 16:25:16,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:16,050 INFO L462 AbstractCegarLoop]: Abstraction has 7837 states and 21112 transitions. [2019-12-07 16:25:16,050 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:25:16,050 INFO L276 IsEmpty]: Start isEmpty. Operand 7837 states and 21112 transitions. [2019-12-07 16:25:16,057 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 16:25:16,057 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:16,057 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:16,058 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:16,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:16,058 INFO L82 PathProgramCache]: Analyzing trace with hash -118101162, now seen corresponding path program 1 times [2019-12-07 16:25:16,058 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:16,058 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414280563] [2019-12-07 16:25:16,058 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:16,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:16,105 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:16,105 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [414280563] [2019-12-07 16:25:16,105 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:16,105 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:25:16,106 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [213597813] [2019-12-07 16:25:16,106 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:25:16,106 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:16,106 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:25:16,106 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:25:16,106 INFO L87 Difference]: Start difference. First operand 7837 states and 21112 transitions. Second operand 5 states. [2019-12-07 16:25:16,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:16,130 INFO L93 Difference]: Finished difference Result 5331 states and 15289 transitions. [2019-12-07 16:25:16,131 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:25:16,131 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-12-07 16:25:16,131 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:16,137 INFO L225 Difference]: With dead ends: 5331 [2019-12-07 16:25:16,137 INFO L226 Difference]: Without dead ends: 5331 [2019-12-07 16:25:16,137 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:25:16,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5331 states. [2019-12-07 16:25:16,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5331 to 4967. [2019-12-07 16:25:16,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4967 states. [2019-12-07 16:25:16,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4967 states to 4967 states and 14305 transitions. [2019-12-07 16:25:16,201 INFO L78 Accepts]: Start accepts. Automaton has 4967 states and 14305 transitions. Word has length 51 [2019-12-07 16:25:16,201 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:16,201 INFO L462 AbstractCegarLoop]: Abstraction has 4967 states and 14305 transitions. [2019-12-07 16:25:16,201 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:25:16,201 INFO L276 IsEmpty]: Start isEmpty. Operand 4967 states and 14305 transitions. [2019-12-07 16:25:16,205 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 16:25:16,205 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:16,205 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:16,205 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:16,205 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:16,206 INFO L82 PathProgramCache]: Analyzing trace with hash -1019045356, now seen corresponding path program 1 times [2019-12-07 16:25:16,206 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:16,206 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [478790435] [2019-12-07 16:25:16,206 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:16,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:16,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:16,266 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [478790435] [2019-12-07 16:25:16,267 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:16,267 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:25:16,267 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2052397939] [2019-12-07 16:25:16,267 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:25:16,267 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:16,268 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:25:16,268 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:25:16,268 INFO L87 Difference]: Start difference. First operand 4967 states and 14305 transitions. Second operand 5 states. [2019-12-07 16:25:16,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:16,464 INFO L93 Difference]: Finished difference Result 7558 states and 21570 transitions. [2019-12-07 16:25:16,465 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:25:16,465 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 65 [2019-12-07 16:25:16,465 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:16,471 INFO L225 Difference]: With dead ends: 7558 [2019-12-07 16:25:16,471 INFO L226 Difference]: Without dead ends: 7558 [2019-12-07 16:25:16,472 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:25:16,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7558 states. [2019-12-07 16:25:16,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7558 to 6659. [2019-12-07 16:25:16,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6659 states. [2019-12-07 16:25:16,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6659 states to 6659 states and 19091 transitions. [2019-12-07 16:25:16,552 INFO L78 Accepts]: Start accepts. Automaton has 6659 states and 19091 transitions. Word has length 65 [2019-12-07 16:25:16,552 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:16,552 INFO L462 AbstractCegarLoop]: Abstraction has 6659 states and 19091 transitions. [2019-12-07 16:25:16,552 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:25:16,552 INFO L276 IsEmpty]: Start isEmpty. Operand 6659 states and 19091 transitions. [2019-12-07 16:25:16,557 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 16:25:16,557 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:16,557 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:16,557 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:16,557 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:16,557 INFO L82 PathProgramCache]: Analyzing trace with hash -613444874, now seen corresponding path program 2 times [2019-12-07 16:25:16,558 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:16,558 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1788090525] [2019-12-07 16:25:16,558 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:16,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:16,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:16,616 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1788090525] [2019-12-07 16:25:16,616 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:16,617 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:25:16,617 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1994295763] [2019-12-07 16:25:16,617 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:25:16,617 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:16,617 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:25:16,617 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:25:16,617 INFO L87 Difference]: Start difference. First operand 6659 states and 19091 transitions. Second operand 3 states. [2019-12-07 16:25:16,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:16,641 INFO L93 Difference]: Finished difference Result 6289 states and 17750 transitions. [2019-12-07 16:25:16,642 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:25:16,642 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 16:25:16,642 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:16,647 INFO L225 Difference]: With dead ends: 6289 [2019-12-07 16:25:16,647 INFO L226 Difference]: Without dead ends: 6289 [2019-12-07 16:25:16,648 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:25:16,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6289 states. [2019-12-07 16:25:16,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6289 to 6133. [2019-12-07 16:25:16,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6133 states. [2019-12-07 16:25:16,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6133 states to 6133 states and 17320 transitions. [2019-12-07 16:25:16,718 INFO L78 Accepts]: Start accepts. Automaton has 6133 states and 17320 transitions. Word has length 65 [2019-12-07 16:25:16,718 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:16,718 INFO L462 AbstractCegarLoop]: Abstraction has 6133 states and 17320 transitions. [2019-12-07 16:25:16,718 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:25:16,718 INFO L276 IsEmpty]: Start isEmpty. Operand 6133 states and 17320 transitions. [2019-12-07 16:25:16,722 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 16:25:16,722 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:16,723 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:16,723 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:16,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:16,723 INFO L82 PathProgramCache]: Analyzing trace with hash 223341978, now seen corresponding path program 1 times [2019-12-07 16:25:16,723 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:16,723 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [156269980] [2019-12-07 16:25:16,723 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:16,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:16,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:16,792 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [156269980] [2019-12-07 16:25:16,792 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:16,792 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:25:16,792 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2046381082] [2019-12-07 16:25:16,793 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:25:16,793 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:16,793 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:25:16,793 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:25:16,793 INFO L87 Difference]: Start difference. First operand 6133 states and 17320 transitions. Second operand 5 states. [2019-12-07 16:25:17,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:17,016 INFO L93 Difference]: Finished difference Result 8712 states and 24399 transitions. [2019-12-07 16:25:17,016 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 16:25:17,016 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 66 [2019-12-07 16:25:17,017 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:17,024 INFO L225 Difference]: With dead ends: 8712 [2019-12-07 16:25:17,024 INFO L226 Difference]: Without dead ends: 8712 [2019-12-07 16:25:17,024 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:25:17,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8712 states. [2019-12-07 16:25:17,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8712 to 6784. [2019-12-07 16:25:17,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6784 states. [2019-12-07 16:25:17,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6784 states to 6784 states and 19209 transitions. [2019-12-07 16:25:17,115 INFO L78 Accepts]: Start accepts. Automaton has 6784 states and 19209 transitions. Word has length 66 [2019-12-07 16:25:17,115 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:17,115 INFO L462 AbstractCegarLoop]: Abstraction has 6784 states and 19209 transitions. [2019-12-07 16:25:17,115 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:25:17,115 INFO L276 IsEmpty]: Start isEmpty. Operand 6784 states and 19209 transitions. [2019-12-07 16:25:17,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 16:25:17,120 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:17,120 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:17,120 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:17,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:17,120 INFO L82 PathProgramCache]: Analyzing trace with hash -446701502, now seen corresponding path program 2 times [2019-12-07 16:25:17,120 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:17,121 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [165268391] [2019-12-07 16:25:17,121 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:17,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:17,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:17,304 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [165268391] [2019-12-07 16:25:17,304 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:17,305 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 16:25:17,305 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [176217448] [2019-12-07 16:25:17,305 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 16:25:17,305 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:17,305 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 16:25:17,305 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2019-12-07 16:25:17,305 INFO L87 Difference]: Start difference. First operand 6784 states and 19209 transitions. Second operand 13 states. [2019-12-07 16:25:17,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:17,762 INFO L93 Difference]: Finished difference Result 15281 states and 43257 transitions. [2019-12-07 16:25:17,762 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 16:25:17,762 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 66 [2019-12-07 16:25:17,762 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:17,769 INFO L225 Difference]: With dead ends: 15281 [2019-12-07 16:25:17,769 INFO L226 Difference]: Without dead ends: 7828 [2019-12-07 16:25:17,769 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 87 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=145, Invalid=455, Unknown=0, NotChecked=0, Total=600 [2019-12-07 16:25:17,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7828 states. [2019-12-07 16:25:17,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7828 to 6415. [2019-12-07 16:25:17,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6415 states. [2019-12-07 16:25:17,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6415 states to 6415 states and 18105 transitions. [2019-12-07 16:25:17,854 INFO L78 Accepts]: Start accepts. Automaton has 6415 states and 18105 transitions. Word has length 66 [2019-12-07 16:25:17,855 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:17,855 INFO L462 AbstractCegarLoop]: Abstraction has 6415 states and 18105 transitions. [2019-12-07 16:25:17,855 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 16:25:17,855 INFO L276 IsEmpty]: Start isEmpty. Operand 6415 states and 18105 transitions. [2019-12-07 16:25:17,859 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 16:25:17,859 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:17,860 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:17,860 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:17,860 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:17,860 INFO L82 PathProgramCache]: Analyzing trace with hash -806353662, now seen corresponding path program 3 times [2019-12-07 16:25:17,860 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:17,860 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [220306374] [2019-12-07 16:25:17,860 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:17,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:17,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:17,933 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [220306374] [2019-12-07 16:25:17,933 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:17,933 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 16:25:17,933 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [339047951] [2019-12-07 16:25:17,934 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 16:25:17,934 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:17,934 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 16:25:17,934 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:25:17,934 INFO L87 Difference]: Start difference. First operand 6415 states and 18105 transitions. Second operand 7 states. [2019-12-07 16:25:18,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:18,553 INFO L93 Difference]: Finished difference Result 9213 states and 25620 transitions. [2019-12-07 16:25:18,554 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 16:25:18,554 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 66 [2019-12-07 16:25:18,554 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:18,561 INFO L225 Difference]: With dead ends: 9213 [2019-12-07 16:25:18,561 INFO L226 Difference]: Without dead ends: 9213 [2019-12-07 16:25:18,561 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=42, Invalid=114, Unknown=0, NotChecked=0, Total=156 [2019-12-07 16:25:18,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9213 states. [2019-12-07 16:25:18,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9213 to 6830. [2019-12-07 16:25:18,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6830 states. [2019-12-07 16:25:18,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6830 states to 6830 states and 19261 transitions. [2019-12-07 16:25:18,652 INFO L78 Accepts]: Start accepts. Automaton has 6830 states and 19261 transitions. Word has length 66 [2019-12-07 16:25:18,652 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:18,652 INFO L462 AbstractCegarLoop]: Abstraction has 6830 states and 19261 transitions. [2019-12-07 16:25:18,652 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 16:25:18,652 INFO L276 IsEmpty]: Start isEmpty. Operand 6830 states and 19261 transitions. [2019-12-07 16:25:18,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 16:25:18,657 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:18,657 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:18,657 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:18,657 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:18,657 INFO L82 PathProgramCache]: Analyzing trace with hash 1549059410, now seen corresponding path program 4 times [2019-12-07 16:25:18,657 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:18,657 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2022114631] [2019-12-07 16:25:18,658 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:18,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:18,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:18,752 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2022114631] [2019-12-07 16:25:18,752 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:18,752 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 16:25:18,752 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [16573479] [2019-12-07 16:25:18,752 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 16:25:18,753 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:18,753 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 16:25:18,753 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2019-12-07 16:25:18,753 INFO L87 Difference]: Start difference. First operand 6830 states and 19261 transitions. Second operand 9 states. [2019-12-07 16:25:19,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:19,282 INFO L93 Difference]: Finished difference Result 11724 states and 32586 transitions. [2019-12-07 16:25:19,282 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 16:25:19,282 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 66 [2019-12-07 16:25:19,282 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:19,291 INFO L225 Difference]: With dead ends: 11724 [2019-12-07 16:25:19,291 INFO L226 Difference]: Without dead ends: 11724 [2019-12-07 16:25:19,292 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=50, Invalid=160, Unknown=0, NotChecked=0, Total=210 [2019-12-07 16:25:19,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11724 states. [2019-12-07 16:25:19,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11724 to 7479. [2019-12-07 16:25:19,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7479 states. [2019-12-07 16:25:19,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7479 states to 7479 states and 21056 transitions. [2019-12-07 16:25:19,400 INFO L78 Accepts]: Start accepts. Automaton has 7479 states and 21056 transitions. Word has length 66 [2019-12-07 16:25:19,400 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:19,400 INFO L462 AbstractCegarLoop]: Abstraction has 7479 states and 21056 transitions. [2019-12-07 16:25:19,400 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 16:25:19,400 INFO L276 IsEmpty]: Start isEmpty. Operand 7479 states and 21056 transitions. [2019-12-07 16:25:19,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 16:25:19,406 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:19,406 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:19,406 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:19,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:19,406 INFO L82 PathProgramCache]: Analyzing trace with hash 479477378, now seen corresponding path program 5 times [2019-12-07 16:25:19,406 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:19,406 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [195382825] [2019-12-07 16:25:19,406 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:19,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:19,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:19,530 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [195382825] [2019-12-07 16:25:19,530 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:19,530 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 16:25:19,530 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1806152138] [2019-12-07 16:25:19,530 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 16:25:19,530 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:19,531 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 16:25:19,531 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2019-12-07 16:25:19,531 INFO L87 Difference]: Start difference. First operand 7479 states and 21056 transitions. Second operand 10 states. [2019-12-07 16:25:20,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:20,500 INFO L93 Difference]: Finished difference Result 12163 states and 33776 transitions. [2019-12-07 16:25:20,500 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 16:25:20,500 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 66 [2019-12-07 16:25:20,500 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:20,510 INFO L225 Difference]: With dead ends: 12163 [2019-12-07 16:25:20,510 INFO L226 Difference]: Without dead ends: 12163 [2019-12-07 16:25:20,510 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 7 SyntacticMatches, 2 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 137 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=138, Invalid=564, Unknown=0, NotChecked=0, Total=702 [2019-12-07 16:25:20,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12163 states. [2019-12-07 16:25:20,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12163 to 8091. [2019-12-07 16:25:20,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8091 states. [2019-12-07 16:25:20,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8091 states to 8091 states and 22798 transitions. [2019-12-07 16:25:20,622 INFO L78 Accepts]: Start accepts. Automaton has 8091 states and 22798 transitions. Word has length 66 [2019-12-07 16:25:20,622 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:20,622 INFO L462 AbstractCegarLoop]: Abstraction has 8091 states and 22798 transitions. [2019-12-07 16:25:20,622 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 16:25:20,622 INFO L276 IsEmpty]: Start isEmpty. Operand 8091 states and 22798 transitions. [2019-12-07 16:25:20,627 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 16:25:20,628 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:20,628 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:20,628 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:20,628 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:20,628 INFO L82 PathProgramCache]: Analyzing trace with hash 1795321204, now seen corresponding path program 6 times [2019-12-07 16:25:20,628 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:20,628 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [207564526] [2019-12-07 16:25:20,628 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:20,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:20,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:20,762 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [207564526] [2019-12-07 16:25:20,762 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:20,762 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 16:25:20,762 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1324246019] [2019-12-07 16:25:20,763 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 16:25:20,763 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:20,763 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 16:25:20,763 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2019-12-07 16:25:20,763 INFO L87 Difference]: Start difference. First operand 8091 states and 22798 transitions. Second operand 11 states. [2019-12-07 16:25:21,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:21,648 INFO L93 Difference]: Finished difference Result 12207 states and 33965 transitions. [2019-12-07 16:25:21,649 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-12-07 16:25:21,649 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 66 [2019-12-07 16:25:21,649 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:21,658 INFO L225 Difference]: With dead ends: 12207 [2019-12-07 16:25:21,658 INFO L226 Difference]: Without dead ends: 12207 [2019-12-07 16:25:21,659 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 6 SyntacticMatches, 2 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 168 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=148, Invalid=664, Unknown=0, NotChecked=0, Total=812 [2019-12-07 16:25:21,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12207 states. [2019-12-07 16:25:21,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12207 to 7521. [2019-12-07 16:25:21,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7521 states. [2019-12-07 16:25:21,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7521 states to 7521 states and 21207 transitions. [2019-12-07 16:25:21,767 INFO L78 Accepts]: Start accepts. Automaton has 7521 states and 21207 transitions. Word has length 66 [2019-12-07 16:25:21,767 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:21,767 INFO L462 AbstractCegarLoop]: Abstraction has 7521 states and 21207 transitions. [2019-12-07 16:25:21,767 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 16:25:21,767 INFO L276 IsEmpty]: Start isEmpty. Operand 7521 states and 21207 transitions. [2019-12-07 16:25:21,772 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 16:25:21,772 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:21,772 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:21,772 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:21,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:21,772 INFO L82 PathProgramCache]: Analyzing trace with hash 2091502336, now seen corresponding path program 7 times [2019-12-07 16:25:21,773 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:21,773 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1652622803] [2019-12-07 16:25:21,773 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:21,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:21,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:21,868 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1652622803] [2019-12-07 16:25:21,869 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:21,869 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 16:25:21,869 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [991608612] [2019-12-07 16:25:21,869 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 16:25:21,869 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:21,869 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 16:25:21,870 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2019-12-07 16:25:21,870 INFO L87 Difference]: Start difference. First operand 7521 states and 21207 transitions. Second operand 9 states. [2019-12-07 16:25:22,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:22,663 INFO L93 Difference]: Finished difference Result 12432 states and 34845 transitions. [2019-12-07 16:25:22,664 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 16:25:22,664 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 66 [2019-12-07 16:25:22,664 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:22,675 INFO L225 Difference]: With dead ends: 12432 [2019-12-07 16:25:22,675 INFO L226 Difference]: Without dead ends: 12432 [2019-12-07 16:25:22,675 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 10 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 69 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=96, Invalid=284, Unknown=0, NotChecked=0, Total=380 [2019-12-07 16:25:22,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12432 states. [2019-12-07 16:25:22,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12432 to 7731. [2019-12-07 16:25:22,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7731 states. [2019-12-07 16:25:22,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7731 states to 7731 states and 21807 transitions. [2019-12-07 16:25:22,788 INFO L78 Accepts]: Start accepts. Automaton has 7731 states and 21807 transitions. Word has length 66 [2019-12-07 16:25:22,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:22,788 INFO L462 AbstractCegarLoop]: Abstraction has 7731 states and 21807 transitions. [2019-12-07 16:25:22,788 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 16:25:22,788 INFO L276 IsEmpty]: Start isEmpty. Operand 7731 states and 21807 transitions. [2019-12-07 16:25:22,793 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 16:25:22,794 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:22,794 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:22,794 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:22,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:22,794 INFO L82 PathProgramCache]: Analyzing trace with hash -1951217226, now seen corresponding path program 8 times [2019-12-07 16:25:22,794 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:22,794 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [368469350] [2019-12-07 16:25:22,794 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:22,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:22,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:22,825 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [368469350] [2019-12-07 16:25:22,826 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:22,826 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:25:22,826 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [423228718] [2019-12-07 16:25:22,826 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:25:22,826 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:22,826 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:25:22,827 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:25:22,827 INFO L87 Difference]: Start difference. First operand 7731 states and 21807 transitions. Second operand 3 states. [2019-12-07 16:25:22,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:22,867 INFO L93 Difference]: Finished difference Result 7730 states and 21805 transitions. [2019-12-07 16:25:22,867 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:25:22,868 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 16:25:22,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:22,874 INFO L225 Difference]: With dead ends: 7730 [2019-12-07 16:25:22,874 INFO L226 Difference]: Without dead ends: 7730 [2019-12-07 16:25:22,875 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:25:22,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7730 states. [2019-12-07 16:25:22,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7730 to 5129. [2019-12-07 16:25:22,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5129 states. [2019-12-07 16:25:22,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5129 states to 5129 states and 14540 transitions. [2019-12-07 16:25:22,965 INFO L78 Accepts]: Start accepts. Automaton has 5129 states and 14540 transitions. Word has length 66 [2019-12-07 16:25:22,966 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:22,966 INFO L462 AbstractCegarLoop]: Abstraction has 5129 states and 14540 transitions. [2019-12-07 16:25:22,966 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:25:22,966 INFO L276 IsEmpty]: Start isEmpty. Operand 5129 states and 14540 transitions. [2019-12-07 16:25:22,969 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 16:25:22,969 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:22,969 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:22,969 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:22,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:22,970 INFO L82 PathProgramCache]: Analyzing trace with hash 1374418208, now seen corresponding path program 1 times [2019-12-07 16:25:22,970 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:22,970 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [949133629] [2019-12-07 16:25:22,970 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:22,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:22,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:22,999 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [949133629] [2019-12-07 16:25:22,999 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:22,999 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:25:22,999 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [993180114] [2019-12-07 16:25:22,999 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:25:22,999 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:23,000 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:25:23,000 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:25:23,000 INFO L87 Difference]: Start difference. First operand 5129 states and 14540 transitions. Second operand 3 states. [2019-12-07 16:25:23,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:23,020 INFO L93 Difference]: Finished difference Result 4739 states and 13191 transitions. [2019-12-07 16:25:23,021 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:25:23,021 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 16:25:23,021 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:23,026 INFO L225 Difference]: With dead ends: 4739 [2019-12-07 16:25:23,026 INFO L226 Difference]: Without dead ends: 4739 [2019-12-07 16:25:23,026 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:25:23,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4739 states. [2019-12-07 16:25:23,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4739 to 4174. [2019-12-07 16:25:23,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4174 states. [2019-12-07 16:25:23,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4174 states to 4174 states and 11624 transitions. [2019-12-07 16:25:23,084 INFO L78 Accepts]: Start accepts. Automaton has 4174 states and 11624 transitions. Word has length 67 [2019-12-07 16:25:23,084 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:23,084 INFO L462 AbstractCegarLoop]: Abstraction has 4174 states and 11624 transitions. [2019-12-07 16:25:23,084 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:25:23,084 INFO L276 IsEmpty]: Start isEmpty. Operand 4174 states and 11624 transitions. [2019-12-07 16:25:23,087 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:25:23,087 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:23,087 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:23,087 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:23,088 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:23,088 INFO L82 PathProgramCache]: Analyzing trace with hash -1090372922, now seen corresponding path program 1 times [2019-12-07 16:25:23,088 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:23,088 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781741724] [2019-12-07 16:25:23,088 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:23,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:23,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:23,246 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [781741724] [2019-12-07 16:25:23,246 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:23,246 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 16:25:23,246 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2008365381] [2019-12-07 16:25:23,247 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 16:25:23,247 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:23,247 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 16:25:23,247 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=129, Unknown=0, NotChecked=0, Total=156 [2019-12-07 16:25:23,247 INFO L87 Difference]: Start difference. First operand 4174 states and 11624 transitions. Second operand 13 states. [2019-12-07 16:25:24,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:24,172 INFO L93 Difference]: Finished difference Result 7214 states and 20004 transitions. [2019-12-07 16:25:24,173 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 16:25:24,173 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 68 [2019-12-07 16:25:24,173 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:24,182 INFO L225 Difference]: With dead ends: 7214 [2019-12-07 16:25:24,182 INFO L226 Difference]: Without dead ends: 6455 [2019-12-07 16:25:24,183 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 118 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=155, Invalid=601, Unknown=0, NotChecked=0, Total=756 [2019-12-07 16:25:24,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6455 states. [2019-12-07 16:25:24,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6455 to 5351. [2019-12-07 16:25:24,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5351 states. [2019-12-07 16:25:24,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5351 states to 5351 states and 14810 transitions. [2019-12-07 16:25:24,257 INFO L78 Accepts]: Start accepts. Automaton has 5351 states and 14810 transitions. Word has length 68 [2019-12-07 16:25:24,257 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:24,257 INFO L462 AbstractCegarLoop]: Abstraction has 5351 states and 14810 transitions. [2019-12-07 16:25:24,257 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 16:25:24,257 INFO L276 IsEmpty]: Start isEmpty. Operand 5351 states and 14810 transitions. [2019-12-07 16:25:24,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:25:24,260 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:24,261 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:24,261 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:24,261 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:24,261 INFO L82 PathProgramCache]: Analyzing trace with hash -1311051616, now seen corresponding path program 2 times [2019-12-07 16:25:24,261 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:24,261 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [199026295] [2019-12-07 16:25:24,261 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:24,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:24,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:24,581 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [199026295] [2019-12-07 16:25:24,581 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:24,581 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 16:25:24,581 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [140246292] [2019-12-07 16:25:24,581 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 16:25:24,581 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:24,582 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 16:25:24,582 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=259, Unknown=0, NotChecked=0, Total=306 [2019-12-07 16:25:24,582 INFO L87 Difference]: Start difference. First operand 5351 states and 14810 transitions. Second operand 18 states. [2019-12-07 16:25:27,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:27,536 INFO L93 Difference]: Finished difference Result 12815 states and 35313 transitions. [2019-12-07 16:25:27,537 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-12-07 16:25:27,537 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 68 [2019-12-07 16:25:27,537 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:27,555 INFO L225 Difference]: With dead ends: 12815 [2019-12-07 16:25:27,555 INFO L226 Difference]: Without dead ends: 12790 [2019-12-07 16:25:27,557 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 1 SyntacticMatches, 4 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 374 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=275, Invalid=1447, Unknown=0, NotChecked=0, Total=1722 [2019-12-07 16:25:27,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12790 states. [2019-12-07 16:25:27,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12790 to 5528. [2019-12-07 16:25:27,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5528 states. [2019-12-07 16:25:27,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5528 states to 5528 states and 15292 transitions. [2019-12-07 16:25:27,658 INFO L78 Accepts]: Start accepts. Automaton has 5528 states and 15292 transitions. Word has length 68 [2019-12-07 16:25:27,658 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:27,658 INFO L462 AbstractCegarLoop]: Abstraction has 5528 states and 15292 transitions. [2019-12-07 16:25:27,658 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 16:25:27,658 INFO L276 IsEmpty]: Start isEmpty. Operand 5528 states and 15292 transitions. [2019-12-07 16:25:27,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:25:27,661 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:27,662 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:27,662 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:27,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:27,662 INFO L82 PathProgramCache]: Analyzing trace with hash 209870412, now seen corresponding path program 3 times [2019-12-07 16:25:27,662 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:27,662 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396084162] [2019-12-07 16:25:27,662 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:27,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:27,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:27,815 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1396084162] [2019-12-07 16:25:27,815 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:27,815 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 16:25:27,815 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [480395815] [2019-12-07 16:25:27,816 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 16:25:27,816 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:27,816 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 16:25:27,816 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=129, Unknown=0, NotChecked=0, Total=156 [2019-12-07 16:25:27,816 INFO L87 Difference]: Start difference. First operand 5528 states and 15292 transitions. Second operand 13 states. [2019-12-07 16:25:28,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:28,263 INFO L93 Difference]: Finished difference Result 8894 states and 24440 transitions. [2019-12-07 16:25:28,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 16:25:28,263 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 68 [2019-12-07 16:25:28,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:28,270 INFO L225 Difference]: With dead ends: 8894 [2019-12-07 16:25:28,270 INFO L226 Difference]: Without dead ends: 8387 [2019-12-07 16:25:28,271 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 150 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=185, Invalid=685, Unknown=0, NotChecked=0, Total=870 [2019-12-07 16:25:28,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8387 states. [2019-12-07 16:25:28,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8387 to 5640. [2019-12-07 16:25:28,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5640 states. [2019-12-07 16:25:28,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5640 states to 5640 states and 15625 transitions. [2019-12-07 16:25:28,347 INFO L78 Accepts]: Start accepts. Automaton has 5640 states and 15625 transitions. Word has length 68 [2019-12-07 16:25:28,347 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:28,347 INFO L462 AbstractCegarLoop]: Abstraction has 5640 states and 15625 transitions. [2019-12-07 16:25:28,347 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 16:25:28,348 INFO L276 IsEmpty]: Start isEmpty. Operand 5640 states and 15625 transitions. [2019-12-07 16:25:28,351 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:25:28,351 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:28,351 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:28,352 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:28,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:28,352 INFO L82 PathProgramCache]: Analyzing trace with hash -526111866, now seen corresponding path program 4 times [2019-12-07 16:25:28,352 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:28,352 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [121985069] [2019-12-07 16:25:28,352 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:28,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:28,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:28,743 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [121985069] [2019-12-07 16:25:28,743 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:28,743 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2019-12-07 16:25:28,743 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [984108214] [2019-12-07 16:25:28,743 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-12-07 16:25:28,743 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:28,743 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 16:25:28,744 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=323, Unknown=0, NotChecked=0, Total=380 [2019-12-07 16:25:28,744 INFO L87 Difference]: Start difference. First operand 5640 states and 15625 transitions. Second operand 20 states. [2019-12-07 16:25:32,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:32,172 INFO L93 Difference]: Finished difference Result 14734 states and 40575 transitions. [2019-12-07 16:25:32,173 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-12-07 16:25:32,173 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 68 [2019-12-07 16:25:32,174 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:32,194 INFO L225 Difference]: With dead ends: 14734 [2019-12-07 16:25:32,194 INFO L226 Difference]: Without dead ends: 14709 [2019-12-07 16:25:32,196 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 659 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=469, Invalid=2287, Unknown=0, NotChecked=0, Total=2756 [2019-12-07 16:25:32,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14709 states. [2019-12-07 16:25:32,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14709 to 5867. [2019-12-07 16:25:32,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5867 states. [2019-12-07 16:25:32,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5867 states to 5867 states and 16248 transitions. [2019-12-07 16:25:32,307 INFO L78 Accepts]: Start accepts. Automaton has 5867 states and 16248 transitions. Word has length 68 [2019-12-07 16:25:32,307 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:32,307 INFO L462 AbstractCegarLoop]: Abstraction has 5867 states and 16248 transitions. [2019-12-07 16:25:32,307 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-12-07 16:25:32,307 INFO L276 IsEmpty]: Start isEmpty. Operand 5867 states and 16248 transitions. [2019-12-07 16:25:32,311 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:25:32,311 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:32,311 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:32,311 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:32,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:32,311 INFO L82 PathProgramCache]: Analyzing trace with hash -450226916, now seen corresponding path program 5 times [2019-12-07 16:25:32,312 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:32,312 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2064386323] [2019-12-07 16:25:32,312 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:32,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:32,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:32,738 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2064386323] [2019-12-07 16:25:32,739 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:32,739 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2019-12-07 16:25:32,739 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1815135577] [2019-12-07 16:25:32,739 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-12-07 16:25:32,739 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:32,739 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 16:25:32,739 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=422, Unknown=0, NotChecked=0, Total=506 [2019-12-07 16:25:32,739 INFO L87 Difference]: Start difference. First operand 5867 states and 16248 transitions. Second operand 23 states. [2019-12-07 16:25:38,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:38,080 INFO L93 Difference]: Finished difference Result 21895 states and 59421 transitions. [2019-12-07 16:25:38,080 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2019-12-07 16:25:38,080 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 68 [2019-12-07 16:25:38,080 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:38,097 INFO L225 Difference]: With dead ends: 21895 [2019-12-07 16:25:38,098 INFO L226 Difference]: Without dead ends: 21425 [2019-12-07 16:25:38,099 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1290 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=595, Invalid=4097, Unknown=0, NotChecked=0, Total=4692 [2019-12-07 16:25:38,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21425 states. [2019-12-07 16:25:38,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21425 to 6315. [2019-12-07 16:25:38,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6315 states. [2019-12-07 16:25:38,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6315 states to 6315 states and 17494 transitions. [2019-12-07 16:25:38,252 INFO L78 Accepts]: Start accepts. Automaton has 6315 states and 17494 transitions. Word has length 68 [2019-12-07 16:25:38,252 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:38,252 INFO L462 AbstractCegarLoop]: Abstraction has 6315 states and 17494 transitions. [2019-12-07 16:25:38,253 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-12-07 16:25:38,253 INFO L276 IsEmpty]: Start isEmpty. Operand 6315 states and 17494 transitions. [2019-12-07 16:25:38,257 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:25:38,257 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:38,257 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:38,257 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:38,257 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:38,258 INFO L82 PathProgramCache]: Analyzing trace with hash 1082498466, now seen corresponding path program 6 times [2019-12-07 16:25:38,258 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:38,258 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [401572345] [2019-12-07 16:25:38,258 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:38,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:38,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:38,565 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [401572345] [2019-12-07 16:25:38,566 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:38,566 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 16:25:38,566 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1700705200] [2019-12-07 16:25:38,566 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 16:25:38,566 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:38,566 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 16:25:38,566 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=258, Unknown=0, NotChecked=0, Total=306 [2019-12-07 16:25:38,566 INFO L87 Difference]: Start difference. First operand 6315 states and 17494 transitions. Second operand 18 states. [2019-12-07 16:25:41,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:41,251 INFO L93 Difference]: Finished difference Result 16538 states and 45554 transitions. [2019-12-07 16:25:41,251 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2019-12-07 16:25:41,251 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 68 [2019-12-07 16:25:41,251 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:41,264 INFO L225 Difference]: With dead ends: 16538 [2019-12-07 16:25:41,264 INFO L226 Difference]: Without dead ends: 15821 [2019-12-07 16:25:41,265 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 739 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=428, Invalid=2542, Unknown=0, NotChecked=0, Total=2970 [2019-12-07 16:25:41,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15821 states. [2019-12-07 16:25:41,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15821 to 6278. [2019-12-07 16:25:41,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6278 states. [2019-12-07 16:25:41,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6278 states to 6278 states and 17423 transitions. [2019-12-07 16:25:41,381 INFO L78 Accepts]: Start accepts. Automaton has 6278 states and 17423 transitions. Word has length 68 [2019-12-07 16:25:41,381 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:41,381 INFO L462 AbstractCegarLoop]: Abstraction has 6278 states and 17423 transitions. [2019-12-07 16:25:41,381 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 16:25:41,381 INFO L276 IsEmpty]: Start isEmpty. Operand 6278 states and 17423 transitions. [2019-12-07 16:25:41,385 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:25:41,385 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:41,385 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:41,385 INFO L410 AbstractCegarLoop]: === Iteration 29 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:41,386 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:41,386 INFO L82 PathProgramCache]: Analyzing trace with hash 932771090, now seen corresponding path program 7 times [2019-12-07 16:25:41,386 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:41,386 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [708507618] [2019-12-07 16:25:41,386 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:41,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:41,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:41,765 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [708507618] [2019-12-07 16:25:41,765 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:41,765 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2019-12-07 16:25:41,765 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [850861463] [2019-12-07 16:25:41,765 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 16:25:41,766 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:41,766 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 16:25:41,766 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=361, Unknown=0, NotChecked=0, Total=420 [2019-12-07 16:25:41,766 INFO L87 Difference]: Start difference. First operand 6278 states and 17423 transitions. Second operand 21 states. [2019-12-07 16:25:44,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:44,331 INFO L93 Difference]: Finished difference Result 17618 states and 48232 transitions. [2019-12-07 16:25:44,331 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2019-12-07 16:25:44,331 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 68 [2019-12-07 16:25:44,332 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:44,345 INFO L225 Difference]: With dead ends: 17618 [2019-12-07 16:25:44,346 INFO L226 Difference]: Without dead ends: 17116 [2019-12-07 16:25:44,347 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1147 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=656, Invalid=3634, Unknown=0, NotChecked=0, Total=4290 [2019-12-07 16:25:44,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17116 states. [2019-12-07 16:25:44,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17116 to 6112. [2019-12-07 16:25:44,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6112 states. [2019-12-07 16:25:44,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6112 states to 6112 states and 16954 transitions. [2019-12-07 16:25:44,468 INFO L78 Accepts]: Start accepts. Automaton has 6112 states and 16954 transitions. Word has length 68 [2019-12-07 16:25:44,468 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:44,468 INFO L462 AbstractCegarLoop]: Abstraction has 6112 states and 16954 transitions. [2019-12-07 16:25:44,468 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 16:25:44,468 INFO L276 IsEmpty]: Start isEmpty. Operand 6112 states and 16954 transitions. [2019-12-07 16:25:44,472 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:25:44,472 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:44,472 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:44,473 INFO L410 AbstractCegarLoop]: === Iteration 30 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:44,473 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:44,473 INFO L82 PathProgramCache]: Analyzing trace with hash -1425961288, now seen corresponding path program 8 times [2019-12-07 16:25:44,473 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:44,473 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1802700576] [2019-12-07 16:25:44,473 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:44,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:45,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:45,006 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1802700576] [2019-12-07 16:25:45,007 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:45,007 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [20] imperfect sequences [] total 20 [2019-12-07 16:25:45,007 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [847312340] [2019-12-07 16:25:45,007 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-12-07 16:25:45,007 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:45,007 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-12-07 16:25:45,007 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=394, Unknown=0, NotChecked=0, Total=462 [2019-12-07 16:25:45,007 INFO L87 Difference]: Start difference. First operand 6112 states and 16954 transitions. Second operand 22 states. [2019-12-07 16:25:50,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:50,832 INFO L93 Difference]: Finished difference Result 16233 states and 45182 transitions. [2019-12-07 16:25:50,833 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 86 states. [2019-12-07 16:25:50,833 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 68 [2019-12-07 16:25:50,833 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:50,853 INFO L225 Difference]: With dead ends: 16233 [2019-12-07 16:25:50,854 INFO L226 Difference]: Without dead ends: 15904 [2019-12-07 16:25:50,856 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 1 SyntacticMatches, 5 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2486 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1102, Invalid=7270, Unknown=0, NotChecked=0, Total=8372 [2019-12-07 16:25:50,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15904 states. [2019-12-07 16:25:50,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15904 to 6188. [2019-12-07 16:25:50,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6188 states. [2019-12-07 16:25:50,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6188 states to 6188 states and 17178 transitions. [2019-12-07 16:25:50,975 INFO L78 Accepts]: Start accepts. Automaton has 6188 states and 17178 transitions. Word has length 68 [2019-12-07 16:25:50,975 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:50,975 INFO L462 AbstractCegarLoop]: Abstraction has 6188 states and 17178 transitions. [2019-12-07 16:25:50,976 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-12-07 16:25:50,976 INFO L276 IsEmpty]: Start isEmpty. Operand 6188 states and 17178 transitions. [2019-12-07 16:25:50,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:25:50,980 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:50,980 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:50,980 INFO L410 AbstractCegarLoop]: === Iteration 31 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:50,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:50,980 INFO L82 PathProgramCache]: Analyzing trace with hash 556311610, now seen corresponding path program 9 times [2019-12-07 16:25:50,980 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:50,980 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1649856354] [2019-12-07 16:25:50,980 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:50,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:51,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:51,537 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1649856354] [2019-12-07 16:25:51,537 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:51,537 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2019-12-07 16:25:51,537 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [895068990] [2019-12-07 16:25:51,537 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-12-07 16:25:51,537 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:51,537 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 16:25:51,537 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=69, Invalid=437, Unknown=0, NotChecked=0, Total=506 [2019-12-07 16:25:51,538 INFO L87 Difference]: Start difference. First operand 6188 states and 17178 transitions. Second operand 23 states. [2019-12-07 16:25:59,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:25:59,219 INFO L93 Difference]: Finished difference Result 17074 states and 47394 transitions. [2019-12-07 16:25:59,220 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2019-12-07 16:25:59,220 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 68 [2019-12-07 16:25:59,220 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:25:59,233 INFO L225 Difference]: With dead ends: 17074 [2019-12-07 16:25:59,234 INFO L226 Difference]: Without dead ends: 16981 [2019-12-07 16:25:59,235 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 89 GetRequests, 1 SyntacticMatches, 5 SemanticMatches, 83 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2124 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1005, Invalid=6135, Unknown=0, NotChecked=0, Total=7140 [2019-12-07 16:25:59,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16981 states. [2019-12-07 16:25:59,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16981 to 6173. [2019-12-07 16:25:59,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6173 states. [2019-12-07 16:25:59,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6173 states to 6173 states and 17116 transitions. [2019-12-07 16:25:59,357 INFO L78 Accepts]: Start accepts. Automaton has 6173 states and 17116 transitions. Word has length 68 [2019-12-07 16:25:59,357 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:25:59,357 INFO L462 AbstractCegarLoop]: Abstraction has 6173 states and 17116 transitions. [2019-12-07 16:25:59,358 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-12-07 16:25:59,358 INFO L276 IsEmpty]: Start isEmpty. Operand 6173 states and 17116 transitions. [2019-12-07 16:25:59,362 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:25:59,362 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:25:59,362 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:25:59,362 INFO L410 AbstractCegarLoop]: === Iteration 32 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:25:59,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:25:59,362 INFO L82 PathProgramCache]: Analyzing trace with hash 261877780, now seen corresponding path program 10 times [2019-12-07 16:25:59,362 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:25:59,362 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1898312055] [2019-12-07 16:25:59,362 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:25:59,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:25:59,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:25:59,690 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1898312055] [2019-12-07 16:25:59,690 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:25:59,690 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2019-12-07 16:25:59,691 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1079536066] [2019-12-07 16:25:59,691 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-12-07 16:25:59,691 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:25:59,691 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 16:25:59,691 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2019-12-07 16:25:59,691 INFO L87 Difference]: Start difference. First operand 6173 states and 17116 transitions. Second operand 20 states. [2019-12-07 16:26:01,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:26:01,728 INFO L93 Difference]: Finished difference Result 18839 states and 51386 transitions. [2019-12-07 16:26:01,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2019-12-07 16:26:01,728 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 68 [2019-12-07 16:26:01,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:26:01,743 INFO L225 Difference]: With dead ends: 18839 [2019-12-07 16:26:01,743 INFO L226 Difference]: Without dead ends: 18070 [2019-12-07 16:26:01,744 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 66 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1054 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=594, Invalid=3312, Unknown=0, NotChecked=0, Total=3906 [2019-12-07 16:26:01,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18070 states. [2019-12-07 16:26:01,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18070 to 6430. [2019-12-07 16:26:01,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6430 states. [2019-12-07 16:26:01,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6430 states to 6430 states and 17869 transitions. [2019-12-07 16:26:01,872 INFO L78 Accepts]: Start accepts. Automaton has 6430 states and 17869 transitions. Word has length 68 [2019-12-07 16:26:01,872 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:26:01,872 INFO L462 AbstractCegarLoop]: Abstraction has 6430 states and 17869 transitions. [2019-12-07 16:26:01,872 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-12-07 16:26:01,872 INFO L276 IsEmpty]: Start isEmpty. Operand 6430 states and 17869 transitions. [2019-12-07 16:26:01,876 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:26:01,876 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:26:01,877 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:26:01,877 INFO L410 AbstractCegarLoop]: === Iteration 33 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:26:01,877 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:26:01,877 INFO L82 PathProgramCache]: Analyzing trace with hash -133778180, now seen corresponding path program 11 times [2019-12-07 16:26:01,877 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:26:01,877 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [106002389] [2019-12-07 16:26:01,877 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:26:01,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:26:02,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:26:02,447 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [106002389] [2019-12-07 16:26:02,447 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:26:02,447 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2019-12-07 16:26:02,447 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2135414251] [2019-12-07 16:26:02,447 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-12-07 16:26:02,447 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:26:02,447 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 16:26:02,448 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=70, Invalid=436, Unknown=0, NotChecked=0, Total=506 [2019-12-07 16:26:02,448 INFO L87 Difference]: Start difference. First operand 6430 states and 17869 transitions. Second operand 23 states. [2019-12-07 16:26:09,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:26:09,369 INFO L93 Difference]: Finished difference Result 19796 states and 54937 transitions. [2019-12-07 16:26:09,369 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 80 states. [2019-12-07 16:26:09,369 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 68 [2019-12-07 16:26:09,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:26:09,386 INFO L225 Difference]: With dead ends: 19796 [2019-12-07 16:26:09,386 INFO L226 Difference]: Without dead ends: 19631 [2019-12-07 16:26:09,388 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 3 SyntacticMatches, 4 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2301 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1134, Invalid=6698, Unknown=0, NotChecked=0, Total=7832 [2019-12-07 16:26:09,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19631 states. [2019-12-07 16:26:09,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19631 to 6852. [2019-12-07 16:26:09,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6852 states. [2019-12-07 16:26:09,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6852 states to 6852 states and 19085 transitions. [2019-12-07 16:26:09,530 INFO L78 Accepts]: Start accepts. Automaton has 6852 states and 19085 transitions. Word has length 68 [2019-12-07 16:26:09,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:26:09,530 INFO L462 AbstractCegarLoop]: Abstraction has 6852 states and 19085 transitions. [2019-12-07 16:26:09,530 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-12-07 16:26:09,530 INFO L276 IsEmpty]: Start isEmpty. Operand 6852 states and 19085 transitions. [2019-12-07 16:26:09,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:26:09,535 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:26:09,535 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:26:09,535 INFO L410 AbstractCegarLoop]: === Iteration 34 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:26:09,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:26:09,536 INFO L82 PathProgramCache]: Analyzing trace with hash 2056032048, now seen corresponding path program 12 times [2019-12-07 16:26:09,536 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:26:09,536 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1895956483] [2019-12-07 16:26:09,536 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:26:09,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 16:26:09,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 16:26:09,601 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 16:26:09,601 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 16:26:09,604 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [827] [827] ULTIMATE.startENTRY-->L807: Formula: (let ((.cse0 (store |v_#valid_66| 0 0))) (and (= 0 v_~__unbuffered_p2_EAX~0_40) (= v_~z$r_buff1_thd0~0_289 0) (= v_~z$r_buff0_thd1~0_194 0) (= v_~z$mem_tmp~0_22 0) (= v_~z$w_buff0~0_192 0) (= 0 v_~weak$$choice0~0_14) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1970~0.base_23| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1970~0.base_23|) |v_ULTIMATE.start_main_~#t1970~0.offset_17| 0)) |v_#memory_int_23|) (= v_~z~0_201 0) (= 0 v_~__unbuffered_p1_EAX~0_42) (= v_~y~0_14 0) (= v_~main$tmp_guard1~0_48 0) (= |v_#NULL.offset_3| 0) (= v_~z$w_buff0_used~0_745 0) (= v_~z$r_buff0_thd0~0_352 0) (= 0 v_~z$r_buff0_thd3~0_106) (= v_~z$w_buff1_used~0_381 0) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t1970~0.base_23| 4)) (= v_~main$tmp_guard0~0_23 0) (= v_~z$read_delayed_var~0.offset_7 0) (< 0 |v_#StackHeapBarrier_18|) (= v_~z$r_buff1_thd1~0_172 0) (= v_~__unbuffered_cnt~0_156 0) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$read_delayed~0_7 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t1970~0.base_23|) (= 0 v_~z$flush_delayed~0_41) (= 0 |v_ULTIMATE.start_main_~#t1970~0.offset_17|) (= v_~z$w_buff1~0_171 0) (= 0 v_~x~0_113) (= 0 |v_#NULL.base_3|) (= v_~weak$$choice2~0_111 0) (= (select .cse0 |v_ULTIMATE.start_main_~#t1970~0.base_23|) 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t1970~0.base_23| 1) |v_#valid_64|) (= v_~z$r_buff0_thd2~0_100 0) (= v_~z$r_buff1_thd2~0_185 0) (= 0 v_~z$r_buff1_thd3~0_186))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_66|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_20|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_26|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_185, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_34|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_27|, #NULL.offset=|v_#NULL.offset_3|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_24|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_72|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_42|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_24|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_72|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_35|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_352, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_42, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_40, ~z$mem_tmp~0=v_~z$mem_tmp~0_22, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_28|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_41|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_381, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_39|, ~z$flush_delayed~0=v_~z$flush_delayed~0_41, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_74|, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_149|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_172, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_106, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_156, ~x~0=v_~x~0_113, ULTIMATE.start_main_~#t1970~0.base=|v_ULTIMATE.start_main_~#t1970~0.base_23|, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_20|, ULTIMATE.start_main_~#t1970~0.offset=|v_ULTIMATE.start_main_~#t1970~0.offset_17|, ULTIMATE.start_main_~#t1971~0.base=|v_ULTIMATE.start_main_~#t1971~0.base_21|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_32|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_25|, ~z$w_buff1~0=v_~z$w_buff1~0_171, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_48, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_32|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_28|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_260|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_40|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_74|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_289, ~y~0=v_~y~0_14, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_100, ULTIMATE.start_main_~#t1972~0.offset=|v_ULTIMATE.start_main_~#t1972~0.offset_16|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_8|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_745, ~z$w_buff0~0=v_~z$w_buff0~0_192, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_186, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_24|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_44|, #NULL.base=|v_#NULL.base_3|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_41|, ULTIMATE.start_main_~#t1972~0.base=|v_ULTIMATE.start_main_~#t1972~0.base_20|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_149|, ULTIMATE.start_main_~#t1971~0.offset=|v_ULTIMATE.start_main_~#t1971~0.offset_16|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_23|, ~z~0=v_~z~0_201, ~weak$$choice2~0=v_~weak$$choice2~0_111, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_194} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_~#t1970~0.base, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_~#t1970~0.offset, ULTIMATE.start_main_~#t1971~0.base, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_~#t1972~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_~#t1972~0.base, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_~#t1971~0.offset, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 16:26:09,604 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L807-1-->L809: Formula: (and (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1971~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1971~0.base_11|) |v_ULTIMATE.start_main_~#t1971~0.offset_10| 1)) |v_#memory_int_15|) (= 0 |v_ULTIMATE.start_main_~#t1971~0.offset_10|) (= (store |v_#valid_36| |v_ULTIMATE.start_main_~#t1971~0.base_11| 1) |v_#valid_35|) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t1971~0.base_11|)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1971~0.base_11|) (= (store |v_#length_18| |v_ULTIMATE.start_main_~#t1971~0.base_11| 4) |v_#length_17|) (not (= 0 |v_ULTIMATE.start_main_~#t1971~0.base_11|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t1971~0.offset=|v_ULTIMATE.start_main_~#t1971~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, ULTIMATE.start_main_~#t1971~0.base=|v_ULTIMATE.start_main_~#t1971~0.base_11|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_15|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1971~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t1971~0.base, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 16:26:09,604 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] P0ENTRY-->L4-3: Formula: (and (= v_~z$w_buff0~0_42 v_~z$w_buff1~0_28) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 0)) (= v_P0Thread1of1ForFork0_~arg.offset_6 |v_P0Thread1of1ForFork0_#in~arg.offset_8|) (= |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| (ite (not (and (not (= 0 (mod v_~z$w_buff1_used~0_97 256))) (not (= (mod v_~z$w_buff0_used~0_206 256) 0)))) 1 0)) (= v_~z$w_buff0_used~0_207 v_~z$w_buff1_used~0_97) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~z$w_buff0_used~0_206 1) (= v_P0Thread1of1ForFork0_~arg.base_6 |v_P0Thread1of1ForFork0_#in~arg.base_8|) (= 2 v_~z$w_buff0~0_41)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_207, ~z$w_buff0~0=v_~z$w_buff0~0_42, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_206, ~z$w_buff0~0=v_~z$w_buff0~0_41, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_97, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|, ~z$w_buff1~0=v_~z$w_buff1~0_28, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_6, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_6} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 16:26:09,605 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L809-1-->L811: Formula: (and (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1972~0.base_12|) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1972~0.base_12| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1972~0.base_12|) |v_ULTIMATE.start_main_~#t1972~0.offset_10| 2))) (not (= |v_ULTIMATE.start_main_~#t1972~0.base_12| 0)) (= 0 |v_ULTIMATE.start_main_~#t1972~0.offset_10|) (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t1972~0.base_12|)) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1972~0.base_12| 4)) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t1972~0.base_12| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t1972~0.offset=|v_ULTIMATE.start_main_~#t1972~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, #length=|v_#length_15|, ULTIMATE.start_main_~#t1972~0.base=|v_ULTIMATE.start_main_~#t1972~0.base_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1972~0.offset, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1972~0.base] because there is no mapped edge [2019-12-07 16:26:09,605 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L745-->L745-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In159571 256))) (.cse0 (= (mod ~z$r_buff0_thd1~0_In159571 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |P0Thread1of1ForFork0_#t~ite5_Out159571|)) (and (= ~z$w_buff0_used~0_In159571 |P0Thread1of1ForFork0_#t~ite5_Out159571|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In159571, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In159571} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out159571|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In159571, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In159571} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 16:26:09,606 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L746-->L746-2: Formula: (let ((.cse2 (= (mod ~z$w_buff0_used~0_In-636046993 256) 0)) (.cse3 (= (mod ~z$r_buff0_thd1~0_In-636046993 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd1~0_In-636046993 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In-636046993 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork0_#t~ite6_Out-636046993|)) (and (= ~z$w_buff1_used~0_In-636046993 |P0Thread1of1ForFork0_#t~ite6_Out-636046993|) (or .cse2 .cse3) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-636046993, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-636046993, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-636046993, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-636046993} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out-636046993|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-636046993, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-636046993, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-636046993, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-636046993} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 16:26:09,606 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L747-->L748: Formula: (let ((.cse1 (= ~z$r_buff0_thd1~0_In-915845322 ~z$r_buff0_thd1~0_Out-915845322)) (.cse0 (= (mod ~z$w_buff0_used~0_In-915845322 256) 0)) (.cse2 (= 0 (mod ~z$r_buff0_thd1~0_In-915845322 256)))) (or (and .cse0 .cse1) (and .cse2 .cse1) (and (not .cse0) (not .cse2) (= 0 ~z$r_buff0_thd1~0_Out-915845322)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-915845322, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-915845322} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-915845322, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out-915845322|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out-915845322} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 16:26:09,606 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L748-->L748-2: Formula: (let ((.cse1 (= (mod ~z$r_buff1_thd1~0_In1527255017 256) 0)) (.cse0 (= (mod ~z$w_buff1_used~0_In1527255017 256) 0)) (.cse3 (= (mod ~z$r_buff0_thd1~0_In1527255017 256) 0)) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In1527255017 256)))) (or (and (or .cse0 .cse1) (= ~z$r_buff1_thd1~0_In1527255017 |P0Thread1of1ForFork0_#t~ite8_Out1527255017|) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2))) (= 0 |P0Thread1of1ForFork0_#t~ite8_Out1527255017|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1527255017, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1527255017, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1527255017, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1527255017} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1527255017, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out1527255017|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1527255017, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1527255017, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1527255017} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 16:26:09,606 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L748-2-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_66 1) v_~__unbuffered_cnt~0_65) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_64 |v_P0Thread1of1ForFork0_#t~ite8_42|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_42|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_41|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_64, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_65} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 16:26:09,607 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L764-2-->L764-4: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd2~0_In36371985 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In36371985 256) 0))) (or (and (= ~z$w_buff1~0_In36371985 |P1Thread1of1ForFork1_#t~ite9_Out36371985|) (not .cse0) (not .cse1)) (and (= ~z~0_In36371985 |P1Thread1of1ForFork1_#t~ite9_Out36371985|) (or .cse1 .cse0)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In36371985, ~z$w_buff1_used~0=~z$w_buff1_used~0_In36371985, ~z$w_buff1~0=~z$w_buff1~0_In36371985, ~z~0=~z~0_In36371985} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out36371985|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In36371985, ~z$w_buff1_used~0=~z$w_buff1_used~0_In36371985, ~z$w_buff1~0=~z$w_buff1~0_In36371985, ~z~0=~z~0_In36371985} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-12-07 16:26:09,607 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L764-4-->L765: Formula: (= v_~z~0_33 |v_P1Thread1of1ForFork1_#t~ite9_14|) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_14|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_13|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_19|, ~z~0=v_~z~0_33} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~z~0] because there is no mapped edge [2019-12-07 16:26:09,608 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L765-->L765-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd2~0_In-1957311214 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1957311214 256)))) (or (and (= |P1Thread1of1ForFork1_#t~ite11_Out-1957311214| ~z$w_buff0_used~0_In-1957311214) (or .cse0 .cse1)) (and (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite11_Out-1957311214|) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1957311214, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1957311214} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1957311214, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out-1957311214|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1957311214} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 16:26:09,608 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L784-2-->L784-4: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In-802701951 256) 0)) (.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In-802701951 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite15_Out-802701951| ~z$w_buff1~0_In-802701951) (not .cse0) (not .cse1)) (and (= |P2Thread1of1ForFork2_#t~ite15_Out-802701951| ~z~0_In-802701951) (or .cse0 .cse1)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-802701951, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-802701951, ~z$w_buff1~0=~z$w_buff1~0_In-802701951, ~z~0=~z~0_In-802701951} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-802701951|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-802701951, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-802701951, ~z$w_buff1~0=~z$w_buff1~0_In-802701951, ~z~0=~z~0_In-802701951} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 16:26:09,608 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L766-->L766-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In46320247 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In46320247 256))) (.cse3 (= (mod ~z$w_buff1_used~0_In46320247 256) 0)) (.cse2 (= (mod ~z$r_buff1_thd2~0_In46320247 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork1_#t~ite12_Out46320247|)) (and (or .cse0 .cse1) (or .cse3 .cse2) (= ~z$w_buff1_used~0_In46320247 |P1Thread1of1ForFork1_#t~ite12_Out46320247|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In46320247, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In46320247, ~z$w_buff1_used~0=~z$w_buff1_used~0_In46320247, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In46320247} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In46320247, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In46320247, ~z$w_buff1_used~0=~z$w_buff1_used~0_In46320247, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out46320247|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In46320247} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 16:26:09,608 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L767-->L767-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In-1683167558 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1683167558 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite13_Out-1683167558|)) (and (or .cse1 .cse0) (= ~z$r_buff0_thd2~0_In-1683167558 |P1Thread1of1ForFork1_#t~ite13_Out-1683167558|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1683167558, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1683167558} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1683167558, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-1683167558|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1683167558} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 16:26:09,609 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L784-4-->L785: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~z~0_45) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, ~z~0=v_~z~0_45, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_13|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~z~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 16:26:09,609 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L785-->L785-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-1179045677 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-1179045677 256)))) (or (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In-1179045677 |P2Thread1of1ForFork2_#t~ite17_Out-1179045677|)) (and (= 0 |P2Thread1of1ForFork2_#t~ite17_Out-1179045677|) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1179045677, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1179045677} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1179045677, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1179045677, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out-1179045677|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 16:26:09,609 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L786-->L786-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In-612522564 256))) (.cse1 (= (mod ~z$r_buff1_thd3~0_In-612522564 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In-612522564 256) 0)) (.cse2 (= 0 (mod ~z$r_buff0_thd3~0_In-612522564 256)))) (or (and (= ~z$w_buff1_used~0_In-612522564 |P2Thread1of1ForFork2_#t~ite18_Out-612522564|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork2_#t~ite18_Out-612522564|) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-612522564, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-612522564, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-612522564, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-612522564} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-612522564, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-612522564, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-612522564, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-612522564, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-612522564|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 16:26:09,609 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L787-->L787-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-1709604888 256) 0)) (.cse1 (= (mod ~z$r_buff0_thd3~0_In-1709604888 256) 0))) (or (and (= ~z$r_buff0_thd3~0_In-1709604888 |P2Thread1of1ForFork2_#t~ite19_Out-1709604888|) (or .cse0 .cse1)) (and (= |P2Thread1of1ForFork2_#t~ite19_Out-1709604888| 0) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1709604888, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1709604888} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1709604888, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1709604888, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-1709604888|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 16:26:09,610 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [769] [769] L788-->L788-2: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In-800330924 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd3~0_In-800330924 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-800330924 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd3~0_In-800330924 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork2_#t~ite20_Out-800330924| ~z$r_buff1_thd3~0_In-800330924)) (and (= |P2Thread1of1ForFork2_#t~ite20_Out-800330924| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-800330924, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-800330924, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-800330924, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-800330924} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-800330924, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-800330924|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-800330924, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-800330924, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-800330924} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 16:26:09,610 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L788-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite20_32| v_~z$r_buff1_thd3~0_66) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_73 1) v_~__unbuffered_cnt~0_72)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_73} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_31|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_66, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 16:26:09,610 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L768-->L768-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In1809829356 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In1809829356 256) 0)) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In1809829356 256))) (.cse3 (= (mod ~z$r_buff0_thd2~0_In1809829356 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork1_#t~ite14_Out1809829356| 0)) (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite14_Out1809829356| ~z$r_buff1_thd2~0_In1809829356) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1809829356, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1809829356, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1809829356, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1809829356} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1809829356, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1809829356, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1809829356, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out1809829356|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1809829356} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 16:26:09,610 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L768-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_38 1) v_~__unbuffered_cnt~0_37) (= |v_P1Thread1of1ForFork1_#t~ite14_28| v_~z$r_buff1_thd2~0_54) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_28|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_54, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_37, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_27|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 16:26:09,610 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L811-1-->L817: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 16:26:09,611 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L817-2-->L817-4: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In-1867632557 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1867632557 256)))) (or (and (or .cse0 .cse1) (= ~z~0_In-1867632557 |ULTIMATE.start_main_#t~ite24_Out-1867632557|)) (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In-1867632557 |ULTIMATE.start_main_#t~ite24_Out-1867632557|)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1867632557, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1867632557, ~z$w_buff1~0=~z$w_buff1~0_In-1867632557, ~z~0=~z~0_In-1867632557} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1867632557, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-1867632557|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1867632557, ~z$w_buff1~0=~z$w_buff1~0_In-1867632557, ~z~0=~z~0_In-1867632557} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 16:26:09,611 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L817-4-->L818: Formula: (= v_~z~0_21 |v_ULTIMATE.start_main_#t~ite24_9|) InVars {ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_9|} OutVars{ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_8|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_12|, ~z~0=v_~z~0_21} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25, ~z~0] because there is no mapped edge [2019-12-07 16:26:09,611 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L818-->L818-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In694862629 256))) (.cse0 (= (mod ~z$r_buff0_thd0~0_In694862629 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite26_Out694862629| ~z$w_buff0_used~0_In694862629)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite26_Out694862629| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In694862629, ~z$w_buff0_used~0=~z$w_buff0_used~0_In694862629} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In694862629, ~z$w_buff0_used~0=~z$w_buff0_used~0_In694862629, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out694862629|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 16:26:09,611 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L819-->L819-2: Formula: (let ((.cse3 (= (mod ~z$w_buff0_used~0_In67406370 256) 0)) (.cse2 (= (mod ~z$r_buff0_thd0~0_In67406370 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In67406370 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In67406370 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite27_Out67406370| 0)) (and (or .cse3 .cse2) (= ~z$w_buff1_used~0_In67406370 |ULTIMATE.start_main_#t~ite27_Out67406370|) (or .cse1 .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In67406370, ~z$w_buff0_used~0=~z$w_buff0_used~0_In67406370, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In67406370, ~z$w_buff1_used~0=~z$w_buff1_used~0_In67406370} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In67406370, ~z$w_buff0_used~0=~z$w_buff0_used~0_In67406370, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In67406370, ~z$w_buff1_used~0=~z$w_buff1_used~0_In67406370, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out67406370|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 16:26:09,612 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [780] [780] L820-->L820-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In853503343 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In853503343 256)))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite28_Out853503343| 0)) (and (or .cse1 .cse0) (= ~z$r_buff0_thd0~0_In853503343 |ULTIMATE.start_main_#t~ite28_Out853503343|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In853503343, ~z$w_buff0_used~0=~z$w_buff0_used~0_In853503343} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In853503343, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out853503343|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In853503343} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 16:26:09,612 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L821-->L821-2: Formula: (let ((.cse3 (= (mod ~z$w_buff0_used~0_In-516925516 256) 0)) (.cse2 (= (mod ~z$r_buff0_thd0~0_In-516925516 256) 0)) (.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In-516925516 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-516925516 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$r_buff1_thd0~0_In-516925516 |ULTIMATE.start_main_#t~ite29_Out-516925516|)) (and (= |ULTIMATE.start_main_#t~ite29_Out-516925516| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-516925516, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-516925516, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-516925516, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-516925516} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-516925516, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-516925516|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-516925516, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-516925516, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-516925516} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 16:26:09,616 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L833-->L834: Formula: (and (= v_~z$r_buff0_thd0~0_167 v_~z$r_buff0_thd0~0_166) (not (= (mod v_~weak$$choice2~0_39 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_167, ~weak$$choice2~0=v_~weak$$choice2~0_39} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_166, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_10|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_11|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_8|, ~weak$$choice2~0=v_~weak$$choice2~0_39} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 16:26:09,617 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L836-->L4: Formula: (and (= v_~z$mem_tmp~0_13 v_~z~0_134) (= 0 v_~z$flush_delayed~0_22) (= (mod v_~main$tmp_guard1~0_32 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (not (= (mod v_~z$flush_delayed~0_23 256) 0))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_13, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_23} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_13, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_17|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_22, ~z~0=v_~z~0_134, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 16:26:09,618 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_13, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 16:26:09,674 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 04:26:09 BasicIcfg [2019-12-07 16:26:09,674 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 16:26:09,674 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 16:26:09,674 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 16:26:09,675 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 16:26:09,675 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:23:13" (3/4) ... [2019-12-07 16:26:09,676 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 16:26:09,677 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [827] [827] ULTIMATE.startENTRY-->L807: Formula: (let ((.cse0 (store |v_#valid_66| 0 0))) (and (= 0 v_~__unbuffered_p2_EAX~0_40) (= v_~z$r_buff1_thd0~0_289 0) (= v_~z$r_buff0_thd1~0_194 0) (= v_~z$mem_tmp~0_22 0) (= v_~z$w_buff0~0_192 0) (= 0 v_~weak$$choice0~0_14) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1970~0.base_23| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1970~0.base_23|) |v_ULTIMATE.start_main_~#t1970~0.offset_17| 0)) |v_#memory_int_23|) (= v_~z~0_201 0) (= 0 v_~__unbuffered_p1_EAX~0_42) (= v_~y~0_14 0) (= v_~main$tmp_guard1~0_48 0) (= |v_#NULL.offset_3| 0) (= v_~z$w_buff0_used~0_745 0) (= v_~z$r_buff0_thd0~0_352 0) (= 0 v_~z$r_buff0_thd3~0_106) (= v_~z$w_buff1_used~0_381 0) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t1970~0.base_23| 4)) (= v_~main$tmp_guard0~0_23 0) (= v_~z$read_delayed_var~0.offset_7 0) (< 0 |v_#StackHeapBarrier_18|) (= v_~z$r_buff1_thd1~0_172 0) (= v_~__unbuffered_cnt~0_156 0) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$read_delayed~0_7 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t1970~0.base_23|) (= 0 v_~z$flush_delayed~0_41) (= 0 |v_ULTIMATE.start_main_~#t1970~0.offset_17|) (= v_~z$w_buff1~0_171 0) (= 0 v_~x~0_113) (= 0 |v_#NULL.base_3|) (= v_~weak$$choice2~0_111 0) (= (select .cse0 |v_ULTIMATE.start_main_~#t1970~0.base_23|) 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t1970~0.base_23| 1) |v_#valid_64|) (= v_~z$r_buff0_thd2~0_100 0) (= v_~z$r_buff1_thd2~0_185 0) (= 0 v_~z$r_buff1_thd3~0_186))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_66|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_20|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_26|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_185, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_34|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_27|, #NULL.offset=|v_#NULL.offset_3|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_24|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_72|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_42|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_24|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_72|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_35|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_352, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_42, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_40, ~z$mem_tmp~0=v_~z$mem_tmp~0_22, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_28|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_41|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_381, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_39|, ~z$flush_delayed~0=v_~z$flush_delayed~0_41, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_74|, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_149|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_172, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_106, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_156, ~x~0=v_~x~0_113, ULTIMATE.start_main_~#t1970~0.base=|v_ULTIMATE.start_main_~#t1970~0.base_23|, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_20|, ULTIMATE.start_main_~#t1970~0.offset=|v_ULTIMATE.start_main_~#t1970~0.offset_17|, ULTIMATE.start_main_~#t1971~0.base=|v_ULTIMATE.start_main_~#t1971~0.base_21|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_32|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_25|, ~z$w_buff1~0=v_~z$w_buff1~0_171, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_48, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_32|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_28|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_260|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_40|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_74|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_289, ~y~0=v_~y~0_14, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_100, ULTIMATE.start_main_~#t1972~0.offset=|v_ULTIMATE.start_main_~#t1972~0.offset_16|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_8|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_745, ~z$w_buff0~0=v_~z$w_buff0~0_192, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_186, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_24|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_44|, #NULL.base=|v_#NULL.base_3|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_41|, ULTIMATE.start_main_~#t1972~0.base=|v_ULTIMATE.start_main_~#t1972~0.base_20|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_149|, ULTIMATE.start_main_~#t1971~0.offset=|v_ULTIMATE.start_main_~#t1971~0.offset_16|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_23|, ~z~0=v_~z~0_201, ~weak$$choice2~0=v_~weak$$choice2~0_111, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_194} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_~#t1970~0.base, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_~#t1970~0.offset, ULTIMATE.start_main_~#t1971~0.base, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_~#t1972~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_~#t1972~0.base, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_~#t1971~0.offset, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 16:26:09,677 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L807-1-->L809: Formula: (and (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1971~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1971~0.base_11|) |v_ULTIMATE.start_main_~#t1971~0.offset_10| 1)) |v_#memory_int_15|) (= 0 |v_ULTIMATE.start_main_~#t1971~0.offset_10|) (= (store |v_#valid_36| |v_ULTIMATE.start_main_~#t1971~0.base_11| 1) |v_#valid_35|) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t1971~0.base_11|)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1971~0.base_11|) (= (store |v_#length_18| |v_ULTIMATE.start_main_~#t1971~0.base_11| 4) |v_#length_17|) (not (= 0 |v_ULTIMATE.start_main_~#t1971~0.base_11|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t1971~0.offset=|v_ULTIMATE.start_main_~#t1971~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, ULTIMATE.start_main_~#t1971~0.base=|v_ULTIMATE.start_main_~#t1971~0.base_11|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_15|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1971~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t1971~0.base, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 16:26:09,677 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] P0ENTRY-->L4-3: Formula: (and (= v_~z$w_buff0~0_42 v_~z$w_buff1~0_28) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 0)) (= v_P0Thread1of1ForFork0_~arg.offset_6 |v_P0Thread1of1ForFork0_#in~arg.offset_8|) (= |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| (ite (not (and (not (= 0 (mod v_~z$w_buff1_used~0_97 256))) (not (= (mod v_~z$w_buff0_used~0_206 256) 0)))) 1 0)) (= v_~z$w_buff0_used~0_207 v_~z$w_buff1_used~0_97) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~z$w_buff0_used~0_206 1) (= v_P0Thread1of1ForFork0_~arg.base_6 |v_P0Thread1of1ForFork0_#in~arg.base_8|) (= 2 v_~z$w_buff0~0_41)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_207, ~z$w_buff0~0=v_~z$w_buff0~0_42, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_206, ~z$w_buff0~0=v_~z$w_buff0~0_41, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_97, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|, ~z$w_buff1~0=v_~z$w_buff1~0_28, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_6, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_6} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 16:26:09,678 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L809-1-->L811: Formula: (and (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1972~0.base_12|) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1972~0.base_12| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1972~0.base_12|) |v_ULTIMATE.start_main_~#t1972~0.offset_10| 2))) (not (= |v_ULTIMATE.start_main_~#t1972~0.base_12| 0)) (= 0 |v_ULTIMATE.start_main_~#t1972~0.offset_10|) (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t1972~0.base_12|)) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1972~0.base_12| 4)) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t1972~0.base_12| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t1972~0.offset=|v_ULTIMATE.start_main_~#t1972~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, #length=|v_#length_15|, ULTIMATE.start_main_~#t1972~0.base=|v_ULTIMATE.start_main_~#t1972~0.base_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1972~0.offset, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1972~0.base] because there is no mapped edge [2019-12-07 16:26:09,678 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L745-->L745-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In159571 256))) (.cse0 (= (mod ~z$r_buff0_thd1~0_In159571 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |P0Thread1of1ForFork0_#t~ite5_Out159571|)) (and (= ~z$w_buff0_used~0_In159571 |P0Thread1of1ForFork0_#t~ite5_Out159571|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In159571, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In159571} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out159571|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In159571, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In159571} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 16:26:09,678 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L746-->L746-2: Formula: (let ((.cse2 (= (mod ~z$w_buff0_used~0_In-636046993 256) 0)) (.cse3 (= (mod ~z$r_buff0_thd1~0_In-636046993 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd1~0_In-636046993 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In-636046993 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork0_#t~ite6_Out-636046993|)) (and (= ~z$w_buff1_used~0_In-636046993 |P0Thread1of1ForFork0_#t~ite6_Out-636046993|) (or .cse2 .cse3) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-636046993, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-636046993, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-636046993, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-636046993} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out-636046993|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-636046993, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-636046993, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-636046993, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-636046993} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 16:26:09,678 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L747-->L748: Formula: (let ((.cse1 (= ~z$r_buff0_thd1~0_In-915845322 ~z$r_buff0_thd1~0_Out-915845322)) (.cse0 (= (mod ~z$w_buff0_used~0_In-915845322 256) 0)) (.cse2 (= 0 (mod ~z$r_buff0_thd1~0_In-915845322 256)))) (or (and .cse0 .cse1) (and .cse2 .cse1) (and (not .cse0) (not .cse2) (= 0 ~z$r_buff0_thd1~0_Out-915845322)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-915845322, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-915845322} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-915845322, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out-915845322|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out-915845322} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 16:26:09,679 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L748-->L748-2: Formula: (let ((.cse1 (= (mod ~z$r_buff1_thd1~0_In1527255017 256) 0)) (.cse0 (= (mod ~z$w_buff1_used~0_In1527255017 256) 0)) (.cse3 (= (mod ~z$r_buff0_thd1~0_In1527255017 256) 0)) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In1527255017 256)))) (or (and (or .cse0 .cse1) (= ~z$r_buff1_thd1~0_In1527255017 |P0Thread1of1ForFork0_#t~ite8_Out1527255017|) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2))) (= 0 |P0Thread1of1ForFork0_#t~ite8_Out1527255017|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1527255017, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1527255017, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1527255017, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1527255017} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1527255017, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out1527255017|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1527255017, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1527255017, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1527255017} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 16:26:09,679 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L748-2-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_66 1) v_~__unbuffered_cnt~0_65) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_64 |v_P0Thread1of1ForFork0_#t~ite8_42|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_42|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_41|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_64, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_65} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 16:26:09,679 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L764-2-->L764-4: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd2~0_In36371985 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In36371985 256) 0))) (or (and (= ~z$w_buff1~0_In36371985 |P1Thread1of1ForFork1_#t~ite9_Out36371985|) (not .cse0) (not .cse1)) (and (= ~z~0_In36371985 |P1Thread1of1ForFork1_#t~ite9_Out36371985|) (or .cse1 .cse0)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In36371985, ~z$w_buff1_used~0=~z$w_buff1_used~0_In36371985, ~z$w_buff1~0=~z$w_buff1~0_In36371985, ~z~0=~z~0_In36371985} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out36371985|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In36371985, ~z$w_buff1_used~0=~z$w_buff1_used~0_In36371985, ~z$w_buff1~0=~z$w_buff1~0_In36371985, ~z~0=~z~0_In36371985} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-12-07 16:26:09,680 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L764-4-->L765: Formula: (= v_~z~0_33 |v_P1Thread1of1ForFork1_#t~ite9_14|) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_14|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_13|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_19|, ~z~0=v_~z~0_33} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~z~0] because there is no mapped edge [2019-12-07 16:26:09,680 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L765-->L765-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd2~0_In-1957311214 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1957311214 256)))) (or (and (= |P1Thread1of1ForFork1_#t~ite11_Out-1957311214| ~z$w_buff0_used~0_In-1957311214) (or .cse0 .cse1)) (and (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite11_Out-1957311214|) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1957311214, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1957311214} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1957311214, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out-1957311214|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1957311214} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 16:26:09,680 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L784-2-->L784-4: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In-802701951 256) 0)) (.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In-802701951 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite15_Out-802701951| ~z$w_buff1~0_In-802701951) (not .cse0) (not .cse1)) (and (= |P2Thread1of1ForFork2_#t~ite15_Out-802701951| ~z~0_In-802701951) (or .cse0 .cse1)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-802701951, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-802701951, ~z$w_buff1~0=~z$w_buff1~0_In-802701951, ~z~0=~z~0_In-802701951} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-802701951|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-802701951, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-802701951, ~z$w_buff1~0=~z$w_buff1~0_In-802701951, ~z~0=~z~0_In-802701951} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 16:26:09,680 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L766-->L766-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In46320247 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In46320247 256))) (.cse3 (= (mod ~z$w_buff1_used~0_In46320247 256) 0)) (.cse2 (= (mod ~z$r_buff1_thd2~0_In46320247 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork1_#t~ite12_Out46320247|)) (and (or .cse0 .cse1) (or .cse3 .cse2) (= ~z$w_buff1_used~0_In46320247 |P1Thread1of1ForFork1_#t~ite12_Out46320247|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In46320247, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In46320247, ~z$w_buff1_used~0=~z$w_buff1_used~0_In46320247, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In46320247} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In46320247, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In46320247, ~z$w_buff1_used~0=~z$w_buff1_used~0_In46320247, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out46320247|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In46320247} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 16:26:09,680 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L767-->L767-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In-1683167558 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1683167558 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite13_Out-1683167558|)) (and (or .cse1 .cse0) (= ~z$r_buff0_thd2~0_In-1683167558 |P1Thread1of1ForFork1_#t~ite13_Out-1683167558|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1683167558, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1683167558} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1683167558, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-1683167558|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1683167558} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 16:26:09,681 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L784-4-->L785: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~z~0_45) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, ~z~0=v_~z~0_45, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_13|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~z~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 16:26:09,681 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L785-->L785-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-1179045677 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-1179045677 256)))) (or (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In-1179045677 |P2Thread1of1ForFork2_#t~ite17_Out-1179045677|)) (and (= 0 |P2Thread1of1ForFork2_#t~ite17_Out-1179045677|) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1179045677, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1179045677} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1179045677, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1179045677, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out-1179045677|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 16:26:09,681 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L786-->L786-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In-612522564 256))) (.cse1 (= (mod ~z$r_buff1_thd3~0_In-612522564 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In-612522564 256) 0)) (.cse2 (= 0 (mod ~z$r_buff0_thd3~0_In-612522564 256)))) (or (and (= ~z$w_buff1_used~0_In-612522564 |P2Thread1of1ForFork2_#t~ite18_Out-612522564|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork2_#t~ite18_Out-612522564|) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-612522564, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-612522564, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-612522564, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-612522564} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-612522564, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-612522564, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-612522564, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-612522564, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-612522564|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 16:26:09,681 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L787-->L787-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-1709604888 256) 0)) (.cse1 (= (mod ~z$r_buff0_thd3~0_In-1709604888 256) 0))) (or (and (= ~z$r_buff0_thd3~0_In-1709604888 |P2Thread1of1ForFork2_#t~ite19_Out-1709604888|) (or .cse0 .cse1)) (and (= |P2Thread1of1ForFork2_#t~ite19_Out-1709604888| 0) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1709604888, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1709604888} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1709604888, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1709604888, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-1709604888|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 16:26:09,682 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [769] [769] L788-->L788-2: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In-800330924 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd3~0_In-800330924 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-800330924 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd3~0_In-800330924 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork2_#t~ite20_Out-800330924| ~z$r_buff1_thd3~0_In-800330924)) (and (= |P2Thread1of1ForFork2_#t~ite20_Out-800330924| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-800330924, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-800330924, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-800330924, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-800330924} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-800330924, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-800330924|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-800330924, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-800330924, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-800330924} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 16:26:09,682 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L788-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite20_32| v_~z$r_buff1_thd3~0_66) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_73 1) v_~__unbuffered_cnt~0_72)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_73} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_31|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_66, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 16:26:09,682 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L768-->L768-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In1809829356 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In1809829356 256) 0)) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In1809829356 256))) (.cse3 (= (mod ~z$r_buff0_thd2~0_In1809829356 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork1_#t~ite14_Out1809829356| 0)) (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite14_Out1809829356| ~z$r_buff1_thd2~0_In1809829356) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1809829356, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1809829356, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1809829356, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1809829356} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1809829356, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1809829356, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1809829356, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out1809829356|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1809829356} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 16:26:09,682 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L768-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_38 1) v_~__unbuffered_cnt~0_37) (= |v_P1Thread1of1ForFork1_#t~ite14_28| v_~z$r_buff1_thd2~0_54) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_28|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_54, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_37, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_27|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 16:26:09,682 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L811-1-->L817: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 16:26:09,682 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L817-2-->L817-4: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In-1867632557 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1867632557 256)))) (or (and (or .cse0 .cse1) (= ~z~0_In-1867632557 |ULTIMATE.start_main_#t~ite24_Out-1867632557|)) (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In-1867632557 |ULTIMATE.start_main_#t~ite24_Out-1867632557|)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1867632557, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1867632557, ~z$w_buff1~0=~z$w_buff1~0_In-1867632557, ~z~0=~z~0_In-1867632557} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1867632557, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-1867632557|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1867632557, ~z$w_buff1~0=~z$w_buff1~0_In-1867632557, ~z~0=~z~0_In-1867632557} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 16:26:09,682 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L817-4-->L818: Formula: (= v_~z~0_21 |v_ULTIMATE.start_main_#t~ite24_9|) InVars {ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_9|} OutVars{ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_8|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_12|, ~z~0=v_~z~0_21} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25, ~z~0] because there is no mapped edge [2019-12-07 16:26:09,682 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L818-->L818-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In694862629 256))) (.cse0 (= (mod ~z$r_buff0_thd0~0_In694862629 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite26_Out694862629| ~z$w_buff0_used~0_In694862629)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite26_Out694862629| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In694862629, ~z$w_buff0_used~0=~z$w_buff0_used~0_In694862629} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In694862629, ~z$w_buff0_used~0=~z$w_buff0_used~0_In694862629, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out694862629|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 16:26:09,683 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L819-->L819-2: Formula: (let ((.cse3 (= (mod ~z$w_buff0_used~0_In67406370 256) 0)) (.cse2 (= (mod ~z$r_buff0_thd0~0_In67406370 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In67406370 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In67406370 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite27_Out67406370| 0)) (and (or .cse3 .cse2) (= ~z$w_buff1_used~0_In67406370 |ULTIMATE.start_main_#t~ite27_Out67406370|) (or .cse1 .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In67406370, ~z$w_buff0_used~0=~z$w_buff0_used~0_In67406370, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In67406370, ~z$w_buff1_used~0=~z$w_buff1_used~0_In67406370} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In67406370, ~z$w_buff0_used~0=~z$w_buff0_used~0_In67406370, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In67406370, ~z$w_buff1_used~0=~z$w_buff1_used~0_In67406370, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out67406370|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 16:26:09,683 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [780] [780] L820-->L820-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In853503343 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In853503343 256)))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite28_Out853503343| 0)) (and (or .cse1 .cse0) (= ~z$r_buff0_thd0~0_In853503343 |ULTIMATE.start_main_#t~ite28_Out853503343|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In853503343, ~z$w_buff0_used~0=~z$w_buff0_used~0_In853503343} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In853503343, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out853503343|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In853503343} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 16:26:09,683 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L821-->L821-2: Formula: (let ((.cse3 (= (mod ~z$w_buff0_used~0_In-516925516 256) 0)) (.cse2 (= (mod ~z$r_buff0_thd0~0_In-516925516 256) 0)) (.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In-516925516 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-516925516 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$r_buff1_thd0~0_In-516925516 |ULTIMATE.start_main_#t~ite29_Out-516925516|)) (and (= |ULTIMATE.start_main_#t~ite29_Out-516925516| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-516925516, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-516925516, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-516925516, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-516925516} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-516925516, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-516925516|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-516925516, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-516925516, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-516925516} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 16:26:09,686 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L833-->L834: Formula: (and (= v_~z$r_buff0_thd0~0_167 v_~z$r_buff0_thd0~0_166) (not (= (mod v_~weak$$choice2~0_39 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_167, ~weak$$choice2~0=v_~weak$$choice2~0_39} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_166, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_10|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_11|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_8|, ~weak$$choice2~0=v_~weak$$choice2~0_39} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 16:26:09,686 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L836-->L4: Formula: (and (= v_~z$mem_tmp~0_13 v_~z~0_134) (= 0 v_~z$flush_delayed~0_22) (= (mod v_~main$tmp_guard1~0_32 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (not (= (mod v_~z$flush_delayed~0_23 256) 0))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_13, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_23} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_13, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_17|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_22, ~z~0=v_~z~0_134, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 16:26:09,686 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_13, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 16:26:09,740 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_e0ce35dc-272f-4007-a337-749b3e0d3967/bin/uautomizer/witness.graphml [2019-12-07 16:26:09,740 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 16:26:09,741 INFO L168 Benchmark]: Toolchain (without parser) took 176810.87 ms. Allocated memory was 1.0 GB in the beginning and 7.1 GB in the end (delta: 6.1 GB). Free memory was 934.0 MB in the beginning and 3.4 GB in the end (delta: -2.4 GB). Peak memory consumption was 3.7 GB. Max. memory is 11.5 GB. [2019-12-07 16:26:09,742 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 16:26:09,742 INFO L168 Benchmark]: CACSL2BoogieTranslator took 391.88 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 146.3 MB). Free memory was 934.0 MB in the beginning and 1.1 GB in the end (delta: -180.1 MB). Peak memory consumption was 18.2 MB. Max. memory is 11.5 GB. [2019-12-07 16:26:09,742 INFO L168 Benchmark]: Boogie Procedure Inliner took 42.38 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 16:26:09,742 INFO L168 Benchmark]: Boogie Preprocessor took 26.16 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 16:26:09,743 INFO L168 Benchmark]: RCFGBuilder took 404.67 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 50.1 MB). Peak memory consumption was 50.1 MB. Max. memory is 11.5 GB. [2019-12-07 16:26:09,743 INFO L168 Benchmark]: TraceAbstraction took 175876.72 ms. Allocated memory was 1.2 GB in the beginning and 7.1 GB in the end (delta: 6.0 GB). Free memory was 1.0 GB in the beginning and 3.4 GB in the end (delta: -2.4 GB). Peak memory consumption was 3.6 GB. Max. memory is 11.5 GB. [2019-12-07 16:26:09,743 INFO L168 Benchmark]: Witness Printer took 65.85 ms. Allocated memory is still 7.1 GB. Free memory was 3.4 GB in the beginning and 3.4 GB in the end (delta: 38.8 MB). Peak memory consumption was 38.8 MB. Max. memory is 11.5 GB. [2019-12-07 16:26:09,745 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 391.88 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 146.3 MB). Free memory was 934.0 MB in the beginning and 1.1 GB in the end (delta: -180.1 MB). Peak memory consumption was 18.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 42.38 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.16 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 404.67 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 50.1 MB). Peak memory consumption was 50.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 175876.72 ms. Allocated memory was 1.2 GB in the beginning and 7.1 GB in the end (delta: 6.0 GB). Free memory was 1.0 GB in the beginning and 3.4 GB in the end (delta: -2.4 GB). Peak memory consumption was 3.6 GB. Max. memory is 11.5 GB. * Witness Printer took 65.85 ms. Allocated memory is still 7.1 GB. Free memory was 3.4 GB in the beginning and 3.4 GB in the end (delta: 38.8 MB). Peak memory consumption was 38.8 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 2.9s, 175 ProgramPointsBefore, 95 ProgramPointsAfterwards, 212 TransitionsBefore, 106 TransitionsAfterwards, 17114 CoEnabledTransitionPairs, 7 FixpointIterations, 32 TrivialSequentialCompositions, 46 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 34 ConcurrentYvCompositions, 30 ChoiceCompositions, 5490 VarBasedMoverChecksPositive, 229 VarBasedMoverChecksNegative, 63 SemBasedMoverChecksPositive, 239 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.7s, 0 MoverChecksTotal, 80053 CheckedPairsTotal, 112 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L807] FCALL, FORK 0 pthread_create(&t1970, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L734] 1 z$r_buff1_thd0 = z$r_buff0_thd0 [L735] 1 z$r_buff1_thd1 = z$r_buff0_thd1 [L736] 1 z$r_buff1_thd2 = z$r_buff0_thd2 [L737] 1 z$r_buff1_thd3 = z$r_buff0_thd3 [L738] 1 z$r_buff0_thd1 = (_Bool)1 [L741] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L744] EXPR 1 z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L809] FCALL, FORK 0 pthread_create(&t1971, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L744] 1 z = z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) [L745] 1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used [L746] 1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used [L811] FCALL, FORK 0 pthread_create(&t1972, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L758] 2 __unbuffered_p1_EAX = x [L761] 2 y = 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L764] 2 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L778] 3 __unbuffered_p2_EAX = y [L781] 3 z = 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=2] [L784] 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L765] 2 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used [L766] 2 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used [L767] 2 z$r_buff0_thd2 = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 [L785] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L786] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L787] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L817] 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L818] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L819] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L820] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L821] 0 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L824] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L825] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L826] 0 z$flush_delayed = weak$$choice2 [L827] 0 z$mem_tmp = z VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L828] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L828] 0 z = !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) [L829] EXPR 0 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L829] 0 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) [L830] EXPR 0 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L830] 0 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) [L831] EXPR 0 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L831] 0 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) [L832] EXPR 0 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L832] 0 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L834] EXPR 0 weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L834] 0 z$r_buff1_thd0 = weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L835] 0 main$tmp_guard1 = !(z == 2 && __unbuffered_p1_EAX == 1 && __unbuffered_p2_EAX == 1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 166 locations, 2 error locations. Result: UNSAFE, OverallTime: 175.7s, OverallIterations: 34, TraceHistogramMax: 1, AutomataDifference: 68.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 6440 SDtfs, 11486 SDslu, 31430 SDs, 0 SdLazy, 41378 SolverSat, 1235 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 29.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 957 GetRequests, 74 SyntacticMatches, 52 SemanticMatches, 831 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12993 ImplicationChecksByTransitivity, 14.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=245714occurred in iteration=7, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 83.5s AutomataMinimizationTime, 33 MinimizatonAttempts, 575777 StatesRemovedByMinimization, 31 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 5.0s InterpolantComputationTime, 1780 NumberOfCodeBlocks, 1780 NumberOfCodeBlocksAsserted, 34 NumberOfCheckSat, 1679 ConstructedInterpolants, 0 QuantifiedInterpolants, 674448 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 33 InterpolantComputations, 33 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...