./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe008_rmo.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_f7561b11-7f80-476d-97f0-1a45ce2175a4/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_f7561b11-7f80-476d-97f0-1a45ce2175a4/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_f7561b11-7f80-476d-97f0-1a45ce2175a4/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_f7561b11-7f80-476d-97f0-1a45ce2175a4/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe008_rmo.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_f7561b11-7f80-476d-97f0-1a45ce2175a4/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_f7561b11-7f80-476d-97f0-1a45ce2175a4/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1cab4ceea0126be7a5379a9e32896660842c307a ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 16:18:52,739 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 16:18:52,740 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 16:18:52,747 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 16:18:52,748 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 16:18:52,748 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 16:18:52,749 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 16:18:52,751 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 16:18:52,752 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 16:18:52,752 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 16:18:52,753 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 16:18:52,754 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 16:18:52,754 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 16:18:52,755 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 16:18:52,755 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 16:18:52,756 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 16:18:52,757 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 16:18:52,757 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 16:18:52,759 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 16:18:52,761 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 16:18:52,762 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 16:18:52,762 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 16:18:52,763 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 16:18:52,763 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 16:18:52,765 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 16:18:52,765 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 16:18:52,765 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 16:18:52,766 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 16:18:52,766 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 16:18:52,767 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 16:18:52,767 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 16:18:52,768 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 16:18:52,768 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 16:18:52,768 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 16:18:52,769 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 16:18:52,769 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 16:18:52,770 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 16:18:52,770 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 16:18:52,770 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 16:18:52,770 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 16:18:52,771 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 16:18:52,771 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_f7561b11-7f80-476d-97f0-1a45ce2175a4/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 16:18:52,781 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 16:18:52,781 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 16:18:52,782 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 16:18:52,782 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 16:18:52,782 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 16:18:52,782 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 16:18:52,783 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 16:18:52,783 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 16:18:52,783 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 16:18:52,783 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 16:18:52,783 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 16:18:52,783 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 16:18:52,783 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 16:18:52,784 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 16:18:52,784 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 16:18:52,784 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 16:18:52,784 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 16:18:52,784 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 16:18:52,784 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 16:18:52,784 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 16:18:52,785 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 16:18:52,785 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 16:18:52,785 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 16:18:52,785 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 16:18:52,785 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 16:18:52,785 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 16:18:52,785 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 16:18:52,785 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 16:18:52,786 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 16:18:52,786 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_f7561b11-7f80-476d-97f0-1a45ce2175a4/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1cab4ceea0126be7a5379a9e32896660842c307a [2019-12-07 16:18:52,887 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 16:18:52,898 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 16:18:52,901 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 16:18:52,902 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 16:18:52,902 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 16:18:52,903 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_f7561b11-7f80-476d-97f0-1a45ce2175a4/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe008_rmo.opt.i [2019-12-07 16:18:52,941 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_f7561b11-7f80-476d-97f0-1a45ce2175a4/bin/uautomizer/data/a91a00c8d/8375328cdacb4529ad6f79cd57ebfb95/FLAG4742e4504 [2019-12-07 16:18:53,403 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 16:18:53,404 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_f7561b11-7f80-476d-97f0-1a45ce2175a4/sv-benchmarks/c/pthread-wmm/safe008_rmo.opt.i [2019-12-07 16:18:53,414 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_f7561b11-7f80-476d-97f0-1a45ce2175a4/bin/uautomizer/data/a91a00c8d/8375328cdacb4529ad6f79cd57ebfb95/FLAG4742e4504 [2019-12-07 16:18:53,423 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_f7561b11-7f80-476d-97f0-1a45ce2175a4/bin/uautomizer/data/a91a00c8d/8375328cdacb4529ad6f79cd57ebfb95 [2019-12-07 16:18:53,425 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 16:18:53,426 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 16:18:53,426 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 16:18:53,426 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 16:18:53,429 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 16:18:53,429 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 04:18:53" (1/1) ... [2019-12-07 16:18:53,431 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3482028c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:18:53, skipping insertion in model container [2019-12-07 16:18:53,431 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 04:18:53" (1/1) ... [2019-12-07 16:18:53,436 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 16:18:53,462 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 16:18:53,701 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 16:18:53,709 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 16:18:53,754 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 16:18:53,802 INFO L208 MainTranslator]: Completed translation [2019-12-07 16:18:53,802 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:18:53 WrapperNode [2019-12-07 16:18:53,802 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 16:18:53,803 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 16:18:53,803 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 16:18:53,803 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 16:18:53,809 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:18:53" (1/1) ... [2019-12-07 16:18:53,823 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:18:53" (1/1) ... [2019-12-07 16:18:53,847 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 16:18:53,847 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 16:18:53,847 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 16:18:53,848 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 16:18:53,855 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:18:53" (1/1) ... [2019-12-07 16:18:53,855 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:18:53" (1/1) ... [2019-12-07 16:18:53,859 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:18:53" (1/1) ... [2019-12-07 16:18:53,859 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:18:53" (1/1) ... [2019-12-07 16:18:53,867 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:18:53" (1/1) ... [2019-12-07 16:18:53,869 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:18:53" (1/1) ... [2019-12-07 16:18:53,872 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:18:53" (1/1) ... [2019-12-07 16:18:53,876 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 16:18:53,876 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 16:18:53,876 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 16:18:53,876 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 16:18:53,877 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:18:53" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_f7561b11-7f80-476d-97f0-1a45ce2175a4/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 16:18:53,916 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 16:18:53,917 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 16:18:53,917 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 16:18:53,917 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 16:18:53,917 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 16:18:53,917 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 16:18:53,917 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 16:18:53,917 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 16:18:53,917 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 16:18:53,917 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 16:18:53,917 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 16:18:53,918 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 16:18:53,918 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 16:18:53,919 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 16:18:54,280 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 16:18:54,280 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 16:18:54,281 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:18:54 BoogieIcfgContainer [2019-12-07 16:18:54,281 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 16:18:54,281 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 16:18:54,281 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 16:18:54,283 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 16:18:54,283 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 04:18:53" (1/3) ... [2019-12-07 16:18:54,284 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6f437f45 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 04:18:54, skipping insertion in model container [2019-12-07 16:18:54,284 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:18:53" (2/3) ... [2019-12-07 16:18:54,284 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6f437f45 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 04:18:54, skipping insertion in model container [2019-12-07 16:18:54,285 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:18:54" (3/3) ... [2019-12-07 16:18:54,286 INFO L109 eAbstractionObserver]: Analyzing ICFG safe008_rmo.opt.i [2019-12-07 16:18:54,292 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 16:18:54,292 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 16:18:54,297 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 16:18:54,297 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 16:18:54,321 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,321 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,321 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,321 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,321 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,321 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,321 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,322 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,322 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,322 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,322 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,322 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,322 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,322 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,322 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,323 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,323 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,323 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,323 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,323 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,323 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,323 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,323 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,324 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,324 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,324 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,324 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,324 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,324 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,324 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,324 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,324 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,325 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,325 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,325 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,325 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,325 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,325 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,325 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,326 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,326 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,326 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,326 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,326 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,326 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,326 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,327 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,327 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,327 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,327 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,327 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,327 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,327 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,327 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,327 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,328 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,328 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,328 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,328 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,328 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,328 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,328 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,328 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,328 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,329 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,329 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,329 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,329 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,329 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,329 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,329 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,329 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,330 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,330 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,330 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,330 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,330 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,330 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,330 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,330 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,330 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,331 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,331 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,331 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,331 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,331 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,331 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,331 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,331 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,331 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,331 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,332 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,332 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,332 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 16:18:54,346 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 16:18:54,361 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 16:18:54,361 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 16:18:54,361 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 16:18:54,361 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 16:18:54,361 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 16:18:54,361 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 16:18:54,361 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 16:18:54,362 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 16:18:54,373 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 175 places, 212 transitions [2019-12-07 16:18:54,375 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 175 places, 212 transitions [2019-12-07 16:18:54,436 INFO L134 PetriNetUnfolder]: 47/209 cut-off events. [2019-12-07 16:18:54,436 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 16:18:54,446 INFO L76 FinitePrefix]: Finished finitePrefix Result has 219 conditions, 209 events. 47/209 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 585 event pairs. 9/169 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 16:18:54,460 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 175 places, 212 transitions [2019-12-07 16:18:54,496 INFO L134 PetriNetUnfolder]: 47/209 cut-off events. [2019-12-07 16:18:54,497 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 16:18:54,501 INFO L76 FinitePrefix]: Finished finitePrefix Result has 219 conditions, 209 events. 47/209 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 585 event pairs. 9/169 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 16:18:54,515 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 17114 [2019-12-07 16:18:54,516 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 16:18:57,222 WARN L192 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 89 DAG size of output: 87 [2019-12-07 16:18:57,311 INFO L206 etLargeBlockEncoding]: Checked pairs total: 80053 [2019-12-07 16:18:57,311 INFO L214 etLargeBlockEncoding]: Total number of compositions: 112 [2019-12-07 16:18:57,313 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 95 places, 106 transitions [2019-12-07 16:19:12,757 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 115670 states. [2019-12-07 16:19:12,759 INFO L276 IsEmpty]: Start isEmpty. Operand 115670 states. [2019-12-07 16:19:12,763 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-12-07 16:19:12,763 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:19:12,763 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-12-07 16:19:12,764 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:19:12,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:19:12,768 INFO L82 PathProgramCache]: Analyzing trace with hash 846448, now seen corresponding path program 1 times [2019-12-07 16:19:12,774 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:19:12,774 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [893804174] [2019-12-07 16:19:12,774 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:19:12,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:19:12,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:19:12,903 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [893804174] [2019-12-07 16:19:12,903 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:19:12,904 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 16:19:12,904 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269894315] [2019-12-07 16:19:12,907 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:19:12,907 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:19:12,916 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:19:12,916 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:19:12,917 INFO L87 Difference]: Start difference. First operand 115670 states. Second operand 3 states. [2019-12-07 16:19:13,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:19:13,750 INFO L93 Difference]: Finished difference Result 115182 states and 492924 transitions. [2019-12-07 16:19:13,751 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:19:13,752 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-12-07 16:19:13,752 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:19:14,264 INFO L225 Difference]: With dead ends: 115182 [2019-12-07 16:19:14,264 INFO L226 Difference]: Without dead ends: 112830 [2019-12-07 16:19:14,265 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:19:17,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112830 states. [2019-12-07 16:19:20,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112830 to 112830. [2019-12-07 16:19:20,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112830 states. [2019-12-07 16:19:21,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112830 states to 112830 states and 483320 transitions. [2019-12-07 16:19:21,090 INFO L78 Accepts]: Start accepts. Automaton has 112830 states and 483320 transitions. Word has length 3 [2019-12-07 16:19:21,090 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:19:21,090 INFO L462 AbstractCegarLoop]: Abstraction has 112830 states and 483320 transitions. [2019-12-07 16:19:21,090 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:19:21,091 INFO L276 IsEmpty]: Start isEmpty. Operand 112830 states and 483320 transitions. [2019-12-07 16:19:21,094 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 16:19:21,094 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:19:21,094 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:19:21,094 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:19:21,095 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:19:21,095 INFO L82 PathProgramCache]: Analyzing trace with hash -939919620, now seen corresponding path program 1 times [2019-12-07 16:19:21,095 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:19:21,095 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1758252282] [2019-12-07 16:19:21,095 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:19:21,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:19:21,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:19:21,161 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1758252282] [2019-12-07 16:19:21,161 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:19:21,161 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:19:21,161 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1013529775] [2019-12-07 16:19:21,162 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:19:21,162 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:19:21,162 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:19:21,163 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:19:21,163 INFO L87 Difference]: Start difference. First operand 112830 states and 483320 transitions. Second operand 4 states. [2019-12-07 16:19:22,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:19:22,121 INFO L93 Difference]: Finished difference Result 176302 states and 727515 transitions. [2019-12-07 16:19:22,122 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:19:22,122 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 16:19:22,122 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:19:22,603 INFO L225 Difference]: With dead ends: 176302 [2019-12-07 16:19:22,603 INFO L226 Difference]: Without dead ends: 176253 [2019-12-07 16:19:22,604 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:19:27,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176253 states. [2019-12-07 16:19:31,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176253 to 159436. [2019-12-07 16:19:31,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159436 states. [2019-12-07 16:19:31,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159436 states to 159436 states and 665691 transitions. [2019-12-07 16:19:31,925 INFO L78 Accepts]: Start accepts. Automaton has 159436 states and 665691 transitions. Word has length 11 [2019-12-07 16:19:31,926 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:19:31,926 INFO L462 AbstractCegarLoop]: Abstraction has 159436 states and 665691 transitions. [2019-12-07 16:19:31,926 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:19:31,926 INFO L276 IsEmpty]: Start isEmpty. Operand 159436 states and 665691 transitions. [2019-12-07 16:19:31,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 16:19:31,933 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:19:31,933 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:19:31,933 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:19:31,933 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:19:31,933 INFO L82 PathProgramCache]: Analyzing trace with hash 670018080, now seen corresponding path program 1 times [2019-12-07 16:19:31,934 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:19:31,934 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2084108048] [2019-12-07 16:19:31,934 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:19:31,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:19:31,993 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:19:31,993 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2084108048] [2019-12-07 16:19:31,993 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:19:31,993 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:19:31,994 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [380655657] [2019-12-07 16:19:31,994 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:19:31,994 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:19:31,994 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:19:31,994 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:19:31,994 INFO L87 Difference]: Start difference. First operand 159436 states and 665691 transitions. Second operand 4 states. [2019-12-07 16:19:33,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:19:33,159 INFO L93 Difference]: Finished difference Result 228428 states and 932375 transitions. [2019-12-07 16:19:33,160 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:19:33,160 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 16:19:33,160 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:19:33,744 INFO L225 Difference]: With dead ends: 228428 [2019-12-07 16:19:33,744 INFO L226 Difference]: Without dead ends: 228365 [2019-12-07 16:19:33,745 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:19:38,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228365 states. [2019-12-07 16:19:43,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228365 to 192396. [2019-12-07 16:19:43,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192396 states. [2019-12-07 16:19:44,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192396 states to 192396 states and 797806 transitions. [2019-12-07 16:19:44,483 INFO L78 Accepts]: Start accepts. Automaton has 192396 states and 797806 transitions. Word has length 13 [2019-12-07 16:19:44,484 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:19:44,484 INFO L462 AbstractCegarLoop]: Abstraction has 192396 states and 797806 transitions. [2019-12-07 16:19:44,484 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:19:44,484 INFO L276 IsEmpty]: Start isEmpty. Operand 192396 states and 797806 transitions. [2019-12-07 16:19:44,486 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 16:19:44,487 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:19:44,487 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:19:44,487 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:19:44,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:19:44,487 INFO L82 PathProgramCache]: Analyzing trace with hash -293312110, now seen corresponding path program 1 times [2019-12-07 16:19:44,487 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:19:44,487 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [844130013] [2019-12-07 16:19:44,487 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:19:44,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:19:44,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:19:44,529 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [844130013] [2019-12-07 16:19:44,529 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:19:44,529 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:19:44,529 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1252558926] [2019-12-07 16:19:44,530 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:19:44,530 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:19:44,530 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:19:44,530 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:19:44,530 INFO L87 Difference]: Start difference. First operand 192396 states and 797806 transitions. Second operand 4 states. [2019-12-07 16:19:46,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:19:46,154 INFO L93 Difference]: Finished difference Result 240534 states and 988069 transitions. [2019-12-07 16:19:46,154 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:19:46,154 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 16:19:46,155 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:19:46,763 INFO L225 Difference]: With dead ends: 240534 [2019-12-07 16:19:46,763 INFO L226 Difference]: Without dead ends: 240534 [2019-12-07 16:19:46,763 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:19:52,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 240534 states. [2019-12-07 16:19:55,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 240534 to 203638. [2019-12-07 16:19:55,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203638 states. [2019-12-07 16:19:55,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203638 states to 203638 states and 844577 transitions. [2019-12-07 16:19:55,931 INFO L78 Accepts]: Start accepts. Automaton has 203638 states and 844577 transitions. Word has length 13 [2019-12-07 16:19:55,931 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:19:55,931 INFO L462 AbstractCegarLoop]: Abstraction has 203638 states and 844577 transitions. [2019-12-07 16:19:55,931 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:19:55,932 INFO L276 IsEmpty]: Start isEmpty. Operand 203638 states and 844577 transitions. [2019-12-07 16:19:55,952 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 16:19:55,952 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:19:55,952 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:19:55,952 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:19:55,953 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:19:55,953 INFO L82 PathProgramCache]: Analyzing trace with hash 1303088540, now seen corresponding path program 1 times [2019-12-07 16:19:55,953 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:19:55,953 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [187807206] [2019-12-07 16:19:55,953 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:19:55,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:19:56,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:19:56,001 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [187807206] [2019-12-07 16:19:56,001 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:19:56,001 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:19:56,001 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1965156750] [2019-12-07 16:19:56,002 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:19:56,002 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:19:56,002 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:19:56,002 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:19:56,002 INFO L87 Difference]: Start difference. First operand 203638 states and 844577 transitions. Second operand 5 states. [2019-12-07 16:19:57,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:19:57,594 INFO L93 Difference]: Finished difference Result 300567 states and 1220027 transitions. [2019-12-07 16:19:57,595 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 16:19:57,595 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 16:19:57,595 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:20:01,468 INFO L225 Difference]: With dead ends: 300567 [2019-12-07 16:20:01,468 INFO L226 Difference]: Without dead ends: 300504 [2019-12-07 16:20:01,469 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 16:20:07,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 300504 states. [2019-12-07 16:20:10,613 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 300504 to 216214. [2019-12-07 16:20:10,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 216214 states. [2019-12-07 16:20:11,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 216214 states to 216214 states and 891891 transitions. [2019-12-07 16:20:11,260 INFO L78 Accepts]: Start accepts. Automaton has 216214 states and 891891 transitions. Word has length 19 [2019-12-07 16:20:11,260 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:20:11,260 INFO L462 AbstractCegarLoop]: Abstraction has 216214 states and 891891 transitions. [2019-12-07 16:20:11,260 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:20:11,261 INFO L276 IsEmpty]: Start isEmpty. Operand 216214 states and 891891 transitions. [2019-12-07 16:20:11,276 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 16:20:11,276 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:20:11,276 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:20:11,276 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:20:11,276 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:20:11,277 INFO L82 PathProgramCache]: Analyzing trace with hash -2105368373, now seen corresponding path program 1 times [2019-12-07 16:20:11,277 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:20:11,277 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1520705323] [2019-12-07 16:20:11,277 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:20:11,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:20:11,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:20:11,352 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1520705323] [2019-12-07 16:20:11,352 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:20:11,352 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:20:11,352 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1437423025] [2019-12-07 16:20:11,353 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:20:11,353 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:20:11,353 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:20:11,353 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:20:11,353 INFO L87 Difference]: Start difference. First operand 216214 states and 891891 transitions. Second operand 6 states. [2019-12-07 16:20:13,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:20:13,730 INFO L93 Difference]: Finished difference Result 344024 states and 1388585 transitions. [2019-12-07 16:20:13,730 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 16:20:13,730 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 19 [2019-12-07 16:20:13,731 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:20:15,102 INFO L225 Difference]: With dead ends: 344024 [2019-12-07 16:20:15,102 INFO L226 Difference]: Without dead ends: 343905 [2019-12-07 16:20:15,102 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2019-12-07 16:20:24,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 343905 states. [2019-12-07 16:20:27,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 343905 to 209983. [2019-12-07 16:20:27,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 209983 states. [2019-12-07 16:20:28,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209983 states to 209983 states and 866944 transitions. [2019-12-07 16:20:28,395 INFO L78 Accepts]: Start accepts. Automaton has 209983 states and 866944 transitions. Word has length 19 [2019-12-07 16:20:28,396 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:20:28,396 INFO L462 AbstractCegarLoop]: Abstraction has 209983 states and 866944 transitions. [2019-12-07 16:20:28,396 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:20:28,396 INFO L276 IsEmpty]: Start isEmpty. Operand 209983 states and 866944 transitions. [2019-12-07 16:20:28,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 16:20:28,411 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:20:28,411 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:20:28,411 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:20:28,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:20:28,412 INFO L82 PathProgramCache]: Analyzing trace with hash 550593021, now seen corresponding path program 1 times [2019-12-07 16:20:28,412 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:20:28,412 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763986465] [2019-12-07 16:20:28,412 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:20:28,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:20:28,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:20:28,453 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763986465] [2019-12-07 16:20:28,453 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:20:28,454 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:20:28,454 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [243563485] [2019-12-07 16:20:28,454 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:20:28,454 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:20:28,454 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:20:28,454 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:20:28,455 INFO L87 Difference]: Start difference. First operand 209983 states and 866944 transitions. Second operand 5 states. [2019-12-07 16:20:30,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:20:30,412 INFO L93 Difference]: Finished difference Result 306127 states and 1240602 transitions. [2019-12-07 16:20:30,412 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 16:20:30,413 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 16:20:30,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:20:31,174 INFO L225 Difference]: With dead ends: 306127 [2019-12-07 16:20:31,174 INFO L226 Difference]: Without dead ends: 306064 [2019-12-07 16:20:31,174 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 16:20:37,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 306064 states. [2019-12-07 16:20:41,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 306064 to 236120. [2019-12-07 16:20:41,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 236120 states. [2019-12-07 16:20:42,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236120 states to 236120 states and 971823 transitions. [2019-12-07 16:20:42,214 INFO L78 Accepts]: Start accepts. Automaton has 236120 states and 971823 transitions. Word has length 19 [2019-12-07 16:20:42,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:20:42,214 INFO L462 AbstractCegarLoop]: Abstraction has 236120 states and 971823 transitions. [2019-12-07 16:20:42,215 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:20:42,215 INFO L276 IsEmpty]: Start isEmpty. Operand 236120 states and 971823 transitions. [2019-12-07 16:20:42,259 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2019-12-07 16:20:42,259 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:20:42,259 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:20:42,259 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:20:42,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:20:42,259 INFO L82 PathProgramCache]: Analyzing trace with hash 1785546309, now seen corresponding path program 1 times [2019-12-07 16:20:42,260 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:20:42,260 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1226288071] [2019-12-07 16:20:42,260 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:20:42,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:20:42,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:20:42,359 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1226288071] [2019-12-07 16:20:42,359 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:20:42,359 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:20:42,359 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [67743339] [2019-12-07 16:20:42,359 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 16:20:42,359 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:20:42,359 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 16:20:42,360 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:20:42,360 INFO L87 Difference]: Start difference. First operand 236120 states and 971823 transitions. Second operand 7 states. [2019-12-07 16:20:47,347 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:20:47,348 INFO L93 Difference]: Finished difference Result 374697 states and 1513828 transitions. [2019-12-07 16:20:47,348 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 16:20:47,348 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 23 [2019-12-07 16:20:47,349 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:20:48,295 INFO L225 Difference]: With dead ends: 374697 [2019-12-07 16:20:48,296 INFO L226 Difference]: Without dead ends: 374578 [2019-12-07 16:20:48,296 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-12-07 16:20:55,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 374578 states. [2019-12-07 16:20:59,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 374578 to 241496. [2019-12-07 16:20:59,254 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 241496 states. [2019-12-07 16:21:00,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 241496 states to 241496 states and 993711 transitions. [2019-12-07 16:21:00,262 INFO L78 Accepts]: Start accepts. Automaton has 241496 states and 993711 transitions. Word has length 23 [2019-12-07 16:21:00,262 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:21:00,262 INFO L462 AbstractCegarLoop]: Abstraction has 241496 states and 993711 transitions. [2019-12-07 16:21:00,262 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 16:21:00,262 INFO L276 IsEmpty]: Start isEmpty. Operand 241496 states and 993711 transitions. [2019-12-07 16:21:00,321 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 16:21:00,321 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:21:00,321 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:21:00,321 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:21:00,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:21:00,322 INFO L82 PathProgramCache]: Analyzing trace with hash 956366417, now seen corresponding path program 1 times [2019-12-07 16:21:00,322 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:21:00,322 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661502644] [2019-12-07 16:21:00,322 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:21:00,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:21:00,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:21:00,368 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1661502644] [2019-12-07 16:21:00,368 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:21:00,368 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:21:00,368 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [985621249] [2019-12-07 16:21:00,368 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 16:21:00,369 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:21:00,369 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 16:21:00,369 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:21:00,369 INFO L87 Difference]: Start difference. First operand 241496 states and 993711 transitions. Second operand 6 states. [2019-12-07 16:21:02,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:21:02,693 INFO L93 Difference]: Finished difference Result 289219 states and 1176416 transitions. [2019-12-07 16:21:02,694 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 16:21:02,694 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2019-12-07 16:21:02,694 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:21:03,434 INFO L225 Difference]: With dead ends: 289219 [2019-12-07 16:21:03,434 INFO L226 Difference]: Without dead ends: 289072 [2019-12-07 16:21:03,434 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=81, Invalid=191, Unknown=0, NotChecked=0, Total=272 [2019-12-07 16:21:09,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 289072 states. [2019-12-07 16:21:13,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 289072 to 204092. [2019-12-07 16:21:13,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 204092 states. [2019-12-07 16:21:13,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204092 states to 204092 states and 844469 transitions. [2019-12-07 16:21:13,874 INFO L78 Accepts]: Start accepts. Automaton has 204092 states and 844469 transitions. Word has length 25 [2019-12-07 16:21:13,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:21:13,875 INFO L462 AbstractCegarLoop]: Abstraction has 204092 states and 844469 transitions. [2019-12-07 16:21:13,875 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 16:21:13,875 INFO L276 IsEmpty]: Start isEmpty. Operand 204092 states and 844469 transitions. [2019-12-07 16:21:13,941 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 16:21:13,942 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:21:13,942 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:21:13,942 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:21:13,942 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:21:13,942 INFO L82 PathProgramCache]: Analyzing trace with hash -826573092, now seen corresponding path program 1 times [2019-12-07 16:21:13,942 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:21:13,942 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1526729656] [2019-12-07 16:21:13,942 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:21:13,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:21:13,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:21:13,967 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1526729656] [2019-12-07 16:21:13,967 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:21:13,967 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:21:13,968 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [27840237] [2019-12-07 16:21:13,968 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:21:13,968 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:21:13,968 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:21:13,968 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:21:13,968 INFO L87 Difference]: Start difference. First operand 204092 states and 844469 transitions. Second operand 3 states. [2019-12-07 16:21:14,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:21:14,095 INFO L93 Difference]: Finished difference Result 40957 states and 132425 transitions. [2019-12-07 16:21:14,095 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:21:14,095 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 16:21:14,096 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:21:14,154 INFO L225 Difference]: With dead ends: 40957 [2019-12-07 16:21:14,154 INFO L226 Difference]: Without dead ends: 40957 [2019-12-07 16:21:14,154 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:21:14,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40957 states. [2019-12-07 16:21:15,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40957 to 40957. [2019-12-07 16:21:15,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40957 states. [2019-12-07 16:21:15,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40957 states to 40957 states and 132425 transitions. [2019-12-07 16:21:15,125 INFO L78 Accepts]: Start accepts. Automaton has 40957 states and 132425 transitions. Word has length 27 [2019-12-07 16:21:15,125 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:21:15,125 INFO L462 AbstractCegarLoop]: Abstraction has 40957 states and 132425 transitions. [2019-12-07 16:21:15,125 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:21:15,125 INFO L276 IsEmpty]: Start isEmpty. Operand 40957 states and 132425 transitions. [2019-12-07 16:21:15,144 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2019-12-07 16:21:15,145 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:21:15,145 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:21:15,145 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:21:15,145 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:21:15,145 INFO L82 PathProgramCache]: Analyzing trace with hash -181038669, now seen corresponding path program 1 times [2019-12-07 16:21:15,145 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:21:15,145 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1513842408] [2019-12-07 16:21:15,145 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:21:15,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:21:15,181 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:21:15,181 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1513842408] [2019-12-07 16:21:15,181 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:21:15,182 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:21:15,182 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497869390] [2019-12-07 16:21:15,182 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 16:21:15,182 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:21:15,182 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 16:21:15,182 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:21:15,182 INFO L87 Difference]: Start difference. First operand 40957 states and 132425 transitions. Second operand 4 states. [2019-12-07 16:21:15,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:21:15,206 INFO L93 Difference]: Finished difference Result 7713 states and 20774 transitions. [2019-12-07 16:21:15,206 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 16:21:15,207 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 39 [2019-12-07 16:21:15,207 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:21:15,213 INFO L225 Difference]: With dead ends: 7713 [2019-12-07 16:21:15,213 INFO L226 Difference]: Without dead ends: 7713 [2019-12-07 16:21:15,213 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 16:21:15,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7713 states. [2019-12-07 16:21:15,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7713 to 7601. [2019-12-07 16:21:15,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7601 states. [2019-12-07 16:21:15,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7601 states to 7601 states and 20454 transitions. [2019-12-07 16:21:15,297 INFO L78 Accepts]: Start accepts. Automaton has 7601 states and 20454 transitions. Word has length 39 [2019-12-07 16:21:15,297 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:21:15,297 INFO L462 AbstractCegarLoop]: Abstraction has 7601 states and 20454 transitions. [2019-12-07 16:21:15,297 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 16:21:15,297 INFO L276 IsEmpty]: Start isEmpty. Operand 7601 states and 20454 transitions. [2019-12-07 16:21:15,302 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 16:21:15,303 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:21:15,303 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:21:15,303 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:21:15,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:21:15,303 INFO L82 PathProgramCache]: Analyzing trace with hash -118101162, now seen corresponding path program 1 times [2019-12-07 16:21:15,303 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:21:15,303 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [298246524] [2019-12-07 16:21:15,303 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:21:15,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:21:15,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:21:15,345 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [298246524] [2019-12-07 16:21:15,345 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:21:15,345 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 16:21:15,345 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1618153763] [2019-12-07 16:21:15,345 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:21:15,345 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:21:15,346 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:21:15,346 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:21:15,346 INFO L87 Difference]: Start difference. First operand 7601 states and 20454 transitions. Second operand 5 states. [2019-12-07 16:21:15,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:21:15,368 INFO L93 Difference]: Finished difference Result 5139 states and 14727 transitions. [2019-12-07 16:21:15,369 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 16:21:15,369 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-12-07 16:21:15,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:21:15,373 INFO L225 Difference]: With dead ends: 5139 [2019-12-07 16:21:15,373 INFO L226 Difference]: Without dead ends: 5139 [2019-12-07 16:21:15,373 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:21:15,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5139 states. [2019-12-07 16:21:15,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5139 to 4775. [2019-12-07 16:21:15,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4775 states. [2019-12-07 16:21:15,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4775 states to 4775 states and 13743 transitions. [2019-12-07 16:21:15,429 INFO L78 Accepts]: Start accepts. Automaton has 4775 states and 13743 transitions. Word has length 51 [2019-12-07 16:21:15,429 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:21:15,429 INFO L462 AbstractCegarLoop]: Abstraction has 4775 states and 13743 transitions. [2019-12-07 16:21:15,429 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:21:15,429 INFO L276 IsEmpty]: Start isEmpty. Operand 4775 states and 13743 transitions. [2019-12-07 16:21:15,432 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 16:21:15,432 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:21:15,432 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:21:15,432 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:21:15,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:21:15,433 INFO L82 PathProgramCache]: Analyzing trace with hash -1019045356, now seen corresponding path program 1 times [2019-12-07 16:21:15,433 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:21:15,433 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [800576214] [2019-12-07 16:21:15,433 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:21:15,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:21:15,497 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:21:15,498 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [800576214] [2019-12-07 16:21:15,498 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:21:15,498 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:21:15,498 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1124125035] [2019-12-07 16:21:15,498 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:21:15,498 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:21:15,498 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:21:15,499 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:21:15,499 INFO L87 Difference]: Start difference. First operand 4775 states and 13743 transitions. Second operand 5 states. [2019-12-07 16:21:15,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:21:15,692 INFO L93 Difference]: Finished difference Result 7334 states and 20910 transitions. [2019-12-07 16:21:15,693 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:21:15,693 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 65 [2019-12-07 16:21:15,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:21:15,699 INFO L225 Difference]: With dead ends: 7334 [2019-12-07 16:21:15,699 INFO L226 Difference]: Without dead ends: 7334 [2019-12-07 16:21:15,699 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 16:21:15,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7334 states. [2019-12-07 16:21:15,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7334 to 6411. [2019-12-07 16:21:15,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6411 states. [2019-12-07 16:21:15,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6411 states to 6411 states and 18363 transitions. [2019-12-07 16:21:15,780 INFO L78 Accepts]: Start accepts. Automaton has 6411 states and 18363 transitions. Word has length 65 [2019-12-07 16:21:15,780 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:21:15,780 INFO L462 AbstractCegarLoop]: Abstraction has 6411 states and 18363 transitions. [2019-12-07 16:21:15,780 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:21:15,780 INFO L276 IsEmpty]: Start isEmpty. Operand 6411 states and 18363 transitions. [2019-12-07 16:21:15,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 16:21:15,785 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:21:15,785 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:21:15,785 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:21:15,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:21:15,785 INFO L82 PathProgramCache]: Analyzing trace with hash -613444874, now seen corresponding path program 2 times [2019-12-07 16:21:15,785 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:21:15,785 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [209669940] [2019-12-07 16:21:15,785 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:21:15,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:21:15,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:21:15,841 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [209669940] [2019-12-07 16:21:15,841 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:21:15,841 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:21:15,841 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2103806342] [2019-12-07 16:21:15,842 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:21:15,842 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:21:15,842 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:21:15,842 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:21:15,842 INFO L87 Difference]: Start difference. First operand 6411 states and 18363 transitions. Second operand 3 states. [2019-12-07 16:21:15,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:21:15,862 INFO L93 Difference]: Finished difference Result 6147 states and 17335 transitions. [2019-12-07 16:21:15,863 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:21:15,863 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 16:21:15,863 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:21:15,868 INFO L225 Difference]: With dead ends: 6147 [2019-12-07 16:21:15,868 INFO L226 Difference]: Without dead ends: 6147 [2019-12-07 16:21:15,869 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:21:15,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6147 states. [2019-12-07 16:21:15,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6147 to 6003. [2019-12-07 16:21:15,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6003 states. [2019-12-07 16:21:15,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6003 states to 6003 states and 16939 transitions. [2019-12-07 16:21:15,943 INFO L78 Accepts]: Start accepts. Automaton has 6003 states and 16939 transitions. Word has length 65 [2019-12-07 16:21:15,943 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:21:15,943 INFO L462 AbstractCegarLoop]: Abstraction has 6003 states and 16939 transitions. [2019-12-07 16:21:15,943 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:21:15,943 INFO L276 IsEmpty]: Start isEmpty. Operand 6003 states and 16939 transitions. [2019-12-07 16:21:15,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 16:21:15,947 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:21:15,947 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:21:15,947 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:21:15,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:21:15,947 INFO L82 PathProgramCache]: Analyzing trace with hash 223341978, now seen corresponding path program 1 times [2019-12-07 16:21:15,947 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:21:15,947 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1708975318] [2019-12-07 16:21:15,948 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:21:15,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:21:15,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:21:16,000 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1708975318] [2019-12-07 16:21:16,000 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:21:16,000 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:21:16,000 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [948404783] [2019-12-07 16:21:16,000 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:21:16,000 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:21:16,000 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:21:16,000 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:21:16,001 INFO L87 Difference]: Start difference. First operand 6003 states and 16939 transitions. Second operand 5 states. [2019-12-07 16:21:16,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:21:16,184 INFO L93 Difference]: Finished difference Result 8512 states and 23814 transitions. [2019-12-07 16:21:16,184 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 16:21:16,184 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 66 [2019-12-07 16:21:16,185 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:21:16,192 INFO L225 Difference]: With dead ends: 8512 [2019-12-07 16:21:16,192 INFO L226 Difference]: Without dead ends: 8512 [2019-12-07 16:21:16,192 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:21:16,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8512 states. [2019-12-07 16:21:16,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8512 to 6604. [2019-12-07 16:21:16,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6604 states. [2019-12-07 16:21:16,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6604 states to 6604 states and 18681 transitions. [2019-12-07 16:21:16,281 INFO L78 Accepts]: Start accepts. Automaton has 6604 states and 18681 transitions. Word has length 66 [2019-12-07 16:21:16,282 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:21:16,282 INFO L462 AbstractCegarLoop]: Abstraction has 6604 states and 18681 transitions. [2019-12-07 16:21:16,282 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:21:16,282 INFO L276 IsEmpty]: Start isEmpty. Operand 6604 states and 18681 transitions. [2019-12-07 16:21:16,287 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 16:21:16,287 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:21:16,287 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:21:16,287 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:21:16,288 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:21:16,288 INFO L82 PathProgramCache]: Analyzing trace with hash -446701502, now seen corresponding path program 2 times [2019-12-07 16:21:16,288 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:21:16,288 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [101704591] [2019-12-07 16:21:16,288 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:21:16,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:21:16,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:21:16,326 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [101704591] [2019-12-07 16:21:16,326 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:21:16,326 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:21:16,327 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [680941059] [2019-12-07 16:21:16,327 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:21:16,327 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:21:16,327 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:21:16,327 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:21:16,327 INFO L87 Difference]: Start difference. First operand 6604 states and 18681 transitions. Second operand 3 states. [2019-12-07 16:21:16,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:21:16,345 INFO L93 Difference]: Finished difference Result 5808 states and 16174 transitions. [2019-12-07 16:21:16,345 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:21:16,345 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 16:21:16,345 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:21:16,350 INFO L225 Difference]: With dead ends: 5808 [2019-12-07 16:21:16,350 INFO L226 Difference]: Without dead ends: 5808 [2019-12-07 16:21:16,350 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:21:16,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5808 states. [2019-12-07 16:21:16,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5808 to 5484. [2019-12-07 16:21:16,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5484 states. [2019-12-07 16:21:16,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5484 states to 5484 states and 15292 transitions. [2019-12-07 16:21:16,411 INFO L78 Accepts]: Start accepts. Automaton has 5484 states and 15292 transitions. Word has length 66 [2019-12-07 16:21:16,411 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:21:16,411 INFO L462 AbstractCegarLoop]: Abstraction has 5484 states and 15292 transitions. [2019-12-07 16:21:16,411 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:21:16,411 INFO L276 IsEmpty]: Start isEmpty. Operand 5484 states and 15292 transitions. [2019-12-07 16:21:16,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 16:21:16,415 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:21:16,415 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:21:16,415 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:21:16,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:21:16,415 INFO L82 PathProgramCache]: Analyzing trace with hash 991626200, now seen corresponding path program 1 times [2019-12-07 16:21:16,415 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:21:16,415 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2060950424] [2019-12-07 16:21:16,415 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:21:16,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:21:16,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:21:16,449 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2060950424] [2019-12-07 16:21:16,449 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:21:16,450 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:21:16,450 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1319215617] [2019-12-07 16:21:16,450 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:21:16,450 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:21:16,450 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:21:16,450 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:21:16,450 INFO L87 Difference]: Start difference. First operand 5484 states and 15292 transitions. Second operand 3 states. [2019-12-07 16:21:16,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:21:16,483 INFO L93 Difference]: Finished difference Result 5483 states and 15290 transitions. [2019-12-07 16:21:16,483 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:21:16,483 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 16:21:16,483 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:21:16,487 INFO L225 Difference]: With dead ends: 5483 [2019-12-07 16:21:16,487 INFO L226 Difference]: Without dead ends: 5483 [2019-12-07 16:21:16,487 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:21:16,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5483 states. [2019-12-07 16:21:16,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5483 to 4426. [2019-12-07 16:21:16,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4426 states. [2019-12-07 16:21:16,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4426 states to 4426 states and 12361 transitions. [2019-12-07 16:21:16,544 INFO L78 Accepts]: Start accepts. Automaton has 4426 states and 12361 transitions. Word has length 67 [2019-12-07 16:21:16,544 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:21:16,544 INFO L462 AbstractCegarLoop]: Abstraction has 4426 states and 12361 transitions. [2019-12-07 16:21:16,544 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:21:16,544 INFO L276 IsEmpty]: Start isEmpty. Operand 4426 states and 12361 transitions. [2019-12-07 16:21:16,547 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:21:16,547 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:21:16,547 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:21:16,547 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:21:16,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:21:16,547 INFO L82 PathProgramCache]: Analyzing trace with hash 1277219082, now seen corresponding path program 1 times [2019-12-07 16:21:16,548 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:21:16,548 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1839484254] [2019-12-07 16:21:16,548 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:21:16,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:21:16,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:21:16,627 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1839484254] [2019-12-07 16:21:16,627 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:21:16,627 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:21:16,627 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [987878197] [2019-12-07 16:21:16,627 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 16:21:16,627 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:21:16,627 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 16:21:16,627 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:21:16,628 INFO L87 Difference]: Start difference. First operand 4426 states and 12361 transitions. Second operand 7 states. [2019-12-07 16:21:16,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:21:16,699 INFO L93 Difference]: Finished difference Result 8487 states and 23682 transitions. [2019-12-07 16:21:16,699 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 16:21:16,699 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 68 [2019-12-07 16:21:16,699 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:21:16,703 INFO L225 Difference]: With dead ends: 8487 [2019-12-07 16:21:16,703 INFO L226 Difference]: Without dead ends: 4885 [2019-12-07 16:21:16,703 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=61, Unknown=0, NotChecked=0, Total=90 [2019-12-07 16:21:16,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4885 states. [2019-12-07 16:21:16,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4885 to 4174. [2019-12-07 16:21:16,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4174 states. [2019-12-07 16:21:16,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4174 states to 4174 states and 11624 transitions. [2019-12-07 16:21:16,752 INFO L78 Accepts]: Start accepts. Automaton has 4174 states and 11624 transitions. Word has length 68 [2019-12-07 16:21:16,752 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:21:16,752 INFO L462 AbstractCegarLoop]: Abstraction has 4174 states and 11624 transitions. [2019-12-07 16:21:16,752 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 16:21:16,752 INFO L276 IsEmpty]: Start isEmpty. Operand 4174 states and 11624 transitions. [2019-12-07 16:21:16,754 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:21:16,754 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:21:16,754 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:21:16,755 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:21:16,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:21:16,755 INFO L82 PathProgramCache]: Analyzing trace with hash -1090372922, now seen corresponding path program 2 times [2019-12-07 16:21:16,755 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:21:16,755 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [316940507] [2019-12-07 16:21:16,755 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:21:16,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:21:16,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:21:16,909 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [316940507] [2019-12-07 16:21:16,909 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:21:16,909 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 16:21:16,910 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [214239178] [2019-12-07 16:21:16,910 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 16:21:16,910 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:21:16,910 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 16:21:16,910 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=129, Unknown=0, NotChecked=0, Total=156 [2019-12-07 16:21:16,910 INFO L87 Difference]: Start difference. First operand 4174 states and 11624 transitions. Second operand 13 states. [2019-12-07 16:21:17,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:21:17,368 INFO L93 Difference]: Finished difference Result 7214 states and 20004 transitions. [2019-12-07 16:21:17,369 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 16:21:17,369 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 68 [2019-12-07 16:21:17,370 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:21:17,377 INFO L225 Difference]: With dead ends: 7214 [2019-12-07 16:21:17,377 INFO L226 Difference]: Without dead ends: 6455 [2019-12-07 16:21:17,378 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 118 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=155, Invalid=601, Unknown=0, NotChecked=0, Total=756 [2019-12-07 16:21:17,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6455 states. [2019-12-07 16:21:17,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6455 to 5351. [2019-12-07 16:21:17,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5351 states. [2019-12-07 16:21:17,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5351 states to 5351 states and 14810 transitions. [2019-12-07 16:21:17,452 INFO L78 Accepts]: Start accepts. Automaton has 5351 states and 14810 transitions. Word has length 68 [2019-12-07 16:21:17,452 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:21:17,452 INFO L462 AbstractCegarLoop]: Abstraction has 5351 states and 14810 transitions. [2019-12-07 16:21:17,452 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 16:21:17,452 INFO L276 IsEmpty]: Start isEmpty. Operand 5351 states and 14810 transitions. [2019-12-07 16:21:17,456 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:21:17,456 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:21:17,456 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:21:17,456 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:21:17,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:21:17,456 INFO L82 PathProgramCache]: Analyzing trace with hash -1311051616, now seen corresponding path program 3 times [2019-12-07 16:21:17,456 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:21:17,456 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1741061858] [2019-12-07 16:21:17,456 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:21:17,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:21:17,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:21:17,606 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1741061858] [2019-12-07 16:21:17,607 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:21:17,607 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 16:21:17,607 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1149619195] [2019-12-07 16:21:17,607 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 16:21:17,607 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:21:17,607 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 16:21:17,607 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=129, Unknown=0, NotChecked=0, Total=156 [2019-12-07 16:21:17,608 INFO L87 Difference]: Start difference. First operand 5351 states and 14810 transitions. Second operand 13 states. [2019-12-07 16:21:18,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:21:18,585 INFO L93 Difference]: Finished difference Result 8219 states and 22676 transitions. [2019-12-07 16:21:18,585 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 16:21:18,585 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 68 [2019-12-07 16:21:18,585 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:21:18,591 INFO L225 Difference]: With dead ends: 8219 [2019-12-07 16:21:18,591 INFO L226 Difference]: Without dead ends: 7712 [2019-12-07 16:21:18,592 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 150 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=185, Invalid=685, Unknown=0, NotChecked=0, Total=870 [2019-12-07 16:21:18,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7712 states. [2019-12-07 16:21:18,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7712 to 5640. [2019-12-07 16:21:18,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5640 states. [2019-12-07 16:21:18,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5640 states to 5640 states and 15625 transitions. [2019-12-07 16:21:18,663 INFO L78 Accepts]: Start accepts. Automaton has 5640 states and 15625 transitions. Word has length 68 [2019-12-07 16:21:18,663 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:21:18,663 INFO L462 AbstractCegarLoop]: Abstraction has 5640 states and 15625 transitions. [2019-12-07 16:21:18,663 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 16:21:18,663 INFO L276 IsEmpty]: Start isEmpty. Operand 5640 states and 15625 transitions. [2019-12-07 16:21:18,667 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:21:18,667 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:21:18,667 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:21:18,667 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:21:18,667 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:21:18,667 INFO L82 PathProgramCache]: Analyzing trace with hash -526111866, now seen corresponding path program 4 times [2019-12-07 16:21:18,667 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:21:18,668 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [834696033] [2019-12-07 16:21:18,668 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:21:18,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:21:18,805 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:21:18,805 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [834696033] [2019-12-07 16:21:18,805 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:21:18,806 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 16:21:18,806 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [467097313] [2019-12-07 16:21:18,806 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 16:21:18,806 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:21:18,806 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 16:21:18,807 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=126, Unknown=0, NotChecked=0, Total=156 [2019-12-07 16:21:18,807 INFO L87 Difference]: Start difference. First operand 5640 states and 15625 transitions. Second operand 13 states. [2019-12-07 16:21:19,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:21:19,210 INFO L93 Difference]: Finished difference Result 8292 states and 22743 transitions. [2019-12-07 16:21:19,211 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-12-07 16:21:19,211 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 68 [2019-12-07 16:21:19,211 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:21:19,217 INFO L225 Difference]: With dead ends: 8292 [2019-12-07 16:21:19,217 INFO L226 Difference]: Without dead ends: 7701 [2019-12-07 16:21:19,217 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 158 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=175, Invalid=695, Unknown=0, NotChecked=0, Total=870 [2019-12-07 16:21:19,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7701 states. [2019-12-07 16:21:19,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7701 to 5476. [2019-12-07 16:21:19,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5476 states. [2019-12-07 16:21:19,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5476 states to 5476 states and 15095 transitions. [2019-12-07 16:21:19,290 INFO L78 Accepts]: Start accepts. Automaton has 5476 states and 15095 transitions. Word has length 68 [2019-12-07 16:21:19,290 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:21:19,290 INFO L462 AbstractCegarLoop]: Abstraction has 5476 states and 15095 transitions. [2019-12-07 16:21:19,290 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 16:21:19,290 INFO L276 IsEmpty]: Start isEmpty. Operand 5476 states and 15095 transitions. [2019-12-07 16:21:19,294 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 16:21:19,295 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:21:19,295 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:21:19,295 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:21:19,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:21:19,295 INFO L82 PathProgramCache]: Analyzing trace with hash 2056032048, now seen corresponding path program 5 times [2019-12-07 16:21:19,295 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:21:19,296 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [507486421] [2019-12-07 16:21:19,296 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:21:19,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 16:21:19,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 16:21:19,399 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 16:21:19,399 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 16:21:19,403 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [827] [827] ULTIMATE.startENTRY-->L807: Formula: (let ((.cse0 (store |v_#valid_66| 0 0))) (and (= 0 v_~__unbuffered_p2_EAX~0_40) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1976~0.base_23| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1976~0.base_23|) |v_ULTIMATE.start_main_~#t1976~0.offset_17| 0)) |v_#memory_int_23|) (= v_~z$r_buff1_thd0~0_289 0) (= v_~z$r_buff0_thd1~0_194 0) (= v_~z$mem_tmp~0_22 0) (= v_~z$w_buff0~0_192 0) (= 0 v_~weak$$choice0~0_14) (= v_~z~0_201 0) (= 0 v_~__unbuffered_p1_EAX~0_42) (= v_~y~0_14 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1976~0.base_23|)) (= v_~main$tmp_guard1~0_48 0) (= |v_#NULL.offset_3| 0) (= v_~z$w_buff0_used~0_745 0) (= v_~z$r_buff0_thd0~0_352 0) (= 0 v_~z$r_buff0_thd3~0_106) (= 0 |v_ULTIMATE.start_main_~#t1976~0.offset_17|) (= v_~z$w_buff1_used~0_381 0) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t1976~0.base_23| 4)) (= v_~main$tmp_guard0~0_23 0) (= v_~z$read_delayed_var~0.offset_7 0) (< 0 |v_#StackHeapBarrier_18|) (= v_~z$r_buff1_thd1~0_172 0) (= v_~__unbuffered_cnt~0_156 0) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$read_delayed~0_7 0) (= 0 v_~z$flush_delayed~0_41) (= |v_#valid_64| (store .cse0 |v_ULTIMATE.start_main_~#t1976~0.base_23| 1)) (= v_~z$w_buff1~0_171 0) (= 0 v_~x~0_113) (= 0 |v_#NULL.base_3|) (= v_~weak$$choice2~0_111 0) (= v_~z$r_buff0_thd2~0_100 0) (= v_~z$r_buff1_thd2~0_185 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t1976~0.base_23|) (= 0 v_~z$r_buff1_thd3~0_186))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_66|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_20|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_26|, ULTIMATE.start_main_~#t1977~0.offset=|v_ULTIMATE.start_main_~#t1977~0.offset_16|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_185, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_34|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_27|, #NULL.offset=|v_#NULL.offset_3|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_24|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_72|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_42|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_24|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_72|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_35|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_352, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_42, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_40, ~z$mem_tmp~0=v_~z$mem_tmp~0_22, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_28|, ULTIMATE.start_main_~#t1976~0.base=|v_ULTIMATE.start_main_~#t1976~0.base_23|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_41|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_381, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_39|, ~z$flush_delayed~0=v_~z$flush_delayed~0_41, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_74|, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_149|, ULTIMATE.start_main_~#t1976~0.offset=|v_ULTIMATE.start_main_~#t1976~0.offset_17|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_172, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_106, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_156, ~x~0=v_~x~0_113, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_20|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_32|, ULTIMATE.start_main_~#t1977~0.base=|v_ULTIMATE.start_main_~#t1977~0.base_21|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_25|, ~z$w_buff1~0=v_~z$w_buff1~0_171, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_48, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_32|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_28|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_260|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_40|, ULTIMATE.start_main_~#t1978~0.offset=|v_ULTIMATE.start_main_~#t1978~0.offset_16|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_74|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_289, ~y~0=v_~y~0_14, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_100, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_8|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_745, ~z$w_buff0~0=v_~z$w_buff0~0_192, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_186, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_24|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_44|, #NULL.base=|v_#NULL.base_3|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_41|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_149|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_23|, ~z~0=v_~z~0_201, ~weak$$choice2~0=v_~weak$$choice2~0_111, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_194, ULTIMATE.start_main_~#t1978~0.base=|v_ULTIMATE.start_main_~#t1978~0.base_20|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1977~0.offset, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_~#t1976~0.base, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_~#t1976~0.offset, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_~#t1977~0.base, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t1978~0.offset, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0, ULTIMATE.start_main_~#t1978~0.base] because there is no mapped edge [2019-12-07 16:21:19,403 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L807-1-->L809: Formula: (and (= |v_#valid_35| (store |v_#valid_36| |v_ULTIMATE.start_main_~#t1977~0.base_11| 1)) (not (= |v_ULTIMATE.start_main_~#t1977~0.base_11| 0)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1977~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1977~0.base_11|) |v_ULTIMATE.start_main_~#t1977~0.offset_10| 1)) |v_#memory_int_15|) (= |v_ULTIMATE.start_main_~#t1977~0.offset_10| 0) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1977~0.base_11|) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t1977~0.base_11|)) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1977~0.base_11| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, ULTIMATE.start_main_~#t1977~0.base=|v_ULTIMATE.start_main_~#t1977~0.base_11|, ULTIMATE.start_main_~#t1977~0.offset=|v_ULTIMATE.start_main_~#t1977~0.offset_10|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_15|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t1977~0.base, ULTIMATE.start_main_~#t1977~0.offset, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 16:21:19,404 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] P0ENTRY-->L4-3: Formula: (and (= v_~z$w_buff0~0_42 v_~z$w_buff1~0_28) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 0)) (= v_P0Thread1of1ForFork0_~arg.offset_6 |v_P0Thread1of1ForFork0_#in~arg.offset_8|) (= |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| (ite (not (and (not (= 0 (mod v_~z$w_buff1_used~0_97 256))) (not (= (mod v_~z$w_buff0_used~0_206 256) 0)))) 1 0)) (= v_~z$w_buff0_used~0_207 v_~z$w_buff1_used~0_97) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~z$w_buff0_used~0_206 1) (= v_P0Thread1of1ForFork0_~arg.base_6 |v_P0Thread1of1ForFork0_#in~arg.base_8|) (= 2 v_~z$w_buff0~0_41)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_207, ~z$w_buff0~0=v_~z$w_buff0~0_42, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_206, ~z$w_buff0~0=v_~z$w_buff0~0_41, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_97, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|, ~z$w_buff1~0=v_~z$w_buff1~0_28, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_6, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_6} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 16:21:19,405 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L809-1-->L811: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t1978~0.base_12|)) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1978~0.base_12| 4)) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1978~0.base_12|) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1978~0.base_12| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1978~0.base_12|) |v_ULTIMATE.start_main_~#t1978~0.offset_10| 2)) |v_#memory_int_13|) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t1978~0.base_12| 1)) (= (select |v_#valid_32| |v_ULTIMATE.start_main_~#t1978~0.base_12|) 0) (= |v_ULTIMATE.start_main_~#t1978~0.offset_10| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t1978~0.offset=|v_ULTIMATE.start_main_~#t1978~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, #length=|v_#length_15|, ULTIMATE.start_main_~#t1978~0.base=|v_ULTIMATE.start_main_~#t1978~0.base_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1978~0.offset, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1978~0.base] because there is no mapped edge [2019-12-07 16:21:19,405 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L745-->L745-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-226044341 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd1~0_In-226044341 256)))) (or (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In-226044341 |P0Thread1of1ForFork0_#t~ite5_Out-226044341|)) (and (= 0 |P0Thread1of1ForFork0_#t~ite5_Out-226044341|) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-226044341, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-226044341} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-226044341|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-226044341, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-226044341} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 16:21:19,406 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L746-->L746-2: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In45945055 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd1~0_In45945055 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In45945055 256) 0)) (.cse2 (= (mod ~z$r_buff0_thd1~0_In45945055 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite6_Out45945055| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P0Thread1of1ForFork0_#t~ite6_Out45945055| ~z$w_buff1_used~0_In45945055) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In45945055, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In45945055, ~z$w_buff1_used~0=~z$w_buff1_used~0_In45945055, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In45945055} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out45945055|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In45945055, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In45945055, ~z$w_buff1_used~0=~z$w_buff1_used~0_In45945055, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In45945055} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 16:21:19,406 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L747-->L748: Formula: (let ((.cse0 (= ~z$r_buff0_thd1~0_In-868846686 ~z$r_buff0_thd1~0_Out-868846686)) (.cse1 (= 0 (mod ~z$r_buff0_thd1~0_In-868846686 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-868846686 256)))) (or (and .cse0 .cse1) (and .cse2 .cse0) (and (not .cse1) (= 0 ~z$r_buff0_thd1~0_Out-868846686) (not .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-868846686, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-868846686} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-868846686, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out-868846686|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out-868846686} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 16:21:19,406 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L748-->L748-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In1177858547 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd1~0_In1177858547 256))) (.cse2 (= (mod ~z$r_buff0_thd1~0_In1177858547 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In1177858547 256)))) (or (and (or .cse0 .cse1) (= ~z$r_buff1_thd1~0_In1177858547 |P0Thread1of1ForFork0_#t~ite8_Out1177858547|) (or .cse2 .cse3)) (and (= |P0Thread1of1ForFork0_#t~ite8_Out1177858547| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1177858547, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1177858547, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1177858547, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1177858547} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1177858547, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out1177858547|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1177858547, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1177858547, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1177858547} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 16:21:19,406 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L748-2-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_66 1) v_~__unbuffered_cnt~0_65) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_64 |v_P0Thread1of1ForFork0_#t~ite8_42|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_42|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_41|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_64, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_65} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 16:21:19,408 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L764-2-->L764-4: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd2~0_In-1963015696 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1963015696 256)))) (or (and (not .cse0) (= |P1Thread1of1ForFork1_#t~ite9_Out-1963015696| ~z$w_buff1~0_In-1963015696) (not .cse1)) (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite9_Out-1963015696| ~z~0_In-1963015696)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1963015696, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1963015696, ~z$w_buff1~0=~z$w_buff1~0_In-1963015696, ~z~0=~z~0_In-1963015696} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out-1963015696|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1963015696, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1963015696, ~z$w_buff1~0=~z$w_buff1~0_In-1963015696, ~z~0=~z~0_In-1963015696} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-12-07 16:21:19,408 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L764-4-->L765: Formula: (= v_~z~0_33 |v_P1Thread1of1ForFork1_#t~ite9_14|) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_14|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_13|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_19|, ~z~0=v_~z~0_33} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~z~0] because there is no mapped edge [2019-12-07 16:21:19,408 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L765-->L765-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-1511865958 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In-1511865958 256) 0))) (or (and (= |P1Thread1of1ForFork1_#t~ite11_Out-1511865958| ~z$w_buff0_used~0_In-1511865958) (or .cse0 .cse1)) (and (not .cse0) (= |P1Thread1of1ForFork1_#t~ite11_Out-1511865958| 0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1511865958, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1511865958} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1511865958, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out-1511865958|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1511865958} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 16:21:19,409 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L784-2-->L784-4: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In-639636434 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In-639636434 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite15_Out-639636434| ~z$w_buff1~0_In-639636434) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~z~0_In-639636434 |P2Thread1of1ForFork2_#t~ite15_Out-639636434|)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-639636434, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-639636434, ~z$w_buff1~0=~z$w_buff1~0_In-639636434, ~z~0=~z~0_In-639636434} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-639636434|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-639636434, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-639636434, ~z$w_buff1~0=~z$w_buff1~0_In-639636434, ~z~0=~z~0_In-639636434} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 16:21:19,409 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L766-->L766-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In-724234301 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In-724234301 256) 0)) (.cse2 (= (mod ~z$r_buff0_thd2~0_In-724234301 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In-724234301 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$w_buff1_used~0_In-724234301 |P1Thread1of1ForFork1_#t~ite12_Out-724234301|)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork1_#t~ite12_Out-724234301|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-724234301, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-724234301, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-724234301, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-724234301} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-724234301, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-724234301, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-724234301, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-724234301|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-724234301} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 16:21:19,410 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L767-->L767-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-1716681304 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-1716681304 256)))) (or (and (= |P1Thread1of1ForFork1_#t~ite13_Out-1716681304| ~z$r_buff0_thd2~0_In-1716681304) (or .cse0 .cse1)) (and (= |P1Thread1of1ForFork1_#t~ite13_Out-1716681304| 0) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1716681304, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1716681304} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1716681304, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-1716681304|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1716681304} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 16:21:19,410 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L784-4-->L785: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~z~0_45) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, ~z~0=v_~z~0_45, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_13|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~z~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 16:21:19,410 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L785-->L785-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In2084538868 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In2084538868 256)))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite17_Out2084538868| ~z$w_buff0_used~0_In2084538868)) (and (= 0 |P2Thread1of1ForFork2_#t~ite17_Out2084538868|) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In2084538868, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In2084538868} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In2084538868, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In2084538868, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out2084538868|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 16:21:19,411 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L786-->L786-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In-1710650687 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In-1710650687 256) 0)) (.cse2 (= (mod ~z$r_buff1_thd3~0_In-1710650687 256) 0)) (.cse3 (= (mod ~z$w_buff1_used~0_In-1710650687 256) 0))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite18_Out-1710650687|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$w_buff1_used~0_In-1710650687 |P2Thread1of1ForFork2_#t~ite18_Out-1710650687|) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1710650687, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1710650687, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1710650687, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1710650687} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1710650687, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1710650687, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1710650687, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1710650687, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-1710650687|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 16:21:19,411 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L787-->L787-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In-343203905 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-343203905 256) 0))) (or (and (not .cse0) (= 0 |P2Thread1of1ForFork2_#t~ite19_Out-343203905|) (not .cse1)) (and (or .cse0 .cse1) (= ~z$r_buff0_thd3~0_In-343203905 |P2Thread1of1ForFork2_#t~ite19_Out-343203905|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-343203905, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-343203905} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-343203905, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-343203905, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-343203905|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 16:21:19,412 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [769] [769] L788-->L788-2: Formula: (let ((.cse2 (= (mod ~z$r_buff1_thd3~0_In1562810780 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In1562810780 256))) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In1562810780 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In1562810780 256)))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite20_Out1562810780|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$r_buff1_thd3~0_In1562810780 |P2Thread1of1ForFork2_#t~ite20_Out1562810780|) (or .cse2 .cse3) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1562810780, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1562810780, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1562810780, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1562810780} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1562810780, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out1562810780|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1562810780, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1562810780, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1562810780} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 16:21:19,412 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L788-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite20_32| v_~z$r_buff1_thd3~0_66) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_73 1) v_~__unbuffered_cnt~0_72)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_73} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_31|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_66, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 16:21:19,412 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L768-->L768-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-1850158423 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-1850158423 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd2~0_In-1850158423 256))) (.cse3 (= (mod ~z$w_buff1_used~0_In-1850158423 256) 0))) (or (and (= ~z$r_buff1_thd2~0_In-1850158423 |P1Thread1of1ForFork1_#t~ite14_Out-1850158423|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork1_#t~ite14_Out-1850158423| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1850158423, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1850158423, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1850158423, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1850158423} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1850158423, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1850158423, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1850158423, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-1850158423|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1850158423} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 16:21:19,412 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L768-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_38 1) v_~__unbuffered_cnt~0_37) (= |v_P1Thread1of1ForFork1_#t~ite14_28| v_~z$r_buff1_thd2~0_54) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_28|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_54, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_37, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_27|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 16:21:19,412 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L811-1-->L817: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 16:21:19,413 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L817-2-->L817-4: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In835122685 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In835122685 256) 0))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite24_Out835122685| ~z$w_buff1~0_In835122685)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite24_Out835122685| ~z~0_In835122685)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In835122685, ~z$w_buff1_used~0=~z$w_buff1_used~0_In835122685, ~z$w_buff1~0=~z$w_buff1~0_In835122685, ~z~0=~z~0_In835122685} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In835122685, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out835122685|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In835122685, ~z$w_buff1~0=~z$w_buff1~0_In835122685, ~z~0=~z~0_In835122685} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 16:21:19,413 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L817-4-->L818: Formula: (= v_~z~0_21 |v_ULTIMATE.start_main_#t~ite24_9|) InVars {ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_9|} OutVars{ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_8|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_12|, ~z~0=v_~z~0_21} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25, ~z~0] because there is no mapped edge [2019-12-07 16:21:19,413 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L818-->L818-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In1371602919 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In1371602919 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite26_Out1371602919| ~z$w_buff0_used~0_In1371602919)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite26_Out1371602919| 0) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1371602919, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1371602919} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1371602919, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1371602919, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out1371602919|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 16:21:19,413 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L819-->L819-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In180162478 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd0~0_In180162478 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In180162478 256) 0)) (.cse3 (= 0 (mod ~z$r_buff1_thd0~0_In180162478 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite27_Out180162478| ~z$w_buff1_used~0_In180162478)) (and (= 0 |ULTIMATE.start_main_#t~ite27_Out180162478|) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In180162478, ~z$w_buff0_used~0=~z$w_buff0_used~0_In180162478, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In180162478, ~z$w_buff1_used~0=~z$w_buff1_used~0_In180162478} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In180162478, ~z$w_buff0_used~0=~z$w_buff0_used~0_In180162478, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In180162478, ~z$w_buff1_used~0=~z$w_buff1_used~0_In180162478, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out180162478|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 16:21:19,414 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [780] [780] L820-->L820-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In313763121 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In313763121 256)))) (or (and (= ~z$r_buff0_thd0~0_In313763121 |ULTIMATE.start_main_#t~ite28_Out313763121|) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite28_Out313763121|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In313763121, ~z$w_buff0_used~0=~z$w_buff0_used~0_In313763121} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In313763121, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out313763121|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In313763121} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 16:21:19,414 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L821-->L821-2: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In161486046 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In161486046 256) 0)) (.cse2 (= (mod ~z$w_buff0_used~0_In161486046 256) 0)) (.cse3 (= (mod ~z$r_buff0_thd0~0_In161486046 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite29_Out161486046| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite29_Out161486046| ~z$r_buff1_thd0~0_In161486046) (or .cse2 .cse3)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In161486046, ~z$w_buff0_used~0=~z$w_buff0_used~0_In161486046, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In161486046, ~z$w_buff1_used~0=~z$w_buff1_used~0_In161486046} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In161486046, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out161486046|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In161486046, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In161486046, ~z$w_buff1_used~0=~z$w_buff1_used~0_In161486046} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 16:21:19,418 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L833-->L834: Formula: (and (= v_~z$r_buff0_thd0~0_167 v_~z$r_buff0_thd0~0_166) (not (= (mod v_~weak$$choice2~0_39 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_167, ~weak$$choice2~0=v_~weak$$choice2~0_39} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_166, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_10|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_11|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_8|, ~weak$$choice2~0=v_~weak$$choice2~0_39} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 16:21:19,419 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L836-->L4: Formula: (and (= v_~z$mem_tmp~0_13 v_~z~0_134) (= 0 v_~z$flush_delayed~0_22) (= (mod v_~main$tmp_guard1~0_32 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (not (= (mod v_~z$flush_delayed~0_23 256) 0))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_13, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_23} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_13, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_17|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_22, ~z~0=v_~z~0_134, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 16:21:19,419 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_13, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 16:21:19,484 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 04:21:19 BasicIcfg [2019-12-07 16:21:19,484 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 16:21:19,485 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 16:21:19,485 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 16:21:19,485 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 16:21:19,485 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:18:54" (3/4) ... [2019-12-07 16:21:19,487 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 16:21:19,488 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [827] [827] ULTIMATE.startENTRY-->L807: Formula: (let ((.cse0 (store |v_#valid_66| 0 0))) (and (= 0 v_~__unbuffered_p2_EAX~0_40) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1976~0.base_23| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1976~0.base_23|) |v_ULTIMATE.start_main_~#t1976~0.offset_17| 0)) |v_#memory_int_23|) (= v_~z$r_buff1_thd0~0_289 0) (= v_~z$r_buff0_thd1~0_194 0) (= v_~z$mem_tmp~0_22 0) (= v_~z$w_buff0~0_192 0) (= 0 v_~weak$$choice0~0_14) (= v_~z~0_201 0) (= 0 v_~__unbuffered_p1_EAX~0_42) (= v_~y~0_14 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1976~0.base_23|)) (= v_~main$tmp_guard1~0_48 0) (= |v_#NULL.offset_3| 0) (= v_~z$w_buff0_used~0_745 0) (= v_~z$r_buff0_thd0~0_352 0) (= 0 v_~z$r_buff0_thd3~0_106) (= 0 |v_ULTIMATE.start_main_~#t1976~0.offset_17|) (= v_~z$w_buff1_used~0_381 0) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t1976~0.base_23| 4)) (= v_~main$tmp_guard0~0_23 0) (= v_~z$read_delayed_var~0.offset_7 0) (< 0 |v_#StackHeapBarrier_18|) (= v_~z$r_buff1_thd1~0_172 0) (= v_~__unbuffered_cnt~0_156 0) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$read_delayed~0_7 0) (= 0 v_~z$flush_delayed~0_41) (= |v_#valid_64| (store .cse0 |v_ULTIMATE.start_main_~#t1976~0.base_23| 1)) (= v_~z$w_buff1~0_171 0) (= 0 v_~x~0_113) (= 0 |v_#NULL.base_3|) (= v_~weak$$choice2~0_111 0) (= v_~z$r_buff0_thd2~0_100 0) (= v_~z$r_buff1_thd2~0_185 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t1976~0.base_23|) (= 0 v_~z$r_buff1_thd3~0_186))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_66|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_20|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_26|, ULTIMATE.start_main_~#t1977~0.offset=|v_ULTIMATE.start_main_~#t1977~0.offset_16|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_185, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_34|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_27|, #NULL.offset=|v_#NULL.offset_3|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_24|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_72|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_42|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_24|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_72|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_35|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_352, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_42, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_40, ~z$mem_tmp~0=v_~z$mem_tmp~0_22, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_28|, ULTIMATE.start_main_~#t1976~0.base=|v_ULTIMATE.start_main_~#t1976~0.base_23|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_41|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_381, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_39|, ~z$flush_delayed~0=v_~z$flush_delayed~0_41, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_74|, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_149|, ULTIMATE.start_main_~#t1976~0.offset=|v_ULTIMATE.start_main_~#t1976~0.offset_17|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_172, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_106, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_156, ~x~0=v_~x~0_113, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_20|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_32|, ULTIMATE.start_main_~#t1977~0.base=|v_ULTIMATE.start_main_~#t1977~0.base_21|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_25|, ~z$w_buff1~0=v_~z$w_buff1~0_171, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_48, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_32|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_28|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_260|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_40|, ULTIMATE.start_main_~#t1978~0.offset=|v_ULTIMATE.start_main_~#t1978~0.offset_16|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_74|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_289, ~y~0=v_~y~0_14, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_100, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_8|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_745, ~z$w_buff0~0=v_~z$w_buff0~0_192, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_186, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_24|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_44|, #NULL.base=|v_#NULL.base_3|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_41|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_149|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_23|, ~z~0=v_~z~0_201, ~weak$$choice2~0=v_~weak$$choice2~0_111, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_194, ULTIMATE.start_main_~#t1978~0.base=|v_ULTIMATE.start_main_~#t1978~0.base_20|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1977~0.offset, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_~#t1976~0.base, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_~#t1976~0.offset, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_~#t1977~0.base, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t1978~0.offset, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0, ULTIMATE.start_main_~#t1978~0.base] because there is no mapped edge [2019-12-07 16:21:19,488 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L807-1-->L809: Formula: (and (= |v_#valid_35| (store |v_#valid_36| |v_ULTIMATE.start_main_~#t1977~0.base_11| 1)) (not (= |v_ULTIMATE.start_main_~#t1977~0.base_11| 0)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1977~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1977~0.base_11|) |v_ULTIMATE.start_main_~#t1977~0.offset_10| 1)) |v_#memory_int_15|) (= |v_ULTIMATE.start_main_~#t1977~0.offset_10| 0) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1977~0.base_11|) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t1977~0.base_11|)) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1977~0.base_11| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, ULTIMATE.start_main_~#t1977~0.base=|v_ULTIMATE.start_main_~#t1977~0.base_11|, ULTIMATE.start_main_~#t1977~0.offset=|v_ULTIMATE.start_main_~#t1977~0.offset_10|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_15|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t1977~0.base, ULTIMATE.start_main_~#t1977~0.offset, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 16:21:19,488 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] P0ENTRY-->L4-3: Formula: (and (= v_~z$w_buff0~0_42 v_~z$w_buff1~0_28) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 0)) (= v_P0Thread1of1ForFork0_~arg.offset_6 |v_P0Thread1of1ForFork0_#in~arg.offset_8|) (= |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| (ite (not (and (not (= 0 (mod v_~z$w_buff1_used~0_97 256))) (not (= (mod v_~z$w_buff0_used~0_206 256) 0)))) 1 0)) (= v_~z$w_buff0_used~0_207 v_~z$w_buff1_used~0_97) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~z$w_buff0_used~0_206 1) (= v_P0Thread1of1ForFork0_~arg.base_6 |v_P0Thread1of1ForFork0_#in~arg.base_8|) (= 2 v_~z$w_buff0~0_41)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_207, ~z$w_buff0~0=v_~z$w_buff0~0_42, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_206, ~z$w_buff0~0=v_~z$w_buff0~0_41, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_10, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_97, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|, ~z$w_buff1~0=v_~z$w_buff1~0_28, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_6, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_6} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 16:21:19,489 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L809-1-->L811: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t1978~0.base_12|)) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1978~0.base_12| 4)) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1978~0.base_12|) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1978~0.base_12| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1978~0.base_12|) |v_ULTIMATE.start_main_~#t1978~0.offset_10| 2)) |v_#memory_int_13|) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t1978~0.base_12| 1)) (= (select |v_#valid_32| |v_ULTIMATE.start_main_~#t1978~0.base_12|) 0) (= |v_ULTIMATE.start_main_~#t1978~0.offset_10| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t1978~0.offset=|v_ULTIMATE.start_main_~#t1978~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, #length=|v_#length_15|, ULTIMATE.start_main_~#t1978~0.base=|v_ULTIMATE.start_main_~#t1978~0.base_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1978~0.offset, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t1978~0.base] because there is no mapped edge [2019-12-07 16:21:19,489 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L745-->L745-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-226044341 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd1~0_In-226044341 256)))) (or (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In-226044341 |P0Thread1of1ForFork0_#t~ite5_Out-226044341|)) (and (= 0 |P0Thread1of1ForFork0_#t~ite5_Out-226044341|) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-226044341, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-226044341} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-226044341|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-226044341, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-226044341} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 16:21:19,490 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L746-->L746-2: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In45945055 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd1~0_In45945055 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In45945055 256) 0)) (.cse2 (= (mod ~z$r_buff0_thd1~0_In45945055 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite6_Out45945055| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P0Thread1of1ForFork0_#t~ite6_Out45945055| ~z$w_buff1_used~0_In45945055) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In45945055, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In45945055, ~z$w_buff1_used~0=~z$w_buff1_used~0_In45945055, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In45945055} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out45945055|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In45945055, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In45945055, ~z$w_buff1_used~0=~z$w_buff1_used~0_In45945055, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In45945055} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 16:21:19,490 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L747-->L748: Formula: (let ((.cse0 (= ~z$r_buff0_thd1~0_In-868846686 ~z$r_buff0_thd1~0_Out-868846686)) (.cse1 (= 0 (mod ~z$r_buff0_thd1~0_In-868846686 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-868846686 256)))) (or (and .cse0 .cse1) (and .cse2 .cse0) (and (not .cse1) (= 0 ~z$r_buff0_thd1~0_Out-868846686) (not .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-868846686, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-868846686} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-868846686, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out-868846686|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out-868846686} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 16:21:19,490 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L748-->L748-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In1177858547 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd1~0_In1177858547 256))) (.cse2 (= (mod ~z$r_buff0_thd1~0_In1177858547 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In1177858547 256)))) (or (and (or .cse0 .cse1) (= ~z$r_buff1_thd1~0_In1177858547 |P0Thread1of1ForFork0_#t~ite8_Out1177858547|) (or .cse2 .cse3)) (and (= |P0Thread1of1ForFork0_#t~ite8_Out1177858547| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1177858547, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1177858547, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1177858547, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1177858547} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1177858547, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out1177858547|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1177858547, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1177858547, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1177858547} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 16:21:19,491 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L748-2-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_66 1) v_~__unbuffered_cnt~0_65) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_64 |v_P0Thread1of1ForFork0_#t~ite8_42|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_42|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_41|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_64, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_65} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 16:21:19,492 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L764-2-->L764-4: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd2~0_In-1963015696 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1963015696 256)))) (or (and (not .cse0) (= |P1Thread1of1ForFork1_#t~ite9_Out-1963015696| ~z$w_buff1~0_In-1963015696) (not .cse1)) (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite9_Out-1963015696| ~z~0_In-1963015696)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1963015696, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1963015696, ~z$w_buff1~0=~z$w_buff1~0_In-1963015696, ~z~0=~z~0_In-1963015696} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out-1963015696|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1963015696, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1963015696, ~z$w_buff1~0=~z$w_buff1~0_In-1963015696, ~z~0=~z~0_In-1963015696} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-12-07 16:21:19,492 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L764-4-->L765: Formula: (= v_~z~0_33 |v_P1Thread1of1ForFork1_#t~ite9_14|) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_14|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_13|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_19|, ~z~0=v_~z~0_33} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~z~0] because there is no mapped edge [2019-12-07 16:21:19,492 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L765-->L765-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-1511865958 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In-1511865958 256) 0))) (or (and (= |P1Thread1of1ForFork1_#t~ite11_Out-1511865958| ~z$w_buff0_used~0_In-1511865958) (or .cse0 .cse1)) (and (not .cse0) (= |P1Thread1of1ForFork1_#t~ite11_Out-1511865958| 0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1511865958, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1511865958} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1511865958, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out-1511865958|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1511865958} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 16:21:19,493 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L784-2-->L784-4: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In-639636434 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In-639636434 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite15_Out-639636434| ~z$w_buff1~0_In-639636434) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~z~0_In-639636434 |P2Thread1of1ForFork2_#t~ite15_Out-639636434|)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-639636434, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-639636434, ~z$w_buff1~0=~z$w_buff1~0_In-639636434, ~z~0=~z~0_In-639636434} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-639636434|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-639636434, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-639636434, ~z$w_buff1~0=~z$w_buff1~0_In-639636434, ~z~0=~z~0_In-639636434} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 16:21:19,493 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L766-->L766-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In-724234301 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In-724234301 256) 0)) (.cse2 (= (mod ~z$r_buff0_thd2~0_In-724234301 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In-724234301 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$w_buff1_used~0_In-724234301 |P1Thread1of1ForFork1_#t~ite12_Out-724234301|)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork1_#t~ite12_Out-724234301|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-724234301, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-724234301, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-724234301, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-724234301} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-724234301, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-724234301, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-724234301, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-724234301|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-724234301} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 16:21:19,493 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L767-->L767-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-1716681304 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-1716681304 256)))) (or (and (= |P1Thread1of1ForFork1_#t~ite13_Out-1716681304| ~z$r_buff0_thd2~0_In-1716681304) (or .cse0 .cse1)) (and (= |P1Thread1of1ForFork1_#t~ite13_Out-1716681304| 0) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1716681304, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1716681304} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1716681304, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-1716681304|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1716681304} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 16:21:19,494 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L784-4-->L785: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~z~0_45) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, ~z~0=v_~z~0_45, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_13|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~z~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 16:21:19,494 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L785-->L785-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In2084538868 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In2084538868 256)))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite17_Out2084538868| ~z$w_buff0_used~0_In2084538868)) (and (= 0 |P2Thread1of1ForFork2_#t~ite17_Out2084538868|) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In2084538868, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In2084538868} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In2084538868, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In2084538868, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out2084538868|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 16:21:19,494 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L786-->L786-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In-1710650687 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In-1710650687 256) 0)) (.cse2 (= (mod ~z$r_buff1_thd3~0_In-1710650687 256) 0)) (.cse3 (= (mod ~z$w_buff1_used~0_In-1710650687 256) 0))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite18_Out-1710650687|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$w_buff1_used~0_In-1710650687 |P2Thread1of1ForFork2_#t~ite18_Out-1710650687|) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1710650687, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1710650687, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1710650687, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1710650687} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1710650687, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1710650687, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1710650687, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1710650687, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-1710650687|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 16:21:19,495 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L787-->L787-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In-343203905 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-343203905 256) 0))) (or (and (not .cse0) (= 0 |P2Thread1of1ForFork2_#t~ite19_Out-343203905|) (not .cse1)) (and (or .cse0 .cse1) (= ~z$r_buff0_thd3~0_In-343203905 |P2Thread1of1ForFork2_#t~ite19_Out-343203905|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-343203905, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-343203905} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-343203905, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-343203905, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-343203905|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 16:21:19,495 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [769] [769] L788-->L788-2: Formula: (let ((.cse2 (= (mod ~z$r_buff1_thd3~0_In1562810780 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In1562810780 256))) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In1562810780 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In1562810780 256)))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite20_Out1562810780|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$r_buff1_thd3~0_In1562810780 |P2Thread1of1ForFork2_#t~ite20_Out1562810780|) (or .cse2 .cse3) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1562810780, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1562810780, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1562810780, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1562810780} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1562810780, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out1562810780|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1562810780, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1562810780, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1562810780} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 16:21:19,495 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L788-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite20_32| v_~z$r_buff1_thd3~0_66) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_73 1) v_~__unbuffered_cnt~0_72)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_73} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_31|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_66, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 16:21:19,495 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L768-->L768-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-1850158423 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-1850158423 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd2~0_In-1850158423 256))) (.cse3 (= (mod ~z$w_buff1_used~0_In-1850158423 256) 0))) (or (and (= ~z$r_buff1_thd2~0_In-1850158423 |P1Thread1of1ForFork1_#t~ite14_Out-1850158423|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork1_#t~ite14_Out-1850158423| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1850158423, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1850158423, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1850158423, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1850158423} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1850158423, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1850158423, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1850158423, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-1850158423|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1850158423} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 16:21:19,496 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L768-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_38 1) v_~__unbuffered_cnt~0_37) (= |v_P1Thread1of1ForFork1_#t~ite14_28| v_~z$r_buff1_thd2~0_54) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_28|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_54, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_37, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_27|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 16:21:19,496 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L811-1-->L817: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 16:21:19,496 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L817-2-->L817-4: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In835122685 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In835122685 256) 0))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite24_Out835122685| ~z$w_buff1~0_In835122685)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite24_Out835122685| ~z~0_In835122685)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In835122685, ~z$w_buff1_used~0=~z$w_buff1_used~0_In835122685, ~z$w_buff1~0=~z$w_buff1~0_In835122685, ~z~0=~z~0_In835122685} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In835122685, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out835122685|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In835122685, ~z$w_buff1~0=~z$w_buff1~0_In835122685, ~z~0=~z~0_In835122685} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-12-07 16:21:19,496 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L817-4-->L818: Formula: (= v_~z~0_21 |v_ULTIMATE.start_main_#t~ite24_9|) InVars {ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_9|} OutVars{ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_8|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_12|, ~z~0=v_~z~0_21} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25, ~z~0] because there is no mapped edge [2019-12-07 16:21:19,496 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L818-->L818-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In1371602919 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In1371602919 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite26_Out1371602919| ~z$w_buff0_used~0_In1371602919)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite26_Out1371602919| 0) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1371602919, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1371602919} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1371602919, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1371602919, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out1371602919|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 16:21:19,497 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L819-->L819-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In180162478 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd0~0_In180162478 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In180162478 256) 0)) (.cse3 (= 0 (mod ~z$r_buff1_thd0~0_In180162478 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite27_Out180162478| ~z$w_buff1_used~0_In180162478)) (and (= 0 |ULTIMATE.start_main_#t~ite27_Out180162478|) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In180162478, ~z$w_buff0_used~0=~z$w_buff0_used~0_In180162478, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In180162478, ~z$w_buff1_used~0=~z$w_buff1_used~0_In180162478} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In180162478, ~z$w_buff0_used~0=~z$w_buff0_used~0_In180162478, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In180162478, ~z$w_buff1_used~0=~z$w_buff1_used~0_In180162478, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out180162478|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 16:21:19,497 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [780] [780] L820-->L820-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In313763121 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In313763121 256)))) (or (and (= ~z$r_buff0_thd0~0_In313763121 |ULTIMATE.start_main_#t~ite28_Out313763121|) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite28_Out313763121|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In313763121, ~z$w_buff0_used~0=~z$w_buff0_used~0_In313763121} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In313763121, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out313763121|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In313763121} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 16:21:19,498 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L821-->L821-2: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In161486046 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In161486046 256) 0)) (.cse2 (= (mod ~z$w_buff0_used~0_In161486046 256) 0)) (.cse3 (= (mod ~z$r_buff0_thd0~0_In161486046 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite29_Out161486046| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite29_Out161486046| ~z$r_buff1_thd0~0_In161486046) (or .cse2 .cse3)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In161486046, ~z$w_buff0_used~0=~z$w_buff0_used~0_In161486046, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In161486046, ~z$w_buff1_used~0=~z$w_buff1_used~0_In161486046} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In161486046, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out161486046|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In161486046, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In161486046, ~z$w_buff1_used~0=~z$w_buff1_used~0_In161486046} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 16:21:19,502 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L833-->L834: Formula: (and (= v_~z$r_buff0_thd0~0_167 v_~z$r_buff0_thd0~0_166) (not (= (mod v_~weak$$choice2~0_39 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_167, ~weak$$choice2~0=v_~weak$$choice2~0_39} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_166, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_10|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_11|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_8|, ~weak$$choice2~0=v_~weak$$choice2~0_39} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 16:21:19,502 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L836-->L4: Formula: (and (= v_~z$mem_tmp~0_13 v_~z~0_134) (= 0 v_~z$flush_delayed~0_22) (= (mod v_~main$tmp_guard1~0_32 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (not (= (mod v_~z$flush_delayed~0_23 256) 0))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_13, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_23} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_13, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_17|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ~z$flush_delayed~0=v_~z$flush_delayed~0_22, ~z~0=v_~z~0_134, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 16:21:19,503 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_13 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_13, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 16:21:19,583 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_f7561b11-7f80-476d-97f0-1a45ce2175a4/bin/uautomizer/witness.graphml [2019-12-07 16:21:19,583 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 16:21:19,584 INFO L168 Benchmark]: Toolchain (without parser) took 146158.55 ms. Allocated memory was 1.0 GB in the beginning and 7.0 GB in the end (delta: 6.0 GB). Free memory was 932.6 MB in the beginning and 6.2 GB in the end (delta: -5.3 GB). Peak memory consumption was 730.2 MB. Max. memory is 11.5 GB. [2019-12-07 16:21:19,585 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 16:21:19,585 INFO L168 Benchmark]: CACSL2BoogieTranslator took 376.04 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 97.5 MB). Free memory was 932.6 MB in the beginning and 1.1 GB in the end (delta: -132.6 MB). Peak memory consumption was 18.3 MB. Max. memory is 11.5 GB. [2019-12-07 16:21:19,585 INFO L168 Benchmark]: Boogie Procedure Inliner took 44.68 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 16:21:19,586 INFO L168 Benchmark]: Boogie Preprocessor took 28.48 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 16:21:19,586 INFO L168 Benchmark]: RCFGBuilder took 404.78 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 56.8 MB). Peak memory consumption was 56.8 MB. Max. memory is 11.5 GB. [2019-12-07 16:21:19,586 INFO L168 Benchmark]: TraceAbstraction took 145203.02 ms. Allocated memory was 1.1 GB in the beginning and 7.0 GB in the end (delta: 5.9 GB). Free memory was 997.7 MB in the beginning and 6.2 GB in the end (delta: -5.2 GB). Peak memory consumption was 660.0 MB. Max. memory is 11.5 GB. [2019-12-07 16:21:19,587 INFO L168 Benchmark]: Witness Printer took 98.44 ms. Allocated memory is still 7.0 GB. Free memory was 6.2 GB in the beginning and 6.2 GB in the end (delta: 37.8 MB). Peak memory consumption was 37.8 MB. Max. memory is 11.5 GB. [2019-12-07 16:21:19,588 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 376.04 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 97.5 MB). Free memory was 932.6 MB in the beginning and 1.1 GB in the end (delta: -132.6 MB). Peak memory consumption was 18.3 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 44.68 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 28.48 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 404.78 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 56.8 MB). Peak memory consumption was 56.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 145203.02 ms. Allocated memory was 1.1 GB in the beginning and 7.0 GB in the end (delta: 5.9 GB). Free memory was 997.7 MB in the beginning and 6.2 GB in the end (delta: -5.2 GB). Peak memory consumption was 660.0 MB. Max. memory is 11.5 GB. * Witness Printer took 98.44 ms. Allocated memory is still 7.0 GB. Free memory was 6.2 GB in the beginning and 6.2 GB in the end (delta: 37.8 MB). Peak memory consumption was 37.8 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 2.9s, 175 ProgramPointsBefore, 95 ProgramPointsAfterwards, 212 TransitionsBefore, 106 TransitionsAfterwards, 17114 CoEnabledTransitionPairs, 7 FixpointIterations, 32 TrivialSequentialCompositions, 46 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 34 ConcurrentYvCompositions, 30 ChoiceCompositions, 5490 VarBasedMoverChecksPositive, 229 VarBasedMoverChecksNegative, 63 SemBasedMoverChecksPositive, 239 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.7s, 0 MoverChecksTotal, 80053 CheckedPairsTotal, 112 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L807] FCALL, FORK 0 pthread_create(&t1976, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L734] 1 z$r_buff1_thd0 = z$r_buff0_thd0 [L735] 1 z$r_buff1_thd1 = z$r_buff0_thd1 [L736] 1 z$r_buff1_thd2 = z$r_buff0_thd2 [L737] 1 z$r_buff1_thd3 = z$r_buff0_thd3 [L738] 1 z$r_buff0_thd1 = (_Bool)1 [L741] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L744] EXPR 1 z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L809] FCALL, FORK 0 pthread_create(&t1977, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L744] 1 z = z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) [L745] 1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used [L746] 1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used [L811] FCALL, FORK 0 pthread_create(&t1978, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L758] 2 __unbuffered_p1_EAX = x [L761] 2 y = 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L764] 2 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L778] 3 __unbuffered_p2_EAX = y [L781] 3 z = 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=2] [L784] 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L765] 2 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used [L766] 2 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used [L767] 2 z$r_buff0_thd2 = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 [L785] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L786] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L787] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L817] 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L818] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L819] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L820] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L821] 0 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L824] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L825] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L826] 0 z$flush_delayed = weak$$choice2 [L827] 0 z$mem_tmp = z VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L828] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L828] 0 z = !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) [L829] EXPR 0 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L829] 0 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) [L830] EXPR 0 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L830] 0 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) [L831] EXPR 0 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L831] 0 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) [L832] EXPR 0 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L832] 0 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L834] EXPR 0 weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L834] 0 z$r_buff1_thd0 = weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L835] 0 main$tmp_guard1 = !(z == 2 && __unbuffered_p1_EAX == 1 && __unbuffered_p2_EAX == 1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 166 locations, 2 error locations. Result: UNSAFE, OverallTime: 145.0s, OverallIterations: 22, TraceHistogramMax: 1, AutomataDifference: 30.3s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 3952 SDtfs, 4211 SDslu, 8967 SDs, 0 SdLazy, 4854 SolverSat, 260 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 207 GetRequests, 28 SyntacticMatches, 13 SemanticMatches, 166 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 500 ImplicationChecksByTransitivity, 1.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=241496occurred in iteration=8, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 94.3s AutomataMinimizationTime, 21 MinimizatonAttempts, 606844 StatesRemovedByMinimization, 19 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.0s InterpolantComputationTime, 931 NumberOfCodeBlocks, 931 NumberOfCodeBlocksAsserted, 22 NumberOfCheckSat, 842 ConstructedInterpolants, 0 QuantifiedInterpolants, 214279 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 21 InterpolantComputations, 21 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...