./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe011_power.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_ceec2073-65a5-4ec4-98cb-5e6b17b2e955/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_ceec2073-65a5-4ec4-98cb-5e6b17b2e955/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_ceec2073-65a5-4ec4-98cb-5e6b17b2e955/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_ceec2073-65a5-4ec4-98cb-5e6b17b2e955/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe011_power.oepc.i -s /tmp/vcloud-vcloud-master/worker/run_dir_ceec2073-65a5-4ec4-98cb-5e6b17b2e955/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_ceec2073-65a5-4ec4-98cb-5e6b17b2e955/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 990cdd7f471d7a1b05089f8d842917591a50d2f2 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:54:18,484 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:54:18,486 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:54:18,493 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:54:18,493 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:54:18,494 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:54:18,495 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:54:18,496 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:54:18,497 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:54:18,498 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:54:18,499 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:54:18,499 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:54:18,500 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:54:18,500 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:54:18,501 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:54:18,502 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:54:18,502 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:54:18,503 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:54:18,504 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:54:18,506 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:54:18,507 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:54:18,507 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:54:18,508 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:54:18,508 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:54:18,510 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:54:18,510 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:54:18,510 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:54:18,511 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:54:18,511 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:54:18,512 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:54:18,512 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:54:18,512 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:54:18,513 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:54:18,513 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:54:18,514 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:54:18,514 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:54:18,514 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:54:18,514 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:54:18,514 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:54:18,515 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:54:18,515 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:54:18,516 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_ceec2073-65a5-4ec4-98cb-5e6b17b2e955/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 18:54:18,525 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:54:18,526 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:54:18,526 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:54:18,526 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:54:18,527 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:54:18,527 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:54:18,527 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:54:18,527 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:54:18,527 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:54:18,527 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:54:18,527 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 18:54:18,527 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 18:54:18,528 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 18:54:18,528 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:54:18,528 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:54:18,528 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:54:18,528 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 18:54:18,528 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:54:18,528 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:54:18,529 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 18:54:18,529 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 18:54:18,529 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:54:18,529 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:54:18,529 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 18:54:18,529 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 18:54:18,529 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:54:18,529 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 18:54:18,530 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 18:54:18,530 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:54:18,530 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_ceec2073-65a5-4ec4-98cb-5e6b17b2e955/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 990cdd7f471d7a1b05089f8d842917591a50d2f2 [2019-12-07 18:54:18,629 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:54:18,639 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:54:18,641 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:54:18,643 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:54:18,643 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:54:18,643 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_ceec2073-65a5-4ec4-98cb-5e6b17b2e955/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe011_power.oepc.i [2019-12-07 18:54:18,690 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_ceec2073-65a5-4ec4-98cb-5e6b17b2e955/bin/uautomizer/data/1bc3f0bd0/9d16c0c9c82e49c996749b80088b898f/FLAGecee70213 [2019-12-07 18:54:19,176 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:54:19,176 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_ceec2073-65a5-4ec4-98cb-5e6b17b2e955/sv-benchmarks/c/pthread-wmm/safe011_power.oepc.i [2019-12-07 18:54:19,188 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_ceec2073-65a5-4ec4-98cb-5e6b17b2e955/bin/uautomizer/data/1bc3f0bd0/9d16c0c9c82e49c996749b80088b898f/FLAGecee70213 [2019-12-07 18:54:19,197 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_ceec2073-65a5-4ec4-98cb-5e6b17b2e955/bin/uautomizer/data/1bc3f0bd0/9d16c0c9c82e49c996749b80088b898f [2019-12-07 18:54:19,199 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:54:19,199 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:54:19,200 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:54:19,200 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:54:19,202 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:54:19,203 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:54:19" (1/1) ... [2019-12-07 18:54:19,205 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3f8fae9c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:54:19, skipping insertion in model container [2019-12-07 18:54:19,205 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:54:19" (1/1) ... [2019-12-07 18:54:19,210 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:54:19,248 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:54:19,500 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:54:19,507 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:54:19,551 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:54:19,597 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:54:19,598 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:54:19 WrapperNode [2019-12-07 18:54:19,598 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:54:19,598 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:54:19,598 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:54:19,598 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:54:19,604 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:54:19" (1/1) ... [2019-12-07 18:54:19,617 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:54:19" (1/1) ... [2019-12-07 18:54:19,639 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:54:19,639 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:54:19,639 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:54:19,639 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:54:19,646 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:54:19" (1/1) ... [2019-12-07 18:54:19,646 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:54:19" (1/1) ... [2019-12-07 18:54:19,650 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:54:19" (1/1) ... [2019-12-07 18:54:19,650 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:54:19" (1/1) ... [2019-12-07 18:54:19,657 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:54:19" (1/1) ... [2019-12-07 18:54:19,660 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:54:19" (1/1) ... [2019-12-07 18:54:19,662 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:54:19" (1/1) ... [2019-12-07 18:54:19,666 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:54:19,666 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:54:19,666 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:54:19,666 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:54:19,667 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:54:19" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_ceec2073-65a5-4ec4-98cb-5e6b17b2e955/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:54:19,709 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 18:54:19,709 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 18:54:19,709 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 18:54:19,709 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 18:54:19,709 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 18:54:19,709 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 18:54:19,709 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 18:54:19,709 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 18:54:19,710 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 18:54:19,710 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 18:54:19,710 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 18:54:19,710 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:54:19,710 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:54:19,711 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 18:54:20,074 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:54:20,075 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 18:54:20,075 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:54:20 BoogieIcfgContainer [2019-12-07 18:54:20,076 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:54:20,076 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 18:54:20,076 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 18:54:20,078 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 18:54:20,078 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 06:54:19" (1/3) ... [2019-12-07 18:54:20,079 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3823441 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:54:20, skipping insertion in model container [2019-12-07 18:54:20,079 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:54:19" (2/3) ... [2019-12-07 18:54:20,079 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3823441 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:54:20, skipping insertion in model container [2019-12-07 18:54:20,079 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:54:20" (3/3) ... [2019-12-07 18:54:20,080 INFO L109 eAbstractionObserver]: Analyzing ICFG safe011_power.oepc.i [2019-12-07 18:54:20,087 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 18:54:20,087 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 18:54:20,092 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 18:54:20,093 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 18:54:20,116 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,116 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,116 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,116 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,116 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,116 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,117 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,117 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,117 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,117 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,117 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,117 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,118 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,118 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,118 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,118 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,118 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,118 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,118 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,119 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,119 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,119 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,119 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,119 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,119 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,119 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,120 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,120 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,120 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,120 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,120 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,120 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,120 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,120 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,121 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,121 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,121 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,121 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,121 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,122 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,122 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,122 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,122 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,122 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,122 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,122 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,122 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,123 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,123 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,123 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,123 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,123 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,123 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,123 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,124 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,124 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,124 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,124 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,124 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,124 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,124 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,124 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,125 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,125 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,125 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,125 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,125 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,125 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,126 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,126 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,126 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,126 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,126 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,126 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,126 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,127 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,127 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,127 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,127 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,127 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,127 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,127 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,127 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,127 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,128 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,128 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,128 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,128 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,128 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,128 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,128 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,128 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,129 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,129 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:54:20,139 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 18:54:20,152 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 18:54:20,152 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 18:54:20,152 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 18:54:20,152 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:54:20,152 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:54:20,152 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 18:54:20,152 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:54:20,152 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 18:54:20,164 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 174 places, 211 transitions [2019-12-07 18:54:20,165 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 174 places, 211 transitions [2019-12-07 18:54:20,218 INFO L134 PetriNetUnfolder]: 47/208 cut-off events. [2019-12-07 18:54:20,218 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:54:20,229 INFO L76 FinitePrefix]: Finished finitePrefix Result has 218 conditions, 208 events. 47/208 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 573 event pairs. 9/168 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 18:54:20,243 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 174 places, 211 transitions [2019-12-07 18:54:20,274 INFO L134 PetriNetUnfolder]: 47/208 cut-off events. [2019-12-07 18:54:20,274 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:54:20,280 INFO L76 FinitePrefix]: Finished finitePrefix Result has 218 conditions, 208 events. 47/208 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 573 event pairs. 9/168 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 18:54:20,295 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 17114 [2019-12-07 18:54:20,296 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 18:54:23,153 WARN L192 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 85 [2019-12-07 18:54:23,249 INFO L206 etLargeBlockEncoding]: Checked pairs total: 86146 [2019-12-07 18:54:23,250 INFO L214 etLargeBlockEncoding]: Total number of compositions: 112 [2019-12-07 18:54:23,252 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 93 places, 104 transitions [2019-12-07 18:54:35,603 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 104862 states. [2019-12-07 18:54:35,604 INFO L276 IsEmpty]: Start isEmpty. Operand 104862 states. [2019-12-07 18:54:35,608 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-12-07 18:54:35,608 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:54:35,608 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-12-07 18:54:35,608 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:54:35,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:54:35,612 INFO L82 PathProgramCache]: Analyzing trace with hash 844471, now seen corresponding path program 1 times [2019-12-07 18:54:35,617 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:54:35,618 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [315830311] [2019-12-07 18:54:35,618 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:54:35,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:54:35,748 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:54:35,748 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [315830311] [2019-12-07 18:54:35,749 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:54:35,749 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:54:35,750 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [463009351] [2019-12-07 18:54:35,752 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:54:35,752 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:54:35,761 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:54:35,762 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:54:35,763 INFO L87 Difference]: Start difference. First operand 104862 states. Second operand 3 states. [2019-12-07 18:54:36,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:54:36,501 INFO L93 Difference]: Finished difference Result 104560 states and 448162 transitions. [2019-12-07 18:54:36,502 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:54:36,503 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-12-07 18:54:36,503 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:54:37,259 INFO L225 Difference]: With dead ends: 104560 [2019-12-07 18:54:37,259 INFO L226 Difference]: Without dead ends: 102376 [2019-12-07 18:54:37,260 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:54:40,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102376 states. [2019-12-07 18:54:42,177 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102376 to 102376. [2019-12-07 18:54:42,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102376 states. [2019-12-07 18:54:42,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102376 states to 102376 states and 439244 transitions. [2019-12-07 18:54:42,544 INFO L78 Accepts]: Start accepts. Automaton has 102376 states and 439244 transitions. Word has length 3 [2019-12-07 18:54:42,545 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:54:42,545 INFO L462 AbstractCegarLoop]: Abstraction has 102376 states and 439244 transitions. [2019-12-07 18:54:42,545 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:54:42,545 INFO L276 IsEmpty]: Start isEmpty. Operand 102376 states and 439244 transitions. [2019-12-07 18:54:42,548 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 18:54:42,549 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:54:42,549 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:54:42,549 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:54:42,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:54:42,549 INFO L82 PathProgramCache]: Analyzing trace with hash 205437058, now seen corresponding path program 1 times [2019-12-07 18:54:42,549 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:54:42,550 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [469106365] [2019-12-07 18:54:42,550 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:54:42,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:54:42,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:54:42,626 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [469106365] [2019-12-07 18:54:42,626 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:54:42,627 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:54:42,627 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [264730647] [2019-12-07 18:54:42,628 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:54:42,628 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:54:42,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:54:42,628 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:54:42,628 INFO L87 Difference]: Start difference. First operand 102376 states and 439244 transitions. Second operand 4 states. [2019-12-07 18:54:45,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:54:45,525 INFO L93 Difference]: Finished difference Result 164490 states and 678436 transitions. [2019-12-07 18:54:45,526 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:54:45,526 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 18:54:45,526 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:54:46,015 INFO L225 Difference]: With dead ends: 164490 [2019-12-07 18:54:46,015 INFO L226 Difference]: Without dead ends: 164441 [2019-12-07 18:54:46,016 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:54:50,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 164441 states. [2019-12-07 18:54:52,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 164441 to 148513. [2019-12-07 18:54:52,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148513 states. [2019-12-07 18:54:52,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148513 states to 148513 states and 619831 transitions. [2019-12-07 18:54:52,718 INFO L78 Accepts]: Start accepts. Automaton has 148513 states and 619831 transitions. Word has length 11 [2019-12-07 18:54:52,719 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:54:52,719 INFO L462 AbstractCegarLoop]: Abstraction has 148513 states and 619831 transitions. [2019-12-07 18:54:52,719 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:54:52,719 INFO L276 IsEmpty]: Start isEmpty. Operand 148513 states and 619831 transitions. [2019-12-07 18:54:52,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:54:52,724 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:54:52,724 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:54:52,725 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:54:52,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:54:52,725 INFO L82 PathProgramCache]: Analyzing trace with hash 1045519438, now seen corresponding path program 1 times [2019-12-07 18:54:52,725 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:54:52,725 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [227468766] [2019-12-07 18:54:52,725 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:54:52,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:54:52,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:54:52,781 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [227468766] [2019-12-07 18:54:52,781 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:54:52,781 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:54:52,781 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [825583016] [2019-12-07 18:54:52,781 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:54:52,782 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:54:52,782 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:54:52,782 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:54:52,782 INFO L87 Difference]: Start difference. First operand 148513 states and 619831 transitions. Second operand 4 states. [2019-12-07 18:54:54,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:54:54,382 INFO L93 Difference]: Finished difference Result 211896 states and 864765 transitions. [2019-12-07 18:54:54,383 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:54:54,383 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 18:54:54,383 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:54:54,924 INFO L225 Difference]: With dead ends: 211896 [2019-12-07 18:54:54,924 INFO L226 Difference]: Without dead ends: 211833 [2019-12-07 18:54:54,924 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:55:01,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211833 states. [2019-12-07 18:55:04,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211833 to 178183. [2019-12-07 18:55:04,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178183 states. [2019-12-07 18:55:04,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178183 states to 178183 states and 738846 transitions. [2019-12-07 18:55:04,843 INFO L78 Accepts]: Start accepts. Automaton has 178183 states and 738846 transitions. Word has length 13 [2019-12-07 18:55:04,844 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:04,844 INFO L462 AbstractCegarLoop]: Abstraction has 178183 states and 738846 transitions. [2019-12-07 18:55:04,844 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:55:04,844 INFO L276 IsEmpty]: Start isEmpty. Operand 178183 states and 738846 transitions. [2019-12-07 18:55:04,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:55:04,846 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:04,846 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:04,847 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:04,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:04,847 INFO L82 PathProgramCache]: Analyzing trace with hash 31849685, now seen corresponding path program 1 times [2019-12-07 18:55:04,847 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:04,847 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [993747906] [2019-12-07 18:55:04,847 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:04,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:04,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:04,909 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [993747906] [2019-12-07 18:55:04,909 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:04,909 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:55:04,909 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2116727483] [2019-12-07 18:55:04,909 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:55:04,910 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:04,910 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:55:04,910 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:55:04,910 INFO L87 Difference]: Start difference. First operand 178183 states and 738846 transitions. Second operand 4 states. [2019-12-07 18:55:06,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:06,133 INFO L93 Difference]: Finished difference Result 223676 states and 918481 transitions. [2019-12-07 18:55:06,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:55:06,134 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 18:55:06,134 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:06,727 INFO L225 Difference]: With dead ends: 223676 [2019-12-07 18:55:06,727 INFO L226 Difference]: Without dead ends: 223676 [2019-12-07 18:55:06,728 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:55:12,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223676 states. [2019-12-07 18:55:17,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223676 to 188328. [2019-12-07 18:55:17,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 188328 states. [2019-12-07 18:55:17,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188328 states to 188328 states and 781098 transitions. [2019-12-07 18:55:17,880 INFO L78 Accepts]: Start accepts. Automaton has 188328 states and 781098 transitions. Word has length 13 [2019-12-07 18:55:17,880 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:17,880 INFO L462 AbstractCegarLoop]: Abstraction has 188328 states and 781098 transitions. [2019-12-07 18:55:17,880 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:55:17,880 INFO L276 IsEmpty]: Start isEmpty. Operand 188328 states and 781098 transitions. [2019-12-07 18:55:17,901 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 18:55:17,901 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:17,901 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:17,901 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:17,901 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:17,901 INFO L82 PathProgramCache]: Analyzing trace with hash 227208446, now seen corresponding path program 1 times [2019-12-07 18:55:17,901 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:17,901 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2061563303] [2019-12-07 18:55:17,902 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:17,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:17,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:17,944 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2061563303] [2019-12-07 18:55:17,944 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:17,944 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:55:17,945 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1014967189] [2019-12-07 18:55:17,945 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:55:17,945 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:17,945 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:55:17,945 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:55:17,945 INFO L87 Difference]: Start difference. First operand 188328 states and 781098 transitions. Second operand 3 states. [2019-12-07 18:55:18,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:18,060 INFO L93 Difference]: Finished difference Result 36088 states and 117391 transitions. [2019-12-07 18:55:18,061 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:55:18,061 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2019-12-07 18:55:18,061 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:18,113 INFO L225 Difference]: With dead ends: 36088 [2019-12-07 18:55:18,113 INFO L226 Difference]: Without dead ends: 36088 [2019-12-07 18:55:18,113 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:55:18,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36088 states. [2019-12-07 18:55:19,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36088 to 36088. [2019-12-07 18:55:19,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36088 states. [2019-12-07 18:55:19,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36088 states to 36088 states and 117391 transitions. [2019-12-07 18:55:19,066 INFO L78 Accepts]: Start accepts. Automaton has 36088 states and 117391 transitions. Word has length 19 [2019-12-07 18:55:19,066 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:19,066 INFO L462 AbstractCegarLoop]: Abstraction has 36088 states and 117391 transitions. [2019-12-07 18:55:19,066 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:55:19,067 INFO L276 IsEmpty]: Start isEmpty. Operand 36088 states and 117391 transitions. [2019-12-07 18:55:19,070 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 18:55:19,070 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:19,070 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:19,071 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:19,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:19,071 INFO L82 PathProgramCache]: Analyzing trace with hash -1539749953, now seen corresponding path program 1 times [2019-12-07 18:55:19,071 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:19,071 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1261810697] [2019-12-07 18:55:19,071 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:19,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:19,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:19,184 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1261810697] [2019-12-07 18:55:19,185 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:19,185 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:55:19,185 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [931381288] [2019-12-07 18:55:19,185 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:55:19,185 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:19,186 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:55:19,186 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:55:19,186 INFO L87 Difference]: Start difference. First operand 36088 states and 117391 transitions. Second operand 7 states. [2019-12-07 18:55:19,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:19,824 INFO L93 Difference]: Finished difference Result 50098 states and 158333 transitions. [2019-12-07 18:55:19,825 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 18:55:19,825 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 19 [2019-12-07 18:55:19,825 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:19,901 INFO L225 Difference]: With dead ends: 50098 [2019-12-07 18:55:19,901 INFO L226 Difference]: Without dead ends: 50091 [2019-12-07 18:55:19,901 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:55:20,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50091 states. [2019-12-07 18:55:20,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50091 to 36331. [2019-12-07 18:55:20,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36331 states. [2019-12-07 18:55:20,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36331 states to 36331 states and 118099 transitions. [2019-12-07 18:55:20,630 INFO L78 Accepts]: Start accepts. Automaton has 36331 states and 118099 transitions. Word has length 19 [2019-12-07 18:55:20,631 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:20,631 INFO L462 AbstractCegarLoop]: Abstraction has 36331 states and 118099 transitions. [2019-12-07 18:55:20,631 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:55:20,631 INFO L276 IsEmpty]: Start isEmpty. Operand 36331 states and 118099 transitions. [2019-12-07 18:55:20,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 18:55:20,634 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:20,634 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:20,634 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:20,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:20,634 INFO L82 PathProgramCache]: Analyzing trace with hash 1843003519, now seen corresponding path program 2 times [2019-12-07 18:55:20,634 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:20,634 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1159819860] [2019-12-07 18:55:20,634 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:20,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:20,691 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:20,691 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1159819860] [2019-12-07 18:55:20,691 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:20,691 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:55:20,692 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1406867126] [2019-12-07 18:55:20,692 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:55:20,692 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:20,692 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:55:20,692 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:55:20,692 INFO L87 Difference]: Start difference. First operand 36331 states and 118099 transitions. Second operand 5 states. [2019-12-07 18:55:21,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:21,158 INFO L93 Difference]: Finished difference Result 46087 states and 147024 transitions. [2019-12-07 18:55:21,159 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:55:21,159 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 18:55:21,159 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:21,221 INFO L225 Difference]: With dead ends: 46087 [2019-12-07 18:55:21,221 INFO L226 Difference]: Without dead ends: 46080 [2019-12-07 18:55:21,222 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:55:21,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46080 states. [2019-12-07 18:55:21,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46080 to 36431. [2019-12-07 18:55:21,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36431 states. [2019-12-07 18:55:21,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36431 states to 36431 states and 118357 transitions. [2019-12-07 18:55:21,910 INFO L78 Accepts]: Start accepts. Automaton has 36431 states and 118357 transitions. Word has length 19 [2019-12-07 18:55:21,911 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:21,911 INFO L462 AbstractCegarLoop]: Abstraction has 36431 states and 118357 transitions. [2019-12-07 18:55:21,911 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:55:21,911 INFO L276 IsEmpty]: Start isEmpty. Operand 36431 states and 118357 transitions. [2019-12-07 18:55:21,917 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 18:55:21,917 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:21,917 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:21,917 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:21,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:21,918 INFO L82 PathProgramCache]: Analyzing trace with hash 1129453691, now seen corresponding path program 1 times [2019-12-07 18:55:21,918 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:21,918 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2027769435] [2019-12-07 18:55:21,918 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:21,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:21,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:21,970 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2027769435] [2019-12-07 18:55:21,970 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:21,970 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:55:21,970 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1170084766] [2019-12-07 18:55:21,970 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:55:21,971 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:21,971 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:55:21,971 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:55:21,971 INFO L87 Difference]: Start difference. First operand 36431 states and 118357 transitions. Second operand 5 states. [2019-12-07 18:55:22,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:22,346 INFO L93 Difference]: Finished difference Result 49997 states and 159227 transitions. [2019-12-07 18:55:22,346 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:55:22,347 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 25 [2019-12-07 18:55:22,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:22,422 INFO L225 Difference]: With dead ends: 49997 [2019-12-07 18:55:22,422 INFO L226 Difference]: Without dead ends: 49997 [2019-12-07 18:55:22,422 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 0 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:55:22,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49997 states. [2019-12-07 18:55:23,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49997 to 40086. [2019-12-07 18:55:23,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40086 states. [2019-12-07 18:55:23,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40086 states to 40086 states and 129428 transitions. [2019-12-07 18:55:23,445 INFO L78 Accepts]: Start accepts. Automaton has 40086 states and 129428 transitions. Word has length 25 [2019-12-07 18:55:23,446 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:23,446 INFO L462 AbstractCegarLoop]: Abstraction has 40086 states and 129428 transitions. [2019-12-07 18:55:23,446 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:55:23,446 INFO L276 IsEmpty]: Start isEmpty. Operand 40086 states and 129428 transitions. [2019-12-07 18:55:23,452 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 18:55:23,452 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:23,453 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:23,453 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:23,453 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:23,453 INFO L82 PathProgramCache]: Analyzing trace with hash -2008358183, now seen corresponding path program 1 times [2019-12-07 18:55:23,453 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:23,453 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1140659384] [2019-12-07 18:55:23,453 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:23,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:23,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:23,527 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1140659384] [2019-12-07 18:55:23,528 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:23,528 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:55:23,528 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [567075715] [2019-12-07 18:55:23,528 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:55:23,529 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:23,529 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:55:23,529 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:55:23,529 INFO L87 Difference]: Start difference. First operand 40086 states and 129428 transitions. Second operand 5 states. [2019-12-07 18:55:23,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:23,919 INFO L93 Difference]: Finished difference Result 54194 states and 172124 transitions. [2019-12-07 18:55:23,920 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:55:23,920 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 25 [2019-12-07 18:55:23,920 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:24,003 INFO L225 Difference]: With dead ends: 54194 [2019-12-07 18:55:24,003 INFO L226 Difference]: Without dead ends: 54194 [2019-12-07 18:55:24,003 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 4 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:55:24,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54194 states. [2019-12-07 18:55:24,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54194 to 42378. [2019-12-07 18:55:24,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42378 states. [2019-12-07 18:55:24,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42378 states to 42378 states and 136610 transitions. [2019-12-07 18:55:24,795 INFO L78 Accepts]: Start accepts. Automaton has 42378 states and 136610 transitions. Word has length 25 [2019-12-07 18:55:24,795 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:24,795 INFO L462 AbstractCegarLoop]: Abstraction has 42378 states and 136610 transitions. [2019-12-07 18:55:24,795 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:55:24,795 INFO L276 IsEmpty]: Start isEmpty. Operand 42378 states and 136610 transitions. [2019-12-07 18:55:24,809 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 18:55:24,810 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:24,810 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:24,810 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:24,810 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:24,810 INFO L82 PathProgramCache]: Analyzing trace with hash 1003495210, now seen corresponding path program 1 times [2019-12-07 18:55:24,810 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:24,810 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [478416092] [2019-12-07 18:55:24,810 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:24,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:24,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:24,841 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [478416092] [2019-12-07 18:55:24,841 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:24,842 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:55:24,842 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [852439073] [2019-12-07 18:55:24,842 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:55:24,842 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:24,842 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:55:24,842 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:55:24,843 INFO L87 Difference]: Start difference. First operand 42378 states and 136610 transitions. Second operand 4 states. [2019-12-07 18:55:24,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:24,873 INFO L93 Difference]: Finished difference Result 8615 states and 23213 transitions. [2019-12-07 18:55:24,874 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:55:24,874 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 31 [2019-12-07 18:55:24,874 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:24,882 INFO L225 Difference]: With dead ends: 8615 [2019-12-07 18:55:24,882 INFO L226 Difference]: Without dead ends: 8615 [2019-12-07 18:55:24,882 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:55:24,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8615 states. [2019-12-07 18:55:24,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8615 to 8447. [2019-12-07 18:55:24,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8447 states. [2019-12-07 18:55:24,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8447 states to 8447 states and 22733 transitions. [2019-12-07 18:55:24,986 INFO L78 Accepts]: Start accepts. Automaton has 8447 states and 22733 transitions. Word has length 31 [2019-12-07 18:55:24,986 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:24,986 INFO L462 AbstractCegarLoop]: Abstraction has 8447 states and 22733 transitions. [2019-12-07 18:55:24,986 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:55:24,986 INFO L276 IsEmpty]: Start isEmpty. Operand 8447 states and 22733 transitions. [2019-12-07 18:55:24,995 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 18:55:24,995 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:24,995 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:24,995 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:24,995 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:24,995 INFO L82 PathProgramCache]: Analyzing trace with hash -1811341367, now seen corresponding path program 1 times [2019-12-07 18:55:24,995 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:24,995 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [214988329] [2019-12-07 18:55:24,996 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:25,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:25,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:25,060 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [214988329] [2019-12-07 18:55:25,061 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:25,061 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:55:25,061 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1897226665] [2019-12-07 18:55:25,061 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:55:25,061 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:25,061 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:55:25,061 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:55:25,061 INFO L87 Difference]: Start difference. First operand 8447 states and 22733 transitions. Second operand 6 states. [2019-12-07 18:55:25,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:25,459 INFO L93 Difference]: Finished difference Result 9397 states and 24854 transitions. [2019-12-07 18:55:25,460 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 18:55:25,460 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 37 [2019-12-07 18:55:25,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:25,467 INFO L225 Difference]: With dead ends: 9397 [2019-12-07 18:55:25,467 INFO L226 Difference]: Without dead ends: 9397 [2019-12-07 18:55:25,468 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 0 SyntacticMatches, 4 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=47, Invalid=109, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:55:25,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9397 states. [2019-12-07 18:55:25,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9397 to 7435. [2019-12-07 18:55:25,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7435 states. [2019-12-07 18:55:25,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7435 states to 7435 states and 20021 transitions. [2019-12-07 18:55:25,564 INFO L78 Accepts]: Start accepts. Automaton has 7435 states and 20021 transitions. Word has length 37 [2019-12-07 18:55:25,564 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:25,564 INFO L462 AbstractCegarLoop]: Abstraction has 7435 states and 20021 transitions. [2019-12-07 18:55:25,564 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:55:25,564 INFO L276 IsEmpty]: Start isEmpty. Operand 7435 states and 20021 transitions. [2019-12-07 18:55:25,573 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 18:55:25,573 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:25,573 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:25,573 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:25,573 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:25,573 INFO L82 PathProgramCache]: Analyzing trace with hash -1693083721, now seen corresponding path program 1 times [2019-12-07 18:55:25,573 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:25,573 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1375746927] [2019-12-07 18:55:25,574 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:25,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:25,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:25,603 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1375746927] [2019-12-07 18:55:25,603 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:25,603 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:55:25,603 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1836869483] [2019-12-07 18:55:25,604 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:55:25,604 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:25,604 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:55:25,604 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:55:25,604 INFO L87 Difference]: Start difference. First operand 7435 states and 20021 transitions. Second operand 3 states. [2019-12-07 18:55:25,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:25,653 INFO L93 Difference]: Finished difference Result 7898 states and 21079 transitions. [2019-12-07 18:55:25,653 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:55:25,654 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 51 [2019-12-07 18:55:25,654 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:25,660 INFO L225 Difference]: With dead ends: 7898 [2019-12-07 18:55:25,660 INFO L226 Difference]: Without dead ends: 7898 [2019-12-07 18:55:25,660 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:55:25,685 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7898 states. [2019-12-07 18:55:25,738 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7898 to 7740. [2019-12-07 18:55:25,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7740 states. [2019-12-07 18:55:25,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7740 states to 7740 states and 20756 transitions. [2019-12-07 18:55:25,748 INFO L78 Accepts]: Start accepts. Automaton has 7740 states and 20756 transitions. Word has length 51 [2019-12-07 18:55:25,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:25,748 INFO L462 AbstractCegarLoop]: Abstraction has 7740 states and 20756 transitions. [2019-12-07 18:55:25,748 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:55:25,748 INFO L276 IsEmpty]: Start isEmpty. Operand 7740 states and 20756 transitions. [2019-12-07 18:55:25,756 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 18:55:25,756 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:25,756 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:25,756 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:25,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:25,757 INFO L82 PathProgramCache]: Analyzing trace with hash -1565012212, now seen corresponding path program 1 times [2019-12-07 18:55:25,757 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:25,757 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1378057626] [2019-12-07 18:55:25,757 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:25,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:25,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:25,808 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1378057626] [2019-12-07 18:55:25,808 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:25,808 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:55:25,808 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [982642198] [2019-12-07 18:55:25,808 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:55:25,808 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:25,809 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:55:25,809 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:55:25,809 INFO L87 Difference]: Start difference. First operand 7740 states and 20756 transitions. Second operand 5 states. [2019-12-07 18:55:25,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:25,839 INFO L93 Difference]: Finished difference Result 5049 states and 14453 transitions. [2019-12-07 18:55:25,839 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:55:25,840 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-12-07 18:55:25,840 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:25,845 INFO L225 Difference]: With dead ends: 5049 [2019-12-07 18:55:25,846 INFO L226 Difference]: Without dead ends: 5049 [2019-12-07 18:55:25,846 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:55:25,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5049 states. [2019-12-07 18:55:25,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5049 to 4685. [2019-12-07 18:55:25,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4685 states. [2019-12-07 18:55:25,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4685 states to 4685 states and 13469 transitions. [2019-12-07 18:55:25,908 INFO L78 Accepts]: Start accepts. Automaton has 4685 states and 13469 transitions. Word has length 51 [2019-12-07 18:55:25,908 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:25,908 INFO L462 AbstractCegarLoop]: Abstraction has 4685 states and 13469 transitions. [2019-12-07 18:55:25,908 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:55:25,908 INFO L276 IsEmpty]: Start isEmpty. Operand 4685 states and 13469 transitions. [2019-12-07 18:55:25,914 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:55:25,914 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:25,914 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:25,914 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:25,914 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:25,914 INFO L82 PathProgramCache]: Analyzing trace with hash 1173172274, now seen corresponding path program 1 times [2019-12-07 18:55:25,915 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:25,915 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [725611130] [2019-12-07 18:55:25,915 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:25,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:25,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:25,951 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [725611130] [2019-12-07 18:55:25,951 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:25,952 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:55:25,952 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [787255271] [2019-12-07 18:55:25,952 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:55:25,952 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:25,952 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:55:25,952 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:55:25,953 INFO L87 Difference]: Start difference. First operand 4685 states and 13469 transitions. Second operand 3 states. [2019-12-07 18:55:25,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:25,994 INFO L93 Difference]: Finished difference Result 4689 states and 13463 transitions. [2019-12-07 18:55:25,994 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:55:25,994 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 18:55:25,994 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:26,000 INFO L225 Difference]: With dead ends: 4689 [2019-12-07 18:55:26,000 INFO L226 Difference]: Without dead ends: 4689 [2019-12-07 18:55:26,000 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:55:26,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4689 states. [2019-12-07 18:55:26,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4689 to 4681. [2019-12-07 18:55:26,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4681 states. [2019-12-07 18:55:26,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4681 states to 4681 states and 13455 transitions. [2019-12-07 18:55:26,062 INFO L78 Accepts]: Start accepts. Automaton has 4681 states and 13455 transitions. Word has length 65 [2019-12-07 18:55:26,063 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:26,063 INFO L462 AbstractCegarLoop]: Abstraction has 4681 states and 13455 transitions. [2019-12-07 18:55:26,063 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:55:26,063 INFO L276 IsEmpty]: Start isEmpty. Operand 4681 states and 13455 transitions. [2019-12-07 18:55:26,068 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:55:26,068 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:26,068 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:26,068 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:26,068 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:26,068 INFO L82 PathProgramCache]: Analyzing trace with hash 1163492121, now seen corresponding path program 1 times [2019-12-07 18:55:26,068 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:26,069 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [561099263] [2019-12-07 18:55:26,069 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:26,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:26,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:26,133 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [561099263] [2019-12-07 18:55:26,133 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:26,133 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:55:26,133 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [366019529] [2019-12-07 18:55:26,133 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:55:26,134 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:26,134 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:55:26,134 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:55:26,134 INFO L87 Difference]: Start difference. First operand 4681 states and 13455 transitions. Second operand 5 states. [2019-12-07 18:55:26,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:26,322 INFO L93 Difference]: Finished difference Result 7105 states and 20244 transitions. [2019-12-07 18:55:26,322 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:55:26,322 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 65 [2019-12-07 18:55:26,322 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:26,328 INFO L225 Difference]: With dead ends: 7105 [2019-12-07 18:55:26,329 INFO L226 Difference]: Without dead ends: 7105 [2019-12-07 18:55:26,329 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:55:26,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7105 states. [2019-12-07 18:55:26,411 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7105 to 6291. [2019-12-07 18:55:26,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6291 states. [2019-12-07 18:55:26,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6291 states to 6291 states and 18000 transitions. [2019-12-07 18:55:26,420 INFO L78 Accepts]: Start accepts. Automaton has 6291 states and 18000 transitions. Word has length 65 [2019-12-07 18:55:26,420 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:26,420 INFO L462 AbstractCegarLoop]: Abstraction has 6291 states and 18000 transitions. [2019-12-07 18:55:26,420 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:55:26,420 INFO L276 IsEmpty]: Start isEmpty. Operand 6291 states and 18000 transitions. [2019-12-07 18:55:26,427 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:55:26,427 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:26,428 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:26,428 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:26,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:26,428 INFO L82 PathProgramCache]: Analyzing trace with hash -2061317327, now seen corresponding path program 2 times [2019-12-07 18:55:26,428 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:26,428 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [233197804] [2019-12-07 18:55:26,428 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:26,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:26,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:26,491 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [233197804] [2019-12-07 18:55:26,492 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:26,492 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:55:26,492 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1853545379] [2019-12-07 18:55:26,492 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:55:26,492 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:26,492 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:55:26,492 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:55:26,492 INFO L87 Difference]: Start difference. First operand 6291 states and 18000 transitions. Second operand 5 states. [2019-12-07 18:55:26,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:26,688 INFO L93 Difference]: Finished difference Result 9383 states and 26609 transitions. [2019-12-07 18:55:26,688 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:55:26,688 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 65 [2019-12-07 18:55:26,688 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:26,696 INFO L225 Difference]: With dead ends: 9383 [2019-12-07 18:55:26,696 INFO L226 Difference]: Without dead ends: 9383 [2019-12-07 18:55:26,696 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:55:26,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9383 states. [2019-12-07 18:55:26,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9383 to 7346. [2019-12-07 18:55:26,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7346 states. [2019-12-07 18:55:26,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7346 states to 7346 states and 21123 transitions. [2019-12-07 18:55:26,796 INFO L78 Accepts]: Start accepts. Automaton has 7346 states and 21123 transitions. Word has length 65 [2019-12-07 18:55:26,796 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:26,796 INFO L462 AbstractCegarLoop]: Abstraction has 7346 states and 21123 transitions. [2019-12-07 18:55:26,796 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:55:26,796 INFO L276 IsEmpty]: Start isEmpty. Operand 7346 states and 21123 transitions. [2019-12-07 18:55:26,802 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:55:26,802 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:26,802 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:26,802 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:26,803 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:26,803 INFO L82 PathProgramCache]: Analyzing trace with hash -1650424373, now seen corresponding path program 3 times [2019-12-07 18:55:26,803 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:26,803 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [441230359] [2019-12-07 18:55:26,803 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:26,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:26,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:26,880 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [441230359] [2019-12-07 18:55:26,881 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:26,881 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:55:26,881 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1830571095] [2019-12-07 18:55:26,881 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:55:26,881 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:26,882 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:55:26,882 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:55:26,882 INFO L87 Difference]: Start difference. First operand 7346 states and 21123 transitions. Second operand 6 states. [2019-12-07 18:55:27,170 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:27,170 INFO L93 Difference]: Finished difference Result 11509 states and 32952 transitions. [2019-12-07 18:55:27,171 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:55:27,171 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 65 [2019-12-07 18:55:27,171 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:27,180 INFO L225 Difference]: With dead ends: 11509 [2019-12-07 18:55:27,181 INFO L226 Difference]: Without dead ends: 11509 [2019-12-07 18:55:27,181 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:55:27,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11509 states. [2019-12-07 18:55:27,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11509 to 8187. [2019-12-07 18:55:27,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8187 states. [2019-12-07 18:55:27,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8187 states to 8187 states and 23603 transitions. [2019-12-07 18:55:27,307 INFO L78 Accepts]: Start accepts. Automaton has 8187 states and 23603 transitions. Word has length 65 [2019-12-07 18:55:27,307 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:27,307 INFO L462 AbstractCegarLoop]: Abstraction has 8187 states and 23603 transitions. [2019-12-07 18:55:27,307 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:55:27,307 INFO L276 IsEmpty]: Start isEmpty. Operand 8187 states and 23603 transitions. [2019-12-07 18:55:27,314 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:55:27,314 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:27,314 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:27,314 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:27,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:27,315 INFO L82 PathProgramCache]: Analyzing trace with hash 2063456247, now seen corresponding path program 4 times [2019-12-07 18:55:27,315 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:27,315 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1092637053] [2019-12-07 18:55:27,315 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:27,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:27,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:27,385 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1092637053] [2019-12-07 18:55:27,385 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:27,385 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 18:55:27,386 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1816440010] [2019-12-07 18:55:27,386 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:55:27,386 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:27,386 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:55:27,386 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:55:27,386 INFO L87 Difference]: Start difference. First operand 8187 states and 23603 transitions. Second operand 7 states. [2019-12-07 18:55:27,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:27,859 INFO L93 Difference]: Finished difference Result 11659 states and 33360 transitions. [2019-12-07 18:55:27,859 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 18:55:27,859 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 65 [2019-12-07 18:55:27,859 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:27,869 INFO L225 Difference]: With dead ends: 11659 [2019-12-07 18:55:27,869 INFO L226 Difference]: Without dead ends: 11659 [2019-12-07 18:55:27,870 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 11 SyntacticMatches, 2 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=72, Invalid=200, Unknown=0, NotChecked=0, Total=272 [2019-12-07 18:55:27,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11659 states. [2019-12-07 18:55:27,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11659 to 8348. [2019-12-07 18:55:27,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8348 states. [2019-12-07 18:55:27,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8348 states to 8348 states and 24042 transitions. [2019-12-07 18:55:27,996 INFO L78 Accepts]: Start accepts. Automaton has 8348 states and 24042 transitions. Word has length 65 [2019-12-07 18:55:27,996 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:27,996 INFO L462 AbstractCegarLoop]: Abstraction has 8348 states and 24042 transitions. [2019-12-07 18:55:27,996 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:55:27,996 INFO L276 IsEmpty]: Start isEmpty. Operand 8348 states and 24042 transitions. [2019-12-07 18:55:28,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:55:28,003 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:28,003 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:28,003 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:28,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:28,003 INFO L82 PathProgramCache]: Analyzing trace with hash 695487673, now seen corresponding path program 5 times [2019-12-07 18:55:28,004 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:28,004 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1905185467] [2019-12-07 18:55:28,004 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:28,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:28,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:28,054 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1905185467] [2019-12-07 18:55:28,054 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:28,054 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:55:28,054 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1049886070] [2019-12-07 18:55:28,054 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:55:28,055 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:28,055 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:55:28,055 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:55:28,055 INFO L87 Difference]: Start difference. First operand 8348 states and 24042 transitions. Second operand 6 states. [2019-12-07 18:55:28,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:28,378 INFO L93 Difference]: Finished difference Result 11624 states and 32873 transitions. [2019-12-07 18:55:28,379 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 18:55:28,379 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 65 [2019-12-07 18:55:28,379 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:28,388 INFO L225 Difference]: With dead ends: 11624 [2019-12-07 18:55:28,388 INFO L226 Difference]: Without dead ends: 11624 [2019-12-07 18:55:28,388 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:55:28,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11624 states. [2019-12-07 18:55:28,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11624 to 8586. [2019-12-07 18:55:28,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8586 states. [2019-12-07 18:55:28,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8586 states to 8586 states and 24721 transitions. [2019-12-07 18:55:28,516 INFO L78 Accepts]: Start accepts. Automaton has 8586 states and 24721 transitions. Word has length 65 [2019-12-07 18:55:28,516 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:28,516 INFO L462 AbstractCegarLoop]: Abstraction has 8586 states and 24721 transitions. [2019-12-07 18:55:28,516 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:55:28,516 INFO L276 IsEmpty]: Start isEmpty. Operand 8586 states and 24721 transitions. [2019-12-07 18:55:28,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:55:28,523 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:28,523 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:28,523 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:28,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:28,524 INFO L82 PathProgramCache]: Analyzing trace with hash -1544002871, now seen corresponding path program 6 times [2019-12-07 18:55:28,524 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:28,524 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1966634054] [2019-12-07 18:55:28,524 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:28,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:28,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:28,580 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1966634054] [2019-12-07 18:55:28,580 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:28,580 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 18:55:28,580 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1873666789] [2019-12-07 18:55:28,580 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:55:28,580 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:28,580 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:55:28,580 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:55:28,580 INFO L87 Difference]: Start difference. First operand 8586 states and 24721 transitions. Second operand 7 states. [2019-12-07 18:55:29,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:29,160 INFO L93 Difference]: Finished difference Result 11785 states and 33389 transitions. [2019-12-07 18:55:29,160 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 18:55:29,160 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 65 [2019-12-07 18:55:29,160 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:29,170 INFO L225 Difference]: With dead ends: 11785 [2019-12-07 18:55:29,170 INFO L226 Difference]: Without dead ends: 11785 [2019-12-07 18:55:29,171 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 8 SyntacticMatches, 2 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 100 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=110, Invalid=396, Unknown=0, NotChecked=0, Total=506 [2019-12-07 18:55:29,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11785 states. [2019-12-07 18:55:29,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11785 to 8963. [2019-12-07 18:55:29,289 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8963 states. [2019-12-07 18:55:29,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8963 states to 8963 states and 25746 transitions. [2019-12-07 18:55:29,300 INFO L78 Accepts]: Start accepts. Automaton has 8963 states and 25746 transitions. Word has length 65 [2019-12-07 18:55:29,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:29,301 INFO L462 AbstractCegarLoop]: Abstraction has 8963 states and 25746 transitions. [2019-12-07 18:55:29,301 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:55:29,301 INFO L276 IsEmpty]: Start isEmpty. Operand 8963 states and 25746 transitions. [2019-12-07 18:55:29,307 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:55:29,307 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:29,307 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:29,307 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:29,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:29,308 INFO L82 PathProgramCache]: Analyzing trace with hash -323311555, now seen corresponding path program 7 times [2019-12-07 18:55:29,308 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:29,308 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [285715136] [2019-12-07 18:55:29,308 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:29,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:29,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:29,364 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [285715136] [2019-12-07 18:55:29,364 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:29,364 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 18:55:29,364 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1951849538] [2019-12-07 18:55:29,364 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:55:29,364 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:29,364 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:55:29,364 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:55:29,365 INFO L87 Difference]: Start difference. First operand 8963 states and 25746 transitions. Second operand 7 states. [2019-12-07 18:55:29,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:29,888 INFO L93 Difference]: Finished difference Result 12966 states and 36969 transitions. [2019-12-07 18:55:29,889 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 18:55:29,889 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 65 [2019-12-07 18:55:29,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:29,900 INFO L225 Difference]: With dead ends: 12966 [2019-12-07 18:55:29,900 INFO L226 Difference]: Without dead ends: 12966 [2019-12-07 18:55:29,900 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 11 SyntacticMatches, 2 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=72, Invalid=200, Unknown=0, NotChecked=0, Total=272 [2019-12-07 18:55:29,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12966 states. [2019-12-07 18:55:30,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12966 to 8793. [2019-12-07 18:55:30,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8793 states. [2019-12-07 18:55:30,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8793 states to 8793 states and 25290 transitions. [2019-12-07 18:55:30,036 INFO L78 Accepts]: Start accepts. Automaton has 8793 states and 25290 transitions. Word has length 65 [2019-12-07 18:55:30,037 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:30,037 INFO L462 AbstractCegarLoop]: Abstraction has 8793 states and 25290 transitions. [2019-12-07 18:55:30,037 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:55:30,037 INFO L276 IsEmpty]: Start isEmpty. Operand 8793 states and 25290 transitions. [2019-12-07 18:55:30,044 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:55:30,045 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:30,045 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:30,045 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:30,045 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:30,045 INFO L82 PathProgramCache]: Analyzing trace with hash 2116191721, now seen corresponding path program 8 times [2019-12-07 18:55:30,045 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:30,045 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1023938470] [2019-12-07 18:55:30,046 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:30,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:30,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:30,072 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1023938470] [2019-12-07 18:55:30,072 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:30,072 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:55:30,072 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1506426573] [2019-12-07 18:55:30,072 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:55:30,072 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:30,072 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:55:30,072 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:55:30,073 INFO L87 Difference]: Start difference. First operand 8793 states and 25290 transitions. Second operand 3 states. [2019-12-07 18:55:30,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:30,097 INFO L93 Difference]: Finished difference Result 7716 states and 21836 transitions. [2019-12-07 18:55:30,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:55:30,098 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 18:55:30,098 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:30,107 INFO L225 Difference]: With dead ends: 7716 [2019-12-07 18:55:30,107 INFO L226 Difference]: Without dead ends: 7716 [2019-12-07 18:55:30,107 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:55:30,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7716 states. [2019-12-07 18:55:30,197 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7716 to 7716. [2019-12-07 18:55:30,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7716 states. [2019-12-07 18:55:30,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7716 states to 7716 states and 21836 transitions. [2019-12-07 18:55:30,207 INFO L78 Accepts]: Start accepts. Automaton has 7716 states and 21836 transitions. Word has length 65 [2019-12-07 18:55:30,207 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:30,207 INFO L462 AbstractCegarLoop]: Abstraction has 7716 states and 21836 transitions. [2019-12-07 18:55:30,207 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:55:30,207 INFO L276 IsEmpty]: Start isEmpty. Operand 7716 states and 21836 transitions. [2019-12-07 18:55:30,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 18:55:30,212 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:30,213 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:30,213 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:30,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:30,213 INFO L82 PathProgramCache]: Analyzing trace with hash 924001521, now seen corresponding path program 1 times [2019-12-07 18:55:30,213 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:30,213 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [374947701] [2019-12-07 18:55:30,213 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:30,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:30,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:30,242 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [374947701] [2019-12-07 18:55:30,242 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:30,242 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:55:30,242 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [96858480] [2019-12-07 18:55:30,242 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:55:30,242 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:30,243 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:55:30,243 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:55:30,243 INFO L87 Difference]: Start difference. First operand 7716 states and 21836 transitions. Second operand 3 states. [2019-12-07 18:55:30,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:30,287 INFO L93 Difference]: Finished difference Result 7716 states and 21835 transitions. [2019-12-07 18:55:30,287 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:55:30,287 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 18:55:30,287 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:30,296 INFO L225 Difference]: With dead ends: 7716 [2019-12-07 18:55:30,296 INFO L226 Difference]: Without dead ends: 7716 [2019-12-07 18:55:30,296 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:55:30,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7716 states. [2019-12-07 18:55:30,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7716 to 4983. [2019-12-07 18:55:30,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4983 states. [2019-12-07 18:55:30,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4983 states to 4983 states and 14209 transitions. [2019-12-07 18:55:30,369 INFO L78 Accepts]: Start accepts. Automaton has 4983 states and 14209 transitions. Word has length 66 [2019-12-07 18:55:30,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:30,369 INFO L462 AbstractCegarLoop]: Abstraction has 4983 states and 14209 transitions. [2019-12-07 18:55:30,370 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:55:30,370 INFO L276 IsEmpty]: Start isEmpty. Operand 4983 states and 14209 transitions. [2019-12-07 18:55:30,373 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:55:30,373 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:30,373 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:30,373 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:30,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:30,373 INFO L82 PathProgramCache]: Analyzing trace with hash 1781723931, now seen corresponding path program 1 times [2019-12-07 18:55:30,373 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:30,373 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335673919] [2019-12-07 18:55:30,374 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:30,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:30,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:30,442 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [335673919] [2019-12-07 18:55:30,442 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:30,442 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:55:30,442 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2120094004] [2019-12-07 18:55:30,442 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:55:30,442 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:30,442 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:55:30,442 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:55:30,442 INFO L87 Difference]: Start difference. First operand 4983 states and 14209 transitions. Second operand 6 states. [2019-12-07 18:55:30,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:30,499 INFO L93 Difference]: Finished difference Result 8628 states and 24566 transitions. [2019-12-07 18:55:30,499 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:55:30,499 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 67 [2019-12-07 18:55:30,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:30,504 INFO L225 Difference]: With dead ends: 8628 [2019-12-07 18:55:30,504 INFO L226 Difference]: Without dead ends: 4601 [2019-12-07 18:55:30,505 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:55:30,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4601 states. [2019-12-07 18:55:30,558 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4601 to 4601. [2019-12-07 18:55:30,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4601 states. [2019-12-07 18:55:30,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4601 states to 4601 states and 13097 transitions. [2019-12-07 18:55:30,564 INFO L78 Accepts]: Start accepts. Automaton has 4601 states and 13097 transitions. Word has length 67 [2019-12-07 18:55:30,564 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:30,564 INFO L462 AbstractCegarLoop]: Abstraction has 4601 states and 13097 transitions. [2019-12-07 18:55:30,564 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:55:30,564 INFO L276 IsEmpty]: Start isEmpty. Operand 4601 states and 13097 transitions. [2019-12-07 18:55:30,567 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:55:30,567 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:30,567 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:30,567 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:30,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:30,567 INFO L82 PathProgramCache]: Analyzing trace with hash 728190721, now seen corresponding path program 2 times [2019-12-07 18:55:30,567 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:30,567 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1838574816] [2019-12-07 18:55:30,568 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:30,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:30,608 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:30,608 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1838574816] [2019-12-07 18:55:30,608 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:30,608 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:55:30,608 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [787113269] [2019-12-07 18:55:30,608 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:55:30,608 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:30,609 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:55:30,609 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:55:30,609 INFO L87 Difference]: Start difference. First operand 4601 states and 13097 transitions. Second operand 3 states. [2019-12-07 18:55:30,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:30,624 INFO L93 Difference]: Finished difference Result 4379 states and 12167 transitions. [2019-12-07 18:55:30,624 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:55:30,624 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 18:55:30,625 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:30,628 INFO L225 Difference]: With dead ends: 4379 [2019-12-07 18:55:30,628 INFO L226 Difference]: Without dead ends: 4379 [2019-12-07 18:55:30,628 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:55:30,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4379 states. [2019-12-07 18:55:30,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4379 to 4177. [2019-12-07 18:55:30,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4177 states. [2019-12-07 18:55:30,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4177 states to 4177 states and 11620 transitions. [2019-12-07 18:55:30,680 INFO L78 Accepts]: Start accepts. Automaton has 4177 states and 11620 transitions. Word has length 67 [2019-12-07 18:55:30,680 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:30,680 INFO L462 AbstractCegarLoop]: Abstraction has 4177 states and 11620 transitions. [2019-12-07 18:55:30,680 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:55:30,680 INFO L276 IsEmpty]: Start isEmpty. Operand 4177 states and 11620 transitions. [2019-12-07 18:55:30,682 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:55:30,683 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:30,683 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:30,683 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:30,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:30,683 INFO L82 PathProgramCache]: Analyzing trace with hash -829052917, now seen corresponding path program 1 times [2019-12-07 18:55:30,683 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:30,683 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1090907722] [2019-12-07 18:55:30,683 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:30,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:30,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:30,856 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1090907722] [2019-12-07 18:55:30,856 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:30,856 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 18:55:30,857 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [421333854] [2019-12-07 18:55:30,857 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 18:55:30,857 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:30,857 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 18:55:30,857 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=173, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:55:30,857 INFO L87 Difference]: Start difference. First operand 4177 states and 11620 transitions. Second operand 15 states. [2019-12-07 18:55:31,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:31,433 INFO L93 Difference]: Finished difference Result 7316 states and 20129 transitions. [2019-12-07 18:55:31,433 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 18:55:31,433 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 68 [2019-12-07 18:55:31,434 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:31,439 INFO L225 Difference]: With dead ends: 7316 [2019-12-07 18:55:31,439 INFO L226 Difference]: Without dead ends: 6470 [2019-12-07 18:55:31,439 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 251 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=289, Invalid=1043, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 18:55:31,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6470 states. [2019-12-07 18:55:31,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6470 to 5479. [2019-12-07 18:55:31,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5479 states. [2019-12-07 18:55:31,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5479 states to 5479 states and 15091 transitions. [2019-12-07 18:55:31,506 INFO L78 Accepts]: Start accepts. Automaton has 5479 states and 15091 transitions. Word has length 68 [2019-12-07 18:55:31,506 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:31,506 INFO L462 AbstractCegarLoop]: Abstraction has 5479 states and 15091 transitions. [2019-12-07 18:55:31,506 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 18:55:31,507 INFO L276 IsEmpty]: Start isEmpty. Operand 5479 states and 15091 transitions. [2019-12-07 18:55:31,510 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:55:31,510 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:31,510 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:31,510 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:31,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:31,510 INFO L82 PathProgramCache]: Analyzing trace with hash 1851838847, now seen corresponding path program 2 times [2019-12-07 18:55:31,510 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:31,510 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1323440987] [2019-12-07 18:55:31,510 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:31,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:55:31,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:55:31,579 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:55:31,579 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 18:55:31,582 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] ULTIMATE.startENTRY-->L805: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t2025~0.base_21| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t2025~0.base_21|) |v_ULTIMATE.start_main_~#t2025~0.offset_17| 0)) |v_#memory_int_21|) (= v_~__unbuffered_cnt~0_140 0) (= 0 v_~z$flush_delayed~0_34) (= v_~z$r_buff1_thd0~0_308 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t2025~0.base_21|) (= v_~z$w_buff1_used~0_516 0) (= |v_#valid_53| (store .cse0 |v_ULTIMATE.start_main_~#t2025~0.base_21| 1)) (= v_~z$r_buff1_thd1~0_190 0) (= 0 |v_ULTIMATE.start_main_~#t2025~0.offset_17|) (= v_~z$read_delayed~0_8 0) (= v_~z$w_buff0~0_342 0) (= v_~main$tmp_guard1~0_21 0) (= v_~z$read_delayed_var~0.offset_7 0) (= (store |v_#length_26| |v_ULTIMATE.start_main_~#t2025~0.base_21| 4) |v_#length_25|) (< 0 |v_#StackHeapBarrier_18|) (= v_~z$r_buff1_thd2~0_206 0) (= v_~y~0_34 0) (= 0 |v_#NULL.base_4|) (= 0 v_~z$r_buff0_thd3~0_140) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$r_buff0_thd1~0_226 0) (= v_~main$tmp_guard0~0_21 0) (= v_~weak$$choice2~0_109 0) (= v_~z$mem_tmp~0_19 0) (= v_~z$r_buff0_thd0~0_374 0) (= |v_#NULL.offset_4| 0) (= 0 v_~z$r_buff1_thd3~0_196) (= v_~z$r_buff0_thd2~0_140 0) (= (select .cse0 |v_ULTIMATE.start_main_~#t2025~0.base_21|) 0) (= 0 v_~__unbuffered_p2_EAX~0_36) (= v_~z$w_buff0_used~0_875 0) (= 0 v_~weak$$choice0~0_13) (= v_~z$w_buff1~0_249 0) (= 0 v_~x~0_138) (= v_~z~0_182 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_22|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_21|, ULTIMATE.start_main_~#t2026~0.base=|v_ULTIMATE.start_main_~#t2026~0.base_20|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_27|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_206, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_39|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_29|, ULTIMATE.start_main_~#t2026~0.offset=|v_ULTIMATE.start_main_~#t2026~0.offset_17|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_49|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_47|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_25|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_45|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_32|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_374, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_36, ~z$mem_tmp~0=v_~z$mem_tmp~0_19, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_43|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_516, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_52|, ULTIMATE.start_main_~#t2027~0.base=|v_ULTIMATE.start_main_~#t2027~0.base_20|, ~z$flush_delayed~0=v_~z$flush_delayed~0_34, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_111|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_32|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_190, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_140, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_140, ~x~0=v_~x~0_138, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_33|, ~z$read_delayed~0=v_~z$read_delayed~0_8, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_31|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_29|, ~z$w_buff1~0=v_~z$w_buff1~0_249, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_121|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_17|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_25|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_41|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_31|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_308, ULTIMATE.start_main_~#t2025~0.offset=|v_ULTIMATE.start_main_~#t2025~0.offset_17|, ~y~0=v_~y~0_34, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_140, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_10|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_21|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_875, ~z$w_buff0~0=v_~z$w_buff0~0_342, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_196, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_25|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_54|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_21, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_59|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_38|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_32|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_21|, ULTIMATE.start_main_~#t2025~0.base=|v_ULTIMATE.start_main_~#t2025~0.base_21|, ~z~0=v_~z~0_182, ~weak$$choice2~0=v_~weak$$choice2~0_109, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_226, ULTIMATE.start_main_~#t2027~0.offset=|v_ULTIMATE.start_main_~#t2027~0.offset_16|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_~#t2026~0.base, ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_~#t2026~0.offset, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_~#t2027~0.base, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ULTIMATE.start_main_~#t2025~0.offset, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_~#t2025~0.base, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0, ULTIMATE.start_main_~#t2027~0.offset] because there is no mapped edge [2019-12-07 18:55:31,582 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L805-1-->L807: Formula: (and (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2026~0.base_12| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2026~0.base_12|) |v_ULTIMATE.start_main_~#t2026~0.offset_11| 1))) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t2026~0.base_12| 4)) (= (select |v_#valid_35| |v_ULTIMATE.start_main_~#t2026~0.base_12|) 0) (not (= 0 |v_ULTIMATE.start_main_~#t2026~0.base_12|)) (= 0 |v_ULTIMATE.start_main_~#t2026~0.offset_11|) (= (store |v_#valid_35| |v_ULTIMATE.start_main_~#t2026~0.base_12| 1) |v_#valid_34|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t2026~0.base_12|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t2026~0.base=|v_ULTIMATE.start_main_~#t2026~0.base_12|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_6|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t2026~0.offset=|v_ULTIMATE.start_main_~#t2026~0.offset_11|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2026~0.base, ULTIMATE.start_main_#t~nondet21, #valid, #memory_int, ULTIMATE.start_main_~#t2026~0.offset, #length] because there is no mapped edge [2019-12-07 18:55:31,582 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] P0ENTRY-->L4-3: Formula: (and (= v_~z$w_buff0_used~0_226 v_~z$w_buff1_used~0_114) (= v_P0Thread1of1ForFork0_~arg.base_20 |v_P0Thread1of1ForFork0_#in~arg.base_22|) (= 2 v_~z$w_buff0~0_55) (= v_~z$w_buff0~0_56 v_~z$w_buff1~0_53) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_24 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_20|) (= (ite (not (and (not (= 0 (mod v_~z$w_buff0_used~0_225 256))) (not (= 0 (mod v_~z$w_buff1_used~0_114 256))))) 1 0) |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_20|) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_24 0)) (= v_P0Thread1of1ForFork0_~arg.offset_20 |v_P0Thread1of1ForFork0_#in~arg.offset_22|) (= v_~z$w_buff0_used~0_225 1)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_226, ~z$w_buff0~0=v_~z$w_buff0~0_56, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_22|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_225, ~z$w_buff0~0=v_~z$w_buff0~0_55, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_24, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_114, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_22|, ~z$w_buff1~0=v_~z$w_buff1~0_53, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_20, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_20|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_20} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 18:55:31,583 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L807-1-->L809: Formula: (and (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t2027~0.base_9|) (not (= 0 |v_ULTIMATE.start_main_~#t2027~0.base_9|)) (= |v_#memory_int_9| (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2027~0.base_9| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2027~0.base_9|) |v_ULTIMATE.start_main_~#t2027~0.offset_8| 2))) (= (store |v_#length_14| |v_ULTIMATE.start_main_~#t2027~0.base_9| 4) |v_#length_13|) (= 0 (select |v_#valid_28| |v_ULTIMATE.start_main_~#t2027~0.base_9|)) (= 0 |v_ULTIMATE.start_main_~#t2027~0.offset_8|) (= (store |v_#valid_28| |v_ULTIMATE.start_main_~#t2027~0.base_9| 1) |v_#valid_27|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_28|, #memory_int=|v_#memory_int_10|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_27|, #memory_int=|v_#memory_int_9|, #length=|v_#length_13|, ULTIMATE.start_main_~#t2027~0.base=|v_ULTIMATE.start_main_~#t2027~0.base_9|, ULTIMATE.start_main_~#t2027~0.offset=|v_ULTIMATE.start_main_~#t2027~0.offset_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t2027~0.base, ULTIMATE.start_main_~#t2027~0.offset] because there is no mapped edge [2019-12-07 18:55:31,583 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L743-->L743-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-1179045677 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In-1179045677 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P0Thread1of1ForFork0_#t~ite5_Out-1179045677|)) (and (or .cse1 .cse0) (= ~z$w_buff0_used~0_In-1179045677 |P0Thread1of1ForFork0_#t~ite5_Out-1179045677|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1179045677, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1179045677} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-1179045677|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1179045677, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1179045677} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 18:55:31,584 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L744-->L744-2: Formula: (let ((.cse3 (= (mod ~z$r_buff1_thd1~0_In-928969378 256) 0)) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-928969378 256))) (.cse0 (= (mod ~z$r_buff0_thd1~0_In-928969378 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-928969378 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork0_#t~ite6_Out-928969378|)) (and (or .cse3 .cse2) (= ~z$w_buff1_used~0_In-928969378 |P0Thread1of1ForFork0_#t~ite6_Out-928969378|) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-928969378, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-928969378, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-928969378, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-928969378} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out-928969378|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-928969378, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-928969378, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-928969378, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-928969378} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 18:55:31,584 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L745-->L746: Formula: (let ((.cse0 (= ~z$r_buff0_thd1~0_In968733521 ~z$r_buff0_thd1~0_Out968733521)) (.cse2 (= (mod ~z$r_buff0_thd1~0_In968733521 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In968733521 256) 0))) (or (and .cse0 .cse1) (and .cse0 .cse2) (and (= 0 ~z$r_buff0_thd1~0_Out968733521) (not .cse2) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In968733521, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In968733521} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In968733521, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out968733521|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out968733521} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 18:55:31,585 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L746-->L746-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In-1263679357 256))) (.cse1 (= (mod ~z$r_buff1_thd1~0_In-1263679357 256) 0)) (.cse3 (= (mod ~z$r_buff0_thd1~0_In-1263679357 256) 0)) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-1263679357 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite8_Out-1263679357| 0)) (and (or .cse0 .cse1) (or .cse3 .cse2) (= |P0Thread1of1ForFork0_#t~ite8_Out-1263679357| ~z$r_buff1_thd1~0_In-1263679357)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1263679357, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1263679357, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1263679357, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1263679357} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1263679357, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-1263679357|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1263679357, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1263679357, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1263679357} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 18:55:31,585 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L746-2-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_44 1) v_~__unbuffered_cnt~0_43) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_63 |v_P0Thread1of1ForFork0_#t~ite8_26|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_44} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_25|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_63, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_43} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 18:55:31,585 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L762-2-->L762-5: Formula: (let ((.cse0 (= |P1Thread1of1ForFork1_#t~ite10_Out1290905860| |P1Thread1of1ForFork1_#t~ite9_Out1290905860|)) (.cse1 (= (mod ~z$r_buff1_thd2~0_In1290905860 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In1290905860 256) 0))) (or (and .cse0 (not .cse1) (not .cse2) (= ~z$w_buff1~0_In1290905860 |P1Thread1of1ForFork1_#t~ite9_Out1290905860|)) (and (= ~z~0_In1290905860 |P1Thread1of1ForFork1_#t~ite9_Out1290905860|) .cse0 (or .cse1 .cse2)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1290905860, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1290905860, ~z$w_buff1~0=~z$w_buff1~0_In1290905860, ~z~0=~z~0_In1290905860} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out1290905860|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1290905860, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1290905860, P1Thread1of1ForFork1_#t~ite10=|P1Thread1of1ForFork1_#t~ite10_Out1290905860|, ~z$w_buff1~0=~z$w_buff1~0_In1290905860, ~z~0=~z~0_In1290905860} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10] because there is no mapped edge [2019-12-07 18:55:31,585 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L782-2-->L782-4: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd3~0_In-2039380594 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-2039380594 256)))) (or (and (or .cse0 .cse1) (= ~z~0_In-2039380594 |P2Thread1of1ForFork2_#t~ite15_Out-2039380594|)) (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In-2039380594 |P2Thread1of1ForFork2_#t~ite15_Out-2039380594|)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-2039380594, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2039380594, ~z$w_buff1~0=~z$w_buff1~0_In-2039380594, ~z~0=~z~0_In-2039380594} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-2039380594|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-2039380594, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2039380594, ~z$w_buff1~0=~z$w_buff1~0_In-2039380594, ~z~0=~z~0_In-2039380594} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 18:55:31,585 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L782-4-->L783: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~z~0_20) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, ~z~0=v_~z~0_20, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_11|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~z~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 18:55:31,585 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [774] [774] L783-->L783-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-612522564 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-612522564 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite17_Out-612522564| 0) (not .cse0) (not .cse1)) (and (= |P2Thread1of1ForFork2_#t~ite17_Out-612522564| ~z$w_buff0_used~0_In-612522564) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-612522564, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-612522564} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-612522564, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-612522564, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out-612522564|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 18:55:31,586 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L784-->L784-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd3~0_In-1921554792 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-1921554792 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-1921554792 256))) (.cse1 (= (mod ~z$r_buff1_thd3~0_In-1921554792 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite18_Out-1921554792|)) (and (= ~z$w_buff1_used~0_In-1921554792 |P2Thread1of1ForFork2_#t~ite18_Out-1921554792|) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1921554792, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1921554792, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1921554792, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1921554792} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1921554792, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1921554792, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1921554792, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1921554792, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-1921554792|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 18:55:31,586 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L785-->L785-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd3~0_In-1500518232 256) 0)) (.cse0 (= (mod ~z$w_buff0_used~0_In-1500518232 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite19_Out-1500518232| 0) (not .cse0) (not .cse1)) (and (= ~z$r_buff0_thd3~0_In-1500518232 |P2Thread1of1ForFork2_#t~ite19_Out-1500518232|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1500518232, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1500518232} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1500518232, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1500518232, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-1500518232|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 18:55:31,586 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L786-->L786-2: Formula: (let ((.cse3 (= 0 (mod ~z$w_buff1_used~0_In-1189064342 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In-1189064342 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1189064342 256))) (.cse1 (= (mod ~z$r_buff0_thd3~0_In-1189064342 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork2_#t~ite20_Out-1189064342| 0)) (and (or .cse3 .cse2) (= |P2Thread1of1ForFork2_#t~ite20_Out-1189064342| ~z$r_buff1_thd3~0_In-1189064342) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1189064342, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1189064342, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1189064342, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1189064342} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1189064342, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-1189064342|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1189064342, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1189064342, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1189064342} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 18:55:31,586 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L786-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_54 (+ v_~__unbuffered_cnt~0_55 1)) (= |v_P2Thread1of1ForFork2_#t~ite20_30| v_~z$r_buff1_thd3~0_67)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_30|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_29|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_67, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 18:55:31,587 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L763-->L763-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In847495186 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In847495186 256)))) (or (and (= |P1Thread1of1ForFork1_#t~ite11_Out847495186| 0) (not .cse0) (not .cse1)) (and (= |P1Thread1of1ForFork1_#t~ite11_Out847495186| ~z$w_buff0_used~0_In847495186) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In847495186, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In847495186} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In847495186, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out847495186|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In847495186} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 18:55:31,587 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L764-->L764-2: Formula: (let ((.cse3 (= (mod ~z$r_buff1_thd2~0_In-516925516 256) 0)) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-516925516 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-516925516 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In-516925516 256) 0))) (or (and (= ~z$w_buff1_used~0_In-516925516 |P1Thread1of1ForFork1_#t~ite12_Out-516925516|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out-516925516|) (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-516925516, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-516925516, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-516925516, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-516925516} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-516925516, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-516925516, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-516925516, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-516925516|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-516925516} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 18:55:31,587 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L765-->L765-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1242086709 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-1242086709 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite13_Out-1242086709|) (not .cse0) (not .cse1)) (and (= ~z$r_buff0_thd2~0_In-1242086709 |P1Thread1of1ForFork1_#t~ite13_Out-1242086709|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1242086709, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1242086709} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1242086709, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-1242086709|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1242086709} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 18:55:31,588 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L766-->L766-2: Formula: (let ((.cse3 (= 0 (mod ~z$w_buff0_used~0_In875920522 256))) (.cse2 (= (mod ~z$r_buff0_thd2~0_In875920522 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd2~0_In875920522 256) 0)) (.cse0 (= (mod ~z$w_buff1_used~0_In875920522 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork1_#t~ite14_Out875920522|)) (and (or .cse3 .cse2) (= |P1Thread1of1ForFork1_#t~ite14_Out875920522| ~z$r_buff1_thd2~0_In875920522) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In875920522, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In875920522, ~z$w_buff1_used~0=~z$w_buff1_used~0_In875920522, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In875920522} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In875920522, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In875920522, ~z$w_buff1_used~0=~z$w_buff1_used~0_In875920522, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out875920522|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In875920522} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 18:55:31,588 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L766-2-->P1EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_61 1) v_~__unbuffered_cnt~0_60) (= |v_P1Thread1of1ForFork1_#t~ite14_30| v_~z$r_buff1_thd2~0_84) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_61, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_30|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_84, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_60, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_29|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 18:55:31,588 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L809-1-->L815: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (= v_~main$tmp_guard0~0_8 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_18) 1 0) 0) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_18} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_7|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_18, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:55:31,588 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L815-2-->L815-5: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite25_Out-1778705683| |ULTIMATE.start_main_#t~ite24_Out-1778705683|)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-1778705683 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In-1778705683 256) 0))) (or (and .cse0 (= ~z~0_In-1778705683 |ULTIMATE.start_main_#t~ite24_Out-1778705683|) (or .cse1 .cse2)) (and .cse0 (not .cse1) (not .cse2) (= ~z$w_buff1~0_In-1778705683 |ULTIMATE.start_main_#t~ite24_Out-1778705683|)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1778705683, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1778705683, ~z$w_buff1~0=~z$w_buff1~0_In-1778705683, ~z~0=~z~0_In-1778705683} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1778705683, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-1778705683|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1778705683, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-1778705683|, ~z$w_buff1~0=~z$w_buff1~0_In-1778705683, ~z~0=~z~0_In-1778705683} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 18:55:31,588 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [768] [768] L816-->L816-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In-51037365 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-51037365 256)))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite26_Out-51037365|)) (and (= |ULTIMATE.start_main_#t~ite26_Out-51037365| ~z$w_buff0_used~0_In-51037365) (or .cse1 .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-51037365, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-51037365} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-51037365, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-51037365, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-51037365|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 18:55:31,589 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L817-->L817-2: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In-1957311214 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-1957311214 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-1957311214 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd0~0_In-1957311214 256)))) (or (and (= 0 |ULTIMATE.start_main_#t~ite27_Out-1957311214|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$w_buff1_used~0_In-1957311214 |ULTIMATE.start_main_#t~ite27_Out-1957311214|) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1957311214, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1957311214, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1957311214, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1957311214} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1957311214, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1957311214, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1957311214, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1957311214, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-1957311214|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 18:55:31,589 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L818-->L818-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In1162972327 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd0~0_In1162972327 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite28_Out1162972327|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite28_Out1162972327| ~z$r_buff0_thd0~0_In1162972327)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1162972327, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1162972327} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1162972327, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out1162972327|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1162972327} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 18:55:31,589 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L819-->L819-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In-1867632557 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1867632557 256))) (.cse2 (= (mod ~z$r_buff0_thd0~0_In-1867632557 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In-1867632557 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite29_Out-1867632557| ~z$r_buff1_thd0~0_In-1867632557) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |ULTIMATE.start_main_#t~ite29_Out-1867632557| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1867632557, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1867632557, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1867632557, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1867632557} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1867632557, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-1867632557|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1867632557, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1867632557, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1867632557} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 18:55:31,592 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L831-->L832: Formula: (and (= v_~z$r_buff0_thd0~0_103 v_~z$r_buff0_thd0~0_102) (not (= (mod v_~weak$$choice2~0_23 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_103, ~weak$$choice2~0=v_~weak$$choice2~0_23} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_102, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_6|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_10|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_6|, ~weak$$choice2~0=v_~weak$$choice2~0_23} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 18:55:31,592 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L834-->L837-1: Formula: (and (= v_~z$mem_tmp~0_11 v_~z~0_133) (= (mod v_~main$tmp_guard1~0_9 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (not (= 0 (mod v_~z$flush_delayed~0_21 256))) (= 0 v_~z$flush_delayed~0_20)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_11, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_9, ~z$flush_delayed~0=v_~z$flush_delayed~0_21} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_11, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_18|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_9, ~z$flush_delayed~0=v_~z$flush_delayed~0_20, ~z~0=v_~z~0_133, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:55:31,592 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L837-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:55:31,652 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 06:55:31 BasicIcfg [2019-12-07 18:55:31,652 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 18:55:31,652 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:55:31,652 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:55:31,652 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:55:31,653 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:54:20" (3/4) ... [2019-12-07 18:55:31,654 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 18:55:31,655 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] ULTIMATE.startENTRY-->L805: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t2025~0.base_21| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t2025~0.base_21|) |v_ULTIMATE.start_main_~#t2025~0.offset_17| 0)) |v_#memory_int_21|) (= v_~__unbuffered_cnt~0_140 0) (= 0 v_~z$flush_delayed~0_34) (= v_~z$r_buff1_thd0~0_308 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t2025~0.base_21|) (= v_~z$w_buff1_used~0_516 0) (= |v_#valid_53| (store .cse0 |v_ULTIMATE.start_main_~#t2025~0.base_21| 1)) (= v_~z$r_buff1_thd1~0_190 0) (= 0 |v_ULTIMATE.start_main_~#t2025~0.offset_17|) (= v_~z$read_delayed~0_8 0) (= v_~z$w_buff0~0_342 0) (= v_~main$tmp_guard1~0_21 0) (= v_~z$read_delayed_var~0.offset_7 0) (= (store |v_#length_26| |v_ULTIMATE.start_main_~#t2025~0.base_21| 4) |v_#length_25|) (< 0 |v_#StackHeapBarrier_18|) (= v_~z$r_buff1_thd2~0_206 0) (= v_~y~0_34 0) (= 0 |v_#NULL.base_4|) (= 0 v_~z$r_buff0_thd3~0_140) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$r_buff0_thd1~0_226 0) (= v_~main$tmp_guard0~0_21 0) (= v_~weak$$choice2~0_109 0) (= v_~z$mem_tmp~0_19 0) (= v_~z$r_buff0_thd0~0_374 0) (= |v_#NULL.offset_4| 0) (= 0 v_~z$r_buff1_thd3~0_196) (= v_~z$r_buff0_thd2~0_140 0) (= (select .cse0 |v_ULTIMATE.start_main_~#t2025~0.base_21|) 0) (= 0 v_~__unbuffered_p2_EAX~0_36) (= v_~z$w_buff0_used~0_875 0) (= 0 v_~weak$$choice0~0_13) (= v_~z$w_buff1~0_249 0) (= 0 v_~x~0_138) (= v_~z~0_182 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_22|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_21|, ULTIMATE.start_main_~#t2026~0.base=|v_ULTIMATE.start_main_~#t2026~0.base_20|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_27|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_206, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_39|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_29|, ULTIMATE.start_main_~#t2026~0.offset=|v_ULTIMATE.start_main_~#t2026~0.offset_17|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_49|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_47|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_25|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_45|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_32|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_374, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_36, ~z$mem_tmp~0=v_~z$mem_tmp~0_19, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_43|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_516, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_52|, ULTIMATE.start_main_~#t2027~0.base=|v_ULTIMATE.start_main_~#t2027~0.base_20|, ~z$flush_delayed~0=v_~z$flush_delayed~0_34, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_111|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_32|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_190, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_140, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_140, ~x~0=v_~x~0_138, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_33|, ~z$read_delayed~0=v_~z$read_delayed~0_8, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_31|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_29|, ~z$w_buff1~0=v_~z$w_buff1~0_249, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_121|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_17|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_25|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_41|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_31|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_308, ULTIMATE.start_main_~#t2025~0.offset=|v_ULTIMATE.start_main_~#t2025~0.offset_17|, ~y~0=v_~y~0_34, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_140, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_10|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_21|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_875, ~z$w_buff0~0=v_~z$w_buff0~0_342, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_196, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_25|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_54|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_21, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_59|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_38|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_32|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_21|, ULTIMATE.start_main_~#t2025~0.base=|v_ULTIMATE.start_main_~#t2025~0.base_21|, ~z~0=v_~z~0_182, ~weak$$choice2~0=v_~weak$$choice2~0_109, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_226, ULTIMATE.start_main_~#t2027~0.offset=|v_ULTIMATE.start_main_~#t2027~0.offset_16|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_~#t2026~0.base, ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_~#t2026~0.offset, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_~#t2027~0.base, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ULTIMATE.start_main_~#t2025~0.offset, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_~#t2025~0.base, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0, ULTIMATE.start_main_~#t2027~0.offset] because there is no mapped edge [2019-12-07 18:55:31,655 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L805-1-->L807: Formula: (and (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2026~0.base_12| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2026~0.base_12|) |v_ULTIMATE.start_main_~#t2026~0.offset_11| 1))) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t2026~0.base_12| 4)) (= (select |v_#valid_35| |v_ULTIMATE.start_main_~#t2026~0.base_12|) 0) (not (= 0 |v_ULTIMATE.start_main_~#t2026~0.base_12|)) (= 0 |v_ULTIMATE.start_main_~#t2026~0.offset_11|) (= (store |v_#valid_35| |v_ULTIMATE.start_main_~#t2026~0.base_12| 1) |v_#valid_34|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t2026~0.base_12|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t2026~0.base=|v_ULTIMATE.start_main_~#t2026~0.base_12|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_6|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t2026~0.offset=|v_ULTIMATE.start_main_~#t2026~0.offset_11|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2026~0.base, ULTIMATE.start_main_#t~nondet21, #valid, #memory_int, ULTIMATE.start_main_~#t2026~0.offset, #length] because there is no mapped edge [2019-12-07 18:55:31,655 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] P0ENTRY-->L4-3: Formula: (and (= v_~z$w_buff0_used~0_226 v_~z$w_buff1_used~0_114) (= v_P0Thread1of1ForFork0_~arg.base_20 |v_P0Thread1of1ForFork0_#in~arg.base_22|) (= 2 v_~z$w_buff0~0_55) (= v_~z$w_buff0~0_56 v_~z$w_buff1~0_53) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_24 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_20|) (= (ite (not (and (not (= 0 (mod v_~z$w_buff0_used~0_225 256))) (not (= 0 (mod v_~z$w_buff1_used~0_114 256))))) 1 0) |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_20|) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_24 0)) (= v_P0Thread1of1ForFork0_~arg.offset_20 |v_P0Thread1of1ForFork0_#in~arg.offset_22|) (= v_~z$w_buff0_used~0_225 1)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_226, ~z$w_buff0~0=v_~z$w_buff0~0_56, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_22|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_225, ~z$w_buff0~0=v_~z$w_buff0~0_55, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_24, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_114, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_22|, ~z$w_buff1~0=v_~z$w_buff1~0_53, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_20, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_20|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_20} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 18:55:31,655 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L807-1-->L809: Formula: (and (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t2027~0.base_9|) (not (= 0 |v_ULTIMATE.start_main_~#t2027~0.base_9|)) (= |v_#memory_int_9| (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2027~0.base_9| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2027~0.base_9|) |v_ULTIMATE.start_main_~#t2027~0.offset_8| 2))) (= (store |v_#length_14| |v_ULTIMATE.start_main_~#t2027~0.base_9| 4) |v_#length_13|) (= 0 (select |v_#valid_28| |v_ULTIMATE.start_main_~#t2027~0.base_9|)) (= 0 |v_ULTIMATE.start_main_~#t2027~0.offset_8|) (= (store |v_#valid_28| |v_ULTIMATE.start_main_~#t2027~0.base_9| 1) |v_#valid_27|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_28|, #memory_int=|v_#memory_int_10|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_27|, #memory_int=|v_#memory_int_9|, #length=|v_#length_13|, ULTIMATE.start_main_~#t2027~0.base=|v_ULTIMATE.start_main_~#t2027~0.base_9|, ULTIMATE.start_main_~#t2027~0.offset=|v_ULTIMATE.start_main_~#t2027~0.offset_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t2027~0.base, ULTIMATE.start_main_~#t2027~0.offset] because there is no mapped edge [2019-12-07 18:55:31,656 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L743-->L743-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-1179045677 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In-1179045677 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P0Thread1of1ForFork0_#t~ite5_Out-1179045677|)) (and (or .cse1 .cse0) (= ~z$w_buff0_used~0_In-1179045677 |P0Thread1of1ForFork0_#t~ite5_Out-1179045677|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1179045677, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1179045677} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-1179045677|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1179045677, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1179045677} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 18:55:31,656 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L744-->L744-2: Formula: (let ((.cse3 (= (mod ~z$r_buff1_thd1~0_In-928969378 256) 0)) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-928969378 256))) (.cse0 (= (mod ~z$r_buff0_thd1~0_In-928969378 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-928969378 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork0_#t~ite6_Out-928969378|)) (and (or .cse3 .cse2) (= ~z$w_buff1_used~0_In-928969378 |P0Thread1of1ForFork0_#t~ite6_Out-928969378|) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-928969378, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-928969378, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-928969378, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-928969378} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out-928969378|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-928969378, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-928969378, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-928969378, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-928969378} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 18:55:31,657 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L745-->L746: Formula: (let ((.cse0 (= ~z$r_buff0_thd1~0_In968733521 ~z$r_buff0_thd1~0_Out968733521)) (.cse2 (= (mod ~z$r_buff0_thd1~0_In968733521 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In968733521 256) 0))) (or (and .cse0 .cse1) (and .cse0 .cse2) (and (= 0 ~z$r_buff0_thd1~0_Out968733521) (not .cse2) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In968733521, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In968733521} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In968733521, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out968733521|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out968733521} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 18:55:31,657 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L746-->L746-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In-1263679357 256))) (.cse1 (= (mod ~z$r_buff1_thd1~0_In-1263679357 256) 0)) (.cse3 (= (mod ~z$r_buff0_thd1~0_In-1263679357 256) 0)) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-1263679357 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite8_Out-1263679357| 0)) (and (or .cse0 .cse1) (or .cse3 .cse2) (= |P0Thread1of1ForFork0_#t~ite8_Out-1263679357| ~z$r_buff1_thd1~0_In-1263679357)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1263679357, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1263679357, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1263679357, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1263679357} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1263679357, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-1263679357|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1263679357, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1263679357, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1263679357} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 18:55:31,657 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L746-2-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_44 1) v_~__unbuffered_cnt~0_43) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_63 |v_P0Thread1of1ForFork0_#t~ite8_26|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_44} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_25|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_63, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_43} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 18:55:31,657 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L762-2-->L762-5: Formula: (let ((.cse0 (= |P1Thread1of1ForFork1_#t~ite10_Out1290905860| |P1Thread1of1ForFork1_#t~ite9_Out1290905860|)) (.cse1 (= (mod ~z$r_buff1_thd2~0_In1290905860 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In1290905860 256) 0))) (or (and .cse0 (not .cse1) (not .cse2) (= ~z$w_buff1~0_In1290905860 |P1Thread1of1ForFork1_#t~ite9_Out1290905860|)) (and (= ~z~0_In1290905860 |P1Thread1of1ForFork1_#t~ite9_Out1290905860|) .cse0 (or .cse1 .cse2)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1290905860, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1290905860, ~z$w_buff1~0=~z$w_buff1~0_In1290905860, ~z~0=~z~0_In1290905860} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out1290905860|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1290905860, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1290905860, P1Thread1of1ForFork1_#t~ite10=|P1Thread1of1ForFork1_#t~ite10_Out1290905860|, ~z$w_buff1~0=~z$w_buff1~0_In1290905860, ~z~0=~z~0_In1290905860} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10] because there is no mapped edge [2019-12-07 18:55:31,658 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L782-2-->L782-4: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd3~0_In-2039380594 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-2039380594 256)))) (or (and (or .cse0 .cse1) (= ~z~0_In-2039380594 |P2Thread1of1ForFork2_#t~ite15_Out-2039380594|)) (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In-2039380594 |P2Thread1of1ForFork2_#t~ite15_Out-2039380594|)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-2039380594, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2039380594, ~z$w_buff1~0=~z$w_buff1~0_In-2039380594, ~z~0=~z~0_In-2039380594} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-2039380594|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-2039380594, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2039380594, ~z$w_buff1~0=~z$w_buff1~0_In-2039380594, ~z~0=~z~0_In-2039380594} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 18:55:31,658 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L782-4-->L783: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~z~0_20) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, ~z~0=v_~z~0_20, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_11|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~z~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 18:55:31,658 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [774] [774] L783-->L783-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-612522564 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-612522564 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite17_Out-612522564| 0) (not .cse0) (not .cse1)) (and (= |P2Thread1of1ForFork2_#t~ite17_Out-612522564| ~z$w_buff0_used~0_In-612522564) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-612522564, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-612522564} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-612522564, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-612522564, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out-612522564|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 18:55:31,658 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L784-->L784-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd3~0_In-1921554792 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-1921554792 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-1921554792 256))) (.cse1 (= (mod ~z$r_buff1_thd3~0_In-1921554792 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite18_Out-1921554792|)) (and (= ~z$w_buff1_used~0_In-1921554792 |P2Thread1of1ForFork2_#t~ite18_Out-1921554792|) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1921554792, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1921554792, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1921554792, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1921554792} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1921554792, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1921554792, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1921554792, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1921554792, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-1921554792|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 18:55:31,658 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L785-->L785-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd3~0_In-1500518232 256) 0)) (.cse0 (= (mod ~z$w_buff0_used~0_In-1500518232 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite19_Out-1500518232| 0) (not .cse0) (not .cse1)) (and (= ~z$r_buff0_thd3~0_In-1500518232 |P2Thread1of1ForFork2_#t~ite19_Out-1500518232|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1500518232, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1500518232} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1500518232, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1500518232, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-1500518232|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 18:55:31,659 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L786-->L786-2: Formula: (let ((.cse3 (= 0 (mod ~z$w_buff1_used~0_In-1189064342 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In-1189064342 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1189064342 256))) (.cse1 (= (mod ~z$r_buff0_thd3~0_In-1189064342 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork2_#t~ite20_Out-1189064342| 0)) (and (or .cse3 .cse2) (= |P2Thread1of1ForFork2_#t~ite20_Out-1189064342| ~z$r_buff1_thd3~0_In-1189064342) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1189064342, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1189064342, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1189064342, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1189064342} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1189064342, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-1189064342|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1189064342, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1189064342, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1189064342} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 18:55:31,659 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L786-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_54 (+ v_~__unbuffered_cnt~0_55 1)) (= |v_P2Thread1of1ForFork2_#t~ite20_30| v_~z$r_buff1_thd3~0_67)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_30|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_29|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_67, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 18:55:31,659 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L763-->L763-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In847495186 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In847495186 256)))) (or (and (= |P1Thread1of1ForFork1_#t~ite11_Out847495186| 0) (not .cse0) (not .cse1)) (and (= |P1Thread1of1ForFork1_#t~ite11_Out847495186| ~z$w_buff0_used~0_In847495186) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In847495186, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In847495186} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In847495186, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out847495186|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In847495186} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 18:55:31,659 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L764-->L764-2: Formula: (let ((.cse3 (= (mod ~z$r_buff1_thd2~0_In-516925516 256) 0)) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-516925516 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-516925516 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In-516925516 256) 0))) (or (and (= ~z$w_buff1_used~0_In-516925516 |P1Thread1of1ForFork1_#t~ite12_Out-516925516|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out-516925516|) (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-516925516, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-516925516, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-516925516, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-516925516} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-516925516, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-516925516, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-516925516, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-516925516|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-516925516} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 18:55:31,659 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L765-->L765-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1242086709 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-1242086709 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite13_Out-1242086709|) (not .cse0) (not .cse1)) (and (= ~z$r_buff0_thd2~0_In-1242086709 |P1Thread1of1ForFork1_#t~ite13_Out-1242086709|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1242086709, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1242086709} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1242086709, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-1242086709|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1242086709} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 18:55:31,660 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L766-->L766-2: Formula: (let ((.cse3 (= 0 (mod ~z$w_buff0_used~0_In875920522 256))) (.cse2 (= (mod ~z$r_buff0_thd2~0_In875920522 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd2~0_In875920522 256) 0)) (.cse0 (= (mod ~z$w_buff1_used~0_In875920522 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork1_#t~ite14_Out875920522|)) (and (or .cse3 .cse2) (= |P1Thread1of1ForFork1_#t~ite14_Out875920522| ~z$r_buff1_thd2~0_In875920522) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In875920522, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In875920522, ~z$w_buff1_used~0=~z$w_buff1_used~0_In875920522, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In875920522} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In875920522, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In875920522, ~z$w_buff1_used~0=~z$w_buff1_used~0_In875920522, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out875920522|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In875920522} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 18:55:31,660 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L766-2-->P1EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_61 1) v_~__unbuffered_cnt~0_60) (= |v_P1Thread1of1ForFork1_#t~ite14_30| v_~z$r_buff1_thd2~0_84) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_61, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_30|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_84, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_60, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_29|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 18:55:31,660 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L809-1-->L815: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (= v_~main$tmp_guard0~0_8 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_18) 1 0) 0) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_18} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_7|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_18, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:55:31,660 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L815-2-->L815-5: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite25_Out-1778705683| |ULTIMATE.start_main_#t~ite24_Out-1778705683|)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-1778705683 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In-1778705683 256) 0))) (or (and .cse0 (= ~z~0_In-1778705683 |ULTIMATE.start_main_#t~ite24_Out-1778705683|) (or .cse1 .cse2)) (and .cse0 (not .cse1) (not .cse2) (= ~z$w_buff1~0_In-1778705683 |ULTIMATE.start_main_#t~ite24_Out-1778705683|)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1778705683, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1778705683, ~z$w_buff1~0=~z$w_buff1~0_In-1778705683, ~z~0=~z~0_In-1778705683} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1778705683, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-1778705683|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1778705683, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-1778705683|, ~z$w_buff1~0=~z$w_buff1~0_In-1778705683, ~z~0=~z~0_In-1778705683} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 18:55:31,660 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [768] [768] L816-->L816-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In-51037365 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-51037365 256)))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite26_Out-51037365|)) (and (= |ULTIMATE.start_main_#t~ite26_Out-51037365| ~z$w_buff0_used~0_In-51037365) (or .cse1 .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-51037365, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-51037365} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-51037365, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-51037365, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-51037365|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 18:55:31,661 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L817-->L817-2: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In-1957311214 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-1957311214 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-1957311214 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd0~0_In-1957311214 256)))) (or (and (= 0 |ULTIMATE.start_main_#t~ite27_Out-1957311214|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$w_buff1_used~0_In-1957311214 |ULTIMATE.start_main_#t~ite27_Out-1957311214|) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1957311214, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1957311214, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1957311214, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1957311214} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1957311214, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1957311214, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1957311214, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1957311214, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-1957311214|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 18:55:31,661 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L818-->L818-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In1162972327 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd0~0_In1162972327 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite28_Out1162972327|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite28_Out1162972327| ~z$r_buff0_thd0~0_In1162972327)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1162972327, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1162972327} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1162972327, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out1162972327|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1162972327} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 18:55:31,661 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L819-->L819-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In-1867632557 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1867632557 256))) (.cse2 (= (mod ~z$r_buff0_thd0~0_In-1867632557 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In-1867632557 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite29_Out-1867632557| ~z$r_buff1_thd0~0_In-1867632557) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |ULTIMATE.start_main_#t~ite29_Out-1867632557| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1867632557, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1867632557, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1867632557, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1867632557} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1867632557, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-1867632557|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1867632557, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1867632557, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1867632557} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 18:55:31,664 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L831-->L832: Formula: (and (= v_~z$r_buff0_thd0~0_103 v_~z$r_buff0_thd0~0_102) (not (= (mod v_~weak$$choice2~0_23 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_103, ~weak$$choice2~0=v_~weak$$choice2~0_23} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_102, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_6|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_10|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_6|, ~weak$$choice2~0=v_~weak$$choice2~0_23} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 18:55:31,664 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L834-->L837-1: Formula: (and (= v_~z$mem_tmp~0_11 v_~z~0_133) (= (mod v_~main$tmp_guard1~0_9 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (not (= 0 (mod v_~z$flush_delayed~0_21 256))) (= 0 v_~z$flush_delayed~0_20)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_11, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_9, ~z$flush_delayed~0=v_~z$flush_delayed~0_21} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_11, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_18|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_9, ~z$flush_delayed~0=v_~z$flush_delayed~0_20, ~z~0=v_~z~0_133, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:55:31,664 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L837-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:55:31,722 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_ceec2073-65a5-4ec4-98cb-5e6b17b2e955/bin/uautomizer/witness.graphml [2019-12-07 18:55:31,723 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:55:31,724 INFO L168 Benchmark]: Toolchain (without parser) took 72524.42 ms. Allocated memory was 1.0 GB in the beginning and 6.9 GB in the end (delta: 5.9 GB). Free memory was 937.1 MB in the beginning and 2.5 GB in the end (delta: -1.5 GB). Peak memory consumption was 4.4 GB. Max. memory is 11.5 GB. [2019-12-07 18:55:31,724 INFO L168 Benchmark]: CDTParser took 0.20 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:55:31,724 INFO L168 Benchmark]: CACSL2BoogieTranslator took 398.04 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 112.7 MB). Free memory was 937.1 MB in the beginning and 1.1 GB in the end (delta: -143.4 MB). Peak memory consumption was 18.2 MB. Max. memory is 11.5 GB. [2019-12-07 18:55:31,724 INFO L168 Benchmark]: Boogie Procedure Inliner took 40.67 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:55:31,725 INFO L168 Benchmark]: Boogie Preprocessor took 26.89 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:55:31,725 INFO L168 Benchmark]: RCFGBuilder took 409.42 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 56.3 MB). Peak memory consumption was 56.3 MB. Max. memory is 11.5 GB. [2019-12-07 18:55:31,725 INFO L168 Benchmark]: TraceAbstraction took 71575.79 ms. Allocated memory was 1.1 GB in the beginning and 6.9 GB in the end (delta: 5.8 GB). Free memory was 1.0 GB in the beginning and 2.5 GB in the end (delta: -1.5 GB). Peak memory consumption was 4.3 GB. Max. memory is 11.5 GB. [2019-12-07 18:55:31,725 INFO L168 Benchmark]: Witness Printer took 70.57 ms. Allocated memory is still 6.9 GB. Free memory was 2.5 GB in the beginning and 2.5 GB in the end (delta: 54.7 MB). Peak memory consumption was 54.7 MB. Max. memory is 11.5 GB. [2019-12-07 18:55:31,727 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 398.04 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 112.7 MB). Free memory was 937.1 MB in the beginning and 1.1 GB in the end (delta: -143.4 MB). Peak memory consumption was 18.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 40.67 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.89 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 409.42 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 56.3 MB). Peak memory consumption was 56.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 71575.79 ms. Allocated memory was 1.1 GB in the beginning and 6.9 GB in the end (delta: 5.8 GB). Free memory was 1.0 GB in the beginning and 2.5 GB in the end (delta: -1.5 GB). Peak memory consumption was 4.3 GB. Max. memory is 11.5 GB. * Witness Printer took 70.57 ms. Allocated memory is still 6.9 GB. Free memory was 2.5 GB in the beginning and 2.5 GB in the end (delta: 54.7 MB). Peak memory consumption was 54.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.0s, 174 ProgramPointsBefore, 93 ProgramPointsAfterwards, 211 TransitionsBefore, 104 TransitionsAfterwards, 17114 CoEnabledTransitionPairs, 8 FixpointIterations, 31 TrivialSequentialCompositions, 44 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 37 ConcurrentYvCompositions, 30 ChoiceCompositions, 6114 VarBasedMoverChecksPositive, 254 VarBasedMoverChecksNegative, 80 SemBasedMoverChecksPositive, 255 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.9s, 0 MoverChecksTotal, 86146 CheckedPairsTotal, 112 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L805] FCALL, FORK 0 pthread_create(&t2025, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L732] 1 z$r_buff1_thd0 = z$r_buff0_thd0 [L733] 1 z$r_buff1_thd1 = z$r_buff0_thd1 [L734] 1 z$r_buff1_thd2 = z$r_buff0_thd2 [L735] 1 z$r_buff1_thd3 = z$r_buff0_thd3 [L736] 1 z$r_buff0_thd1 = (_Bool)1 [L739] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L742] EXPR 1 z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L807] FCALL, FORK 0 pthread_create(&t2026, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L742] 1 z = z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) [L743] 1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used [L744] 1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used [L809] FCALL, FORK 0 pthread_create(&t2027, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L756] 2 x = 2 [L759] 2 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L762] EXPR 2 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L776] 3 __unbuffered_p2_EAX = y [L779] 3 z = 1 VAL [__unbuffered_cnt=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z)=2, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=2] [L782] 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z)=2, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=2] [L783] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L784] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L785] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L762] 2 z = z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) [L763] 2 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used [L764] 2 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used [L765] 2 z$r_buff0_thd2 = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 [L815] EXPR 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L815] 0 z = z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) [L816] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L817] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L818] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L819] 0 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L822] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L823] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L824] 0 z$flush_delayed = weak$$choice2 [L825] 0 z$mem_tmp = z VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L826] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L826] 0 z = !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) [L827] EXPR 0 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L827] 0 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) [L828] EXPR 0 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L828] 0 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) [L829] EXPR 0 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L829] 0 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) [L830] EXPR 0 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L830] 0 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L832] EXPR 0 weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L832] 0 z$r_buff1_thd0 = weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L833] 0 main$tmp_guard1 = !(x == 2 && z == 2 && __unbuffered_p2_EAX == 1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 165 locations, 2 error locations. Result: UNSAFE, OverallTime: 71.4s, OverallIterations: 27, TraceHistogramMax: 1, AutomataDifference: 15.1s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 4810 SDtfs, 4168 SDslu, 9878 SDs, 0 SdLazy, 6582 SolverSat, 262 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 273 GetRequests, 61 SyntacticMatches, 34 SemanticMatches, 178 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 496 ImplicationChecksByTransitivity, 1.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=188328occurred in iteration=4, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 38.8s AutomataMinimizationTime, 26 MinimizatonAttempts, 156165 StatesRemovedByMinimization, 22 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.1s InterpolantComputationTime, 1238 NumberOfCodeBlocks, 1238 NumberOfCodeBlocksAsserted, 27 NumberOfCheckSat, 1144 ConstructedInterpolants, 0 QuantifiedInterpolants, 210165 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 26 InterpolantComputations, 26 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...