./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe011_power.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_bdae239a-3fdf-4a6e-8196-337d13ba2380/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_bdae239a-3fdf-4a6e-8196-337d13ba2380/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_bdae239a-3fdf-4a6e-8196-337d13ba2380/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_bdae239a-3fdf-4a6e-8196-337d13ba2380/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe011_power.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_bdae239a-3fdf-4a6e-8196-337d13ba2380/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_bdae239a-3fdf-4a6e-8196-337d13ba2380/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2e968c5f2a92cb11b369bb4f63bfcc230f6422c8 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 17:16:15,764 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 17:16:15,765 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 17:16:15,774 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 17:16:15,774 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 17:16:15,774 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 17:16:15,775 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 17:16:15,777 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 17:16:15,779 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 17:16:15,779 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 17:16:15,780 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 17:16:15,781 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 17:16:15,781 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 17:16:15,782 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 17:16:15,782 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 17:16:15,783 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 17:16:15,784 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 17:16:15,785 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 17:16:15,786 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 17:16:15,787 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 17:16:15,789 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 17:16:15,789 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 17:16:15,790 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 17:16:15,790 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 17:16:15,792 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 17:16:15,792 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 17:16:15,792 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 17:16:15,793 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 17:16:15,793 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 17:16:15,793 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 17:16:15,794 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 17:16:15,794 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 17:16:15,795 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 17:16:15,795 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 17:16:15,796 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 17:16:15,796 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 17:16:15,797 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 17:16:15,797 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 17:16:15,797 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 17:16:15,798 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 17:16:15,798 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 17:16:15,799 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_bdae239a-3fdf-4a6e-8196-337d13ba2380/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 17:16:15,811 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 17:16:15,811 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 17:16:15,812 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 17:16:15,813 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 17:16:15,813 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 17:16:15,813 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 17:16:15,813 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 17:16:15,813 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 17:16:15,814 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 17:16:15,814 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 17:16:15,814 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 17:16:15,814 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 17:16:15,814 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 17:16:15,815 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 17:16:15,815 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 17:16:15,815 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 17:16:15,815 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 17:16:15,815 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 17:16:15,815 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 17:16:15,816 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 17:16:15,816 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 17:16:15,816 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:16:15,816 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 17:16:15,816 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 17:16:15,817 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 17:16:15,817 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 17:16:15,817 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 17:16:15,817 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 17:16:15,817 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 17:16:15,817 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_bdae239a-3fdf-4a6e-8196-337d13ba2380/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2e968c5f2a92cb11b369bb4f63bfcc230f6422c8 [2019-12-07 17:16:15,928 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 17:16:15,937 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 17:16:15,939 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 17:16:15,940 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 17:16:15,941 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 17:16:15,941 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_bdae239a-3fdf-4a6e-8196-337d13ba2380/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe011_power.opt.i [2019-12-07 17:16:15,980 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_bdae239a-3fdf-4a6e-8196-337d13ba2380/bin/uautomizer/data/53ac75dc3/5d583d5808b24d5f8b34bf344d4d654b/FLAG32127060a [2019-12-07 17:16:16,433 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 17:16:16,433 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_bdae239a-3fdf-4a6e-8196-337d13ba2380/sv-benchmarks/c/pthread-wmm/safe011_power.opt.i [2019-12-07 17:16:16,443 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_bdae239a-3fdf-4a6e-8196-337d13ba2380/bin/uautomizer/data/53ac75dc3/5d583d5808b24d5f8b34bf344d4d654b/FLAG32127060a [2019-12-07 17:16:16,452 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_bdae239a-3fdf-4a6e-8196-337d13ba2380/bin/uautomizer/data/53ac75dc3/5d583d5808b24d5f8b34bf344d4d654b [2019-12-07 17:16:16,454 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 17:16:16,455 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 17:16:16,455 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 17:16:16,455 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 17:16:16,458 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 17:16:16,458 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:16:16" (1/1) ... [2019-12-07 17:16:16,460 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@551fb3cf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:16:16, skipping insertion in model container [2019-12-07 17:16:16,460 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:16:16" (1/1) ... [2019-12-07 17:16:16,465 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 17:16:16,495 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 17:16:16,759 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:16:16,767 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 17:16:16,812 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:16:16,858 INFO L208 MainTranslator]: Completed translation [2019-12-07 17:16:16,858 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:16:16 WrapperNode [2019-12-07 17:16:16,858 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 17:16:16,859 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 17:16:16,859 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 17:16:16,859 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 17:16:16,865 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:16:16" (1/1) ... [2019-12-07 17:16:16,879 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:16:16" (1/1) ... [2019-12-07 17:16:16,901 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 17:16:16,901 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 17:16:16,901 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 17:16:16,901 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 17:16:16,908 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:16:16" (1/1) ... [2019-12-07 17:16:16,908 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:16:16" (1/1) ... [2019-12-07 17:16:16,912 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:16:16" (1/1) ... [2019-12-07 17:16:16,912 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:16:16" (1/1) ... [2019-12-07 17:16:16,919 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:16:16" (1/1) ... [2019-12-07 17:16:16,922 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:16:16" (1/1) ... [2019-12-07 17:16:16,924 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:16:16" (1/1) ... [2019-12-07 17:16:16,928 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 17:16:16,929 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 17:16:16,929 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 17:16:16,929 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 17:16:16,929 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:16:16" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bdae239a-3fdf-4a6e-8196-337d13ba2380/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:16:16,970 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 17:16:16,970 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 17:16:16,970 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 17:16:16,970 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 17:16:16,970 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 17:16:16,970 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 17:16:16,970 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 17:16:16,970 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 17:16:16,970 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 17:16:16,971 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 17:16:16,971 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 17:16:16,971 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 17:16:16,971 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 17:16:16,972 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 17:16:17,329 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 17:16:17,330 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 17:16:17,330 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:16:17 BoogieIcfgContainer [2019-12-07 17:16:17,331 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 17:16:17,331 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 17:16:17,331 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 17:16:17,334 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 17:16:17,334 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 05:16:16" (1/3) ... [2019-12-07 17:16:17,335 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@bb46c0d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:16:17, skipping insertion in model container [2019-12-07 17:16:17,335 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:16:16" (2/3) ... [2019-12-07 17:16:17,335 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@bb46c0d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:16:17, skipping insertion in model container [2019-12-07 17:16:17,335 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:16:17" (3/3) ... [2019-12-07 17:16:17,337 INFO L109 eAbstractionObserver]: Analyzing ICFG safe011_power.opt.i [2019-12-07 17:16:17,343 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 17:16:17,343 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 17:16:17,348 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 17:16:17,349 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 17:16:17,373 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,373 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,373 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,373 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,373 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,373 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,373 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,374 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,374 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,374 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,374 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,374 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,374 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,374 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,374 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,374 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,375 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,375 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,375 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,375 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,375 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,375 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,375 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,375 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,375 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,376 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,376 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,376 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,376 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,376 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,377 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,377 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,377 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,377 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,377 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,377 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,377 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,377 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,377 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,378 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,378 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,378 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,378 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,378 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,378 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,378 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,378 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,379 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,379 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,379 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,379 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,379 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,379 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,379 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,379 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,379 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,380 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,380 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,380 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,380 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,380 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,380 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,380 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,380 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,381 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,381 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,383 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,383 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,383 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,383 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,383 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,383 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,383 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,383 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,383 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,384 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,384 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,384 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:16:17,394 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 17:16:17,407 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 17:16:17,407 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 17:16:17,407 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 17:16:17,407 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 17:16:17,407 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 17:16:17,407 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 17:16:17,407 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 17:16:17,407 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 17:16:17,418 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 174 places, 211 transitions [2019-12-07 17:16:17,420 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 174 places, 211 transitions [2019-12-07 17:16:17,473 INFO L134 PetriNetUnfolder]: 47/208 cut-off events. [2019-12-07 17:16:17,474 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 17:16:17,484 INFO L76 FinitePrefix]: Finished finitePrefix Result has 218 conditions, 208 events. 47/208 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 572 event pairs. 9/168 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 17:16:17,498 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 174 places, 211 transitions [2019-12-07 17:16:17,529 INFO L134 PetriNetUnfolder]: 47/208 cut-off events. [2019-12-07 17:16:17,529 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 17:16:17,535 INFO L76 FinitePrefix]: Finished finitePrefix Result has 218 conditions, 208 events. 47/208 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 572 event pairs. 9/168 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 17:16:17,549 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 17074 [2019-12-07 17:16:17,550 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 17:16:20,351 WARN L192 SmtUtils]: Spent 139.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 85 [2019-12-07 17:16:20,435 INFO L206 etLargeBlockEncoding]: Checked pairs total: 87419 [2019-12-07 17:16:20,436 INFO L214 etLargeBlockEncoding]: Total number of compositions: 111 [2019-12-07 17:16:20,438 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 94 places, 106 transitions [2019-12-07 17:16:33,258 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 107408 states. [2019-12-07 17:16:33,259 INFO L276 IsEmpty]: Start isEmpty. Operand 107408 states. [2019-12-07 17:16:33,263 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-12-07 17:16:33,264 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:16:33,264 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-12-07 17:16:33,264 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:16:33,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:16:33,268 INFO L82 PathProgramCache]: Analyzing trace with hash 809706692, now seen corresponding path program 1 times [2019-12-07 17:16:33,273 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:16:33,273 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1077086271] [2019-12-07 17:16:33,274 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:16:33,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:16:33,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:16:33,413 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1077086271] [2019-12-07 17:16:33,414 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:16:33,414 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 17:16:33,415 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [609519884] [2019-12-07 17:16:33,417 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:16:33,418 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:16:33,426 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:16:33,427 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:16:33,428 INFO L87 Difference]: Start difference. First operand 107408 states. Second operand 3 states. [2019-12-07 17:16:34,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:16:34,334 INFO L93 Difference]: Finished difference Result 107108 states and 460900 transitions. [2019-12-07 17:16:34,335 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:16:34,336 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 5 [2019-12-07 17:16:34,336 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:16:34,847 INFO L225 Difference]: With dead ends: 107108 [2019-12-07 17:16:34,847 INFO L226 Difference]: Without dead ends: 104924 [2019-12-07 17:16:34,848 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:16:38,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104924 states. [2019-12-07 17:16:39,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104924 to 104924. [2019-12-07 17:16:39,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 104924 states. [2019-12-07 17:16:40,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104924 states to 104924 states and 451982 transitions. [2019-12-07 17:16:40,254 INFO L78 Accepts]: Start accepts. Automaton has 104924 states and 451982 transitions. Word has length 5 [2019-12-07 17:16:40,254 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:16:40,255 INFO L462 AbstractCegarLoop]: Abstraction has 104924 states and 451982 transitions. [2019-12-07 17:16:40,255 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:16:40,255 INFO L276 IsEmpty]: Start isEmpty. Operand 104924 states and 451982 transitions. [2019-12-07 17:16:40,257 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 17:16:40,257 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:16:40,257 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:16:40,258 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:16:40,258 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:16:40,258 INFO L82 PathProgramCache]: Analyzing trace with hash 1056800905, now seen corresponding path program 1 times [2019-12-07 17:16:40,258 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:16:40,258 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1238511550] [2019-12-07 17:16:40,258 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:16:40,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:16:40,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:16:40,313 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1238511550] [2019-12-07 17:16:40,314 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:16:40,314 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:16:40,314 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1687933233] [2019-12-07 17:16:40,315 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:16:40,315 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:16:40,315 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:16:40,315 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:16:40,315 INFO L87 Difference]: Start difference. First operand 104924 states and 451982 transitions. Second operand 4 states. [2019-12-07 17:16:43,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:16:43,018 INFO L93 Difference]: Finished difference Result 168606 states and 697152 transitions. [2019-12-07 17:16:43,019 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:16:43,019 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 17:16:43,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:16:43,452 INFO L225 Difference]: With dead ends: 168606 [2019-12-07 17:16:43,452 INFO L226 Difference]: Without dead ends: 168557 [2019-12-07 17:16:43,453 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:16:47,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 168557 states. [2019-12-07 17:16:49,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 168557 to 152629. [2019-12-07 17:16:49,773 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 152629 states. [2019-12-07 17:16:50,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152629 states to 152629 states and 638547 transitions. [2019-12-07 17:16:50,200 INFO L78 Accepts]: Start accepts. Automaton has 152629 states and 638547 transitions. Word has length 11 [2019-12-07 17:16:50,200 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:16:50,200 INFO L462 AbstractCegarLoop]: Abstraction has 152629 states and 638547 transitions. [2019-12-07 17:16:50,200 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:16:50,200 INFO L276 IsEmpty]: Start isEmpty. Operand 152629 states and 638547 transitions. [2019-12-07 17:16:50,205 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 17:16:50,205 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:16:50,205 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:16:50,205 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:16:50,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:16:50,206 INFO L82 PathProgramCache]: Analyzing trace with hash 933289536, now seen corresponding path program 1 times [2019-12-07 17:16:50,206 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:16:50,206 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [298899323] [2019-12-07 17:16:50,206 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:16:50,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:16:50,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:16:50,250 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [298899323] [2019-12-07 17:16:50,250 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:16:50,250 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:16:50,250 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [689881467] [2019-12-07 17:16:50,250 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:16:50,251 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:16:50,251 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:16:50,251 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:16:50,251 INFO L87 Difference]: Start difference. First operand 152629 states and 638547 transitions. Second operand 4 states. [2019-12-07 17:16:51,710 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:16:51,710 INFO L93 Difference]: Finished difference Result 217678 states and 889823 transitions. [2019-12-07 17:16:51,711 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:16:51,711 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 17:16:51,711 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:16:52,240 INFO L225 Difference]: With dead ends: 217678 [2019-12-07 17:16:52,240 INFO L226 Difference]: Without dead ends: 217615 [2019-12-07 17:16:52,241 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:16:59,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217615 states. [2019-12-07 17:17:01,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217615 to 183279. [2019-12-07 17:17:01,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 183279 states. [2019-12-07 17:17:02,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183279 states to 183279 states and 761454 transitions. [2019-12-07 17:17:02,388 INFO L78 Accepts]: Start accepts. Automaton has 183279 states and 761454 transitions. Word has length 13 [2019-12-07 17:17:02,389 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:02,389 INFO L462 AbstractCegarLoop]: Abstraction has 183279 states and 761454 transitions. [2019-12-07 17:17:02,389 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:17:02,389 INFO L276 IsEmpty]: Start isEmpty. Operand 183279 states and 761454 transitions. [2019-12-07 17:17:02,391 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 17:17:02,391 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:02,391 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:02,392 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:02,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:02,392 INFO L82 PathProgramCache]: Analyzing trace with hash -1797085387, now seen corresponding path program 1 times [2019-12-07 17:17:02,392 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:02,392 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1966913828] [2019-12-07 17:17:02,392 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:02,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:02,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:02,435 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1966913828] [2019-12-07 17:17:02,436 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:02,436 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:17:02,436 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [101605326] [2019-12-07 17:17:02,436 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:17:02,436 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:02,436 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:17:02,436 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:17:02,436 INFO L87 Difference]: Start difference. First operand 183279 states and 761454 transitions. Second operand 4 states. [2019-12-07 17:17:03,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:03,564 INFO L93 Difference]: Finished difference Result 228772 states and 941089 transitions. [2019-12-07 17:17:03,564 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:17:03,564 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 17:17:03,565 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:04,135 INFO L225 Difference]: With dead ends: 228772 [2019-12-07 17:17:04,136 INFO L226 Difference]: Without dead ends: 228772 [2019-12-07 17:17:04,136 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:17:09,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228772 states. [2019-12-07 17:17:14,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228772 to 193424. [2019-12-07 17:17:14,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 193424 states. [2019-12-07 17:17:15,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193424 states to 193424 states and 803706 transitions. [2019-12-07 17:17:15,309 INFO L78 Accepts]: Start accepts. Automaton has 193424 states and 803706 transitions. Word has length 13 [2019-12-07 17:17:15,309 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:15,309 INFO L462 AbstractCegarLoop]: Abstraction has 193424 states and 803706 transitions. [2019-12-07 17:17:15,309 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:17:15,309 INFO L276 IsEmpty]: Start isEmpty. Operand 193424 states and 803706 transitions. [2019-12-07 17:17:15,325 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 17:17:15,326 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:15,326 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:15,326 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:15,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:15,326 INFO L82 PathProgramCache]: Analyzing trace with hash 1117796869, now seen corresponding path program 1 times [2019-12-07 17:17:15,326 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:15,327 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [271346807] [2019-12-07 17:17:15,327 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:15,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:15,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:15,372 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [271346807] [2019-12-07 17:17:15,372 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:15,373 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:17:15,373 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2032747812] [2019-12-07 17:17:15,373 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:17:15,373 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:15,373 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:17:15,373 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:17:15,373 INFO L87 Difference]: Start difference. First operand 193424 states and 803706 transitions. Second operand 5 states. [2019-12-07 17:17:17,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:17,342 INFO L93 Difference]: Finished difference Result 284752 states and 1156454 transitions. [2019-12-07 17:17:17,343 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:17:17,343 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 17:17:17,343 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:18,043 INFO L225 Difference]: With dead ends: 284752 [2019-12-07 17:17:18,044 INFO L226 Difference]: Without dead ends: 284612 [2019-12-07 17:17:18,044 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:17:24,078 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284612 states. [2019-12-07 17:17:29,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284612 to 212401. [2019-12-07 17:17:29,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 212401 states. [2019-12-07 17:17:30,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212401 states to 212401 states and 878348 transitions. [2019-12-07 17:17:30,803 INFO L78 Accepts]: Start accepts. Automaton has 212401 states and 878348 transitions. Word has length 19 [2019-12-07 17:17:30,804 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:30,804 INFO L462 AbstractCegarLoop]: Abstraction has 212401 states and 878348 transitions. [2019-12-07 17:17:30,804 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:17:30,804 INFO L276 IsEmpty]: Start isEmpty. Operand 212401 states and 878348 transitions. [2019-12-07 17:17:30,816 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 17:17:30,817 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:30,817 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:30,817 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:30,817 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:30,817 INFO L82 PathProgramCache]: Analyzing trace with hash 658145402, now seen corresponding path program 1 times [2019-12-07 17:17:30,817 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:30,817 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [232943113] [2019-12-07 17:17:30,817 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:30,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:30,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:30,847 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [232943113] [2019-12-07 17:17:30,847 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:30,847 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:17:30,848 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2024892938] [2019-12-07 17:17:30,848 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:17:30,848 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:30,848 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:17:30,848 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:17:30,848 INFO L87 Difference]: Start difference. First operand 212401 states and 878348 transitions. Second operand 3 states. [2019-12-07 17:17:30,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:30,957 INFO L93 Difference]: Finished difference Result 37328 states and 121606 transitions. [2019-12-07 17:17:30,957 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:17:30,957 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2019-12-07 17:17:30,958 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:31,007 INFO L225 Difference]: With dead ends: 37328 [2019-12-07 17:17:31,007 INFO L226 Difference]: Without dead ends: 37328 [2019-12-07 17:17:31,008 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:17:31,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37328 states. [2019-12-07 17:17:31,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37328 to 37328. [2019-12-07 17:17:31,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37328 states. [2019-12-07 17:17:31,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37328 states to 37328 states and 121606 transitions. [2019-12-07 17:17:31,614 INFO L78 Accepts]: Start accepts. Automaton has 37328 states and 121606 transitions. Word has length 19 [2019-12-07 17:17:31,614 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:31,614 INFO L462 AbstractCegarLoop]: Abstraction has 37328 states and 121606 transitions. [2019-12-07 17:17:31,614 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:17:31,614 INFO L276 IsEmpty]: Start isEmpty. Operand 37328 states and 121606 transitions. [2019-12-07 17:17:31,620 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 17:17:31,620 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:31,620 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:31,620 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:31,620 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:31,620 INFO L82 PathProgramCache]: Analyzing trace with hash 7812214, now seen corresponding path program 1 times [2019-12-07 17:17:31,620 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:31,621 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [157969935] [2019-12-07 17:17:31,621 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:31,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:31,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:31,694 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [157969935] [2019-12-07 17:17:31,694 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:31,694 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:17:31,694 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [964451066] [2019-12-07 17:17:31,694 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:17:31,695 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:31,695 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:17:31,695 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:17:31,695 INFO L87 Difference]: Start difference. First operand 37328 states and 121606 transitions. Second operand 6 states. [2019-12-07 17:17:32,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:32,169 INFO L93 Difference]: Finished difference Result 52640 states and 167868 transitions. [2019-12-07 17:17:32,170 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:17:32,170 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2019-12-07 17:17:32,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:32,247 INFO L225 Difference]: With dead ends: 52640 [2019-12-07 17:17:32,247 INFO L226 Difference]: Without dead ends: 52640 [2019-12-07 17:17:32,247 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:17:32,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52640 states. [2019-12-07 17:17:32,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52640 to 41234. [2019-12-07 17:17:32,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41234 states. [2019-12-07 17:17:32,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41234 states to 41234 states and 133454 transitions. [2019-12-07 17:17:32,974 INFO L78 Accepts]: Start accepts. Automaton has 41234 states and 133454 transitions. Word has length 25 [2019-12-07 17:17:32,974 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:32,974 INFO L462 AbstractCegarLoop]: Abstraction has 41234 states and 133454 transitions. [2019-12-07 17:17:32,974 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:17:32,974 INFO L276 IsEmpty]: Start isEmpty. Operand 41234 states and 133454 transitions. [2019-12-07 17:17:32,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 17:17:32,980 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:32,980 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:32,981 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:32,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:32,981 INFO L82 PathProgramCache]: Analyzing trace with hash -782102681, now seen corresponding path program 1 times [2019-12-07 17:17:32,981 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:32,981 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1168095584] [2019-12-07 17:17:32,981 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:32,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:33,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:33,037 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1168095584] [2019-12-07 17:17:33,037 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:33,037 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:17:33,037 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1166383146] [2019-12-07 17:17:33,037 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:17:33,037 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:33,038 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:17:33,038 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:17:33,038 INFO L87 Difference]: Start difference. First operand 41234 states and 133454 transitions. Second operand 5 states. [2019-12-07 17:17:33,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:33,389 INFO L93 Difference]: Finished difference Result 55154 states and 175550 transitions. [2019-12-07 17:17:33,390 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 17:17:33,390 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 25 [2019-12-07 17:17:33,390 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:33,468 INFO L225 Difference]: With dead ends: 55154 [2019-12-07 17:17:33,468 INFO L226 Difference]: Without dead ends: 55154 [2019-12-07 17:17:33,469 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:17:33,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55154 states. [2019-12-07 17:17:34,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55154 to 43275. [2019-12-07 17:17:34,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43275 states. [2019-12-07 17:17:34,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43275 states to 43275 states and 139859 transitions. [2019-12-07 17:17:34,510 INFO L78 Accepts]: Start accepts. Automaton has 43275 states and 139859 transitions. Word has length 25 [2019-12-07 17:17:34,510 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:34,510 INFO L462 AbstractCegarLoop]: Abstraction has 43275 states and 139859 transitions. [2019-12-07 17:17:34,510 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:17:34,510 INFO L276 IsEmpty]: Start isEmpty. Operand 43275 states and 139859 transitions. [2019-12-07 17:17:34,522 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 17:17:34,522 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:34,522 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:34,522 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:34,522 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:34,522 INFO L82 PathProgramCache]: Analyzing trace with hash -310678356, now seen corresponding path program 1 times [2019-12-07 17:17:34,522 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:34,523 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1084543692] [2019-12-07 17:17:34,523 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:34,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:34,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:34,585 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1084543692] [2019-12-07 17:17:34,586 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:34,586 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:17:34,586 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [22024575] [2019-12-07 17:17:34,586 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:17:34,586 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:34,587 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:17:34,587 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:17:34,587 INFO L87 Difference]: Start difference. First operand 43275 states and 139859 transitions. Second operand 6 states. [2019-12-07 17:17:35,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:35,309 INFO L93 Difference]: Finished difference Result 54041 states and 172398 transitions. [2019-12-07 17:17:35,309 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 17:17:35,309 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 31 [2019-12-07 17:17:35,310 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:35,389 INFO L225 Difference]: With dead ends: 54041 [2019-12-07 17:17:35,389 INFO L226 Difference]: Without dead ends: 54028 [2019-12-07 17:17:35,390 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2019-12-07 17:17:35,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54028 states. [2019-12-07 17:17:36,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54028 to 39992. [2019-12-07 17:17:36,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39992 states. [2019-12-07 17:17:36,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39992 states to 39992 states and 129830 transitions. [2019-12-07 17:17:36,125 INFO L78 Accepts]: Start accepts. Automaton has 39992 states and 129830 transitions. Word has length 31 [2019-12-07 17:17:36,125 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:36,125 INFO L462 AbstractCegarLoop]: Abstraction has 39992 states and 129830 transitions. [2019-12-07 17:17:36,125 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:17:36,125 INFO L276 IsEmpty]: Start isEmpty. Operand 39992 states and 129830 transitions. [2019-12-07 17:17:36,148 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2019-12-07 17:17:36,148 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:36,148 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:36,148 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:36,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:36,149 INFO L82 PathProgramCache]: Analyzing trace with hash -1797088220, now seen corresponding path program 1 times [2019-12-07 17:17:36,149 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:36,149 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [525823173] [2019-12-07 17:17:36,149 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:36,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:36,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:36,178 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [525823173] [2019-12-07 17:17:36,178 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:36,178 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:17:36,178 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [36167775] [2019-12-07 17:17:36,178 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:17:36,179 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:36,179 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:17:36,179 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:17:36,179 INFO L87 Difference]: Start difference. First operand 39992 states and 129830 transitions. Second operand 3 states. [2019-12-07 17:17:36,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:36,327 INFO L93 Difference]: Finished difference Result 46835 states and 152675 transitions. [2019-12-07 17:17:36,327 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:17:36,327 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 39 [2019-12-07 17:17:36,328 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:36,392 INFO L225 Difference]: With dead ends: 46835 [2019-12-07 17:17:36,392 INFO L226 Difference]: Without dead ends: 46835 [2019-12-07 17:17:36,392 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:17:36,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46835 states. [2019-12-07 17:17:37,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46835 to 44393. [2019-12-07 17:17:37,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44393 states. [2019-12-07 17:17:37,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44393 states to 44393 states and 145223 transitions. [2019-12-07 17:17:37,391 INFO L78 Accepts]: Start accepts. Automaton has 44393 states and 145223 transitions. Word has length 39 [2019-12-07 17:17:37,391 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:37,391 INFO L462 AbstractCegarLoop]: Abstraction has 44393 states and 145223 transitions. [2019-12-07 17:17:37,392 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:17:37,392 INFO L276 IsEmpty]: Start isEmpty. Operand 44393 states and 145223 transitions. [2019-12-07 17:17:37,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2019-12-07 17:17:37,414 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:37,414 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:37,414 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:37,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:37,415 INFO L82 PathProgramCache]: Analyzing trace with hash -1663208923, now seen corresponding path program 1 times [2019-12-07 17:17:37,415 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:37,415 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [502154591] [2019-12-07 17:17:37,415 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:37,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:37,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:37,448 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [502154591] [2019-12-07 17:17:37,448 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:37,448 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:17:37,448 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1000679771] [2019-12-07 17:17:37,449 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:17:37,449 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:37,449 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:17:37,449 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:17:37,449 INFO L87 Difference]: Start difference. First operand 44393 states and 145223 transitions. Second operand 4 states. [2019-12-07 17:17:37,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:37,478 INFO L93 Difference]: Finished difference Result 7906 states and 21265 transitions. [2019-12-07 17:17:37,479 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 17:17:37,479 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 39 [2019-12-07 17:17:37,479 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:37,485 INFO L225 Difference]: With dead ends: 7906 [2019-12-07 17:17:37,485 INFO L226 Difference]: Without dead ends: 7906 [2019-12-07 17:17:37,485 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:17:37,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7906 states. [2019-12-07 17:17:37,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7906 to 7794. [2019-12-07 17:17:37,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7794 states. [2019-12-07 17:17:37,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7794 states to 7794 states and 20945 transitions. [2019-12-07 17:17:37,573 INFO L78 Accepts]: Start accepts. Automaton has 7794 states and 20945 transitions. Word has length 39 [2019-12-07 17:17:37,573 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:37,573 INFO L462 AbstractCegarLoop]: Abstraction has 7794 states and 20945 transitions. [2019-12-07 17:17:37,573 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:17:37,573 INFO L276 IsEmpty]: Start isEmpty. Operand 7794 states and 20945 transitions. [2019-12-07 17:17:37,578 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 17:17:37,578 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:37,578 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:37,578 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:37,578 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:37,578 INFO L82 PathProgramCache]: Analyzing trace with hash 995119447, now seen corresponding path program 1 times [2019-12-07 17:17:37,578 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:37,579 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [192343009] [2019-12-07 17:17:37,579 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:37,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:37,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:37,617 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [192343009] [2019-12-07 17:17:37,617 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:37,618 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:17:37,618 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703917002] [2019-12-07 17:17:37,618 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:17:37,618 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:37,618 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:17:37,619 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:17:37,619 INFO L87 Difference]: Start difference. First operand 7794 states and 20945 transitions. Second operand 5 states. [2019-12-07 17:17:37,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:37,644 INFO L93 Difference]: Finished difference Result 5050 states and 14454 transitions. [2019-12-07 17:17:37,644 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:17:37,644 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-12-07 17:17:37,644 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:37,649 INFO L225 Difference]: With dead ends: 5050 [2019-12-07 17:17:37,649 INFO L226 Difference]: Without dead ends: 5050 [2019-12-07 17:17:37,649 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:17:37,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5050 states. [2019-12-07 17:17:37,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5050 to 4686. [2019-12-07 17:17:37,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4686 states. [2019-12-07 17:17:37,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4686 states to 4686 states and 13470 transitions. [2019-12-07 17:17:37,709 INFO L78 Accepts]: Start accepts. Automaton has 4686 states and 13470 transitions. Word has length 51 [2019-12-07 17:17:37,709 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:37,709 INFO L462 AbstractCegarLoop]: Abstraction has 4686 states and 13470 transitions. [2019-12-07 17:17:37,709 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:17:37,709 INFO L276 IsEmpty]: Start isEmpty. Operand 4686 states and 13470 transitions. [2019-12-07 17:17:37,713 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 17:17:37,713 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:37,713 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:37,713 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:37,713 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:37,713 INFO L82 PathProgramCache]: Analyzing trace with hash -151073877, now seen corresponding path program 1 times [2019-12-07 17:17:37,713 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:37,713 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1371863366] [2019-12-07 17:17:37,714 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:37,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:37,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:37,753 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1371863366] [2019-12-07 17:17:37,754 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:37,754 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:17:37,754 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1606501753] [2019-12-07 17:17:37,754 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:17:37,754 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:37,754 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:17:37,754 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:17:37,755 INFO L87 Difference]: Start difference. First operand 4686 states and 13470 transitions. Second operand 3 states. [2019-12-07 17:17:37,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:37,789 INFO L93 Difference]: Finished difference Result 4690 states and 13463 transitions. [2019-12-07 17:17:37,789 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:17:37,789 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 17:17:37,790 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:37,794 INFO L225 Difference]: With dead ends: 4690 [2019-12-07 17:17:37,794 INFO L226 Difference]: Without dead ends: 4690 [2019-12-07 17:17:37,794 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:17:37,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4690 states. [2019-12-07 17:17:37,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4690 to 4682. [2019-12-07 17:17:37,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4682 states. [2019-12-07 17:17:37,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4682 states to 4682 states and 13455 transitions. [2019-12-07 17:17:37,854 INFO L78 Accepts]: Start accepts. Automaton has 4682 states and 13455 transitions. Word has length 65 [2019-12-07 17:17:37,854 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:37,854 INFO L462 AbstractCegarLoop]: Abstraction has 4682 states and 13455 transitions. [2019-12-07 17:17:37,854 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:17:37,854 INFO L276 IsEmpty]: Start isEmpty. Operand 4682 states and 13455 transitions. [2019-12-07 17:17:37,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 17:17:37,858 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:37,858 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:37,859 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:37,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:37,859 INFO L82 PathProgramCache]: Analyzing trace with hash -160756913, now seen corresponding path program 1 times [2019-12-07 17:17:37,859 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:37,859 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1641046324] [2019-12-07 17:17:37,859 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:37,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:37,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:37,932 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1641046324] [2019-12-07 17:17:37,932 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:37,932 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:17:37,932 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1491236002] [2019-12-07 17:17:37,933 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:17:37,933 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:37,933 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:17:37,933 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:17:37,933 INFO L87 Difference]: Start difference. First operand 4682 states and 13455 transitions. Second operand 5 states. [2019-12-07 17:17:38,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:38,135 INFO L93 Difference]: Finished difference Result 7436 states and 21084 transitions. [2019-12-07 17:17:38,135 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 17:17:38,135 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 65 [2019-12-07 17:17:38,135 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:38,141 INFO L225 Difference]: With dead ends: 7436 [2019-12-07 17:17:38,141 INFO L226 Difference]: Without dead ends: 7436 [2019-12-07 17:17:38,142 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:17:38,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7436 states. [2019-12-07 17:17:38,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7436 to 5995. [2019-12-07 17:17:38,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5995 states. [2019-12-07 17:17:38,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5995 states to 5995 states and 17174 transitions. [2019-12-07 17:17:38,225 INFO L78 Accepts]: Start accepts. Automaton has 5995 states and 17174 transitions. Word has length 65 [2019-12-07 17:17:38,225 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:38,226 INFO L462 AbstractCegarLoop]: Abstraction has 5995 states and 17174 transitions. [2019-12-07 17:17:38,226 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:17:38,226 INFO L276 IsEmpty]: Start isEmpty. Operand 5995 states and 17174 transitions. [2019-12-07 17:17:38,230 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 17:17:38,230 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:38,231 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:38,231 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:38,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:38,231 INFO L82 PathProgramCache]: Analyzing trace with hash 947021199, now seen corresponding path program 2 times [2019-12-07 17:17:38,231 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:38,231 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1891977154] [2019-12-07 17:17:38,231 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:38,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:38,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:38,283 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1891977154] [2019-12-07 17:17:38,283 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:38,284 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:17:38,284 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1181740359] [2019-12-07 17:17:38,284 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:17:38,284 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:38,284 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:17:38,284 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:17:38,284 INFO L87 Difference]: Start difference. First operand 5995 states and 17174 transitions. Second operand 6 states. [2019-12-07 17:17:38,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:38,594 INFO L93 Difference]: Finished difference Result 9730 states and 27765 transitions. [2019-12-07 17:17:38,595 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:17:38,595 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 65 [2019-12-07 17:17:38,595 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:38,603 INFO L225 Difference]: With dead ends: 9730 [2019-12-07 17:17:38,603 INFO L226 Difference]: Without dead ends: 9730 [2019-12-07 17:17:38,603 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:17:38,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9730 states. [2019-12-07 17:17:38,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9730 to 6771. [2019-12-07 17:17:38,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6771 states. [2019-12-07 17:17:38,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6771 states to 6771 states and 19440 transitions. [2019-12-07 17:17:38,705 INFO L78 Accepts]: Start accepts. Automaton has 6771 states and 19440 transitions. Word has length 65 [2019-12-07 17:17:38,705 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:38,705 INFO L462 AbstractCegarLoop]: Abstraction has 6771 states and 19440 transitions. [2019-12-07 17:17:38,705 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:17:38,705 INFO L276 IsEmpty]: Start isEmpty. Operand 6771 states and 19440 transitions. [2019-12-07 17:17:38,710 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 17:17:38,710 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:38,710 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:38,710 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:38,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:38,711 INFO L82 PathProgramCache]: Analyzing trace with hash 1073447055, now seen corresponding path program 3 times [2019-12-07 17:17:38,711 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:38,711 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [404985685] [2019-12-07 17:17:38,711 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:38,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:38,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:38,778 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [404985685] [2019-12-07 17:17:38,778 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:38,778 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 17:17:38,778 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1148176678] [2019-12-07 17:17:38,779 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:17:38,779 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:38,779 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:17:38,779 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:17:38,779 INFO L87 Difference]: Start difference. First operand 6771 states and 19440 transitions. Second operand 7 states. [2019-12-07 17:17:39,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:39,039 INFO L93 Difference]: Finished difference Result 9163 states and 25848 transitions. [2019-12-07 17:17:39,039 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:17:39,039 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 65 [2019-12-07 17:17:39,039 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:39,047 INFO L225 Difference]: With dead ends: 9163 [2019-12-07 17:17:39,047 INFO L226 Difference]: Without dead ends: 9163 [2019-12-07 17:17:39,047 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=64, Unknown=0, NotChecked=0, Total=90 [2019-12-07 17:17:39,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9163 states. [2019-12-07 17:17:39,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9163 to 7401. [2019-12-07 17:17:39,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7401 states. [2019-12-07 17:17:39,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7401 states to 7401 states and 21205 transitions. [2019-12-07 17:17:39,148 INFO L78 Accepts]: Start accepts. Automaton has 7401 states and 21205 transitions. Word has length 65 [2019-12-07 17:17:39,148 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:39,148 INFO L462 AbstractCegarLoop]: Abstraction has 7401 states and 21205 transitions. [2019-12-07 17:17:39,148 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:17:39,149 INFO L276 IsEmpty]: Start isEmpty. Operand 7401 states and 21205 transitions. [2019-12-07 17:17:39,154 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 17:17:39,154 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:39,154 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:39,154 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:39,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:39,154 INFO L82 PathProgramCache]: Analyzing trace with hash -539971339, now seen corresponding path program 4 times [2019-12-07 17:17:39,155 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:39,155 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [747259865] [2019-12-07 17:17:39,155 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:39,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:39,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:39,225 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [747259865] [2019-12-07 17:17:39,225 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:39,225 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 17:17:39,226 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [966161917] [2019-12-07 17:17:39,226 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:17:39,226 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:39,226 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:17:39,226 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:17:39,227 INFO L87 Difference]: Start difference. First operand 7401 states and 21205 transitions. Second operand 7 states. [2019-12-07 17:17:39,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:39,791 INFO L93 Difference]: Finished difference Result 10865 states and 30860 transitions. [2019-12-07 17:17:39,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 17:17:39,792 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 65 [2019-12-07 17:17:39,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:39,806 INFO L225 Difference]: With dead ends: 10865 [2019-12-07 17:17:39,807 INFO L226 Difference]: Without dead ends: 10865 [2019-12-07 17:17:39,807 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 7 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2019-12-07 17:17:39,847 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10865 states. [2019-12-07 17:17:39,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10865 to 7716. [2019-12-07 17:17:39,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7716 states. [2019-12-07 17:17:39,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7716 states to 7716 states and 22112 transitions. [2019-12-07 17:17:39,926 INFO L78 Accepts]: Start accepts. Automaton has 7716 states and 22112 transitions. Word has length 65 [2019-12-07 17:17:39,926 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:39,926 INFO L462 AbstractCegarLoop]: Abstraction has 7716 states and 22112 transitions. [2019-12-07 17:17:39,927 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:17:39,927 INFO L276 IsEmpty]: Start isEmpty. Operand 7716 states and 22112 transitions. [2019-12-07 17:17:39,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 17:17:39,932 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:39,932 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:39,933 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:39,933 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:39,933 INFO L82 PathProgramCache]: Analyzing trace with hash -1939973301, now seen corresponding path program 5 times [2019-12-07 17:17:39,933 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:39,933 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2033042919] [2019-12-07 17:17:39,933 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:39,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:39,998 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:39,998 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2033042919] [2019-12-07 17:17:39,998 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:39,998 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:17:39,998 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [406341119] [2019-12-07 17:17:39,999 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:17:39,999 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:39,999 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:17:39,999 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:17:39,999 INFO L87 Difference]: Start difference. First operand 7716 states and 22112 transitions. Second operand 6 states. [2019-12-07 17:17:40,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:40,604 INFO L93 Difference]: Finished difference Result 9836 states and 27636 transitions. [2019-12-07 17:17:40,605 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 17:17:40,605 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 65 [2019-12-07 17:17:40,605 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:40,613 INFO L225 Difference]: With dead ends: 9836 [2019-12-07 17:17:40,613 INFO L226 Difference]: Without dead ends: 9836 [2019-12-07 17:17:40,613 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2019-12-07 17:17:40,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9836 states. [2019-12-07 17:17:40,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9836 to 7757. [2019-12-07 17:17:40,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7757 states. [2019-12-07 17:17:40,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7757 states to 7757 states and 21980 transitions. [2019-12-07 17:17:40,721 INFO L78 Accepts]: Start accepts. Automaton has 7757 states and 21980 transitions. Word has length 65 [2019-12-07 17:17:40,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:40,721 INFO L462 AbstractCegarLoop]: Abstraction has 7757 states and 21980 transitions. [2019-12-07 17:17:40,721 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:17:40,721 INFO L276 IsEmpty]: Start isEmpty. Operand 7757 states and 21980 transitions. [2019-12-07 17:17:40,727 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 17:17:40,727 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:40,728 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:40,728 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:40,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:40,728 INFO L82 PathProgramCache]: Analyzing trace with hash 1530095929, now seen corresponding path program 6 times [2019-12-07 17:17:40,728 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:40,728 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [158241692] [2019-12-07 17:17:40,728 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:40,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:40,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:40,805 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [158241692] [2019-12-07 17:17:40,805 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:40,805 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:17:40,805 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [778730905] [2019-12-07 17:17:40,805 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:17:40,805 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:40,806 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:17:40,806 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:17:40,806 INFO L87 Difference]: Start difference. First operand 7757 states and 21980 transitions. Second operand 6 states. [2019-12-07 17:17:40,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:40,875 INFO L93 Difference]: Finished difference Result 15127 states and 43050 transitions. [2019-12-07 17:17:40,875 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:17:40,875 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 65 [2019-12-07 17:17:40,875 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:40,882 INFO L225 Difference]: With dead ends: 15127 [2019-12-07 17:17:40,882 INFO L226 Difference]: Without dead ends: 7725 [2019-12-07 17:17:40,882 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 17:17:40,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7725 states. [2019-12-07 17:17:40,957 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7725 to 6575. [2019-12-07 17:17:40,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6575 states. [2019-12-07 17:17:40,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6575 states to 6575 states and 18596 transitions. [2019-12-07 17:17:40,965 INFO L78 Accepts]: Start accepts. Automaton has 6575 states and 18596 transitions. Word has length 65 [2019-12-07 17:17:40,965 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:40,965 INFO L462 AbstractCegarLoop]: Abstraction has 6575 states and 18596 transitions. [2019-12-07 17:17:40,965 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:17:40,965 INFO L276 IsEmpty]: Start isEmpty. Operand 6575 states and 18596 transitions. [2019-12-07 17:17:40,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 17:17:40,970 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:40,970 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:40,970 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:40,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:40,970 INFO L82 PathProgramCache]: Analyzing trace with hash 1337639271, now seen corresponding path program 7 times [2019-12-07 17:17:40,970 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:40,970 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1722204578] [2019-12-07 17:17:40,971 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:40,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:41,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:41,036 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1722204578] [2019-12-07 17:17:41,036 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:41,036 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 17:17:41,036 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [968860815] [2019-12-07 17:17:41,036 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 17:17:41,036 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:41,037 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 17:17:41,037 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2019-12-07 17:17:41,037 INFO L87 Difference]: Start difference. First operand 6575 states and 18596 transitions. Second operand 8 states. [2019-12-07 17:17:41,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:41,660 INFO L93 Difference]: Finished difference Result 9740 states and 27165 transitions. [2019-12-07 17:17:41,660 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 17:17:41,660 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 65 [2019-12-07 17:17:41,660 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:41,669 INFO L225 Difference]: With dead ends: 9740 [2019-12-07 17:17:41,669 INFO L226 Difference]: Without dead ends: 9740 [2019-12-07 17:17:41,669 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 9 SyntacticMatches, 2 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 78 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=92, Invalid=328, Unknown=0, NotChecked=0, Total=420 [2019-12-07 17:17:41,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9740 states. [2019-12-07 17:17:41,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9740 to 6792. [2019-12-07 17:17:41,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6792 states. [2019-12-07 17:17:41,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6792 states to 6792 states and 19188 transitions. [2019-12-07 17:17:41,774 INFO L78 Accepts]: Start accepts. Automaton has 6792 states and 19188 transitions. Word has length 65 [2019-12-07 17:17:41,775 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:41,775 INFO L462 AbstractCegarLoop]: Abstraction has 6792 states and 19188 transitions. [2019-12-07 17:17:41,775 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 17:17:41,775 INFO L276 IsEmpty]: Start isEmpty. Operand 6792 states and 19188 transitions. [2019-12-07 17:17:41,780 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 17:17:41,780 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:41,780 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:41,780 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:41,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:41,780 INFO L82 PathProgramCache]: Analyzing trace with hash -1290983485, now seen corresponding path program 8 times [2019-12-07 17:17:41,780 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:41,780 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [129358810] [2019-12-07 17:17:41,780 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:41,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:41,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:41,842 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [129358810] [2019-12-07 17:17:41,842 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:41,842 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 17:17:41,842 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [946578707] [2019-12-07 17:17:41,843 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:17:41,843 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:41,843 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:17:41,843 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:17:41,843 INFO L87 Difference]: Start difference. First operand 6792 states and 19188 transitions. Second operand 7 states. [2019-12-07 17:17:42,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:42,324 INFO L93 Difference]: Finished difference Result 10185 states and 28301 transitions. [2019-12-07 17:17:42,324 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 17:17:42,325 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 65 [2019-12-07 17:17:42,325 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:42,333 INFO L225 Difference]: With dead ends: 10185 [2019-12-07 17:17:42,333 INFO L226 Difference]: Without dead ends: 10185 [2019-12-07 17:17:42,333 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 9 SyntacticMatches, 2 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=55, Invalid=155, Unknown=0, NotChecked=0, Total=210 [2019-12-07 17:17:42,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10185 states. [2019-12-07 17:17:42,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10185 to 6652. [2019-12-07 17:17:42,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6652 states. [2019-12-07 17:17:42,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6652 states to 6652 states and 18795 transitions. [2019-12-07 17:17:42,438 INFO L78 Accepts]: Start accepts. Automaton has 6652 states and 18795 transitions. Word has length 65 [2019-12-07 17:17:42,438 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:42,438 INFO L462 AbstractCegarLoop]: Abstraction has 6652 states and 18795 transitions. [2019-12-07 17:17:42,438 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:17:42,438 INFO L276 IsEmpty]: Start isEmpty. Operand 6652 states and 18795 transitions. [2019-12-07 17:17:42,443 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 17:17:42,444 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:42,444 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:42,444 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:42,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:42,444 INFO L82 PathProgramCache]: Analyzing trace with hash -802576675, now seen corresponding path program 9 times [2019-12-07 17:17:42,444 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:42,444 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1651680602] [2019-12-07 17:17:42,444 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:42,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:42,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:42,508 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1651680602] [2019-12-07 17:17:42,508 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:42,508 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 17:17:42,508 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1221490577] [2019-12-07 17:17:42,508 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:17:42,509 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:42,509 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:17:42,509 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:17:42,509 INFO L87 Difference]: Start difference. First operand 6652 states and 18795 transitions. Second operand 7 states. [2019-12-07 17:17:42,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:42,950 INFO L93 Difference]: Finished difference Result 9674 states and 26957 transitions. [2019-12-07 17:17:42,950 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 17:17:42,950 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 65 [2019-12-07 17:17:42,950 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:42,958 INFO L225 Difference]: With dead ends: 9674 [2019-12-07 17:17:42,958 INFO L226 Difference]: Without dead ends: 9674 [2019-12-07 17:17:42,958 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 8 SyntacticMatches, 2 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=65, Invalid=207, Unknown=0, NotChecked=0, Total=272 [2019-12-07 17:17:42,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9674 states. [2019-12-07 17:17:43,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9674 to 6766. [2019-12-07 17:17:43,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6766 states. [2019-12-07 17:17:43,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6766 states to 6766 states and 19120 transitions. [2019-12-07 17:17:43,056 INFO L78 Accepts]: Start accepts. Automaton has 6766 states and 19120 transitions. Word has length 65 [2019-12-07 17:17:43,056 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:43,056 INFO L462 AbstractCegarLoop]: Abstraction has 6766 states and 19120 transitions. [2019-12-07 17:17:43,056 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:17:43,056 INFO L276 IsEmpty]: Start isEmpty. Operand 6766 states and 19120 transitions. [2019-12-07 17:17:43,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 17:17:43,061 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:43,061 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:43,061 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:43,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:43,061 INFO L82 PathProgramCache]: Analyzing trace with hash -742451517, now seen corresponding path program 10 times [2019-12-07 17:17:43,061 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:43,061 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [865451915] [2019-12-07 17:17:43,061 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:43,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:43,125 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:43,125 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [865451915] [2019-12-07 17:17:43,125 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:43,125 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:17:43,125 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [128977400] [2019-12-07 17:17:43,126 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:17:43,126 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:43,126 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:17:43,126 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:17:43,126 INFO L87 Difference]: Start difference. First operand 6766 states and 19120 transitions. Second operand 7 states. [2019-12-07 17:17:43,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:43,197 INFO L93 Difference]: Finished difference Result 11895 states and 33861 transitions. [2019-12-07 17:17:43,197 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 17:17:43,197 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 65 [2019-12-07 17:17:43,197 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:43,201 INFO L225 Difference]: With dead ends: 11895 [2019-12-07 17:17:43,201 INFO L226 Difference]: Without dead ends: 5170 [2019-12-07 17:17:43,202 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=61, Unknown=0, NotChecked=0, Total=90 [2019-12-07 17:17:43,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5170 states. [2019-12-07 17:17:43,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5170 to 4261. [2019-12-07 17:17:43,252 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4261 states. [2019-12-07 17:17:43,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4261 states to 4261 states and 12094 transitions. [2019-12-07 17:17:43,256 INFO L78 Accepts]: Start accepts. Automaton has 4261 states and 12094 transitions. Word has length 65 [2019-12-07 17:17:43,256 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:43,257 INFO L462 AbstractCegarLoop]: Abstraction has 4261 states and 12094 transitions. [2019-12-07 17:17:43,257 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:17:43,257 INFO L276 IsEmpty]: Start isEmpty. Operand 4261 states and 12094 transitions. [2019-12-07 17:17:43,259 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 17:17:43,259 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:43,259 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:43,259 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:43,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:43,259 INFO L82 PathProgramCache]: Analyzing trace with hash 1243991607, now seen corresponding path program 11 times [2019-12-07 17:17:43,260 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:43,260 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [26303233] [2019-12-07 17:17:43,260 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:43,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:43,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:43,321 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [26303233] [2019-12-07 17:17:43,321 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:43,321 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 17:17:43,322 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [203464411] [2019-12-07 17:17:43,322 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 17:17:43,322 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:43,322 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 17:17:43,322 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-12-07 17:17:43,322 INFO L87 Difference]: Start difference. First operand 4261 states and 12094 transitions. Second operand 8 states. [2019-12-07 17:17:43,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:43,617 INFO L93 Difference]: Finished difference Result 6635 states and 18458 transitions. [2019-12-07 17:17:43,618 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 17:17:43,618 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 65 [2019-12-07 17:17:43,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:43,623 INFO L225 Difference]: With dead ends: 6635 [2019-12-07 17:17:43,623 INFO L226 Difference]: Without dead ends: 6635 [2019-12-07 17:17:43,624 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2019-12-07 17:17:43,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6635 states. [2019-12-07 17:17:43,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6635 to 4270. [2019-12-07 17:17:43,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4270 states. [2019-12-07 17:17:43,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4270 states to 4270 states and 12112 transitions. [2019-12-07 17:17:43,688 INFO L78 Accepts]: Start accepts. Automaton has 4270 states and 12112 transitions. Word has length 65 [2019-12-07 17:17:43,688 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:43,688 INFO L462 AbstractCegarLoop]: Abstraction has 4270 states and 12112 transitions. [2019-12-07 17:17:43,688 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 17:17:43,688 INFO L276 IsEmpty]: Start isEmpty. Operand 4270 states and 12112 transitions. [2019-12-07 17:17:43,691 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 17:17:43,691 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:43,691 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:43,691 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:43,691 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:43,691 INFO L82 PathProgramCache]: Analyzing trace with hash -438034733, now seen corresponding path program 12 times [2019-12-07 17:17:43,691 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:43,691 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1497617051] [2019-12-07 17:17:43,691 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:43,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:43,760 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:43,760 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1497617051] [2019-12-07 17:17:43,761 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:43,761 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 17:17:43,761 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [70530367] [2019-12-07 17:17:43,761 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 17:17:43,761 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:43,761 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 17:17:43,761 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2019-12-07 17:17:43,761 INFO L87 Difference]: Start difference. First operand 4270 states and 12112 transitions. Second operand 8 states. [2019-12-07 17:17:44,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:44,171 INFO L93 Difference]: Finished difference Result 6947 states and 19300 transitions. [2019-12-07 17:17:44,171 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 17:17:44,171 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 65 [2019-12-07 17:17:44,171 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:44,177 INFO L225 Difference]: With dead ends: 6947 [2019-12-07 17:17:44,177 INFO L226 Difference]: Without dead ends: 6947 [2019-12-07 17:17:44,177 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 6 SyntacticMatches, 2 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=117, Unknown=0, NotChecked=0, Total=156 [2019-12-07 17:17:44,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6947 states. [2019-12-07 17:17:44,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6947 to 4084. [2019-12-07 17:17:44,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4084 states. [2019-12-07 17:17:44,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4084 states to 4084 states and 11603 transitions. [2019-12-07 17:17:44,241 INFO L78 Accepts]: Start accepts. Automaton has 4084 states and 11603 transitions. Word has length 65 [2019-12-07 17:17:44,241 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:44,241 INFO L462 AbstractCegarLoop]: Abstraction has 4084 states and 11603 transitions. [2019-12-07 17:17:44,241 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 17:17:44,241 INFO L276 IsEmpty]: Start isEmpty. Operand 4084 states and 11603 transitions. [2019-12-07 17:17:44,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:17:44,244 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:44,244 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:44,244 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:44,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:44,244 INFO L82 PathProgramCache]: Analyzing trace with hash 860114141, now seen corresponding path program 1 times [2019-12-07 17:17:44,244 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:44,244 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842208959] [2019-12-07 17:17:44,244 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:44,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:44,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:44,290 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842208959] [2019-12-07 17:17:44,291 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:44,291 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:17:44,291 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [452657547] [2019-12-07 17:17:44,291 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:17:44,291 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:44,291 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:17:44,291 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:17:44,291 INFO L87 Difference]: Start difference. First operand 4084 states and 11603 transitions. Second operand 3 states. [2019-12-07 17:17:44,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:44,303 INFO L93 Difference]: Finished difference Result 3722 states and 10392 transitions. [2019-12-07 17:17:44,304 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:17:44,304 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 17:17:44,304 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:44,306 INFO L225 Difference]: With dead ends: 3722 [2019-12-07 17:17:44,307 INFO L226 Difference]: Without dead ends: 3722 [2019-12-07 17:17:44,307 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:17:44,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3722 states. [2019-12-07 17:17:44,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3722 to 3722. [2019-12-07 17:17:44,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3722 states. [2019-12-07 17:17:44,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3722 states to 3722 states and 10392 transitions. [2019-12-07 17:17:44,351 INFO L78 Accepts]: Start accepts. Automaton has 3722 states and 10392 transitions. Word has length 66 [2019-12-07 17:17:44,351 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:44,351 INFO L462 AbstractCegarLoop]: Abstraction has 3722 states and 10392 transitions. [2019-12-07 17:17:44,351 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:17:44,351 INFO L276 IsEmpty]: Start isEmpty. Operand 3722 states and 10392 transitions. [2019-12-07 17:17:44,353 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:17:44,353 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:44,353 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:44,353 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:44,353 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:44,354 INFO L82 PathProgramCache]: Analyzing trace with hash 1955460849, now seen corresponding path program 1 times [2019-12-07 17:17:44,354 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:44,354 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [348385855] [2019-12-07 17:17:44,354 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:44,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:44,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:44,512 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [348385855] [2019-12-07 17:17:44,512 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:44,512 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 17:17:44,512 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1889839768] [2019-12-07 17:17:44,513 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 17:17:44,513 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:44,513 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 17:17:44,513 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=84, Unknown=0, NotChecked=0, Total=110 [2019-12-07 17:17:44,513 INFO L87 Difference]: Start difference. First operand 3722 states and 10392 transitions. Second operand 11 states. [2019-12-07 17:17:45,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:45,026 INFO L93 Difference]: Finished difference Result 6678 states and 18107 transitions. [2019-12-07 17:17:45,027 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 17:17:45,027 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 66 [2019-12-07 17:17:45,027 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:45,032 INFO L225 Difference]: With dead ends: 6678 [2019-12-07 17:17:45,032 INFO L226 Difference]: Without dead ends: 6678 [2019-12-07 17:17:45,032 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=81, Invalid=225, Unknown=0, NotChecked=0, Total=306 [2019-12-07 17:17:45,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6678 states. [2019-12-07 17:17:45,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6678 to 3750. [2019-12-07 17:17:45,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3750 states. [2019-12-07 17:17:45,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3750 states to 3750 states and 10395 transitions. [2019-12-07 17:17:45,093 INFO L78 Accepts]: Start accepts. Automaton has 3750 states and 10395 transitions. Word has length 66 [2019-12-07 17:17:45,093 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:45,094 INFO L462 AbstractCegarLoop]: Abstraction has 3750 states and 10395 transitions. [2019-12-07 17:17:45,094 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 17:17:45,094 INFO L276 IsEmpty]: Start isEmpty. Operand 3750 states and 10395 transitions. [2019-12-07 17:17:45,096 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:17:45,096 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:45,096 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:45,096 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:45,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:45,096 INFO L82 PathProgramCache]: Analyzing trace with hash -1676125237, now seen corresponding path program 2 times [2019-12-07 17:17:45,096 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:45,096 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1599229950] [2019-12-07 17:17:45,096 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:45,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:45,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:45,124 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1599229950] [2019-12-07 17:17:45,124 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:45,124 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:17:45,124 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [614948683] [2019-12-07 17:17:45,124 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:17:45,124 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:45,124 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:17:45,124 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:17:45,124 INFO L87 Difference]: Start difference. First operand 3750 states and 10395 transitions. Second operand 3 states. [2019-12-07 17:17:45,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:45,153 INFO L93 Difference]: Finished difference Result 3750 states and 10394 transitions. [2019-12-07 17:17:45,153 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:17:45,153 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 17:17:45,153 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:45,156 INFO L225 Difference]: With dead ends: 3750 [2019-12-07 17:17:45,156 INFO L226 Difference]: Without dead ends: 3750 [2019-12-07 17:17:45,156 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:17:45,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3750 states. [2019-12-07 17:17:45,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3750 to 2101. [2019-12-07 17:17:45,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2101 states. [2019-12-07 17:17:45,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2101 states to 2101 states and 5862 transitions. [2019-12-07 17:17:45,191 INFO L78 Accepts]: Start accepts. Automaton has 2101 states and 5862 transitions. Word has length 66 [2019-12-07 17:17:45,191 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:45,191 INFO L462 AbstractCegarLoop]: Abstraction has 2101 states and 5862 transitions. [2019-12-07 17:17:45,191 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:17:45,191 INFO L276 IsEmpty]: Start isEmpty. Operand 2101 states and 5862 transitions. [2019-12-07 17:17:45,193 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:17:45,193 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:45,193 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:45,193 INFO L410 AbstractCegarLoop]: === Iteration 29 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:45,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:45,193 INFO L82 PathProgramCache]: Analyzing trace with hash 1668809625, now seen corresponding path program 1 times [2019-12-07 17:17:45,193 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:45,193 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083585619] [2019-12-07 17:17:45,193 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:45,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:17:45,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:17:45,224 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083585619] [2019-12-07 17:17:45,225 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:17:45,225 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:17:45,225 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2074644532] [2019-12-07 17:17:45,225 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:17:45,225 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:17:45,225 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:17:45,225 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:17:45,225 INFO L87 Difference]: Start difference. First operand 2101 states and 5862 transitions. Second operand 3 states. [2019-12-07 17:17:45,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:17:45,234 INFO L93 Difference]: Finished difference Result 1840 states and 5032 transitions. [2019-12-07 17:17:45,234 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:17:45,235 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 17:17:45,235 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:17:45,236 INFO L225 Difference]: With dead ends: 1840 [2019-12-07 17:17:45,236 INFO L226 Difference]: Without dead ends: 1840 [2019-12-07 17:17:45,236 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:17:45,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1840 states. [2019-12-07 17:17:45,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1840 to 1792. [2019-12-07 17:17:45,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1792 states. [2019-12-07 17:17:45,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1792 states to 1792 states and 4902 transitions. [2019-12-07 17:17:45,259 INFO L78 Accepts]: Start accepts. Automaton has 1792 states and 4902 transitions. Word has length 67 [2019-12-07 17:17:45,259 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:17:45,259 INFO L462 AbstractCegarLoop]: Abstraction has 1792 states and 4902 transitions. [2019-12-07 17:17:45,259 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:17:45,259 INFO L276 IsEmpty]: Start isEmpty. Operand 1792 states and 4902 transitions. [2019-12-07 17:17:45,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 17:17:45,260 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:17:45,260 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:17:45,260 INFO L410 AbstractCegarLoop]: === Iteration 30 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:17:45,261 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:17:45,261 INFO L82 PathProgramCache]: Analyzing trace with hash -1093105687, now seen corresponding path program 1 times [2019-12-07 17:17:45,261 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:17:45,261 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1945855339] [2019-12-07 17:17:45,261 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:17:45,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:17:45,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:17:45,330 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:17:45,330 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 17:17:45,333 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] ULTIMATE.startENTRY-->L805: Formula: (let ((.cse0 (store |v_#valid_49| 0 0))) (and (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t2028~0.base_21| 4)) (= 0 v_~x$w_buff0_used~0_815) (= v_~x$r_buff0_thd1~0_121 0) (= v_~x$flush_delayed~0_33 0) (= v_~y~0_122 0) (= 0 v_~x$r_buff0_thd3~0_131) (= 0 |v_ULTIMATE.start_main_~#t2028~0.offset_18|) (= 0 v_~x$r_buff1_thd3~0_199) (= v_~x$mem_tmp~0_19 0) (= 0 v_~x$r_buff1_thd2~0_200) (= v_~weak$$choice2~0_113 0) (= v_~z~0_31 0) (= v_~main$tmp_guard1~0_21 0) (= 0 v_~x$w_buff1~0_221) (= 0 v_~weak$$choice0~0_15) (= v_~main$tmp_guard0~0_23 0) (= 0 v_~x$read_delayed_var~0.base_7) (< 0 |v_#StackHeapBarrier_15|) (= (select .cse0 |v_ULTIMATE.start_main_~#t2028~0.base_21|) 0) (= v_~x$r_buff0_thd0~0_372 0) (= 0 v_~x~0_181) (= 0 |v_#NULL.base_4|) (= v_~__unbuffered_cnt~0_156 0) (= 0 v_~x$read_delayed~0_7) (= 0 v_~x$r_buff0_thd2~0_212) (= |v_#memory_int_15| (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2028~0.base_21| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2028~0.base_21|) |v_ULTIMATE.start_main_~#t2028~0.offset_18| 0))) (= 0 v_~x$w_buff1_used~0_499) (= |v_#NULL.offset_4| 0) (= v_~x$r_buff1_thd1~0_184 0) (= v_~x$r_buff1_thd0~0_296 0) (= 0 v_~x$read_delayed_var~0.offset_7) (= |v_#valid_47| (store .cse0 |v_ULTIMATE.start_main_~#t2028~0.base_21| 1)) (= 0 v_~__unbuffered_p2_EAX~0_22) (< |v_#StackHeapBarrier_15| |v_ULTIMATE.start_main_~#t2028~0.base_21|) (= 0 v_~x$w_buff0~0_269))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_49|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_22|, ~x$w_buff0~0=v_~x$w_buff0~0_269, ULTIMATE.start_main_~#t2029~0.base=|v_ULTIMATE.start_main_~#t2029~0.base_22|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_28|, ~x$flush_delayed~0=v_~x$flush_delayed~0_33, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_40|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_30|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_30|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_46|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_184, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_131, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_51|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_37|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_46|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_33|, #length=|v_#length_19|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_22, ULTIMATE.start_main_~#t2029~0.offset=|v_ULTIMATE.start_main_~#t2029~0.offset_18|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_372, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_11|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_38|, ~x$w_buff1~0=v_~x$w_buff1~0_221, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_43|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_499, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_200, ULTIMATE.start_main_~#t2028~0.base=|v_ULTIMATE.start_main_~#t2028~0.base_21|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_49|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_112|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_7, ~weak$$choice0~0=v_~weak$$choice0~0_15, #StackHeapBarrier=|v_#StackHeapBarrier_15|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_33|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_156, ~x~0=v_~x~0_181, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_121, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_22|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_34|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_32|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_30|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_199, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_118|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_18|, ~x$mem_tmp~0=v_~x$mem_tmp~0_19, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_26|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_51|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_32|, ~y~0=v_~y~0_122, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_11|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_24|, ULTIMATE.start_main_~#t2030~0.base=|v_ULTIMATE.start_main_~#t2030~0.base_21|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_26|, ULTIMATE.start_main_~#t2030~0.offset=|v_ULTIMATE.start_main_~#t2030~0.offset_17|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_49|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_~#t2028~0.offset=|v_ULTIMATE.start_main_~#t2028~0.offset_18|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_296, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_212, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_60|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_39|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_815, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_33|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_7, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_21|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_15|, ~z~0=v_~z~0_31, ~weak$$choice2~0=v_~weak$$choice2~0_113, ~x$read_delayed~0=v_~x$read_delayed~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ~x$w_buff0~0, ULTIMATE.start_main_~#t2029~0.base, ULTIMATE.start_main_#t~ite28, ~x$flush_delayed~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ~x$r_buff1_thd1~0, ~x$r_buff0_thd3~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t2029~0.offset, ~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ~x$w_buff1~0, ULTIMATE.start_main_#t~ite35, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_~#t2028~0.base, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~x$read_delayed_var~0.base, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~__unbuffered_cnt~0, ~x~0, ~x$r_buff0_thd1~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~x$r_buff1_thd3~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~x$mem_tmp~0, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ~y~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_~#t2030~0.base, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_~#t2030~0.offset, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_~#t2028~0.offset, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~x$w_buff0_used~0, ULTIMATE.start_main_#t~ite41, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~x$read_delayed~0] because there is no mapped edge [2019-12-07 17:17:45,333 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L805-1-->L807: Formula: (and (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2029~0.base_13| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2029~0.base_13|) |v_ULTIMATE.start_main_~#t2029~0.offset_11| 1)) |v_#memory_int_11|) (= |v_#valid_32| (store |v_#valid_33| |v_ULTIMATE.start_main_~#t2029~0.base_13| 1)) (not (= 0 |v_ULTIMATE.start_main_~#t2029~0.base_13|)) (= 0 |v_ULTIMATE.start_main_~#t2029~0.offset_11|) (= 0 (select |v_#valid_33| |v_ULTIMATE.start_main_~#t2029~0.base_13|)) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t2029~0.base_13| 4)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2029~0.base_13|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_12|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_6|, ULTIMATE.start_main_~#t2029~0.base=|v_ULTIMATE.start_main_~#t2029~0.base_13|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_11|, #length=|v_#length_15|, ULTIMATE.start_main_~#t2029~0.offset=|v_ULTIMATE.start_main_~#t2029~0.offset_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t2029~0.base, #valid, #memory_int, #length, ULTIMATE.start_main_~#t2029~0.offset] because there is no mapped edge [2019-12-07 17:17:45,334 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] P1ENTRY-->L4-3: Formula: (and (not (= 0 v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11)) (= v_P1Thread1of1ForFork1_~arg.offset_9 |v_P1Thread1of1ForFork1_#in~arg.offset_11|) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9| v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11) (= 1 v_~x$w_buff0_used~0_98) (= v_P1Thread1of1ForFork1_~arg.base_9 |v_P1Thread1of1ForFork1_#in~arg.base_11|) (= v_~x$w_buff1_used~0_55 v_~x$w_buff0_used~0_99) (= 2 v_~x$w_buff0~0_30) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9| (ite (not (and (not (= (mod v_~x$w_buff0_used~0_98 256) 0)) (not (= 0 (mod v_~x$w_buff1_used~0_55 256))))) 1 0)) (= v_~x$w_buff0~0_31 v_~x$w_buff1~0_21)) InVars {~x$w_buff0~0=v_~x$w_buff0~0_31, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_11|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_11|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_99} OutVars{P1Thread1of1ForFork1___VERIFIER_assert_~expression=v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11, ~x$w_buff0~0=v_~x$w_buff0~0_30, P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_9, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression=|v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9|, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_9, ~x$w_buff1~0=v_~x$w_buff1~0_21, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_11|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_11|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_55, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_98} AuxVars[] AssignedVars[P1Thread1of1ForFork1___VERIFIER_assert_~expression, ~x$w_buff0~0, P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression, P1Thread1of1ForFork1_~arg.base, ~x$w_buff1~0, ~x$w_buff1_used~0, ~x$w_buff0_used~0] because there is no mapped edge [2019-12-07 17:17:45,334 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L807-1-->L809: Formula: (and (= (store |v_#length_14| |v_ULTIMATE.start_main_~#t2030~0.base_9| 4) |v_#length_13|) (= |v_ULTIMATE.start_main_~#t2030~0.offset_8| 0) (= |v_#valid_27| (store |v_#valid_28| |v_ULTIMATE.start_main_~#t2030~0.base_9| 1)) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t2030~0.base_9|) (not (= 0 |v_ULTIMATE.start_main_~#t2030~0.base_9|)) (= |v_#memory_int_9| (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2030~0.base_9| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2030~0.base_9|) |v_ULTIMATE.start_main_~#t2030~0.offset_8| 2))) (= 0 (select |v_#valid_28| |v_ULTIMATE.start_main_~#t2030~0.base_9|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_28|, #memory_int=|v_#memory_int_10|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_~#t2030~0.base=|v_ULTIMATE.start_main_~#t2030~0.base_9|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_27|, #memory_int=|v_#memory_int_9|, ULTIMATE.start_main_~#t2030~0.offset=|v_ULTIMATE.start_main_~#t2030~0.offset_8|, #length=|v_#length_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2030~0.base, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, ULTIMATE.start_main_~#t2030~0.offset, #length] because there is no mapped edge [2019-12-07 17:17:45,335 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L782-2-->L782-4: Formula: (let ((.cse1 (= (mod ~x$r_buff1_thd3~0_In-1669820522 256) 0)) (.cse0 (= (mod ~x$w_buff1_used~0_In-1669820522 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite15_Out-1669820522| ~x$w_buff1~0_In-1669820522) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~x~0_In-1669820522 |P2Thread1of1ForFork2_#t~ite15_Out-1669820522|)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-1669820522, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1669820522, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1669820522, ~x~0=~x~0_In-1669820522} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-1669820522|, ~x$w_buff1~0=~x$w_buff1~0_In-1669820522, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1669820522, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1669820522, ~x~0=~x~0_In-1669820522} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 17:17:45,335 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [695] [695] L782-4-->L783: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_6| v_~x~0_17) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_6|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_5|, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_5|, ~x~0=v_~x~0_17} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, P2Thread1of1ForFork2_#t~ite16, ~x~0] because there is no mapped edge [2019-12-07 17:17:45,336 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L783-->L783-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In929674980 256))) (.cse1 (= 0 (mod ~x$r_buff0_thd3~0_In929674980 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P2Thread1of1ForFork2_#t~ite17_Out929674980|)) (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In929674980 |P2Thread1of1ForFork2_#t~ite17_Out929674980|)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In929674980, ~x$w_buff0_used~0=~x$w_buff0_used~0_In929674980} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In929674980, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out929674980|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In929674980} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 17:17:45,336 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L784-->L784-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff1_used~0_In-980421816 256))) (.cse0 (= 0 (mod ~x$r_buff1_thd3~0_In-980421816 256))) (.cse2 (= (mod ~x$r_buff0_thd3~0_In-980421816 256) 0)) (.cse3 (= 0 (mod ~x$w_buff0_used~0_In-980421816 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite18_Out-980421816|)) (and (or .cse1 .cse0) (or .cse2 .cse3) (= ~x$w_buff1_used~0_In-980421816 |P2Thread1of1ForFork2_#t~ite18_Out-980421816|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-980421816, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-980421816, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-980421816, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-980421816} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-980421816, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-980421816, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-980421816, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-980421816|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-980421816} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 17:17:45,336 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L785-->L785-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In-380305941 256))) (.cse1 (= (mod ~x$w_buff0_used~0_In-380305941 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite19_Out-380305941| ~x$r_buff0_thd3~0_In-380305941)) (and (not .cse0) (not .cse1) (= 0 |P2Thread1of1ForFork2_#t~ite19_Out-380305941|)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-380305941, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-380305941} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-380305941, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-380305941|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-380305941} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 17:17:45,337 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [769] [769] L786-->L786-2: Formula: (let ((.cse3 (= 0 (mod ~x$r_buff1_thd3~0_In1996586475 256))) (.cse2 (= (mod ~x$w_buff1_used~0_In1996586475 256) 0)) (.cse0 (= (mod ~x$w_buff0_used~0_In1996586475 256) 0)) (.cse1 (= 0 (mod ~x$r_buff0_thd3~0_In1996586475 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork2_#t~ite20_Out1996586475| ~x$r_buff1_thd3~0_In1996586475)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= |P2Thread1of1ForFork2_#t~ite20_Out1996586475| 0)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In1996586475, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1996586475, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1996586475, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1996586475} OutVars{P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out1996586475|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1996586475, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1996586475, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1996586475, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1996586475} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 17:17:45,337 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L786-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74) (= |v_P2Thread1of1ForFork2_#t~ite20_54| v_~x$r_buff1_thd3~0_147)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_54|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_53|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_147, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~x$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 17:17:45,337 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L733-2-->L733-5: Formula: (let ((.cse0 (= |P0Thread1of1ForFork0_#t~ite3_Out1524172528| |P0Thread1of1ForFork0_#t~ite4_Out1524172528|)) (.cse1 (= (mod ~x$r_buff1_thd1~0_In1524172528 256) 0)) (.cse2 (= (mod ~x$w_buff1_used~0_In1524172528 256) 0))) (or (and .cse0 (= ~x~0_In1524172528 |P0Thread1of1ForFork0_#t~ite3_Out1524172528|) (or .cse1 .cse2)) (and .cse0 (not .cse1) (not .cse2) (= |P0Thread1of1ForFork0_#t~ite3_Out1524172528| ~x$w_buff1~0_In1524172528)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In1524172528, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1524172528, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In1524172528, ~x~0=~x~0_In1524172528} OutVars{P0Thread1of1ForFork0_#t~ite3=|P0Thread1of1ForFork0_#t~ite3_Out1524172528|, P0Thread1of1ForFork0_#t~ite4=|P0Thread1of1ForFork0_#t~ite4_Out1524172528|, ~x$w_buff1~0=~x$w_buff1~0_In1524172528, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1524172528, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In1524172528, ~x~0=~x~0_In1524172528} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite3, P0Thread1of1ForFork0_#t~ite4] because there is no mapped edge [2019-12-07 17:17:45,337 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [774] [774] L734-->L734-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd1~0_In-994691513 256))) (.cse0 (= (mod ~x$w_buff0_used~0_In-994691513 256) 0))) (or (and (not .cse0) (= |P0Thread1of1ForFork0_#t~ite5_Out-994691513| 0) (not .cse1)) (and (= ~x$w_buff0_used~0_In-994691513 |P0Thread1of1ForFork0_#t~ite5_Out-994691513|) (or .cse1 .cse0)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-994691513, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-994691513} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-994691513|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-994691513, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-994691513} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 17:17:45,338 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L735-->L735-2: Formula: (let ((.cse2 (= (mod ~x$w_buff0_used~0_In1328825479 256) 0)) (.cse3 (= 0 (mod ~x$r_buff0_thd1~0_In1328825479 256))) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In1328825479 256))) (.cse0 (= (mod ~x$r_buff1_thd1~0_In1328825479 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite6_Out1328825479| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (or .cse1 .cse0) (= |P0Thread1of1ForFork0_#t~ite6_Out1328825479| ~x$w_buff1_used~0_In1328825479)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In1328825479, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1328825479, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In1328825479, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1328825479} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out1328825479|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In1328825479, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1328825479, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In1328825479, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1328825479} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 17:17:45,338 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L736-->L736-2: Formula: (let ((.cse0 (= (mod ~x$r_buff0_thd1~0_In587091137 256) 0)) (.cse1 (= (mod ~x$w_buff0_used~0_In587091137 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite7_Out587091137| 0) (not .cse0) (not .cse1)) (and (= |P0Thread1of1ForFork0_#t~ite7_Out587091137| ~x$r_buff0_thd1~0_In587091137) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In587091137, ~x$w_buff0_used~0=~x$w_buff0_used~0_In587091137} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In587091137, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out587091137|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In587091137} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-12-07 17:17:45,338 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L737-->L737-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff1_used~0_In2143732912 256))) (.cse0 (= 0 (mod ~x$r_buff1_thd1~0_In2143732912 256))) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In2143732912 256))) (.cse3 (= 0 (mod ~x$r_buff0_thd1~0_In2143732912 256)))) (or (and (= |P0Thread1of1ForFork0_#t~ite8_Out2143732912| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P0Thread1of1ForFork0_#t~ite8_Out2143732912| ~x$r_buff1_thd1~0_In2143732912) (or .cse1 .cse0) (or .cse2 .cse3)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In2143732912, ~x$w_buff1_used~0=~x$w_buff1_used~0_In2143732912, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In2143732912, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2143732912} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In2143732912, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out2143732912|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In2143732912, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In2143732912, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2143732912} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 17:17:45,338 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L737-2-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= v_~x$r_buff1_thd1~0_126 |v_P0Thread1of1ForFork0_#t~ite8_34|) (= (+ v_~__unbuffered_cnt~0_63 1) v_~__unbuffered_cnt~0_62)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_63} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_33|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_62, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_126} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, ~x$r_buff1_thd1~0] because there is no mapped edge [2019-12-07 17:17:45,339 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L763-->L763-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In2037784181 256) 0)) (.cse1 (= 0 (mod ~x$r_buff0_thd2~0_In2037784181 256)))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out2037784181| 0)) (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In2037784181 |P1Thread1of1ForFork1_#t~ite11_Out2037784181|)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2037784181, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2037784181} OutVars{P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out2037784181|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2037784181, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2037784181} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 17:17:45,339 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [783] [783] L764-->L764-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-41014310 256))) (.cse0 (= 0 (mod ~x$r_buff0_thd2~0_In-41014310 256))) (.cse2 (= 0 (mod ~x$w_buff1_used~0_In-41014310 256))) (.cse3 (= 0 (mod ~x$r_buff1_thd2~0_In-41014310 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~x$w_buff1_used~0_In-41014310 |P1Thread1of1ForFork1_#t~ite12_Out-41014310|)) (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out-41014310|) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-41014310, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-41014310, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-41014310, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-41014310} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-41014310, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-41014310, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-41014310|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-41014310, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-41014310} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 17:17:45,339 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L765-->L766: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd2~0_In-1696183501 256))) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In-1696183501 256))) (.cse0 (= ~x$r_buff0_thd2~0_In-1696183501 ~x$r_buff0_thd2~0_Out-1696183501))) (or (and .cse0 .cse1) (and (not .cse2) (not .cse1) (= 0 ~x$r_buff0_thd2~0_Out-1696183501)) (and .cse2 .cse0))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1696183501, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1696183501} OutVars{P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-1696183501|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out-1696183501, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1696183501} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-12-07 17:17:45,340 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L766-->L766-2: Formula: (let ((.cse2 (= (mod ~x$w_buff0_used~0_In-1305240713 256) 0)) (.cse3 (= 0 (mod ~x$r_buff0_thd2~0_In-1305240713 256))) (.cse1 (= (mod ~x$r_buff1_thd2~0_In-1305240713 256) 0)) (.cse0 (= (mod ~x$w_buff1_used~0_In-1305240713 256) 0))) (or (and (= ~x$r_buff1_thd2~0_In-1305240713 |P1Thread1of1ForFork1_#t~ite14_Out-1305240713|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P1Thread1of1ForFork1_#t~ite14_Out-1305240713| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1305240713, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1305240713, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1305240713, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1305240713} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-1305240713, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1305240713, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1305240713, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-1305240713|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1305240713} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 17:17:45,340 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L766-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= v_~x$r_buff1_thd2~0_154 |v_P1Thread1of1ForFork1_#t~ite14_40|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_93 1) v_~__unbuffered_cnt~0_92)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_93, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_40|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_154, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_92, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_39|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 17:17:45,340 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [711] [711] L809-1-->L815: Formula: (and (= v_~main$tmp_guard0~0_6 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= 0 (mod v_~main$tmp_guard0~0_6 256)))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 17:17:45,340 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L815-2-->L815-5: Formula: (let ((.cse1 (= (mod ~x$r_buff1_thd0~0_In-1077227679 256) 0)) (.cse2 (= (mod ~x$w_buff1_used~0_In-1077227679 256) 0)) (.cse0 (= |ULTIMATE.start_main_#t~ite25_Out-1077227679| |ULTIMATE.start_main_#t~ite24_Out-1077227679|))) (or (and .cse0 (not .cse1) (= ~x$w_buff1~0_In-1077227679 |ULTIMATE.start_main_#t~ite24_Out-1077227679|) (not .cse2)) (and (or .cse1 .cse2) .cse0 (= |ULTIMATE.start_main_#t~ite24_Out-1077227679| ~x~0_In-1077227679)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-1077227679, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1077227679, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1077227679, ~x~0=~x~0_In-1077227679} OutVars{~x$w_buff1~0=~x$w_buff1~0_In-1077227679, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-1077227679|, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-1077227679|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1077227679, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1077227679, ~x~0=~x~0_In-1077227679} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 17:17:45,340 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L816-->L816-2: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd0~0_In-1296925237 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In-1296925237 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite26_Out-1296925237| 0) (not .cse1)) (and (= ~x$w_buff0_used~0_In-1296925237 |ULTIMATE.start_main_#t~ite26_Out-1296925237|) (or .cse1 .cse0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1296925237, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1296925237} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1296925237, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-1296925237|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1296925237} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 17:17:45,341 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L817-->L817-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In1797287797 256) 0)) (.cse1 (= (mod ~x$r_buff0_thd0~0_In1797287797 256) 0)) (.cse3 (= (mod ~x$w_buff1_used~0_In1797287797 256) 0)) (.cse2 (= (mod ~x$r_buff1_thd0~0_In1797287797 256) 0))) (or (and (= ~x$w_buff1_used~0_In1797287797 |ULTIMATE.start_main_#t~ite27_Out1797287797|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2))) (= 0 |ULTIMATE.start_main_#t~ite27_Out1797287797|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1797287797, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1797287797, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1797287797, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1797287797} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1797287797, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1797287797, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out1797287797|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1797287797, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1797287797} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 17:17:45,341 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [768] [768] L818-->L818-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd0~0_In869228053 256))) (.cse0 (= (mod ~x$w_buff0_used~0_In869228053 256) 0))) (or (and (= ~x$r_buff0_thd0~0_In869228053 |ULTIMATE.start_main_#t~ite28_Out869228053|) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite28_Out869228053|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In869228053, ~x$w_buff0_used~0=~x$w_buff0_used~0_In869228053} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In869228053, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out869228053|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In869228053} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 17:17:45,341 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L819-->L819-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff1_thd0~0_In-2081649921 256))) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In-2081649921 256))) (.cse2 (= 0 (mod ~x$r_buff0_thd0~0_In-2081649921 256))) (.cse3 (= 0 (mod ~x$w_buff0_used~0_In-2081649921 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite29_Out-2081649921| ~x$r_buff1_thd0~0_In-2081649921)) (and (= |ULTIMATE.start_main_#t~ite29_Out-2081649921| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-2081649921, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-2081649921, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-2081649921, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-2081649921} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-2081649921, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-2081649921|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-2081649921, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-2081649921, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-2081649921} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 17:17:45,344 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L831-->L832: Formula: (and (= v_~x$r_buff0_thd0~0_111 v_~x$r_buff0_thd0~0_110) (not (= (mod v_~weak$$choice2~0_23 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_111, ~weak$$choice2~0=v_~weak$$choice2~0_23} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_110, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_6|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_10|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_6|, ~weak$$choice2~0=v_~weak$$choice2~0_23} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 17:17:45,344 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L834-->L837-1: Formula: (and (= v_~x$mem_tmp~0_12 v_~x~0_151) (= (mod v_~main$tmp_guard1~0_14 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|) (= v_~x$flush_delayed~0_25 0) (not (= (mod v_~x$flush_delayed~0_26 256) 0))) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_26, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_14, ~x$mem_tmp~0=v_~x$mem_tmp~0_12} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_24|, ~x$flush_delayed~0=v_~x$flush_delayed~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_14, ~x$mem_tmp~0=v_~x$mem_tmp~0_12, ~x~0=v_~x~0_151, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ~x$flush_delayed~0, ~x~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 17:17:45,345 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L837-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 17:17:45,404 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 05:17:45 BasicIcfg [2019-12-07 17:17:45,404 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 17:17:45,405 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 17:17:45,405 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 17:17:45,405 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 17:17:45,405 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:16:17" (3/4) ... [2019-12-07 17:17:45,407 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 17:17:45,407 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] ULTIMATE.startENTRY-->L805: Formula: (let ((.cse0 (store |v_#valid_49| 0 0))) (and (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t2028~0.base_21| 4)) (= 0 v_~x$w_buff0_used~0_815) (= v_~x$r_buff0_thd1~0_121 0) (= v_~x$flush_delayed~0_33 0) (= v_~y~0_122 0) (= 0 v_~x$r_buff0_thd3~0_131) (= 0 |v_ULTIMATE.start_main_~#t2028~0.offset_18|) (= 0 v_~x$r_buff1_thd3~0_199) (= v_~x$mem_tmp~0_19 0) (= 0 v_~x$r_buff1_thd2~0_200) (= v_~weak$$choice2~0_113 0) (= v_~z~0_31 0) (= v_~main$tmp_guard1~0_21 0) (= 0 v_~x$w_buff1~0_221) (= 0 v_~weak$$choice0~0_15) (= v_~main$tmp_guard0~0_23 0) (= 0 v_~x$read_delayed_var~0.base_7) (< 0 |v_#StackHeapBarrier_15|) (= (select .cse0 |v_ULTIMATE.start_main_~#t2028~0.base_21|) 0) (= v_~x$r_buff0_thd0~0_372 0) (= 0 v_~x~0_181) (= 0 |v_#NULL.base_4|) (= v_~__unbuffered_cnt~0_156 0) (= 0 v_~x$read_delayed~0_7) (= 0 v_~x$r_buff0_thd2~0_212) (= |v_#memory_int_15| (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2028~0.base_21| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2028~0.base_21|) |v_ULTIMATE.start_main_~#t2028~0.offset_18| 0))) (= 0 v_~x$w_buff1_used~0_499) (= |v_#NULL.offset_4| 0) (= v_~x$r_buff1_thd1~0_184 0) (= v_~x$r_buff1_thd0~0_296 0) (= 0 v_~x$read_delayed_var~0.offset_7) (= |v_#valid_47| (store .cse0 |v_ULTIMATE.start_main_~#t2028~0.base_21| 1)) (= 0 v_~__unbuffered_p2_EAX~0_22) (< |v_#StackHeapBarrier_15| |v_ULTIMATE.start_main_~#t2028~0.base_21|) (= 0 v_~x$w_buff0~0_269))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_49|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_22|, ~x$w_buff0~0=v_~x$w_buff0~0_269, ULTIMATE.start_main_~#t2029~0.base=|v_ULTIMATE.start_main_~#t2029~0.base_22|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_28|, ~x$flush_delayed~0=v_~x$flush_delayed~0_33, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_40|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_30|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_30|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_46|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_184, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_131, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_51|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_37|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_46|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_33|, #length=|v_#length_19|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_22, ULTIMATE.start_main_~#t2029~0.offset=|v_ULTIMATE.start_main_~#t2029~0.offset_18|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_372, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_11|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_38|, ~x$w_buff1~0=v_~x$w_buff1~0_221, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_43|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_499, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_200, ULTIMATE.start_main_~#t2028~0.base=|v_ULTIMATE.start_main_~#t2028~0.base_21|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_49|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_112|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_7, ~weak$$choice0~0=v_~weak$$choice0~0_15, #StackHeapBarrier=|v_#StackHeapBarrier_15|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_33|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_156, ~x~0=v_~x~0_181, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_121, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_22|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_34|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_32|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_30|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_199, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_118|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_18|, ~x$mem_tmp~0=v_~x$mem_tmp~0_19, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_26|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_51|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_32|, ~y~0=v_~y~0_122, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_11|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_24|, ULTIMATE.start_main_~#t2030~0.base=|v_ULTIMATE.start_main_~#t2030~0.base_21|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_26|, ULTIMATE.start_main_~#t2030~0.offset=|v_ULTIMATE.start_main_~#t2030~0.offset_17|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_49|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_~#t2028~0.offset=|v_ULTIMATE.start_main_~#t2028~0.offset_18|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_296, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_212, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_60|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_39|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_815, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_33|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_7, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_21|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_15|, ~z~0=v_~z~0_31, ~weak$$choice2~0=v_~weak$$choice2~0_113, ~x$read_delayed~0=v_~x$read_delayed~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ~x$w_buff0~0, ULTIMATE.start_main_~#t2029~0.base, ULTIMATE.start_main_#t~ite28, ~x$flush_delayed~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ~x$r_buff1_thd1~0, ~x$r_buff0_thd3~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t2029~0.offset, ~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ~x$w_buff1~0, ULTIMATE.start_main_#t~ite35, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_~#t2028~0.base, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~x$read_delayed_var~0.base, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~__unbuffered_cnt~0, ~x~0, ~x$r_buff0_thd1~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~x$r_buff1_thd3~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~x$mem_tmp~0, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ~y~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_~#t2030~0.base, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_~#t2030~0.offset, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_~#t2028~0.offset, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~x$w_buff0_used~0, ULTIMATE.start_main_#t~ite41, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~x$read_delayed~0] because there is no mapped edge [2019-12-07 17:17:45,408 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L805-1-->L807: Formula: (and (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2029~0.base_13| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2029~0.base_13|) |v_ULTIMATE.start_main_~#t2029~0.offset_11| 1)) |v_#memory_int_11|) (= |v_#valid_32| (store |v_#valid_33| |v_ULTIMATE.start_main_~#t2029~0.base_13| 1)) (not (= 0 |v_ULTIMATE.start_main_~#t2029~0.base_13|)) (= 0 |v_ULTIMATE.start_main_~#t2029~0.offset_11|) (= 0 (select |v_#valid_33| |v_ULTIMATE.start_main_~#t2029~0.base_13|)) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t2029~0.base_13| 4)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2029~0.base_13|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_12|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_6|, ULTIMATE.start_main_~#t2029~0.base=|v_ULTIMATE.start_main_~#t2029~0.base_13|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_11|, #length=|v_#length_15|, ULTIMATE.start_main_~#t2029~0.offset=|v_ULTIMATE.start_main_~#t2029~0.offset_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t2029~0.base, #valid, #memory_int, #length, ULTIMATE.start_main_~#t2029~0.offset] because there is no mapped edge [2019-12-07 17:17:45,408 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] P1ENTRY-->L4-3: Formula: (and (not (= 0 v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11)) (= v_P1Thread1of1ForFork1_~arg.offset_9 |v_P1Thread1of1ForFork1_#in~arg.offset_11|) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9| v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11) (= 1 v_~x$w_buff0_used~0_98) (= v_P1Thread1of1ForFork1_~arg.base_9 |v_P1Thread1of1ForFork1_#in~arg.base_11|) (= v_~x$w_buff1_used~0_55 v_~x$w_buff0_used~0_99) (= 2 v_~x$w_buff0~0_30) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9| (ite (not (and (not (= (mod v_~x$w_buff0_used~0_98 256) 0)) (not (= 0 (mod v_~x$w_buff1_used~0_55 256))))) 1 0)) (= v_~x$w_buff0~0_31 v_~x$w_buff1~0_21)) InVars {~x$w_buff0~0=v_~x$w_buff0~0_31, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_11|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_11|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_99} OutVars{P1Thread1of1ForFork1___VERIFIER_assert_~expression=v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_11, ~x$w_buff0~0=v_~x$w_buff0~0_30, P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_9, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression=|v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_9|, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_9, ~x$w_buff1~0=v_~x$w_buff1~0_21, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_11|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_11|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_55, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_98} AuxVars[] AssignedVars[P1Thread1of1ForFork1___VERIFIER_assert_~expression, ~x$w_buff0~0, P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression, P1Thread1of1ForFork1_~arg.base, ~x$w_buff1~0, ~x$w_buff1_used~0, ~x$w_buff0_used~0] because there is no mapped edge [2019-12-07 17:17:45,408 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L807-1-->L809: Formula: (and (= (store |v_#length_14| |v_ULTIMATE.start_main_~#t2030~0.base_9| 4) |v_#length_13|) (= |v_ULTIMATE.start_main_~#t2030~0.offset_8| 0) (= |v_#valid_27| (store |v_#valid_28| |v_ULTIMATE.start_main_~#t2030~0.base_9| 1)) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t2030~0.base_9|) (not (= 0 |v_ULTIMATE.start_main_~#t2030~0.base_9|)) (= |v_#memory_int_9| (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2030~0.base_9| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2030~0.base_9|) |v_ULTIMATE.start_main_~#t2030~0.offset_8| 2))) (= 0 (select |v_#valid_28| |v_ULTIMATE.start_main_~#t2030~0.base_9|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_28|, #memory_int=|v_#memory_int_10|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_~#t2030~0.base=|v_ULTIMATE.start_main_~#t2030~0.base_9|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_27|, #memory_int=|v_#memory_int_9|, ULTIMATE.start_main_~#t2030~0.offset=|v_ULTIMATE.start_main_~#t2030~0.offset_8|, #length=|v_#length_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2030~0.base, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, ULTIMATE.start_main_~#t2030~0.offset, #length] because there is no mapped edge [2019-12-07 17:17:45,409 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L782-2-->L782-4: Formula: (let ((.cse1 (= (mod ~x$r_buff1_thd3~0_In-1669820522 256) 0)) (.cse0 (= (mod ~x$w_buff1_used~0_In-1669820522 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite15_Out-1669820522| ~x$w_buff1~0_In-1669820522) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~x~0_In-1669820522 |P2Thread1of1ForFork2_#t~ite15_Out-1669820522|)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-1669820522, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1669820522, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1669820522, ~x~0=~x~0_In-1669820522} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-1669820522|, ~x$w_buff1~0=~x$w_buff1~0_In-1669820522, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1669820522, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1669820522, ~x~0=~x~0_In-1669820522} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 17:17:45,409 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [695] [695] L782-4-->L783: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_6| v_~x~0_17) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_6|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_5|, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_5|, ~x~0=v_~x~0_17} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, P2Thread1of1ForFork2_#t~ite16, ~x~0] because there is no mapped edge [2019-12-07 17:17:45,409 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L783-->L783-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In929674980 256))) (.cse1 (= 0 (mod ~x$r_buff0_thd3~0_In929674980 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P2Thread1of1ForFork2_#t~ite17_Out929674980|)) (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In929674980 |P2Thread1of1ForFork2_#t~ite17_Out929674980|)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In929674980, ~x$w_buff0_used~0=~x$w_buff0_used~0_In929674980} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In929674980, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out929674980|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In929674980} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 17:17:45,410 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L784-->L784-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff1_used~0_In-980421816 256))) (.cse0 (= 0 (mod ~x$r_buff1_thd3~0_In-980421816 256))) (.cse2 (= (mod ~x$r_buff0_thd3~0_In-980421816 256) 0)) (.cse3 (= 0 (mod ~x$w_buff0_used~0_In-980421816 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite18_Out-980421816|)) (and (or .cse1 .cse0) (or .cse2 .cse3) (= ~x$w_buff1_used~0_In-980421816 |P2Thread1of1ForFork2_#t~ite18_Out-980421816|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-980421816, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-980421816, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-980421816, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-980421816} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-980421816, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-980421816, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-980421816, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-980421816|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-980421816} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 17:17:45,410 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L785-->L785-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In-380305941 256))) (.cse1 (= (mod ~x$w_buff0_used~0_In-380305941 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite19_Out-380305941| ~x$r_buff0_thd3~0_In-380305941)) (and (not .cse0) (not .cse1) (= 0 |P2Thread1of1ForFork2_#t~ite19_Out-380305941|)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-380305941, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-380305941} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-380305941, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-380305941|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-380305941} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 17:17:45,411 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [769] [769] L786-->L786-2: Formula: (let ((.cse3 (= 0 (mod ~x$r_buff1_thd3~0_In1996586475 256))) (.cse2 (= (mod ~x$w_buff1_used~0_In1996586475 256) 0)) (.cse0 (= (mod ~x$w_buff0_used~0_In1996586475 256) 0)) (.cse1 (= 0 (mod ~x$r_buff0_thd3~0_In1996586475 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork2_#t~ite20_Out1996586475| ~x$r_buff1_thd3~0_In1996586475)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= |P2Thread1of1ForFork2_#t~ite20_Out1996586475| 0)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In1996586475, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1996586475, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1996586475, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1996586475} OutVars{P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out1996586475|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1996586475, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1996586475, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1996586475, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1996586475} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 17:17:45,411 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L786-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74) (= |v_P2Thread1of1ForFork2_#t~ite20_54| v_~x$r_buff1_thd3~0_147)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_54|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_53|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_147, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~x$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 17:17:45,411 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L733-2-->L733-5: Formula: (let ((.cse0 (= |P0Thread1of1ForFork0_#t~ite3_Out1524172528| |P0Thread1of1ForFork0_#t~ite4_Out1524172528|)) (.cse1 (= (mod ~x$r_buff1_thd1~0_In1524172528 256) 0)) (.cse2 (= (mod ~x$w_buff1_used~0_In1524172528 256) 0))) (or (and .cse0 (= ~x~0_In1524172528 |P0Thread1of1ForFork0_#t~ite3_Out1524172528|) (or .cse1 .cse2)) (and .cse0 (not .cse1) (not .cse2) (= |P0Thread1of1ForFork0_#t~ite3_Out1524172528| ~x$w_buff1~0_In1524172528)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In1524172528, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1524172528, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In1524172528, ~x~0=~x~0_In1524172528} OutVars{P0Thread1of1ForFork0_#t~ite3=|P0Thread1of1ForFork0_#t~ite3_Out1524172528|, P0Thread1of1ForFork0_#t~ite4=|P0Thread1of1ForFork0_#t~ite4_Out1524172528|, ~x$w_buff1~0=~x$w_buff1~0_In1524172528, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1524172528, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In1524172528, ~x~0=~x~0_In1524172528} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite3, P0Thread1of1ForFork0_#t~ite4] because there is no mapped edge [2019-12-07 17:17:45,411 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [774] [774] L734-->L734-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd1~0_In-994691513 256))) (.cse0 (= (mod ~x$w_buff0_used~0_In-994691513 256) 0))) (or (and (not .cse0) (= |P0Thread1of1ForFork0_#t~ite5_Out-994691513| 0) (not .cse1)) (and (= ~x$w_buff0_used~0_In-994691513 |P0Thread1of1ForFork0_#t~ite5_Out-994691513|) (or .cse1 .cse0)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-994691513, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-994691513} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-994691513|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-994691513, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-994691513} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 17:17:45,411 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L735-->L735-2: Formula: (let ((.cse2 (= (mod ~x$w_buff0_used~0_In1328825479 256) 0)) (.cse3 (= 0 (mod ~x$r_buff0_thd1~0_In1328825479 256))) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In1328825479 256))) (.cse0 (= (mod ~x$r_buff1_thd1~0_In1328825479 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite6_Out1328825479| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (or .cse1 .cse0) (= |P0Thread1of1ForFork0_#t~ite6_Out1328825479| ~x$w_buff1_used~0_In1328825479)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In1328825479, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1328825479, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In1328825479, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1328825479} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out1328825479|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In1328825479, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1328825479, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In1328825479, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1328825479} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 17:17:45,412 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L736-->L736-2: Formula: (let ((.cse0 (= (mod ~x$r_buff0_thd1~0_In587091137 256) 0)) (.cse1 (= (mod ~x$w_buff0_used~0_In587091137 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite7_Out587091137| 0) (not .cse0) (not .cse1)) (and (= |P0Thread1of1ForFork0_#t~ite7_Out587091137| ~x$r_buff0_thd1~0_In587091137) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In587091137, ~x$w_buff0_used~0=~x$w_buff0_used~0_In587091137} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In587091137, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out587091137|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In587091137} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-12-07 17:17:45,412 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L737-->L737-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff1_used~0_In2143732912 256))) (.cse0 (= 0 (mod ~x$r_buff1_thd1~0_In2143732912 256))) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In2143732912 256))) (.cse3 (= 0 (mod ~x$r_buff0_thd1~0_In2143732912 256)))) (or (and (= |P0Thread1of1ForFork0_#t~ite8_Out2143732912| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P0Thread1of1ForFork0_#t~ite8_Out2143732912| ~x$r_buff1_thd1~0_In2143732912) (or .cse1 .cse0) (or .cse2 .cse3)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In2143732912, ~x$w_buff1_used~0=~x$w_buff1_used~0_In2143732912, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In2143732912, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2143732912} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In2143732912, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out2143732912|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In2143732912, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In2143732912, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2143732912} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 17:17:45,412 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L737-2-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= v_~x$r_buff1_thd1~0_126 |v_P0Thread1of1ForFork0_#t~ite8_34|) (= (+ v_~__unbuffered_cnt~0_63 1) v_~__unbuffered_cnt~0_62)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_63} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_33|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_62, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_126} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, ~x$r_buff1_thd1~0] because there is no mapped edge [2019-12-07 17:17:45,412 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L763-->L763-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In2037784181 256) 0)) (.cse1 (= 0 (mod ~x$r_buff0_thd2~0_In2037784181 256)))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out2037784181| 0)) (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In2037784181 |P1Thread1of1ForFork1_#t~ite11_Out2037784181|)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2037784181, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2037784181} OutVars{P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out2037784181|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2037784181, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2037784181} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 17:17:45,413 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [783] [783] L764-->L764-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-41014310 256))) (.cse0 (= 0 (mod ~x$r_buff0_thd2~0_In-41014310 256))) (.cse2 (= 0 (mod ~x$w_buff1_used~0_In-41014310 256))) (.cse3 (= 0 (mod ~x$r_buff1_thd2~0_In-41014310 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~x$w_buff1_used~0_In-41014310 |P1Thread1of1ForFork1_#t~ite12_Out-41014310|)) (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out-41014310|) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-41014310, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-41014310, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-41014310, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-41014310} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-41014310, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-41014310, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-41014310|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-41014310, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-41014310} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 17:17:45,413 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L765-->L766: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd2~0_In-1696183501 256))) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In-1696183501 256))) (.cse0 (= ~x$r_buff0_thd2~0_In-1696183501 ~x$r_buff0_thd2~0_Out-1696183501))) (or (and .cse0 .cse1) (and (not .cse2) (not .cse1) (= 0 ~x$r_buff0_thd2~0_Out-1696183501)) (and .cse2 .cse0))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1696183501, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1696183501} OutVars{P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-1696183501|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out-1696183501, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1696183501} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-12-07 17:17:45,413 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L766-->L766-2: Formula: (let ((.cse2 (= (mod ~x$w_buff0_used~0_In-1305240713 256) 0)) (.cse3 (= 0 (mod ~x$r_buff0_thd2~0_In-1305240713 256))) (.cse1 (= (mod ~x$r_buff1_thd2~0_In-1305240713 256) 0)) (.cse0 (= (mod ~x$w_buff1_used~0_In-1305240713 256) 0))) (or (and (= ~x$r_buff1_thd2~0_In-1305240713 |P1Thread1of1ForFork1_#t~ite14_Out-1305240713|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P1Thread1of1ForFork1_#t~ite14_Out-1305240713| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1305240713, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1305240713, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1305240713, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1305240713} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-1305240713, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1305240713, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1305240713, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-1305240713|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1305240713} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 17:17:45,413 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L766-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= v_~x$r_buff1_thd2~0_154 |v_P1Thread1of1ForFork1_#t~ite14_40|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_93 1) v_~__unbuffered_cnt~0_92)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_93, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_40|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_154, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_92, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_39|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 17:17:45,413 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [711] [711] L809-1-->L815: Formula: (and (= v_~main$tmp_guard0~0_6 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= 0 (mod v_~main$tmp_guard0~0_6 256)))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 17:17:45,414 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L815-2-->L815-5: Formula: (let ((.cse1 (= (mod ~x$r_buff1_thd0~0_In-1077227679 256) 0)) (.cse2 (= (mod ~x$w_buff1_used~0_In-1077227679 256) 0)) (.cse0 (= |ULTIMATE.start_main_#t~ite25_Out-1077227679| |ULTIMATE.start_main_#t~ite24_Out-1077227679|))) (or (and .cse0 (not .cse1) (= ~x$w_buff1~0_In-1077227679 |ULTIMATE.start_main_#t~ite24_Out-1077227679|) (not .cse2)) (and (or .cse1 .cse2) .cse0 (= |ULTIMATE.start_main_#t~ite24_Out-1077227679| ~x~0_In-1077227679)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-1077227679, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1077227679, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1077227679, ~x~0=~x~0_In-1077227679} OutVars{~x$w_buff1~0=~x$w_buff1~0_In-1077227679, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-1077227679|, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-1077227679|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1077227679, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1077227679, ~x~0=~x~0_In-1077227679} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 17:17:45,414 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L816-->L816-2: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd0~0_In-1296925237 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In-1296925237 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite26_Out-1296925237| 0) (not .cse1)) (and (= ~x$w_buff0_used~0_In-1296925237 |ULTIMATE.start_main_#t~ite26_Out-1296925237|) (or .cse1 .cse0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1296925237, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1296925237} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1296925237, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-1296925237|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1296925237} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 17:17:45,414 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L817-->L817-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In1797287797 256) 0)) (.cse1 (= (mod ~x$r_buff0_thd0~0_In1797287797 256) 0)) (.cse3 (= (mod ~x$w_buff1_used~0_In1797287797 256) 0)) (.cse2 (= (mod ~x$r_buff1_thd0~0_In1797287797 256) 0))) (or (and (= ~x$w_buff1_used~0_In1797287797 |ULTIMATE.start_main_#t~ite27_Out1797287797|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2))) (= 0 |ULTIMATE.start_main_#t~ite27_Out1797287797|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1797287797, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1797287797, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1797287797, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1797287797} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1797287797, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1797287797, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out1797287797|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1797287797, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1797287797} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 17:17:45,415 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [768] [768] L818-->L818-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd0~0_In869228053 256))) (.cse0 (= (mod ~x$w_buff0_used~0_In869228053 256) 0))) (or (and (= ~x$r_buff0_thd0~0_In869228053 |ULTIMATE.start_main_#t~ite28_Out869228053|) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite28_Out869228053|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In869228053, ~x$w_buff0_used~0=~x$w_buff0_used~0_In869228053} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In869228053, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out869228053|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In869228053} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 17:17:45,415 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L819-->L819-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff1_thd0~0_In-2081649921 256))) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In-2081649921 256))) (.cse2 (= 0 (mod ~x$r_buff0_thd0~0_In-2081649921 256))) (.cse3 (= 0 (mod ~x$w_buff0_used~0_In-2081649921 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite29_Out-2081649921| ~x$r_buff1_thd0~0_In-2081649921)) (and (= |ULTIMATE.start_main_#t~ite29_Out-2081649921| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-2081649921, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-2081649921, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-2081649921, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-2081649921} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-2081649921, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-2081649921|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-2081649921, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-2081649921, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-2081649921} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 17:17:45,417 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L831-->L832: Formula: (and (= v_~x$r_buff0_thd0~0_111 v_~x$r_buff0_thd0~0_110) (not (= (mod v_~weak$$choice2~0_23 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_111, ~weak$$choice2~0=v_~weak$$choice2~0_23} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_110, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_6|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_10|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_6|, ~weak$$choice2~0=v_~weak$$choice2~0_23} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 17:17:45,418 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L834-->L837-1: Formula: (and (= v_~x$mem_tmp~0_12 v_~x~0_151) (= (mod v_~main$tmp_guard1~0_14 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|) (= v_~x$flush_delayed~0_25 0) (not (= (mod v_~x$flush_delayed~0_26 256) 0))) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_26, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_14, ~x$mem_tmp~0=v_~x$mem_tmp~0_12} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_24|, ~x$flush_delayed~0=v_~x$flush_delayed~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_14, ~x$mem_tmp~0=v_~x$mem_tmp~0_12, ~x~0=v_~x~0_151, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ~x$flush_delayed~0, ~x~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 17:17:45,418 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L837-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 17:17:45,474 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_bdae239a-3fdf-4a6e-8196-337d13ba2380/bin/uautomizer/witness.graphml [2019-12-07 17:17:45,474 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 17:17:45,475 INFO L168 Benchmark]: Toolchain (without parser) took 89020.52 ms. Allocated memory was 1.0 GB in the beginning and 7.4 GB in the end (delta: 6.4 GB). Free memory was 940.9 MB in the beginning and 4.2 GB in the end (delta: -3.3 GB). Peak memory consumption was 3.1 GB. Max. memory is 11.5 GB. [2019-12-07 17:17:45,475 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 961.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 17:17:45,476 INFO L168 Benchmark]: CACSL2BoogieTranslator took 403.44 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 96.5 MB). Free memory was 940.9 MB in the beginning and 1.1 GB in the end (delta: -123.3 MB). Peak memory consumption was 18.3 MB. Max. memory is 11.5 GB. [2019-12-07 17:17:45,476 INFO L168 Benchmark]: Boogie Procedure Inliner took 42.15 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 17:17:45,476 INFO L168 Benchmark]: Boogie Preprocessor took 27.02 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 17:17:45,476 INFO L168 Benchmark]: RCFGBuilder took 402.11 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 56.8 MB). Peak memory consumption was 56.8 MB. Max. memory is 11.5 GB. [2019-12-07 17:17:45,477 INFO L168 Benchmark]: TraceAbstraction took 88073.33 ms. Allocated memory was 1.1 GB in the beginning and 7.4 GB in the end (delta: 6.3 GB). Free memory was 996.7 MB in the beginning and 4.2 GB in the end (delta: -3.2 GB). Peak memory consumption was 3.1 GB. Max. memory is 11.5 GB. [2019-12-07 17:17:45,477 INFO L168 Benchmark]: Witness Printer took 69.32 ms. Allocated memory is still 7.4 GB. Free memory was 4.2 GB in the beginning and 4.2 GB in the end (delta: 9.3 MB). Peak memory consumption was 9.3 MB. Max. memory is 11.5 GB. [2019-12-07 17:17:45,478 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 961.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 403.44 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 96.5 MB). Free memory was 940.9 MB in the beginning and 1.1 GB in the end (delta: -123.3 MB). Peak memory consumption was 18.3 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 42.15 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 27.02 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 402.11 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 56.8 MB). Peak memory consumption was 56.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 88073.33 ms. Allocated memory was 1.1 GB in the beginning and 7.4 GB in the end (delta: 6.3 GB). Free memory was 996.7 MB in the beginning and 4.2 GB in the end (delta: -3.2 GB). Peak memory consumption was 3.1 GB. Max. memory is 11.5 GB. * Witness Printer took 69.32 ms. Allocated memory is still 7.4 GB. Free memory was 4.2 GB in the beginning and 4.2 GB in the end (delta: 9.3 MB). Peak memory consumption was 9.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.0s, 174 ProgramPointsBefore, 94 ProgramPointsAfterwards, 211 TransitionsBefore, 106 TransitionsAfterwards, 17074 CoEnabledTransitionPairs, 8 FixpointIterations, 31 TrivialSequentialCompositions, 42 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 38 ConcurrentYvCompositions, 29 ChoiceCompositions, 6170 VarBasedMoverChecksPositive, 251 VarBasedMoverChecksNegative, 77 SemBasedMoverChecksPositive, 248 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.9s, 0 MoverChecksTotal, 87419 CheckedPairsTotal, 111 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L805] FCALL, FORK 0 pthread_create(&t2028, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L807] FCALL, FORK 0 pthread_create(&t2029, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L809] FCALL, FORK 0 pthread_create(&t2030, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L752] 2 x$r_buff1_thd0 = x$r_buff0_thd0 [L753] 2 x$r_buff1_thd1 = x$r_buff0_thd1 [L754] 2 x$r_buff1_thd2 = x$r_buff0_thd2 [L755] 2 x$r_buff1_thd3 = x$r_buff0_thd3 [L756] 2 x$r_buff0_thd2 = (_Bool)1 [L759] 2 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1, z=0] [L776] 3 __unbuffered_p2_EAX = y [L779] 3 z = 1 VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1, z=1] [L727] 1 z = 2 [L730] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1, z=2] [L782] 3 x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd3 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1, z=2] [L733] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1, z=2] [L783] 3 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$w_buff0_used [L762] EXPR 2 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd3 || x$w_buff1_used && x$r_buff1_thd3 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1, z=2] [L784] 3 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd3 || x$w_buff1_used && x$r_buff1_thd3 ? (_Bool)0 : x$w_buff1_used [L785] 3 x$r_buff0_thd3 = x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$r_buff0_thd3 [L733] 1 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L734] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L735] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L736] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L762] 2 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L763] 2 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L764] 2 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L815] EXPR 0 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1, z=2] [L815] 0 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L816] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L817] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L818] 0 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L819] 0 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L822] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L823] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L824] 0 x$flush_delayed = weak$$choice2 [L825] 0 x$mem_tmp = x VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1, z=2] [L826] EXPR 0 !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1, z=2] [L826] 0 x = !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) [L827] EXPR 0 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1, z=2] [L827] 0 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) [L828] EXPR 0 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1, z=2] [L828] 0 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) [L829] EXPR 0 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1, z=2] [L829] 0 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) [L830] EXPR 0 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1, z=2] [L830] 0 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L832] EXPR 0 weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1, z=2] [L832] 0 x$r_buff1_thd0 = weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L833] 0 main$tmp_guard1 = !(x == 2 && z == 2 && __unbuffered_p2_EAX == 1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1, z=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 165 locations, 2 error locations. Result: UNSAFE, OverallTime: 87.9s, OverallIterations: 30, TraceHistogramMax: 1, AutomataDifference: 18.2s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 5126 SDtfs, 4464 SDslu, 11491 SDs, 0 SdLazy, 8454 SolverSat, 291 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 295 GetRequests, 79 SyntacticMatches, 31 SemanticMatches, 185 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 283 ImplicationChecksByTransitivity, 1.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=212401occurred in iteration=5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 51.7s AutomataMinimizationTime, 29 MinimizatonAttempts, 230761 StatesRemovedByMinimization, 26 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.2s InterpolantComputationTime, 1468 NumberOfCodeBlocks, 1468 NumberOfCodeBlocksAsserted, 30 NumberOfCheckSat, 1371 ConstructedInterpolants, 0 QuantifiedInterpolants, 241942 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 29 InterpolantComputations, 29 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...