./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe011_pso.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_4739de85-2d8c-4d99-832b-63bd60268610/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_4739de85-2d8c-4d99-832b-63bd60268610/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_4739de85-2d8c-4d99-832b-63bd60268610/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_4739de85-2d8c-4d99-832b-63bd60268610/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe011_pso.oepc.i -s /tmp/vcloud-vcloud-master/worker/run_dir_4739de85-2d8c-4d99-832b-63bd60268610/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_4739de85-2d8c-4d99-832b-63bd60268610/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 75c872d5c26417c53e4cd302cde187f7b82f1644 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:59:29,354 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:59:29,356 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:59:29,363 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:59:29,363 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:59:29,364 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:59:29,365 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:59:29,366 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:59:29,368 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:59:29,368 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:59:29,369 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:59:29,370 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:59:29,370 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:59:29,370 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:59:29,371 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:59:29,372 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:59:29,372 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:59:29,373 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:59:29,374 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:59:29,376 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:59:29,377 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:59:29,378 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:59:29,378 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:59:29,379 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:59:29,381 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:59:29,381 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:59:29,381 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:59:29,381 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:59:29,382 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:59:29,382 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:59:29,383 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:59:29,383 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:59:29,383 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:59:29,384 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:59:29,384 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:59:29,385 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:59:29,385 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:59:29,385 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:59:29,385 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:59:29,386 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:59:29,386 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:59:29,387 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_4739de85-2d8c-4d99-832b-63bd60268610/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 18:59:29,396 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:59:29,397 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:59:29,397 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:59:29,397 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:59:29,398 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:59:29,398 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:59:29,398 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:59:29,398 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:59:29,398 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:59:29,398 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:59:29,398 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 18:59:29,399 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 18:59:29,399 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 18:59:29,399 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:59:29,399 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:59:29,399 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:59:29,399 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 18:59:29,400 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:59:29,400 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:59:29,400 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 18:59:29,400 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 18:59:29,400 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:59:29,400 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:59:29,400 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 18:59:29,401 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 18:59:29,401 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:59:29,401 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 18:59:29,401 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 18:59:29,401 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:59:29,401 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_4739de85-2d8c-4d99-832b-63bd60268610/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 75c872d5c26417c53e4cd302cde187f7b82f1644 [2019-12-07 18:59:29,500 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:59:29,509 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:59:29,511 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:59:29,512 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:59:29,512 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:59:29,513 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_4739de85-2d8c-4d99-832b-63bd60268610/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe011_pso.oepc.i [2019-12-07 18:59:29,552 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_4739de85-2d8c-4d99-832b-63bd60268610/bin/uautomizer/data/948fb14fc/af1ac80294054dc0a89881fd62744c14/FLAGb47c35a38 [2019-12-07 18:59:29,933 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:59:29,934 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_4739de85-2d8c-4d99-832b-63bd60268610/sv-benchmarks/c/pthread-wmm/safe011_pso.oepc.i [2019-12-07 18:59:29,945 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_4739de85-2d8c-4d99-832b-63bd60268610/bin/uautomizer/data/948fb14fc/af1ac80294054dc0a89881fd62744c14/FLAGb47c35a38 [2019-12-07 18:59:29,953 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_4739de85-2d8c-4d99-832b-63bd60268610/bin/uautomizer/data/948fb14fc/af1ac80294054dc0a89881fd62744c14 [2019-12-07 18:59:29,955 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:59:29,956 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:59:29,957 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:59:29,957 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:59:29,959 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:59:29,959 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:59:29" (1/1) ... [2019-12-07 18:59:29,961 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@43650ad2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:29, skipping insertion in model container [2019-12-07 18:59:29,961 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:59:29" (1/1) ... [2019-12-07 18:59:29,966 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:59:29,995 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:59:30,269 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:59:30,279 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:59:30,333 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:59:30,384 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:59:30,384 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30 WrapperNode [2019-12-07 18:59:30,384 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:59:30,385 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:59:30,385 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:59:30,385 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:59:30,390 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... [2019-12-07 18:59:30,408 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... [2019-12-07 18:59:30,434 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:59:30,435 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:59:30,435 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:59:30,435 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:59:30,443 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... [2019-12-07 18:59:30,443 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... [2019-12-07 18:59:30,447 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... [2019-12-07 18:59:30,448 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... [2019-12-07 18:59:30,457 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... [2019-12-07 18:59:30,461 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... [2019-12-07 18:59:30,465 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... [2019-12-07 18:59:30,468 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:59:30,468 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:59:30,468 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:59:30,468 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:59:30,469 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_4739de85-2d8c-4d99-832b-63bd60268610/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:59:30,508 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 18:59:30,508 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 18:59:30,508 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 18:59:30,508 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 18:59:30,508 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 18:59:30,508 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 18:59:30,508 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 18:59:30,509 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 18:59:30,509 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 18:59:30,509 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 18:59:30,509 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 18:59:30,509 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:59:30,509 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:59:30,510 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 18:59:30,883 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:59:30,883 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 18:59:30,884 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:59:30 BoogieIcfgContainer [2019-12-07 18:59:30,884 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:59:30,885 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 18:59:30,885 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 18:59:30,887 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 18:59:30,887 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 06:59:29" (1/3) ... [2019-12-07 18:59:30,888 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@49823819 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:59:30, skipping insertion in model container [2019-12-07 18:59:30,888 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (2/3) ... [2019-12-07 18:59:30,888 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@49823819 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:59:30, skipping insertion in model container [2019-12-07 18:59:30,888 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:59:30" (3/3) ... [2019-12-07 18:59:30,889 INFO L109 eAbstractionObserver]: Analyzing ICFG safe011_pso.oepc.i [2019-12-07 18:59:30,895 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 18:59:30,895 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 18:59:30,900 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 18:59:30,901 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 18:59:30,925 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,925 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,925 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,925 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,925 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,925 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,925 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,926 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,926 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,926 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,926 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,926 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,926 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,926 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,926 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,927 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,927 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,927 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,927 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,927 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,927 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,927 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,927 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,928 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,928 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,928 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,928 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,928 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,928 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,928 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,928 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,928 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,929 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,929 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,929 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,929 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,929 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,929 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,929 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,930 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,930 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,930 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,930 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,930 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,930 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,930 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,930 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,930 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,931 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,931 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,931 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,931 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,931 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,931 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,931 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,931 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,932 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,932 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,932 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,932 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,932 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,932 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,932 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,932 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,933 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,933 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,933 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,933 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,933 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,933 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,933 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,933 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,933 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,934 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,934 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,934 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,934 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,934 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,934 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,934 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,934 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,934 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,935 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,935 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,935 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,935 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,935 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,935 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,935 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,935 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,935 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,935 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,936 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,936 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,950 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 18:59:30,964 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 18:59:30,964 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 18:59:30,964 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 18:59:30,964 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:59:30,964 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:59:30,964 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 18:59:30,964 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:59:30,965 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 18:59:30,979 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 174 places, 211 transitions [2019-12-07 18:59:30,981 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 174 places, 211 transitions [2019-12-07 18:59:31,039 INFO L134 PetriNetUnfolder]: 47/208 cut-off events. [2019-12-07 18:59:31,039 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:59:31,049 INFO L76 FinitePrefix]: Finished finitePrefix Result has 218 conditions, 208 events. 47/208 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 573 event pairs. 9/168 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 18:59:31,064 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 174 places, 211 transitions [2019-12-07 18:59:31,094 INFO L134 PetriNetUnfolder]: 47/208 cut-off events. [2019-12-07 18:59:31,094 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:59:31,100 INFO L76 FinitePrefix]: Finished finitePrefix Result has 218 conditions, 208 events. 47/208 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 573 event pairs. 9/168 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 18:59:31,115 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 17114 [2019-12-07 18:59:31,116 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 18:59:33,940 WARN L192 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 85 [2019-12-07 18:59:34,030 INFO L206 etLargeBlockEncoding]: Checked pairs total: 86146 [2019-12-07 18:59:34,030 INFO L214 etLargeBlockEncoding]: Total number of compositions: 112 [2019-12-07 18:59:34,033 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 93 places, 104 transitions [2019-12-07 18:59:45,904 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 104862 states. [2019-12-07 18:59:45,906 INFO L276 IsEmpty]: Start isEmpty. Operand 104862 states. [2019-12-07 18:59:45,909 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-12-07 18:59:45,910 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:45,910 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-12-07 18:59:45,910 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:45,914 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:45,914 INFO L82 PathProgramCache]: Analyzing trace with hash 844471, now seen corresponding path program 1 times [2019-12-07 18:59:45,919 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:45,919 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243055245] [2019-12-07 18:59:45,919 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:46,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:46,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:46,056 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [243055245] [2019-12-07 18:59:46,056 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:46,056 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:59:46,057 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [588956963] [2019-12-07 18:59:46,060 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:59:46,060 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:46,068 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:59:46,069 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:59:46,070 INFO L87 Difference]: Start difference. First operand 104862 states. Second operand 3 states. [2019-12-07 18:59:46,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:46,868 INFO L93 Difference]: Finished difference Result 104560 states and 448162 transitions. [2019-12-07 18:59:46,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:59:46,869 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-12-07 18:59:46,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:47,445 INFO L225 Difference]: With dead ends: 104560 [2019-12-07 18:59:47,445 INFO L226 Difference]: Without dead ends: 102376 [2019-12-07 18:59:47,446 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:59:50,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102376 states. [2019-12-07 18:59:51,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102376 to 102376. [2019-12-07 18:59:51,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102376 states. [2019-12-07 18:59:52,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102376 states to 102376 states and 439244 transitions. [2019-12-07 18:59:52,415 INFO L78 Accepts]: Start accepts. Automaton has 102376 states and 439244 transitions. Word has length 3 [2019-12-07 18:59:52,415 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:52,415 INFO L462 AbstractCegarLoop]: Abstraction has 102376 states and 439244 transitions. [2019-12-07 18:59:52,416 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:59:52,416 INFO L276 IsEmpty]: Start isEmpty. Operand 102376 states and 439244 transitions. [2019-12-07 18:59:52,419 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 18:59:52,419 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:52,419 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:52,419 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:52,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:52,420 INFO L82 PathProgramCache]: Analyzing trace with hash 205437058, now seen corresponding path program 1 times [2019-12-07 18:59:52,420 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:52,420 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2058246092] [2019-12-07 18:59:52,420 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:52,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:52,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:52,482 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2058246092] [2019-12-07 18:59:52,483 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:52,483 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:59:52,483 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [158885010] [2019-12-07 18:59:52,484 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:59:52,484 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:52,484 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:59:52,484 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:59:52,484 INFO L87 Difference]: Start difference. First operand 102376 states and 439244 transitions. Second operand 4 states. [2019-12-07 18:59:53,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:53,359 INFO L93 Difference]: Finished difference Result 164490 states and 678436 transitions. [2019-12-07 18:59:53,360 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:59:53,360 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 18:59:53,360 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:53,835 INFO L225 Difference]: With dead ends: 164490 [2019-12-07 18:59:53,835 INFO L226 Difference]: Without dead ends: 164441 [2019-12-07 18:59:53,836 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:00,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 164441 states. [2019-12-07 19:00:02,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 164441 to 148513. [2019-12-07 19:00:02,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148513 states. [2019-12-07 19:00:02,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148513 states to 148513 states and 619831 transitions. [2019-12-07 19:00:02,520 INFO L78 Accepts]: Start accepts. Automaton has 148513 states and 619831 transitions. Word has length 11 [2019-12-07 19:00:02,520 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:02,520 INFO L462 AbstractCegarLoop]: Abstraction has 148513 states and 619831 transitions. [2019-12-07 19:00:02,521 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 19:00:02,521 INFO L276 IsEmpty]: Start isEmpty. Operand 148513 states and 619831 transitions. [2019-12-07 19:00:02,525 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 19:00:02,525 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:02,525 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:02,525 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:02,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:02,525 INFO L82 PathProgramCache]: Analyzing trace with hash 1045519438, now seen corresponding path program 1 times [2019-12-07 19:00:02,525 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:02,526 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [296956065] [2019-12-07 19:00:02,526 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:02,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:02,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:02,574 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [296956065] [2019-12-07 19:00:02,574 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:02,574 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:02,574 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [763739885] [2019-12-07 19:00:02,575 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 19:00:02,575 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:02,575 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 19:00:02,575 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 19:00:02,575 INFO L87 Difference]: Start difference. First operand 148513 states and 619831 transitions. Second operand 4 states. [2019-12-07 19:00:04,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:04,050 INFO L93 Difference]: Finished difference Result 211896 states and 864765 transitions. [2019-12-07 19:00:04,050 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 19:00:04,050 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 19:00:04,051 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:04,561 INFO L225 Difference]: With dead ends: 211896 [2019-12-07 19:00:04,562 INFO L226 Difference]: Without dead ends: 211833 [2019-12-07 19:00:04,562 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:11,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211833 states. [2019-12-07 19:00:13,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211833 to 178183. [2019-12-07 19:00:13,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178183 states. [2019-12-07 19:00:14,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178183 states to 178183 states and 738846 transitions. [2019-12-07 19:00:14,167 INFO L78 Accepts]: Start accepts. Automaton has 178183 states and 738846 transitions. Word has length 13 [2019-12-07 19:00:14,167 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:14,168 INFO L462 AbstractCegarLoop]: Abstraction has 178183 states and 738846 transitions. [2019-12-07 19:00:14,168 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 19:00:14,168 INFO L276 IsEmpty]: Start isEmpty. Operand 178183 states and 738846 transitions. [2019-12-07 19:00:14,170 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 19:00:14,170 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:14,170 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:14,170 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:14,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:14,170 INFO L82 PathProgramCache]: Analyzing trace with hash 31849685, now seen corresponding path program 1 times [2019-12-07 19:00:14,170 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:14,171 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775372037] [2019-12-07 19:00:14,171 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:14,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:14,217 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:14,218 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775372037] [2019-12-07 19:00:14,218 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:14,218 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:14,218 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1022818642] [2019-12-07 19:00:14,218 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 19:00:14,218 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:14,218 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 19:00:14,219 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 19:00:14,219 INFO L87 Difference]: Start difference. First operand 178183 states and 738846 transitions. Second operand 4 states. [2019-12-07 19:00:15,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:15,706 INFO L93 Difference]: Finished difference Result 223676 states and 918481 transitions. [2019-12-07 19:00:15,707 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 19:00:15,707 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 19:00:15,707 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:16,263 INFO L225 Difference]: With dead ends: 223676 [2019-12-07 19:00:16,263 INFO L226 Difference]: Without dead ends: 223676 [2019-12-07 19:00:16,264 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:23,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223676 states. [2019-12-07 19:00:26,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223676 to 188328. [2019-12-07 19:00:26,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 188328 states. [2019-12-07 19:00:26,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188328 states to 188328 states and 781098 transitions. [2019-12-07 19:00:26,897 INFO L78 Accepts]: Start accepts. Automaton has 188328 states and 781098 transitions. Word has length 13 [2019-12-07 19:00:26,897 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:26,897 INFO L462 AbstractCegarLoop]: Abstraction has 188328 states and 781098 transitions. [2019-12-07 19:00:26,897 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 19:00:26,897 INFO L276 IsEmpty]: Start isEmpty. Operand 188328 states and 781098 transitions. [2019-12-07 19:00:26,916 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 19:00:26,916 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:26,917 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:26,917 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:26,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:26,917 INFO L82 PathProgramCache]: Analyzing trace with hash 227208446, now seen corresponding path program 1 times [2019-12-07 19:00:26,917 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:26,917 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [880300407] [2019-12-07 19:00:26,917 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:26,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:26,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:26,975 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [880300407] [2019-12-07 19:00:26,975 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:26,975 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 19:00:26,975 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [222996792] [2019-12-07 19:00:26,975 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:00:26,975 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:26,976 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:00:26,976 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:26,976 INFO L87 Difference]: Start difference. First operand 188328 states and 781098 transitions. Second operand 5 states. [2019-12-07 19:00:28,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:28,367 INFO L93 Difference]: Finished difference Result 280213 states and 1136950 transitions. [2019-12-07 19:00:28,368 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 19:00:28,368 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 19:00:28,368 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:29,093 INFO L225 Difference]: With dead ends: 280213 [2019-12-07 19:00:29,093 INFO L226 Difference]: Without dead ends: 280150 [2019-12-07 19:00:29,093 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 19:00:35,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 280150 states. [2019-12-07 19:00:40,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 280150 to 199900. [2019-12-07 19:00:40,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 199900 states. [2019-12-07 19:00:41,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199900 states to 199900 states and 824830 transitions. [2019-12-07 19:00:41,423 INFO L78 Accepts]: Start accepts. Automaton has 199900 states and 824830 transitions. Word has length 19 [2019-12-07 19:00:41,424 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:41,424 INFO L462 AbstractCegarLoop]: Abstraction has 199900 states and 824830 transitions. [2019-12-07 19:00:41,424 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:00:41,424 INFO L276 IsEmpty]: Start isEmpty. Operand 199900 states and 824830 transitions. [2019-12-07 19:00:41,438 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 19:00:41,438 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:41,438 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:41,438 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:41,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:41,439 INFO L82 PathProgramCache]: Analyzing trace with hash -1539749953, now seen corresponding path program 1 times [2019-12-07 19:00:41,439 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:41,439 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1730116161] [2019-12-07 19:00:41,439 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:41,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:41,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:41,492 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1730116161] [2019-12-07 19:00:41,492 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:41,492 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 19:00:41,492 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1307151698] [2019-12-07 19:00:41,493 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:00:41,493 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:41,493 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:00:41,493 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:41,493 INFO L87 Difference]: Start difference. First operand 199900 states and 824830 transitions. Second operand 5 states. [2019-12-07 19:00:43,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:43,392 INFO L93 Difference]: Finished difference Result 304999 states and 1233542 transitions. [2019-12-07 19:00:43,393 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 19:00:43,393 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 19:00:43,393 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:44,154 INFO L225 Difference]: With dead ends: 304999 [2019-12-07 19:00:44,154 INFO L226 Difference]: Without dead ends: 304859 [2019-12-07 19:00:44,155 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 19:00:50,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 304859 states. [2019-12-07 19:00:53,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 304859 to 208169. [2019-12-07 19:00:53,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 208169 states. [2019-12-07 19:00:54,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 208169 states to 208169 states and 858647 transitions. [2019-12-07 19:00:54,832 INFO L78 Accepts]: Start accepts. Automaton has 208169 states and 858647 transitions. Word has length 19 [2019-12-07 19:00:54,832 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:54,832 INFO L462 AbstractCegarLoop]: Abstraction has 208169 states and 858647 transitions. [2019-12-07 19:00:54,833 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:00:54,833 INFO L276 IsEmpty]: Start isEmpty. Operand 208169 states and 858647 transitions. [2019-12-07 19:00:54,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 19:00:54,846 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:54,846 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:54,846 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:54,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:54,846 INFO L82 PathProgramCache]: Analyzing trace with hash -737624118, now seen corresponding path program 1 times [2019-12-07 19:00:54,846 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:54,847 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [204269790] [2019-12-07 19:00:54,847 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:54,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:54,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:54,884 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [204269790] [2019-12-07 19:00:54,884 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:54,885 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 19:00:54,885 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [355875476] [2019-12-07 19:00:54,885 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:00:54,885 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:54,885 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:00:54,886 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:54,886 INFO L87 Difference]: Start difference. First operand 208169 states and 858647 transitions. Second operand 5 states. [2019-12-07 19:00:56,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:56,457 INFO L93 Difference]: Finished difference Result 307935 states and 1248366 transitions. [2019-12-07 19:00:56,457 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 19:00:56,458 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 19:00:56,458 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:57,770 INFO L225 Difference]: With dead ends: 307935 [2019-12-07 19:00:57,770 INFO L226 Difference]: Without dead ends: 307872 [2019-12-07 19:00:57,771 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 19:01:06,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 307872 states. [2019-12-07 19:01:10,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 307872 to 225509. [2019-12-07 19:01:10,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 225509 states. [2019-12-07 19:01:10,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225509 states to 225509 states and 928979 transitions. [2019-12-07 19:01:10,889 INFO L78 Accepts]: Start accepts. Automaton has 225509 states and 928979 transitions. Word has length 19 [2019-12-07 19:01:10,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:10,889 INFO L462 AbstractCegarLoop]: Abstraction has 225509 states and 928979 transitions. [2019-12-07 19:01:10,890 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:01:10,890 INFO L276 IsEmpty]: Start isEmpty. Operand 225509 states and 928979 transitions. [2019-12-07 19:01:10,941 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 19:01:10,941 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:10,941 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:10,941 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:10,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:10,942 INFO L82 PathProgramCache]: Analyzing trace with hash -451334861, now seen corresponding path program 1 times [2019-12-07 19:01:10,942 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:10,942 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529058226] [2019-12-07 19:01:10,942 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:10,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:11,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:11,004 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1529058226] [2019-12-07 19:01:11,004 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:11,004 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 19:01:11,004 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [920680924] [2019-12-07 19:01:11,004 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 19:01:11,004 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:11,004 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 19:01:11,004 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 19:01:11,005 INFO L87 Difference]: Start difference. First operand 225509 states and 928979 transitions. Second operand 6 states. [2019-12-07 19:01:13,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:13,115 INFO L93 Difference]: Finished difference Result 271732 states and 1106088 transitions. [2019-12-07 19:01:13,115 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 19:01:13,115 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2019-12-07 19:01:13,116 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:13,821 INFO L225 Difference]: With dead ends: 271732 [2019-12-07 19:01:13,821 INFO L226 Difference]: Without dead ends: 271592 [2019-12-07 19:01:13,821 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=81, Invalid=191, Unknown=0, NotChecked=0, Total=272 [2019-12-07 19:01:19,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271592 states. [2019-12-07 19:01:22,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271592 to 186079. [2019-12-07 19:01:22,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186079 states. [2019-12-07 19:01:22,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186079 states to 186079 states and 770012 transitions. [2019-12-07 19:01:22,978 INFO L78 Accepts]: Start accepts. Automaton has 186079 states and 770012 transitions. Word has length 25 [2019-12-07 19:01:22,978 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:22,978 INFO L462 AbstractCegarLoop]: Abstraction has 186079 states and 770012 transitions. [2019-12-07 19:01:22,978 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 19:01:22,978 INFO L276 IsEmpty]: Start isEmpty. Operand 186079 states and 770012 transitions. [2019-12-07 19:01:23,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 19:01:23,039 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:23,039 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:23,039 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:23,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:23,039 INFO L82 PathProgramCache]: Analyzing trace with hash 955559875, now seen corresponding path program 1 times [2019-12-07 19:01:23,039 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:23,039 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1032747783] [2019-12-07 19:01:23,039 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:23,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:23,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:23,062 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1032747783] [2019-12-07 19:01:23,062 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:23,062 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 19:01:23,063 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1089903287] [2019-12-07 19:01:23,063 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:01:23,063 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:23,063 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:01:23,063 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:01:23,063 INFO L87 Difference]: Start difference. First operand 186079 states and 770012 transitions. Second operand 3 states. [2019-12-07 19:01:24,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:24,355 INFO L93 Difference]: Finished difference Result 224357 states and 927664 transitions. [2019-12-07 19:01:24,356 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:01:24,356 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 19:01:24,356 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:24,946 INFO L225 Difference]: With dead ends: 224357 [2019-12-07 19:01:24,946 INFO L226 Difference]: Without dead ends: 224357 [2019-12-07 19:01:24,947 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:01:32,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224357 states. [2019-12-07 19:01:35,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224357 to 210135. [2019-12-07 19:01:35,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 210135 states. [2019-12-07 19:01:35,922 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 210135 states to 210135 states and 871503 transitions. [2019-12-07 19:01:35,923 INFO L78 Accepts]: Start accepts. Automaton has 210135 states and 871503 transitions. Word has length 27 [2019-12-07 19:01:35,923 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:35,923 INFO L462 AbstractCegarLoop]: Abstraction has 210135 states and 871503 transitions. [2019-12-07 19:01:35,923 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:01:35,923 INFO L276 IsEmpty]: Start isEmpty. Operand 210135 states and 871503 transitions. [2019-12-07 19:01:35,982 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 19:01:35,982 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:35,982 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:35,982 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:35,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:35,982 INFO L82 PathProgramCache]: Analyzing trace with hash 1083631384, now seen corresponding path program 1 times [2019-12-07 19:01:35,982 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:35,982 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317046582] [2019-12-07 19:01:35,983 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:35,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:36,004 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:36,004 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317046582] [2019-12-07 19:01:36,005 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:36,005 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:01:36,005 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1844363752] [2019-12-07 19:01:36,005 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:01:36,005 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:36,005 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:01:36,005 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:01:36,005 INFO L87 Difference]: Start difference. First operand 210135 states and 871503 transitions. Second operand 3 states. [2019-12-07 19:01:36,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:36,128 INFO L93 Difference]: Finished difference Result 43496 states and 141400 transitions. [2019-12-07 19:01:36,128 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:01:36,128 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 19:01:36,128 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:36,188 INFO L225 Difference]: With dead ends: 43496 [2019-12-07 19:01:36,188 INFO L226 Difference]: Without dead ends: 43496 [2019-12-07 19:01:36,189 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:01:36,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43496 states. [2019-12-07 19:01:36,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43496 to 43496. [2019-12-07 19:01:36,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43496 states. [2019-12-07 19:01:36,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43496 states to 43496 states and 141400 transitions. [2019-12-07 19:01:36,878 INFO L78 Accepts]: Start accepts. Automaton has 43496 states and 141400 transitions. Word has length 27 [2019-12-07 19:01:36,878 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:36,878 INFO L462 AbstractCegarLoop]: Abstraction has 43496 states and 141400 transitions. [2019-12-07 19:01:36,878 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:01:36,878 INFO L276 IsEmpty]: Start isEmpty. Operand 43496 states and 141400 transitions. [2019-12-07 19:01:36,896 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2019-12-07 19:01:36,896 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:36,896 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:36,896 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:36,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:36,896 INFO L82 PathProgramCache]: Analyzing trace with hash -42031042, now seen corresponding path program 1 times [2019-12-07 19:01:36,896 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:36,896 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1060033973] [2019-12-07 19:01:36,896 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:36,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:36,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:36,933 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1060033973] [2019-12-07 19:01:36,933 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:36,933 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 19:01:36,933 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [101777498] [2019-12-07 19:01:36,933 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 19:01:36,933 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:36,933 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 19:01:36,933 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 19:01:36,934 INFO L87 Difference]: Start difference. First operand 43496 states and 141400 transitions. Second operand 4 states. [2019-12-07 19:01:36,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:36,958 INFO L93 Difference]: Finished difference Result 7852 states and 21076 transitions. [2019-12-07 19:01:36,959 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 19:01:36,959 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 39 [2019-12-07 19:01:36,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:36,965 INFO L225 Difference]: With dead ends: 7852 [2019-12-07 19:01:36,965 INFO L226 Difference]: Without dead ends: 7852 [2019-12-07 19:01:36,965 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 19:01:36,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7852 states. [2019-12-07 19:01:37,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7852 to 7740. [2019-12-07 19:01:37,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7740 states. [2019-12-07 19:01:37,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7740 states to 7740 states and 20756 transitions. [2019-12-07 19:01:37,051 INFO L78 Accepts]: Start accepts. Automaton has 7740 states and 20756 transitions. Word has length 39 [2019-12-07 19:01:37,052 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:37,052 INFO L462 AbstractCegarLoop]: Abstraction has 7740 states and 20756 transitions. [2019-12-07 19:01:37,052 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 19:01:37,052 INFO L276 IsEmpty]: Start isEmpty. Operand 7740 states and 20756 transitions. [2019-12-07 19:01:37,057 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 19:01:37,057 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:37,057 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:37,057 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:37,057 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:37,057 INFO L82 PathProgramCache]: Analyzing trace with hash -1565012212, now seen corresponding path program 1 times [2019-12-07 19:01:37,058 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:37,058 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1187987763] [2019-12-07 19:01:37,058 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:37,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:37,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:37,113 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1187987763] [2019-12-07 19:01:37,113 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:37,113 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 19:01:37,113 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2010589039] [2019-12-07 19:01:37,113 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:01:37,113 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:37,114 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:01:37,114 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:01:37,114 INFO L87 Difference]: Start difference. First operand 7740 states and 20756 transitions. Second operand 5 states. [2019-12-07 19:01:37,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:37,136 INFO L93 Difference]: Finished difference Result 5049 states and 14453 transitions. [2019-12-07 19:01:37,136 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 19:01:37,137 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-12-07 19:01:37,137 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:37,141 INFO L225 Difference]: With dead ends: 5049 [2019-12-07 19:01:37,141 INFO L226 Difference]: Without dead ends: 5049 [2019-12-07 19:01:37,141 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:01:37,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5049 states. [2019-12-07 19:01:37,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5049 to 4685. [2019-12-07 19:01:37,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4685 states. [2019-12-07 19:01:37,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4685 states to 4685 states and 13469 transitions. [2019-12-07 19:01:37,198 INFO L78 Accepts]: Start accepts. Automaton has 4685 states and 13469 transitions. Word has length 51 [2019-12-07 19:01:37,199 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:37,199 INFO L462 AbstractCegarLoop]: Abstraction has 4685 states and 13469 transitions. [2019-12-07 19:01:37,199 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:01:37,199 INFO L276 IsEmpty]: Start isEmpty. Operand 4685 states and 13469 transitions. [2019-12-07 19:01:37,202 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 19:01:37,202 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:37,202 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:37,202 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:37,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:37,202 INFO L82 PathProgramCache]: Analyzing trace with hash 1173172274, now seen corresponding path program 1 times [2019-12-07 19:01:37,202 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:37,202 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1738162136] [2019-12-07 19:01:37,202 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:37,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:37,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:37,247 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1738162136] [2019-12-07 19:01:37,247 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:37,247 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 19:01:37,247 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1083293944] [2019-12-07 19:01:37,247 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:01:37,247 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:37,248 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:01:37,248 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:01:37,248 INFO L87 Difference]: Start difference. First operand 4685 states and 13469 transitions. Second operand 3 states. [2019-12-07 19:01:37,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:37,287 INFO L93 Difference]: Finished difference Result 4689 states and 13463 transitions. [2019-12-07 19:01:37,288 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:01:37,288 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 19:01:37,288 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:37,292 INFO L225 Difference]: With dead ends: 4689 [2019-12-07 19:01:37,292 INFO L226 Difference]: Without dead ends: 4689 [2019-12-07 19:01:37,292 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:01:37,311 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4689 states. [2019-12-07 19:01:37,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4689 to 4681. [2019-12-07 19:01:37,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4681 states. [2019-12-07 19:01:37,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4681 states to 4681 states and 13455 transitions. [2019-12-07 19:01:37,348 INFO L78 Accepts]: Start accepts. Automaton has 4681 states and 13455 transitions. Word has length 65 [2019-12-07 19:01:37,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:37,348 INFO L462 AbstractCegarLoop]: Abstraction has 4681 states and 13455 transitions. [2019-12-07 19:01:37,349 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:01:37,349 INFO L276 IsEmpty]: Start isEmpty. Operand 4681 states and 13455 transitions. [2019-12-07 19:01:37,352 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 19:01:37,352 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:37,352 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:37,352 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:37,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:37,352 INFO L82 PathProgramCache]: Analyzing trace with hash 1163492121, now seen corresponding path program 1 times [2019-12-07 19:01:37,352 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:37,352 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246617090] [2019-12-07 19:01:37,352 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:37,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:37,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:37,414 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [246617090] [2019-12-07 19:01:37,414 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:37,414 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 19:01:37,414 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992966683] [2019-12-07 19:01:37,415 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:01:37,415 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:37,415 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:01:37,415 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:01:37,415 INFO L87 Difference]: Start difference. First operand 4681 states and 13455 transitions. Second operand 5 states. [2019-12-07 19:01:37,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:37,604 INFO L93 Difference]: Finished difference Result 7105 states and 20244 transitions. [2019-12-07 19:01:37,604 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 19:01:37,604 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 65 [2019-12-07 19:01:37,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:37,610 INFO L225 Difference]: With dead ends: 7105 [2019-12-07 19:01:37,610 INFO L226 Difference]: Without dead ends: 7105 [2019-12-07 19:01:37,610 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 19:01:37,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7105 states. [2019-12-07 19:01:37,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7105 to 6291. [2019-12-07 19:01:37,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6291 states. [2019-12-07 19:01:37,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6291 states to 6291 states and 18000 transitions. [2019-12-07 19:01:37,694 INFO L78 Accepts]: Start accepts. Automaton has 6291 states and 18000 transitions. Word has length 65 [2019-12-07 19:01:37,694 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:37,694 INFO L462 AbstractCegarLoop]: Abstraction has 6291 states and 18000 transitions. [2019-12-07 19:01:37,694 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:01:37,694 INFO L276 IsEmpty]: Start isEmpty. Operand 6291 states and 18000 transitions. [2019-12-07 19:01:37,698 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 19:01:37,699 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:37,699 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:37,699 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:37,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:37,699 INFO L82 PathProgramCache]: Analyzing trace with hash -2061317327, now seen corresponding path program 2 times [2019-12-07 19:01:37,699 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:37,699 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [795326215] [2019-12-07 19:01:37,699 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:37,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:38,021 WARN L192 SmtUtils]: Spent 289.00 ms on a formula simplification that was a NOOP. DAG size: 12 [2019-12-07 19:01:38,068 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:38,068 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [795326215] [2019-12-07 19:01:38,068 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:38,068 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 19:01:38,068 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1933019113] [2019-12-07 19:01:38,069 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:01:38,069 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:38,069 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:01:38,069 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:01:38,069 INFO L87 Difference]: Start difference. First operand 6291 states and 18000 transitions. Second operand 5 states. [2019-12-07 19:01:38,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:38,264 INFO L93 Difference]: Finished difference Result 9383 states and 26609 transitions. [2019-12-07 19:01:38,264 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 19:01:38,264 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 65 [2019-12-07 19:01:38,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:38,272 INFO L225 Difference]: With dead ends: 9383 [2019-12-07 19:01:38,273 INFO L226 Difference]: Without dead ends: 9383 [2019-12-07 19:01:38,273 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 19:01:38,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9383 states. [2019-12-07 19:01:38,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9383 to 7346. [2019-12-07 19:01:38,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7346 states. [2019-12-07 19:01:38,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7346 states to 7346 states and 21123 transitions. [2019-12-07 19:01:38,371 INFO L78 Accepts]: Start accepts. Automaton has 7346 states and 21123 transitions. Word has length 65 [2019-12-07 19:01:38,371 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:38,371 INFO L462 AbstractCegarLoop]: Abstraction has 7346 states and 21123 transitions. [2019-12-07 19:01:38,371 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:01:38,371 INFO L276 IsEmpty]: Start isEmpty. Operand 7346 states and 21123 transitions. [2019-12-07 19:01:38,376 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 19:01:38,376 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:38,376 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:38,376 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:38,376 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:38,376 INFO L82 PathProgramCache]: Analyzing trace with hash -1650424373, now seen corresponding path program 3 times [2019-12-07 19:01:38,376 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:38,376 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [275305032] [2019-12-07 19:01:38,377 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:38,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:38,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:38,431 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [275305032] [2019-12-07 19:01:38,431 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:38,431 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 19:01:38,432 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [381396729] [2019-12-07 19:01:38,432 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 19:01:38,432 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:38,432 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 19:01:38,432 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 19:01:38,432 INFO L87 Difference]: Start difference. First operand 7346 states and 21123 transitions. Second operand 6 states. [2019-12-07 19:01:38,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:38,709 INFO L93 Difference]: Finished difference Result 11509 states and 32952 transitions. [2019-12-07 19:01:38,710 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 19:01:38,710 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 65 [2019-12-07 19:01:38,710 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:38,719 INFO L225 Difference]: With dead ends: 11509 [2019-12-07 19:01:38,719 INFO L226 Difference]: Without dead ends: 11509 [2019-12-07 19:01:38,720 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-12-07 19:01:38,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11509 states. [2019-12-07 19:01:38,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11509 to 8187. [2019-12-07 19:01:38,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8187 states. [2019-12-07 19:01:38,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8187 states to 8187 states and 23603 transitions. [2019-12-07 19:01:38,840 INFO L78 Accepts]: Start accepts. Automaton has 8187 states and 23603 transitions. Word has length 65 [2019-12-07 19:01:38,840 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:38,840 INFO L462 AbstractCegarLoop]: Abstraction has 8187 states and 23603 transitions. [2019-12-07 19:01:38,840 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 19:01:38,840 INFO L276 IsEmpty]: Start isEmpty. Operand 8187 states and 23603 transitions. [2019-12-07 19:01:38,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 19:01:38,846 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:38,846 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:38,846 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:38,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:38,846 INFO L82 PathProgramCache]: Analyzing trace with hash 2063456247, now seen corresponding path program 4 times [2019-12-07 19:01:38,846 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:38,846 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1151870396] [2019-12-07 19:01:38,846 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:38,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:38,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:38,924 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1151870396] [2019-12-07 19:01:38,924 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:38,924 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 19:01:38,925 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [630137097] [2019-12-07 19:01:38,925 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 19:01:38,925 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:38,925 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 19:01:38,925 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 19:01:38,925 INFO L87 Difference]: Start difference. First operand 8187 states and 23603 transitions. Second operand 7 states. [2019-12-07 19:01:39,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:39,390 INFO L93 Difference]: Finished difference Result 11659 states and 33360 transitions. [2019-12-07 19:01:39,390 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 19:01:39,390 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 65 [2019-12-07 19:01:39,390 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:39,400 INFO L225 Difference]: With dead ends: 11659 [2019-12-07 19:01:39,400 INFO L226 Difference]: Without dead ends: 11659 [2019-12-07 19:01:39,400 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 11 SyntacticMatches, 3 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 46 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=72, Invalid=200, Unknown=0, NotChecked=0, Total=272 [2019-12-07 19:01:39,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11659 states. [2019-12-07 19:01:39,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11659 to 8348. [2019-12-07 19:01:39,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8348 states. [2019-12-07 19:01:39,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8348 states to 8348 states and 24042 transitions. [2019-12-07 19:01:39,521 INFO L78 Accepts]: Start accepts. Automaton has 8348 states and 24042 transitions. Word has length 65 [2019-12-07 19:01:39,521 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:39,521 INFO L462 AbstractCegarLoop]: Abstraction has 8348 states and 24042 transitions. [2019-12-07 19:01:39,521 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 19:01:39,521 INFO L276 IsEmpty]: Start isEmpty. Operand 8348 states and 24042 transitions. [2019-12-07 19:01:39,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 19:01:39,527 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:39,527 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:39,527 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:39,527 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:39,527 INFO L82 PathProgramCache]: Analyzing trace with hash 695487673, now seen corresponding path program 5 times [2019-12-07 19:01:39,527 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:39,527 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1591260775] [2019-12-07 19:01:39,528 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:39,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:39,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:39,585 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1591260775] [2019-12-07 19:01:39,585 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:39,585 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 19:01:39,585 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1144783808] [2019-12-07 19:01:39,585 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 19:01:39,586 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:39,586 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 19:01:39,586 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 19:01:39,586 INFO L87 Difference]: Start difference. First operand 8348 states and 24042 transitions. Second operand 6 states. [2019-12-07 19:01:39,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:39,929 INFO L93 Difference]: Finished difference Result 11624 states and 32873 transitions. [2019-12-07 19:01:39,930 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 19:01:39,930 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 65 [2019-12-07 19:01:39,930 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:39,939 INFO L225 Difference]: With dead ends: 11624 [2019-12-07 19:01:39,939 INFO L226 Difference]: Without dead ends: 11624 [2019-12-07 19:01:39,940 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2019-12-07 19:01:39,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11624 states. [2019-12-07 19:01:40,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11624 to 8586. [2019-12-07 19:01:40,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8586 states. [2019-12-07 19:01:40,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8586 states to 8586 states and 24721 transitions. [2019-12-07 19:01:40,068 INFO L78 Accepts]: Start accepts. Automaton has 8586 states and 24721 transitions. Word has length 65 [2019-12-07 19:01:40,068 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:40,068 INFO L462 AbstractCegarLoop]: Abstraction has 8586 states and 24721 transitions. [2019-12-07 19:01:40,068 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 19:01:40,068 INFO L276 IsEmpty]: Start isEmpty. Operand 8586 states and 24721 transitions. [2019-12-07 19:01:40,074 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 19:01:40,074 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:40,074 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:40,074 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:40,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:40,075 INFO L82 PathProgramCache]: Analyzing trace with hash -1544002871, now seen corresponding path program 6 times [2019-12-07 19:01:40,075 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:40,075 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1420037513] [2019-12-07 19:01:40,075 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:40,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:40,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:40,117 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1420037513] [2019-12-07 19:01:40,117 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:40,117 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:01:40,117 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [351958196] [2019-12-07 19:01:40,117 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:01:40,117 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:40,118 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:01:40,118 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:01:40,118 INFO L87 Difference]: Start difference. First operand 8586 states and 24721 transitions. Second operand 3 states. [2019-12-07 19:01:40,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:40,157 INFO L93 Difference]: Finished difference Result 8586 states and 24720 transitions. [2019-12-07 19:01:40,158 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:01:40,158 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 19:01:40,158 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:40,165 INFO L225 Difference]: With dead ends: 8586 [2019-12-07 19:01:40,165 INFO L226 Difference]: Without dead ends: 8586 [2019-12-07 19:01:40,165 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:01:40,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8586 states. [2019-12-07 19:01:40,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8586 to 6339. [2019-12-07 19:01:40,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6339 states. [2019-12-07 19:01:40,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6339 states to 6339 states and 18436 transitions. [2019-12-07 19:01:40,259 INFO L78 Accepts]: Start accepts. Automaton has 6339 states and 18436 transitions. Word has length 65 [2019-12-07 19:01:40,259 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:40,259 INFO L462 AbstractCegarLoop]: Abstraction has 6339 states and 18436 transitions. [2019-12-07 19:01:40,259 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:01:40,259 INFO L276 IsEmpty]: Start isEmpty. Operand 6339 states and 18436 transitions. [2019-12-07 19:01:40,263 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 19:01:40,264 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:40,264 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:40,264 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:40,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:40,264 INFO L82 PathProgramCache]: Analyzing trace with hash -68576263, now seen corresponding path program 1 times [2019-12-07 19:01:40,264 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:40,264 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [670947819] [2019-12-07 19:01:40,264 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:40,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:40,338 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:40,338 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [670947819] [2019-12-07 19:01:40,338 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:40,339 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 19:01:40,339 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1339513530] [2019-12-07 19:01:40,339 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 19:01:40,339 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:40,339 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 19:01:40,339 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 19:01:40,339 INFO L87 Difference]: Start difference. First operand 6339 states and 18436 transitions. Second operand 7 states. [2019-12-07 19:01:40,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:40,426 INFO L93 Difference]: Finished difference Result 12441 states and 36633 transitions. [2019-12-07 19:01:40,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 19:01:40,427 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 66 [2019-12-07 19:01:40,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:40,435 INFO L225 Difference]: With dead ends: 12441 [2019-12-07 19:01:40,435 INFO L226 Difference]: Without dead ends: 7643 [2019-12-07 19:01:40,435 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=61, Unknown=0, NotChecked=0, Total=90 [2019-12-07 19:01:40,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7643 states. [2019-12-07 19:01:40,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7643 to 5851. [2019-12-07 19:01:40,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5851 states. [2019-12-07 19:01:40,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5851 states to 5851 states and 17000 transitions. [2019-12-07 19:01:40,520 INFO L78 Accepts]: Start accepts. Automaton has 5851 states and 17000 transitions. Word has length 66 [2019-12-07 19:01:40,521 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:40,521 INFO L462 AbstractCegarLoop]: Abstraction has 5851 states and 17000 transitions. [2019-12-07 19:01:40,521 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 19:01:40,521 INFO L276 IsEmpty]: Start isEmpty. Operand 5851 states and 17000 transitions. [2019-12-07 19:01:40,525 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 19:01:40,525 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:40,525 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:40,525 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:40,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:40,526 INFO L82 PathProgramCache]: Analyzing trace with hash 1020623707, now seen corresponding path program 2 times [2019-12-07 19:01:40,526 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:40,526 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [857658805] [2019-12-07 19:01:40,526 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:40,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:40,556 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:40,556 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [857658805] [2019-12-07 19:01:40,556 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:40,557 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:01:40,557 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [454342095] [2019-12-07 19:01:40,557 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:01:40,557 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:40,557 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:01:40,557 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:01:40,557 INFO L87 Difference]: Start difference. First operand 5851 states and 17000 transitions. Second operand 3 states. [2019-12-07 19:01:40,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:40,575 INFO L93 Difference]: Finished difference Result 5329 states and 15095 transitions. [2019-12-07 19:01:40,576 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:01:40,576 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 19:01:40,576 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:40,580 INFO L225 Difference]: With dead ends: 5329 [2019-12-07 19:01:40,580 INFO L226 Difference]: Without dead ends: 5329 [2019-12-07 19:01:40,581 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:01:40,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5329 states. [2019-12-07 19:01:40,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5329 to 5132. [2019-12-07 19:01:40,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5132 states. [2019-12-07 19:01:40,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5132 states to 5132 states and 14536 transitions. [2019-12-07 19:01:40,645 INFO L78 Accepts]: Start accepts. Automaton has 5132 states and 14536 transitions. Word has length 66 [2019-12-07 19:01:40,645 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:40,645 INFO L462 AbstractCegarLoop]: Abstraction has 5132 states and 14536 transitions. [2019-12-07 19:01:40,645 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:01:40,646 INFO L276 IsEmpty]: Start isEmpty. Operand 5132 states and 14536 transitions. [2019-12-07 19:01:40,649 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 19:01:40,649 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:40,649 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:40,649 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:40,649 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:40,649 INFO L82 PathProgramCache]: Analyzing trace with hash 897051641, now seen corresponding path program 1 times [2019-12-07 19:01:40,650 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:40,650 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [587275089] [2019-12-07 19:01:40,650 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:40,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:40,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:40,675 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [587275089] [2019-12-07 19:01:40,675 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:40,675 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:01:40,675 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707574526] [2019-12-07 19:01:40,675 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:01:40,675 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:40,675 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:01:40,676 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:01:40,676 INFO L87 Difference]: Start difference. First operand 5132 states and 14536 transitions. Second operand 3 states. [2019-12-07 19:01:40,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:40,692 INFO L93 Difference]: Finished difference Result 4742 states and 13187 transitions. [2019-12-07 19:01:40,692 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:01:40,692 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 19:01:40,692 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:40,696 INFO L225 Difference]: With dead ends: 4742 [2019-12-07 19:01:40,696 INFO L226 Difference]: Without dead ends: 4742 [2019-12-07 19:01:40,696 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:01:40,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4742 states. [2019-12-07 19:01:40,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4742 to 4177. [2019-12-07 19:01:40,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4177 states. [2019-12-07 19:01:40,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4177 states to 4177 states and 11620 transitions. [2019-12-07 19:01:40,749 INFO L78 Accepts]: Start accepts. Automaton has 4177 states and 11620 transitions. Word has length 67 [2019-12-07 19:01:40,749 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:40,749 INFO L462 AbstractCegarLoop]: Abstraction has 4177 states and 11620 transitions. [2019-12-07 19:01:40,749 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:01:40,749 INFO L276 IsEmpty]: Start isEmpty. Operand 4177 states and 11620 transitions. [2019-12-07 19:01:40,752 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 19:01:40,752 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:40,752 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:40,752 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:40,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:40,753 INFO L82 PathProgramCache]: Analyzing trace with hash -829052917, now seen corresponding path program 1 times [2019-12-07 19:01:40,753 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:40,753 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [757257875] [2019-12-07 19:01:40,753 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:40,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:40,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:40,989 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [757257875] [2019-12-07 19:01:40,989 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:40,989 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 19:01:40,989 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [93666716] [2019-12-07 19:01:40,990 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 19:01:40,990 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:40,990 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 19:01:40,990 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=173, Unknown=0, NotChecked=0, Total=210 [2019-12-07 19:01:40,990 INFO L87 Difference]: Start difference. First operand 4177 states and 11620 transitions. Second operand 15 states. [2019-12-07 19:01:41,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:41,770 INFO L93 Difference]: Finished difference Result 8274 states and 22865 transitions. [2019-12-07 19:01:41,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-12-07 19:01:41,770 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 68 [2019-12-07 19:01:41,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:41,777 INFO L225 Difference]: With dead ends: 8274 [2019-12-07 19:01:41,777 INFO L226 Difference]: Without dead ends: 7722 [2019-12-07 19:01:41,778 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 305 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=311, Invalid=1171, Unknown=0, NotChecked=0, Total=1482 [2019-12-07 19:01:41,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7722 states. [2019-12-07 19:01:41,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7722 to 5815. [2019-12-07 19:01:41,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5815 states. [2019-12-07 19:01:41,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5815 states to 5815 states and 16081 transitions. [2019-12-07 19:01:41,853 INFO L78 Accepts]: Start accepts. Automaton has 5815 states and 16081 transitions. Word has length 68 [2019-12-07 19:01:41,853 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:41,853 INFO L462 AbstractCegarLoop]: Abstraction has 5815 states and 16081 transitions. [2019-12-07 19:01:41,853 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 19:01:41,853 INFO L276 IsEmpty]: Start isEmpty. Operand 5815 states and 16081 transitions. [2019-12-07 19:01:41,856 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 19:01:41,857 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:41,857 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:41,857 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:41,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:41,857 INFO L82 PathProgramCache]: Analyzing trace with hash 226058755, now seen corresponding path program 2 times [2019-12-07 19:01:41,857 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:41,857 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [542871208] [2019-12-07 19:01:41,857 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:41,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:42,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:42,007 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [542871208] [2019-12-07 19:01:42,008 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:42,008 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 19:01:42,008 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2053990260] [2019-12-07 19:01:42,008 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 19:01:42,008 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:42,008 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 19:01:42,008 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=128, Unknown=0, NotChecked=0, Total=156 [2019-12-07 19:01:42,009 INFO L87 Difference]: Start difference. First operand 5815 states and 16081 transitions. Second operand 13 states. [2019-12-07 19:01:42,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:42,394 INFO L93 Difference]: Finished difference Result 9608 states and 26450 transitions. [2019-12-07 19:01:42,394 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 19:01:42,394 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 68 [2019-12-07 19:01:42,395 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:42,402 INFO L225 Difference]: With dead ends: 9608 [2019-12-07 19:01:42,402 INFO L226 Difference]: Without dead ends: 9116 [2019-12-07 19:01:42,403 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 109 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=137, Invalid=565, Unknown=0, NotChecked=0, Total=702 [2019-12-07 19:01:42,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9116 states. [2019-12-07 19:01:42,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9116 to 5994. [2019-12-07 19:01:42,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5994 states. [2019-12-07 19:01:42,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5994 states to 5994 states and 16578 transitions. [2019-12-07 19:01:42,487 INFO L78 Accepts]: Start accepts. Automaton has 5994 states and 16578 transitions. Word has length 68 [2019-12-07 19:01:42,487 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:42,487 INFO L462 AbstractCegarLoop]: Abstraction has 5994 states and 16578 transitions. [2019-12-07 19:01:42,487 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 19:01:42,487 INFO L276 IsEmpty]: Start isEmpty. Operand 5994 states and 16578 transitions. [2019-12-07 19:01:42,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 19:01:42,490 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:42,491 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:42,491 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:42,491 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:42,491 INFO L82 PathProgramCache]: Analyzing trace with hash 1101405001, now seen corresponding path program 3 times [2019-12-07 19:01:42,491 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:42,491 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [807596060] [2019-12-07 19:01:42,491 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:42,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:42,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:42,689 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [807596060] [2019-12-07 19:01:42,689 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:42,689 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 19:01:42,689 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1811123077] [2019-12-07 19:01:42,689 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 19:01:42,690 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:42,690 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 19:01:42,690 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=173, Unknown=0, NotChecked=0, Total=210 [2019-12-07 19:01:42,690 INFO L87 Difference]: Start difference. First operand 5994 states and 16578 transitions. Second operand 15 states. [2019-12-07 19:01:43,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:43,761 INFO L93 Difference]: Finished difference Result 10419 states and 28833 transitions. [2019-12-07 19:01:43,761 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-12-07 19:01:43,761 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 68 [2019-12-07 19:01:43,761 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:43,769 INFO L225 Difference]: With dead ends: 10419 [2019-12-07 19:01:43,770 INFO L226 Difference]: Without dead ends: 10275 [2019-12-07 19:01:43,770 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 157 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=163, Invalid=707, Unknown=0, NotChecked=0, Total=870 [2019-12-07 19:01:43,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10275 states. [2019-12-07 19:01:43,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10275 to 6087. [2019-12-07 19:01:43,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6087 states. [2019-12-07 19:01:43,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6087 states to 6087 states and 16855 transitions. [2019-12-07 19:01:43,860 INFO L78 Accepts]: Start accepts. Automaton has 6087 states and 16855 transitions. Word has length 68 [2019-12-07 19:01:43,860 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:43,860 INFO L462 AbstractCegarLoop]: Abstraction has 6087 states and 16855 transitions. [2019-12-07 19:01:43,860 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 19:01:43,860 INFO L276 IsEmpty]: Start isEmpty. Operand 6087 states and 16855 transitions. [2019-12-07 19:01:43,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 19:01:43,864 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:43,864 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:43,864 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:43,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:43,865 INFO L82 PathProgramCache]: Analyzing trace with hash 1851838847, now seen corresponding path program 4 times [2019-12-07 19:01:43,865 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:43,865 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [975687146] [2019-12-07 19:01:43,865 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:43,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 19:01:43,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 19:01:43,941 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 19:01:43,941 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 19:01:43,944 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] ULTIMATE.startENTRY-->L805: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t2031~0.base_21| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t2031~0.base_21|) |v_ULTIMATE.start_main_~#t2031~0.offset_17| 0)) |v_#memory_int_21|) (= v_~__unbuffered_cnt~0_140 0) (= 0 v_~z$flush_delayed~0_34) (= v_~z$r_buff1_thd0~0_308 0) (= v_~z$w_buff1_used~0_516 0) (= v_~z$r_buff1_thd1~0_190 0) (= v_~z$read_delayed~0_8 0) (= v_~z$w_buff0~0_342 0) (= v_~main$tmp_guard1~0_21 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t2031~0.base_21|) (= v_~z$read_delayed_var~0.offset_7 0) (= |v_ULTIMATE.start_main_~#t2031~0.offset_17| 0) (< 0 |v_#StackHeapBarrier_18|) (= v_~z$r_buff1_thd2~0_206 0) (= v_~y~0_34 0) (= 0 |v_#NULL.base_4|) (= 0 v_~z$r_buff0_thd3~0_140) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$r_buff0_thd1~0_226 0) (= v_~main$tmp_guard0~0_21 0) (= v_~weak$$choice2~0_109 0) (= v_~z$mem_tmp~0_19 0) (= v_~z$r_buff0_thd0~0_374 0) (= |v_#NULL.offset_4| 0) (= 0 v_~z$r_buff1_thd3~0_196) (= v_~z$r_buff0_thd2~0_140 0) (= 0 v_~__unbuffered_p2_EAX~0_36) (= (select .cse0 |v_ULTIMATE.start_main_~#t2031~0.base_21|) 0) (= v_~z$w_buff0_used~0_875 0) (= 0 v_~weak$$choice0~0_13) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t2031~0.base_21| 4)) (= (store .cse0 |v_ULTIMATE.start_main_~#t2031~0.base_21| 1) |v_#valid_53|) (= v_~z$w_buff1~0_249 0) (= 0 v_~x~0_138) (= v_~z~0_182 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_22|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_21|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_27|, ULTIMATE.start_main_~#t2032~0.base=|v_ULTIMATE.start_main_~#t2032~0.base_20|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_206, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_39|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_29|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_49|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_47|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_25|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_45|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_32|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_374, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_36, ULTIMATE.start_main_~#t2031~0.offset=|v_ULTIMATE.start_main_~#t2031~0.offset_17|, ~z$mem_tmp~0=v_~z$mem_tmp~0_19, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_43|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_516, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_52|, ~z$flush_delayed~0=v_~z$flush_delayed~0_34, ULTIMATE.start_main_~#t2033~0.base=|v_ULTIMATE.start_main_~#t2033~0.base_20|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_111|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_32|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_190, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_140, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_140, ~x~0=v_~x~0_138, ULTIMATE.start_main_~#t2033~0.offset=|v_ULTIMATE.start_main_~#t2033~0.offset_16|, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_33|, ~z$read_delayed~0=v_~z$read_delayed~0_8, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_31|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_29|, ~z$w_buff1~0=v_~z$w_buff1~0_249, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_121|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_17|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_25|, ULTIMATE.start_main_~#t2032~0.offset=|v_ULTIMATE.start_main_~#t2032~0.offset_17|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_41|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_31|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_308, ~y~0=v_~y~0_34, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_140, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_10|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_21|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_875, ~z$w_buff0~0=v_~z$w_buff0~0_342, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_196, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_25|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_54|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_21, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_59|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_38|, ULTIMATE.start_main_~#t2031~0.base=|v_ULTIMATE.start_main_~#t2031~0.base_21|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_32|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_21|, ~z~0=v_~z~0_182, ~weak$$choice2~0=v_~weak$$choice2~0_109, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_226} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t2032~0.base, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t2031~0.offset, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_~#t2033~0.base, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_~#t2033~0.offset, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_~#t2032~0.offset, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_~#t2031~0.base, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 19:01:43,944 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L805-1-->L807: Formula: (and (= |v_#valid_34| (store |v_#valid_35| |v_ULTIMATE.start_main_~#t2032~0.base_12| 1)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2032~0.base_12| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2032~0.base_12|) |v_ULTIMATE.start_main_~#t2032~0.offset_11| 1)) |v_#memory_int_13|) (= 0 (select |v_#valid_35| |v_ULTIMATE.start_main_~#t2032~0.base_12|)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t2032~0.base_12|) (not (= 0 |v_ULTIMATE.start_main_~#t2032~0.base_12|)) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t2032~0.base_12| 4)) (= |v_ULTIMATE.start_main_~#t2032~0.offset_11| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_6|, ULTIMATE.start_main_~#t2032~0.base=|v_ULTIMATE.start_main_~#t2032~0.base_12|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_13|, #length=|v_#length_17|, ULTIMATE.start_main_~#t2032~0.offset=|v_ULTIMATE.start_main_~#t2032~0.offset_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t2032~0.base, #valid, #memory_int, #length, ULTIMATE.start_main_~#t2032~0.offset] because there is no mapped edge [2019-12-07 19:01:43,944 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] P0ENTRY-->L4-3: Formula: (and (= v_~z$w_buff0_used~0_226 v_~z$w_buff1_used~0_114) (= v_P0Thread1of1ForFork0_~arg.base_20 |v_P0Thread1of1ForFork0_#in~arg.base_22|) (= 2 v_~z$w_buff0~0_55) (= v_~z$w_buff0~0_56 v_~z$w_buff1~0_53) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_24 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_20|) (= (ite (not (and (not (= 0 (mod v_~z$w_buff0_used~0_225 256))) (not (= 0 (mod v_~z$w_buff1_used~0_114 256))))) 1 0) |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_20|) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_24 0)) (= v_P0Thread1of1ForFork0_~arg.offset_20 |v_P0Thread1of1ForFork0_#in~arg.offset_22|) (= v_~z$w_buff0_used~0_225 1)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_226, ~z$w_buff0~0=v_~z$w_buff0~0_56, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_22|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_225, ~z$w_buff0~0=v_~z$w_buff0~0_55, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_24, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_114, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_22|, ~z$w_buff1~0=v_~z$w_buff1~0_53, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_20, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_20|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_20} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 19:01:43,945 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L807-1-->L809: Formula: (and (= |v_#memory_int_9| (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2033~0.base_9| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2033~0.base_9|) |v_ULTIMATE.start_main_~#t2033~0.offset_8| 2))) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t2033~0.base_9|) (= (select |v_#valid_28| |v_ULTIMATE.start_main_~#t2033~0.base_9|) 0) (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t2033~0.base_9| 4)) (= |v_#valid_27| (store |v_#valid_28| |v_ULTIMATE.start_main_~#t2033~0.base_9| 1)) (not (= 0 |v_ULTIMATE.start_main_~#t2033~0.base_9|)) (= |v_ULTIMATE.start_main_~#t2033~0.offset_8| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_28|, #memory_int=|v_#memory_int_10|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_27|, #memory_int=|v_#memory_int_9|, #length=|v_#length_13|, ULTIMATE.start_main_~#t2033~0.base=|v_ULTIMATE.start_main_~#t2033~0.base_9|, ULTIMATE.start_main_~#t2033~0.offset=|v_ULTIMATE.start_main_~#t2033~0.offset_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t2033~0.base, ULTIMATE.start_main_~#t2033~0.offset] because there is no mapped edge [2019-12-07 19:01:43,945 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L743-->L743-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd1~0_In497331916 256) 0)) (.cse0 (= (mod ~z$w_buff0_used~0_In497331916 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite5_Out497331916| 0) (not .cse0) (not .cse1)) (and (= |P0Thread1of1ForFork0_#t~ite5_Out497331916| ~z$w_buff0_used~0_In497331916) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In497331916, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In497331916} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out497331916|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In497331916, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In497331916} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 19:01:43,946 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L744-->L744-2: Formula: (let ((.cse1 (= (mod ~z$r_buff1_thd1~0_In138640008 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In138640008 256))) (.cse3 (= 0 (mod ~z$r_buff0_thd1~0_In138640008 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In138640008 256)))) (or (and (= |P0Thread1of1ForFork0_#t~ite6_Out138640008| ~z$w_buff1_used~0_In138640008) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P0Thread1of1ForFork0_#t~ite6_Out138640008| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In138640008, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In138640008, ~z$w_buff1_used~0=~z$w_buff1_used~0_In138640008, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In138640008} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out138640008|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In138640008, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In138640008, ~z$w_buff1_used~0=~z$w_buff1_used~0_In138640008, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In138640008} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 19:01:43,947 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L745-->L746: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd1~0_In1933115398 256))) (.cse2 (= ~z$r_buff0_thd1~0_In1933115398 ~z$r_buff0_thd1~0_Out1933115398)) (.cse0 (= (mod ~z$w_buff0_used~0_In1933115398 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 ~z$r_buff0_thd1~0_Out1933115398)) (and .cse1 .cse2) (and .cse2 .cse0))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1933115398, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1933115398} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1933115398, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out1933115398|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out1933115398} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 19:01:43,947 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L746-->L746-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff1_thd1~0_In-1861045831 256))) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-1861045831 256))) (.cse0 (= (mod ~z$r_buff0_thd1~0_In-1861045831 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1861045831 256)))) (or (and (= |P0Thread1of1ForFork0_#t~ite8_Out-1861045831| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (= |P0Thread1of1ForFork0_#t~ite8_Out-1861045831| ~z$r_buff1_thd1~0_In-1861045831) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1861045831, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1861045831, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1861045831, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1861045831} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1861045831, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-1861045831|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1861045831, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1861045831, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1861045831} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 19:01:43,947 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L746-2-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_44 1) v_~__unbuffered_cnt~0_43) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_63 |v_P0Thread1of1ForFork0_#t~ite8_26|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_44} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_25|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_63, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_43} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 19:01:43,947 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L762-2-->L762-5: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In866179867 256) 0)) (.cse2 (= 0 (mod ~z$r_buff1_thd2~0_In866179867 256))) (.cse0 (= |P1Thread1of1ForFork1_#t~ite10_Out866179867| |P1Thread1of1ForFork1_#t~ite9_Out866179867|))) (or (and (= ~z~0_In866179867 |P1Thread1of1ForFork1_#t~ite9_Out866179867|) .cse0 (or .cse1 .cse2)) (and (not .cse1) (not .cse2) .cse0 (= ~z$w_buff1~0_In866179867 |P1Thread1of1ForFork1_#t~ite9_Out866179867|)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In866179867, ~z$w_buff1_used~0=~z$w_buff1_used~0_In866179867, ~z$w_buff1~0=~z$w_buff1~0_In866179867, ~z~0=~z~0_In866179867} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out866179867|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In866179867, ~z$w_buff1_used~0=~z$w_buff1_used~0_In866179867, P1Thread1of1ForFork1_#t~ite10=|P1Thread1of1ForFork1_#t~ite10_Out866179867|, ~z$w_buff1~0=~z$w_buff1~0_In866179867, ~z~0=~z~0_In866179867} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10] because there is no mapped edge [2019-12-07 19:01:43,947 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L782-2-->L782-4: Formula: (let ((.cse1 (= (mod ~z$r_buff1_thd3~0_In-168215761 256) 0)) (.cse0 (= (mod ~z$w_buff1_used~0_In-168215761 256) 0))) (or (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In-168215761 |P2Thread1of1ForFork2_#t~ite15_Out-168215761|)) (and (= ~z~0_In-168215761 |P2Thread1of1ForFork2_#t~ite15_Out-168215761|) (or .cse1 .cse0)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-168215761, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-168215761, ~z$w_buff1~0=~z$w_buff1~0_In-168215761, ~z~0=~z~0_In-168215761} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-168215761|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-168215761, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-168215761, ~z$w_buff1~0=~z$w_buff1~0_In-168215761, ~z~0=~z~0_In-168215761} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 19:01:43,947 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L782-4-->L783: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~z~0_20) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, ~z~0=v_~z~0_20, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_11|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~z~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 19:01:43,948 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [774] [774] L783-->L783-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd3~0_In-1840070820 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1840070820 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P2Thread1of1ForFork2_#t~ite17_Out-1840070820|)) (and (= ~z$w_buff0_used~0_In-1840070820 |P2Thread1of1ForFork2_#t~ite17_Out-1840070820|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1840070820, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1840070820} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1840070820, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1840070820, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out-1840070820|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 19:01:43,948 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L784-->L784-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In1994600450 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In1994600450 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In1994600450 256))) (.cse3 (= (mod ~z$w_buff1_used~0_In1994600450 256) 0))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite18_Out1994600450|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$w_buff1_used~0_In1994600450 |P2Thread1of1ForFork2_#t~ite18_Out1994600450|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1994600450, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1994600450, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1994600450, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1994600450} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1994600450, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1994600450, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1994600450, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1994600450, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out1994600450|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 19:01:43,948 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L785-->L785-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-2375935 256))) (.cse1 (= (mod ~z$r_buff0_thd3~0_In-2375935 256) 0))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite19_Out-2375935|) (not .cse0) (not .cse1)) (and (= ~z$r_buff0_thd3~0_In-2375935 |P2Thread1of1ForFork2_#t~ite19_Out-2375935|) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-2375935, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-2375935} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-2375935, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-2375935, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-2375935|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 19:01:43,948 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L786-->L786-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In2106500356 256))) (.cse0 (= (mod ~z$r_buff0_thd3~0_In2106500356 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In2106500356 256) 0)) (.cse3 (= 0 (mod ~z$r_buff1_thd3~0_In2106500356 256)))) (or (and (= ~z$r_buff1_thd3~0_In2106500356 |P2Thread1of1ForFork2_#t~ite20_Out2106500356|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork2_#t~ite20_Out2106500356|) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In2106500356, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In2106500356, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2106500356, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In2106500356} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In2106500356, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out2106500356|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In2106500356, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2106500356, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In2106500356} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 19:01:43,948 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L786-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_54 (+ v_~__unbuffered_cnt~0_55 1)) (= |v_P2Thread1of1ForFork2_#t~ite20_30| v_~z$r_buff1_thd3~0_67)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_30|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_29|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_67, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 19:01:43,949 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L763-->L763-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In1713412744 256) 0)) (.cse1 (= (mod ~z$r_buff0_thd2~0_In1713412744 256) 0))) (or (and (= |P1Thread1of1ForFork1_#t~ite11_Out1713412744| ~z$w_buff0_used~0_In1713412744) (or .cse0 .cse1)) (and (not .cse0) (= 0 |P1Thread1of1ForFork1_#t~ite11_Out1713412744|) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1713412744, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1713412744} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1713412744, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out1713412744|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1713412744} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 19:01:43,949 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L764-->L764-2: Formula: (let ((.cse3 (= 0 (mod ~z$w_buff1_used~0_In-1515790868 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd2~0_In-1515790868 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In-1515790868 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1515790868 256)))) (or (and (= |P1Thread1of1ForFork1_#t~ite12_Out-1515790868| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (= |P1Thread1of1ForFork1_#t~ite12_Out-1515790868| ~z$w_buff1_used~0_In-1515790868) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1515790868, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1515790868, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1515790868, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1515790868} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1515790868, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1515790868, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1515790868, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-1515790868|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1515790868} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 19:01:43,949 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L765-->L765-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In948749047 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In948749047 256)))) (or (and (or .cse0 .cse1) (= ~z$r_buff0_thd2~0_In948749047 |P1Thread1of1ForFork1_#t~ite13_Out948749047|)) (and (= 0 |P1Thread1of1ForFork1_#t~ite13_Out948749047|) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In948749047, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In948749047} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In948749047, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out948749047|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In948749047} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 19:01:43,950 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L766-->L766-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd2~0_In-1015547216 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In-1015547216 256) 0)) (.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In-1015547216 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1015547216 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite14_Out-1015547216|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse0 .cse1) (= ~z$r_buff1_thd2~0_In-1015547216 |P1Thread1of1ForFork1_#t~ite14_Out-1015547216|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1015547216, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1015547216, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1015547216, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1015547216} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1015547216, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1015547216, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1015547216, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-1015547216|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1015547216} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 19:01:43,950 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L766-2-->P1EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_61 1) v_~__unbuffered_cnt~0_60) (= |v_P1Thread1of1ForFork1_#t~ite14_30| v_~z$r_buff1_thd2~0_84) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_61, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_30|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_84, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_60, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_29|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 19:01:43,950 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L809-1-->L815: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (= v_~main$tmp_guard0~0_8 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_18) 1 0) 0) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_18} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_7|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_18, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 19:01:43,950 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L815-2-->L815-5: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In-462132085 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-462132085 256) 0)) (.cse2 (= |ULTIMATE.start_main_#t~ite24_Out-462132085| |ULTIMATE.start_main_#t~ite25_Out-462132085|))) (or (and (not .cse0) (not .cse1) .cse2 (= |ULTIMATE.start_main_#t~ite24_Out-462132085| ~z$w_buff1~0_In-462132085)) (and (or .cse0 .cse1) .cse2 (= |ULTIMATE.start_main_#t~ite24_Out-462132085| ~z~0_In-462132085)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-462132085, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-462132085, ~z$w_buff1~0=~z$w_buff1~0_In-462132085, ~z~0=~z~0_In-462132085} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-462132085, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-462132085|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-462132085, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-462132085|, ~z$w_buff1~0=~z$w_buff1~0_In-462132085, ~z~0=~z~0_In-462132085} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 19:01:43,950 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [768] [768] L816-->L816-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-1385175578 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-1385175578 256)))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite26_Out-1385175578|) (not .cse1)) (and (or .cse1 .cse0) (= ~z$w_buff0_used~0_In-1385175578 |ULTIMATE.start_main_#t~ite26_Out-1385175578|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1385175578, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1385175578} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1385175578, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1385175578, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-1385175578|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 19:01:43,951 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L817-->L817-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd0~0_In-1274498138 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-1274498138 256) 0)) (.cse2 (= 0 (mod ~z$r_buff1_thd0~0_In-1274498138 256))) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In-1274498138 256)))) (or (and (= 0 |ULTIMATE.start_main_#t~ite27_Out-1274498138|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In-1274498138 |ULTIMATE.start_main_#t~ite27_Out-1274498138|) (or .cse2 .cse3)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1274498138, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1274498138, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1274498138, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1274498138} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1274498138, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1274498138, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1274498138, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1274498138, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-1274498138|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 19:01:43,951 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L818-->L818-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd0~0_In-135639886 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In-135639886 256)))) (or (and (= |ULTIMATE.start_main_#t~ite28_Out-135639886| ~z$r_buff0_thd0~0_In-135639886) (or .cse0 .cse1)) (and (= |ULTIMATE.start_main_#t~ite28_Out-135639886| 0) (not .cse0) (not .cse1)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-135639886, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-135639886} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-135639886, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out-135639886|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-135639886} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 19:01:43,951 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L819-->L819-2: Formula: (let ((.cse2 (= 0 (mod ~z$r_buff0_thd0~0_In2033272641 256))) (.cse3 (= (mod ~z$w_buff0_used~0_In2033272641 256) 0)) (.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In2033272641 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In2033272641 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite29_Out2033272641| 0)) (and (or .cse2 .cse3) (or .cse1 .cse0) (= ~z$r_buff1_thd0~0_In2033272641 |ULTIMATE.start_main_#t~ite29_Out2033272641|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In2033272641, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2033272641, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In2033272641, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2033272641} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In2033272641, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out2033272641|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2033272641, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In2033272641, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2033272641} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 19:01:43,954 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L831-->L832: Formula: (and (= v_~z$r_buff0_thd0~0_103 v_~z$r_buff0_thd0~0_102) (not (= (mod v_~weak$$choice2~0_23 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_103, ~weak$$choice2~0=v_~weak$$choice2~0_23} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_102, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_6|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_10|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_6|, ~weak$$choice2~0=v_~weak$$choice2~0_23} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 19:01:43,954 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L834-->L837-1: Formula: (and (= v_~z$mem_tmp~0_11 v_~z~0_133) (= (mod v_~main$tmp_guard1~0_9 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (not (= 0 (mod v_~z$flush_delayed~0_21 256))) (= 0 v_~z$flush_delayed~0_20)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_11, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_9, ~z$flush_delayed~0=v_~z$flush_delayed~0_21} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_11, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_18|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_9, ~z$flush_delayed~0=v_~z$flush_delayed~0_20, ~z~0=v_~z~0_133, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 19:01:43,954 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L837-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 19:01:44,012 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 07:01:44 BasicIcfg [2019-12-07 19:01:44,012 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 19:01:44,012 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 19:01:44,012 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 19:01:44,012 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 19:01:44,013 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:59:30" (3/4) ... [2019-12-07 19:01:44,014 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 19:01:44,014 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] ULTIMATE.startENTRY-->L805: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t2031~0.base_21| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t2031~0.base_21|) |v_ULTIMATE.start_main_~#t2031~0.offset_17| 0)) |v_#memory_int_21|) (= v_~__unbuffered_cnt~0_140 0) (= 0 v_~z$flush_delayed~0_34) (= v_~z$r_buff1_thd0~0_308 0) (= v_~z$w_buff1_used~0_516 0) (= v_~z$r_buff1_thd1~0_190 0) (= v_~z$read_delayed~0_8 0) (= v_~z$w_buff0~0_342 0) (= v_~main$tmp_guard1~0_21 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t2031~0.base_21|) (= v_~z$read_delayed_var~0.offset_7 0) (= |v_ULTIMATE.start_main_~#t2031~0.offset_17| 0) (< 0 |v_#StackHeapBarrier_18|) (= v_~z$r_buff1_thd2~0_206 0) (= v_~y~0_34 0) (= 0 |v_#NULL.base_4|) (= 0 v_~z$r_buff0_thd3~0_140) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$r_buff0_thd1~0_226 0) (= v_~main$tmp_guard0~0_21 0) (= v_~weak$$choice2~0_109 0) (= v_~z$mem_tmp~0_19 0) (= v_~z$r_buff0_thd0~0_374 0) (= |v_#NULL.offset_4| 0) (= 0 v_~z$r_buff1_thd3~0_196) (= v_~z$r_buff0_thd2~0_140 0) (= 0 v_~__unbuffered_p2_EAX~0_36) (= (select .cse0 |v_ULTIMATE.start_main_~#t2031~0.base_21|) 0) (= v_~z$w_buff0_used~0_875 0) (= 0 v_~weak$$choice0~0_13) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t2031~0.base_21| 4)) (= (store .cse0 |v_ULTIMATE.start_main_~#t2031~0.base_21| 1) |v_#valid_53|) (= v_~z$w_buff1~0_249 0) (= 0 v_~x~0_138) (= v_~z~0_182 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_22|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_21|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_27|, ULTIMATE.start_main_~#t2032~0.base=|v_ULTIMATE.start_main_~#t2032~0.base_20|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_206, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_39|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_29|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_49|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_47|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_25|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_45|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_32|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_374, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_36, ULTIMATE.start_main_~#t2031~0.offset=|v_ULTIMATE.start_main_~#t2031~0.offset_17|, ~z$mem_tmp~0=v_~z$mem_tmp~0_19, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_43|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_516, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_52|, ~z$flush_delayed~0=v_~z$flush_delayed~0_34, ULTIMATE.start_main_~#t2033~0.base=|v_ULTIMATE.start_main_~#t2033~0.base_20|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_111|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_32|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_190, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_140, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_140, ~x~0=v_~x~0_138, ULTIMATE.start_main_~#t2033~0.offset=|v_ULTIMATE.start_main_~#t2033~0.offset_16|, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_33|, ~z$read_delayed~0=v_~z$read_delayed~0_8, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_31|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_29|, ~z$w_buff1~0=v_~z$w_buff1~0_249, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_121|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_17|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_25|, ULTIMATE.start_main_~#t2032~0.offset=|v_ULTIMATE.start_main_~#t2032~0.offset_17|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_41|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_31|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_308, ~y~0=v_~y~0_34, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_140, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_10|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_21|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_875, ~z$w_buff0~0=v_~z$w_buff0~0_342, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_196, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_25|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_54|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_21, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_59|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_38|, ULTIMATE.start_main_~#t2031~0.base=|v_ULTIMATE.start_main_~#t2031~0.base_21|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_32|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_21|, ~z~0=v_~z~0_182, ~weak$$choice2~0=v_~weak$$choice2~0_109, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_226} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t2032~0.base, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t2031~0.offset, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_~#t2033~0.base, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_~#t2033~0.offset, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_~#t2032~0.offset, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_~#t2031~0.base, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 19:01:44,015 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L805-1-->L807: Formula: (and (= |v_#valid_34| (store |v_#valid_35| |v_ULTIMATE.start_main_~#t2032~0.base_12| 1)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2032~0.base_12| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2032~0.base_12|) |v_ULTIMATE.start_main_~#t2032~0.offset_11| 1)) |v_#memory_int_13|) (= 0 (select |v_#valid_35| |v_ULTIMATE.start_main_~#t2032~0.base_12|)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t2032~0.base_12|) (not (= 0 |v_ULTIMATE.start_main_~#t2032~0.base_12|)) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t2032~0.base_12| 4)) (= |v_ULTIMATE.start_main_~#t2032~0.offset_11| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_6|, ULTIMATE.start_main_~#t2032~0.base=|v_ULTIMATE.start_main_~#t2032~0.base_12|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_13|, #length=|v_#length_17|, ULTIMATE.start_main_~#t2032~0.offset=|v_ULTIMATE.start_main_~#t2032~0.offset_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t2032~0.base, #valid, #memory_int, #length, ULTIMATE.start_main_~#t2032~0.offset] because there is no mapped edge [2019-12-07 19:01:44,015 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] P0ENTRY-->L4-3: Formula: (and (= v_~z$w_buff0_used~0_226 v_~z$w_buff1_used~0_114) (= v_P0Thread1of1ForFork0_~arg.base_20 |v_P0Thread1of1ForFork0_#in~arg.base_22|) (= 2 v_~z$w_buff0~0_55) (= v_~z$w_buff0~0_56 v_~z$w_buff1~0_53) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_24 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_20|) (= (ite (not (and (not (= 0 (mod v_~z$w_buff0_used~0_225 256))) (not (= 0 (mod v_~z$w_buff1_used~0_114 256))))) 1 0) |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_20|) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_24 0)) (= v_P0Thread1of1ForFork0_~arg.offset_20 |v_P0Thread1of1ForFork0_#in~arg.offset_22|) (= v_~z$w_buff0_used~0_225 1)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_226, ~z$w_buff0~0=v_~z$w_buff0~0_56, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_22|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_225, ~z$w_buff0~0=v_~z$w_buff0~0_55, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_24, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_114, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_22|, ~z$w_buff1~0=v_~z$w_buff1~0_53, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_20, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_20|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_20} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 19:01:44,015 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L807-1-->L809: Formula: (and (= |v_#memory_int_9| (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2033~0.base_9| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2033~0.base_9|) |v_ULTIMATE.start_main_~#t2033~0.offset_8| 2))) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t2033~0.base_9|) (= (select |v_#valid_28| |v_ULTIMATE.start_main_~#t2033~0.base_9|) 0) (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t2033~0.base_9| 4)) (= |v_#valid_27| (store |v_#valid_28| |v_ULTIMATE.start_main_~#t2033~0.base_9| 1)) (not (= 0 |v_ULTIMATE.start_main_~#t2033~0.base_9|)) (= |v_ULTIMATE.start_main_~#t2033~0.offset_8| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_28|, #memory_int=|v_#memory_int_10|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_27|, #memory_int=|v_#memory_int_9|, #length=|v_#length_13|, ULTIMATE.start_main_~#t2033~0.base=|v_ULTIMATE.start_main_~#t2033~0.base_9|, ULTIMATE.start_main_~#t2033~0.offset=|v_ULTIMATE.start_main_~#t2033~0.offset_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t2033~0.base, ULTIMATE.start_main_~#t2033~0.offset] because there is no mapped edge [2019-12-07 19:01:44,016 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L743-->L743-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd1~0_In497331916 256) 0)) (.cse0 (= (mod ~z$w_buff0_used~0_In497331916 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite5_Out497331916| 0) (not .cse0) (not .cse1)) (and (= |P0Thread1of1ForFork0_#t~ite5_Out497331916| ~z$w_buff0_used~0_In497331916) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In497331916, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In497331916} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out497331916|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In497331916, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In497331916} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 19:01:44,016 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L744-->L744-2: Formula: (let ((.cse1 (= (mod ~z$r_buff1_thd1~0_In138640008 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In138640008 256))) (.cse3 (= 0 (mod ~z$r_buff0_thd1~0_In138640008 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In138640008 256)))) (or (and (= |P0Thread1of1ForFork0_#t~ite6_Out138640008| ~z$w_buff1_used~0_In138640008) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P0Thread1of1ForFork0_#t~ite6_Out138640008| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In138640008, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In138640008, ~z$w_buff1_used~0=~z$w_buff1_used~0_In138640008, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In138640008} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out138640008|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In138640008, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In138640008, ~z$w_buff1_used~0=~z$w_buff1_used~0_In138640008, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In138640008} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 19:01:44,017 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L745-->L746: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd1~0_In1933115398 256))) (.cse2 (= ~z$r_buff0_thd1~0_In1933115398 ~z$r_buff0_thd1~0_Out1933115398)) (.cse0 (= (mod ~z$w_buff0_used~0_In1933115398 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 ~z$r_buff0_thd1~0_Out1933115398)) (and .cse1 .cse2) (and .cse2 .cse0))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1933115398, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1933115398} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1933115398, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out1933115398|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out1933115398} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 19:01:44,017 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L746-->L746-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff1_thd1~0_In-1861045831 256))) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-1861045831 256))) (.cse0 (= (mod ~z$r_buff0_thd1~0_In-1861045831 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1861045831 256)))) (or (and (= |P0Thread1of1ForFork0_#t~ite8_Out-1861045831| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (= |P0Thread1of1ForFork0_#t~ite8_Out-1861045831| ~z$r_buff1_thd1~0_In-1861045831) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1861045831, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1861045831, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1861045831, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1861045831} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1861045831, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-1861045831|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1861045831, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1861045831, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1861045831} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 19:01:44,017 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L746-2-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_44 1) v_~__unbuffered_cnt~0_43) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_63 |v_P0Thread1of1ForFork0_#t~ite8_26|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_44} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_25|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_63, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_43} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 19:01:44,017 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L762-2-->L762-5: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In866179867 256) 0)) (.cse2 (= 0 (mod ~z$r_buff1_thd2~0_In866179867 256))) (.cse0 (= |P1Thread1of1ForFork1_#t~ite10_Out866179867| |P1Thread1of1ForFork1_#t~ite9_Out866179867|))) (or (and (= ~z~0_In866179867 |P1Thread1of1ForFork1_#t~ite9_Out866179867|) .cse0 (or .cse1 .cse2)) (and (not .cse1) (not .cse2) .cse0 (= ~z$w_buff1~0_In866179867 |P1Thread1of1ForFork1_#t~ite9_Out866179867|)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In866179867, ~z$w_buff1_used~0=~z$w_buff1_used~0_In866179867, ~z$w_buff1~0=~z$w_buff1~0_In866179867, ~z~0=~z~0_In866179867} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out866179867|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In866179867, ~z$w_buff1_used~0=~z$w_buff1_used~0_In866179867, P1Thread1of1ForFork1_#t~ite10=|P1Thread1of1ForFork1_#t~ite10_Out866179867|, ~z$w_buff1~0=~z$w_buff1~0_In866179867, ~z~0=~z~0_In866179867} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10] because there is no mapped edge [2019-12-07 19:01:44,017 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L782-2-->L782-4: Formula: (let ((.cse1 (= (mod ~z$r_buff1_thd3~0_In-168215761 256) 0)) (.cse0 (= (mod ~z$w_buff1_used~0_In-168215761 256) 0))) (or (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In-168215761 |P2Thread1of1ForFork2_#t~ite15_Out-168215761|)) (and (= ~z~0_In-168215761 |P2Thread1of1ForFork2_#t~ite15_Out-168215761|) (or .cse1 .cse0)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-168215761, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-168215761, ~z$w_buff1~0=~z$w_buff1~0_In-168215761, ~z~0=~z~0_In-168215761} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-168215761|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-168215761, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-168215761, ~z$w_buff1~0=~z$w_buff1~0_In-168215761, ~z~0=~z~0_In-168215761} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 19:01:44,017 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L782-4-->L783: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~z~0_20) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, ~z~0=v_~z~0_20, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_11|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~z~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 19:01:44,017 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [774] [774] L783-->L783-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd3~0_In-1840070820 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1840070820 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P2Thread1of1ForFork2_#t~ite17_Out-1840070820|)) (and (= ~z$w_buff0_used~0_In-1840070820 |P2Thread1of1ForFork2_#t~ite17_Out-1840070820|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1840070820, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1840070820} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1840070820, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1840070820, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out-1840070820|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 19:01:44,018 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L784-->L784-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In1994600450 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In1994600450 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In1994600450 256))) (.cse3 (= (mod ~z$w_buff1_used~0_In1994600450 256) 0))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite18_Out1994600450|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$w_buff1_used~0_In1994600450 |P2Thread1of1ForFork2_#t~ite18_Out1994600450|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1994600450, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1994600450, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1994600450, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1994600450} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1994600450, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1994600450, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1994600450, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1994600450, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out1994600450|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 19:01:44,018 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L785-->L785-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-2375935 256))) (.cse1 (= (mod ~z$r_buff0_thd3~0_In-2375935 256) 0))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite19_Out-2375935|) (not .cse0) (not .cse1)) (and (= ~z$r_buff0_thd3~0_In-2375935 |P2Thread1of1ForFork2_#t~ite19_Out-2375935|) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-2375935, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-2375935} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-2375935, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-2375935, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-2375935|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 19:01:44,018 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L786-->L786-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In2106500356 256))) (.cse0 (= (mod ~z$r_buff0_thd3~0_In2106500356 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In2106500356 256) 0)) (.cse3 (= 0 (mod ~z$r_buff1_thd3~0_In2106500356 256)))) (or (and (= ~z$r_buff1_thd3~0_In2106500356 |P2Thread1of1ForFork2_#t~ite20_Out2106500356|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork2_#t~ite20_Out2106500356|) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In2106500356, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In2106500356, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2106500356, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In2106500356} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In2106500356, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out2106500356|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In2106500356, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2106500356, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In2106500356} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 19:01:44,018 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L786-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_54 (+ v_~__unbuffered_cnt~0_55 1)) (= |v_P2Thread1of1ForFork2_#t~ite20_30| v_~z$r_buff1_thd3~0_67)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_30|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_29|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_67, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 19:01:44,019 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L763-->L763-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In1713412744 256) 0)) (.cse1 (= (mod ~z$r_buff0_thd2~0_In1713412744 256) 0))) (or (and (= |P1Thread1of1ForFork1_#t~ite11_Out1713412744| ~z$w_buff0_used~0_In1713412744) (or .cse0 .cse1)) (and (not .cse0) (= 0 |P1Thread1of1ForFork1_#t~ite11_Out1713412744|) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1713412744, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1713412744} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1713412744, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out1713412744|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1713412744} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 19:01:44,019 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L764-->L764-2: Formula: (let ((.cse3 (= 0 (mod ~z$w_buff1_used~0_In-1515790868 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd2~0_In-1515790868 256))) (.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In-1515790868 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1515790868 256)))) (or (and (= |P1Thread1of1ForFork1_#t~ite12_Out-1515790868| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (= |P1Thread1of1ForFork1_#t~ite12_Out-1515790868| ~z$w_buff1_used~0_In-1515790868) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1515790868, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1515790868, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1515790868, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1515790868} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1515790868, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1515790868, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1515790868, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-1515790868|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1515790868} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 19:01:44,019 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L765-->L765-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In948749047 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In948749047 256)))) (or (and (or .cse0 .cse1) (= ~z$r_buff0_thd2~0_In948749047 |P1Thread1of1ForFork1_#t~ite13_Out948749047|)) (and (= 0 |P1Thread1of1ForFork1_#t~ite13_Out948749047|) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In948749047, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In948749047} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In948749047, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out948749047|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In948749047} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 19:01:44,019 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L766-->L766-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd2~0_In-1015547216 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In-1015547216 256) 0)) (.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In-1015547216 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1015547216 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite14_Out-1015547216|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse0 .cse1) (= ~z$r_buff1_thd2~0_In-1015547216 |P1Thread1of1ForFork1_#t~ite14_Out-1015547216|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1015547216, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1015547216, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1015547216, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1015547216} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1015547216, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1015547216, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1015547216, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-1015547216|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1015547216} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 19:01:44,020 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L766-2-->P1EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_61 1) v_~__unbuffered_cnt~0_60) (= |v_P1Thread1of1ForFork1_#t~ite14_30| v_~z$r_buff1_thd2~0_84) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_61, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_30|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_84, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_60, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_29|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 19:01:44,020 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L809-1-->L815: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (= v_~main$tmp_guard0~0_8 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_18) 1 0) 0) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_18} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_7|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_18, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 19:01:44,020 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L815-2-->L815-5: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In-462132085 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-462132085 256) 0)) (.cse2 (= |ULTIMATE.start_main_#t~ite24_Out-462132085| |ULTIMATE.start_main_#t~ite25_Out-462132085|))) (or (and (not .cse0) (not .cse1) .cse2 (= |ULTIMATE.start_main_#t~ite24_Out-462132085| ~z$w_buff1~0_In-462132085)) (and (or .cse0 .cse1) .cse2 (= |ULTIMATE.start_main_#t~ite24_Out-462132085| ~z~0_In-462132085)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-462132085, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-462132085, ~z$w_buff1~0=~z$w_buff1~0_In-462132085, ~z~0=~z~0_In-462132085} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-462132085, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-462132085|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-462132085, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-462132085|, ~z$w_buff1~0=~z$w_buff1~0_In-462132085, ~z~0=~z~0_In-462132085} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 19:01:44,020 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [768] [768] L816-->L816-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-1385175578 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-1385175578 256)))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite26_Out-1385175578|) (not .cse1)) (and (or .cse1 .cse0) (= ~z$w_buff0_used~0_In-1385175578 |ULTIMATE.start_main_#t~ite26_Out-1385175578|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1385175578, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1385175578} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1385175578, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1385175578, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-1385175578|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 19:01:44,020 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L817-->L817-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd0~0_In-1274498138 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-1274498138 256) 0)) (.cse2 (= 0 (mod ~z$r_buff1_thd0~0_In-1274498138 256))) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In-1274498138 256)))) (or (and (= 0 |ULTIMATE.start_main_#t~ite27_Out-1274498138|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In-1274498138 |ULTIMATE.start_main_#t~ite27_Out-1274498138|) (or .cse2 .cse3)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1274498138, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1274498138, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1274498138, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1274498138} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1274498138, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1274498138, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1274498138, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1274498138, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-1274498138|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 19:01:44,021 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L818-->L818-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd0~0_In-135639886 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In-135639886 256)))) (or (and (= |ULTIMATE.start_main_#t~ite28_Out-135639886| ~z$r_buff0_thd0~0_In-135639886) (or .cse0 .cse1)) (and (= |ULTIMATE.start_main_#t~ite28_Out-135639886| 0) (not .cse0) (not .cse1)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-135639886, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-135639886} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-135639886, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out-135639886|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-135639886} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 19:01:44,021 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L819-->L819-2: Formula: (let ((.cse2 (= 0 (mod ~z$r_buff0_thd0~0_In2033272641 256))) (.cse3 (= (mod ~z$w_buff0_used~0_In2033272641 256) 0)) (.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In2033272641 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In2033272641 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite29_Out2033272641| 0)) (and (or .cse2 .cse3) (or .cse1 .cse0) (= ~z$r_buff1_thd0~0_In2033272641 |ULTIMATE.start_main_#t~ite29_Out2033272641|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In2033272641, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2033272641, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In2033272641, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2033272641} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In2033272641, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out2033272641|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2033272641, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In2033272641, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2033272641} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 19:01:44,023 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L831-->L832: Formula: (and (= v_~z$r_buff0_thd0~0_103 v_~z$r_buff0_thd0~0_102) (not (= (mod v_~weak$$choice2~0_23 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_103, ~weak$$choice2~0=v_~weak$$choice2~0_23} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_102, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_6|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_10|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_6|, ~weak$$choice2~0=v_~weak$$choice2~0_23} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 19:01:44,024 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L834-->L837-1: Formula: (and (= v_~z$mem_tmp~0_11 v_~z~0_133) (= (mod v_~main$tmp_guard1~0_9 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (not (= 0 (mod v_~z$flush_delayed~0_21 256))) (= 0 v_~z$flush_delayed~0_20)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_11, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_9, ~z$flush_delayed~0=v_~z$flush_delayed~0_21} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_11, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_18|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_9, ~z$flush_delayed~0=v_~z$flush_delayed~0_20, ~z~0=v_~z~0_133, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 19:01:44,024 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L837-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 19:01:44,081 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_4739de85-2d8c-4d99-832b-63bd60268610/bin/uautomizer/witness.graphml [2019-12-07 19:01:44,081 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 19:01:44,082 INFO L168 Benchmark]: Toolchain (without parser) took 134126.26 ms. Allocated memory was 1.0 GB in the beginning and 6.9 GB in the end (delta: 5.8 GB). Free memory was 939.8 MB in the beginning and 3.5 GB in the end (delta: -2.6 GB). Peak memory consumption was 3.3 GB. Max. memory is 11.5 GB. [2019-12-07 19:01:44,083 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 960.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 19:01:44,083 INFO L168 Benchmark]: CACSL2BoogieTranslator took 427.88 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 136.8 MB). Free memory was 939.8 MB in the beginning and 1.1 GB in the end (delta: -164.7 MB). Peak memory consumption was 22.7 MB. Max. memory is 11.5 GB. [2019-12-07 19:01:44,083 INFO L168 Benchmark]: Boogie Procedure Inliner took 49.84 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.2 MB). Peak memory consumption was 3.2 MB. Max. memory is 11.5 GB. [2019-12-07 19:01:44,083 INFO L168 Benchmark]: Boogie Preprocessor took 33.14 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.2 MB). Peak memory consumption was 2.2 MB. Max. memory is 11.5 GB. [2019-12-07 19:01:44,084 INFO L168 Benchmark]: RCFGBuilder took 416.35 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.5 MB). Peak memory consumption was 55.5 MB. Max. memory is 11.5 GB. [2019-12-07 19:01:44,084 INFO L168 Benchmark]: TraceAbstraction took 133126.82 ms. Allocated memory was 1.2 GB in the beginning and 6.9 GB in the end (delta: 5.7 GB). Free memory was 1.0 GB in the beginning and 3.5 GB in the end (delta: -2.5 GB). Peak memory consumption was 3.2 GB. Max. memory is 11.5 GB. [2019-12-07 19:01:44,084 INFO L168 Benchmark]: Witness Printer took 69.18 ms. Allocated memory is still 6.9 GB. Free memory was 3.5 GB in the beginning and 3.5 GB in the end (delta: 37.7 MB). Peak memory consumption was 37.7 MB. Max. memory is 11.5 GB. [2019-12-07 19:01:44,085 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 960.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 427.88 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 136.8 MB). Free memory was 939.8 MB in the beginning and 1.1 GB in the end (delta: -164.7 MB). Peak memory consumption was 22.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 49.84 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.2 MB). Peak memory consumption was 3.2 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 33.14 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.2 MB). Peak memory consumption was 2.2 MB. Max. memory is 11.5 GB. * RCFGBuilder took 416.35 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.5 MB). Peak memory consumption was 55.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 133126.82 ms. Allocated memory was 1.2 GB in the beginning and 6.9 GB in the end (delta: 5.7 GB). Free memory was 1.0 GB in the beginning and 3.5 GB in the end (delta: -2.5 GB). Peak memory consumption was 3.2 GB. Max. memory is 11.5 GB. * Witness Printer took 69.18 ms. Allocated memory is still 6.9 GB. Free memory was 3.5 GB in the beginning and 3.5 GB in the end (delta: 37.7 MB). Peak memory consumption was 37.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.0s, 174 ProgramPointsBefore, 93 ProgramPointsAfterwards, 211 TransitionsBefore, 104 TransitionsAfterwards, 17114 CoEnabledTransitionPairs, 8 FixpointIterations, 31 TrivialSequentialCompositions, 44 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 37 ConcurrentYvCompositions, 30 ChoiceCompositions, 6114 VarBasedMoverChecksPositive, 254 VarBasedMoverChecksNegative, 80 SemBasedMoverChecksPositive, 255 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.9s, 0 MoverChecksTotal, 86146 CheckedPairsTotal, 112 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L805] FCALL, FORK 0 pthread_create(&t2031, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L732] 1 z$r_buff1_thd0 = z$r_buff0_thd0 [L733] 1 z$r_buff1_thd1 = z$r_buff0_thd1 [L734] 1 z$r_buff1_thd2 = z$r_buff0_thd2 [L735] 1 z$r_buff1_thd3 = z$r_buff0_thd3 [L736] 1 z$r_buff0_thd1 = (_Bool)1 [L739] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L742] EXPR 1 z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L807] FCALL, FORK 0 pthread_create(&t2032, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L742] 1 z = z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) [L743] 1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used [L744] 1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used [L809] FCALL, FORK 0 pthread_create(&t2033, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L756] 2 x = 2 [L759] 2 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L762] EXPR 2 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L776] 3 __unbuffered_p2_EAX = y [L779] 3 z = 1 VAL [__unbuffered_cnt=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z)=2, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=2] [L782] 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z)=2, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=2] [L783] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L784] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L785] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L762] 2 z = z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) [L763] 2 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used [L764] 2 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used [L765] 2 z$r_buff0_thd2 = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 [L815] EXPR 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L815] 0 z = z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) [L816] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L817] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L818] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L819] 0 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L822] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L823] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L824] 0 z$flush_delayed = weak$$choice2 [L825] 0 z$mem_tmp = z VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L826] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L826] 0 z = !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) [L827] EXPR 0 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L827] 0 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) [L828] EXPR 0 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L828] 0 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) [L829] EXPR 0 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L829] 0 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) [L830] EXPR 0 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L830] 0 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L832] EXPR 0 weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L832] 0 z$r_buff1_thd0 = weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L833] 0 main$tmp_guard1 = !(x == 2 && z == 2 && __unbuffered_p2_EAX == 1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 165 locations, 2 error locations. Result: UNSAFE, OverallTime: 132.9s, OverallIterations: 26, TraceHistogramMax: 1, AutomataDifference: 23.3s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 4346 SDtfs, 4490 SDslu, 10331 SDs, 0 SdLazy, 6133 SolverSat, 322 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 266 GetRequests, 48 SyntacticMatches, 22 SemanticMatches, 196 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 694 ImplicationChecksByTransitivity, 2.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=225509occurred in iteration=7, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 92.1s AutomataMinimizationTime, 25 MinimizatonAttempts, 470988 StatesRemovedByMinimization, 23 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.5s InterpolantComputationTime, 1192 NumberOfCodeBlocks, 1192 NumberOfCodeBlocksAsserted, 26 NumberOfCheckSat, 1099 ConstructedInterpolants, 0 QuantifiedInterpolants, 243721 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 25 InterpolantComputations, 25 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...