./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe011_rmo.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_cbb69b23-2ffa-4739-a536-4c1fc45c20c9/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_cbb69b23-2ffa-4739-a536-4c1fc45c20c9/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_cbb69b23-2ffa-4739-a536-4c1fc45c20c9/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_cbb69b23-2ffa-4739-a536-4c1fc45c20c9/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe011_rmo.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_cbb69b23-2ffa-4739-a536-4c1fc45c20c9/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_cbb69b23-2ffa-4739-a536-4c1fc45c20c9/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 39fd7864f58ccd1962c7ae68b07ca104ef8b5483 .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:17:45,366 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:17:45,368 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:17:45,375 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:17:45,376 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:17:45,376 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:17:45,377 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:17:45,379 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:17:45,380 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:17:45,380 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:17:45,381 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:17:45,382 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:17:45,382 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:17:45,383 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:17:45,383 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:17:45,384 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:17:45,385 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:17:45,386 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:17:45,387 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:17:45,389 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:17:45,390 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:17:45,390 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:17:45,391 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:17:45,392 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:17:45,393 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:17:45,394 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:17:45,394 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:17:45,394 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:17:45,395 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:17:45,395 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:17:45,395 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:17:45,396 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:17:45,396 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:17:45,397 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:17:45,397 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:17:45,397 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:17:45,398 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:17:45,398 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:17:45,398 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:17:45,399 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:17:45,399 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:17:45,399 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_cbb69b23-2ffa-4739-a536-4c1fc45c20c9/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 18:17:45,409 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:17:45,409 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:17:45,410 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:17:45,410 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:17:45,410 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:17:45,410 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:17:45,410 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:17:45,410 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:17:45,410 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:17:45,411 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:17:45,411 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 18:17:45,411 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 18:17:45,411 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 18:17:45,411 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:17:45,411 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:17:45,411 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:17:45,411 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 18:17:45,412 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:17:45,412 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:17:45,412 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 18:17:45,412 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 18:17:45,412 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:17:45,412 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:17:45,412 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 18:17:45,412 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 18:17:45,412 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:17:45,413 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 18:17:45,413 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 18:17:45,413 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:17:45,413 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_cbb69b23-2ffa-4739-a536-4c1fc45c20c9/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 39fd7864f58ccd1962c7ae68b07ca104ef8b5483 [2019-12-07 18:17:45,513 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:17:45,523 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:17:45,526 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:17:45,527 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:17:45,527 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:17:45,528 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_cbb69b23-2ffa-4739-a536-4c1fc45c20c9/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe011_rmo.opt.i [2019-12-07 18:17:45,570 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_cbb69b23-2ffa-4739-a536-4c1fc45c20c9/bin/uautomizer/data/cdd42a2c2/a26ceddb031b4f73b0b41ebfd3941066/FLAG34e1135f3 [2019-12-07 18:17:45,944 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:17:45,944 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_cbb69b23-2ffa-4739-a536-4c1fc45c20c9/sv-benchmarks/c/pthread-wmm/safe011_rmo.opt.i [2019-12-07 18:17:45,954 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_cbb69b23-2ffa-4739-a536-4c1fc45c20c9/bin/uautomizer/data/cdd42a2c2/a26ceddb031b4f73b0b41ebfd3941066/FLAG34e1135f3 [2019-12-07 18:17:45,962 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_cbb69b23-2ffa-4739-a536-4c1fc45c20c9/bin/uautomizer/data/cdd42a2c2/a26ceddb031b4f73b0b41ebfd3941066 [2019-12-07 18:17:45,964 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:17:45,965 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:17:45,965 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:17:45,965 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:17:45,968 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:17:45,968 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:17:45" (1/1) ... [2019-12-07 18:17:45,970 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3f8fae9c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:45, skipping insertion in model container [2019-12-07 18:17:45,970 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:17:45" (1/1) ... [2019-12-07 18:17:45,974 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:17:46,008 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:17:46,257 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:17:46,264 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:17:46,305 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:17:46,349 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:17:46,350 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:46 WrapperNode [2019-12-07 18:17:46,350 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:17:46,350 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:17:46,350 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:17:46,350 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:17:46,355 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:46" (1/1) ... [2019-12-07 18:17:46,368 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:46" (1/1) ... [2019-12-07 18:17:46,389 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:17:46,390 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:17:46,390 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:17:46,390 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:17:46,397 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:46" (1/1) ... [2019-12-07 18:17:46,397 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:46" (1/1) ... [2019-12-07 18:17:46,400 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:46" (1/1) ... [2019-12-07 18:17:46,400 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:46" (1/1) ... [2019-12-07 18:17:46,407 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:46" (1/1) ... [2019-12-07 18:17:46,411 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:46" (1/1) ... [2019-12-07 18:17:46,413 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:46" (1/1) ... [2019-12-07 18:17:46,417 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:17:46,417 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:17:46,417 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:17:46,417 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:17:46,418 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:46" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_cbb69b23-2ffa-4739-a536-4c1fc45c20c9/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:17:46,457 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 18:17:46,457 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 18:17:46,457 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 18:17:46,457 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 18:17:46,457 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 18:17:46,457 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 18:17:46,457 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 18:17:46,457 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 18:17:46,458 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 18:17:46,458 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 18:17:46,458 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 18:17:46,458 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:17:46,458 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:17:46,459 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 18:17:46,812 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:17:46,812 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 18:17:46,813 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:17:46 BoogieIcfgContainer [2019-12-07 18:17:46,813 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:17:46,814 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 18:17:46,814 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 18:17:46,816 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 18:17:46,816 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 06:17:45" (1/3) ... [2019-12-07 18:17:46,817 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3823441 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:17:46, skipping insertion in model container [2019-12-07 18:17:46,817 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:17:46" (2/3) ... [2019-12-07 18:17:46,817 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3823441 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:17:46, skipping insertion in model container [2019-12-07 18:17:46,817 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:17:46" (3/3) ... [2019-12-07 18:17:46,818 INFO L109 eAbstractionObserver]: Analyzing ICFG safe011_rmo.opt.i [2019-12-07 18:17:46,825 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 18:17:46,825 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 18:17:46,830 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 18:17:46,830 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 18:17:46,853 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,854 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,854 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,854 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,854 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,854 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,854 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,855 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,855 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,855 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,855 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,855 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,855 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,855 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,856 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,856 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,856 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,856 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,856 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,856 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,856 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,856 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,857 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,857 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,857 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,857 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,857 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,857 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,857 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,858 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,858 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,858 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,858 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,858 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,858 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,859 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,859 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,859 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,859 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,859 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,859 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,859 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,859 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,860 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,860 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,860 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,860 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,860 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,860 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,860 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,861 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,861 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,861 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,861 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,861 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,861 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,861 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,861 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,862 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,862 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,862 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,862 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,862 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,862 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,863 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,863 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,863 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,863 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,863 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,863 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,863 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,863 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,864 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,864 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,864 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,864 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,864 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,864 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,864 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,864 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,864 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,865 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,865 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,865 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,865 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,865 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,865 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,865 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,865 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,866 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,866 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,866 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,866 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,866 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:17:46,877 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 18:17:46,889 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 18:17:46,890 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 18:17:46,890 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 18:17:46,890 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:17:46,890 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:17:46,890 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 18:17:46,890 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:17:46,890 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 18:17:46,901 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 174 places, 211 transitions [2019-12-07 18:17:46,903 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 174 places, 211 transitions [2019-12-07 18:17:46,955 INFO L134 PetriNetUnfolder]: 47/208 cut-off events. [2019-12-07 18:17:46,955 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:17:46,965 INFO L76 FinitePrefix]: Finished finitePrefix Result has 218 conditions, 208 events. 47/208 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 573 event pairs. 9/168 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 18:17:46,979 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 174 places, 211 transitions [2019-12-07 18:17:47,007 INFO L134 PetriNetUnfolder]: 47/208 cut-off events. [2019-12-07 18:17:47,007 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:17:47,012 INFO L76 FinitePrefix]: Finished finitePrefix Result has 218 conditions, 208 events. 47/208 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 573 event pairs. 9/168 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 18:17:47,029 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 17114 [2019-12-07 18:17:47,029 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 18:17:49,883 WARN L192 SmtUtils]: Spent 135.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 85 [2019-12-07 18:17:49,976 INFO L206 etLargeBlockEncoding]: Checked pairs total: 86146 [2019-12-07 18:17:49,976 INFO L214 etLargeBlockEncoding]: Total number of compositions: 112 [2019-12-07 18:17:49,979 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 93 places, 104 transitions [2019-12-07 18:18:02,358 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 104862 states. [2019-12-07 18:18:02,360 INFO L276 IsEmpty]: Start isEmpty. Operand 104862 states. [2019-12-07 18:18:02,364 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-12-07 18:18:02,364 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:18:02,364 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-12-07 18:18:02,364 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:18:02,368 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:18:02,368 INFO L82 PathProgramCache]: Analyzing trace with hash 844471, now seen corresponding path program 1 times [2019-12-07 18:18:02,374 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:18:02,374 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [315830311] [2019-12-07 18:18:02,374 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:18:02,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:18:02,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:18:02,518 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [315830311] [2019-12-07 18:18:02,518 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:18:02,519 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:18:02,519 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [734705790] [2019-12-07 18:18:02,522 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:18:02,522 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:18:02,531 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:18:02,531 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:18:02,532 INFO L87 Difference]: Start difference. First operand 104862 states. Second operand 3 states. [2019-12-07 18:18:03,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:18:03,248 INFO L93 Difference]: Finished difference Result 104560 states and 448162 transitions. [2019-12-07 18:18:03,248 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:18:03,249 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-12-07 18:18:03,249 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:18:03,826 INFO L225 Difference]: With dead ends: 104560 [2019-12-07 18:18:03,826 INFO L226 Difference]: Without dead ends: 102376 [2019-12-07 18:18:03,827 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:18:07,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102376 states. [2019-12-07 18:18:08,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102376 to 102376. [2019-12-07 18:18:08,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102376 states. [2019-12-07 18:18:09,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102376 states to 102376 states and 439244 transitions. [2019-12-07 18:18:09,204 INFO L78 Accepts]: Start accepts. Automaton has 102376 states and 439244 transitions. Word has length 3 [2019-12-07 18:18:09,204 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:18:09,204 INFO L462 AbstractCegarLoop]: Abstraction has 102376 states and 439244 transitions. [2019-12-07 18:18:09,205 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:18:09,205 INFO L276 IsEmpty]: Start isEmpty. Operand 102376 states and 439244 transitions. [2019-12-07 18:18:09,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 18:18:09,209 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:18:09,209 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:18:09,209 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:18:09,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:18:09,210 INFO L82 PathProgramCache]: Analyzing trace with hash 205437058, now seen corresponding path program 1 times [2019-12-07 18:18:09,210 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:18:09,210 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1160317951] [2019-12-07 18:18:09,210 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:18:09,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:18:09,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:18:09,276 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1160317951] [2019-12-07 18:18:09,277 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:18:09,277 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:18:09,277 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [479405328] [2019-12-07 18:18:09,278 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:18:09,278 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:18:09,279 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:18:09,279 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:18:09,279 INFO L87 Difference]: Start difference. First operand 102376 states and 439244 transitions. Second operand 4 states. [2019-12-07 18:18:12,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:18:12,176 INFO L93 Difference]: Finished difference Result 164490 states and 678436 transitions. [2019-12-07 18:18:12,177 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:18:12,177 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 18:18:12,177 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:18:12,574 INFO L225 Difference]: With dead ends: 164490 [2019-12-07 18:18:12,574 INFO L226 Difference]: Without dead ends: 164441 [2019-12-07 18:18:12,575 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:18:16,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 164441 states. [2019-12-07 18:18:18,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 164441 to 148513. [2019-12-07 18:18:18,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148513 states. [2019-12-07 18:18:19,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148513 states to 148513 states and 619831 transitions. [2019-12-07 18:18:19,135 INFO L78 Accepts]: Start accepts. Automaton has 148513 states and 619831 transitions. Word has length 11 [2019-12-07 18:18:19,135 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:18:19,135 INFO L462 AbstractCegarLoop]: Abstraction has 148513 states and 619831 transitions. [2019-12-07 18:18:19,135 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:18:19,135 INFO L276 IsEmpty]: Start isEmpty. Operand 148513 states and 619831 transitions. [2019-12-07 18:18:19,140 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:18:19,140 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:18:19,140 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:18:19,141 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:18:19,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:18:19,141 INFO L82 PathProgramCache]: Analyzing trace with hash 1045519438, now seen corresponding path program 1 times [2019-12-07 18:18:19,141 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:18:19,141 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1821749997] [2019-12-07 18:18:19,141 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:18:19,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:18:19,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:18:19,195 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1821749997] [2019-12-07 18:18:19,195 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:18:19,196 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:18:19,196 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1380911005] [2019-12-07 18:18:19,196 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:18:19,196 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:18:19,196 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:18:19,197 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:18:19,197 INFO L87 Difference]: Start difference. First operand 148513 states and 619831 transitions. Second operand 4 states. [2019-12-07 18:18:20,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:18:20,701 INFO L93 Difference]: Finished difference Result 211896 states and 864765 transitions. [2019-12-07 18:18:20,702 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:18:20,702 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 18:18:20,703 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:18:21,225 INFO L225 Difference]: With dead ends: 211896 [2019-12-07 18:18:21,226 INFO L226 Difference]: Without dead ends: 211833 [2019-12-07 18:18:21,226 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:18:28,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211833 states. [2019-12-07 18:18:30,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211833 to 178183. [2019-12-07 18:18:30,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178183 states. [2019-12-07 18:18:31,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178183 states to 178183 states and 738846 transitions. [2019-12-07 18:18:31,115 INFO L78 Accepts]: Start accepts. Automaton has 178183 states and 738846 transitions. Word has length 13 [2019-12-07 18:18:31,116 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:18:31,116 INFO L462 AbstractCegarLoop]: Abstraction has 178183 states and 738846 transitions. [2019-12-07 18:18:31,116 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:18:31,116 INFO L276 IsEmpty]: Start isEmpty. Operand 178183 states and 738846 transitions. [2019-12-07 18:18:31,118 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:18:31,118 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:18:31,118 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:18:31,118 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:18:31,118 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:18:31,118 INFO L82 PathProgramCache]: Analyzing trace with hash 31849685, now seen corresponding path program 1 times [2019-12-07 18:18:31,118 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:18:31,119 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [628088584] [2019-12-07 18:18:31,119 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:18:31,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:18:31,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:18:31,156 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [628088584] [2019-12-07 18:18:31,157 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:18:31,157 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:18:31,157 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1599027808] [2019-12-07 18:18:31,157 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:18:31,157 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:18:31,157 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:18:31,157 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:18:31,157 INFO L87 Difference]: Start difference. First operand 178183 states and 738846 transitions. Second operand 4 states. [2019-12-07 18:18:32,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:18:32,249 INFO L93 Difference]: Finished difference Result 223676 states and 918481 transitions. [2019-12-07 18:18:32,250 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:18:32,250 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 18:18:32,250 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:18:32,836 INFO L225 Difference]: With dead ends: 223676 [2019-12-07 18:18:32,836 INFO L226 Difference]: Without dead ends: 223676 [2019-12-07 18:18:32,837 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:18:38,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223676 states. [2019-12-07 18:18:43,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223676 to 188328. [2019-12-07 18:18:43,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 188328 states. [2019-12-07 18:18:43,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188328 states to 188328 states and 781098 transitions. [2019-12-07 18:18:43,657 INFO L78 Accepts]: Start accepts. Automaton has 188328 states and 781098 transitions. Word has length 13 [2019-12-07 18:18:43,657 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:18:43,657 INFO L462 AbstractCegarLoop]: Abstraction has 188328 states and 781098 transitions. [2019-12-07 18:18:43,657 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:18:43,657 INFO L276 IsEmpty]: Start isEmpty. Operand 188328 states and 781098 transitions. [2019-12-07 18:18:43,672 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 18:18:43,672 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:18:43,672 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:18:43,672 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:18:43,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:18:43,672 INFO L82 PathProgramCache]: Analyzing trace with hash 227208446, now seen corresponding path program 1 times [2019-12-07 18:18:43,672 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:18:43,673 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1954633846] [2019-12-07 18:18:43,673 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:18:43,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:18:43,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:18:43,720 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1954633846] [2019-12-07 18:18:43,720 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:18:43,720 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:18:43,720 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1759865184] [2019-12-07 18:18:43,720 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:18:43,721 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:18:43,721 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:18:43,721 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:18:43,721 INFO L87 Difference]: Start difference. First operand 188328 states and 781098 transitions. Second operand 5 states. [2019-12-07 18:18:45,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:18:45,188 INFO L93 Difference]: Finished difference Result 280213 states and 1136950 transitions. [2019-12-07 18:18:45,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:18:45,189 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 18:18:45,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:18:45,904 INFO L225 Difference]: With dead ends: 280213 [2019-12-07 18:18:45,904 INFO L226 Difference]: Without dead ends: 280150 [2019-12-07 18:18:45,905 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:18:51,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 280150 states. [2019-12-07 18:18:55,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 280150 to 199900. [2019-12-07 18:18:55,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 199900 states. [2019-12-07 18:18:55,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199900 states to 199900 states and 824830 transitions. [2019-12-07 18:18:55,968 INFO L78 Accepts]: Start accepts. Automaton has 199900 states and 824830 transitions. Word has length 19 [2019-12-07 18:18:55,968 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:18:55,968 INFO L462 AbstractCegarLoop]: Abstraction has 199900 states and 824830 transitions. [2019-12-07 18:18:55,969 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:18:55,969 INFO L276 IsEmpty]: Start isEmpty. Operand 199900 states and 824830 transitions. [2019-12-07 18:18:55,985 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 18:18:55,985 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:18:55,986 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:18:55,986 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:18:55,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:18:55,986 INFO L82 PathProgramCache]: Analyzing trace with hash -1539749953, now seen corresponding path program 1 times [2019-12-07 18:18:55,986 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:18:55,986 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2130887659] [2019-12-07 18:18:55,986 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:18:55,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:18:56,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:18:56,028 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2130887659] [2019-12-07 18:18:56,028 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:18:56,028 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:18:56,028 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1949115544] [2019-12-07 18:18:56,028 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:18:56,028 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:18:56,028 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:18:56,029 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:18:56,029 INFO L87 Difference]: Start difference. First operand 199900 states and 824830 transitions. Second operand 5 states. [2019-12-07 18:18:57,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:18:57,667 INFO L93 Difference]: Finished difference Result 304999 states and 1233542 transitions. [2019-12-07 18:18:57,668 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:18:57,668 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 18:18:57,668 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:01,253 INFO L225 Difference]: With dead ends: 304999 [2019-12-07 18:19:01,253 INFO L226 Difference]: Without dead ends: 304859 [2019-12-07 18:19:01,253 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:19:07,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 304859 states. [2019-12-07 18:19:10,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 304859 to 208169. [2019-12-07 18:19:10,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 208169 states. [2019-12-07 18:19:11,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 208169 states to 208169 states and 858647 transitions. [2019-12-07 18:19:11,311 INFO L78 Accepts]: Start accepts. Automaton has 208169 states and 858647 transitions. Word has length 19 [2019-12-07 18:19:11,312 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:11,312 INFO L462 AbstractCegarLoop]: Abstraction has 208169 states and 858647 transitions. [2019-12-07 18:19:11,312 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:19:11,312 INFO L276 IsEmpty]: Start isEmpty. Operand 208169 states and 858647 transitions. [2019-12-07 18:19:11,324 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 18:19:11,325 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:11,325 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:11,325 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:11,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:11,325 INFO L82 PathProgramCache]: Analyzing trace with hash -737624118, now seen corresponding path program 1 times [2019-12-07 18:19:11,325 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:11,325 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2119862692] [2019-12-07 18:19:11,325 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:11,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:11,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:11,372 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2119862692] [2019-12-07 18:19:11,373 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:11,373 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:19:11,373 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [650867685] [2019-12-07 18:19:11,373 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:19:11,374 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:11,374 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:19:11,374 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:11,374 INFO L87 Difference]: Start difference. First operand 208169 states and 858647 transitions. Second operand 5 states. [2019-12-07 18:19:12,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:12,930 INFO L93 Difference]: Finished difference Result 307935 states and 1248366 transitions. [2019-12-07 18:19:12,930 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:19:12,930 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 18:19:12,930 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:14,175 INFO L225 Difference]: With dead ends: 307935 [2019-12-07 18:19:14,175 INFO L226 Difference]: Without dead ends: 307872 [2019-12-07 18:19:14,175 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:19:22,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 307872 states. [2019-12-07 18:19:26,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 307872 to 225509. [2019-12-07 18:19:26,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 225509 states. [2019-12-07 18:19:26,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225509 states to 225509 states and 928979 transitions. [2019-12-07 18:19:26,840 INFO L78 Accepts]: Start accepts. Automaton has 225509 states and 928979 transitions. Word has length 19 [2019-12-07 18:19:26,840 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:26,840 INFO L462 AbstractCegarLoop]: Abstraction has 225509 states and 928979 transitions. [2019-12-07 18:19:26,840 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:19:26,840 INFO L276 IsEmpty]: Start isEmpty. Operand 225509 states and 928979 transitions. [2019-12-07 18:19:26,891 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 18:19:26,891 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:26,892 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:26,892 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:26,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:26,892 INFO L82 PathProgramCache]: Analyzing trace with hash -451334861, now seen corresponding path program 1 times [2019-12-07 18:19:26,892 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:26,892 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [472231912] [2019-12-07 18:19:26,892 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:26,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:26,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:26,919 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [472231912] [2019-12-07 18:19:26,919 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:26,919 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:19:26,919 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1602004379] [2019-12-07 18:19:26,920 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:19:26,920 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:26,920 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:19:26,920 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:26,920 INFO L87 Difference]: Start difference. First operand 225509 states and 928979 transitions. Second operand 3 states. [2019-12-07 18:19:27,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:27,043 INFO L93 Difference]: Finished difference Result 42378 states and 136610 transitions. [2019-12-07 18:19:27,044 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:19:27,044 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-12-07 18:19:27,044 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:27,098 INFO L225 Difference]: With dead ends: 42378 [2019-12-07 18:19:27,098 INFO L226 Difference]: Without dead ends: 42378 [2019-12-07 18:19:27,098 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:27,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42378 states. [2019-12-07 18:19:27,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42378 to 42378. [2019-12-07 18:19:27,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42378 states. [2019-12-07 18:19:27,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42378 states to 42378 states and 136610 transitions. [2019-12-07 18:19:27,763 INFO L78 Accepts]: Start accepts. Automaton has 42378 states and 136610 transitions. Word has length 25 [2019-12-07 18:19:27,763 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:27,763 INFO L462 AbstractCegarLoop]: Abstraction has 42378 states and 136610 transitions. [2019-12-07 18:19:27,763 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:19:27,764 INFO L276 IsEmpty]: Start isEmpty. Operand 42378 states and 136610 transitions. [2019-12-07 18:19:27,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 18:19:27,776 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:27,776 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:27,777 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:27,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:27,777 INFO L82 PathProgramCache]: Analyzing trace with hash 1003495210, now seen corresponding path program 1 times [2019-12-07 18:19:27,777 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:27,777 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399065939] [2019-12-07 18:19:27,777 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:27,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:27,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:27,824 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1399065939] [2019-12-07 18:19:27,824 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:27,824 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:19:27,825 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [126888091] [2019-12-07 18:19:27,825 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:19:27,825 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:27,825 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:19:27,825 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:19:27,825 INFO L87 Difference]: Start difference. First operand 42378 states and 136610 transitions. Second operand 6 states. [2019-12-07 18:19:28,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:28,857 INFO L93 Difference]: Finished difference Result 52886 states and 168375 transitions. [2019-12-07 18:19:28,858 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 18:19:28,858 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 31 [2019-12-07 18:19:28,858 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:28,935 INFO L225 Difference]: With dead ends: 52886 [2019-12-07 18:19:28,935 INFO L226 Difference]: Without dead ends: 52873 [2019-12-07 18:19:28,935 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:19:29,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52873 states. [2019-12-07 18:19:29,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52873 to 39095. [2019-12-07 18:19:29,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39095 states. [2019-12-07 18:19:29,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39095 states to 39095 states and 126581 transitions. [2019-12-07 18:19:29,653 INFO L78 Accepts]: Start accepts. Automaton has 39095 states and 126581 transitions. Word has length 31 [2019-12-07 18:19:29,653 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:29,653 INFO L462 AbstractCegarLoop]: Abstraction has 39095 states and 126581 transitions. [2019-12-07 18:19:29,653 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:19:29,653 INFO L276 IsEmpty]: Start isEmpty. Operand 39095 states and 126581 transitions. [2019-12-07 18:19:29,673 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2019-12-07 18:19:29,673 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:29,673 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:29,673 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:29,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:29,674 INFO L82 PathProgramCache]: Analyzing trace with hash -170102551, now seen corresponding path program 1 times [2019-12-07 18:19:29,674 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:29,674 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [880741626] [2019-12-07 18:19:29,674 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:29,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:29,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:29,706 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [880741626] [2019-12-07 18:19:29,706 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:29,706 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:19:29,706 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [740858189] [2019-12-07 18:19:29,707 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:19:29,707 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:29,707 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:19:29,707 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:29,707 INFO L87 Difference]: Start difference. First operand 39095 states and 126581 transitions. Second operand 3 states. [2019-12-07 18:19:29,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:29,854 INFO L93 Difference]: Finished difference Result 45938 states and 148852 transitions. [2019-12-07 18:19:29,854 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:19:29,854 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 39 [2019-12-07 18:19:29,854 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:29,916 INFO L225 Difference]: With dead ends: 45938 [2019-12-07 18:19:29,916 INFO L226 Difference]: Without dead ends: 45938 [2019-12-07 18:19:29,916 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:30,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45938 states. [2019-12-07 18:19:30,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45938 to 43496. [2019-12-07 18:19:30,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43496 states. [2019-12-07 18:19:30,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43496 states to 43496 states and 141400 transitions. [2019-12-07 18:19:30,620 INFO L78 Accepts]: Start accepts. Automaton has 43496 states and 141400 transitions. Word has length 39 [2019-12-07 18:19:30,620 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:30,620 INFO L462 AbstractCegarLoop]: Abstraction has 43496 states and 141400 transitions. [2019-12-07 18:19:30,620 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:19:30,620 INFO L276 IsEmpty]: Start isEmpty. Operand 43496 states and 141400 transitions. [2019-12-07 18:19:30,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2019-12-07 18:19:30,637 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:30,637 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:30,637 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:30,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:30,637 INFO L82 PathProgramCache]: Analyzing trace with hash -42031042, now seen corresponding path program 1 times [2019-12-07 18:19:30,638 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:30,638 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [864544901] [2019-12-07 18:19:30,638 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:30,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:30,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:30,670 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [864544901] [2019-12-07 18:19:30,670 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:30,671 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:19:30,671 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [335869937] [2019-12-07 18:19:30,671 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:19:30,671 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:30,671 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:19:30,671 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:19:30,671 INFO L87 Difference]: Start difference. First operand 43496 states and 141400 transitions. Second operand 4 states. [2019-12-07 18:19:30,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:30,704 INFO L93 Difference]: Finished difference Result 7852 states and 21076 transitions. [2019-12-07 18:19:30,704 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:19:30,704 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 39 [2019-12-07 18:19:30,704 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:30,712 INFO L225 Difference]: With dead ends: 7852 [2019-12-07 18:19:30,712 INFO L226 Difference]: Without dead ends: 7852 [2019-12-07 18:19:30,712 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:19:30,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7852 states. [2019-12-07 18:19:31,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7852 to 7740. [2019-12-07 18:19:31,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7740 states. [2019-12-07 18:19:31,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7740 states to 7740 states and 20756 transitions. [2019-12-07 18:19:31,157 INFO L78 Accepts]: Start accepts. Automaton has 7740 states and 20756 transitions. Word has length 39 [2019-12-07 18:19:31,157 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:31,157 INFO L462 AbstractCegarLoop]: Abstraction has 7740 states and 20756 transitions. [2019-12-07 18:19:31,157 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:19:31,157 INFO L276 IsEmpty]: Start isEmpty. Operand 7740 states and 20756 transitions. [2019-12-07 18:19:31,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 18:19:31,162 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:31,162 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:31,162 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:31,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:31,163 INFO L82 PathProgramCache]: Analyzing trace with hash -1565012212, now seen corresponding path program 1 times [2019-12-07 18:19:31,163 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:31,163 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [371891917] [2019-12-07 18:19:31,163 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:31,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:31,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:31,214 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [371891917] [2019-12-07 18:19:31,214 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:31,215 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:19:31,215 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1747628329] [2019-12-07 18:19:31,215 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:19:31,215 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:31,215 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:19:31,215 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:31,216 INFO L87 Difference]: Start difference. First operand 7740 states and 20756 transitions. Second operand 5 states. [2019-12-07 18:19:31,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:31,240 INFO L93 Difference]: Finished difference Result 5049 states and 14453 transitions. [2019-12-07 18:19:31,241 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:19:31,241 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-12-07 18:19:31,241 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:31,245 INFO L225 Difference]: With dead ends: 5049 [2019-12-07 18:19:31,246 INFO L226 Difference]: Without dead ends: 5049 [2019-12-07 18:19:31,246 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:31,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5049 states. [2019-12-07 18:19:31,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5049 to 4685. [2019-12-07 18:19:31,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4685 states. [2019-12-07 18:19:31,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4685 states to 4685 states and 13469 transitions. [2019-12-07 18:19:31,304 INFO L78 Accepts]: Start accepts. Automaton has 4685 states and 13469 transitions. Word has length 51 [2019-12-07 18:19:31,304 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:31,304 INFO L462 AbstractCegarLoop]: Abstraction has 4685 states and 13469 transitions. [2019-12-07 18:19:31,304 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:19:31,304 INFO L276 IsEmpty]: Start isEmpty. Operand 4685 states and 13469 transitions. [2019-12-07 18:19:31,308 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:19:31,309 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:31,309 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:31,309 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:31,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:31,309 INFO L82 PathProgramCache]: Analyzing trace with hash 1173172274, now seen corresponding path program 1 times [2019-12-07 18:19:31,309 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:31,310 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1407492529] [2019-12-07 18:19:31,310 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:31,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:31,355 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:31,356 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1407492529] [2019-12-07 18:19:31,356 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:31,356 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:19:31,356 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1193200957] [2019-12-07 18:19:31,356 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:19:31,357 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:31,357 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:19:31,357 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:31,357 INFO L87 Difference]: Start difference. First operand 4685 states and 13469 transitions. Second operand 3 states. [2019-12-07 18:19:31,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:31,396 INFO L93 Difference]: Finished difference Result 4689 states and 13463 transitions. [2019-12-07 18:19:31,396 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:19:31,396 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 18:19:31,396 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:31,401 INFO L225 Difference]: With dead ends: 4689 [2019-12-07 18:19:31,401 INFO L226 Difference]: Without dead ends: 4689 [2019-12-07 18:19:31,401 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:31,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4689 states. [2019-12-07 18:19:31,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4689 to 4681. [2019-12-07 18:19:31,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4681 states. [2019-12-07 18:19:31,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4681 states to 4681 states and 13455 transitions. [2019-12-07 18:19:31,460 INFO L78 Accepts]: Start accepts. Automaton has 4681 states and 13455 transitions. Word has length 65 [2019-12-07 18:19:31,460 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:31,460 INFO L462 AbstractCegarLoop]: Abstraction has 4681 states and 13455 transitions. [2019-12-07 18:19:31,461 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:19:31,461 INFO L276 IsEmpty]: Start isEmpty. Operand 4681 states and 13455 transitions. [2019-12-07 18:19:31,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:19:31,464 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:31,465 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:31,465 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:31,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:31,465 INFO L82 PathProgramCache]: Analyzing trace with hash 1163492121, now seen corresponding path program 1 times [2019-12-07 18:19:31,465 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:31,465 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1149137438] [2019-12-07 18:19:31,465 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:31,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:31,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:31,521 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1149137438] [2019-12-07 18:19:31,521 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:31,521 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:19:31,521 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1850019307] [2019-12-07 18:19:31,522 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:19:31,522 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:31,522 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:19:31,522 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:31,522 INFO L87 Difference]: Start difference. First operand 4681 states and 13455 transitions. Second operand 5 states. [2019-12-07 18:19:31,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:31,731 INFO L93 Difference]: Finished difference Result 7105 states and 20244 transitions. [2019-12-07 18:19:31,731 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:19:31,731 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 65 [2019-12-07 18:19:31,731 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:31,737 INFO L225 Difference]: With dead ends: 7105 [2019-12-07 18:19:31,738 INFO L226 Difference]: Without dead ends: 7105 [2019-12-07 18:19:31,738 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:19:31,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7105 states. [2019-12-07 18:19:31,813 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7105 to 6291. [2019-12-07 18:19:31,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6291 states. [2019-12-07 18:19:31,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6291 states to 6291 states and 18000 transitions. [2019-12-07 18:19:31,820 INFO L78 Accepts]: Start accepts. Automaton has 6291 states and 18000 transitions. Word has length 65 [2019-12-07 18:19:31,820 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:31,820 INFO L462 AbstractCegarLoop]: Abstraction has 6291 states and 18000 transitions. [2019-12-07 18:19:31,821 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:19:31,821 INFO L276 IsEmpty]: Start isEmpty. Operand 6291 states and 18000 transitions. [2019-12-07 18:19:31,825 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:19:31,825 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:31,825 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:31,825 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:31,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:31,826 INFO L82 PathProgramCache]: Analyzing trace with hash -2061317327, now seen corresponding path program 2 times [2019-12-07 18:19:31,826 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:31,826 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568860212] [2019-12-07 18:19:31,826 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:31,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:31,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:31,899 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1568860212] [2019-12-07 18:19:31,899 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:31,899 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:19:31,899 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [187196237] [2019-12-07 18:19:31,899 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:19:31,900 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:31,900 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:19:31,900 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:31,900 INFO L87 Difference]: Start difference. First operand 6291 states and 18000 transitions. Second operand 5 states. [2019-12-07 18:19:32,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:32,097 INFO L93 Difference]: Finished difference Result 9383 states and 26609 transitions. [2019-12-07 18:19:32,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:19:32,097 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 65 [2019-12-07 18:19:32,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:32,105 INFO L225 Difference]: With dead ends: 9383 [2019-12-07 18:19:32,105 INFO L226 Difference]: Without dead ends: 9383 [2019-12-07 18:19:32,106 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:19:32,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9383 states. [2019-12-07 18:19:32,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9383 to 7346. [2019-12-07 18:19:32,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7346 states. [2019-12-07 18:19:32,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7346 states to 7346 states and 21123 transitions. [2019-12-07 18:19:32,205 INFO L78 Accepts]: Start accepts. Automaton has 7346 states and 21123 transitions. Word has length 65 [2019-12-07 18:19:32,205 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:32,205 INFO L462 AbstractCegarLoop]: Abstraction has 7346 states and 21123 transitions. [2019-12-07 18:19:32,205 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:19:32,205 INFO L276 IsEmpty]: Start isEmpty. Operand 7346 states and 21123 transitions. [2019-12-07 18:19:32,210 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:19:32,211 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:32,211 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:32,211 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:32,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:32,211 INFO L82 PathProgramCache]: Analyzing trace with hash -1650424373, now seen corresponding path program 3 times [2019-12-07 18:19:32,211 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:32,211 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446036315] [2019-12-07 18:19:32,211 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:32,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:32,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:32,261 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1446036315] [2019-12-07 18:19:32,261 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:32,261 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:19:32,262 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [872251869] [2019-12-07 18:19:32,262 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:19:32,262 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:32,262 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:19:32,262 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:19:32,262 INFO L87 Difference]: Start difference. First operand 7346 states and 21123 transitions. Second operand 6 states. [2019-12-07 18:19:32,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:32,536 INFO L93 Difference]: Finished difference Result 11509 states and 32952 transitions. [2019-12-07 18:19:32,536 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:19:32,536 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 65 [2019-12-07 18:19:32,536 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:32,546 INFO L225 Difference]: With dead ends: 11509 [2019-12-07 18:19:32,546 INFO L226 Difference]: Without dead ends: 11509 [2019-12-07 18:19:32,547 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:19:32,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11509 states. [2019-12-07 18:19:32,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11509 to 8187. [2019-12-07 18:19:32,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8187 states. [2019-12-07 18:19:32,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8187 states to 8187 states and 23603 transitions. [2019-12-07 18:19:32,665 INFO L78 Accepts]: Start accepts. Automaton has 8187 states and 23603 transitions. Word has length 65 [2019-12-07 18:19:32,666 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:32,666 INFO L462 AbstractCegarLoop]: Abstraction has 8187 states and 23603 transitions. [2019-12-07 18:19:32,666 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:19:32,666 INFO L276 IsEmpty]: Start isEmpty. Operand 8187 states and 23603 transitions. [2019-12-07 18:19:32,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:19:32,671 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:32,671 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:32,672 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:32,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:32,672 INFO L82 PathProgramCache]: Analyzing trace with hash 2063456247, now seen corresponding path program 4 times [2019-12-07 18:19:32,672 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:32,672 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782289835] [2019-12-07 18:19:32,672 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:32,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:32,748 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:32,749 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [782289835] [2019-12-07 18:19:32,749 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:32,749 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:19:32,749 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1780085798] [2019-12-07 18:19:32,750 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:19:32,750 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:32,750 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:19:32,750 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:19:32,750 INFO L87 Difference]: Start difference. First operand 8187 states and 23603 transitions. Second operand 7 states. [2019-12-07 18:19:32,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:32,834 INFO L93 Difference]: Finished difference Result 16785 states and 48827 transitions. [2019-12-07 18:19:32,835 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:19:32,835 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 65 [2019-12-07 18:19:32,835 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:32,844 INFO L225 Difference]: With dead ends: 16785 [2019-12-07 18:19:32,844 INFO L226 Difference]: Without dead ends: 10139 [2019-12-07 18:19:32,844 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=61, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:19:32,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10139 states. [2019-12-07 18:19:32,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10139 to 7699. [2019-12-07 18:19:32,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7699 states. [2019-12-07 18:19:32,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7699 states to 7699 states and 22167 transitions. [2019-12-07 18:19:32,950 INFO L78 Accepts]: Start accepts. Automaton has 7699 states and 22167 transitions. Word has length 65 [2019-12-07 18:19:32,950 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:32,950 INFO L462 AbstractCegarLoop]: Abstraction has 7699 states and 22167 transitions. [2019-12-07 18:19:32,950 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:19:32,951 INFO L276 IsEmpty]: Start isEmpty. Operand 7699 states and 22167 transitions. [2019-12-07 18:19:32,956 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:19:32,956 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:32,956 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:32,956 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:32,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:32,957 INFO L82 PathProgramCache]: Analyzing trace with hash -1622090895, now seen corresponding path program 5 times [2019-12-07 18:19:32,957 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:32,957 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1238804970] [2019-12-07 18:19:32,957 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:32,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:33,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:33,029 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1238804970] [2019-12-07 18:19:33,029 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:33,029 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 18:19:33,029 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2019179902] [2019-12-07 18:19:33,029 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:19:33,030 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:33,030 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:19:33,030 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:19:33,030 INFO L87 Difference]: Start difference. First operand 7699 states and 22167 transitions. Second operand 7 states. [2019-12-07 18:19:33,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:33,574 INFO L93 Difference]: Finished difference Result 11074 states and 31647 transitions. [2019-12-07 18:19:33,574 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 18:19:33,574 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 65 [2019-12-07 18:19:33,575 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:33,583 INFO L225 Difference]: With dead ends: 11074 [2019-12-07 18:19:33,584 INFO L226 Difference]: Without dead ends: 11074 [2019-12-07 18:19:33,584 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 11 SyntacticMatches, 2 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=72, Invalid=200, Unknown=0, NotChecked=0, Total=272 [2019-12-07 18:19:33,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11074 states. [2019-12-07 18:19:33,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11074 to 7818. [2019-12-07 18:19:33,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7818 states. [2019-12-07 18:19:33,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7818 states to 7818 states and 22493 transitions. [2019-12-07 18:19:33,697 INFO L78 Accepts]: Start accepts. Automaton has 7818 states and 22493 transitions. Word has length 65 [2019-12-07 18:19:33,698 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:33,698 INFO L462 AbstractCegarLoop]: Abstraction has 7818 states and 22493 transitions. [2019-12-07 18:19:33,698 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:19:33,698 INFO L276 IsEmpty]: Start isEmpty. Operand 7818 states and 22493 transitions. [2019-12-07 18:19:33,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:19:33,703 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:33,703 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:33,704 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:33,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:33,704 INFO L82 PathProgramCache]: Analyzing trace with hash 1304907827, now seen corresponding path program 6 times [2019-12-07 18:19:33,704 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:33,704 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1177506104] [2019-12-07 18:19:33,704 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:33,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:33,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:33,775 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1177506104] [2019-12-07 18:19:33,775 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:33,776 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:19:33,776 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [24914050] [2019-12-07 18:19:33,776 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:19:33,776 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:33,776 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:19:33,776 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:19:33,777 INFO L87 Difference]: Start difference. First operand 7818 states and 22493 transitions. Second operand 6 states. [2019-12-07 18:19:34,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:34,105 INFO L93 Difference]: Finished difference Result 11087 states and 31304 transitions. [2019-12-07 18:19:34,105 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 18:19:34,105 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 65 [2019-12-07 18:19:34,105 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:34,114 INFO L225 Difference]: With dead ends: 11087 [2019-12-07 18:19:34,114 INFO L226 Difference]: Without dead ends: 11087 [2019-12-07 18:19:34,115 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:19:34,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11087 states. [2019-12-07 18:19:34,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11087 to 8098. [2019-12-07 18:19:34,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8098 states. [2019-12-07 18:19:34,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8098 states to 8098 states and 23285 transitions. [2019-12-07 18:19:34,231 INFO L78 Accepts]: Start accepts. Automaton has 8098 states and 23285 transitions. Word has length 65 [2019-12-07 18:19:34,231 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:34,232 INFO L462 AbstractCegarLoop]: Abstraction has 8098 states and 23285 transitions. [2019-12-07 18:19:34,232 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:19:34,232 INFO L276 IsEmpty]: Start isEmpty. Operand 8098 states and 23285 transitions. [2019-12-07 18:19:34,237 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:19:34,237 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:34,237 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:34,237 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:34,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:34,238 INFO L82 PathProgramCache]: Analyzing trace with hash -338304105, now seen corresponding path program 7 times [2019-12-07 18:19:34,238 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:34,238 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466179400] [2019-12-07 18:19:34,238 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:34,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:34,305 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:34,305 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1466179400] [2019-12-07 18:19:34,305 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:34,305 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 18:19:34,305 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1797315609] [2019-12-07 18:19:34,305 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:19:34,305 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:34,306 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:19:34,306 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:19:34,306 INFO L87 Difference]: Start difference. First operand 8098 states and 23285 transitions. Second operand 7 states. [2019-12-07 18:19:35,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:35,116 INFO L93 Difference]: Finished difference Result 11193 states and 31670 transitions. [2019-12-07 18:19:35,117 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 18:19:35,117 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 65 [2019-12-07 18:19:35,117 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:35,125 INFO L225 Difference]: With dead ends: 11193 [2019-12-07 18:19:35,126 INFO L226 Difference]: Without dead ends: 11193 [2019-12-07 18:19:35,126 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 8 SyntacticMatches, 3 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 100 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=110, Invalid=396, Unknown=0, NotChecked=0, Total=506 [2019-12-07 18:19:35,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11193 states. [2019-12-07 18:19:35,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11193 to 8475. [2019-12-07 18:19:35,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8475 states. [2019-12-07 18:19:35,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8475 states to 8475 states and 24310 transitions. [2019-12-07 18:19:35,242 INFO L78 Accepts]: Start accepts. Automaton has 8475 states and 24310 transitions. Word has length 65 [2019-12-07 18:19:35,242 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:35,242 INFO L462 AbstractCegarLoop]: Abstraction has 8475 states and 24310 transitions. [2019-12-07 18:19:35,242 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:19:35,242 INFO L276 IsEmpty]: Start isEmpty. Operand 8475 states and 24310 transitions. [2019-12-07 18:19:35,248 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:19:35,248 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:35,248 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:35,248 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:35,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:35,248 INFO L82 PathProgramCache]: Analyzing trace with hash 882387211, now seen corresponding path program 8 times [2019-12-07 18:19:35,249 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:35,249 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1187027028] [2019-12-07 18:19:35,249 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:35,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:35,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:35,286 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1187027028] [2019-12-07 18:19:35,286 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:35,286 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:19:35,286 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [455053890] [2019-12-07 18:19:35,287 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:19:35,287 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:35,287 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:19:35,287 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:35,287 INFO L87 Difference]: Start difference. First operand 8475 states and 24310 transitions. Second operand 3 states. [2019-12-07 18:19:35,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:35,308 INFO L93 Difference]: Finished difference Result 7390 states and 20855 transitions. [2019-12-07 18:19:35,309 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:19:35,309 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 18:19:35,309 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:35,315 INFO L225 Difference]: With dead ends: 7390 [2019-12-07 18:19:35,315 INFO L226 Difference]: Without dead ends: 7390 [2019-12-07 18:19:35,316 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:35,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7390 states. [2019-12-07 18:19:35,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7390 to 7082. [2019-12-07 18:19:35,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7082 states. [2019-12-07 18:19:35,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7082 states to 7082 states and 20003 transitions. [2019-12-07 18:19:35,400 INFO L78 Accepts]: Start accepts. Automaton has 7082 states and 20003 transitions. Word has length 65 [2019-12-07 18:19:35,400 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:35,400 INFO L462 AbstractCegarLoop]: Abstraction has 7082 states and 20003 transitions. [2019-12-07 18:19:35,400 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:19:35,400 INFO L276 IsEmpty]: Start isEmpty. Operand 7082 states and 20003 transitions. [2019-12-07 18:19:35,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 18:19:35,405 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:35,405 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:35,405 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:35,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:35,406 INFO L82 PathProgramCache]: Analyzing trace with hash -1218810065, now seen corresponding path program 1 times [2019-12-07 18:19:35,406 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:35,406 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [374824038] [2019-12-07 18:19:35,406 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:35,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:35,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:35,546 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [374824038] [2019-12-07 18:19:35,546 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:35,546 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 18:19:35,546 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1496012205] [2019-12-07 18:19:35,547 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 18:19:35,547 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:35,547 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 18:19:35,547 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:19:35,547 INFO L87 Difference]: Start difference. First operand 7082 states and 20003 transitions. Second operand 10 states. [2019-12-07 18:19:36,241 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:36,241 INFO L93 Difference]: Finished difference Result 13673 states and 38825 transitions. [2019-12-07 18:19:36,241 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 18:19:36,241 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 66 [2019-12-07 18:19:36,242 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:36,253 INFO L225 Difference]: With dead ends: 13673 [2019-12-07 18:19:36,253 INFO L226 Difference]: Without dead ends: 13673 [2019-12-07 18:19:36,253 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 2 SyntacticMatches, 4 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 52 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=83, Invalid=259, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:19:36,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13673 states. [2019-12-07 18:19:36,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13673 to 7220. [2019-12-07 18:19:36,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7220 states. [2019-12-07 18:19:36,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7220 states to 7220 states and 20466 transitions. [2019-12-07 18:19:36,377 INFO L78 Accepts]: Start accepts. Automaton has 7220 states and 20466 transitions. Word has length 66 [2019-12-07 18:19:36,377 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:36,377 INFO L462 AbstractCegarLoop]: Abstraction has 7220 states and 20466 transitions. [2019-12-07 18:19:36,377 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 18:19:36,377 INFO L276 IsEmpty]: Start isEmpty. Operand 7220 states and 20466 transitions. [2019-12-07 18:19:36,382 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 18:19:36,382 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:36,382 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:36,382 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:36,383 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:36,383 INFO L82 PathProgramCache]: Analyzing trace with hash -812873571, now seen corresponding path program 2 times [2019-12-07 18:19:36,383 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:36,383 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195462969] [2019-12-07 18:19:36,383 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:36,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:36,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:36,415 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1195462969] [2019-12-07 18:19:36,415 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:36,415 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:19:36,415 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1788228344] [2019-12-07 18:19:36,415 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:19:36,416 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:36,416 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:19:36,416 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:36,416 INFO L87 Difference]: Start difference. First operand 7220 states and 20466 transitions. Second operand 3 states. [2019-12-07 18:19:36,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:36,462 INFO L93 Difference]: Finished difference Result 7220 states and 20465 transitions. [2019-12-07 18:19:36,462 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:19:36,462 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 18:19:36,463 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:36,471 INFO L225 Difference]: With dead ends: 7220 [2019-12-07 18:19:36,471 INFO L226 Difference]: Without dead ends: 7220 [2019-12-07 18:19:36,472 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:36,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7220 states. [2019-12-07 18:19:36,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7220 to 4611. [2019-12-07 18:19:36,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4611 states. [2019-12-07 18:19:36,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4611 states to 4611 states and 13149 transitions. [2019-12-07 18:19:36,553 INFO L78 Accepts]: Start accepts. Automaton has 4611 states and 13149 transitions. Word has length 66 [2019-12-07 18:19:36,553 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:36,553 INFO L462 AbstractCegarLoop]: Abstraction has 4611 states and 13149 transitions. [2019-12-07 18:19:36,553 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:19:36,553 INFO L276 IsEmpty]: Start isEmpty. Operand 4611 states and 13149 transitions. [2019-12-07 18:19:36,557 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:19:36,557 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:36,557 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:36,557 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:36,557 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:36,557 INFO L82 PathProgramCache]: Analyzing trace with hash 728190721, now seen corresponding path program 1 times [2019-12-07 18:19:36,557 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:36,557 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [22036866] [2019-12-07 18:19:36,557 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:36,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:36,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:36,588 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [22036866] [2019-12-07 18:19:36,589 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:36,589 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:19:36,589 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [916414437] [2019-12-07 18:19:36,589 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:19:36,589 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:36,589 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:19:36,589 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:36,589 INFO L87 Difference]: Start difference. First operand 4611 states and 13149 transitions. Second operand 3 states. [2019-12-07 18:19:36,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:36,604 INFO L93 Difference]: Finished difference Result 4387 states and 12195 transitions. [2019-12-07 18:19:36,604 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:19:36,604 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 18:19:36,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:36,608 INFO L225 Difference]: With dead ends: 4387 [2019-12-07 18:19:36,608 INFO L226 Difference]: Without dead ends: 4387 [2019-12-07 18:19:36,608 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:36,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4387 states. [2019-12-07 18:19:36,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4387 to 4177. [2019-12-07 18:19:36,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4177 states. [2019-12-07 18:19:36,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4177 states to 4177 states and 11620 transitions. [2019-12-07 18:19:36,660 INFO L78 Accepts]: Start accepts. Automaton has 4177 states and 11620 transitions. Word has length 67 [2019-12-07 18:19:36,661 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:36,661 INFO L462 AbstractCegarLoop]: Abstraction has 4177 states and 11620 transitions. [2019-12-07 18:19:36,661 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:19:36,661 INFO L276 IsEmpty]: Start isEmpty. Operand 4177 states and 11620 transitions. [2019-12-07 18:19:36,663 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:19:36,664 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:36,664 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:36,664 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:36,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:36,664 INFO L82 PathProgramCache]: Analyzing trace with hash -829052917, now seen corresponding path program 1 times [2019-12-07 18:19:36,664 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:36,664 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1199036051] [2019-12-07 18:19:36,664 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:36,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:36,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:36,845 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1199036051] [2019-12-07 18:19:36,845 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:36,845 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 18:19:36,846 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [496819117] [2019-12-07 18:19:36,846 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 18:19:36,846 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:36,846 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 18:19:36,846 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=149, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:19:36,846 INFO L87 Difference]: Start difference. First operand 4177 states and 11620 transitions. Second operand 14 states. [2019-12-07 18:19:37,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:37,405 INFO L93 Difference]: Finished difference Result 8900 states and 24838 transitions. [2019-12-07 18:19:37,405 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-12-07 18:19:37,405 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 68 [2019-12-07 18:19:37,405 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:37,412 INFO L225 Difference]: With dead ends: 8900 [2019-12-07 18:19:37,412 INFO L226 Difference]: Without dead ends: 8348 [2019-12-07 18:19:37,413 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 155 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=163, Invalid=707, Unknown=0, NotChecked=0, Total=870 [2019-12-07 18:19:37,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8348 states. [2019-12-07 18:19:37,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8348 to 6060. [2019-12-07 18:19:37,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6060 states. [2019-12-07 18:19:37,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6060 states to 6060 states and 16841 transitions. [2019-12-07 18:19:37,495 INFO L78 Accepts]: Start accepts. Automaton has 6060 states and 16841 transitions. Word has length 68 [2019-12-07 18:19:37,495 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:37,495 INFO L462 AbstractCegarLoop]: Abstraction has 6060 states and 16841 transitions. [2019-12-07 18:19:37,495 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 18:19:37,495 INFO L276 IsEmpty]: Start isEmpty. Operand 6060 states and 16841 transitions. [2019-12-07 18:19:37,499 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:19:37,499 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:37,499 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:37,499 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:37,499 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:37,500 INFO L82 PathProgramCache]: Analyzing trace with hash 226058755, now seen corresponding path program 2 times [2019-12-07 18:19:37,500 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:37,500 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [655613435] [2019-12-07 18:19:37,500 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:37,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:37,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:37,730 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [655613435] [2019-12-07 18:19:37,730 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:37,730 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 18:19:37,730 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1336412886] [2019-12-07 18:19:37,731 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 18:19:37,731 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:37,731 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 18:19:37,731 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=205, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:19:37,731 INFO L87 Difference]: Start difference. First operand 6060 states and 16841 transitions. Second operand 16 states. [2019-12-07 18:19:38,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:38,859 INFO L93 Difference]: Finished difference Result 14384 states and 39713 transitions. [2019-12-07 18:19:38,859 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2019-12-07 18:19:38,860 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 68 [2019-12-07 18:19:38,860 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:38,871 INFO L225 Difference]: With dead ends: 14384 [2019-12-07 18:19:38,871 INFO L226 Difference]: Without dead ends: 14036 [2019-12-07 18:19:38,872 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 438 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=319, Invalid=1751, Unknown=0, NotChecked=0, Total=2070 [2019-12-07 18:19:38,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14036 states. [2019-12-07 18:19:38,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14036 to 6724. [2019-12-07 18:19:38,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6724 states. [2019-12-07 18:19:38,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6724 states to 6724 states and 18639 transitions. [2019-12-07 18:19:38,996 INFO L78 Accepts]: Start accepts. Automaton has 6724 states and 18639 transitions. Word has length 68 [2019-12-07 18:19:38,996 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:38,997 INFO L462 AbstractCegarLoop]: Abstraction has 6724 states and 18639 transitions. [2019-12-07 18:19:38,997 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 18:19:38,997 INFO L276 IsEmpty]: Start isEmpty. Operand 6724 states and 18639 transitions. [2019-12-07 18:19:39,001 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:19:39,001 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:39,001 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:39,001 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:39,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:39,001 INFO L82 PathProgramCache]: Analyzing trace with hash 1101405001, now seen corresponding path program 3 times [2019-12-07 18:19:39,001 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:39,002 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [315068966] [2019-12-07 18:19:39,002 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:39,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:39,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:39,198 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [315068966] [2019-12-07 18:19:39,198 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:39,198 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 18:19:39,198 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [54158388] [2019-12-07 18:19:39,198 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 18:19:39,199 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:39,199 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 18:19:39,199 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=177, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:19:39,199 INFO L87 Difference]: Start difference. First operand 6724 states and 18639 transitions. Second operand 15 states. [2019-12-07 18:19:40,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:40,544 INFO L93 Difference]: Finished difference Result 11848 states and 32532 transitions. [2019-12-07 18:19:40,544 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2019-12-07 18:19:40,544 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 68 [2019-12-07 18:19:40,545 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:40,562 INFO L225 Difference]: With dead ends: 11848 [2019-12-07 18:19:40,562 INFO L226 Difference]: Without dead ends: 11498 [2019-12-07 18:19:40,563 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 395 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=333, Invalid=1389, Unknown=0, NotChecked=0, Total=1722 [2019-12-07 18:19:40,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11498 states. [2019-12-07 18:19:40,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11498 to 6515. [2019-12-07 18:19:40,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6515 states. [2019-12-07 18:19:40,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6515 states to 6515 states and 18027 transitions. [2019-12-07 18:19:40,672 INFO L78 Accepts]: Start accepts. Automaton has 6515 states and 18027 transitions. Word has length 68 [2019-12-07 18:19:40,672 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:40,672 INFO L462 AbstractCegarLoop]: Abstraction has 6515 states and 18027 transitions. [2019-12-07 18:19:40,672 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 18:19:40,672 INFO L276 IsEmpty]: Start isEmpty. Operand 6515 states and 18027 transitions. [2019-12-07 18:19:40,677 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:19:40,677 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:40,677 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:40,677 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:40,677 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:40,677 INFO L82 PathProgramCache]: Analyzing trace with hash -1907883765, now seen corresponding path program 4 times [2019-12-07 18:19:40,677 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:40,677 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [590963907] [2019-12-07 18:19:40,677 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:40,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:40,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:40,921 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [590963907] [2019-12-07 18:19:40,921 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:40,921 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 18:19:40,921 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1052015833] [2019-12-07 18:19:40,922 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 18:19:40,922 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:40,922 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 18:19:40,922 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=200, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:19:40,922 INFO L87 Difference]: Start difference. First operand 6515 states and 18027 transitions. Second operand 16 states. [2019-12-07 18:19:41,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:41,722 INFO L93 Difference]: Finished difference Result 10627 states and 29117 transitions. [2019-12-07 18:19:41,722 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-12-07 18:19:41,723 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 68 [2019-12-07 18:19:41,723 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:41,730 INFO L225 Difference]: With dead ends: 10627 [2019-12-07 18:19:41,730 INFO L226 Difference]: Without dead ends: 9792 [2019-12-07 18:19:41,731 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 354 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=368, Invalid=1354, Unknown=0, NotChecked=0, Total=1722 [2019-12-07 18:19:41,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9792 states. [2019-12-07 18:19:41,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9792 to 5804. [2019-12-07 18:19:41,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5804 states. [2019-12-07 18:19:41,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5804 states to 5804 states and 16009 transitions. [2019-12-07 18:19:41,817 INFO L78 Accepts]: Start accepts. Automaton has 5804 states and 16009 transitions. Word has length 68 [2019-12-07 18:19:41,817 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:41,817 INFO L462 AbstractCegarLoop]: Abstraction has 5804 states and 16009 transitions. [2019-12-07 18:19:41,817 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 18:19:41,817 INFO L276 IsEmpty]: Start isEmpty. Operand 5804 states and 16009 transitions. [2019-12-07 18:19:41,821 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:19:41,821 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:41,821 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:41,821 INFO L410 AbstractCegarLoop]: === Iteration 29 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:41,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:41,821 INFO L82 PathProgramCache]: Analyzing trace with hash 1851838847, now seen corresponding path program 5 times [2019-12-07 18:19:41,821 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:41,822 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [998521993] [2019-12-07 18:19:41,822 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:41,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:19:41,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:19:41,893 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:19:41,894 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 18:19:41,897 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] ULTIMATE.startENTRY-->L805: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t2040~0.base_21|) (= v_~__unbuffered_cnt~0_140 0) (= 0 v_~z$flush_delayed~0_34) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t2040~0.base_21| 4)) (= v_~z$r_buff1_thd0~0_308 0) (= v_~z$w_buff1_used~0_516 0) (= v_~z$r_buff1_thd1~0_190 0) (= v_~z$read_delayed~0_8 0) (= v_~z$w_buff0~0_342 0) (= v_~main$tmp_guard1~0_21 0) (= v_~z$read_delayed_var~0.offset_7 0) (< 0 |v_#StackHeapBarrier_18|) (= v_~z$r_buff1_thd2~0_206 0) (= v_~y~0_34 0) (= 0 |v_#NULL.base_4|) (= 0 v_~z$r_buff0_thd3~0_140) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$r_buff0_thd1~0_226 0) (= |v_ULTIMATE.start_main_~#t2040~0.offset_17| 0) (= v_~main$tmp_guard0~0_21 0) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t2040~0.base_21| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t2040~0.base_21|) |v_ULTIMATE.start_main_~#t2040~0.offset_17| 0)) |v_#memory_int_21|) (= v_~weak$$choice2~0_109 0) (= v_~z$mem_tmp~0_19 0) (= v_~z$r_buff0_thd0~0_374 0) (= |v_#valid_53| (store .cse0 |v_ULTIMATE.start_main_~#t2040~0.base_21| 1)) (= |v_#NULL.offset_4| 0) (= 0 v_~z$r_buff1_thd3~0_196) (= v_~z$r_buff0_thd2~0_140 0) (= 0 v_~__unbuffered_p2_EAX~0_36) (= v_~z$w_buff0_used~0_875 0) (= 0 v_~weak$$choice0~0_13) (= v_~z$w_buff1~0_249 0) (= 0 v_~x~0_138) (= v_~z~0_182 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t2040~0.base_21|)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_22|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_21|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_27|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_206, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_39|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_29|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_49|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_47|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_25|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_45|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_32|, ULTIMATE.start_main_~#t2041~0.offset=|v_ULTIMATE.start_main_~#t2041~0.offset_17|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_374, ULTIMATE.start_main_~#t2041~0.base=|v_ULTIMATE.start_main_~#t2041~0.base_20|, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_36, ~z$mem_tmp~0=v_~z$mem_tmp~0_19, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_43|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_516, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_52|, ~z$flush_delayed~0=v_~z$flush_delayed~0_34, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_111|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_32|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_190, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_140, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_140, ULTIMATE.start_main_~#t2040~0.base=|v_ULTIMATE.start_main_~#t2040~0.base_21|, ~x~0=v_~x~0_138, ULTIMATE.start_main_~#t2042~0.offset=|v_ULTIMATE.start_main_~#t2042~0.offset_16|, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_33|, ~z$read_delayed~0=v_~z$read_delayed~0_8, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_31|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_29|, ~z$w_buff1~0=v_~z$w_buff1~0_249, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_121|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_17|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_25|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_41|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_31|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_308, ~y~0=v_~y~0_34, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_140, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_10|, ULTIMATE.start_main_~#t2042~0.base=|v_ULTIMATE.start_main_~#t2042~0.base_20|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_21|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_875, ~z$w_buff0~0=v_~z$w_buff0~0_342, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_196, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_25|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_54|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_21, ULTIMATE.start_main_~#t2040~0.offset=|v_ULTIMATE.start_main_~#t2040~0.offset_17|, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_59|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_38|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_32|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_21|, ~z~0=v_~z~0_182, ~weak$$choice2~0=v_~weak$$choice2~0_109, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_226} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ULTIMATE.start_main_~#t2041~0.offset, ~z$r_buff0_thd0~0, ULTIMATE.start_main_~#t2041~0.base, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ULTIMATE.start_main_~#t2040~0.base, ~x~0, ULTIMATE.start_main_~#t2042~0.offset, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t2042~0.base, ULTIMATE.start_main_#t~nondet23, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_~#t2040~0.offset, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 18:19:41,897 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L805-1-->L807: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t2041~0.base_12|)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t2041~0.base_12|) (= 0 (select |v_#valid_35| |v_ULTIMATE.start_main_~#t2041~0.base_12|)) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2041~0.base_12| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2041~0.base_12|) |v_ULTIMATE.start_main_~#t2041~0.offset_11| 1))) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t2041~0.base_12| 4)) (= |v_#valid_34| (store |v_#valid_35| |v_ULTIMATE.start_main_~#t2041~0.base_12| 1)) (= 0 |v_ULTIMATE.start_main_~#t2041~0.offset_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t2041~0.offset=|v_ULTIMATE.start_main_~#t2041~0.offset_11|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_6|, ULTIMATE.start_main_~#t2041~0.base=|v_ULTIMATE.start_main_~#t2041~0.base_12|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_13|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2041~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t2041~0.base, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 18:19:41,898 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] P0ENTRY-->L4-3: Formula: (and (= v_~z$w_buff0_used~0_226 v_~z$w_buff1_used~0_114) (= v_P0Thread1of1ForFork0_~arg.base_20 |v_P0Thread1of1ForFork0_#in~arg.base_22|) (= 2 v_~z$w_buff0~0_55) (= v_~z$w_buff0~0_56 v_~z$w_buff1~0_53) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_24 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_20|) (= (ite (not (and (not (= 0 (mod v_~z$w_buff0_used~0_225 256))) (not (= 0 (mod v_~z$w_buff1_used~0_114 256))))) 1 0) |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_20|) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_24 0)) (= v_P0Thread1of1ForFork0_~arg.offset_20 |v_P0Thread1of1ForFork0_#in~arg.offset_22|) (= v_~z$w_buff0_used~0_225 1)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_226, ~z$w_buff0~0=v_~z$w_buff0~0_56, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_22|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_225, ~z$w_buff0~0=v_~z$w_buff0~0_55, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_24, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_114, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_22|, ~z$w_buff1~0=v_~z$w_buff1~0_53, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_20, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_20|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_20} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 18:19:41,899 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L807-1-->L809: Formula: (and (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t2042~0.base_9|) (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t2042~0.base_9| 4)) (= (store |v_#valid_28| |v_ULTIMATE.start_main_~#t2042~0.base_9| 1) |v_#valid_27|) (= 0 (select |v_#valid_28| |v_ULTIMATE.start_main_~#t2042~0.base_9|)) (not (= |v_ULTIMATE.start_main_~#t2042~0.base_9| 0)) (= (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2042~0.base_9| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2042~0.base_9|) |v_ULTIMATE.start_main_~#t2042~0.offset_8| 2)) |v_#memory_int_9|) (= |v_ULTIMATE.start_main_~#t2042~0.offset_8| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_28|, #memory_int=|v_#memory_int_10|, #length=|v_#length_14|} OutVars{ULTIMATE.start_main_~#t2042~0.offset=|v_ULTIMATE.start_main_~#t2042~0.offset_8|, ULTIMATE.start_main_~#t2042~0.base=|v_ULTIMATE.start_main_~#t2042~0.base_9|, #StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_27|, #memory_int=|v_#memory_int_9|, #length=|v_#length_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2042~0.offset, ULTIMATE.start_main_~#t2042~0.base, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 18:19:41,899 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L743-->L743-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-1179045677 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In-1179045677 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P0Thread1of1ForFork0_#t~ite5_Out-1179045677|)) (and (or .cse1 .cse0) (= ~z$w_buff0_used~0_In-1179045677 |P0Thread1of1ForFork0_#t~ite5_Out-1179045677|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1179045677, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1179045677} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-1179045677|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1179045677, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1179045677} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 18:19:41,900 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L744-->L744-2: Formula: (let ((.cse3 (= (mod ~z$r_buff1_thd1~0_In-928969378 256) 0)) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-928969378 256))) (.cse0 (= (mod ~z$r_buff0_thd1~0_In-928969378 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-928969378 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork0_#t~ite6_Out-928969378|)) (and (or .cse3 .cse2) (= ~z$w_buff1_used~0_In-928969378 |P0Thread1of1ForFork0_#t~ite6_Out-928969378|) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-928969378, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-928969378, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-928969378, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-928969378} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out-928969378|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-928969378, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-928969378, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-928969378, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-928969378} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 18:19:41,901 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L745-->L746: Formula: (let ((.cse0 (= ~z$r_buff0_thd1~0_In968733521 ~z$r_buff0_thd1~0_Out968733521)) (.cse2 (= (mod ~z$r_buff0_thd1~0_In968733521 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In968733521 256) 0))) (or (and .cse0 .cse1) (and .cse0 .cse2) (and (= 0 ~z$r_buff0_thd1~0_Out968733521) (not .cse2) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In968733521, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In968733521} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In968733521, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out968733521|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out968733521} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 18:19:41,901 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L746-->L746-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In-1263679357 256))) (.cse1 (= (mod ~z$r_buff1_thd1~0_In-1263679357 256) 0)) (.cse3 (= (mod ~z$r_buff0_thd1~0_In-1263679357 256) 0)) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-1263679357 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite8_Out-1263679357| 0)) (and (or .cse0 .cse1) (or .cse3 .cse2) (= |P0Thread1of1ForFork0_#t~ite8_Out-1263679357| ~z$r_buff1_thd1~0_In-1263679357)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1263679357, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1263679357, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1263679357, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1263679357} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1263679357, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-1263679357|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1263679357, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1263679357, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1263679357} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 18:19:41,901 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L746-2-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_44 1) v_~__unbuffered_cnt~0_43) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_63 |v_P0Thread1of1ForFork0_#t~ite8_26|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_44} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_25|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_63, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_43} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 18:19:41,901 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L762-2-->L762-5: Formula: (let ((.cse0 (= |P1Thread1of1ForFork1_#t~ite10_Out1290905860| |P1Thread1of1ForFork1_#t~ite9_Out1290905860|)) (.cse1 (= (mod ~z$r_buff1_thd2~0_In1290905860 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In1290905860 256) 0))) (or (and .cse0 (not .cse1) (not .cse2) (= ~z$w_buff1~0_In1290905860 |P1Thread1of1ForFork1_#t~ite9_Out1290905860|)) (and (= ~z~0_In1290905860 |P1Thread1of1ForFork1_#t~ite9_Out1290905860|) .cse0 (or .cse1 .cse2)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1290905860, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1290905860, ~z$w_buff1~0=~z$w_buff1~0_In1290905860, ~z~0=~z~0_In1290905860} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out1290905860|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1290905860, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1290905860, P1Thread1of1ForFork1_#t~ite10=|P1Thread1of1ForFork1_#t~ite10_Out1290905860|, ~z$w_buff1~0=~z$w_buff1~0_In1290905860, ~z~0=~z~0_In1290905860} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10] because there is no mapped edge [2019-12-07 18:19:41,902 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L782-2-->L782-4: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd3~0_In-2039380594 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-2039380594 256)))) (or (and (or .cse0 .cse1) (= ~z~0_In-2039380594 |P2Thread1of1ForFork2_#t~ite15_Out-2039380594|)) (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In-2039380594 |P2Thread1of1ForFork2_#t~ite15_Out-2039380594|)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-2039380594, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2039380594, ~z$w_buff1~0=~z$w_buff1~0_In-2039380594, ~z~0=~z~0_In-2039380594} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-2039380594|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-2039380594, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2039380594, ~z$w_buff1~0=~z$w_buff1~0_In-2039380594, ~z~0=~z~0_In-2039380594} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 18:19:41,902 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L782-4-->L783: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~z~0_20) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, ~z~0=v_~z~0_20, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_11|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~z~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 18:19:41,902 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [774] [774] L783-->L783-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-612522564 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-612522564 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite17_Out-612522564| 0) (not .cse0) (not .cse1)) (and (= |P2Thread1of1ForFork2_#t~ite17_Out-612522564| ~z$w_buff0_used~0_In-612522564) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-612522564, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-612522564} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-612522564, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-612522564, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out-612522564|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 18:19:41,903 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L784-->L784-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd3~0_In-1921554792 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-1921554792 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-1921554792 256))) (.cse1 (= (mod ~z$r_buff1_thd3~0_In-1921554792 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite18_Out-1921554792|)) (and (= ~z$w_buff1_used~0_In-1921554792 |P2Thread1of1ForFork2_#t~ite18_Out-1921554792|) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1921554792, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1921554792, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1921554792, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1921554792} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1921554792, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1921554792, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1921554792, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1921554792, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-1921554792|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 18:19:41,903 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L785-->L785-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd3~0_In-1500518232 256) 0)) (.cse0 (= (mod ~z$w_buff0_used~0_In-1500518232 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite19_Out-1500518232| 0) (not .cse0) (not .cse1)) (and (= ~z$r_buff0_thd3~0_In-1500518232 |P2Thread1of1ForFork2_#t~ite19_Out-1500518232|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1500518232, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1500518232} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1500518232, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1500518232, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-1500518232|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 18:19:41,903 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L786-->L786-2: Formula: (let ((.cse3 (= 0 (mod ~z$w_buff1_used~0_In-1189064342 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In-1189064342 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1189064342 256))) (.cse1 (= (mod ~z$r_buff0_thd3~0_In-1189064342 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork2_#t~ite20_Out-1189064342| 0)) (and (or .cse3 .cse2) (= |P2Thread1of1ForFork2_#t~ite20_Out-1189064342| ~z$r_buff1_thd3~0_In-1189064342) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1189064342, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1189064342, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1189064342, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1189064342} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1189064342, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-1189064342|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1189064342, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1189064342, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1189064342} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 18:19:41,903 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L786-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_54 (+ v_~__unbuffered_cnt~0_55 1)) (= |v_P2Thread1of1ForFork2_#t~ite20_30| v_~z$r_buff1_thd3~0_67)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_30|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_29|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_67, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 18:19:41,904 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L763-->L763-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In847495186 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In847495186 256)))) (or (and (= |P1Thread1of1ForFork1_#t~ite11_Out847495186| 0) (not .cse0) (not .cse1)) (and (= |P1Thread1of1ForFork1_#t~ite11_Out847495186| ~z$w_buff0_used~0_In847495186) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In847495186, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In847495186} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In847495186, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out847495186|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In847495186} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 18:19:41,904 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L764-->L764-2: Formula: (let ((.cse3 (= (mod ~z$r_buff1_thd2~0_In-516925516 256) 0)) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-516925516 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-516925516 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In-516925516 256) 0))) (or (and (= ~z$w_buff1_used~0_In-516925516 |P1Thread1of1ForFork1_#t~ite12_Out-516925516|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out-516925516|) (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-516925516, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-516925516, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-516925516, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-516925516} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-516925516, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-516925516, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-516925516, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-516925516|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-516925516} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 18:19:41,904 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L765-->L765-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1242086709 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-1242086709 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite13_Out-1242086709|) (not .cse0) (not .cse1)) (and (= ~z$r_buff0_thd2~0_In-1242086709 |P1Thread1of1ForFork1_#t~ite13_Out-1242086709|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1242086709, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1242086709} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1242086709, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-1242086709|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1242086709} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 18:19:41,904 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L766-->L766-2: Formula: (let ((.cse3 (= 0 (mod ~z$w_buff0_used~0_In875920522 256))) (.cse2 (= (mod ~z$r_buff0_thd2~0_In875920522 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd2~0_In875920522 256) 0)) (.cse0 (= (mod ~z$w_buff1_used~0_In875920522 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork1_#t~ite14_Out875920522|)) (and (or .cse3 .cse2) (= |P1Thread1of1ForFork1_#t~ite14_Out875920522| ~z$r_buff1_thd2~0_In875920522) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In875920522, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In875920522, ~z$w_buff1_used~0=~z$w_buff1_used~0_In875920522, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In875920522} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In875920522, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In875920522, ~z$w_buff1_used~0=~z$w_buff1_used~0_In875920522, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out875920522|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In875920522} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 18:19:41,904 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L766-2-->P1EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_61 1) v_~__unbuffered_cnt~0_60) (= |v_P1Thread1of1ForFork1_#t~ite14_30| v_~z$r_buff1_thd2~0_84) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_61, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_30|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_84, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_60, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_29|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 18:19:41,905 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L809-1-->L815: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (= v_~main$tmp_guard0~0_8 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_18) 1 0) 0) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_18} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_7|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_18, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:19:41,905 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L815-2-->L815-5: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite25_Out-1778705683| |ULTIMATE.start_main_#t~ite24_Out-1778705683|)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-1778705683 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In-1778705683 256) 0))) (or (and .cse0 (= ~z~0_In-1778705683 |ULTIMATE.start_main_#t~ite24_Out-1778705683|) (or .cse1 .cse2)) (and .cse0 (not .cse1) (not .cse2) (= ~z$w_buff1~0_In-1778705683 |ULTIMATE.start_main_#t~ite24_Out-1778705683|)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1778705683, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1778705683, ~z$w_buff1~0=~z$w_buff1~0_In-1778705683, ~z~0=~z~0_In-1778705683} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1778705683, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-1778705683|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1778705683, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-1778705683|, ~z$w_buff1~0=~z$w_buff1~0_In-1778705683, ~z~0=~z~0_In-1778705683} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 18:19:41,905 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [768] [768] L816-->L816-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In-51037365 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-51037365 256)))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite26_Out-51037365|)) (and (= |ULTIMATE.start_main_#t~ite26_Out-51037365| ~z$w_buff0_used~0_In-51037365) (or .cse1 .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-51037365, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-51037365} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-51037365, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-51037365, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-51037365|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 18:19:41,905 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L817-->L817-2: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In-1957311214 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-1957311214 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-1957311214 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd0~0_In-1957311214 256)))) (or (and (= 0 |ULTIMATE.start_main_#t~ite27_Out-1957311214|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$w_buff1_used~0_In-1957311214 |ULTIMATE.start_main_#t~ite27_Out-1957311214|) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1957311214, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1957311214, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1957311214, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1957311214} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1957311214, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1957311214, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1957311214, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1957311214, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-1957311214|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 18:19:41,906 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L818-->L818-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In1162972327 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd0~0_In1162972327 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite28_Out1162972327|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite28_Out1162972327| ~z$r_buff0_thd0~0_In1162972327)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1162972327, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1162972327} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1162972327, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out1162972327|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1162972327} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 18:19:41,906 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L819-->L819-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In-1867632557 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1867632557 256))) (.cse2 (= (mod ~z$r_buff0_thd0~0_In-1867632557 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In-1867632557 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite29_Out-1867632557| ~z$r_buff1_thd0~0_In-1867632557) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |ULTIMATE.start_main_#t~ite29_Out-1867632557| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1867632557, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1867632557, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1867632557, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1867632557} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1867632557, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-1867632557|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1867632557, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1867632557, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1867632557} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 18:19:41,908 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L831-->L832: Formula: (and (= v_~z$r_buff0_thd0~0_103 v_~z$r_buff0_thd0~0_102) (not (= (mod v_~weak$$choice2~0_23 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_103, ~weak$$choice2~0=v_~weak$$choice2~0_23} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_102, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_6|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_10|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_6|, ~weak$$choice2~0=v_~weak$$choice2~0_23} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 18:19:41,909 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L834-->L837-1: Formula: (and (= v_~z$mem_tmp~0_11 v_~z~0_133) (= (mod v_~main$tmp_guard1~0_9 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (not (= 0 (mod v_~z$flush_delayed~0_21 256))) (= 0 v_~z$flush_delayed~0_20)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_11, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_9, ~z$flush_delayed~0=v_~z$flush_delayed~0_21} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_11, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_18|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_9, ~z$flush_delayed~0=v_~z$flush_delayed~0_20, ~z~0=v_~z~0_133, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:19:41,909 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L837-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:19:41,968 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 06:19:41 BasicIcfg [2019-12-07 18:19:41,968 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 18:19:41,968 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:19:41,968 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:19:41,968 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:19:41,969 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:17:46" (3/4) ... [2019-12-07 18:19:41,970 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 18:19:41,971 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] ULTIMATE.startENTRY-->L805: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t2040~0.base_21|) (= v_~__unbuffered_cnt~0_140 0) (= 0 v_~z$flush_delayed~0_34) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t2040~0.base_21| 4)) (= v_~z$r_buff1_thd0~0_308 0) (= v_~z$w_buff1_used~0_516 0) (= v_~z$r_buff1_thd1~0_190 0) (= v_~z$read_delayed~0_8 0) (= v_~z$w_buff0~0_342 0) (= v_~main$tmp_guard1~0_21 0) (= v_~z$read_delayed_var~0.offset_7 0) (< 0 |v_#StackHeapBarrier_18|) (= v_~z$r_buff1_thd2~0_206 0) (= v_~y~0_34 0) (= 0 |v_#NULL.base_4|) (= 0 v_~z$r_buff0_thd3~0_140) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$r_buff0_thd1~0_226 0) (= |v_ULTIMATE.start_main_~#t2040~0.offset_17| 0) (= v_~main$tmp_guard0~0_21 0) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t2040~0.base_21| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t2040~0.base_21|) |v_ULTIMATE.start_main_~#t2040~0.offset_17| 0)) |v_#memory_int_21|) (= v_~weak$$choice2~0_109 0) (= v_~z$mem_tmp~0_19 0) (= v_~z$r_buff0_thd0~0_374 0) (= |v_#valid_53| (store .cse0 |v_ULTIMATE.start_main_~#t2040~0.base_21| 1)) (= |v_#NULL.offset_4| 0) (= 0 v_~z$r_buff1_thd3~0_196) (= v_~z$r_buff0_thd2~0_140 0) (= 0 v_~__unbuffered_p2_EAX~0_36) (= v_~z$w_buff0_used~0_875 0) (= 0 v_~weak$$choice0~0_13) (= v_~z$w_buff1~0_249 0) (= 0 v_~x~0_138) (= v_~z~0_182 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t2040~0.base_21|)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_22|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_21|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_27|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_206, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_39|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_29|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_49|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_47|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_25|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_45|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_32|, ULTIMATE.start_main_~#t2041~0.offset=|v_ULTIMATE.start_main_~#t2041~0.offset_17|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_374, ULTIMATE.start_main_~#t2041~0.base=|v_ULTIMATE.start_main_~#t2041~0.base_20|, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_36, ~z$mem_tmp~0=v_~z$mem_tmp~0_19, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_43|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_516, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_52|, ~z$flush_delayed~0=v_~z$flush_delayed~0_34, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_111|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_32|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_190, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_140, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_140, ULTIMATE.start_main_~#t2040~0.base=|v_ULTIMATE.start_main_~#t2040~0.base_21|, ~x~0=v_~x~0_138, ULTIMATE.start_main_~#t2042~0.offset=|v_ULTIMATE.start_main_~#t2042~0.offset_16|, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_33|, ~z$read_delayed~0=v_~z$read_delayed~0_8, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_31|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_29|, ~z$w_buff1~0=v_~z$w_buff1~0_249, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_121|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_17|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_25|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_41|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_31|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_308, ~y~0=v_~y~0_34, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_140, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_10|, ULTIMATE.start_main_~#t2042~0.base=|v_ULTIMATE.start_main_~#t2042~0.base_20|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_21|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_875, ~z$w_buff0~0=v_~z$w_buff0~0_342, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_196, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_25|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_54|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_21, ULTIMATE.start_main_~#t2040~0.offset=|v_ULTIMATE.start_main_~#t2040~0.offset_17|, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_59|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_38|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_32|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_21|, ~z~0=v_~z~0_182, ~weak$$choice2~0=v_~weak$$choice2~0_109, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_226} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ULTIMATE.start_main_~#t2041~0.offset, ~z$r_buff0_thd0~0, ULTIMATE.start_main_~#t2041~0.base, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ULTIMATE.start_main_~#t2040~0.base, ~x~0, ULTIMATE.start_main_~#t2042~0.offset, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t2042~0.base, ULTIMATE.start_main_#t~nondet23, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_~#t2040~0.offset, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 18:19:41,971 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L805-1-->L807: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t2041~0.base_12|)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t2041~0.base_12|) (= 0 (select |v_#valid_35| |v_ULTIMATE.start_main_~#t2041~0.base_12|)) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2041~0.base_12| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2041~0.base_12|) |v_ULTIMATE.start_main_~#t2041~0.offset_11| 1))) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t2041~0.base_12| 4)) (= |v_#valid_34| (store |v_#valid_35| |v_ULTIMATE.start_main_~#t2041~0.base_12| 1)) (= 0 |v_ULTIMATE.start_main_~#t2041~0.offset_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t2041~0.offset=|v_ULTIMATE.start_main_~#t2041~0.offset_11|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_6|, ULTIMATE.start_main_~#t2041~0.base=|v_ULTIMATE.start_main_~#t2041~0.base_12|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_13|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2041~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t2041~0.base, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 18:19:41,971 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] P0ENTRY-->L4-3: Formula: (and (= v_~z$w_buff0_used~0_226 v_~z$w_buff1_used~0_114) (= v_P0Thread1of1ForFork0_~arg.base_20 |v_P0Thread1of1ForFork0_#in~arg.base_22|) (= 2 v_~z$w_buff0~0_55) (= v_~z$w_buff0~0_56 v_~z$w_buff1~0_53) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_24 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_20|) (= (ite (not (and (not (= 0 (mod v_~z$w_buff0_used~0_225 256))) (not (= 0 (mod v_~z$w_buff1_used~0_114 256))))) 1 0) |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_20|) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_24 0)) (= v_P0Thread1of1ForFork0_~arg.offset_20 |v_P0Thread1of1ForFork0_#in~arg.offset_22|) (= v_~z$w_buff0_used~0_225 1)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_226, ~z$w_buff0~0=v_~z$w_buff0~0_56, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_22|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_22|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_225, ~z$w_buff0~0=v_~z$w_buff0~0_55, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_24, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_114, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_22|, ~z$w_buff1~0=v_~z$w_buff1~0_53, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_20, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_20|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_20} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 18:19:41,972 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L807-1-->L809: Formula: (and (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t2042~0.base_9|) (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t2042~0.base_9| 4)) (= (store |v_#valid_28| |v_ULTIMATE.start_main_~#t2042~0.base_9| 1) |v_#valid_27|) (= 0 (select |v_#valid_28| |v_ULTIMATE.start_main_~#t2042~0.base_9|)) (not (= |v_ULTIMATE.start_main_~#t2042~0.base_9| 0)) (= (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2042~0.base_9| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2042~0.base_9|) |v_ULTIMATE.start_main_~#t2042~0.offset_8| 2)) |v_#memory_int_9|) (= |v_ULTIMATE.start_main_~#t2042~0.offset_8| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_28|, #memory_int=|v_#memory_int_10|, #length=|v_#length_14|} OutVars{ULTIMATE.start_main_~#t2042~0.offset=|v_ULTIMATE.start_main_~#t2042~0.offset_8|, ULTIMATE.start_main_~#t2042~0.base=|v_ULTIMATE.start_main_~#t2042~0.base_9|, #StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_27|, #memory_int=|v_#memory_int_9|, #length=|v_#length_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2042~0.offset, ULTIMATE.start_main_~#t2042~0.base, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 18:19:41,972 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L743-->L743-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-1179045677 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In-1179045677 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P0Thread1of1ForFork0_#t~ite5_Out-1179045677|)) (and (or .cse1 .cse0) (= ~z$w_buff0_used~0_In-1179045677 |P0Thread1of1ForFork0_#t~ite5_Out-1179045677|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1179045677, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1179045677} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-1179045677|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1179045677, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1179045677} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 18:19:41,972 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L744-->L744-2: Formula: (let ((.cse3 (= (mod ~z$r_buff1_thd1~0_In-928969378 256) 0)) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-928969378 256))) (.cse0 (= (mod ~z$r_buff0_thd1~0_In-928969378 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-928969378 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork0_#t~ite6_Out-928969378|)) (and (or .cse3 .cse2) (= ~z$w_buff1_used~0_In-928969378 |P0Thread1of1ForFork0_#t~ite6_Out-928969378|) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-928969378, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-928969378, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-928969378, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-928969378} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out-928969378|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-928969378, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-928969378, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-928969378, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-928969378} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 18:19:41,973 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L745-->L746: Formula: (let ((.cse0 (= ~z$r_buff0_thd1~0_In968733521 ~z$r_buff0_thd1~0_Out968733521)) (.cse2 (= (mod ~z$r_buff0_thd1~0_In968733521 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In968733521 256) 0))) (or (and .cse0 .cse1) (and .cse0 .cse2) (and (= 0 ~z$r_buff0_thd1~0_Out968733521) (not .cse2) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In968733521, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In968733521} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In968733521, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out968733521|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out968733521} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 18:19:41,973 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L746-->L746-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In-1263679357 256))) (.cse1 (= (mod ~z$r_buff1_thd1~0_In-1263679357 256) 0)) (.cse3 (= (mod ~z$r_buff0_thd1~0_In-1263679357 256) 0)) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-1263679357 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite8_Out-1263679357| 0)) (and (or .cse0 .cse1) (or .cse3 .cse2) (= |P0Thread1of1ForFork0_#t~ite8_Out-1263679357| ~z$r_buff1_thd1~0_In-1263679357)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1263679357, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1263679357, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1263679357, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1263679357} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1263679357, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-1263679357|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1263679357, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1263679357, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1263679357} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 18:19:41,973 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L746-2-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_44 1) v_~__unbuffered_cnt~0_43) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_63 |v_P0Thread1of1ForFork0_#t~ite8_26|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_44} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_25|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_63, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_43} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 18:19:41,973 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L762-2-->L762-5: Formula: (let ((.cse0 (= |P1Thread1of1ForFork1_#t~ite10_Out1290905860| |P1Thread1of1ForFork1_#t~ite9_Out1290905860|)) (.cse1 (= (mod ~z$r_buff1_thd2~0_In1290905860 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In1290905860 256) 0))) (or (and .cse0 (not .cse1) (not .cse2) (= ~z$w_buff1~0_In1290905860 |P1Thread1of1ForFork1_#t~ite9_Out1290905860|)) (and (= ~z~0_In1290905860 |P1Thread1of1ForFork1_#t~ite9_Out1290905860|) .cse0 (or .cse1 .cse2)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1290905860, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1290905860, ~z$w_buff1~0=~z$w_buff1~0_In1290905860, ~z~0=~z~0_In1290905860} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out1290905860|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1290905860, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1290905860, P1Thread1of1ForFork1_#t~ite10=|P1Thread1of1ForFork1_#t~ite10_Out1290905860|, ~z$w_buff1~0=~z$w_buff1~0_In1290905860, ~z~0=~z~0_In1290905860} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10] because there is no mapped edge [2019-12-07 18:19:41,974 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L782-2-->L782-4: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd3~0_In-2039380594 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-2039380594 256)))) (or (and (or .cse0 .cse1) (= ~z~0_In-2039380594 |P2Thread1of1ForFork2_#t~ite15_Out-2039380594|)) (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In-2039380594 |P2Thread1of1ForFork2_#t~ite15_Out-2039380594|)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-2039380594, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2039380594, ~z$w_buff1~0=~z$w_buff1~0_In-2039380594, ~z~0=~z~0_In-2039380594} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-2039380594|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-2039380594, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-2039380594, ~z$w_buff1~0=~z$w_buff1~0_In-2039380594, ~z~0=~z~0_In-2039380594} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 18:19:41,974 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L782-4-->L783: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~z~0_20) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, ~z~0=v_~z~0_20, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_11|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~z~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 18:19:41,974 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [774] [774] L783-->L783-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-612522564 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-612522564 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite17_Out-612522564| 0) (not .cse0) (not .cse1)) (and (= |P2Thread1of1ForFork2_#t~ite17_Out-612522564| ~z$w_buff0_used~0_In-612522564) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-612522564, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-612522564} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-612522564, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-612522564, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out-612522564|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 18:19:41,974 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L784-->L784-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd3~0_In-1921554792 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In-1921554792 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-1921554792 256))) (.cse1 (= (mod ~z$r_buff1_thd3~0_In-1921554792 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite18_Out-1921554792|)) (and (= ~z$w_buff1_used~0_In-1921554792 |P2Thread1of1ForFork2_#t~ite18_Out-1921554792|) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1921554792, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1921554792, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1921554792, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1921554792} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1921554792, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1921554792, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1921554792, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1921554792, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-1921554792|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 18:19:41,975 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L785-->L785-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd3~0_In-1500518232 256) 0)) (.cse0 (= (mod ~z$w_buff0_used~0_In-1500518232 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite19_Out-1500518232| 0) (not .cse0) (not .cse1)) (and (= ~z$r_buff0_thd3~0_In-1500518232 |P2Thread1of1ForFork2_#t~ite19_Out-1500518232|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1500518232, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1500518232} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1500518232, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1500518232, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-1500518232|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 18:19:41,975 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L786-->L786-2: Formula: (let ((.cse3 (= 0 (mod ~z$w_buff1_used~0_In-1189064342 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In-1189064342 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1189064342 256))) (.cse1 (= (mod ~z$r_buff0_thd3~0_In-1189064342 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork2_#t~ite20_Out-1189064342| 0)) (and (or .cse3 .cse2) (= |P2Thread1of1ForFork2_#t~ite20_Out-1189064342| ~z$r_buff1_thd3~0_In-1189064342) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1189064342, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1189064342, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1189064342, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1189064342} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1189064342, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-1189064342|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1189064342, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1189064342, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1189064342} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 18:19:41,975 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L786-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_54 (+ v_~__unbuffered_cnt~0_55 1)) (= |v_P2Thread1of1ForFork2_#t~ite20_30| v_~z$r_buff1_thd3~0_67)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_30|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_29|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_67, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 18:19:41,975 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L763-->L763-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In847495186 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In847495186 256)))) (or (and (= |P1Thread1of1ForFork1_#t~ite11_Out847495186| 0) (not .cse0) (not .cse1)) (and (= |P1Thread1of1ForFork1_#t~ite11_Out847495186| ~z$w_buff0_used~0_In847495186) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In847495186, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In847495186} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In847495186, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out847495186|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In847495186} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 18:19:41,976 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L764-->L764-2: Formula: (let ((.cse3 (= (mod ~z$r_buff1_thd2~0_In-516925516 256) 0)) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-516925516 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-516925516 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In-516925516 256) 0))) (or (and (= ~z$w_buff1_used~0_In-516925516 |P1Thread1of1ForFork1_#t~ite12_Out-516925516|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out-516925516|) (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-516925516, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-516925516, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-516925516, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-516925516} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-516925516, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-516925516, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-516925516, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-516925516|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-516925516} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 18:19:41,976 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L765-->L765-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1242086709 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-1242086709 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite13_Out-1242086709|) (not .cse0) (not .cse1)) (and (= ~z$r_buff0_thd2~0_In-1242086709 |P1Thread1of1ForFork1_#t~ite13_Out-1242086709|) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1242086709, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1242086709} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1242086709, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-1242086709|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1242086709} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 18:19:41,976 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L766-->L766-2: Formula: (let ((.cse3 (= 0 (mod ~z$w_buff0_used~0_In875920522 256))) (.cse2 (= (mod ~z$r_buff0_thd2~0_In875920522 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd2~0_In875920522 256) 0)) (.cse0 (= (mod ~z$w_buff1_used~0_In875920522 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork1_#t~ite14_Out875920522|)) (and (or .cse3 .cse2) (= |P1Thread1of1ForFork1_#t~ite14_Out875920522| ~z$r_buff1_thd2~0_In875920522) (or .cse1 .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In875920522, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In875920522, ~z$w_buff1_used~0=~z$w_buff1_used~0_In875920522, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In875920522} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In875920522, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In875920522, ~z$w_buff1_used~0=~z$w_buff1_used~0_In875920522, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out875920522|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In875920522} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 18:19:41,976 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [805] [805] L766-2-->P1EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_61 1) v_~__unbuffered_cnt~0_60) (= |v_P1Thread1of1ForFork1_#t~ite14_30| v_~z$r_buff1_thd2~0_84) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_61, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_30|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_84, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_60, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_29|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 18:19:41,976 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L809-1-->L815: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (= v_~main$tmp_guard0~0_8 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_18) 1 0) 0) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_18} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_7|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_18, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:19:41,977 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L815-2-->L815-5: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite25_Out-1778705683| |ULTIMATE.start_main_#t~ite24_Out-1778705683|)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-1778705683 256) 0)) (.cse2 (= (mod ~z$w_buff1_used~0_In-1778705683 256) 0))) (or (and .cse0 (= ~z~0_In-1778705683 |ULTIMATE.start_main_#t~ite24_Out-1778705683|) (or .cse1 .cse2)) (and .cse0 (not .cse1) (not .cse2) (= ~z$w_buff1~0_In-1778705683 |ULTIMATE.start_main_#t~ite24_Out-1778705683|)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1778705683, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1778705683, ~z$w_buff1~0=~z$w_buff1~0_In-1778705683, ~z~0=~z~0_In-1778705683} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1778705683, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-1778705683|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1778705683, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-1778705683|, ~z$w_buff1~0=~z$w_buff1~0_In-1778705683, ~z~0=~z~0_In-1778705683} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 18:19:41,977 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [768] [768] L816-->L816-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In-51037365 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd0~0_In-51037365 256)))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite26_Out-51037365|)) (and (= |ULTIMATE.start_main_#t~ite26_Out-51037365| ~z$w_buff0_used~0_In-51037365) (or .cse1 .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-51037365, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-51037365} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-51037365, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-51037365, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-51037365|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 18:19:41,977 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L817-->L817-2: Formula: (let ((.cse0 (= (mod ~z$w_buff1_used~0_In-1957311214 256) 0)) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-1957311214 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-1957311214 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd0~0_In-1957311214 256)))) (or (and (= 0 |ULTIMATE.start_main_#t~ite27_Out-1957311214|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$w_buff1_used~0_In-1957311214 |ULTIMATE.start_main_#t~ite27_Out-1957311214|) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1957311214, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1957311214, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1957311214, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1957311214} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1957311214, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1957311214, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1957311214, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1957311214, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-1957311214|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 18:19:41,978 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L818-->L818-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In1162972327 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd0~0_In1162972327 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite28_Out1162972327|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite28_Out1162972327| ~z$r_buff0_thd0~0_In1162972327)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1162972327, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1162972327} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1162972327, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out1162972327|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1162972327} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 18:19:41,978 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L819-->L819-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd0~0_In-1867632557 256))) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In-1867632557 256))) (.cse2 (= (mod ~z$r_buff0_thd0~0_In-1867632557 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In-1867632557 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite29_Out-1867632557| ~z$r_buff1_thd0~0_In-1867632557) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |ULTIMATE.start_main_#t~ite29_Out-1867632557| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1867632557, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1867632557, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1867632557, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1867632557} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1867632557, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-1867632557|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1867632557, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1867632557, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1867632557} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 18:19:41,980 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L831-->L832: Formula: (and (= v_~z$r_buff0_thd0~0_103 v_~z$r_buff0_thd0~0_102) (not (= (mod v_~weak$$choice2~0_23 256) 0))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_103, ~weak$$choice2~0=v_~weak$$choice2~0_23} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_102, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_6|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_10|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_6|, ~weak$$choice2~0=v_~weak$$choice2~0_23} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 18:19:41,981 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L834-->L837-1: Formula: (and (= v_~z$mem_tmp~0_11 v_~z~0_133) (= (mod v_~main$tmp_guard1~0_9 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (not (= 0 (mod v_~z$flush_delayed~0_21 256))) (= 0 v_~z$flush_delayed~0_20)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_11, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_9, ~z$flush_delayed~0=v_~z$flush_delayed~0_21} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_11, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_18|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_9, ~z$flush_delayed~0=v_~z$flush_delayed~0_20, ~z~0=v_~z~0_133, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:19:41,981 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L837-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:19:42,036 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_cbb69b23-2ffa-4739-a536-4c1fc45c20c9/bin/uautomizer/witness.graphml [2019-12-07 18:19:42,037 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:19:42,038 INFO L168 Benchmark]: Toolchain (without parser) took 116073.14 ms. Allocated memory was 1.0 GB in the beginning and 7.8 GB in the end (delta: 6.8 GB). Free memory was 939.2 MB in the beginning and 4.0 GB in the end (delta: -3.0 GB). Peak memory consumption was 3.7 GB. Max. memory is 11.5 GB. [2019-12-07 18:19:42,038 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:19:42,038 INFO L168 Benchmark]: CACSL2BoogieTranslator took 384.55 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 102.2 MB). Free memory was 939.2 MB in the beginning and 1.1 GB in the end (delta: -133.5 MB). Peak memory consumption was 19.3 MB. Max. memory is 11.5 GB. [2019-12-07 18:19:42,039 INFO L168 Benchmark]: Boogie Procedure Inliner took 39.34 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:19:42,039 INFO L168 Benchmark]: Boogie Preprocessor took 27.32 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:19:42,039 INFO L168 Benchmark]: RCFGBuilder took 396.16 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 49.8 MB). Peak memory consumption was 49.8 MB. Max. memory is 11.5 GB. [2019-12-07 18:19:42,039 INFO L168 Benchmark]: TraceAbstraction took 115153.77 ms. Allocated memory was 1.1 GB in the beginning and 7.8 GB in the end (delta: 6.7 GB). Free memory was 1.0 GB in the beginning and 4.0 GB in the end (delta: -3.0 GB). Peak memory consumption was 3.6 GB. Max. memory is 11.5 GB. [2019-12-07 18:19:42,040 INFO L168 Benchmark]: Witness Printer took 68.58 ms. Allocated memory is still 7.8 GB. Free memory was 4.0 GB in the beginning and 4.0 GB in the end (delta: 37.8 MB). Peak memory consumption was 37.8 MB. Max. memory is 11.5 GB. [2019-12-07 18:19:42,041 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 384.55 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 102.2 MB). Free memory was 939.2 MB in the beginning and 1.1 GB in the end (delta: -133.5 MB). Peak memory consumption was 19.3 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 39.34 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 27.32 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 396.16 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 49.8 MB). Peak memory consumption was 49.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 115153.77 ms. Allocated memory was 1.1 GB in the beginning and 7.8 GB in the end (delta: 6.7 GB). Free memory was 1.0 GB in the beginning and 4.0 GB in the end (delta: -3.0 GB). Peak memory consumption was 3.6 GB. Max. memory is 11.5 GB. * Witness Printer took 68.58 ms. Allocated memory is still 7.8 GB. Free memory was 4.0 GB in the beginning and 4.0 GB in the end (delta: 37.8 MB). Peak memory consumption was 37.8 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.0s, 174 ProgramPointsBefore, 93 ProgramPointsAfterwards, 211 TransitionsBefore, 104 TransitionsAfterwards, 17114 CoEnabledTransitionPairs, 8 FixpointIterations, 31 TrivialSequentialCompositions, 44 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 37 ConcurrentYvCompositions, 30 ChoiceCompositions, 6114 VarBasedMoverChecksPositive, 254 VarBasedMoverChecksNegative, 80 SemBasedMoverChecksPositive, 255 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.9s, 0 MoverChecksTotal, 86146 CheckedPairsTotal, 112 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L805] FCALL, FORK 0 pthread_create(&t2040, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L732] 1 z$r_buff1_thd0 = z$r_buff0_thd0 [L733] 1 z$r_buff1_thd1 = z$r_buff0_thd1 [L734] 1 z$r_buff1_thd2 = z$r_buff0_thd2 [L735] 1 z$r_buff1_thd3 = z$r_buff0_thd3 [L736] 1 z$r_buff0_thd1 = (_Bool)1 [L739] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L742] EXPR 1 z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L807] FCALL, FORK 0 pthread_create(&t2041, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L742] 1 z = z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) [L743] 1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used [L744] 1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used [L809] FCALL, FORK 0 pthread_create(&t2042, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L756] 2 x = 2 [L759] 2 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L762] EXPR 2 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L776] 3 __unbuffered_p2_EAX = y [L779] 3 z = 1 VAL [__unbuffered_cnt=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z)=2, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=2] [L782] 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z)=2, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=2] [L783] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L784] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L785] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L762] 2 z = z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) [L763] 2 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used [L764] 2 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used [L765] 2 z$r_buff0_thd2 = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 [L815] EXPR 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L815] 0 z = z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) [L816] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L817] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L818] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L819] 0 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L822] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L823] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L824] 0 z$flush_delayed = weak$$choice2 [L825] 0 z$mem_tmp = z VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L826] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L826] 0 z = !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) [L827] EXPR 0 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L827] 0 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) [L828] EXPR 0 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L828] 0 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) [L829] EXPR 0 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L829] 0 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) [L830] EXPR 0 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L830] 0 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L832] EXPR 0 weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L832] 0 z$r_buff1_thd0 = weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L833] 0 main$tmp_guard1 = !(x == 2 && z == 2 && __unbuffered_p2_EAX == 1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=1, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 165 locations, 2 error locations. Result: UNSAFE, OverallTime: 115.0s, OverallIterations: 29, TraceHistogramMax: 1, AutomataDifference: 27.3s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 5021 SDtfs, 5631 SDslu, 14393 SDs, 0 SdLazy, 9735 SolverSat, 440 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 387 GetRequests, 64 SyntacticMatches, 29 SemanticMatches, 294 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1606 ImplicationChecksByTransitivity, 3.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=225509occurred in iteration=7, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 69.5s AutomataMinimizationTime, 28 MinimizatonAttempts, 406660 StatesRemovedByMinimization, 26 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.6s InterpolantComputationTime, 1406 NumberOfCodeBlocks, 1406 NumberOfCodeBlocksAsserted, 29 NumberOfCheckSat, 1310 ConstructedInterpolants, 0 QuantifiedInterpolants, 329673 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 28 InterpolantComputations, 28 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...