./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe017_pso.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_3a3f6abc-21de-42de-8232-23c735660788/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_3a3f6abc-21de-42de-8232-23c735660788/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_3a3f6abc-21de-42de-8232-23c735660788/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_3a3f6abc-21de-42de-8232-23c735660788/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe017_pso.oepc.i -s /tmp/vcloud-vcloud-master/worker/run_dir_3a3f6abc-21de-42de-8232-23c735660788/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_3a3f6abc-21de-42de-8232-23c735660788/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1cc00d91a541289138f2f75d8b0086a71097655d ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 15:56:14,830 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 15:56:14,831 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 15:56:14,839 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 15:56:14,839 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 15:56:14,840 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 15:56:14,840 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 15:56:14,842 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 15:56:14,843 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 15:56:14,844 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 15:56:14,844 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 15:56:14,845 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 15:56:14,845 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 15:56:14,846 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 15:56:14,847 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 15:56:14,847 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 15:56:14,848 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 15:56:14,848 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 15:56:14,850 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 15:56:14,851 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 15:56:14,852 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 15:56:14,853 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 15:56:14,854 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 15:56:14,854 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 15:56:14,856 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 15:56:14,856 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 15:56:14,856 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 15:56:14,857 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 15:56:14,857 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 15:56:14,858 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 15:56:14,858 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 15:56:14,858 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 15:56:14,858 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 15:56:14,859 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 15:56:14,859 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 15:56:14,860 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 15:56:14,860 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 15:56:14,860 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 15:56:14,860 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 15:56:14,861 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 15:56:14,861 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 15:56:14,862 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_3a3f6abc-21de-42de-8232-23c735660788/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 15:56:14,871 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 15:56:14,872 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 15:56:14,872 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 15:56:14,872 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 15:56:14,873 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 15:56:14,873 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 15:56:14,873 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 15:56:14,873 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 15:56:14,873 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 15:56:14,873 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 15:56:14,873 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 15:56:14,874 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 15:56:14,874 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 15:56:14,874 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 15:56:14,874 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 15:56:14,874 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 15:56:14,874 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 15:56:14,874 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 15:56:14,875 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 15:56:14,875 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 15:56:14,875 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 15:56:14,875 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 15:56:14,875 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 15:56:14,875 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 15:56:14,875 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 15:56:14,875 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 15:56:14,876 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 15:56:14,876 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 15:56:14,876 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 15:56:14,876 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_3a3f6abc-21de-42de-8232-23c735660788/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1cc00d91a541289138f2f75d8b0086a71097655d [2019-12-07 15:56:14,976 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 15:56:14,984 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 15:56:14,986 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 15:56:14,987 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 15:56:14,987 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 15:56:14,988 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_3a3f6abc-21de-42de-8232-23c735660788/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe017_pso.oepc.i [2019-12-07 15:56:15,023 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_3a3f6abc-21de-42de-8232-23c735660788/bin/uautomizer/data/094fc8975/cde2d11137444bdd8968e8999e78a1ee/FLAGc82acbc35 [2019-12-07 15:56:15,540 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 15:56:15,541 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_3a3f6abc-21de-42de-8232-23c735660788/sv-benchmarks/c/pthread-wmm/safe017_pso.oepc.i [2019-12-07 15:56:15,551 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_3a3f6abc-21de-42de-8232-23c735660788/bin/uautomizer/data/094fc8975/cde2d11137444bdd8968e8999e78a1ee/FLAGc82acbc35 [2019-12-07 15:56:16,009 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_3a3f6abc-21de-42de-8232-23c735660788/bin/uautomizer/data/094fc8975/cde2d11137444bdd8968e8999e78a1ee [2019-12-07 15:56:16,011 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 15:56:16,012 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 15:56:16,013 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 15:56:16,013 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 15:56:16,016 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 15:56:16,017 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 03:56:16" (1/1) ... [2019-12-07 15:56:16,019 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@227d51b0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:56:16, skipping insertion in model container [2019-12-07 15:56:16,019 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 03:56:16" (1/1) ... [2019-12-07 15:56:16,025 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 15:56:16,055 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 15:56:16,310 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 15:56:16,318 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 15:56:16,362 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 15:56:16,408 INFO L208 MainTranslator]: Completed translation [2019-12-07 15:56:16,409 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:56:16 WrapperNode [2019-12-07 15:56:16,409 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 15:56:16,409 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 15:56:16,409 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 15:56:16,409 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 15:56:16,416 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:56:16" (1/1) ... [2019-12-07 15:56:16,429 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:56:16" (1/1) ... [2019-12-07 15:56:16,452 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 15:56:16,452 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 15:56:16,452 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 15:56:16,452 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 15:56:16,459 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:56:16" (1/1) ... [2019-12-07 15:56:16,459 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:56:16" (1/1) ... [2019-12-07 15:56:16,463 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:56:16" (1/1) ... [2019-12-07 15:56:16,463 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:56:16" (1/1) ... [2019-12-07 15:56:16,470 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:56:16" (1/1) ... [2019-12-07 15:56:16,473 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:56:16" (1/1) ... [2019-12-07 15:56:16,475 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:56:16" (1/1) ... [2019-12-07 15:56:16,479 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 15:56:16,479 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 15:56:16,479 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 15:56:16,479 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 15:56:16,480 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:56:16" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_3a3f6abc-21de-42de-8232-23c735660788/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 15:56:16,523 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 15:56:16,523 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 15:56:16,523 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 15:56:16,523 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 15:56:16,523 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 15:56:16,523 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 15:56:16,523 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 15:56:16,523 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 15:56:16,523 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 15:56:16,524 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 15:56:16,524 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 15:56:16,524 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 15:56:16,524 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 15:56:16,525 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 15:56:16,885 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 15:56:16,886 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 15:56:16,887 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 03:56:16 BoogieIcfgContainer [2019-12-07 15:56:16,887 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 15:56:16,888 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 15:56:16,888 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 15:56:16,891 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 15:56:16,891 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 03:56:16" (1/3) ... [2019-12-07 15:56:16,892 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7d911232 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 03:56:16, skipping insertion in model container [2019-12-07 15:56:16,892 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:56:16" (2/3) ... [2019-12-07 15:56:16,892 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7d911232 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 03:56:16, skipping insertion in model container [2019-12-07 15:56:16,892 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 03:56:16" (3/3) ... [2019-12-07 15:56:16,894 INFO L109 eAbstractionObserver]: Analyzing ICFG safe017_pso.oepc.i [2019-12-07 15:56:16,902 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 15:56:16,903 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 15:56:16,909 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 15:56:16,910 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 15:56:16,938 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,938 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,938 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,939 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,939 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,939 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,939 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,939 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,940 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,940 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,940 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,940 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,940 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,941 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,941 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,941 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,941 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,941 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,941 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,942 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,942 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,942 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,942 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,942 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,943 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,943 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,943 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,943 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,943 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,943 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,944 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,944 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,944 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,944 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,945 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,945 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,945 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,945 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,945 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,946 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,946 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,946 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,946 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,946 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,946 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,947 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,947 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,947 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,947 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,947 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,947 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,948 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,948 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,948 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,948 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,948 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,948 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,949 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,949 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,949 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,949 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,949 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,949 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,950 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,950 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,950 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,950 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,951 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,951 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,951 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,951 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,951 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,951 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,952 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,952 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,952 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,952 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,952 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,952 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,953 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,953 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,953 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,953 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,953 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,954 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,954 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,954 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,954 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,954 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,954 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,955 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,955 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,955 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,955 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:56:16,969 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 15:56:16,985 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 15:56:16,985 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 15:56:16,985 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 15:56:16,985 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 15:56:16,985 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 15:56:16,986 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 15:56:16,986 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 15:56:16,986 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 15:56:16,996 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 173 places, 210 transitions [2019-12-07 15:56:16,997 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 173 places, 210 transitions [2019-12-07 15:56:17,060 INFO L134 PetriNetUnfolder]: 47/207 cut-off events. [2019-12-07 15:56:17,061 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 15:56:17,071 INFO L76 FinitePrefix]: Finished finitePrefix Result has 217 conditions, 207 events. 47/207 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 585 event pairs. 9/167 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 15:56:17,085 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 173 places, 210 transitions [2019-12-07 15:56:17,112 INFO L134 PetriNetUnfolder]: 47/207 cut-off events. [2019-12-07 15:56:17,112 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 15:56:17,117 INFO L76 FinitePrefix]: Finished finitePrefix Result has 217 conditions, 207 events. 47/207 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 585 event pairs. 9/167 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 15:56:17,131 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 17114 [2019-12-07 15:56:17,131 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 15:56:19,983 WARN L192 SmtUtils]: Spent 135.00 ms on a formula simplification. DAG size of input: 85 DAG size of output: 83 [2019-12-07 15:56:20,065 INFO L206 etLargeBlockEncoding]: Checked pairs total: 78185 [2019-12-07 15:56:20,065 INFO L214 etLargeBlockEncoding]: Total number of compositions: 113 [2019-12-07 15:56:20,067 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 94 places, 104 transitions [2019-12-07 15:56:33,123 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 112926 states. [2019-12-07 15:56:33,125 INFO L276 IsEmpty]: Start isEmpty. Operand 112926 states. [2019-12-07 15:56:33,128 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-12-07 15:56:33,128 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:56:33,129 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-12-07 15:56:33,129 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:56:33,133 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:56:33,133 INFO L82 PathProgramCache]: Analyzing trace with hash 844394, now seen corresponding path program 1 times [2019-12-07 15:56:33,138 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:56:33,138 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [262459338] [2019-12-07 15:56:33,138 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:56:33,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:56:33,264 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:56:33,265 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [262459338] [2019-12-07 15:56:33,265 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:56:33,265 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 15:56:33,266 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1950552353] [2019-12-07 15:56:33,269 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:56:33,269 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:56:33,278 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:56:33,278 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:56:33,279 INFO L87 Difference]: Start difference. First operand 112926 states. Second operand 3 states. [2019-12-07 15:56:34,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:56:34,001 INFO L93 Difference]: Finished difference Result 112536 states and 479624 transitions. [2019-12-07 15:56:34,001 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:56:34,002 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-12-07 15:56:34,002 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:56:34,756 INFO L225 Difference]: With dead ends: 112536 [2019-12-07 15:56:34,756 INFO L226 Difference]: Without dead ends: 110184 [2019-12-07 15:56:34,757 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:56:39,375 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110184 states. [2019-12-07 15:56:40,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110184 to 110184. [2019-12-07 15:56:40,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110184 states. [2019-12-07 15:56:41,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110184 states to 110184 states and 470020 transitions. [2019-12-07 15:56:41,284 INFO L78 Accepts]: Start accepts. Automaton has 110184 states and 470020 transitions. Word has length 3 [2019-12-07 15:56:41,284 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:56:41,285 INFO L462 AbstractCegarLoop]: Abstraction has 110184 states and 470020 transitions. [2019-12-07 15:56:41,285 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:56:41,285 INFO L276 IsEmpty]: Start isEmpty. Operand 110184 states and 470020 transitions. [2019-12-07 15:56:41,288 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 15:56:41,288 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:56:41,288 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:56:41,289 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:56:41,289 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:56:41,289 INFO L82 PathProgramCache]: Analyzing trace with hash -418531443, now seen corresponding path program 1 times [2019-12-07 15:56:41,289 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:56:41,289 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706346926] [2019-12-07 15:56:41,289 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:56:41,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:56:41,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:56:41,352 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1706346926] [2019-12-07 15:56:41,352 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:56:41,352 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:56:41,352 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [815895304] [2019-12-07 15:56:41,353 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 15:56:41,353 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:56:41,354 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 15:56:41,354 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:56:41,354 INFO L87 Difference]: Start difference. First operand 110184 states and 470020 transitions. Second operand 4 states. [2019-12-07 15:56:42,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:56:42,347 INFO L93 Difference]: Finished difference Result 172298 states and 706272 transitions. [2019-12-07 15:56:42,348 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 15:56:42,348 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 15:56:42,348 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:56:43,156 INFO L225 Difference]: With dead ends: 172298 [2019-12-07 15:56:43,156 INFO L226 Difference]: Without dead ends: 172249 [2019-12-07 15:56:43,157 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:56:49,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172249 states. [2019-12-07 15:56:51,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172249 to 156321. [2019-12-07 15:56:51,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156321 states. [2019-12-07 15:56:51,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156321 states to 156321 states and 647667 transitions. [2019-12-07 15:56:51,582 INFO L78 Accepts]: Start accepts. Automaton has 156321 states and 647667 transitions. Word has length 11 [2019-12-07 15:56:51,582 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:56:51,582 INFO L462 AbstractCegarLoop]: Abstraction has 156321 states and 647667 transitions. [2019-12-07 15:56:51,582 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 15:56:51,583 INFO L276 IsEmpty]: Start isEmpty. Operand 156321 states and 647667 transitions. [2019-12-07 15:56:51,590 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 15:56:51,590 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:56:51,590 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:56:51,590 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:56:51,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:56:51,591 INFO L82 PathProgramCache]: Analyzing trace with hash -986312255, now seen corresponding path program 1 times [2019-12-07 15:56:51,591 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:56:51,591 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [29416826] [2019-12-07 15:56:51,591 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:56:51,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:56:51,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:56:51,663 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [29416826] [2019-12-07 15:56:51,663 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:56:51,663 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:56:51,663 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [614166378] [2019-12-07 15:56:51,664 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 15:56:51,664 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:56:51,664 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 15:56:51,664 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:56:51,664 INFO L87 Difference]: Start difference. First operand 156321 states and 647667 transitions. Second operand 4 states. [2019-12-07 15:56:52,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:56:52,654 INFO L93 Difference]: Finished difference Result 198223 states and 807102 transitions. [2019-12-07 15:56:52,655 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 15:56:52,655 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 15:56:52,655 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:56:53,674 INFO L225 Difference]: With dead ends: 198223 [2019-12-07 15:56:53,674 INFO L226 Difference]: Without dead ends: 198223 [2019-12-07 15:56:53,674 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:57:00,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198223 states. [2019-12-07 15:57:02,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198223 to 177721. [2019-12-07 15:57:02,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 177721 states. [2019-12-07 15:57:03,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177721 states to 177721 states and 730453 transitions. [2019-12-07 15:57:03,481 INFO L78 Accepts]: Start accepts. Automaton has 177721 states and 730453 transitions. Word has length 13 [2019-12-07 15:57:03,482 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:57:03,482 INFO L462 AbstractCegarLoop]: Abstraction has 177721 states and 730453 transitions. [2019-12-07 15:57:03,482 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 15:57:03,482 INFO L276 IsEmpty]: Start isEmpty. Operand 177721 states and 730453 transitions. [2019-12-07 15:57:03,484 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 15:57:03,485 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:57:03,485 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:57:03,485 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:57:03,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:57:03,485 INFO L82 PathProgramCache]: Analyzing trace with hash -1176456771, now seen corresponding path program 1 times [2019-12-07 15:57:03,485 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:57:03,485 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347014168] [2019-12-07 15:57:03,486 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:57:03,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:57:03,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:57:03,533 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347014168] [2019-12-07 15:57:03,533 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:57:03,533 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:57:03,533 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1109173292] [2019-12-07 15:57:03,534 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 15:57:03,534 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:57:03,534 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 15:57:03,534 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:57:03,534 INFO L87 Difference]: Start difference. First operand 177721 states and 730453 transitions. Second operand 4 states. [2019-12-07 15:57:04,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:57:04,768 INFO L93 Difference]: Finished difference Result 245470 states and 990922 transitions. [2019-12-07 15:57:04,768 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 15:57:04,768 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 15:57:04,769 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:57:05,412 INFO L225 Difference]: With dead ends: 245470 [2019-12-07 15:57:05,412 INFO L226 Difference]: Without dead ends: 245407 [2019-12-07 15:57:05,412 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:57:10,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 245407 states. [2019-12-07 15:57:16,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 245407 to 199120. [2019-12-07 15:57:16,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 199120 states. [2019-12-07 15:57:17,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199120 states to 199120 states and 817885 transitions. [2019-12-07 15:57:17,132 INFO L78 Accepts]: Start accepts. Automaton has 199120 states and 817885 transitions. Word has length 13 [2019-12-07 15:57:17,133 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:57:17,133 INFO L462 AbstractCegarLoop]: Abstraction has 199120 states and 817885 transitions. [2019-12-07 15:57:17,133 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 15:57:17,133 INFO L276 IsEmpty]: Start isEmpty. Operand 199120 states and 817885 transitions. [2019-12-07 15:57:17,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 15:57:17,158 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:57:17,158 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:57:17,159 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:57:17,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:57:17,159 INFO L82 PathProgramCache]: Analyzing trace with hash -1822366328, now seen corresponding path program 1 times [2019-12-07 15:57:17,159 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:57:17,159 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079586242] [2019-12-07 15:57:17,159 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:57:17,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:57:17,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:57:17,223 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2079586242] [2019-12-07 15:57:17,223 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:57:17,223 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:57:17,223 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [862956519] [2019-12-07 15:57:17,224 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:57:17,224 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:57:17,224 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:57:17,224 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:57:17,224 INFO L87 Difference]: Start difference. First operand 199120 states and 817885 transitions. Second operand 5 states. [2019-12-07 15:57:18,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:57:18,745 INFO L93 Difference]: Finished difference Result 293007 states and 1175742 transitions. [2019-12-07 15:57:18,746 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 15:57:18,746 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 15:57:18,746 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:57:19,519 INFO L225 Difference]: With dead ends: 293007 [2019-12-07 15:57:19,519 INFO L226 Difference]: Without dead ends: 292944 [2019-12-07 15:57:19,520 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:57:25,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 292944 states. [2019-12-07 15:57:29,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 292944 to 209496. [2019-12-07 15:57:29,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 209496 states. [2019-12-07 15:57:29,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209496 states to 209496 states and 856138 transitions. [2019-12-07 15:57:29,770 INFO L78 Accepts]: Start accepts. Automaton has 209496 states and 856138 transitions. Word has length 19 [2019-12-07 15:57:29,770 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:57:29,770 INFO L462 AbstractCegarLoop]: Abstraction has 209496 states and 856138 transitions. [2019-12-07 15:57:29,770 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:57:29,770 INFO L276 IsEmpty]: Start isEmpty. Operand 209496 states and 856138 transitions. [2019-12-07 15:57:29,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 15:57:29,784 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:57:29,784 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:57:29,784 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:57:29,784 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:57:29,784 INFO L82 PathProgramCache]: Analyzing trace with hash -2012510844, now seen corresponding path program 1 times [2019-12-07 15:57:29,784 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:57:29,785 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930800136] [2019-12-07 15:57:29,785 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:57:29,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:57:29,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:57:29,844 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1930800136] [2019-12-07 15:57:29,844 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:57:29,844 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:57:29,844 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1827253582] [2019-12-07 15:57:29,844 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:57:29,844 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:57:29,844 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:57:29,845 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:57:29,845 INFO L87 Difference]: Start difference. First operand 209496 states and 856138 transitions. Second operand 5 states. [2019-12-07 15:57:31,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:57:31,949 INFO L93 Difference]: Finished difference Result 317773 states and 1271331 transitions. [2019-12-07 15:57:31,949 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 15:57:31,949 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 15:57:31,950 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:57:35,735 INFO L225 Difference]: With dead ends: 317773 [2019-12-07 15:57:35,735 INFO L226 Difference]: Without dead ends: 317626 [2019-12-07 15:57:35,735 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:57:41,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 317626 states. [2019-12-07 15:57:45,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 317626 to 221774. [2019-12-07 15:57:45,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 221774 states. [2019-12-07 15:57:45,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221774 states to 221774 states and 905581 transitions. [2019-12-07 15:57:45,668 INFO L78 Accepts]: Start accepts. Automaton has 221774 states and 905581 transitions. Word has length 19 [2019-12-07 15:57:45,668 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:57:45,669 INFO L462 AbstractCegarLoop]: Abstraction has 221774 states and 905581 transitions. [2019-12-07 15:57:45,669 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:57:45,669 INFO L276 IsEmpty]: Start isEmpty. Operand 221774 states and 905581 transitions. [2019-12-07 15:57:45,682 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 15:57:45,682 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:57:45,682 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:57:45,682 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:57:45,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:57:45,682 INFO L82 PathProgramCache]: Analyzing trace with hash 582667357, now seen corresponding path program 1 times [2019-12-07 15:57:45,683 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:57:45,683 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [319419560] [2019-12-07 15:57:45,683 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:57:45,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:57:45,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:57:45,733 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [319419560] [2019-12-07 15:57:45,733 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:57:45,733 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:57:45,733 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1943914992] [2019-12-07 15:57:45,734 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:57:45,734 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:57:45,734 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:57:45,734 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:57:45,734 INFO L87 Difference]: Start difference. First operand 221774 states and 905581 transitions. Second operand 5 states. [2019-12-07 15:57:47,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:57:47,744 INFO L93 Difference]: Finished difference Result 321222 states and 1287889 transitions. [2019-12-07 15:57:47,745 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 15:57:47,745 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 15:57:47,745 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:57:48,576 INFO L225 Difference]: With dead ends: 321222 [2019-12-07 15:57:48,576 INFO L226 Difference]: Without dead ends: 321159 [2019-12-07 15:57:48,576 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:57:55,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321159 states. [2019-12-07 15:57:58,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321159 to 239204. [2019-12-07 15:57:58,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 239204 states. [2019-12-07 15:57:59,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 239204 states to 239204 states and 975197 transitions. [2019-12-07 15:57:59,641 INFO L78 Accepts]: Start accepts. Automaton has 239204 states and 975197 transitions. Word has length 19 [2019-12-07 15:57:59,642 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:57:59,642 INFO L462 AbstractCegarLoop]: Abstraction has 239204 states and 975197 transitions. [2019-12-07 15:57:59,642 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:57:59,642 INFO L276 IsEmpty]: Start isEmpty. Operand 239204 states and 975197 transitions. [2019-12-07 15:57:59,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 15:57:59,703 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:57:59,703 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:57:59,703 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:57:59,703 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:57:59,703 INFO L82 PathProgramCache]: Analyzing trace with hash 187920100, now seen corresponding path program 1 times [2019-12-07 15:57:59,703 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:57:59,703 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [288191707] [2019-12-07 15:57:59,703 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:57:59,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:57:59,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:57:59,753 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [288191707] [2019-12-07 15:57:59,753 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:57:59,753 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 15:57:59,753 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414060261] [2019-12-07 15:57:59,754 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:57:59,754 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:57:59,754 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:57:59,754 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:57:59,754 INFO L87 Difference]: Start difference. First operand 239204 states and 975197 transitions. Second operand 6 states. [2019-12-07 15:58:04,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:04,158 INFO L93 Difference]: Finished difference Result 286551 states and 1154938 transitions. [2019-12-07 15:58:04,158 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 15:58:04,159 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2019-12-07 15:58:04,159 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:04,898 INFO L225 Difference]: With dead ends: 286551 [2019-12-07 15:58:04,898 INFO L226 Difference]: Without dead ends: 286404 [2019-12-07 15:58:04,898 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=81, Invalid=191, Unknown=0, NotChecked=0, Total=272 [2019-12-07 15:58:10,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 286404 states. [2019-12-07 15:58:13,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 286404 to 197306. [2019-12-07 15:58:13,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 197306 states. [2019-12-07 15:58:14,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197306 states to 197306 states and 809085 transitions. [2019-12-07 15:58:14,222 INFO L78 Accepts]: Start accepts. Automaton has 197306 states and 809085 transitions. Word has length 25 [2019-12-07 15:58:14,223 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:14,223 INFO L462 AbstractCegarLoop]: Abstraction has 197306 states and 809085 transitions. [2019-12-07 15:58:14,223 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:58:14,223 INFO L276 IsEmpty]: Start isEmpty. Operand 197306 states and 809085 transitions. [2019-12-07 15:58:14,293 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 15:58:14,293 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:14,293 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:14,293 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:14,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:14,294 INFO L82 PathProgramCache]: Analyzing trace with hash 2036011912, now seen corresponding path program 1 times [2019-12-07 15:58:14,294 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:14,294 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1493461894] [2019-12-07 15:58:14,294 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:14,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:14,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:14,326 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1493461894] [2019-12-07 15:58:14,326 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:14,326 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:58:14,326 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [197259613] [2019-12-07 15:58:14,326 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:58:14,327 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:14,327 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:58:14,327 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:58:14,327 INFO L87 Difference]: Start difference. First operand 197306 states and 809085 transitions. Second operand 3 states. [2019-12-07 15:58:14,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:14,438 INFO L93 Difference]: Finished difference Result 40605 states and 130023 transitions. [2019-12-07 15:58:14,438 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:58:14,438 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 15:58:14,439 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:14,495 INFO L225 Difference]: With dead ends: 40605 [2019-12-07 15:58:14,495 INFO L226 Difference]: Without dead ends: 40605 [2019-12-07 15:58:14,495 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:58:14,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40605 states. [2019-12-07 15:58:15,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40605 to 40605. [2019-12-07 15:58:15,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40605 states. [2019-12-07 15:58:15,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40605 states to 40605 states and 130023 transitions. [2019-12-07 15:58:15,492 INFO L78 Accepts]: Start accepts. Automaton has 40605 states and 130023 transitions. Word has length 27 [2019-12-07 15:58:15,492 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:15,492 INFO L462 AbstractCegarLoop]: Abstraction has 40605 states and 130023 transitions. [2019-12-07 15:58:15,492 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:58:15,493 INFO L276 IsEmpty]: Start isEmpty. Operand 40605 states and 130023 transitions. [2019-12-07 15:58:15,510 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2019-12-07 15:58:15,510 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:15,510 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:15,511 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:15,511 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:15,511 INFO L82 PathProgramCache]: Analyzing trace with hash 1388376233, now seen corresponding path program 1 times [2019-12-07 15:58:15,511 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:15,511 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2112214846] [2019-12-07 15:58:15,511 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:15,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:15,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:15,575 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2112214846] [2019-12-07 15:58:15,575 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:15,575 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 15:58:15,575 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [129250111] [2019-12-07 15:58:15,576 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 15:58:15,576 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:15,576 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 15:58:15,576 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 15:58:15,576 INFO L87 Difference]: Start difference. First operand 40605 states and 130023 transitions. Second operand 7 states. [2019-12-07 15:58:16,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:16,101 INFO L93 Difference]: Finished difference Result 58436 states and 183037 transitions. [2019-12-07 15:58:16,101 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 15:58:16,101 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 39 [2019-12-07 15:58:16,102 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:16,186 INFO L225 Difference]: With dead ends: 58436 [2019-12-07 15:58:16,186 INFO L226 Difference]: Without dead ends: 58408 [2019-12-07 15:58:16,186 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2019-12-07 15:58:16,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58408 states. [2019-12-07 15:58:16,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58408 to 51886. [2019-12-07 15:58:16,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51886 states. [2019-12-07 15:58:17,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51886 states to 51886 states and 163749 transitions. [2019-12-07 15:58:17,069 INFO L78 Accepts]: Start accepts. Automaton has 51886 states and 163749 transitions. Word has length 39 [2019-12-07 15:58:17,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:17,070 INFO L462 AbstractCegarLoop]: Abstraction has 51886 states and 163749 transitions. [2019-12-07 15:58:17,070 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 15:58:17,070 INFO L276 IsEmpty]: Start isEmpty. Operand 51886 states and 163749 transitions. [2019-12-07 15:58:17,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2019-12-07 15:58:17,093 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:17,093 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:17,093 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:17,093 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:17,093 INFO L82 PathProgramCache]: Analyzing trace with hash -1127558066, now seen corresponding path program 1 times [2019-12-07 15:58:17,093 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:17,094 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1899255178] [2019-12-07 15:58:17,094 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:17,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:17,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:17,152 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1899255178] [2019-12-07 15:58:17,152 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:17,152 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 15:58:17,152 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1441320691] [2019-12-07 15:58:17,152 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 15:58:17,152 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:17,153 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 15:58:17,153 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 15:58:17,153 INFO L87 Difference]: Start difference. First operand 51886 states and 163749 transitions. Second operand 7 states. [2019-12-07 15:58:17,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:17,728 INFO L93 Difference]: Finished difference Result 70067 states and 218058 transitions. [2019-12-07 15:58:17,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 15:58:17,728 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 39 [2019-12-07 15:58:17,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:17,828 INFO L225 Difference]: With dead ends: 70067 [2019-12-07 15:58:17,828 INFO L226 Difference]: Without dead ends: 70039 [2019-12-07 15:58:17,829 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2019-12-07 15:58:18,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70039 states. [2019-12-07 15:58:19,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70039 to 55777. [2019-12-07 15:58:19,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55777 states. [2019-12-07 15:58:19,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55777 states to 55777 states and 175822 transitions. [2019-12-07 15:58:19,101 INFO L78 Accepts]: Start accepts. Automaton has 55777 states and 175822 transitions. Word has length 39 [2019-12-07 15:58:19,101 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:19,101 INFO L462 AbstractCegarLoop]: Abstraction has 55777 states and 175822 transitions. [2019-12-07 15:58:19,101 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 15:58:19,101 INFO L276 IsEmpty]: Start isEmpty. Operand 55777 states and 175822 transitions. [2019-12-07 15:58:19,132 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2019-12-07 15:58:19,132 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:19,133 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:19,133 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:19,133 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:19,133 INFO L82 PathProgramCache]: Analyzing trace with hash -305557997, now seen corresponding path program 1 times [2019-12-07 15:58:19,133 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:19,133 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1171666943] [2019-12-07 15:58:19,133 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:19,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:19,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:19,165 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1171666943] [2019-12-07 15:58:19,166 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:19,166 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:58:19,166 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1082430494] [2019-12-07 15:58:19,166 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:58:19,166 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:19,167 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:58:19,167 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:58:19,167 INFO L87 Difference]: Start difference. First operand 55777 states and 175822 transitions. Second operand 3 states. [2019-12-07 15:58:19,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:19,371 INFO L93 Difference]: Finished difference Result 66297 states and 209748 transitions. [2019-12-07 15:58:19,372 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:58:19,372 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 43 [2019-12-07 15:58:19,372 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:19,470 INFO L225 Difference]: With dead ends: 66297 [2019-12-07 15:58:19,470 INFO L226 Difference]: Without dead ends: 66297 [2019-12-07 15:58:19,471 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:58:19,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66297 states. [2019-12-07 15:58:20,324 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66297 to 57725. [2019-12-07 15:58:20,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57725 states. [2019-12-07 15:58:20,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57725 states to 57725 states and 183852 transitions. [2019-12-07 15:58:20,430 INFO L78 Accepts]: Start accepts. Automaton has 57725 states and 183852 transitions. Word has length 43 [2019-12-07 15:58:20,431 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:20,431 INFO L462 AbstractCegarLoop]: Abstraction has 57725 states and 183852 transitions. [2019-12-07 15:58:20,431 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:58:20,431 INFO L276 IsEmpty]: Start isEmpty. Operand 57725 states and 183852 transitions. [2019-12-07 15:58:20,748 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2019-12-07 15:58:20,749 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:20,749 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:20,749 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:20,749 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:20,749 INFO L82 PathProgramCache]: Analyzing trace with hash 152559268, now seen corresponding path program 1 times [2019-12-07 15:58:20,749 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:20,749 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1692908470] [2019-12-07 15:58:20,750 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:20,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:20,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:20,799 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1692908470] [2019-12-07 15:58:20,799 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:20,799 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 15:58:20,800 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1319992393] [2019-12-07 15:58:20,800 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:58:20,800 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:20,800 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:58:20,800 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:58:20,800 INFO L87 Difference]: Start difference. First operand 57725 states and 183852 transitions. Second operand 5 states. [2019-12-07 15:58:21,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:21,326 INFO L93 Difference]: Finished difference Result 77492 states and 244109 transitions. [2019-12-07 15:58:21,326 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 15:58:21,326 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 43 [2019-12-07 15:58:21,326 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:21,437 INFO L225 Difference]: With dead ends: 77492 [2019-12-07 15:58:21,438 INFO L226 Difference]: Without dead ends: 77492 [2019-12-07 15:58:21,438 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:58:21,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77492 states. [2019-12-07 15:58:22,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77492 to 68509. [2019-12-07 15:58:22,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68509 states. [2019-12-07 15:58:22,596 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68509 states to 68509 states and 217346 transitions. [2019-12-07 15:58:22,596 INFO L78 Accepts]: Start accepts. Automaton has 68509 states and 217346 transitions. Word has length 43 [2019-12-07 15:58:22,596 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:22,596 INFO L462 AbstractCegarLoop]: Abstraction has 68509 states and 217346 transitions. [2019-12-07 15:58:22,596 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:58:22,596 INFO L276 IsEmpty]: Start isEmpty. Operand 68509 states and 217346 transitions. [2019-12-07 15:58:22,639 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2019-12-07 15:58:22,639 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:22,639 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:22,639 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:22,639 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:22,639 INFO L82 PathProgramCache]: Analyzing trace with hash 1796258473, now seen corresponding path program 1 times [2019-12-07 15:58:22,639 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:22,640 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [143186195] [2019-12-07 15:58:22,640 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:22,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:22,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:22,713 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [143186195] [2019-12-07 15:58:22,713 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:22,713 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 15:58:22,713 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [476378910] [2019-12-07 15:58:22,713 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:58:22,713 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:22,714 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:58:22,714 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:58:22,714 INFO L87 Difference]: Start difference. First operand 68509 states and 217346 transitions. Second operand 6 states. [2019-12-07 15:58:23,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:23,319 INFO L93 Difference]: Finished difference Result 128114 states and 409497 transitions. [2019-12-07 15:58:23,320 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 15:58:23,320 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 44 [2019-12-07 15:58:23,320 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:23,409 INFO L225 Difference]: With dead ends: 128114 [2019-12-07 15:58:23,409 INFO L226 Difference]: Without dead ends: 66925 [2019-12-07 15:58:23,410 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=47, Invalid=85, Unknown=0, NotChecked=0, Total=132 [2019-12-07 15:58:23,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66925 states. [2019-12-07 15:58:24,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66925 to 61841. [2019-12-07 15:58:24,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61841 states. [2019-12-07 15:58:24,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61841 states to 61841 states and 195153 transitions. [2019-12-07 15:58:24,390 INFO L78 Accepts]: Start accepts. Automaton has 61841 states and 195153 transitions. Word has length 44 [2019-12-07 15:58:24,390 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:24,390 INFO L462 AbstractCegarLoop]: Abstraction has 61841 states and 195153 transitions. [2019-12-07 15:58:24,390 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:58:24,390 INFO L276 IsEmpty]: Start isEmpty. Operand 61841 states and 195153 transitions. [2019-12-07 15:58:24,428 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2019-12-07 15:58:24,428 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:24,428 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:24,429 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:24,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:24,429 INFO L82 PathProgramCache]: Analyzing trace with hash -939306024, now seen corresponding path program 1 times [2019-12-07 15:58:24,429 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:24,429 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1849454703] [2019-12-07 15:58:24,429 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:24,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:24,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:24,478 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1849454703] [2019-12-07 15:58:24,478 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:24,478 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 15:58:24,479 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1532545175] [2019-12-07 15:58:24,479 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:58:24,479 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:24,479 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:58:24,479 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:58:24,479 INFO L87 Difference]: Start difference. First operand 61841 states and 195153 transitions. Second operand 5 states. [2019-12-07 15:58:25,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:25,051 INFO L93 Difference]: Finished difference Result 82293 states and 256642 transitions. [2019-12-07 15:58:25,051 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 15:58:25,051 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 44 [2019-12-07 15:58:25,052 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:25,169 INFO L225 Difference]: With dead ends: 82293 [2019-12-07 15:58:25,169 INFO L226 Difference]: Without dead ends: 82293 [2019-12-07 15:58:25,170 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 15:58:25,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82293 states. [2019-12-07 15:58:26,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82293 to 69111. [2019-12-07 15:58:26,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69111 states. [2019-12-07 15:58:26,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69111 states to 69111 states and 218404 transitions. [2019-12-07 15:58:26,388 INFO L78 Accepts]: Start accepts. Automaton has 69111 states and 218404 transitions. Word has length 44 [2019-12-07 15:58:26,389 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:26,389 INFO L462 AbstractCegarLoop]: Abstraction has 69111 states and 218404 transitions. [2019-12-07 15:58:26,389 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:58:26,389 INFO L276 IsEmpty]: Start isEmpty. Operand 69111 states and 218404 transitions. [2019-12-07 15:58:26,433 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2019-12-07 15:58:26,434 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:26,434 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:26,434 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:26,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:26,434 INFO L82 PathProgramCache]: Analyzing trace with hash -1987614456, now seen corresponding path program 1 times [2019-12-07 15:58:26,434 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:26,434 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1185314240] [2019-12-07 15:58:26,434 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:26,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:26,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:26,516 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1185314240] [2019-12-07 15:58:26,516 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:26,516 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 15:58:26,516 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1079211250] [2019-12-07 15:58:26,517 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:58:26,517 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:26,517 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:58:26,517 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:58:26,517 INFO L87 Difference]: Start difference. First operand 69111 states and 218404 transitions. Second operand 6 states. [2019-12-07 15:58:26,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:26,861 INFO L93 Difference]: Finished difference Result 75344 states and 238316 transitions. [2019-12-07 15:58:26,862 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 15:58:26,862 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 44 [2019-12-07 15:58:26,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:26,971 INFO L225 Difference]: With dead ends: 75344 [2019-12-07 15:58:26,971 INFO L226 Difference]: Without dead ends: 74497 [2019-12-07 15:58:26,971 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=47, Invalid=85, Unknown=0, NotChecked=0, Total=132 [2019-12-07 15:58:27,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74497 states. [2019-12-07 15:58:27,957 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74497 to 69053. [2019-12-07 15:58:27,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69053 states. [2019-12-07 15:58:28,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69053 states to 69053 states and 218211 transitions. [2019-12-07 15:58:28,296 INFO L78 Accepts]: Start accepts. Automaton has 69053 states and 218211 transitions. Word has length 44 [2019-12-07 15:58:28,296 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:28,296 INFO L462 AbstractCegarLoop]: Abstraction has 69053 states and 218211 transitions. [2019-12-07 15:58:28,296 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:58:28,296 INFO L276 IsEmpty]: Start isEmpty. Operand 69053 states and 218211 transitions. [2019-12-07 15:58:28,346 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-12-07 15:58:28,346 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:28,346 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:28,347 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:28,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:28,347 INFO L82 PathProgramCache]: Analyzing trace with hash 606953655, now seen corresponding path program 1 times [2019-12-07 15:58:28,347 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:28,347 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [851129859] [2019-12-07 15:58:28,347 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:28,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:28,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:28,421 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [851129859] [2019-12-07 15:58:28,421 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:28,421 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 15:58:28,422 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1323855349] [2019-12-07 15:58:28,422 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:58:28,422 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:28,422 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:58:28,422 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:58:28,422 INFO L87 Difference]: Start difference. First operand 69053 states and 218211 transitions. Second operand 6 states. [2019-12-07 15:58:28,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:28,747 INFO L93 Difference]: Finished difference Result 75440 states and 238549 transitions. [2019-12-07 15:58:28,747 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 15:58:28,747 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 45 [2019-12-07 15:58:28,747 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:28,854 INFO L225 Difference]: With dead ends: 75440 [2019-12-07 15:58:28,854 INFO L226 Difference]: Without dead ends: 73889 [2019-12-07 15:58:28,854 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2019-12-07 15:58:29,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73889 states. [2019-12-07 15:58:29,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73889 to 68860. [2019-12-07 15:58:29,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68860 states. [2019-12-07 15:58:29,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68860 states to 68860 states and 217543 transitions. [2019-12-07 15:58:29,957 INFO L78 Accepts]: Start accepts. Automaton has 68860 states and 217543 transitions. Word has length 45 [2019-12-07 15:58:29,958 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:29,958 INFO L462 AbstractCegarLoop]: Abstraction has 68860 states and 217543 transitions. [2019-12-07 15:58:29,958 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:58:29,958 INFO L276 IsEmpty]: Start isEmpty. Operand 68860 states and 217543 transitions. [2019-12-07 15:58:30,013 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-12-07 15:58:30,014 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:30,014 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:30,014 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:30,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:30,014 INFO L82 PathProgramCache]: Analyzing trace with hash 134717964, now seen corresponding path program 1 times [2019-12-07 15:58:30,014 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:30,014 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1003037787] [2019-12-07 15:58:30,015 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:30,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:30,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:30,053 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1003037787] [2019-12-07 15:58:30,053 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:30,053 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:58:30,053 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1627710880] [2019-12-07 15:58:30,053 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 15:58:30,053 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:30,053 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 15:58:30,054 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:58:30,054 INFO L87 Difference]: Start difference. First operand 68860 states and 217543 transitions. Second operand 4 states. [2019-12-07 15:58:30,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:30,090 INFO L93 Difference]: Finished difference Result 13126 states and 34358 transitions. [2019-12-07 15:58:30,091 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 15:58:30,091 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 45 [2019-12-07 15:58:30,091 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:30,103 INFO L225 Difference]: With dead ends: 13126 [2019-12-07 15:58:30,103 INFO L226 Difference]: Without dead ends: 13126 [2019-12-07 15:58:30,103 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:58:30,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13126 states. [2019-12-07 15:58:30,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13126 to 12539. [2019-12-07 15:58:30,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12539 states. [2019-12-07 15:58:30,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12539 states to 12539 states and 32777 transitions. [2019-12-07 15:58:30,247 INFO L78 Accepts]: Start accepts. Automaton has 12539 states and 32777 transitions. Word has length 45 [2019-12-07 15:58:30,247 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:30,247 INFO L462 AbstractCegarLoop]: Abstraction has 12539 states and 32777 transitions. [2019-12-07 15:58:30,247 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 15:58:30,248 INFO L276 IsEmpty]: Start isEmpty. Operand 12539 states and 32777 transitions. [2019-12-07 15:58:30,256 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 15:58:30,256 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:30,256 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:30,256 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:30,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:30,257 INFO L82 PathProgramCache]: Analyzing trace with hash -2110715921, now seen corresponding path program 1 times [2019-12-07 15:58:30,257 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:30,257 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1072798175] [2019-12-07 15:58:30,257 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:30,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:30,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:30,318 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1072798175] [2019-12-07 15:58:30,318 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:30,318 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 15:58:30,318 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1962423763] [2019-12-07 15:58:30,319 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 15:58:30,319 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:30,319 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 15:58:30,319 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2019-12-07 15:58:30,319 INFO L87 Difference]: Start difference. First operand 12539 states and 32777 transitions. Second operand 8 states. [2019-12-07 15:58:30,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:30,916 INFO L93 Difference]: Finished difference Result 13940 states and 35658 transitions. [2019-12-07 15:58:30,917 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 15:58:30,917 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 51 [2019-12-07 15:58:30,917 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:30,928 INFO L225 Difference]: With dead ends: 13940 [2019-12-07 15:58:30,928 INFO L226 Difference]: Without dead ends: 13938 [2019-12-07 15:58:30,929 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 73 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=94, Invalid=326, Unknown=0, NotChecked=0, Total=420 [2019-12-07 15:58:30,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13938 states. [2019-12-07 15:58:31,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13938 to 11474. [2019-12-07 15:58:31,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11474 states. [2019-12-07 15:58:31,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11474 states to 11474 states and 30227 transitions. [2019-12-07 15:58:31,106 INFO L78 Accepts]: Start accepts. Automaton has 11474 states and 30227 transitions. Word has length 51 [2019-12-07 15:58:31,106 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:31,106 INFO L462 AbstractCegarLoop]: Abstraction has 11474 states and 30227 transitions. [2019-12-07 15:58:31,106 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 15:58:31,106 INFO L276 IsEmpty]: Start isEmpty. Operand 11474 states and 30227 transitions. [2019-12-07 15:58:31,113 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-12-07 15:58:31,114 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:31,114 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:31,114 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:31,114 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:31,114 INFO L82 PathProgramCache]: Analyzing trace with hash 55581515, now seen corresponding path program 1 times [2019-12-07 15:58:31,114 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:31,114 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1240306468] [2019-12-07 15:58:31,114 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:31,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:31,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:31,169 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1240306468] [2019-12-07 15:58:31,169 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:31,169 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 15:58:31,170 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [456567612] [2019-12-07 15:58:31,170 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:58:31,170 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:31,170 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:58:31,170 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:58:31,170 INFO L87 Difference]: Start difference. First operand 11474 states and 30227 transitions. Second operand 6 states. [2019-12-07 15:58:31,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:31,631 INFO L93 Difference]: Finished difference Result 14428 states and 37605 transitions. [2019-12-07 15:58:31,631 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 15:58:31,631 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 55 [2019-12-07 15:58:31,631 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:31,643 INFO L225 Difference]: With dead ends: 14428 [2019-12-07 15:58:31,643 INFO L226 Difference]: Without dead ends: 14428 [2019-12-07 15:58:31,643 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2019-12-07 15:58:31,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14428 states. [2019-12-07 15:58:31,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14428 to 11554. [2019-12-07 15:58:31,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11554 states. [2019-12-07 15:58:31,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11554 states to 11554 states and 30447 transitions. [2019-12-07 15:58:31,784 INFO L78 Accepts]: Start accepts. Automaton has 11554 states and 30447 transitions. Word has length 55 [2019-12-07 15:58:31,784 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:31,784 INFO L462 AbstractCegarLoop]: Abstraction has 11554 states and 30447 transitions. [2019-12-07 15:58:31,784 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:58:31,784 INFO L276 IsEmpty]: Start isEmpty. Operand 11554 states and 30447 transitions. [2019-12-07 15:58:31,793 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-12-07 15:58:31,793 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:31,793 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:31,793 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:31,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:31,793 INFO L82 PathProgramCache]: Analyzing trace with hash -1657120944, now seen corresponding path program 1 times [2019-12-07 15:58:31,793 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:31,793 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227617319] [2019-12-07 15:58:31,794 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:31,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:31,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:31,850 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1227617319] [2019-12-07 15:58:31,850 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:31,850 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 15:58:31,850 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1352944299] [2019-12-07 15:58:31,850 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:58:31,850 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:31,850 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:58:31,850 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:58:31,850 INFO L87 Difference]: Start difference. First operand 11554 states and 30447 transitions. Second operand 6 states. [2019-12-07 15:58:32,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:32,380 INFO L93 Difference]: Finished difference Result 17468 states and 45397 transitions. [2019-12-07 15:58:32,380 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 15:58:32,380 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 55 [2019-12-07 15:58:32,380 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:32,394 INFO L225 Difference]: With dead ends: 17468 [2019-12-07 15:58:32,395 INFO L226 Difference]: Without dead ends: 17468 [2019-12-07 15:58:32,395 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:58:32,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17468 states. [2019-12-07 15:58:32,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17468 to 12903. [2019-12-07 15:58:32,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12903 states. [2019-12-07 15:58:32,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12903 states to 12903 states and 34132 transitions. [2019-12-07 15:58:32,573 INFO L78 Accepts]: Start accepts. Automaton has 12903 states and 34132 transitions. Word has length 55 [2019-12-07 15:58:32,573 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:32,573 INFO L462 AbstractCegarLoop]: Abstraction has 12903 states and 34132 transitions. [2019-12-07 15:58:32,573 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:58:32,573 INFO L276 IsEmpty]: Start isEmpty. Operand 12903 states and 34132 transitions. [2019-12-07 15:58:32,583 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-12-07 15:58:32,583 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:32,584 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:32,584 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:32,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:32,584 INFO L82 PathProgramCache]: Analyzing trace with hash 137129868, now seen corresponding path program 2 times [2019-12-07 15:58:32,584 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:32,584 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101488166] [2019-12-07 15:58:32,584 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:32,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:32,635 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:32,636 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2101488166] [2019-12-07 15:58:32,636 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:32,636 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 15:58:32,636 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1442253482] [2019-12-07 15:58:32,636 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 15:58:32,636 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:32,637 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 15:58:32,637 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 15:58:32,637 INFO L87 Difference]: Start difference. First operand 12903 states and 34132 transitions. Second operand 6 states. [2019-12-07 15:58:33,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:33,186 INFO L93 Difference]: Finished difference Result 17317 states and 45154 transitions. [2019-12-07 15:58:33,187 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 15:58:33,187 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 55 [2019-12-07 15:58:33,187 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:33,200 INFO L225 Difference]: With dead ends: 17317 [2019-12-07 15:58:33,201 INFO L226 Difference]: Without dead ends: 17317 [2019-12-07 15:58:33,201 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2019-12-07 15:58:33,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17317 states. [2019-12-07 15:58:33,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17317 to 13595. [2019-12-07 15:58:33,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13595 states. [2019-12-07 15:58:33,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13595 states to 13595 states and 35998 transitions. [2019-12-07 15:58:33,379 INFO L78 Accepts]: Start accepts. Automaton has 13595 states and 35998 transitions. Word has length 55 [2019-12-07 15:58:33,379 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:33,379 INFO L462 AbstractCegarLoop]: Abstraction has 13595 states and 35998 transitions. [2019-12-07 15:58:33,379 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 15:58:33,379 INFO L276 IsEmpty]: Start isEmpty. Operand 13595 states and 35998 transitions. [2019-12-07 15:58:33,390 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-12-07 15:58:33,391 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:33,391 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:33,391 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:33,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:33,391 INFO L82 PathProgramCache]: Analyzing trace with hash -429654003, now seen corresponding path program 2 times [2019-12-07 15:58:33,391 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:33,391 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1359923159] [2019-12-07 15:58:33,391 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:33,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:33,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:33,450 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1359923159] [2019-12-07 15:58:33,450 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:33,450 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 15:58:33,451 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [535402613] [2019-12-07 15:58:33,451 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 15:58:33,451 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:33,451 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 15:58:33,451 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 15:58:33,451 INFO L87 Difference]: Start difference. First operand 13595 states and 35998 transitions. Second operand 7 states. [2019-12-07 15:58:34,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:34,125 INFO L93 Difference]: Finished difference Result 19541 states and 50856 transitions. [2019-12-07 15:58:34,125 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 15:58:34,125 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 55 [2019-12-07 15:58:34,126 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:34,141 INFO L225 Difference]: With dead ends: 19541 [2019-12-07 15:58:34,141 INFO L226 Difference]: Without dead ends: 19541 [2019-12-07 15:58:34,141 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2019-12-07 15:58:34,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19541 states. [2019-12-07 15:58:34,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19541 to 13964. [2019-12-07 15:58:34,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13964 states. [2019-12-07 15:58:34,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13964 states to 13964 states and 37018 transitions. [2019-12-07 15:58:34,338 INFO L78 Accepts]: Start accepts. Automaton has 13964 states and 37018 transitions. Word has length 55 [2019-12-07 15:58:34,338 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:34,338 INFO L462 AbstractCegarLoop]: Abstraction has 13964 states and 37018 transitions. [2019-12-07 15:58:34,338 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 15:58:34,338 INFO L276 IsEmpty]: Start isEmpty. Operand 13964 states and 37018 transitions. [2019-12-07 15:58:34,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-12-07 15:58:34,349 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:34,349 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:34,350 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:34,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:34,350 INFO L82 PathProgramCache]: Analyzing trace with hash -845614630, now seen corresponding path program 3 times [2019-12-07 15:58:34,350 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:34,350 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1791157133] [2019-12-07 15:58:34,350 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:34,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:34,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:34,443 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1791157133] [2019-12-07 15:58:34,443 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:34,443 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 15:58:34,443 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [202222873] [2019-12-07 15:58:34,443 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 15:58:34,443 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:34,444 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 15:58:34,444 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2019-12-07 15:58:34,444 INFO L87 Difference]: Start difference. First operand 13964 states and 37018 transitions. Second operand 8 states. [2019-12-07 15:58:35,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:35,271 INFO L93 Difference]: Finished difference Result 20366 states and 52833 transitions. [2019-12-07 15:58:35,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 15:58:35,271 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 55 [2019-12-07 15:58:35,271 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:35,287 INFO L225 Difference]: With dead ends: 20366 [2019-12-07 15:58:35,287 INFO L226 Difference]: Without dead ends: 20366 [2019-12-07 15:58:35,288 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2019-12-07 15:58:35,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20366 states. [2019-12-07 15:58:35,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20366 to 13872. [2019-12-07 15:58:35,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13872 states. [2019-12-07 15:58:35,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13872 states to 13872 states and 36786 transitions. [2019-12-07 15:58:35,484 INFO L78 Accepts]: Start accepts. Automaton has 13872 states and 36786 transitions. Word has length 55 [2019-12-07 15:58:35,484 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:35,484 INFO L462 AbstractCegarLoop]: Abstraction has 13872 states and 36786 transitions. [2019-12-07 15:58:35,484 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 15:58:35,484 INFO L276 IsEmpty]: Start isEmpty. Operand 13872 states and 36786 transitions. [2019-12-07 15:58:35,495 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-12-07 15:58:35,495 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:35,495 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:35,495 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:35,496 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:35,496 INFO L82 PathProgramCache]: Analyzing trace with hash 810821190, now seen corresponding path program 1 times [2019-12-07 15:58:35,496 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:35,496 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1310054707] [2019-12-07 15:58:35,496 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:35,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:35,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:35,527 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1310054707] [2019-12-07 15:58:35,528 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:35,528 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:58:35,528 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1513945900] [2019-12-07 15:58:35,528 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:58:35,528 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:35,528 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:58:35,528 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:58:35,528 INFO L87 Difference]: Start difference. First operand 13872 states and 36786 transitions. Second operand 3 states. [2019-12-07 15:58:35,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:35,579 INFO L93 Difference]: Finished difference Result 12489 states and 32546 transitions. [2019-12-07 15:58:35,580 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:58:35,580 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2019-12-07 15:58:35,580 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:35,591 INFO L225 Difference]: With dead ends: 12489 [2019-12-07 15:58:35,591 INFO L226 Difference]: Without dead ends: 12489 [2019-12-07 15:58:35,591 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:58:35,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12489 states. [2019-12-07 15:58:35,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12489 to 12397. [2019-12-07 15:58:35,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12397 states. [2019-12-07 15:58:35,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12397 states to 12397 states and 32318 transitions. [2019-12-07 15:58:35,722 INFO L78 Accepts]: Start accepts. Automaton has 12397 states and 32318 transitions. Word has length 55 [2019-12-07 15:58:35,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:35,723 INFO L462 AbstractCegarLoop]: Abstraction has 12397 states and 32318 transitions. [2019-12-07 15:58:35,723 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:58:35,723 INFO L276 IsEmpty]: Start isEmpty. Operand 12397 states and 32318 transitions. [2019-12-07 15:58:35,730 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 15:58:35,730 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:35,731 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:35,731 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:35,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:35,731 INFO L82 PathProgramCache]: Analyzing trace with hash 663393734, now seen corresponding path program 1 times [2019-12-07 15:58:35,731 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:35,731 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1544270054] [2019-12-07 15:58:35,731 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:35,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:35,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:35,759 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1544270054] [2019-12-07 15:58:35,759 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:35,759 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 15:58:35,759 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [150802688] [2019-12-07 15:58:35,759 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:58:35,759 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:35,759 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:58:35,759 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:58:35,760 INFO L87 Difference]: Start difference. First operand 12397 states and 32318 transitions. Second operand 5 states. [2019-12-07 15:58:35,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:35,788 INFO L93 Difference]: Finished difference Result 8769 states and 24133 transitions. [2019-12-07 15:58:35,788 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 15:58:35,789 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2019-12-07 15:58:35,789 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:35,796 INFO L225 Difference]: With dead ends: 8769 [2019-12-07 15:58:35,796 INFO L226 Difference]: Without dead ends: 8144 [2019-12-07 15:58:35,796 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:58:35,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8144 states. [2019-12-07 15:58:35,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8144 to 6583. [2019-12-07 15:58:35,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6583 states. [2019-12-07 15:58:35,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6583 states to 6583 states and 18534 transitions. [2019-12-07 15:58:35,884 INFO L78 Accepts]: Start accepts. Automaton has 6583 states and 18534 transitions. Word has length 56 [2019-12-07 15:58:35,885 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:35,885 INFO L462 AbstractCegarLoop]: Abstraction has 6583 states and 18534 transitions. [2019-12-07 15:58:35,885 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:58:35,885 INFO L276 IsEmpty]: Start isEmpty. Operand 6583 states and 18534 transitions. [2019-12-07 15:58:35,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 15:58:35,889 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:35,889 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:35,889 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:35,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:35,890 INFO L82 PathProgramCache]: Analyzing trace with hash -1349403380, now seen corresponding path program 1 times [2019-12-07 15:58:35,890 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:35,890 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [410130164] [2019-12-07 15:58:35,890 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:35,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:35,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:35,946 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [410130164] [2019-12-07 15:58:35,946 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:35,946 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 15:58:35,947 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1953152572] [2019-12-07 15:58:35,947 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 15:58:35,947 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:35,947 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 15:58:35,947 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 15:58:35,947 INFO L87 Difference]: Start difference. First operand 6583 states and 18534 transitions. Second operand 7 states. [2019-12-07 15:58:36,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:36,401 INFO L93 Difference]: Finished difference Result 9263 states and 25842 transitions. [2019-12-07 15:58:36,401 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 15:58:36,401 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 66 [2019-12-07 15:58:36,401 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:36,409 INFO L225 Difference]: With dead ends: 9263 [2019-12-07 15:58:36,409 INFO L226 Difference]: Without dead ends: 9263 [2019-12-07 15:58:36,409 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=55, Invalid=155, Unknown=0, NotChecked=0, Total=210 [2019-12-07 15:58:36,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9263 states. [2019-12-07 15:58:36,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9263 to 6765. [2019-12-07 15:58:36,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6765 states. [2019-12-07 15:58:36,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6765 states to 6765 states and 19053 transitions. [2019-12-07 15:58:36,503 INFO L78 Accepts]: Start accepts. Automaton has 6765 states and 19053 transitions. Word has length 66 [2019-12-07 15:58:36,503 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:36,503 INFO L462 AbstractCegarLoop]: Abstraction has 6765 states and 19053 transitions. [2019-12-07 15:58:36,503 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 15:58:36,503 INFO L276 IsEmpty]: Start isEmpty. Operand 6765 states and 19053 transitions. [2019-12-07 15:58:36,508 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 15:58:36,508 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:36,508 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:36,508 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:36,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:36,508 INFO L82 PathProgramCache]: Analyzing trace with hash 1926726658, now seen corresponding path program 2 times [2019-12-07 15:58:36,508 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:36,508 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [900882190] [2019-12-07 15:58:36,509 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:36,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:36,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:36,547 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [900882190] [2019-12-07 15:58:36,547 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:36,547 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:58:36,547 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1799529778] [2019-12-07 15:58:36,547 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:58:36,547 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:36,548 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:58:36,548 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:58:36,548 INFO L87 Difference]: Start difference. First operand 6765 states and 19053 transitions. Second operand 3 states. [2019-12-07 15:58:36,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:36,581 INFO L93 Difference]: Finished difference Result 6765 states and 19052 transitions. [2019-12-07 15:58:36,581 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:58:36,581 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 15:58:36,581 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:36,587 INFO L225 Difference]: With dead ends: 6765 [2019-12-07 15:58:36,587 INFO L226 Difference]: Without dead ends: 6765 [2019-12-07 15:58:36,587 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:58:36,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6765 states. [2019-12-07 15:58:36,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6765 to 3943. [2019-12-07 15:58:36,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3943 states. [2019-12-07 15:58:36,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3943 states to 3943 states and 11196 transitions. [2019-12-07 15:58:36,647 INFO L78 Accepts]: Start accepts. Automaton has 3943 states and 11196 transitions. Word has length 66 [2019-12-07 15:58:36,647 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:36,647 INFO L462 AbstractCegarLoop]: Abstraction has 3943 states and 11196 transitions. [2019-12-07 15:58:36,647 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:58:36,647 INFO L276 IsEmpty]: Start isEmpty. Operand 3943 states and 11196 transitions. [2019-12-07 15:58:36,649 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 15:58:36,649 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:36,649 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:36,649 INFO L410 AbstractCegarLoop]: === Iteration 29 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:36,650 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:36,650 INFO L82 PathProgramCache]: Analyzing trace with hash 1474263877, now seen corresponding path program 1 times [2019-12-07 15:58:36,650 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:36,650 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1762780509] [2019-12-07 15:58:36,650 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:36,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:36,776 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:36,776 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1762780509] [2019-12-07 15:58:36,776 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:36,776 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 15:58:36,776 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1584906367] [2019-12-07 15:58:36,777 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 15:58:36,777 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:36,777 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 15:58:36,777 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=124, Unknown=0, NotChecked=0, Total=156 [2019-12-07 15:58:36,777 INFO L87 Difference]: Start difference. First operand 3943 states and 11196 transitions. Second operand 13 states. [2019-12-07 15:58:37,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:37,026 INFO L93 Difference]: Finished difference Result 6119 states and 17378 transitions. [2019-12-07 15:58:37,026 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 15:58:37,026 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 67 [2019-12-07 15:58:37,026 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:37,031 INFO L225 Difference]: With dead ends: 6119 [2019-12-07 15:58:37,031 INFO L226 Difference]: Without dead ends: 6087 [2019-12-07 15:58:37,031 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 58 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=91, Invalid=329, Unknown=0, NotChecked=0, Total=420 [2019-12-07 15:58:37,050 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6087 states. [2019-12-07 15:58:37,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6087 to 5095. [2019-12-07 15:58:37,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5095 states. [2019-12-07 15:58:37,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5095 states to 5095 states and 14383 transitions. [2019-12-07 15:58:37,093 INFO L78 Accepts]: Start accepts. Automaton has 5095 states and 14383 transitions. Word has length 67 [2019-12-07 15:58:37,093 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:37,093 INFO L462 AbstractCegarLoop]: Abstraction has 5095 states and 14383 transitions. [2019-12-07 15:58:37,094 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 15:58:37,094 INFO L276 IsEmpty]: Start isEmpty. Operand 5095 states and 14383 transitions. [2019-12-07 15:58:37,097 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 15:58:37,097 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:37,097 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:37,097 INFO L410 AbstractCegarLoop]: === Iteration 30 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:37,097 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:37,097 INFO L82 PathProgramCache]: Analyzing trace with hash 1772687019, now seen corresponding path program 2 times [2019-12-07 15:58:37,097 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:37,097 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [311997294] [2019-12-07 15:58:37,097 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:37,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:58:37,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:58:37,140 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [311997294] [2019-12-07 15:58:37,141 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:58:37,141 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:58:37,141 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [313265038] [2019-12-07 15:58:37,141 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:58:37,141 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:58:37,141 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:58:37,141 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:58:37,142 INFO L87 Difference]: Start difference. First operand 5095 states and 14383 transitions. Second operand 3 states. [2019-12-07 15:58:37,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:58:37,161 INFO L93 Difference]: Finished difference Result 4675 states and 12873 transitions. [2019-12-07 15:58:37,161 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:58:37,161 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 15:58:37,161 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:58:37,166 INFO L225 Difference]: With dead ends: 4675 [2019-12-07 15:58:37,166 INFO L226 Difference]: Without dead ends: 4675 [2019-12-07 15:58:37,167 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:58:37,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4675 states. [2019-12-07 15:58:37,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4675 to 4295. [2019-12-07 15:58:37,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4295 states. [2019-12-07 15:58:37,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4295 states to 4295 states and 11813 transitions. [2019-12-07 15:58:37,225 INFO L78 Accepts]: Start accepts. Automaton has 4295 states and 11813 transitions. Word has length 67 [2019-12-07 15:58:37,225 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:58:37,225 INFO L462 AbstractCegarLoop]: Abstraction has 4295 states and 11813 transitions. [2019-12-07 15:58:37,225 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:58:37,225 INFO L276 IsEmpty]: Start isEmpty. Operand 4295 states and 11813 transitions. [2019-12-07 15:58:37,228 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 15:58:37,228 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:58:37,228 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:58:37,228 INFO L410 AbstractCegarLoop]: === Iteration 31 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:58:37,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:58:37,228 INFO L82 PathProgramCache]: Analyzing trace with hash 15770806, now seen corresponding path program 1 times [2019-12-07 15:58:37,228 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:58:37,228 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1837271288] [2019-12-07 15:58:37,229 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:58:37,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 15:58:37,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 15:58:37,299 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 15:58:37,299 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 15:58:37,301 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] ULTIMATE.startENTRY-->L800: Formula: (let ((.cse0 (store |v_#valid_65| 0 0))) (and (= v_~y$mem_tmp~0_39 0) (= 0 v_~y$read_delayed_var~0.offset_7) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t2183~0.base_27| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t2183~0.base_27|) |v_ULTIMATE.start_main_~#t2183~0.offset_20| 0)) |v_#memory_int_21|) (= 0 v_~y$r_buff0_thd3~0_110) (= (store .cse0 |v_ULTIMATE.start_main_~#t2183~0.base_27| 1) |v_#valid_63|) (= v_~main$tmp_guard0~0_18 0) (= v_~weak$$choice2~0_126 0) (= 0 v_~x~0_147) (= v_~y$r_buff0_thd0~0_348 0) (= v_~y$read_delayed~0_7 0) (= v_~y$w_buff1~0_200 0) (= 0 v_~y$w_buff0~0_179) (= v_~y~0_170 0) (< 0 |v_#StackHeapBarrier_17|) (= v_~y$r_buff1_thd0~0_299 0) (= 0 v_~y$r_buff1_thd2~0_193) (= v_~y$r_buff0_thd1~0_223 0) (= 0 |v_ULTIMATE.start_main_~#t2183~0.offset_20|) (= 0 v_~__unbuffered_p2_EAX~0_33) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t2183~0.base_27| 4)) (= 0 v_~y$read_delayed_var~0.base_7) (= 0 v_~y$flush_delayed~0_56) (= |v_#NULL.offset_5| 0) (= v_~y$w_buff1_used~0_482 0) (= 0 v_~y$r_buff1_thd3~0_211) (= 0 v_~y$r_buff0_thd2~0_114) (= v_~__unbuffered_cnt~0_132 0) (= v_~y$w_buff0_used~0_741 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t2183~0.base_27|)) (= 0 v_~weak$$choice0~0_34) (= 0 |v_#NULL.base_5|) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t2183~0.base_27|) (= v_~y$r_buff1_thd1~0_185 0) (= v_~main$tmp_guard1~0_22 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_65|, #memory_int=|v_#memory_int_22|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_61|, ULTIMATE.start_main_~#t2185~0.offset=|v_ULTIMATE.start_main_~#t2185~0.offset_16|, ULTIMATE.start_main_~#t2185~0.base=|v_ULTIMATE.start_main_~#t2185~0.base_19|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_27|, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_27|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_45|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_141|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_41|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_76|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_62|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_45|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_36|, ~y$mem_tmp~0=v_~y$mem_tmp~0_39, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_211, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_223, ~y$flush_delayed~0=v_~y$flush_delayed~0_56, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_33, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_82|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_54|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_64|, ULTIMATE.start_main_~#t2183~0.offset=|v_ULTIMATE.start_main_~#t2183~0.offset_20|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_31|, ~weak$$choice0~0=v_~weak$$choice0~0_34, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_46|, ~y$w_buff1~0=v_~y$w_buff1~0_200, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_114, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_132, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_299, ~x~0=v_~x~0_147, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_61|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_741, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_73|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_31|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_27|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_22, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_161|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_30|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_51|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_76|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_185, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_31|, ~y$w_buff0~0=v_~y$w_buff0~0_179, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_110, ULTIMATE.start_main_~#t2183~0.base=|v_ULTIMATE.start_main_~#t2183~0.base_27|, ~y~0=v_~y~0_170, ULTIMATE.start_main_~#t2184~0.offset=|v_ULTIMATE.start_main_~#t2184~0.offset_18|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_10|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_21|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_43|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_70|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_18, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_25|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_50|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_193, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_75|, ULTIMATE.start_main_~#t2184~0.base=|v_ULTIMATE.start_main_~#t2184~0.base_23|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_348, #valid=|v_#valid_63|, #memory_int=|v_#memory_int_21|, ~weak$$choice2~0=v_~weak$$choice2~0_126, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_482} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_~#t2185~0.offset, ULTIMATE.start_main_~#t2185~0.base, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ~y$read_delayed~0, ULTIMATE.start_main_#t~ite52, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_~#t2183~0.offset, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite51, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ULTIMATE.start_main_~#t2183~0.base, ~y~0, ULTIMATE.start_main_~#t2184~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_~#t2184~0.base, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 15:58:37,302 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] P0ENTRY-->L4-3: Formula: (and (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_8 0)) (= v_~y$w_buff0_used~0_135 1) (= 2 v_~y$w_buff0~0_28) (= v_~y$w_buff0~0_29 v_~y$w_buff1~0_20) (= v_P0Thread1of1ForFork0_~arg.offset_6 |v_P0Thread1of1ForFork0_#in~arg.offset_8|) (= v_~y$w_buff1_used~0_63 v_~y$w_buff0_used~0_136) (= (ite (not (and (not (= (mod v_~y$w_buff1_used~0_63 256) 0)) (not (= (mod v_~y$w_buff0_used~0_135 256) 0)))) 1 0) |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_8 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_P0Thread1of1ForFork0_~arg.base_6 |v_P0Thread1of1ForFork0_#in~arg.base_8|)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_136, ~y$w_buff0~0=v_~y$w_buff0~0_29, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_135, ~y$w_buff1~0=v_~y$w_buff1~0_20, ~y$w_buff0~0=v_~y$w_buff0~0_28, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_8, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_6, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_6, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_63} AuxVars[] AssignedVars[~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 15:58:37,302 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L800-1-->L802: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t2184~0.base_11|)) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2184~0.base_11| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2184~0.base_11|) |v_ULTIMATE.start_main_~#t2184~0.offset_10| 1)) |v_#memory_int_11|) (= |v_#valid_37| (store |v_#valid_38| |v_ULTIMATE.start_main_~#t2184~0.base_11| 1)) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t2184~0.base_11|) (= 0 |v_ULTIMATE.start_main_~#t2184~0.offset_10|) (= (store |v_#length_16| |v_ULTIMATE.start_main_~#t2184~0.base_11| 4) |v_#length_15|) (= 0 (select |v_#valid_38| |v_ULTIMATE.start_main_~#t2184~0.base_11|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_12|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_6|, ULTIMATE.start_main_~#t2184~0.base=|v_ULTIMATE.start_main_~#t2184~0.base_11|, #valid=|v_#valid_37|, #memory_int=|v_#memory_int_11|, #length=|v_#length_15|, ULTIMATE.start_main_~#t2184~0.offset=|v_ULTIMATE.start_main_~#t2184~0.offset_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t2184~0.base, #valid, #memory_int, #length, ULTIMATE.start_main_~#t2184~0.offset] because there is no mapped edge [2019-12-07 15:58:37,303 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L802-1-->L804: Formula: (and (= |v_#valid_39| (store |v_#valid_40| |v_ULTIMATE.start_main_~#t2185~0.base_13| 1)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2185~0.base_13|) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2185~0.base_13| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2185~0.base_13|) |v_ULTIMATE.start_main_~#t2185~0.offset_11| 2)) |v_#memory_int_13|) (= 0 |v_ULTIMATE.start_main_~#t2185~0.offset_11|) (= (select |v_#valid_40| |v_ULTIMATE.start_main_~#t2185~0.base_13|) 0) (not (= |v_ULTIMATE.start_main_~#t2185~0.base_13| 0)) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t2185~0.base_13| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t2185~0.offset=|v_ULTIMATE.start_main_~#t2185~0.offset_11|, ULTIMATE.start_main_~#t2185~0.base=|v_ULTIMATE.start_main_~#t2185~0.base_13|, #StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_13|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2185~0.offset, ULTIMATE.start_main_~#t2185~0.base, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 15:58:37,303 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [754] [754] L741-->L741-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd1~0_In-868663726 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In-868663726 256) 0))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite5_Out-868663726| 0)) (and (= |P0Thread1of1ForFork0_#t~ite5_Out-868663726| ~y$w_buff0_used~0_In-868663726) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-868663726, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-868663726} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-868663726|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-868663726, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-868663726} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 15:58:37,304 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L757-2-->L757-4: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In1941239793 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In1941239793 256)))) (or (and (not .cse0) (not .cse1) (= ~y$w_buff1~0_In1941239793 |P1Thread1of1ForFork1_#t~ite9_Out1941239793|)) (and (or .cse0 .cse1) (= ~y~0_In1941239793 |P1Thread1of1ForFork1_#t~ite9_Out1941239793|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1941239793, ~y$w_buff1~0=~y$w_buff1~0_In1941239793, ~y~0=~y~0_In1941239793, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1941239793} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1941239793, ~y$w_buff1~0=~y$w_buff1~0_In1941239793, P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out1941239793|, ~y~0=~y~0_In1941239793, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1941239793} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-12-07 15:58:37,305 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L742-->L742-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff0_used~0_In-1190949285 256))) (.cse3 (= 0 (mod ~y$r_buff0_thd1~0_In-1190949285 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd1~0_In-1190949285 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In-1190949285 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite6_Out-1190949285| 0)) (and (= |P0Thread1of1ForFork0_#t~ite6_Out-1190949285| ~y$w_buff1_used~0_In-1190949285) (or .cse2 .cse3) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In-1190949285, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1190949285, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-1190949285, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1190949285} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out-1190949285|, ~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In-1190949285, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1190949285, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-1190949285, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1190949285} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 15:58:37,305 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L743-->L744: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd1~0_In-1539648695 256) 0)) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In-1539648695 256))) (.cse1 (= ~y$r_buff0_thd1~0_In-1539648695 ~y$r_buff0_thd1~0_Out-1539648695))) (or (and .cse0 .cse1) (and (not .cse0) (not .cse2) (= 0 ~y$r_buff0_thd1~0_Out-1539648695)) (and .cse2 .cse1))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1539648695, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-1539648695} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1539648695, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out-1539648695|, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_Out-1539648695} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~y$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 15:58:37,305 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L744-->L744-2: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In1504979038 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd1~0_In1504979038 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd1~0_In1504979038 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In1504979038 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite8_Out1504979038| ~y$r_buff1_thd1~0_In1504979038) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P0Thread1of1ForFork0_#t~ite8_Out1504979038| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In1504979038, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1504979038, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In1504979038, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1504979038} OutVars{~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In1504979038, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1504979038, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out1504979038|, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In1504979038, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1504979038} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 15:58:37,305 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L744-2-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= v_~y$r_buff1_thd1~0_50 |v_P0Thread1of1ForFork0_#t~ite8_26|) (= (+ v_~__unbuffered_cnt~0_40 1) v_~__unbuffered_cnt~0_39)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40} OutVars{~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_50, P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_25|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_39} AuxVars[] AssignedVars[~y$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 15:58:37,306 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L777-2-->L777-4: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In-632457361 256) 0)) (.cse1 (= 0 (mod ~y$r_buff1_thd3~0_In-632457361 256)))) (or (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork2_#t~ite15_Out-632457361| ~y$w_buff1~0_In-632457361)) (and (= |P2Thread1of1ForFork2_#t~ite15_Out-632457361| ~y~0_In-632457361) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-632457361, ~y$w_buff1~0=~y$w_buff1~0_In-632457361, ~y~0=~y~0_In-632457361, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-632457361} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-632457361, P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-632457361|, ~y$w_buff1~0=~y$w_buff1~0_In-632457361, ~y~0=~y~0_In-632457361, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-632457361} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 15:58:37,306 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L777-4-->L778: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_6| v_~y~0_34) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_6|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_5|, ~y~0=v_~y~0_34, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_5|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~y~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 15:58:37,306 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L757-4-->L758: Formula: (= |v_P1Thread1of1ForFork1_#t~ite9_6| v_~y~0_38) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_6|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_5|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_5|, ~y~0=v_~y~0_38} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~y~0] because there is no mapped edge [2019-12-07 15:58:37,306 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L758-->L758-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd2~0_In2058971954 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In2058971954 256)))) (or (and (not .cse0) (= |P1Thread1of1ForFork1_#t~ite11_Out2058971954| 0) (not .cse1)) (and (= ~y$w_buff0_used~0_In2058971954 |P1Thread1of1ForFork1_#t~ite11_Out2058971954|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In2058971954, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2058971954} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In2058971954, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2058971954, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out2058971954|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 15:58:37,306 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L759-->L759-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd2~0_In696933593 256) 0)) (.cse2 (= (mod ~y$w_buff1_used~0_In696933593 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In696933593 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In696933593 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out696933593|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (= ~y$w_buff1_used~0_In696933593 |P1Thread1of1ForFork1_#t~ite12_Out696933593|) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In696933593, ~y$w_buff0_used~0=~y$w_buff0_used~0_In696933593, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In696933593, ~y$w_buff1_used~0=~y$w_buff1_used~0_In696933593} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In696933593, ~y$w_buff0_used~0=~y$w_buff0_used~0_In696933593, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In696933593, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out696933593|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In696933593} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 15:58:37,306 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L760-->L760-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd2~0_In-1513306831 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In-1513306831 256) 0))) (or (and (= |P1Thread1of1ForFork1_#t~ite13_Out-1513306831| ~y$r_buff0_thd2~0_In-1513306831) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= 0 |P1Thread1of1ForFork1_#t~ite13_Out-1513306831|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1513306831, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1513306831} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1513306831, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1513306831, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-1513306831|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 15:58:37,307 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L761-->L761-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd2~0_In1296798992 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1296798992 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In1296798992 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In1296798992 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite14_Out1296798992|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite14_Out1296798992| ~y$r_buff1_thd2~0_In1296798992)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1296798992, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1296798992, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1296798992, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1296798992} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1296798992, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1296798992, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1296798992, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out1296798992|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1296798992} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 15:58:37,307 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L778-->L778-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1739083740 256) 0)) (.cse0 (= (mod ~y$r_buff0_thd3~0_In-1739083740 256) 0))) (or (and (= ~y$w_buff0_used~0_In-1739083740 |P2Thread1of1ForFork2_#t~ite17_Out-1739083740|) (or .cse0 .cse1)) (and (not .cse1) (= 0 |P2Thread1of1ForFork2_#t~ite17_Out-1739083740|) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1739083740, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1739083740} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1739083740, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1739083740, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out-1739083740|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 15:58:37,307 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L779-->L779-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In753551576 256))) (.cse0 (= (mod ~y$r_buff1_thd3~0_In753551576 256) 0)) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In753551576 256))) (.cse2 (= (mod ~y$r_buff0_thd3~0_In753551576 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork2_#t~ite18_Out753551576| 0)) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork2_#t~ite18_Out753551576| ~y$w_buff1_used~0_In753551576) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In753551576, ~y$w_buff0_used~0=~y$w_buff0_used~0_In753551576, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In753551576, ~y$w_buff1_used~0=~y$w_buff1_used~0_In753551576} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In753551576, ~y$w_buff0_used~0=~y$w_buff0_used~0_In753551576, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In753551576, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out753551576|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In753551576} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 15:58:37,307 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [797] [797] L761-2-->P1EXIT: Formula: (and (= v_~__unbuffered_cnt~0_71 (+ v_~__unbuffered_cnt~0_72 1)) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= v_~y$r_buff1_thd2~0_135 |v_P1Thread1of1ForFork1_#t~ite14_40|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_40|} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_135, P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_71, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_39|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork1_#res.offset, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 15:58:37,307 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L780-->L780-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In753342791 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In753342791 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite19_Out753342791| ~y$r_buff0_thd3~0_In753342791) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |P2Thread1of1ForFork2_#t~ite19_Out753342791| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In753342791, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In753342791} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In753342791, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In753342791, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out753342791|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 15:58:37,308 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L781-->L781-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff1_used~0_In525007181 256))) (.cse2 (= 0 (mod ~y$r_buff1_thd3~0_In525007181 256))) (.cse1 (= (mod ~y$r_buff0_thd3~0_In525007181 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In525007181 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite20_Out525007181|)) (and (or .cse3 .cse2) (= ~y$r_buff1_thd3~0_In525007181 |P2Thread1of1ForFork2_#t~ite20_Out525007181|) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In525007181, ~y$w_buff0_used~0=~y$w_buff0_used~0_In525007181, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In525007181, ~y$w_buff1_used~0=~y$w_buff1_used~0_In525007181} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In525007181, ~y$w_buff0_used~0=~y$w_buff0_used~0_In525007181, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out525007181|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In525007181, ~y$w_buff1_used~0=~y$w_buff1_used~0_In525007181} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 15:58:37,308 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L781-2-->P2EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_66 1) v_~__unbuffered_cnt~0_65) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= |v_P2Thread1of1ForFork2_#t~ite20_34| v_~y$r_buff1_thd3~0_132)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66} OutVars{~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_132, P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_33|, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_65, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[~y$r_buff1_thd3~0, P2Thread1of1ForFork2_#t~ite20, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 15:58:37,308 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [733] [733] L804-1-->L810: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (= v_~main$tmp_guard0~0_8 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_18) 1 0) 0) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_18} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_18, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 15:58:37,308 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L810-2-->L810-5: Formula: (let ((.cse2 (= (mod ~y$w_buff1_used~0_In-752451502 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd0~0_In-752451502 256) 0)) (.cse0 (= |ULTIMATE.start_main_#t~ite24_Out-752451502| |ULTIMATE.start_main_#t~ite25_Out-752451502|))) (or (and (= ~y~0_In-752451502 |ULTIMATE.start_main_#t~ite24_Out-752451502|) .cse0 (or .cse1 .cse2)) (and (= |ULTIMATE.start_main_#t~ite24_Out-752451502| ~y$w_buff1~0_In-752451502) (not .cse2) (not .cse1) .cse0))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-752451502, ~y~0=~y~0_In-752451502, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-752451502, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-752451502} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-752451502, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-752451502|, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-752451502|, ~y~0=~y~0_In-752451502, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-752451502, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-752451502} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 15:58:37,309 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [768] [768] L811-->L811-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In1311973059 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In1311973059 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In1311973059 |ULTIMATE.start_main_#t~ite26_Out1311973059|)) (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite26_Out1311973059|) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1311973059, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1311973059} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1311973059, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1311973059, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out1311973059|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 15:58:37,309 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [752] [752] L812-->L812-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In-2128503377 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd0~0_In-2128503377 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd0~0_In-2128503377 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In-2128503377 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~y$w_buff1_used~0_In-2128503377 |ULTIMATE.start_main_#t~ite27_Out-2128503377|)) (and (= 0 |ULTIMATE.start_main_#t~ite27_Out-2128503377|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-2128503377, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-2128503377, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-2128503377, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2128503377} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-2128503377, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-2128503377, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-2128503377|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-2128503377, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2128503377} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 15:58:37,309 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [756] [756] L813-->L813-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In1589347095 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In1589347095 256)))) (or (and (= |ULTIMATE.start_main_#t~ite28_Out1589347095| 0) (not .cse0) (not .cse1)) (and (= ~y$r_buff0_thd0~0_In1589347095 |ULTIMATE.start_main_#t~ite28_Out1589347095|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1589347095, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1589347095} OutVars{ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out1589347095|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1589347095, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1589347095} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 15:58:37,309 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [751] [751] L814-->L814-2: Formula: (let ((.cse2 (= (mod ~y$r_buff1_thd0~0_In-282413009 256) 0)) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In-282413009 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-282413009 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-282413009 256)))) (or (and (= ~y$r_buff1_thd0~0_In-282413009 |ULTIMATE.start_main_#t~ite29_Out-282413009|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |ULTIMATE.start_main_#t~ite29_Out-282413009|) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-282413009, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-282413009, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-282413009, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-282413009} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-282413009, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-282413009|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-282413009, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-282413009, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-282413009} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 15:58:37,311 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [810] [810] L823-->L823-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-1183844402 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite38_In-1183844402| |ULTIMATE.start_main_#t~ite38_Out-1183844402|) (= ~y$w_buff1~0_In-1183844402 |ULTIMATE.start_main_#t~ite39_Out-1183844402|)) (and .cse0 (= |ULTIMATE.start_main_#t~ite39_Out-1183844402| |ULTIMATE.start_main_#t~ite38_Out-1183844402|) (= ~y$w_buff1~0_In-1183844402 |ULTIMATE.start_main_#t~ite38_Out-1183844402|) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-1183844402 256) 0))) (or (and (= (mod ~y$r_buff1_thd0~0_In-1183844402 256) 0) .cse1) (and (= 0 (mod ~y$w_buff1_used~0_In-1183844402 256)) .cse1) (= (mod ~y$w_buff0_used~0_In-1183844402 256) 0)))))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1183844402, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1183844402, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1183844402, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_In-1183844402|, ~weak$$choice2~0=~weak$$choice2~0_In-1183844402, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1183844402, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1183844402} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1183844402, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1183844402, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out-1183844402|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1183844402, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out-1183844402|, ~weak$$choice2~0=~weak$$choice2~0_In-1183844402, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1183844402, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1183844402} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38] because there is no mapped edge [2019-12-07 15:58:37,311 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [809] [809] L824-->L824-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-15705247 256)))) (or (and (= |ULTIMATE.start_main_#t~ite41_In-15705247| |ULTIMATE.start_main_#t~ite41_Out-15705247|) (= |ULTIMATE.start_main_#t~ite42_Out-15705247| ~y$w_buff0_used~0_In-15705247) (not .cse0)) (and (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-15705247 256) 0))) (or (and .cse1 (= 0 (mod ~y$r_buff1_thd0~0_In-15705247 256))) (and .cse1 (= 0 (mod ~y$w_buff1_used~0_In-15705247 256))) (= 0 (mod ~y$w_buff0_used~0_In-15705247 256)))) .cse0 (= |ULTIMATE.start_main_#t~ite42_Out-15705247| |ULTIMATE.start_main_#t~ite41_Out-15705247|) (= |ULTIMATE.start_main_#t~ite41_Out-15705247| ~y$w_buff0_used~0_In-15705247)))) InVars {ULTIMATE.start_main_#t~ite41=|ULTIMATE.start_main_#t~ite41_In-15705247|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-15705247, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-15705247, ~weak$$choice2~0=~weak$$choice2~0_In-15705247, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-15705247, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-15705247} OutVars{ULTIMATE.start_main_#t~ite41=|ULTIMATE.start_main_#t~ite41_Out-15705247|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-15705247, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-15705247, ~weak$$choice2~0=~weak$$choice2~0_In-15705247, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_Out-15705247|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-15705247, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-15705247} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 15:58:37,312 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [736] [736] L826-->L827: Formula: (and (= v_~y$r_buff0_thd0~0_133 v_~y$r_buff0_thd0~0_132) (not (= 0 (mod v_~weak$$choice2~0_33 256)))) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_133, ~weak$$choice2~0=v_~weak$$choice2~0_33} OutVars{~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_132, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_22|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_13|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_8|, ~weak$$choice2~0=v_~weak$$choice2~0_33} AuxVars[] AssignedVars[~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 15:58:37,312 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L829-->L832-1: Formula: (and (not (= (mod v_~y$flush_delayed~0_45 256) 0)) (= 0 v_~y$flush_delayed~0_44) (= v_~y~0_135 v_~y$mem_tmp~0_33) (= (mod v_~main$tmp_guard1~0_13 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_33, ~y$flush_delayed~0=v_~y$flush_delayed~0_45, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_13} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_22|, ~y$mem_tmp~0=v_~y$mem_tmp~0_33, ~y$flush_delayed~0=v_~y$flush_delayed~0_44, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_13, ~y~0=v_~y~0_135, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ~y$flush_delayed~0, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 15:58:37,312 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L832-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 15:58:37,380 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 03:58:37 BasicIcfg [2019-12-07 15:58:37,380 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 15:58:37,380 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 15:58:37,381 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 15:58:37,381 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 15:58:37,381 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 03:56:16" (3/4) ... [2019-12-07 15:58:37,383 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 15:58:37,384 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] ULTIMATE.startENTRY-->L800: Formula: (let ((.cse0 (store |v_#valid_65| 0 0))) (and (= v_~y$mem_tmp~0_39 0) (= 0 v_~y$read_delayed_var~0.offset_7) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t2183~0.base_27| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t2183~0.base_27|) |v_ULTIMATE.start_main_~#t2183~0.offset_20| 0)) |v_#memory_int_21|) (= 0 v_~y$r_buff0_thd3~0_110) (= (store .cse0 |v_ULTIMATE.start_main_~#t2183~0.base_27| 1) |v_#valid_63|) (= v_~main$tmp_guard0~0_18 0) (= v_~weak$$choice2~0_126 0) (= 0 v_~x~0_147) (= v_~y$r_buff0_thd0~0_348 0) (= v_~y$read_delayed~0_7 0) (= v_~y$w_buff1~0_200 0) (= 0 v_~y$w_buff0~0_179) (= v_~y~0_170 0) (< 0 |v_#StackHeapBarrier_17|) (= v_~y$r_buff1_thd0~0_299 0) (= 0 v_~y$r_buff1_thd2~0_193) (= v_~y$r_buff0_thd1~0_223 0) (= 0 |v_ULTIMATE.start_main_~#t2183~0.offset_20|) (= 0 v_~__unbuffered_p2_EAX~0_33) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t2183~0.base_27| 4)) (= 0 v_~y$read_delayed_var~0.base_7) (= 0 v_~y$flush_delayed~0_56) (= |v_#NULL.offset_5| 0) (= v_~y$w_buff1_used~0_482 0) (= 0 v_~y$r_buff1_thd3~0_211) (= 0 v_~y$r_buff0_thd2~0_114) (= v_~__unbuffered_cnt~0_132 0) (= v_~y$w_buff0_used~0_741 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t2183~0.base_27|)) (= 0 v_~weak$$choice0~0_34) (= 0 |v_#NULL.base_5|) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t2183~0.base_27|) (= v_~y$r_buff1_thd1~0_185 0) (= v_~main$tmp_guard1~0_22 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_65|, #memory_int=|v_#memory_int_22|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_61|, ULTIMATE.start_main_~#t2185~0.offset=|v_ULTIMATE.start_main_~#t2185~0.offset_16|, ULTIMATE.start_main_~#t2185~0.base=|v_ULTIMATE.start_main_~#t2185~0.base_19|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_27|, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_27|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_45|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_141|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_41|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_76|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_62|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_45|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_36|, ~y$mem_tmp~0=v_~y$mem_tmp~0_39, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_211, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_223, ~y$flush_delayed~0=v_~y$flush_delayed~0_56, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_33, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_82|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_54|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_64|, ULTIMATE.start_main_~#t2183~0.offset=|v_ULTIMATE.start_main_~#t2183~0.offset_20|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_31|, ~weak$$choice0~0=v_~weak$$choice0~0_34, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_46|, ~y$w_buff1~0=v_~y$w_buff1~0_200, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_114, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_132, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_299, ~x~0=v_~x~0_147, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_61|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_741, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_73|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_31|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_27|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_22, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_161|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_30|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_51|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_76|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_185, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_31|, ~y$w_buff0~0=v_~y$w_buff0~0_179, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_110, ULTIMATE.start_main_~#t2183~0.base=|v_ULTIMATE.start_main_~#t2183~0.base_27|, ~y~0=v_~y~0_170, ULTIMATE.start_main_~#t2184~0.offset=|v_ULTIMATE.start_main_~#t2184~0.offset_18|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_10|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_21|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_43|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_70|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_18, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_25|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_50|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_193, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_75|, ULTIMATE.start_main_~#t2184~0.base=|v_ULTIMATE.start_main_~#t2184~0.base_23|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_348, #valid=|v_#valid_63|, #memory_int=|v_#memory_int_21|, ~weak$$choice2~0=v_~weak$$choice2~0_126, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_482} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ULTIMATE.start_main_~#t2185~0.offset, ULTIMATE.start_main_~#t2185~0.base, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ~y$read_delayed~0, ULTIMATE.start_main_#t~ite52, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_~#t2183~0.offset, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite51, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ULTIMATE.start_main_~#t2183~0.base, ~y~0, ULTIMATE.start_main_~#t2184~0.offset, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_~#t2184~0.base, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 15:58:37,384 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] P0ENTRY-->L4-3: Formula: (and (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_8 0)) (= v_~y$w_buff0_used~0_135 1) (= 2 v_~y$w_buff0~0_28) (= v_~y$w_buff0~0_29 v_~y$w_buff1~0_20) (= v_P0Thread1of1ForFork0_~arg.offset_6 |v_P0Thread1of1ForFork0_#in~arg.offset_8|) (= v_~y$w_buff1_used~0_63 v_~y$w_buff0_used~0_136) (= (ite (not (and (not (= (mod v_~y$w_buff1_used~0_63 256) 0)) (not (= (mod v_~y$w_buff0_used~0_135 256) 0)))) 1 0) |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_8 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_P0Thread1of1ForFork0_~arg.base_6 |v_P0Thread1of1ForFork0_#in~arg.base_8|)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_136, ~y$w_buff0~0=v_~y$w_buff0~0_29, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_8|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_135, ~y$w_buff1~0=v_~y$w_buff1~0_20, ~y$w_buff0~0=v_~y$w_buff0~0_28, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_8, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_8|, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_6, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_6, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_63} AuxVars[] AssignedVars[~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 15:58:37,384 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L800-1-->L802: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t2184~0.base_11|)) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2184~0.base_11| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2184~0.base_11|) |v_ULTIMATE.start_main_~#t2184~0.offset_10| 1)) |v_#memory_int_11|) (= |v_#valid_37| (store |v_#valid_38| |v_ULTIMATE.start_main_~#t2184~0.base_11| 1)) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t2184~0.base_11|) (= 0 |v_ULTIMATE.start_main_~#t2184~0.offset_10|) (= (store |v_#length_16| |v_ULTIMATE.start_main_~#t2184~0.base_11| 4) |v_#length_15|) (= 0 (select |v_#valid_38| |v_ULTIMATE.start_main_~#t2184~0.base_11|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_12|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_6|, ULTIMATE.start_main_~#t2184~0.base=|v_ULTIMATE.start_main_~#t2184~0.base_11|, #valid=|v_#valid_37|, #memory_int=|v_#memory_int_11|, #length=|v_#length_15|, ULTIMATE.start_main_~#t2184~0.offset=|v_ULTIMATE.start_main_~#t2184~0.offset_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t2184~0.base, #valid, #memory_int, #length, ULTIMATE.start_main_~#t2184~0.offset] because there is no mapped edge [2019-12-07 15:58:37,385 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L802-1-->L804: Formula: (and (= |v_#valid_39| (store |v_#valid_40| |v_ULTIMATE.start_main_~#t2185~0.base_13| 1)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2185~0.base_13|) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2185~0.base_13| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2185~0.base_13|) |v_ULTIMATE.start_main_~#t2185~0.offset_11| 2)) |v_#memory_int_13|) (= 0 |v_ULTIMATE.start_main_~#t2185~0.offset_11|) (= (select |v_#valid_40| |v_ULTIMATE.start_main_~#t2185~0.base_13|) 0) (not (= |v_ULTIMATE.start_main_~#t2185~0.base_13| 0)) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t2185~0.base_13| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t2185~0.offset=|v_ULTIMATE.start_main_~#t2185~0.offset_11|, ULTIMATE.start_main_~#t2185~0.base=|v_ULTIMATE.start_main_~#t2185~0.base_13|, #StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_13|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2185~0.offset, ULTIMATE.start_main_~#t2185~0.base, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 15:58:37,385 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [754] [754] L741-->L741-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd1~0_In-868663726 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In-868663726 256) 0))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite5_Out-868663726| 0)) (and (= |P0Thread1of1ForFork0_#t~ite5_Out-868663726| ~y$w_buff0_used~0_In-868663726) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-868663726, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-868663726} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-868663726|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-868663726, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-868663726} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 15:58:37,386 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L757-2-->L757-4: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In1941239793 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In1941239793 256)))) (or (and (not .cse0) (not .cse1) (= ~y$w_buff1~0_In1941239793 |P1Thread1of1ForFork1_#t~ite9_Out1941239793|)) (and (or .cse0 .cse1) (= ~y~0_In1941239793 |P1Thread1of1ForFork1_#t~ite9_Out1941239793|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1941239793, ~y$w_buff1~0=~y$w_buff1~0_In1941239793, ~y~0=~y~0_In1941239793, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1941239793} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1941239793, ~y$w_buff1~0=~y$w_buff1~0_In1941239793, P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out1941239793|, ~y~0=~y~0_In1941239793, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1941239793} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-12-07 15:58:37,386 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L742-->L742-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff0_used~0_In-1190949285 256))) (.cse3 (= 0 (mod ~y$r_buff0_thd1~0_In-1190949285 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd1~0_In-1190949285 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In-1190949285 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite6_Out-1190949285| 0)) (and (= |P0Thread1of1ForFork0_#t~ite6_Out-1190949285| ~y$w_buff1_used~0_In-1190949285) (or .cse2 .cse3) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In-1190949285, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1190949285, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-1190949285, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1190949285} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out-1190949285|, ~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In-1190949285, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1190949285, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-1190949285, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1190949285} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 15:58:37,386 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L743-->L744: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd1~0_In-1539648695 256) 0)) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In-1539648695 256))) (.cse1 (= ~y$r_buff0_thd1~0_In-1539648695 ~y$r_buff0_thd1~0_Out-1539648695))) (or (and .cse0 .cse1) (and (not .cse0) (not .cse2) (= 0 ~y$r_buff0_thd1~0_Out-1539648695)) (and .cse2 .cse1))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1539648695, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-1539648695} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1539648695, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out-1539648695|, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_Out-1539648695} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~y$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 15:58:37,386 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L744-->L744-2: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In1504979038 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd1~0_In1504979038 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd1~0_In1504979038 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In1504979038 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite8_Out1504979038| ~y$r_buff1_thd1~0_In1504979038) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P0Thread1of1ForFork0_#t~ite8_Out1504979038| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In1504979038, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1504979038, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In1504979038, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1504979038} OutVars{~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In1504979038, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1504979038, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out1504979038|, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In1504979038, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1504979038} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 15:58:37,386 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L744-2-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= v_~y$r_buff1_thd1~0_50 |v_P0Thread1of1ForFork0_#t~ite8_26|) (= (+ v_~__unbuffered_cnt~0_40 1) v_~__unbuffered_cnt~0_39)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40} OutVars{~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_50, P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_25|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_39} AuxVars[] AssignedVars[~y$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 15:58:37,387 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [770] [770] L777-2-->L777-4: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In-632457361 256) 0)) (.cse1 (= 0 (mod ~y$r_buff1_thd3~0_In-632457361 256)))) (or (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork2_#t~ite15_Out-632457361| ~y$w_buff1~0_In-632457361)) (and (= |P2Thread1of1ForFork2_#t~ite15_Out-632457361| ~y~0_In-632457361) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-632457361, ~y$w_buff1~0=~y$w_buff1~0_In-632457361, ~y~0=~y~0_In-632457361, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-632457361} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-632457361, P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-632457361|, ~y$w_buff1~0=~y$w_buff1~0_In-632457361, ~y~0=~y~0_In-632457361, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-632457361} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 15:58:37,387 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L777-4-->L778: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_6| v_~y~0_34) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_6|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_5|, ~y~0=v_~y~0_34, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_5|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, ~y~0, P2Thread1of1ForFork2_#t~ite16] because there is no mapped edge [2019-12-07 15:58:37,387 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L757-4-->L758: Formula: (= |v_P1Thread1of1ForFork1_#t~ite9_6| v_~y~0_38) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_6|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_5|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_5|, ~y~0=v_~y~0_38} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~y~0] because there is no mapped edge [2019-12-07 15:58:37,387 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L758-->L758-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd2~0_In2058971954 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In2058971954 256)))) (or (and (not .cse0) (= |P1Thread1of1ForFork1_#t~ite11_Out2058971954| 0) (not .cse1)) (and (= ~y$w_buff0_used~0_In2058971954 |P1Thread1of1ForFork1_#t~ite11_Out2058971954|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In2058971954, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2058971954} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In2058971954, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2058971954, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out2058971954|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 15:58:37,387 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L759-->L759-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd2~0_In696933593 256) 0)) (.cse2 (= (mod ~y$w_buff1_used~0_In696933593 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In696933593 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In696933593 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out696933593|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (= ~y$w_buff1_used~0_In696933593 |P1Thread1of1ForFork1_#t~ite12_Out696933593|) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In696933593, ~y$w_buff0_used~0=~y$w_buff0_used~0_In696933593, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In696933593, ~y$w_buff1_used~0=~y$w_buff1_used~0_In696933593} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In696933593, ~y$w_buff0_used~0=~y$w_buff0_used~0_In696933593, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In696933593, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out696933593|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In696933593} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 15:58:37,388 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L760-->L760-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd2~0_In-1513306831 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In-1513306831 256) 0))) (or (and (= |P1Thread1of1ForFork1_#t~ite13_Out-1513306831| ~y$r_buff0_thd2~0_In-1513306831) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= 0 |P1Thread1of1ForFork1_#t~ite13_Out-1513306831|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1513306831, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1513306831} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1513306831, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1513306831, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-1513306831|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 15:58:37,388 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L761-->L761-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd2~0_In1296798992 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1296798992 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In1296798992 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In1296798992 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite14_Out1296798992|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite14_Out1296798992| ~y$r_buff1_thd2~0_In1296798992)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1296798992, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1296798992, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1296798992, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1296798992} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1296798992, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1296798992, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1296798992, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out1296798992|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1296798992} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 15:58:37,388 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L778-->L778-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1739083740 256) 0)) (.cse0 (= (mod ~y$r_buff0_thd3~0_In-1739083740 256) 0))) (or (and (= ~y$w_buff0_used~0_In-1739083740 |P2Thread1of1ForFork2_#t~ite17_Out-1739083740|) (or .cse0 .cse1)) (and (not .cse1) (= 0 |P2Thread1of1ForFork2_#t~ite17_Out-1739083740|) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1739083740, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1739083740} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1739083740, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1739083740, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out-1739083740|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 15:58:37,388 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L779-->L779-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In753551576 256))) (.cse0 (= (mod ~y$r_buff1_thd3~0_In753551576 256) 0)) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In753551576 256))) (.cse2 (= (mod ~y$r_buff0_thd3~0_In753551576 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork2_#t~ite18_Out753551576| 0)) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork2_#t~ite18_Out753551576| ~y$w_buff1_used~0_In753551576) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In753551576, ~y$w_buff0_used~0=~y$w_buff0_used~0_In753551576, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In753551576, ~y$w_buff1_used~0=~y$w_buff1_used~0_In753551576} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In753551576, ~y$w_buff0_used~0=~y$w_buff0_used~0_In753551576, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In753551576, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out753551576|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In753551576} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 15:58:37,389 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [797] [797] L761-2-->P1EXIT: Formula: (and (= v_~__unbuffered_cnt~0_71 (+ v_~__unbuffered_cnt~0_72 1)) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= v_~y$r_buff1_thd2~0_135 |v_P1Thread1of1ForFork1_#t~ite14_40|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_40|} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_135, P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_71, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_39|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork1_#res.offset, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 15:58:37,389 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L780-->L780-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In753342791 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In753342791 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite19_Out753342791| ~y$r_buff0_thd3~0_In753342791) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |P2Thread1of1ForFork2_#t~ite19_Out753342791| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In753342791, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In753342791} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In753342791, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In753342791, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out753342791|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 15:58:37,389 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L781-->L781-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff1_used~0_In525007181 256))) (.cse2 (= 0 (mod ~y$r_buff1_thd3~0_In525007181 256))) (.cse1 (= (mod ~y$r_buff0_thd3~0_In525007181 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In525007181 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite20_Out525007181|)) (and (or .cse3 .cse2) (= ~y$r_buff1_thd3~0_In525007181 |P2Thread1of1ForFork2_#t~ite20_Out525007181|) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In525007181, ~y$w_buff0_used~0=~y$w_buff0_used~0_In525007181, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In525007181, ~y$w_buff1_used~0=~y$w_buff1_used~0_In525007181} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In525007181, ~y$w_buff0_used~0=~y$w_buff0_used~0_In525007181, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out525007181|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In525007181, ~y$w_buff1_used~0=~y$w_buff1_used~0_In525007181} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 15:58:37,389 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L781-2-->P2EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_66 1) v_~__unbuffered_cnt~0_65) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= |v_P2Thread1of1ForFork2_#t~ite20_34| v_~y$r_buff1_thd3~0_132)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66} OutVars{~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_132, P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_33|, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_65, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[~y$r_buff1_thd3~0, P2Thread1of1ForFork2_#t~ite20, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 15:58:37,389 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [733] [733] L804-1-->L810: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (= v_~main$tmp_guard0~0_8 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_18) 1 0) 0) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_18} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_18, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 15:58:37,390 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L810-2-->L810-5: Formula: (let ((.cse2 (= (mod ~y$w_buff1_used~0_In-752451502 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd0~0_In-752451502 256) 0)) (.cse0 (= |ULTIMATE.start_main_#t~ite24_Out-752451502| |ULTIMATE.start_main_#t~ite25_Out-752451502|))) (or (and (= ~y~0_In-752451502 |ULTIMATE.start_main_#t~ite24_Out-752451502|) .cse0 (or .cse1 .cse2)) (and (= |ULTIMATE.start_main_#t~ite24_Out-752451502| ~y$w_buff1~0_In-752451502) (not .cse2) (not .cse1) .cse0))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-752451502, ~y~0=~y~0_In-752451502, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-752451502, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-752451502} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-752451502, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out-752451502|, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-752451502|, ~y~0=~y~0_In-752451502, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-752451502, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-752451502} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 15:58:37,390 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [768] [768] L811-->L811-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In1311973059 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In1311973059 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In1311973059 |ULTIMATE.start_main_#t~ite26_Out1311973059|)) (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite26_Out1311973059|) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1311973059, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1311973059} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1311973059, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1311973059, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out1311973059|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 15:58:37,390 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [752] [752] L812-->L812-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In-2128503377 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd0~0_In-2128503377 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd0~0_In-2128503377 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In-2128503377 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~y$w_buff1_used~0_In-2128503377 |ULTIMATE.start_main_#t~ite27_Out-2128503377|)) (and (= 0 |ULTIMATE.start_main_#t~ite27_Out-2128503377|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-2128503377, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-2128503377, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-2128503377, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2128503377} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-2128503377, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-2128503377, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-2128503377|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-2128503377, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2128503377} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 15:58:37,391 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [756] [756] L813-->L813-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In1589347095 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In1589347095 256)))) (or (and (= |ULTIMATE.start_main_#t~ite28_Out1589347095| 0) (not .cse0) (not .cse1)) (and (= ~y$r_buff0_thd0~0_In1589347095 |ULTIMATE.start_main_#t~ite28_Out1589347095|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1589347095, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1589347095} OutVars{ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out1589347095|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1589347095, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1589347095} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 15:58:37,391 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [751] [751] L814-->L814-2: Formula: (let ((.cse2 (= (mod ~y$r_buff1_thd0~0_In-282413009 256) 0)) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In-282413009 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-282413009 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-282413009 256)))) (or (and (= ~y$r_buff1_thd0~0_In-282413009 |ULTIMATE.start_main_#t~ite29_Out-282413009|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |ULTIMATE.start_main_#t~ite29_Out-282413009|) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-282413009, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-282413009, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-282413009, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-282413009} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-282413009, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-282413009|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-282413009, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-282413009, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-282413009} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 15:58:37,392 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [810] [810] L823-->L823-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-1183844402 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite38_In-1183844402| |ULTIMATE.start_main_#t~ite38_Out-1183844402|) (= ~y$w_buff1~0_In-1183844402 |ULTIMATE.start_main_#t~ite39_Out-1183844402|)) (and .cse0 (= |ULTIMATE.start_main_#t~ite39_Out-1183844402| |ULTIMATE.start_main_#t~ite38_Out-1183844402|) (= ~y$w_buff1~0_In-1183844402 |ULTIMATE.start_main_#t~ite38_Out-1183844402|) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-1183844402 256) 0))) (or (and (= (mod ~y$r_buff1_thd0~0_In-1183844402 256) 0) .cse1) (and (= 0 (mod ~y$w_buff1_used~0_In-1183844402 256)) .cse1) (= (mod ~y$w_buff0_used~0_In-1183844402 256) 0)))))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1183844402, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1183844402, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1183844402, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_In-1183844402|, ~weak$$choice2~0=~weak$$choice2~0_In-1183844402, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1183844402, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1183844402} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1183844402, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1183844402, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out-1183844402|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1183844402, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out-1183844402|, ~weak$$choice2~0=~weak$$choice2~0_In-1183844402, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1183844402, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1183844402} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38] because there is no mapped edge [2019-12-07 15:58:37,392 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [809] [809] L824-->L824-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-15705247 256)))) (or (and (= |ULTIMATE.start_main_#t~ite41_In-15705247| |ULTIMATE.start_main_#t~ite41_Out-15705247|) (= |ULTIMATE.start_main_#t~ite42_Out-15705247| ~y$w_buff0_used~0_In-15705247) (not .cse0)) (and (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-15705247 256) 0))) (or (and .cse1 (= 0 (mod ~y$r_buff1_thd0~0_In-15705247 256))) (and .cse1 (= 0 (mod ~y$w_buff1_used~0_In-15705247 256))) (= 0 (mod ~y$w_buff0_used~0_In-15705247 256)))) .cse0 (= |ULTIMATE.start_main_#t~ite42_Out-15705247| |ULTIMATE.start_main_#t~ite41_Out-15705247|) (= |ULTIMATE.start_main_#t~ite41_Out-15705247| ~y$w_buff0_used~0_In-15705247)))) InVars {ULTIMATE.start_main_#t~ite41=|ULTIMATE.start_main_#t~ite41_In-15705247|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-15705247, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-15705247, ~weak$$choice2~0=~weak$$choice2~0_In-15705247, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-15705247, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-15705247} OutVars{ULTIMATE.start_main_#t~ite41=|ULTIMATE.start_main_#t~ite41_Out-15705247|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-15705247, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-15705247, ~weak$$choice2~0=~weak$$choice2~0_In-15705247, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_Out-15705247|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-15705247, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-15705247} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 15:58:37,393 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [736] [736] L826-->L827: Formula: (and (= v_~y$r_buff0_thd0~0_133 v_~y$r_buff0_thd0~0_132) (not (= 0 (mod v_~weak$$choice2~0_33 256)))) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_133, ~weak$$choice2~0=v_~weak$$choice2~0_33} OutVars{~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_132, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_22|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_13|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_8|, ~weak$$choice2~0=v_~weak$$choice2~0_33} AuxVars[] AssignedVars[~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 15:58:37,394 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L829-->L832-1: Formula: (and (not (= (mod v_~y$flush_delayed~0_45 256) 0)) (= 0 v_~y$flush_delayed~0_44) (= v_~y~0_135 v_~y$mem_tmp~0_33) (= (mod v_~main$tmp_guard1~0_13 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_33, ~y$flush_delayed~0=v_~y$flush_delayed~0_45, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_13} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_22|, ~y$mem_tmp~0=v_~y$mem_tmp~0_33, ~y$flush_delayed~0=v_~y$flush_delayed~0_44, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_13, ~y~0=v_~y~0_135, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ~y$flush_delayed~0, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 15:58:37,394 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L832-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 15:58:37,459 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_3a3f6abc-21de-42de-8232-23c735660788/bin/uautomizer/witness.graphml [2019-12-07 15:58:37,459 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 15:58:37,461 INFO L168 Benchmark]: Toolchain (without parser) took 141448.22 ms. Allocated memory was 1.0 GB in the beginning and 8.4 GB in the end (delta: 7.4 GB). Free memory was 934.0 MB in the beginning and 4.6 GB in the end (delta: -3.7 GB). Peak memory consumption was 3.7 GB. Max. memory is 11.5 GB. [2019-12-07 15:58:37,461 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 15:58:37,461 INFO L168 Benchmark]: CACSL2BoogieTranslator took 395.85 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 97.5 MB). Free memory was 934.0 MB in the beginning and 1.1 GB in the end (delta: -129.9 MB). Peak memory consumption was 18.3 MB. Max. memory is 11.5 GB. [2019-12-07 15:58:37,462 INFO L168 Benchmark]: Boogie Procedure Inliner took 42.77 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 15:58:37,462 INFO L168 Benchmark]: Boogie Preprocessor took 26.76 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 15:58:37,462 INFO L168 Benchmark]: RCFGBuilder took 407.90 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 999.0 MB in the end (delta: 59.5 MB). Peak memory consumption was 59.5 MB. Max. memory is 11.5 GB. [2019-12-07 15:58:37,463 INFO L168 Benchmark]: TraceAbstraction took 140492.28 ms. Allocated memory was 1.1 GB in the beginning and 8.4 GB in the end (delta: 7.3 GB). Free memory was 999.0 MB in the beginning and 4.7 GB in the end (delta: -3.7 GB). Peak memory consumption was 3.6 GB. Max. memory is 11.5 GB. [2019-12-07 15:58:37,463 INFO L168 Benchmark]: Witness Printer took 78.85 ms. Allocated memory is still 8.4 GB. Free memory was 4.7 GB in the beginning and 4.6 GB in the end (delta: 44.8 MB). Peak memory consumption was 44.8 MB. Max. memory is 11.5 GB. [2019-12-07 15:58:37,465 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 395.85 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 97.5 MB). Free memory was 934.0 MB in the beginning and 1.1 GB in the end (delta: -129.9 MB). Peak memory consumption was 18.3 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 42.77 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.76 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 407.90 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 999.0 MB in the end (delta: 59.5 MB). Peak memory consumption was 59.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 140492.28 ms. Allocated memory was 1.1 GB in the beginning and 8.4 GB in the end (delta: 7.3 GB). Free memory was 999.0 MB in the beginning and 4.7 GB in the end (delta: -3.7 GB). Peak memory consumption was 3.6 GB. Max. memory is 11.5 GB. * Witness Printer took 78.85 ms. Allocated memory is still 8.4 GB. Free memory was 4.7 GB in the beginning and 4.6 GB in the end (delta: 44.8 MB). Peak memory consumption was 44.8 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.0s, 173 ProgramPointsBefore, 94 ProgramPointsAfterwards, 210 TransitionsBefore, 104 TransitionsAfterwards, 17114 CoEnabledTransitionPairs, 7 FixpointIterations, 30 TrivialSequentialCompositions, 44 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 39 ConcurrentYvCompositions, 31 ChoiceCompositions, 5882 VarBasedMoverChecksPositive, 246 VarBasedMoverChecksNegative, 66 SemBasedMoverChecksPositive, 253 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.8s, 0 MoverChecksTotal, 78185 CheckedPairsTotal, 113 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L800] FCALL, FORK 0 pthread_create(&t2183, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] [L730] 1 y$r_buff1_thd0 = y$r_buff0_thd0 [L731] 1 y$r_buff1_thd1 = y$r_buff0_thd1 [L732] 1 y$r_buff1_thd2 = y$r_buff0_thd2 [L733] 1 y$r_buff1_thd3 = y$r_buff0_thd3 [L734] 1 y$r_buff0_thd1 = (_Bool)1 [L737] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L740] EXPR 1 y$w_buff0_used && y$r_buff0_thd1 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd1 ? y$w_buff1 : y) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L802] FCALL, FORK 0 pthread_create(&t2184, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L740] 1 y = y$w_buff0_used && y$r_buff0_thd1 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd1 ? y$w_buff1 : y) [L804] FCALL, FORK 0 pthread_create(&t2185, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L754] 2 x = 2 VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L757] 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L741] 1 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd1 ? (_Bool)0 : y$w_buff0_used [L742] 1 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd1 || y$w_buff1_used && y$r_buff1_thd1 ? (_Bool)0 : y$w_buff1_used [L771] 3 __unbuffered_p2_EAX = x [L774] 3 y = 1 VAL [__unbuffered_cnt=1, __unbuffered_p2_EAX=2, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y=2] [L777] 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [__unbuffered_cnt=1, __unbuffered_p2_EAX=2, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y=2] [L758] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L759] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L760] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L778] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L779] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L780] 3 y$r_buff0_thd3 = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$r_buff0_thd3 [L810] EXPR 0 y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=2, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] [L810] 0 y = y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L811] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L812] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L813] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L814] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L817] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L818] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L819] 0 y$flush_delayed = weak$$choice2 [L820] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=2, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] [L821] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=2, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] [L821] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L822] EXPR 0 weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=2, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] [L822] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L823] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L824] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L825] EXPR 0 weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=2, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] [L825] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L827] EXPR 0 weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=2, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] [L827] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L828] 0 main$tmp_guard1 = !(x == 2 && y == 2 && __unbuffered_p2_EAX == 2) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=2, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 164 locations, 2 error locations. Result: UNSAFE, OverallTime: 140.3s, OverallIterations: 31, TraceHistogramMax: 1, AutomataDifference: 32.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 7179 SDtfs, 7057 SDslu, 16788 SDs, 0 SdLazy, 10788 SolverSat, 343 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 6.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 297 GetRequests, 61 SyntacticMatches, 28 SemanticMatches, 208 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 334 ImplicationChecksByTransitivity, 1.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=239204occurred in iteration=7, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 88.6s AutomataMinimizationTime, 30 MinimizatonAttempts, 534776 StatesRemovedByMinimization, 28 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.2s InterpolantComputationTime, 1306 NumberOfCodeBlocks, 1306 NumberOfCodeBlocksAsserted, 31 NumberOfCheckSat, 1208 ConstructedInterpolants, 0 QuantifiedInterpolants, 192497 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 30 InterpolantComputations, 30 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...