./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe028_rmo.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_6f9e0693-3f0e-474e-9592-a620d1d4cf1b/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_6f9e0693-3f0e-474e-9592-a620d1d4cf1b/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_6f9e0693-3f0e-474e-9592-a620d1d4cf1b/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_6f9e0693-3f0e-474e-9592-a620d1d4cf1b/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe028_rmo.oepc.i -s /tmp/vcloud-vcloud-master/worker/run_dir_6f9e0693-3f0e-474e-9592-a620d1d4cf1b/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_6f9e0693-3f0e-474e-9592-a620d1d4cf1b/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 40a4c4983f467c89f9ad0bd81df3d7c2280ebc02 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:47:14,386 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:47:14,388 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:47:14,397 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:47:14,397 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:47:14,398 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:47:14,399 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:47:14,400 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:47:14,402 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:47:14,402 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:47:14,403 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:47:14,404 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:47:14,404 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:47:14,405 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:47:14,405 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:47:14,406 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:47:14,407 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:47:14,407 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:47:14,408 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:47:14,410 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:47:14,411 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:47:14,412 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:47:14,412 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:47:14,413 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:47:14,414 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:47:14,415 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:47:14,415 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:47:14,415 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:47:14,415 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:47:14,416 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:47:14,416 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:47:14,417 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:47:14,417 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:47:14,418 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:47:14,419 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:47:14,419 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:47:14,419 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:47:14,420 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:47:14,420 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:47:14,421 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:47:14,421 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:47:14,422 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_6f9e0693-3f0e-474e-9592-a620d1d4cf1b/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 18:47:14,434 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:47:14,435 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:47:14,435 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:47:14,436 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:47:14,436 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:47:14,436 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:47:14,436 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:47:14,436 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:47:14,437 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:47:14,437 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:47:14,437 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 18:47:14,437 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 18:47:14,437 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 18:47:14,438 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:47:14,438 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:47:14,438 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:47:14,438 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 18:47:14,438 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:47:14,438 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:47:14,439 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 18:47:14,439 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 18:47:14,439 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:47:14,439 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:47:14,439 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 18:47:14,440 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 18:47:14,440 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:47:14,440 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 18:47:14,440 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 18:47:14,440 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:47:14,440 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_6f9e0693-3f0e-474e-9592-a620d1d4cf1b/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 40a4c4983f467c89f9ad0bd81df3d7c2280ebc02 [2019-12-07 18:47:14,541 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:47:14,549 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:47:14,551 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:47:14,553 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:47:14,553 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:47:14,554 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_6f9e0693-3f0e-474e-9592-a620d1d4cf1b/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe028_rmo.oepc.i [2019-12-07 18:47:14,597 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_6f9e0693-3f0e-474e-9592-a620d1d4cf1b/bin/uautomizer/data/3d895c6a3/8bf8322758d14c60bf32951a8138d7b8/FLAG13096a1be [2019-12-07 18:47:15,058 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:47:15,058 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_6f9e0693-3f0e-474e-9592-a620d1d4cf1b/sv-benchmarks/c/pthread-wmm/safe028_rmo.oepc.i [2019-12-07 18:47:15,068 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_6f9e0693-3f0e-474e-9592-a620d1d4cf1b/bin/uautomizer/data/3d895c6a3/8bf8322758d14c60bf32951a8138d7b8/FLAG13096a1be [2019-12-07 18:47:15,077 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_6f9e0693-3f0e-474e-9592-a620d1d4cf1b/bin/uautomizer/data/3d895c6a3/8bf8322758d14c60bf32951a8138d7b8 [2019-12-07 18:47:15,079 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:47:15,080 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:47:15,081 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:47:15,081 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:47:15,083 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:47:15,084 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:47:15" (1/1) ... [2019-12-07 18:47:15,085 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@551fb3cf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:15, skipping insertion in model container [2019-12-07 18:47:15,085 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:47:15" (1/1) ... [2019-12-07 18:47:15,090 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:47:15,120 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:47:15,378 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:47:15,386 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:47:15,433 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:47:15,479 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:47:15,480 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:15 WrapperNode [2019-12-07 18:47:15,480 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:47:15,480 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:47:15,480 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:47:15,480 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:47:15,486 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:15" (1/1) ... [2019-12-07 18:47:15,500 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:15" (1/1) ... [2019-12-07 18:47:15,518 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:47:15,518 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:47:15,518 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:47:15,518 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:47:15,525 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:15" (1/1) ... [2019-12-07 18:47:15,525 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:15" (1/1) ... [2019-12-07 18:47:15,528 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:15" (1/1) ... [2019-12-07 18:47:15,529 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:15" (1/1) ... [2019-12-07 18:47:15,537 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:15" (1/1) ... [2019-12-07 18:47:15,540 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:15" (1/1) ... [2019-12-07 18:47:15,543 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:15" (1/1) ... [2019-12-07 18:47:15,548 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:47:15,548 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:47:15,548 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:47:15,548 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:47:15,549 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:15" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6f9e0693-3f0e-474e-9592-a620d1d4cf1b/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:47:15,590 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-12-07 18:47:15,590 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 18:47:15,590 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 18:47:15,590 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 18:47:15,590 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 18:47:15,591 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 18:47:15,591 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 18:47:15,591 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 18:47:15,591 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 18:47:15,591 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 18:47:15,591 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 18:47:15,591 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2019-12-07 18:47:15,591 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 18:47:15,591 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:47:15,592 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:47:15,593 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 18:47:16,032 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:47:16,032 INFO L287 CfgBuilder]: Removed 6 assume(true) statements. [2019-12-07 18:47:16,033 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:47:16 BoogieIcfgContainer [2019-12-07 18:47:16,033 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:47:16,033 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 18:47:16,033 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 18:47:16,035 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 18:47:16,035 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 06:47:15" (1/3) ... [2019-12-07 18:47:16,036 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@13841269 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:47:16, skipping insertion in model container [2019-12-07 18:47:16,036 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:47:15" (2/3) ... [2019-12-07 18:47:16,036 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@13841269 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:47:16, skipping insertion in model container [2019-12-07 18:47:16,036 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:47:16" (3/3) ... [2019-12-07 18:47:16,037 INFO L109 eAbstractionObserver]: Analyzing ICFG safe028_rmo.oepc.i [2019-12-07 18:47:16,043 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 18:47:16,044 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 18:47:16,048 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-12-07 18:47:16,049 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 18:47:16,079 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,079 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~nondet3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,079 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~nondet4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,079 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,079 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~mem5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,079 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,080 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~nondet3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,080 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~nondet4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,080 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,080 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,081 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~mem6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,081 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,081 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,081 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,081 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~mem6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,081 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,082 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,082 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,082 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,082 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,082 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,082 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,083 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,083 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,083 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,083 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,083 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,083 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,084 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,084 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,084 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,084 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,084 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,084 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,085 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,085 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,085 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,085 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,085 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,085 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,086 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,086 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,086 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,086 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,086 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,086 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,087 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,087 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,087 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,087 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,087 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,087 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,088 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,088 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,088 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,088 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,088 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,088 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,088 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,089 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,089 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,089 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,089 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,089 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,089 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,090 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,090 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,090 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,090 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,090 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,090 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,091 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,091 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,091 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,091 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,091 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,091 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,092 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,092 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,092 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,092 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,092 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,092 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~mem27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,093 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,093 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,093 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,093 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,093 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~mem28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,094 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,094 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,094 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,094 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,094 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,094 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,095 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~mem28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,095 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,095 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,095 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,095 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,095 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,096 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,096 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,096 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,096 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,097 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,097 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,097 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,097 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,097 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,097 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,098 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,098 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,098 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,098 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,098 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,098 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,098 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,099 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,099 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,099 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,099 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,099 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,099 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,100 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,100 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,100 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,100 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,100 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,100 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,100 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,101 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,101 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,102 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,102 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,102 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~nondet37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,102 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~nondet38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,102 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,102 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,102 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~nondet37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,103 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,103 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~nondet38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,103 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,103 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,103 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,103 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,103 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,104 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,104 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,104 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,104 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,104 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,104 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,105 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,105 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,105 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,105 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,105 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,105 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,105 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,106 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,106 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,106 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,106 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,106 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,106 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,106 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,107 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,107 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,107 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,107 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,107 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,107 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,108 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,108 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,108 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,108 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,108 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,108 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,109 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,109 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,109 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,109 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,109 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,109 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,109 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,110 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,110 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,110 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,110 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,110 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,110 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,111 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,111 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,111 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite57| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,111 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,111 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,111 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,111 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite57| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite57| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite57| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,114 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,114 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,114 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,114 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,114 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,114 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,115 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,115 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,115 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,115 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,115 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,115 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,115 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,116 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,116 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,116 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,116 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,116 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,116 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite67| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,116 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite67| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,117 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,117 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,117 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite67| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,117 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite67| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,117 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite68| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,117 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite68| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,118 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite68| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,118 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite68| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,118 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite69| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,118 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite69| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,118 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite69| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,118 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite69| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,118 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite70| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,119 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite70| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,119 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite70| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,119 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite70| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,119 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,119 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:47:16,131 INFO L249 AbstractCegarLoop]: Starting to check reachability of 4 error locations. [2019-12-07 18:47:16,143 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 18:47:16,143 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 18:47:16,143 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 18:47:16,143 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:47:16,144 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:47:16,144 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 18:47:16,144 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:47:16,144 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 18:47:16,156 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 223 places, 276 transitions [2019-12-07 18:47:16,157 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 223 places, 276 transitions [2019-12-07 18:47:16,246 INFO L134 PetriNetUnfolder]: 63/273 cut-off events. [2019-12-07 18:47:16,246 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:47:16,259 INFO L76 FinitePrefix]: Finished finitePrefix Result has 283 conditions, 273 events. 63/273 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 14. Compared 1060 event pairs. 9/218 useless extension candidates. Maximal degree in co-relation 225. Up to 2 conditions per place. [2019-12-07 18:47:16,289 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 223 places, 276 transitions [2019-12-07 18:47:16,345 INFO L134 PetriNetUnfolder]: 63/273 cut-off events. [2019-12-07 18:47:16,345 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:47:16,357 INFO L76 FinitePrefix]: Finished finitePrefix Result has 283 conditions, 273 events. 63/273 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 14. Compared 1060 event pairs. 9/218 useless extension candidates. Maximal degree in co-relation 225. Up to 2 conditions per place. [2019-12-07 18:47:16,388 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 32976 [2019-12-07 18:47:16,389 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 18:47:20,312 WARN L192 SmtUtils]: Spent 291.00 ms on a formula simplification. DAG size of input: 136 DAG size of output: 132 [2019-12-07 18:47:20,464 WARN L192 SmtUtils]: Spent 151.00 ms on a formula simplification that was a NOOP. DAG size: 130 [2019-12-07 18:47:20,494 INFO L206 etLargeBlockEncoding]: Checked pairs total: 183707 [2019-12-07 18:47:20,494 INFO L214 etLargeBlockEncoding]: Total number of compositions: 146 [2019-12-07 18:47:20,496 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 117 places, 138 transitions [2019-12-07 18:48:45,645 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 300418 states. [2019-12-07 18:48:45,647 INFO L276 IsEmpty]: Start isEmpty. Operand 300418 states. [2019-12-07 18:48:45,680 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2019-12-07 18:48:45,680 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:48:45,681 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:48:45,681 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:48:45,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:45,685 INFO L82 PathProgramCache]: Analyzing trace with hash -2075695311, now seen corresponding path program 1 times [2019-12-07 18:48:45,691 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:45,691 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [185342686] [2019-12-07 18:48:45,691 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:45,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:45,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:48:45,877 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [185342686] [2019-12-07 18:48:45,878 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:48:45,878 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:48:45,879 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1367436007] [2019-12-07 18:48:45,883 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:48:45,883 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:48:45,895 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:48:45,895 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:48:45,897 INFO L87 Difference]: Start difference. First operand 300418 states. Second operand 3 states. [2019-12-07 18:48:47,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:48:47,362 INFO L93 Difference]: Finished difference Result 300418 states and 1374458 transitions. [2019-12-07 18:48:47,363 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:48:47,364 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 17 [2019-12-07 18:48:47,364 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:48:48,466 INFO L225 Difference]: With dead ends: 300418 [2019-12-07 18:48:48,466 INFO L226 Difference]: Without dead ends: 281698 [2019-12-07 18:48:48,467 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:49:13,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281698 states. [2019-12-07 18:49:17,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281698 to 281698. [2019-12-07 18:49:17,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 281698 states. [2019-12-07 18:49:18,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 281698 states to 281698 states and 1288736 transitions. [2019-12-07 18:49:18,685 INFO L78 Accepts]: Start accepts. Automaton has 281698 states and 1288736 transitions. Word has length 17 [2019-12-07 18:49:18,686 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:49:18,686 INFO L462 AbstractCegarLoop]: Abstraction has 281698 states and 1288736 transitions. [2019-12-07 18:49:18,686 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:49:18,686 INFO L276 IsEmpty]: Start isEmpty. Operand 281698 states and 1288736 transitions. [2019-12-07 18:49:18,713 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2019-12-07 18:49:18,713 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:49:18,714 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:49:18,714 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:49:18,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:18,714 INFO L82 PathProgramCache]: Analyzing trace with hash 1282420922, now seen corresponding path program 1 times [2019-12-07 18:49:18,714 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:18,714 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1949881151] [2019-12-07 18:49:18,715 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:18,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:18,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:18,795 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1949881151] [2019-12-07 18:49:18,795 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:49:18,795 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:49:18,795 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1680969503] [2019-12-07 18:49:18,797 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:49:18,797 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:18,797 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:49:18,797 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:49:18,797 INFO L87 Difference]: Start difference. First operand 281698 states and 1288736 transitions. Second operand 4 states. [2019-12-07 18:49:19,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:19,173 INFO L93 Difference]: Finished difference Result 71266 states and 271018 transitions. [2019-12-07 18:49:19,173 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:49:19,174 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 18 [2019-12-07 18:49:19,174 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:49:19,342 INFO L225 Difference]: With dead ends: 71266 [2019-12-07 18:49:19,343 INFO L226 Difference]: Without dead ends: 52546 [2019-12-07 18:49:19,343 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:49:19,854 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52546 states. [2019-12-07 18:49:20,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52546 to 52546. [2019-12-07 18:49:20,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52546 states. [2019-12-07 18:49:21,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52546 states to 52546 states and 187648 transitions. [2019-12-07 18:49:21,158 INFO L78 Accepts]: Start accepts. Automaton has 52546 states and 187648 transitions. Word has length 18 [2019-12-07 18:49:21,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:49:21,158 INFO L462 AbstractCegarLoop]: Abstraction has 52546 states and 187648 transitions. [2019-12-07 18:49:21,158 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:49:21,158 INFO L276 IsEmpty]: Start isEmpty. Operand 52546 states and 187648 transitions. [2019-12-07 18:49:21,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 18:49:21,175 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:49:21,175 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:49:21,175 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:49:21,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:21,175 INFO L82 PathProgramCache]: Analyzing trace with hash 285755223, now seen corresponding path program 1 times [2019-12-07 18:49:21,175 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:21,176 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [318507388] [2019-12-07 18:49:21,176 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:21,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:21,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:21,235 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [318507388] [2019-12-07 18:49:21,236 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:49:21,236 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:49:21,236 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [548646742] [2019-12-07 18:49:21,236 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:49:21,236 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:21,236 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:49:21,236 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:49:21,236 INFO L87 Difference]: Start difference. First operand 52546 states and 187648 transitions. Second operand 3 states. [2019-12-07 18:49:21,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:21,390 INFO L93 Difference]: Finished difference Result 49978 states and 176124 transitions. [2019-12-07 18:49:21,391 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:49:21,391 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-12-07 18:49:21,391 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:49:21,488 INFO L225 Difference]: With dead ends: 49978 [2019-12-07 18:49:21,488 INFO L226 Difference]: Without dead ends: 49978 [2019-12-07 18:49:21,488 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:49:21,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49978 states. [2019-12-07 18:49:22,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49978 to 49978. [2019-12-07 18:49:22,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49978 states. [2019-12-07 18:49:22,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49978 states to 49978 states and 176124 transitions. [2019-12-07 18:49:22,569 INFO L78 Accepts]: Start accepts. Automaton has 49978 states and 176124 transitions. Word has length 28 [2019-12-07 18:49:22,569 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:49:22,569 INFO L462 AbstractCegarLoop]: Abstraction has 49978 states and 176124 transitions. [2019-12-07 18:49:22,569 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:49:22,569 INFO L276 IsEmpty]: Start isEmpty. Operand 49978 states and 176124 transitions. [2019-12-07 18:49:22,585 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-12-07 18:49:22,585 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:49:22,585 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:49:22,585 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:49:22,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:22,586 INFO L82 PathProgramCache]: Analyzing trace with hash -1493897438, now seen corresponding path program 1 times [2019-12-07 18:49:22,586 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:22,586 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1217391892] [2019-12-07 18:49:22,586 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:22,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:22,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:22,661 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1217391892] [2019-12-07 18:49:22,661 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:49:22,661 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:49:22,661 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1566163570] [2019-12-07 18:49:22,661 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:49:22,661 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:22,661 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:49:22,662 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:49:22,662 INFO L87 Difference]: Start difference. First operand 49978 states and 176124 transitions. Second operand 5 states. [2019-12-07 18:49:22,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:22,762 INFO L93 Difference]: Finished difference Result 21608 states and 73711 transitions. [2019-12-07 18:49:22,763 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:49:22,763 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 29 [2019-12-07 18:49:22,763 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:49:22,791 INFO L225 Difference]: With dead ends: 21608 [2019-12-07 18:49:22,791 INFO L226 Difference]: Without dead ends: 19332 [2019-12-07 18:49:22,792 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:49:22,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19332 states. [2019-12-07 18:49:23,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19332 to 19332. [2019-12-07 18:49:23,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19332 states. [2019-12-07 18:49:23,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19332 states to 19332 states and 65883 transitions. [2019-12-07 18:49:23,189 INFO L78 Accepts]: Start accepts. Automaton has 19332 states and 65883 transitions. Word has length 29 [2019-12-07 18:49:23,189 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:49:23,189 INFO L462 AbstractCegarLoop]: Abstraction has 19332 states and 65883 transitions. [2019-12-07 18:49:23,189 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:49:23,190 INFO L276 IsEmpty]: Start isEmpty. Operand 19332 states and 65883 transitions. [2019-12-07 18:49:23,213 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-12-07 18:49:23,213 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:49:23,214 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:49:23,214 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:49:23,214 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:23,214 INFO L82 PathProgramCache]: Analyzing trace with hash -541366890, now seen corresponding path program 1 times [2019-12-07 18:49:23,214 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:23,214 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [231296994] [2019-12-07 18:49:23,214 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:23,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:23,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:23,302 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [231296994] [2019-12-07 18:49:23,302 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:49:23,302 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:49:23,302 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1769294205] [2019-12-07 18:49:23,302 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:49:23,303 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:23,303 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:49:23,303 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:49:23,303 INFO L87 Difference]: Start difference. First operand 19332 states and 65883 transitions. Second operand 6 states. [2019-12-07 18:49:23,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:23,553 INFO L93 Difference]: Finished difference Result 18215 states and 63249 transitions. [2019-12-07 18:49:23,553 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:49:23,553 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 45 [2019-12-07 18:49:23,553 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:49:23,577 INFO L225 Difference]: With dead ends: 18215 [2019-12-07 18:49:23,577 INFO L226 Difference]: Without dead ends: 18128 [2019-12-07 18:49:23,577 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:49:23,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18128 states. [2019-12-07 18:49:23,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18128 to 18128. [2019-12-07 18:49:23,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18128 states. [2019-12-07 18:49:23,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18128 states to 18128 states and 63053 transitions. [2019-12-07 18:49:23,951 INFO L78 Accepts]: Start accepts. Automaton has 18128 states and 63053 transitions. Word has length 45 [2019-12-07 18:49:23,951 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:49:23,951 INFO L462 AbstractCegarLoop]: Abstraction has 18128 states and 63053 transitions. [2019-12-07 18:49:23,951 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:49:23,951 INFO L276 IsEmpty]: Start isEmpty. Operand 18128 states and 63053 transitions. [2019-12-07 18:49:23,974 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 18:49:23,974 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:49:23,974 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:49:23,974 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:49:23,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:23,974 INFO L82 PathProgramCache]: Analyzing trace with hash -1488532936, now seen corresponding path program 1 times [2019-12-07 18:49:23,974 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:23,974 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [823240440] [2019-12-07 18:49:23,974 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:23,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:24,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:24,030 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [823240440] [2019-12-07 18:49:24,030 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:49:24,030 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:49:24,030 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2101526445] [2019-12-07 18:49:24,030 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:49:24,031 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:24,031 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:49:24,031 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:49:24,031 INFO L87 Difference]: Start difference. First operand 18128 states and 63053 transitions. Second operand 3 states. [2019-12-07 18:49:24,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:24,112 INFO L93 Difference]: Finished difference Result 17744 states and 61429 transitions. [2019-12-07 18:49:24,113 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:49:24,113 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2019-12-07 18:49:24,113 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:49:24,138 INFO L225 Difference]: With dead ends: 17744 [2019-12-07 18:49:24,138 INFO L226 Difference]: Without dead ends: 17744 [2019-12-07 18:49:24,138 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:49:24,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17744 states. [2019-12-07 18:49:24,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17744 to 17744. [2019-12-07 18:49:24,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17744 states. [2019-12-07 18:49:24,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17744 states to 17744 states and 61429 transitions. [2019-12-07 18:49:24,518 INFO L78 Accepts]: Start accepts. Automaton has 17744 states and 61429 transitions. Word has length 70 [2019-12-07 18:49:24,518 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:49:24,518 INFO L462 AbstractCegarLoop]: Abstraction has 17744 states and 61429 transitions. [2019-12-07 18:49:24,518 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:49:24,518 INFO L276 IsEmpty]: Start isEmpty. Operand 17744 states and 61429 transitions. [2019-12-07 18:49:24,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-12-07 18:49:24,535 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:49:24,536 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:49:24,536 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:49:24,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:24,536 INFO L82 PathProgramCache]: Analyzing trace with hash 726610784, now seen corresponding path program 1 times [2019-12-07 18:49:24,536 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:24,536 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697130933] [2019-12-07 18:49:24,536 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:24,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:24,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:24,585 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1697130933] [2019-12-07 18:49:24,585 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:49:24,585 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:49:24,585 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [672783497] [2019-12-07 18:49:24,585 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:49:24,585 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:24,586 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:49:24,586 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:49:24,586 INFO L87 Difference]: Start difference. First operand 17744 states and 61429 transitions. Second operand 3 states. [2019-12-07 18:49:24,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:24,642 INFO L93 Difference]: Finished difference Result 17743 states and 61427 transitions. [2019-12-07 18:49:24,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:49:24,643 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 71 [2019-12-07 18:49:24,643 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:49:24,668 INFO L225 Difference]: With dead ends: 17743 [2019-12-07 18:49:24,668 INFO L226 Difference]: Without dead ends: 17743 [2019-12-07 18:49:24,668 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:49:24,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17743 states. [2019-12-07 18:49:25,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17743 to 17743. [2019-12-07 18:49:25,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17743 states. [2019-12-07 18:49:25,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17743 states to 17743 states and 61427 transitions. [2019-12-07 18:49:25,044 INFO L78 Accepts]: Start accepts. Automaton has 17743 states and 61427 transitions. Word has length 71 [2019-12-07 18:49:25,045 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:49:25,045 INFO L462 AbstractCegarLoop]: Abstraction has 17743 states and 61427 transitions. [2019-12-07 18:49:25,045 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:49:25,045 INFO L276 IsEmpty]: Start isEmpty. Operand 17743 states and 61427 transitions. [2019-12-07 18:49:25,062 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:49:25,062 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:49:25,062 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:49:25,062 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:49:25,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:25,062 INFO L82 PathProgramCache]: Analyzing trace with hash 1049534817, now seen corresponding path program 1 times [2019-12-07 18:49:25,063 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:25,063 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1394338690] [2019-12-07 18:49:25,063 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:25,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:25,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:25,154 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1394338690] [2019-12-07 18:49:25,154 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:49:25,154 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:49:25,155 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1982172752] [2019-12-07 18:49:25,155 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:49:25,155 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:25,155 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:49:25,156 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:49:25,156 INFO L87 Difference]: Start difference. First operand 17743 states and 61427 transitions. Second operand 5 states. [2019-12-07 18:49:25,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:25,260 INFO L93 Difference]: Finished difference Result 21847 states and 74322 transitions. [2019-12-07 18:49:25,261 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:49:25,261 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 72 [2019-12-07 18:49:25,261 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:49:25,268 INFO L225 Difference]: With dead ends: 21847 [2019-12-07 18:49:25,268 INFO L226 Difference]: Without dead ends: 4661 [2019-12-07 18:49:25,268 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:49:25,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4661 states. [2019-12-07 18:49:25,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4661 to 4661. [2019-12-07 18:49:25,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4661 states. [2019-12-07 18:49:25,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4661 states to 4661 states and 14222 transitions. [2019-12-07 18:49:25,345 INFO L78 Accepts]: Start accepts. Automaton has 4661 states and 14222 transitions. Word has length 72 [2019-12-07 18:49:25,345 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:49:25,345 INFO L462 AbstractCegarLoop]: Abstraction has 4661 states and 14222 transitions. [2019-12-07 18:49:25,345 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:49:25,345 INFO L276 IsEmpty]: Start isEmpty. Operand 4661 states and 14222 transitions. [2019-12-07 18:49:25,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:49:25,349 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:49:25,349 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:49:25,349 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:49:25,349 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:25,349 INFO L82 PathProgramCache]: Analyzing trace with hash 1176538835, now seen corresponding path program 2 times [2019-12-07 18:49:25,349 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:25,349 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1907608812] [2019-12-07 18:49:25,350 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:25,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:25,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:25,865 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1907608812] [2019-12-07 18:49:25,865 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:49:25,865 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2019-12-07 18:49:25,865 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1597981222] [2019-12-07 18:49:25,865 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 18:49:25,865 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:25,866 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 18:49:25,866 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=300, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:49:25,866 INFO L87 Difference]: Start difference. First operand 4661 states and 14222 transitions. Second operand 19 states. [2019-12-07 18:49:29,474 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:29,474 INFO L93 Difference]: Finished difference Result 11896 states and 35834 transitions. [2019-12-07 18:49:29,474 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2019-12-07 18:49:29,474 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 72 [2019-12-07 18:49:29,474 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:49:29,482 INFO L225 Difference]: With dead ends: 11896 [2019-12-07 18:49:29,483 INFO L226 Difference]: Without dead ends: 8451 [2019-12-07 18:49:29,484 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1049 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=501, Invalid=3659, Unknown=0, NotChecked=0, Total=4160 [2019-12-07 18:49:29,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8451 states. [2019-12-07 18:49:29,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8451 to 6729. [2019-12-07 18:49:29,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6729 states. [2019-12-07 18:49:29,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6729 states to 6729 states and 20308 transitions. [2019-12-07 18:49:29,616 INFO L78 Accepts]: Start accepts. Automaton has 6729 states and 20308 transitions. Word has length 72 [2019-12-07 18:49:29,616 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:49:29,616 INFO L462 AbstractCegarLoop]: Abstraction has 6729 states and 20308 transitions. [2019-12-07 18:49:29,616 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 18:49:29,616 INFO L276 IsEmpty]: Start isEmpty. Operand 6729 states and 20308 transitions. [2019-12-07 18:49:29,623 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:49:29,623 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:49:29,623 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:49:29,623 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:49:29,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:29,623 INFO L82 PathProgramCache]: Analyzing trace with hash -631520119, now seen corresponding path program 3 times [2019-12-07 18:49:29,623 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:29,623 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763286794] [2019-12-07 18:49:29,623 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:29,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:30,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:30,137 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763286794] [2019-12-07 18:49:30,137 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:49:30,137 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [20] imperfect sequences [] total 20 [2019-12-07 18:49:30,137 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1452491869] [2019-12-07 18:49:30,137 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-12-07 18:49:30,137 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:30,137 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-12-07 18:49:30,138 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=412, Unknown=0, NotChecked=0, Total=462 [2019-12-07 18:49:30,138 INFO L87 Difference]: Start difference. First operand 6729 states and 20308 transitions. Second operand 22 states. [2019-12-07 18:49:33,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:33,560 INFO L93 Difference]: Finished difference Result 13889 states and 41872 transitions. [2019-12-07 18:49:33,560 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2019-12-07 18:49:33,560 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 72 [2019-12-07 18:49:33,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:49:33,573 INFO L225 Difference]: With dead ends: 13889 [2019-12-07 18:49:33,573 INFO L226 Difference]: Without dead ends: 12521 [2019-12-07 18:49:33,574 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 562 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=270, Invalid=2382, Unknown=0, NotChecked=0, Total=2652 [2019-12-07 18:49:33,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12521 states. [2019-12-07 18:49:33,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12521 to 9627. [2019-12-07 18:49:33,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9627 states. [2019-12-07 18:49:33,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9627 states to 9627 states and 29032 transitions. [2019-12-07 18:49:33,723 INFO L78 Accepts]: Start accepts. Automaton has 9627 states and 29032 transitions. Word has length 72 [2019-12-07 18:49:33,724 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:49:33,724 INFO L462 AbstractCegarLoop]: Abstraction has 9627 states and 29032 transitions. [2019-12-07 18:49:33,724 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-12-07 18:49:33,724 INFO L276 IsEmpty]: Start isEmpty. Operand 9627 states and 29032 transitions. [2019-12-07 18:49:33,732 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:49:33,732 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:49:33,732 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:49:33,732 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:49:33,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:33,732 INFO L82 PathProgramCache]: Analyzing trace with hash -162566405, now seen corresponding path program 4 times [2019-12-07 18:49:33,733 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:33,733 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [317019324] [2019-12-07 18:49:33,733 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:33,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:34,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:34,206 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [317019324] [2019-12-07 18:49:34,206 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:49:34,206 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2019-12-07 18:49:34,206 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [424327629] [2019-12-07 18:49:34,206 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-12-07 18:49:34,206 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:34,206 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 18:49:34,207 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=334, Unknown=0, NotChecked=0, Total=380 [2019-12-07 18:49:34,207 INFO L87 Difference]: Start difference. First operand 9627 states and 29032 transitions. Second operand 20 states. [2019-12-07 18:49:37,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:37,059 INFO L93 Difference]: Finished difference Result 16791 states and 49674 transitions. [2019-12-07 18:49:37,059 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2019-12-07 18:49:37,059 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 72 [2019-12-07 18:49:37,059 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:49:37,073 INFO L225 Difference]: With dead ends: 16791 [2019-12-07 18:49:37,073 INFO L226 Difference]: Without dead ends: 13188 [2019-12-07 18:49:37,074 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 6 SyntacticMatches, 3 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 749 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=359, Invalid=2721, Unknown=0, NotChecked=0, Total=3080 [2019-12-07 18:49:37,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13188 states. [2019-12-07 18:49:37,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13188 to 9909. [2019-12-07 18:49:37,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9909 states. [2019-12-07 18:49:37,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9909 states to 9909 states and 29736 transitions. [2019-12-07 18:49:37,225 INFO L78 Accepts]: Start accepts. Automaton has 9909 states and 29736 transitions. Word has length 72 [2019-12-07 18:49:37,225 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:49:37,225 INFO L462 AbstractCegarLoop]: Abstraction has 9909 states and 29736 transitions. [2019-12-07 18:49:37,225 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-12-07 18:49:37,225 INFO L276 IsEmpty]: Start isEmpty. Operand 9909 states and 29736 transitions. [2019-12-07 18:49:37,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:49:37,233 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:49:37,233 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:49:37,233 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:49:37,233 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:37,233 INFO L82 PathProgramCache]: Analyzing trace with hash 210711269, now seen corresponding path program 5 times [2019-12-07 18:49:37,234 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:37,234 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1089625072] [2019-12-07 18:49:37,234 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:37,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:37,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:37,772 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1089625072] [2019-12-07 18:49:37,772 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:49:37,772 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2019-12-07 18:49:37,772 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [834070836] [2019-12-07 18:49:37,772 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-12-07 18:49:37,772 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:37,772 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 18:49:37,773 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=450, Unknown=0, NotChecked=0, Total=506 [2019-12-07 18:49:37,773 INFO L87 Difference]: Start difference. First operand 9909 states and 29736 transitions. Second operand 23 states. [2019-12-07 18:49:41,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:41,951 INFO L93 Difference]: Finished difference Result 14911 states and 44631 transitions. [2019-12-07 18:49:41,951 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2019-12-07 18:49:41,951 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 72 [2019-12-07 18:49:41,951 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:49:41,965 INFO L225 Difference]: With dead ends: 14911 [2019-12-07 18:49:41,965 INFO L226 Difference]: Without dead ends: 13552 [2019-12-07 18:49:41,966 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 377 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=210, Invalid=1682, Unknown=0, NotChecked=0, Total=1892 [2019-12-07 18:49:42,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13552 states. [2019-12-07 18:49:42,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13552 to 10774. [2019-12-07 18:49:42,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10774 states. [2019-12-07 18:49:42,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10774 states to 10774 states and 32318 transitions. [2019-12-07 18:49:42,145 INFO L78 Accepts]: Start accepts. Automaton has 10774 states and 32318 transitions. Word has length 72 [2019-12-07 18:49:42,145 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:49:42,145 INFO L462 AbstractCegarLoop]: Abstraction has 10774 states and 32318 transitions. [2019-12-07 18:49:42,145 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-12-07 18:49:42,145 INFO L276 IsEmpty]: Start isEmpty. Operand 10774 states and 32318 transitions. [2019-12-07 18:49:42,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:49:42,153 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:49:42,153 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:49:42,153 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:49:42,153 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:42,153 INFO L82 PathProgramCache]: Analyzing trace with hash -875416119, now seen corresponding path program 6 times [2019-12-07 18:49:42,153 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:42,154 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1293075651] [2019-12-07 18:49:42,154 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:42,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:42,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:42,508 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1293075651] [2019-12-07 18:49:42,508 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:49:42,508 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 18:49:42,508 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1777637656] [2019-12-07 18:49:42,509 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 18:49:42,509 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:42,509 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 18:49:42,509 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=205, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:49:42,509 INFO L87 Difference]: Start difference. First operand 10774 states and 32318 transitions. Second operand 16 states. [2019-12-07 18:49:44,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:44,248 INFO L93 Difference]: Finished difference Result 18003 states and 54063 transitions. [2019-12-07 18:49:44,248 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-12-07 18:49:44,249 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2019-12-07 18:49:44,249 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:49:44,272 INFO L225 Difference]: With dead ends: 18003 [2019-12-07 18:49:44,272 INFO L226 Difference]: Without dead ends: 15089 [2019-12-07 18:49:44,273 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 228 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=195, Invalid=1137, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 18:49:44,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15089 states. [2019-12-07 18:49:44,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15089 to 12025. [2019-12-07 18:49:44,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12025 states. [2019-12-07 18:49:44,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12025 states to 12025 states and 35826 transitions. [2019-12-07 18:49:44,457 INFO L78 Accepts]: Start accepts. Automaton has 12025 states and 35826 transitions. Word has length 72 [2019-12-07 18:49:44,457 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:49:44,457 INFO L462 AbstractCegarLoop]: Abstraction has 12025 states and 35826 transitions. [2019-12-07 18:49:44,457 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 18:49:44,457 INFO L276 IsEmpty]: Start isEmpty. Operand 12025 states and 35826 transitions. [2019-12-07 18:49:44,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:49:44,468 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:49:44,468 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:49:44,468 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:49:44,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:44,469 INFO L82 PathProgramCache]: Analyzing trace with hash 1479181461, now seen corresponding path program 7 times [2019-12-07 18:49:44,469 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:44,469 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221213098] [2019-12-07 18:49:44,469 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:44,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:44,757 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:44,757 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221213098] [2019-12-07 18:49:44,757 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:49:44,757 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 18:49:44,757 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [5665434] [2019-12-07 18:49:44,757 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 18:49:44,757 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:44,758 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 18:49:44,758 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=179, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:49:44,758 INFO L87 Difference]: Start difference. First operand 12025 states and 35826 transitions. Second operand 15 states. [2019-12-07 18:49:46,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:46,282 INFO L93 Difference]: Finished difference Result 14327 states and 41784 transitions. [2019-12-07 18:49:46,282 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-12-07 18:49:46,282 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 72 [2019-12-07 18:49:46,282 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:49:46,296 INFO L225 Difference]: With dead ends: 14327 [2019-12-07 18:49:46,297 INFO L226 Difference]: Without dead ends: 13683 [2019-12-07 18:49:46,297 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 165 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=167, Invalid=889, Unknown=0, NotChecked=0, Total=1056 [2019-12-07 18:49:46,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13683 states. [2019-12-07 18:49:46,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13683 to 11679. [2019-12-07 18:49:46,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11679 states. [2019-12-07 18:49:46,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11679 states to 11679 states and 34906 transitions. [2019-12-07 18:49:46,471 INFO L78 Accepts]: Start accepts. Automaton has 11679 states and 34906 transitions. Word has length 72 [2019-12-07 18:49:46,471 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:49:46,471 INFO L462 AbstractCegarLoop]: Abstraction has 11679 states and 34906 transitions. [2019-12-07 18:49:46,471 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 18:49:46,471 INFO L276 IsEmpty]: Start isEmpty. Operand 11679 states and 34906 transitions. [2019-12-07 18:49:46,480 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:49:46,481 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:49:46,481 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:49:46,481 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:49:46,481 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:46,481 INFO L82 PathProgramCache]: Analyzing trace with hash 723143141, now seen corresponding path program 8 times [2019-12-07 18:49:46,481 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:46,481 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2098348145] [2019-12-07 18:49:46,481 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:46,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:47,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:47,011 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2098348145] [2019-12-07 18:49:47,011 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:49:47,011 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 18:49:47,012 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2005454140] [2019-12-07 18:49:47,012 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 18:49:47,012 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:47,012 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 18:49:47,012 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=496, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:49:47,012 INFO L87 Difference]: Start difference. First operand 11679 states and 34906 transitions. Second operand 24 states. [2019-12-07 18:49:50,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:50,508 INFO L93 Difference]: Finished difference Result 19691 states and 59033 transitions. [2019-12-07 18:49:50,508 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2019-12-07 18:49:50,508 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 18:49:50,508 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:49:50,526 INFO L225 Difference]: With dead ends: 19691 [2019-12-07 18:49:50,526 INFO L226 Difference]: Without dead ends: 16968 [2019-12-07 18:49:50,527 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 485 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=253, Invalid=2099, Unknown=0, NotChecked=0, Total=2352 [2019-12-07 18:49:50,582 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16968 states. [2019-12-07 18:49:50,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16968 to 13109. [2019-12-07 18:49:50,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13109 states. [2019-12-07 18:49:50,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13109 states to 13109 states and 39148 transitions. [2019-12-07 18:49:50,733 INFO L78 Accepts]: Start accepts. Automaton has 13109 states and 39148 transitions. Word has length 72 [2019-12-07 18:49:50,734 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:49:50,734 INFO L462 AbstractCegarLoop]: Abstraction has 13109 states and 39148 transitions. [2019-12-07 18:49:50,734 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 18:49:50,734 INFO L276 IsEmpty]: Start isEmpty. Operand 13109 states and 39148 transitions. [2019-12-07 18:49:50,746 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:49:50,746 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:49:50,746 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:49:50,746 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:49:50,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:50,746 INFO L82 PathProgramCache]: Analyzing trace with hash 1878751243, now seen corresponding path program 9 times [2019-12-07 18:49:50,747 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:50,747 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1462101788] [2019-12-07 18:49:50,747 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:50,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:50,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:50,935 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1462101788] [2019-12-07 18:49:50,935 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:49:50,935 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 18:49:50,935 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1711357902] [2019-12-07 18:49:50,935 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 18:49:50,935 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:50,935 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 18:49:50,935 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:49:50,936 INFO L87 Difference]: Start difference. First operand 13109 states and 39148 transitions. Second operand 12 states. [2019-12-07 18:49:51,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:51,720 INFO L93 Difference]: Finished difference Result 19446 states and 58069 transitions. [2019-12-07 18:49:51,721 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 18:49:51,721 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 72 [2019-12-07 18:49:51,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:49:51,746 INFO L225 Difference]: With dead ends: 19446 [2019-12-07 18:49:51,747 INFO L226 Difference]: Without dead ends: 16008 [2019-12-07 18:49:51,747 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 67 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=104, Invalid=402, Unknown=0, NotChecked=0, Total=506 [2019-12-07 18:49:51,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16008 states. [2019-12-07 18:49:51,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16008 to 13370. [2019-12-07 18:49:51,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13370 states. [2019-12-07 18:49:51,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13370 states to 13370 states and 39916 transitions. [2019-12-07 18:49:51,947 INFO L78 Accepts]: Start accepts. Automaton has 13370 states and 39916 transitions. Word has length 72 [2019-12-07 18:49:51,947 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:49:51,947 INFO L462 AbstractCegarLoop]: Abstraction has 13370 states and 39916 transitions. [2019-12-07 18:49:51,947 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 18:49:51,947 INFO L276 IsEmpty]: Start isEmpty. Operand 13370 states and 39916 transitions. [2019-12-07 18:49:51,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:49:51,959 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:49:51,959 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:49:51,959 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:49:51,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:51,959 INFO L82 PathProgramCache]: Analyzing trace with hash 1474852141, now seen corresponding path program 10 times [2019-12-07 18:49:51,960 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:51,960 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1938620524] [2019-12-07 18:49:51,960 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:51,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:52,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:52,768 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1938620524] [2019-12-07 18:49:52,768 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:49:52,768 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 18:49:52,768 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [439681958] [2019-12-07 18:49:52,768 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 18:49:52,768 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:52,768 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 18:49:52,769 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=69, Invalid=483, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:49:52,769 INFO L87 Difference]: Start difference. First operand 13370 states and 39916 transitions. Second operand 24 states. [2019-12-07 18:49:57,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:57,080 INFO L93 Difference]: Finished difference Result 18703 states and 55946 transitions. [2019-12-07 18:49:57,080 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-12-07 18:49:57,080 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 18:49:57,080 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:49:57,104 INFO L225 Difference]: With dead ends: 18703 [2019-12-07 18:49:57,104 INFO L226 Difference]: Without dead ends: 18543 [2019-12-07 18:49:57,104 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 430 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=256, Invalid=1906, Unknown=0, NotChecked=0, Total=2162 [2019-12-07 18:49:57,162 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18543 states. [2019-12-07 18:49:57,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18543 to 16884. [2019-12-07 18:49:57,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16884 states. [2019-12-07 18:49:57,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16884 states to 16884 states and 51127 transitions. [2019-12-07 18:49:57,348 INFO L78 Accepts]: Start accepts. Automaton has 16884 states and 51127 transitions. Word has length 72 [2019-12-07 18:49:57,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:49:57,348 INFO L462 AbstractCegarLoop]: Abstraction has 16884 states and 51127 transitions. [2019-12-07 18:49:57,348 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 18:49:57,348 INFO L276 IsEmpty]: Start isEmpty. Operand 16884 states and 51127 transitions. [2019-12-07 18:49:57,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:49:57,363 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:49:57,363 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:49:57,363 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:49:57,363 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:57,363 INFO L82 PathProgramCache]: Analyzing trace with hash -1548787677, now seen corresponding path program 11 times [2019-12-07 18:49:57,363 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:57,364 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2072294938] [2019-12-07 18:49:57,364 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:57,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:57,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:57,644 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2072294938] [2019-12-07 18:49:57,644 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:49:57,644 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 18:49:57,645 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2076323471] [2019-12-07 18:49:57,645 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 18:49:57,645 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:57,645 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 18:49:57,645 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=179, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:49:57,645 INFO L87 Difference]: Start difference. First operand 16884 states and 51127 transitions. Second operand 15 states. [2019-12-07 18:49:58,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:58,913 INFO L93 Difference]: Finished difference Result 23430 states and 70771 transitions. [2019-12-07 18:49:58,913 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 18:49:58,913 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 72 [2019-12-07 18:49:58,914 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:49:58,937 INFO L225 Difference]: With dead ends: 23430 [2019-12-07 18:49:58,937 INFO L226 Difference]: Without dead ends: 23170 [2019-12-07 18:49:58,938 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 105 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=120, Invalid=636, Unknown=0, NotChecked=0, Total=756 [2019-12-07 18:49:59,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23170 states. [2019-12-07 18:49:59,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23170 to 20198. [2019-12-07 18:49:59,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20198 states. [2019-12-07 18:49:59,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20198 states to 20198 states and 61707 transitions. [2019-12-07 18:49:59,252 INFO L78 Accepts]: Start accepts. Automaton has 20198 states and 61707 transitions. Word has length 72 [2019-12-07 18:49:59,252 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:49:59,252 INFO L462 AbstractCegarLoop]: Abstraction has 20198 states and 61707 transitions. [2019-12-07 18:49:59,252 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 18:49:59,252 INFO L276 IsEmpty]: Start isEmpty. Operand 20198 states and 61707 transitions. [2019-12-07 18:49:59,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:49:59,270 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:49:59,270 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:49:59,270 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:49:59,270 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:59,270 INFO L82 PathProgramCache]: Analyzing trace with hash -754793831, now seen corresponding path program 12 times [2019-12-07 18:49:59,271 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:59,271 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431923313] [2019-12-07 18:49:59,271 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:59,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:59,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:59,826 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [431923313] [2019-12-07 18:49:59,827 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:49:59,827 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 18:49:59,827 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [926161763] [2019-12-07 18:49:59,827 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 18:49:59,827 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:59,827 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 18:49:59,828 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=496, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:49:59,828 INFO L87 Difference]: Start difference. First operand 20198 states and 61707 transitions. Second operand 24 states. [2019-12-07 18:50:04,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:04,167 INFO L93 Difference]: Finished difference Result 28688 states and 87389 transitions. [2019-12-07 18:50:04,167 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2019-12-07 18:50:04,167 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 18:50:04,168 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:50:04,196 INFO L225 Difference]: With dead ends: 28688 [2019-12-07 18:50:04,196 INFO L226 Difference]: Without dead ends: 24605 [2019-12-07 18:50:04,197 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 456 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=244, Invalid=2012, Unknown=0, NotChecked=0, Total=2256 [2019-12-07 18:50:04,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24605 states. [2019-12-07 18:50:04,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24605 to 20615. [2019-12-07 18:50:04,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20615 states. [2019-12-07 18:50:04,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20615 states to 20615 states and 62766 transitions. [2019-12-07 18:50:04,520 INFO L78 Accepts]: Start accepts. Automaton has 20615 states and 62766 transitions. Word has length 72 [2019-12-07 18:50:04,520 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:50:04,520 INFO L462 AbstractCegarLoop]: Abstraction has 20615 states and 62766 transitions. [2019-12-07 18:50:04,520 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 18:50:04,520 INFO L276 IsEmpty]: Start isEmpty. Operand 20615 states and 62766 transitions. [2019-12-07 18:50:04,539 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:50:04,539 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:50:04,539 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:04,539 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:50:04,539 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:04,540 INFO L82 PathProgramCache]: Analyzing trace with hash 320136691, now seen corresponding path program 13 times [2019-12-07 18:50:04,540 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:04,540 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [761346718] [2019-12-07 18:50:04,540 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:04,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:04,773 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:04,773 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [761346718] [2019-12-07 18:50:04,773 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:04,773 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 18:50:04,773 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1352539157] [2019-12-07 18:50:04,774 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 18:50:04,774 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:04,774 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 18:50:04,774 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=179, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:50:04,774 INFO L87 Difference]: Start difference. First operand 20615 states and 62766 transitions. Second operand 15 states. [2019-12-07 18:50:06,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:06,795 INFO L93 Difference]: Finished difference Result 23385 states and 70058 transitions. [2019-12-07 18:50:06,795 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 18:50:06,795 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 72 [2019-12-07 18:50:06,795 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:50:06,825 INFO L225 Difference]: With dead ends: 23385 [2019-12-07 18:50:06,825 INFO L226 Difference]: Without dead ends: 19995 [2019-12-07 18:50:06,825 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 106 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=120, Invalid=636, Unknown=0, NotChecked=0, Total=756 [2019-12-07 18:50:06,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19995 states. [2019-12-07 18:50:07,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19995 to 16880. [2019-12-07 18:50:07,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16880 states. [2019-12-07 18:50:07,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16880 states to 16880 states and 50928 transitions. [2019-12-07 18:50:07,087 INFO L78 Accepts]: Start accepts. Automaton has 16880 states and 50928 transitions. Word has length 72 [2019-12-07 18:50:07,087 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:50:07,087 INFO L462 AbstractCegarLoop]: Abstraction has 16880 states and 50928 transitions. [2019-12-07 18:50:07,087 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 18:50:07,087 INFO L276 IsEmpty]: Start isEmpty. Operand 16880 states and 50928 transitions. [2019-12-07 18:50:07,101 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:50:07,101 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:50:07,102 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:07,102 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:50:07,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:07,102 INFO L82 PathProgramCache]: Analyzing trace with hash -1848286879, now seen corresponding path program 14 times [2019-12-07 18:50:07,102 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:07,102 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1149955912] [2019-12-07 18:50:07,102 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:07,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:07,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:07,647 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1149955912] [2019-12-07 18:50:07,647 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:07,647 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 18:50:07,647 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1811361965] [2019-12-07 18:50:07,648 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 18:50:07,648 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:07,648 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 18:50:07,648 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=494, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:50:07,648 INFO L87 Difference]: Start difference. First operand 16880 states and 50928 transitions. Second operand 24 states. [2019-12-07 18:50:12,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:12,850 INFO L93 Difference]: Finished difference Result 26563 states and 79660 transitions. [2019-12-07 18:50:12,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2019-12-07 18:50:12,850 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 18:50:12,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:50:12,880 INFO L225 Difference]: With dead ends: 26563 [2019-12-07 18:50:12,880 INFO L226 Difference]: Without dead ends: 24472 [2019-12-07 18:50:12,881 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 515 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=265, Invalid=2185, Unknown=0, NotChecked=0, Total=2450 [2019-12-07 18:50:12,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24472 states. [2019-12-07 18:50:13,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24472 to 17473. [2019-12-07 18:50:13,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17473 states. [2019-12-07 18:50:13,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17473 states to 17473 states and 52777 transitions. [2019-12-07 18:50:13,162 INFO L78 Accepts]: Start accepts. Automaton has 17473 states and 52777 transitions. Word has length 72 [2019-12-07 18:50:13,162 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:50:13,162 INFO L462 AbstractCegarLoop]: Abstraction has 17473 states and 52777 transitions. [2019-12-07 18:50:13,162 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 18:50:13,162 INFO L276 IsEmpty]: Start isEmpty. Operand 17473 states and 52777 transitions. [2019-12-07 18:50:13,178 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:50:13,178 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:50:13,178 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:13,178 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:50:13,178 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:13,178 INFO L82 PathProgramCache]: Analyzing trace with hash 1360553029, now seen corresponding path program 15 times [2019-12-07 18:50:13,178 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:13,178 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [274425191] [2019-12-07 18:50:13,179 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:13,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:13,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:13,980 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [274425191] [2019-12-07 18:50:13,980 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:13,980 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2019-12-07 18:50:13,981 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [355303351] [2019-12-07 18:50:13,981 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-12-07 18:50:13,981 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:13,981 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 18:50:13,981 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=539, Unknown=0, NotChecked=0, Total=600 [2019-12-07 18:50:13,981 INFO L87 Difference]: Start difference. First operand 17473 states and 52777 transitions. Second operand 25 states. [2019-12-07 18:50:18,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:18,748 INFO L93 Difference]: Finished difference Result 24672 states and 73505 transitions. [2019-12-07 18:50:18,748 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2019-12-07 18:50:18,748 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 72 [2019-12-07 18:50:18,748 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:50:18,771 INFO L225 Difference]: With dead ends: 24672 [2019-12-07 18:50:18,771 INFO L226 Difference]: Without dead ends: 22845 [2019-12-07 18:50:18,772 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 686 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=322, Invalid=2758, Unknown=0, NotChecked=0, Total=3080 [2019-12-07 18:50:18,841 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22845 states. [2019-12-07 18:50:19,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22845 to 17323. [2019-12-07 18:50:19,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17323 states. [2019-12-07 18:50:19,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17323 states to 17323 states and 52195 transitions. [2019-12-07 18:50:19,055 INFO L78 Accepts]: Start accepts. Automaton has 17323 states and 52195 transitions. Word has length 72 [2019-12-07 18:50:19,055 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:50:19,055 INFO L462 AbstractCegarLoop]: Abstraction has 17323 states and 52195 transitions. [2019-12-07 18:50:19,056 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-12-07 18:50:19,056 INFO L276 IsEmpty]: Start isEmpty. Operand 17323 states and 52195 transitions. [2019-12-07 18:50:19,071 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:50:19,071 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:50:19,071 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:19,071 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:50:19,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:19,071 INFO L82 PathProgramCache]: Analyzing trace with hash -1335855007, now seen corresponding path program 16 times [2019-12-07 18:50:19,071 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:19,071 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248485400] [2019-12-07 18:50:19,072 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:19,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:19,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:19,612 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1248485400] [2019-12-07 18:50:19,612 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:19,612 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2019-12-07 18:50:19,613 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1066024617] [2019-12-07 18:50:19,613 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-12-07 18:50:19,613 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:19,613 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 18:50:19,613 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=542, Unknown=0, NotChecked=0, Total=600 [2019-12-07 18:50:19,613 INFO L87 Difference]: Start difference. First operand 17323 states and 52195 transitions. Second operand 25 states. [2019-12-07 18:50:25,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:25,201 INFO L93 Difference]: Finished difference Result 24526 states and 73850 transitions. [2019-12-07 18:50:25,202 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2019-12-07 18:50:25,202 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 72 [2019-12-07 18:50:25,202 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:50:25,236 INFO L225 Difference]: With dead ends: 24526 [2019-12-07 18:50:25,236 INFO L226 Difference]: Without dead ends: 21595 [2019-12-07 18:50:25,237 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 702 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=348, Invalid=2844, Unknown=0, NotChecked=0, Total=3192 [2019-12-07 18:50:25,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21595 states. [2019-12-07 18:50:25,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21595 to 17347. [2019-12-07 18:50:25,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17347 states. [2019-12-07 18:50:25,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17347 states to 17347 states and 52351 transitions. [2019-12-07 18:50:25,501 INFO L78 Accepts]: Start accepts. Automaton has 17347 states and 52351 transitions. Word has length 72 [2019-12-07 18:50:25,501 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:50:25,501 INFO L462 AbstractCegarLoop]: Abstraction has 17347 states and 52351 transitions. [2019-12-07 18:50:25,501 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-12-07 18:50:25,501 INFO L276 IsEmpty]: Start isEmpty. Operand 17347 states and 52351 transitions. [2019-12-07 18:50:25,516 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:50:25,516 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:50:25,516 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:25,516 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:50:25,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:25,517 INFO L82 PathProgramCache]: Analyzing trace with hash 982526783, now seen corresponding path program 17 times [2019-12-07 18:50:25,517 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:25,517 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769489824] [2019-12-07 18:50:25,517 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:25,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:25,681 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:25,681 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1769489824] [2019-12-07 18:50:25,681 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:25,681 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 18:50:25,681 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1524035173] [2019-12-07 18:50:25,682 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 18:50:25,682 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:25,682 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 18:50:25,682 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=130, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:50:25,682 INFO L87 Difference]: Start difference. First operand 17347 states and 52351 transitions. Second operand 13 states. [2019-12-07 18:50:27,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:27,513 INFO L93 Difference]: Finished difference Result 23390 states and 70312 transitions. [2019-12-07 18:50:27,514 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 18:50:27,514 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 72 [2019-12-07 18:50:27,514 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:50:27,536 INFO L225 Difference]: With dead ends: 23390 [2019-12-07 18:50:27,536 INFO L226 Difference]: Without dead ends: 20414 [2019-12-07 18:50:27,536 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 82 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=110, Invalid=490, Unknown=0, NotChecked=0, Total=600 [2019-12-07 18:50:27,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20414 states. [2019-12-07 18:50:27,780 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20414 to 17679. [2019-12-07 18:50:27,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17679 states. [2019-12-07 18:50:27,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17679 states to 17679 states and 53395 transitions. [2019-12-07 18:50:27,807 INFO L78 Accepts]: Start accepts. Automaton has 17679 states and 53395 transitions. Word has length 72 [2019-12-07 18:50:27,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:50:27,807 INFO L462 AbstractCegarLoop]: Abstraction has 17679 states and 53395 transitions. [2019-12-07 18:50:27,807 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 18:50:27,807 INFO L276 IsEmpty]: Start isEmpty. Operand 17679 states and 53395 transitions. [2019-12-07 18:50:27,822 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:50:27,822 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:50:27,822 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:27,822 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:50:27,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:27,823 INFO L82 PathProgramCache]: Analyzing trace with hash -970803151, now seen corresponding path program 18 times [2019-12-07 18:50:27,823 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:27,823 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1935529650] [2019-12-07 18:50:27,823 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:27,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:28,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:28,535 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1935529650] [2019-12-07 18:50:28,535 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:28,535 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [24] imperfect sequences [] total 24 [2019-12-07 18:50:28,535 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [721997532] [2019-12-07 18:50:28,535 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-12-07 18:50:28,535 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:28,535 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-12-07 18:50:28,536 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=585, Unknown=0, NotChecked=0, Total=650 [2019-12-07 18:50:28,536 INFO L87 Difference]: Start difference. First operand 17679 states and 53395 transitions. Second operand 26 states. [2019-12-07 18:50:31,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:31,670 INFO L93 Difference]: Finished difference Result 21311 states and 63718 transitions. [2019-12-07 18:50:31,670 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2019-12-07 18:50:31,670 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 72 [2019-12-07 18:50:31,670 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:50:31,690 INFO L225 Difference]: With dead ends: 21311 [2019-12-07 18:50:31,691 INFO L226 Difference]: Without dead ends: 21128 [2019-12-07 18:50:31,692 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 775 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=368, Invalid=3054, Unknown=0, NotChecked=0, Total=3422 [2019-12-07 18:50:31,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21128 states. [2019-12-07 18:50:31,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21128 to 17615. [2019-12-07 18:50:31,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17615 states. [2019-12-07 18:50:31,952 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17615 states to 17615 states and 53188 transitions. [2019-12-07 18:50:31,952 INFO L78 Accepts]: Start accepts. Automaton has 17615 states and 53188 transitions. Word has length 72 [2019-12-07 18:50:31,952 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:50:31,952 INFO L462 AbstractCegarLoop]: Abstraction has 17615 states and 53188 transitions. [2019-12-07 18:50:31,952 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-12-07 18:50:31,952 INFO L276 IsEmpty]: Start isEmpty. Operand 17615 states and 53188 transitions. [2019-12-07 18:50:31,967 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:50:31,967 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:50:31,967 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:31,967 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:50:31,968 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:31,968 INFO L82 PathProgramCache]: Analyzing trace with hash 1922350661, now seen corresponding path program 19 times [2019-12-07 18:50:31,968 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:31,968 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [324929899] [2019-12-07 18:50:31,968 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:31,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:32,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:32,273 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [324929899] [2019-12-07 18:50:32,273 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:32,273 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 18:50:32,273 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [235490624] [2019-12-07 18:50:32,273 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 18:50:32,274 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:32,274 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 18:50:32,274 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=235, Unknown=0, NotChecked=0, Total=272 [2019-12-07 18:50:32,274 INFO L87 Difference]: Start difference. First operand 17615 states and 53188 transitions. Second operand 17 states. [2019-12-07 18:50:36,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:36,627 INFO L93 Difference]: Finished difference Result 23288 states and 69712 transitions. [2019-12-07 18:50:36,627 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-12-07 18:50:36,628 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 72 [2019-12-07 18:50:36,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:50:36,660 INFO L225 Difference]: With dead ends: 23288 [2019-12-07 18:50:36,660 INFO L226 Difference]: Without dead ends: 20701 [2019-12-07 18:50:36,661 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 232 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=193, Invalid=1213, Unknown=0, NotChecked=0, Total=1406 [2019-12-07 18:50:36,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20701 states. [2019-12-07 18:50:36,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20701 to 17663. [2019-12-07 18:50:36,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17663 states. [2019-12-07 18:50:36,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17663 states to 17663 states and 53286 transitions. [2019-12-07 18:50:36,930 INFO L78 Accepts]: Start accepts. Automaton has 17663 states and 53286 transitions. Word has length 72 [2019-12-07 18:50:36,931 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:50:36,931 INFO L462 AbstractCegarLoop]: Abstraction has 17663 states and 53286 transitions. [2019-12-07 18:50:36,931 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 18:50:36,931 INFO L276 IsEmpty]: Start isEmpty. Operand 17663 states and 53286 transitions. [2019-12-07 18:50:36,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:50:36,947 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:50:36,947 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:36,947 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:50:36,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:36,947 INFO L82 PathProgramCache]: Analyzing trace with hash -636832775, now seen corresponding path program 20 times [2019-12-07 18:50:36,947 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:36,948 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574912911] [2019-12-07 18:50:36,948 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:36,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:37,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:37,838 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [574912911] [2019-12-07 18:50:37,838 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:37,838 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [26] imperfect sequences [] total 26 [2019-12-07 18:50:37,838 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [676280852] [2019-12-07 18:50:37,839 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2019-12-07 18:50:37,839 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:37,839 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2019-12-07 18:50:37,839 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=73, Invalid=683, Unknown=0, NotChecked=0, Total=756 [2019-12-07 18:50:37,839 INFO L87 Difference]: Start difference. First operand 17663 states and 53286 transitions. Second operand 28 states. [2019-12-07 18:50:41,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:41,144 INFO L93 Difference]: Finished difference Result 25815 states and 77170 transitions. [2019-12-07 18:50:41,144 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2019-12-07 18:50:41,144 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 72 [2019-12-07 18:50:41,144 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:50:41,165 INFO L225 Difference]: With dead ends: 25815 [2019-12-07 18:50:41,165 INFO L226 Difference]: Without dead ends: 21440 [2019-12-07 18:50:41,166 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 67 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 996 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=491, Invalid=3931, Unknown=0, NotChecked=0, Total=4422 [2019-12-07 18:50:41,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21440 states. [2019-12-07 18:50:41,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21440 to 17936. [2019-12-07 18:50:41,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17936 states. [2019-12-07 18:50:41,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17936 states to 17936 states and 53886 transitions. [2019-12-07 18:50:41,437 INFO L78 Accepts]: Start accepts. Automaton has 17936 states and 53886 transitions. Word has length 72 [2019-12-07 18:50:41,437 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:50:41,438 INFO L462 AbstractCegarLoop]: Abstraction has 17936 states and 53886 transitions. [2019-12-07 18:50:41,438 INFO L463 AbstractCegarLoop]: Interpolant automaton has 28 states. [2019-12-07 18:50:41,438 INFO L276 IsEmpty]: Start isEmpty. Operand 17936 states and 53886 transitions. [2019-12-07 18:50:41,453 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:50:41,453 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:50:41,453 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:41,454 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:50:41,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:41,454 INFO L82 PathProgramCache]: Analyzing trace with hash 1219459465, now seen corresponding path program 21 times [2019-12-07 18:50:41,454 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:41,454 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1547120460] [2019-12-07 18:50:41,454 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:41,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:41,764 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:41,764 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1547120460] [2019-12-07 18:50:41,765 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:41,765 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 18:50:41,765 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1151013523] [2019-12-07 18:50:41,765 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 18:50:41,765 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:41,765 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 18:50:41,766 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2019-12-07 18:50:41,766 INFO L87 Difference]: Start difference. First operand 17936 states and 53886 transitions. Second operand 17 states. [2019-12-07 18:50:43,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:43,731 INFO L93 Difference]: Finished difference Result 26275 states and 79291 transitions. [2019-12-07 18:50:43,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2019-12-07 18:50:43,732 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 72 [2019-12-07 18:50:43,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:50:43,762 INFO L225 Difference]: With dead ends: 26275 [2019-12-07 18:50:43,762 INFO L226 Difference]: Without dead ends: 25684 [2019-12-07 18:50:43,763 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 477 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=273, Invalid=1889, Unknown=0, NotChecked=0, Total=2162 [2019-12-07 18:50:43,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25684 states. [2019-12-07 18:50:44,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25684 to 21840. [2019-12-07 18:50:44,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21840 states. [2019-12-07 18:50:44,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21840 states to 21840 states and 66387 transitions. [2019-12-07 18:50:44,112 INFO L78 Accepts]: Start accepts. Automaton has 21840 states and 66387 transitions. Word has length 72 [2019-12-07 18:50:44,112 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:50:44,112 INFO L462 AbstractCegarLoop]: Abstraction has 21840 states and 66387 transitions. [2019-12-07 18:50:44,112 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 18:50:44,112 INFO L276 IsEmpty]: Start isEmpty. Operand 21840 states and 66387 transitions. [2019-12-07 18:50:44,132 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:50:44,133 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:50:44,133 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:44,133 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:50:44,133 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:44,133 INFO L82 PathProgramCache]: Analyzing trace with hash 92504751, now seen corresponding path program 22 times [2019-12-07 18:50:44,133 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:44,133 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [240512417] [2019-12-07 18:50:44,133 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:44,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:44,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:44,618 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [240512417] [2019-12-07 18:50:44,618 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:44,618 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2019-12-07 18:50:44,618 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [109895882] [2019-12-07 18:50:44,618 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-12-07 18:50:44,618 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:44,618 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 18:50:44,619 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=447, Unknown=0, NotChecked=0, Total=506 [2019-12-07 18:50:44,619 INFO L87 Difference]: Start difference. First operand 21840 states and 66387 transitions. Second operand 23 states. [2019-12-07 18:50:47,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:47,576 INFO L93 Difference]: Finished difference Result 43266 states and 132573 transitions. [2019-12-07 18:50:47,576 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2019-12-07 18:50:47,576 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 72 [2019-12-07 18:50:47,576 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:50:47,614 INFO L225 Difference]: With dead ends: 43266 [2019-12-07 18:50:47,614 INFO L226 Difference]: Without dead ends: 35714 [2019-12-07 18:50:47,616 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 725 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=338, Invalid=2632, Unknown=0, NotChecked=0, Total=2970 [2019-12-07 18:50:47,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35714 states. [2019-12-07 18:50:48,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35714 to 27594. [2019-12-07 18:50:48,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27594 states. [2019-12-07 18:50:48,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27594 states to 27594 states and 83407 transitions. [2019-12-07 18:50:48,051 INFO L78 Accepts]: Start accepts. Automaton has 27594 states and 83407 transitions. Word has length 72 [2019-12-07 18:50:48,052 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:50:48,052 INFO L462 AbstractCegarLoop]: Abstraction has 27594 states and 83407 transitions. [2019-12-07 18:50:48,052 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-12-07 18:50:48,052 INFO L276 IsEmpty]: Start isEmpty. Operand 27594 states and 83407 transitions. [2019-12-07 18:50:48,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:50:48,080 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:50:48,080 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:48,080 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:50:48,080 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:48,080 INFO L82 PathProgramCache]: Analyzing trace with hash -1539543125, now seen corresponding path program 23 times [2019-12-07 18:50:48,080 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:48,081 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [118376563] [2019-12-07 18:50:48,081 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:48,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:48,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:48,675 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [118376563] [2019-12-07 18:50:48,675 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:48,675 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2019-12-07 18:50:48,675 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2132662498] [2019-12-07 18:50:48,676 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 18:50:48,676 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:48,676 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 18:50:48,676 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=371, Unknown=0, NotChecked=0, Total=420 [2019-12-07 18:50:48,676 INFO L87 Difference]: Start difference. First operand 27594 states and 83407 transitions. Second operand 21 states. [2019-12-07 18:50:56,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:56,475 INFO L93 Difference]: Finished difference Result 33587 states and 99915 transitions. [2019-12-07 18:50:56,475 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2019-12-07 18:50:56,475 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 72 [2019-12-07 18:50:56,476 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:50:56,514 INFO L225 Difference]: With dead ends: 33587 [2019-12-07 18:50:56,514 INFO L226 Difference]: Without dead ends: 31230 [2019-12-07 18:50:56,516 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 79 GetRequests, 6 SyntacticMatches, 4 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1293 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=508, Invalid=4462, Unknown=0, NotChecked=0, Total=4970 [2019-12-07 18:50:56,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31230 states. [2019-12-07 18:50:56,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31230 to 27034. [2019-12-07 18:50:56,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27034 states. [2019-12-07 18:50:56,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27034 states to 27034 states and 81623 transitions. [2019-12-07 18:50:56,958 INFO L78 Accepts]: Start accepts. Automaton has 27034 states and 81623 transitions. Word has length 72 [2019-12-07 18:50:56,958 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:50:56,958 INFO L462 AbstractCegarLoop]: Abstraction has 27034 states and 81623 transitions. [2019-12-07 18:50:56,958 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 18:50:56,958 INFO L276 IsEmpty]: Start isEmpty. Operand 27034 states and 81623 transitions. [2019-12-07 18:50:56,986 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:50:56,986 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:50:56,986 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:56,986 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:50:56,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:56,986 INFO L82 PathProgramCache]: Analyzing trace with hash 1043294771, now seen corresponding path program 24 times [2019-12-07 18:50:56,986 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:56,986 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1843312919] [2019-12-07 18:50:56,987 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:57,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:57,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:57,346 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1843312919] [2019-12-07 18:50:57,346 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:57,346 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 18:50:57,346 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [99715136] [2019-12-07 18:50:57,346 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 18:50:57,346 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:57,346 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 18:50:57,347 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=235, Unknown=0, NotChecked=0, Total=272 [2019-12-07 18:50:57,347 INFO L87 Difference]: Start difference. First operand 27034 states and 81623 transitions. Second operand 17 states. [2019-12-07 18:50:59,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:59,541 INFO L93 Difference]: Finished difference Result 32479 states and 96905 transitions. [2019-12-07 18:50:59,541 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-12-07 18:50:59,542 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 72 [2019-12-07 18:50:59,542 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:50:59,578 INFO L225 Difference]: With dead ends: 32479 [2019-12-07 18:50:59,578 INFO L226 Difference]: Without dead ends: 28382 [2019-12-07 18:50:59,579 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 389 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=262, Invalid=1630, Unknown=0, NotChecked=0, Total=1892 [2019-12-07 18:50:59,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28382 states. [2019-12-07 18:50:59,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28382 to 22601. [2019-12-07 18:50:59,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22601 states. [2019-12-07 18:50:59,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22601 states to 22601 states and 67227 transitions. [2019-12-07 18:50:59,938 INFO L78 Accepts]: Start accepts. Automaton has 22601 states and 67227 transitions. Word has length 72 [2019-12-07 18:50:59,938 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:50:59,938 INFO L462 AbstractCegarLoop]: Abstraction has 22601 states and 67227 transitions. [2019-12-07 18:50:59,939 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 18:50:59,939 INFO L276 IsEmpty]: Start isEmpty. Operand 22601 states and 67227 transitions. [2019-12-07 18:50:59,960 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:50:59,960 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:50:59,960 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:59,960 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:50:59,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:59,960 INFO L82 PathProgramCache]: Analyzing trace with hash 870577009, now seen corresponding path program 25 times [2019-12-07 18:50:59,960 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:59,960 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [559307365] [2019-12-07 18:50:59,961 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:59,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:51:00,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:51:00,255 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [559307365] [2019-12-07 18:51:00,255 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:51:00,255 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 18:51:00,255 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1480511846] [2019-12-07 18:51:00,255 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 18:51:00,255 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:51:00,255 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 18:51:00,255 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=267, Unknown=0, NotChecked=0, Total=306 [2019-12-07 18:51:00,256 INFO L87 Difference]: Start difference. First operand 22601 states and 67227 transitions. Second operand 18 states. [2019-12-07 18:51:04,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:51:04,020 INFO L93 Difference]: Finished difference Result 27695 states and 82004 transitions. [2019-12-07 18:51:04,020 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2019-12-07 18:51:04,020 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 72 [2019-12-07 18:51:04,021 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:51:04,063 INFO L225 Difference]: With dead ends: 27695 [2019-12-07 18:51:04,063 INFO L226 Difference]: Without dead ends: 27491 [2019-12-07 18:51:04,064 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 364 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=237, Invalid=1569, Unknown=0, NotChecked=0, Total=1806 [2019-12-07 18:51:04,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27491 states. [2019-12-07 18:51:04,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27491 to 24688. [2019-12-07 18:51:04,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24688 states. [2019-12-07 18:51:04,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24688 states to 24688 states and 73871 transitions. [2019-12-07 18:51:04,439 INFO L78 Accepts]: Start accepts. Automaton has 24688 states and 73871 transitions. Word has length 72 [2019-12-07 18:51:04,439 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:51:04,439 INFO L462 AbstractCegarLoop]: Abstraction has 24688 states and 73871 transitions. [2019-12-07 18:51:04,439 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 18:51:04,439 INFO L276 IsEmpty]: Start isEmpty. Operand 24688 states and 73871 transitions. [2019-12-07 18:51:04,465 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:51:04,465 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:51:04,465 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:51:04,465 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:51:04,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:51:04,465 INFO L82 PathProgramCache]: Analyzing trace with hash 899660859, now seen corresponding path program 26 times [2019-12-07 18:51:04,465 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:51:04,466 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [179780665] [2019-12-07 18:51:04,466 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:51:04,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:51:04,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:51:04,804 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [179780665] [2019-12-07 18:51:04,804 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:51:04,804 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 18:51:04,804 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2016463320] [2019-12-07 18:51:04,804 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 18:51:04,804 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:51:04,805 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 18:51:04,805 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=266, Unknown=0, NotChecked=0, Total=306 [2019-12-07 18:51:04,805 INFO L87 Difference]: Start difference. First operand 24688 states and 73871 transitions. Second operand 18 states. [2019-12-07 18:51:08,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:51:08,669 INFO L93 Difference]: Finished difference Result 28034 states and 82553 transitions. [2019-12-07 18:51:08,669 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-12-07 18:51:08,669 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 72 [2019-12-07 18:51:08,669 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:51:08,697 INFO L225 Difference]: With dead ends: 28034 [2019-12-07 18:51:08,698 INFO L226 Difference]: Without dead ends: 24748 [2019-12-07 18:51:08,698 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 368 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=256, Invalid=1636, Unknown=0, NotChecked=0, Total=1892 [2019-12-07 18:51:08,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24748 states. [2019-12-07 18:51:08,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24748 to 21230. [2019-12-07 18:51:08,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21230 states. [2019-12-07 18:51:09,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21230 states to 21230 states and 63306 transitions. [2019-12-07 18:51:09,003 INFO L78 Accepts]: Start accepts. Automaton has 21230 states and 63306 transitions. Word has length 72 [2019-12-07 18:51:09,003 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:51:09,003 INFO L462 AbstractCegarLoop]: Abstraction has 21230 states and 63306 transitions. [2019-12-07 18:51:09,003 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 18:51:09,003 INFO L276 IsEmpty]: Start isEmpty. Operand 21230 states and 63306 transitions. [2019-12-07 18:51:09,021 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:51:09,021 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:51:09,021 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:51:09,021 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:51:09,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:51:09,021 INFO L82 PathProgramCache]: Analyzing trace with hash 93100351, now seen corresponding path program 27 times [2019-12-07 18:51:09,021 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:51:09,022 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [24100297] [2019-12-07 18:51:09,022 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:51:09,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:51:11,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:51:11,207 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [24100297] [2019-12-07 18:51:11,208 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:51:11,208 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [28] imperfect sequences [] total 28 [2019-12-07 18:51:11,208 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1384643271] [2019-12-07 18:51:11,208 INFO L442 AbstractCegarLoop]: Interpolant automaton has 30 states [2019-12-07 18:51:11,208 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:51:11,208 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2019-12-07 18:51:11,208 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=786, Unknown=0, NotChecked=0, Total=870 [2019-12-07 18:51:11,208 INFO L87 Difference]: Start difference. First operand 21230 states and 63306 transitions. Second operand 30 states. [2019-12-07 18:51:21,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:51:21,995 INFO L93 Difference]: Finished difference Result 28362 states and 82802 transitions. [2019-12-07 18:51:21,996 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2019-12-07 18:51:21,996 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 72 [2019-12-07 18:51:21,996 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:51:22,027 INFO L225 Difference]: With dead ends: 28362 [2019-12-07 18:51:22,028 INFO L226 Difference]: Without dead ends: 28250 [2019-12-07 18:51:22,028 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 4 SyntacticMatches, 5 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1172 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=404, Invalid=4566, Unknown=0, NotChecked=0, Total=4970 [2019-12-07 18:51:22,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28250 states. [2019-12-07 18:51:22,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28250 to 24854. [2019-12-07 18:51:22,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24854 states. [2019-12-07 18:51:22,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24854 states to 24854 states and 73222 transitions. [2019-12-07 18:51:22,437 INFO L78 Accepts]: Start accepts. Automaton has 24854 states and 73222 transitions. Word has length 72 [2019-12-07 18:51:22,437 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:51:22,437 INFO L462 AbstractCegarLoop]: Abstraction has 24854 states and 73222 transitions. [2019-12-07 18:51:22,437 INFO L463 AbstractCegarLoop]: Interpolant automaton has 30 states. [2019-12-07 18:51:22,437 INFO L276 IsEmpty]: Start isEmpty. Operand 24854 states and 73222 transitions. [2019-12-07 18:51:22,462 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:51:22,462 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:51:22,462 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:51:22,463 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:51:22,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:51:22,463 INFO L82 PathProgramCache]: Analyzing trace with hash -2081313235, now seen corresponding path program 28 times [2019-12-07 18:51:22,463 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:51:22,463 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1139363188] [2019-12-07 18:51:22,463 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:51:22,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:51:22,958 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:51:22,958 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1139363188] [2019-12-07 18:51:22,959 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:51:22,959 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2019-12-07 18:51:22,959 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [692631751] [2019-12-07 18:51:22,959 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-12-07 18:51:22,959 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:51:22,959 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 18:51:22,959 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=441, Unknown=0, NotChecked=0, Total=506 [2019-12-07 18:51:22,959 INFO L87 Difference]: Start difference. First operand 24854 states and 73222 transitions. Second operand 23 states. [2019-12-07 18:51:27,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:51:27,836 INFO L93 Difference]: Finished difference Result 38930 states and 114264 transitions. [2019-12-07 18:51:27,836 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2019-12-07 18:51:27,837 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 72 [2019-12-07 18:51:27,837 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:51:27,891 INFO L225 Difference]: With dead ends: 38930 [2019-12-07 18:51:27,892 INFO L226 Difference]: Without dead ends: 38586 [2019-12-07 18:51:27,892 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 591 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=331, Invalid=2321, Unknown=0, NotChecked=0, Total=2652 [2019-12-07 18:51:27,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38586 states. [2019-12-07 18:51:28,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38586 to 29143. [2019-12-07 18:51:28,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29143 states. [2019-12-07 18:51:28,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29143 states to 29143 states and 86636 transitions. [2019-12-07 18:51:28,434 INFO L78 Accepts]: Start accepts. Automaton has 29143 states and 86636 transitions. Word has length 72 [2019-12-07 18:51:28,434 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:51:28,434 INFO L462 AbstractCegarLoop]: Abstraction has 29143 states and 86636 transitions. [2019-12-07 18:51:28,434 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-12-07 18:51:28,434 INFO L276 IsEmpty]: Start isEmpty. Operand 29143 states and 86636 transitions. [2019-12-07 18:51:28,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:51:28,463 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:51:28,463 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:51:28,463 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:51:28,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:51:28,463 INFO L82 PathProgramCache]: Analyzing trace with hash 1855651213, now seen corresponding path program 29 times [2019-12-07 18:51:28,463 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:51:28,463 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [672044836] [2019-12-07 18:51:28,463 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:51:28,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:51:29,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:51:29,104 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [672044836] [2019-12-07 18:51:29,105 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:51:29,105 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2019-12-07 18:51:29,105 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [130040758] [2019-12-07 18:51:29,105 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-12-07 18:51:29,105 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:51:29,105 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 18:51:29,105 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=537, Unknown=0, NotChecked=0, Total=600 [2019-12-07 18:51:29,105 INFO L87 Difference]: Start difference. First operand 29143 states and 86636 transitions. Second operand 25 states. [2019-12-07 18:51:37,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:51:37,006 INFO L93 Difference]: Finished difference Result 35584 states and 104992 transitions. [2019-12-07 18:51:37,007 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2019-12-07 18:51:37,007 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 72 [2019-12-07 18:51:37,007 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:51:37,055 INFO L225 Difference]: With dead ends: 35584 [2019-12-07 18:51:37,055 INFO L226 Difference]: Without dead ends: 35016 [2019-12-07 18:51:37,055 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 6 SyntacticMatches, 3 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 719 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=319, Invalid=2761, Unknown=0, NotChecked=0, Total=3080 [2019-12-07 18:51:37,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35016 states. [2019-12-07 18:51:37,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35016 to 29734. [2019-12-07 18:51:37,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29734 states. [2019-12-07 18:51:37,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29734 states to 29734 states and 88660 transitions. [2019-12-07 18:51:37,510 INFO L78 Accepts]: Start accepts. Automaton has 29734 states and 88660 transitions. Word has length 72 [2019-12-07 18:51:37,510 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:51:37,511 INFO L462 AbstractCegarLoop]: Abstraction has 29734 states and 88660 transitions. [2019-12-07 18:51:37,511 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-12-07 18:51:37,511 INFO L276 IsEmpty]: Start isEmpty. Operand 29734 states and 88660 transitions. [2019-12-07 18:51:37,540 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:51:37,540 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:51:37,540 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:51:37,540 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:51:37,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:51:37,541 INFO L82 PathProgramCache]: Analyzing trace with hash -1848861415, now seen corresponding path program 30 times [2019-12-07 18:51:37,541 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:51:37,541 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1763693450] [2019-12-07 18:51:37,541 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:51:37,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:51:37,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:51:37,752 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1763693450] [2019-12-07 18:51:37,752 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:51:37,752 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 18:51:37,753 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1932287633] [2019-12-07 18:51:37,753 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 18:51:37,753 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:51:37,753 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 18:51:37,753 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=153, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:51:37,753 INFO L87 Difference]: Start difference. First operand 29734 states and 88660 transitions. Second operand 14 states. [2019-12-07 18:51:38,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:51:38,960 INFO L93 Difference]: Finished difference Result 43920 states and 130567 transitions. [2019-12-07 18:51:38,960 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-12-07 18:51:38,960 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 72 [2019-12-07 18:51:38,960 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:51:39,010 INFO L225 Difference]: With dead ends: 43920 [2019-12-07 18:51:39,011 INFO L226 Difference]: Without dead ends: 42298 [2019-12-07 18:51:39,011 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 220 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=161, Invalid=961, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 18:51:39,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42298 states. [2019-12-07 18:51:39,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42298 to 31919. [2019-12-07 18:51:39,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31919 states. [2019-12-07 18:51:39,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31919 states to 31919 states and 95284 transitions. [2019-12-07 18:51:39,539 INFO L78 Accepts]: Start accepts. Automaton has 31919 states and 95284 transitions. Word has length 72 [2019-12-07 18:51:39,539 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:51:39,540 INFO L462 AbstractCegarLoop]: Abstraction has 31919 states and 95284 transitions. [2019-12-07 18:51:39,540 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 18:51:39,540 INFO L276 IsEmpty]: Start isEmpty. Operand 31919 states and 95284 transitions. [2019-12-07 18:51:39,570 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:51:39,570 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:51:39,570 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:51:39,570 INFO L410 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:51:39,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:51:39,570 INFO L82 PathProgramCache]: Analyzing trace with hash -1033854363, now seen corresponding path program 31 times [2019-12-07 18:51:39,570 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:51:39,570 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [148875091] [2019-12-07 18:51:39,570 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:51:39,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:51:39,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:51:39,874 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [148875091] [2019-12-07 18:51:39,874 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:51:39,874 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2019-12-07 18:51:39,874 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [671882385] [2019-12-07 18:51:39,874 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 18:51:39,875 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:51:39,875 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 18:51:39,875 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=295, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:51:39,875 INFO L87 Difference]: Start difference. First operand 31919 states and 95284 transitions. Second operand 19 states. [2019-12-07 18:51:41,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:51:41,656 INFO L93 Difference]: Finished difference Result 39219 states and 116066 transitions. [2019-12-07 18:51:41,657 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2019-12-07 18:51:41,657 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 72 [2019-12-07 18:51:41,657 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:51:41,710 INFO L225 Difference]: With dead ends: 39219 [2019-12-07 18:51:41,710 INFO L226 Difference]: Without dead ends: 36742 [2019-12-07 18:51:41,711 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 340 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=204, Invalid=1436, Unknown=0, NotChecked=0, Total=1640 [2019-12-07 18:51:41,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36742 states. [2019-12-07 18:51:42,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36742 to 32728. [2019-12-07 18:51:42,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32728 states. [2019-12-07 18:51:42,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32728 states to 32728 states and 97758 transitions. [2019-12-07 18:51:42,290 INFO L78 Accepts]: Start accepts. Automaton has 32728 states and 97758 transitions. Word has length 72 [2019-12-07 18:51:42,290 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:51:42,290 INFO L462 AbstractCegarLoop]: Abstraction has 32728 states and 97758 transitions. [2019-12-07 18:51:42,290 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 18:51:42,290 INFO L276 IsEmpty]: Start isEmpty. Operand 32728 states and 97758 transitions. [2019-12-07 18:51:42,318 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:51:42,318 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:51:42,318 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:51:42,318 INFO L410 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:51:42,318 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:51:42,318 INFO L82 PathProgramCache]: Analyzing trace with hash -156257871, now seen corresponding path program 32 times [2019-12-07 18:51:42,318 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:51:42,319 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [783767220] [2019-12-07 18:51:42,319 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:51:42,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:51:42,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:51:42,599 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [783767220] [2019-12-07 18:51:42,600 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:51:42,600 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 18:51:42,600 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [207757298] [2019-12-07 18:51:42,600 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 18:51:42,600 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:51:42,600 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 18:51:42,600 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=267, Unknown=0, NotChecked=0, Total=306 [2019-12-07 18:51:42,600 INFO L87 Difference]: Start difference. First operand 32728 states and 97758 transitions. Second operand 18 states. [2019-12-07 18:51:46,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:51:46,159 INFO L93 Difference]: Finished difference Result 36311 states and 107447 transitions. [2019-12-07 18:51:46,159 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2019-12-07 18:51:46,159 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 72 [2019-12-07 18:51:46,159 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:51:46,202 INFO L225 Difference]: With dead ends: 36311 [2019-12-07 18:51:46,202 INFO L226 Difference]: Without dead ends: 36275 [2019-12-07 18:51:46,202 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 345 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=220, Invalid=1502, Unknown=0, NotChecked=0, Total=1722 [2019-12-07 18:51:46,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36275 states. [2019-12-07 18:51:46,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36275 to 32523. [2019-12-07 18:51:46,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32523 states. [2019-12-07 18:51:46,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32523 states to 32523 states and 97184 transitions. [2019-12-07 18:51:46,709 INFO L78 Accepts]: Start accepts. Automaton has 32523 states and 97184 transitions. Word has length 72 [2019-12-07 18:51:46,710 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:51:46,710 INFO L462 AbstractCegarLoop]: Abstraction has 32523 states and 97184 transitions. [2019-12-07 18:51:46,710 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 18:51:46,710 INFO L276 IsEmpty]: Start isEmpty. Operand 32523 states and 97184 transitions. [2019-12-07 18:51:46,741 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:51:46,741 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:51:46,741 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:51:46,741 INFO L410 AbstractCegarLoop]: === Iteration 40 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:51:46,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:51:46,741 INFO L82 PathProgramCache]: Analyzing trace with hash -1283212585, now seen corresponding path program 33 times [2019-12-07 18:51:46,741 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:51:46,742 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [903156657] [2019-12-07 18:51:46,742 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:51:46,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:51:47,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:51:47,228 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [903156657] [2019-12-07 18:51:47,228 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:51:47,228 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 18:51:47,228 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [352164035] [2019-12-07 18:51:47,228 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 18:51:47,228 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:51:47,229 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 18:51:47,229 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=490, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:51:47,229 INFO L87 Difference]: Start difference. First operand 32523 states and 97184 transitions. Second operand 24 states. [2019-12-07 18:51:50,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:51:50,613 INFO L93 Difference]: Finished difference Result 58235 states and 174563 transitions. [2019-12-07 18:51:50,613 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2019-12-07 18:51:50,613 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 18:51:50,613 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:51:50,672 INFO L225 Difference]: With dead ends: 58235 [2019-12-07 18:51:50,672 INFO L226 Difference]: Without dead ends: 49170 [2019-12-07 18:51:50,672 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1232 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=531, Invalid=4025, Unknown=0, NotChecked=0, Total=4556 [2019-12-07 18:51:50,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49170 states. [2019-12-07 18:51:51,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49170 to 36906. [2019-12-07 18:51:51,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36906 states. [2019-12-07 18:51:51,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36906 states to 36906 states and 109853 transitions. [2019-12-07 18:51:51,317 INFO L78 Accepts]: Start accepts. Automaton has 36906 states and 109853 transitions. Word has length 72 [2019-12-07 18:51:51,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:51:51,317 INFO L462 AbstractCegarLoop]: Abstraction has 36906 states and 109853 transitions. [2019-12-07 18:51:51,317 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 18:51:51,317 INFO L276 IsEmpty]: Start isEmpty. Operand 36906 states and 109853 transitions. [2019-12-07 18:51:51,351 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:51:51,351 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:51:51,351 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:51:51,351 INFO L410 AbstractCegarLoop]: === Iteration 41 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:51:51,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:51:51,352 INFO L82 PathProgramCache]: Analyzing trace with hash -1389596133, now seen corresponding path program 34 times [2019-12-07 18:51:51,352 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:51:51,352 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [75571386] [2019-12-07 18:51:51,352 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:51:51,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:51:51,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:51:51,836 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [75571386] [2019-12-07 18:51:51,836 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:51:51,837 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 18:51:51,837 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1653468400] [2019-12-07 18:51:51,837 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 18:51:51,837 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:51:51,837 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 18:51:51,837 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=490, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:51:51,837 INFO L87 Difference]: Start difference. First operand 36906 states and 109853 transitions. Second operand 24 states. [2019-12-07 18:51:56,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:51:56,239 INFO L93 Difference]: Finished difference Result 52287 states and 153971 transitions. [2019-12-07 18:51:56,240 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2019-12-07 18:51:56,240 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 18:51:56,240 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:51:56,295 INFO L225 Difference]: With dead ends: 52287 [2019-12-07 18:51:56,295 INFO L226 Difference]: Without dead ends: 44900 [2019-12-07 18:51:56,295 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 775 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=367, Invalid=2825, Unknown=0, NotChecked=0, Total=3192 [2019-12-07 18:51:56,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44900 states. [2019-12-07 18:51:56,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44900 to 33051. [2019-12-07 18:51:56,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33051 states. [2019-12-07 18:51:56,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33051 states to 33051 states and 98176 transitions. [2019-12-07 18:51:56,850 INFO L78 Accepts]: Start accepts. Automaton has 33051 states and 98176 transitions. Word has length 72 [2019-12-07 18:51:56,850 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:51:56,850 INFO L462 AbstractCegarLoop]: Abstraction has 33051 states and 98176 transitions. [2019-12-07 18:51:56,850 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 18:51:56,850 INFO L276 IsEmpty]: Start isEmpty. Operand 33051 states and 98176 transitions. [2019-12-07 18:51:56,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:51:56,882 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:51:56,882 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:51:56,882 INFO L410 AbstractCegarLoop]: === Iteration 42 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:51:56,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:51:56,882 INFO L82 PathProgramCache]: Analyzing trace with hash -1903740133, now seen corresponding path program 35 times [2019-12-07 18:51:56,883 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:51:56,883 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1269430231] [2019-12-07 18:51:56,883 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:51:56,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:51:57,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:51:57,092 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1269430231] [2019-12-07 18:51:57,092 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:51:57,092 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 18:51:57,092 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [740669494] [2019-12-07 18:51:57,093 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 18:51:57,093 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:51:57,093 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 18:51:57,093 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:51:57,093 INFO L87 Difference]: Start difference. First operand 33051 states and 98176 transitions. Second operand 16 states. [2019-12-07 18:51:58,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:51:58,571 INFO L93 Difference]: Finished difference Result 36950 states and 109034 transitions. [2019-12-07 18:51:58,571 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2019-12-07 18:51:58,571 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2019-12-07 18:51:58,571 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:51:58,611 INFO L225 Difference]: With dead ends: 36950 [2019-12-07 18:51:58,611 INFO L226 Difference]: Without dead ends: 35650 [2019-12-07 18:51:58,611 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 228 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=159, Invalid=1031, Unknown=0, NotChecked=0, Total=1190 [2019-12-07 18:51:58,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35650 states. [2019-12-07 18:51:59,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35650 to 31903. [2019-12-07 18:51:59,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31903 states. [2019-12-07 18:51:59,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31903 states to 31903 states and 94816 transitions. [2019-12-07 18:51:59,145 INFO L78 Accepts]: Start accepts. Automaton has 31903 states and 94816 transitions. Word has length 72 [2019-12-07 18:51:59,145 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:51:59,145 INFO L462 AbstractCegarLoop]: Abstraction has 31903 states and 94816 transitions. [2019-12-07 18:51:59,145 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 18:51:59,145 INFO L276 IsEmpty]: Start isEmpty. Operand 31903 states and 94816 transitions. [2019-12-07 18:51:59,171 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:51:59,171 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:51:59,171 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:51:59,172 INFO L410 AbstractCegarLoop]: === Iteration 43 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:51:59,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:51:59,172 INFO L82 PathProgramCache]: Analyzing trace with hash -2123960637, now seen corresponding path program 36 times [2019-12-07 18:51:59,172 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:51:59,172 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806148446] [2019-12-07 18:51:59,172 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:51:59,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:00,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:00,059 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1806148446] [2019-12-07 18:52:00,059 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:00,059 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [25] imperfect sequences [] total 25 [2019-12-07 18:52:00,059 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [53313274] [2019-12-07 18:52:00,059 INFO L442 AbstractCegarLoop]: Interpolant automaton has 27 states [2019-12-07 18:52:00,059 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:00,059 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2019-12-07 18:52:00,060 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=70, Invalid=632, Unknown=0, NotChecked=0, Total=702 [2019-12-07 18:52:00,060 INFO L87 Difference]: Start difference. First operand 31903 states and 94816 transitions. Second operand 27 states. [2019-12-07 18:52:07,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:07,166 INFO L93 Difference]: Finished difference Result 41744 states and 122425 transitions. [2019-12-07 18:52:07,166 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2019-12-07 18:52:07,166 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 72 [2019-12-07 18:52:07,166 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:07,222 INFO L225 Difference]: With dead ends: 41744 [2019-12-07 18:52:07,223 INFO L226 Difference]: Without dead ends: 40249 [2019-12-07 18:52:07,223 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 81 GetRequests, 3 SyntacticMatches, 4 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1477 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=563, Invalid=5137, Unknown=0, NotChecked=0, Total=5700 [2019-12-07 18:52:07,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40249 states. [2019-12-07 18:52:07,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40249 to 32362. [2019-12-07 18:52:07,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32362 states. [2019-12-07 18:52:07,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32362 states to 32362 states and 96004 transitions. [2019-12-07 18:52:07,729 INFO L78 Accepts]: Start accepts. Automaton has 32362 states and 96004 transitions. Word has length 72 [2019-12-07 18:52:07,729 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:07,729 INFO L462 AbstractCegarLoop]: Abstraction has 32362 states and 96004 transitions. [2019-12-07 18:52:07,729 INFO L463 AbstractCegarLoop]: Interpolant automaton has 27 states. [2019-12-07 18:52:07,729 INFO L276 IsEmpty]: Start isEmpty. Operand 32362 states and 96004 transitions. [2019-12-07 18:52:07,760 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:52:07,761 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:07,761 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:07,761 INFO L410 AbstractCegarLoop]: === Iteration 44 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:07,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:07,761 INFO L82 PathProgramCache]: Analyzing trace with hash 1859153277, now seen corresponding path program 37 times [2019-12-07 18:52:07,761 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:07,761 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1567996762] [2019-12-07 18:52:07,761 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:07,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:08,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:08,149 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1567996762] [2019-12-07 18:52:08,149 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:08,149 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2019-12-07 18:52:08,150 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [766923033] [2019-12-07 18:52:08,150 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 18:52:08,150 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:08,150 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 18:52:08,150 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=301, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:52:08,150 INFO L87 Difference]: Start difference. First operand 32362 states and 96004 transitions. Second operand 19 states. [2019-12-07 18:52:11,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:11,022 INFO L93 Difference]: Finished difference Result 34985 states and 102953 transitions. [2019-12-07 18:52:11,022 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2019-12-07 18:52:11,022 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 72 [2019-12-07 18:52:11,022 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:11,061 INFO L225 Difference]: With dead ends: 34985 [2019-12-07 18:52:11,061 INFO L226 Difference]: Without dead ends: 34949 [2019-12-07 18:52:11,061 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 520 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=287, Invalid=2163, Unknown=0, NotChecked=0, Total=2450 [2019-12-07 18:52:11,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34949 states. [2019-12-07 18:52:11,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34949 to 32727. [2019-12-07 18:52:11,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32727 states. [2019-12-07 18:52:11,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32727 states to 32727 states and 96867 transitions. [2019-12-07 18:52:11,521 INFO L78 Accepts]: Start accepts. Automaton has 32727 states and 96867 transitions. Word has length 72 [2019-12-07 18:52:11,521 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:11,521 INFO L462 AbstractCegarLoop]: Abstraction has 32727 states and 96867 transitions. [2019-12-07 18:52:11,521 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 18:52:11,521 INFO L276 IsEmpty]: Start isEmpty. Operand 32727 states and 96867 transitions. [2019-12-07 18:52:11,553 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:52:11,553 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:11,553 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:11,553 INFO L410 AbstractCegarLoop]: === Iteration 45 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:11,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:11,553 INFO L82 PathProgramCache]: Analyzing trace with hash 1888237127, now seen corresponding path program 38 times [2019-12-07 18:52:11,553 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:11,553 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [615590516] [2019-12-07 18:52:11,553 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:11,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:12,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:12,050 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [615590516] [2019-12-07 18:52:12,050 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:12,050 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 18:52:12,050 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [684014838] [2019-12-07 18:52:12,050 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 18:52:12,050 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:12,051 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 18:52:12,051 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=490, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:52:12,051 INFO L87 Difference]: Start difference. First operand 32727 states and 96867 transitions. Second operand 24 states. [2019-12-07 18:52:15,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:15,103 INFO L93 Difference]: Finished difference Result 43004 states and 125928 transitions. [2019-12-07 18:52:15,103 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2019-12-07 18:52:15,103 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 18:52:15,103 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:15,147 INFO L225 Difference]: With dead ends: 43004 [2019-12-07 18:52:15,147 INFO L226 Difference]: Without dead ends: 38073 [2019-12-07 18:52:15,147 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1182 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=525, Invalid=3897, Unknown=0, NotChecked=0, Total=4422 [2019-12-07 18:52:15,248 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38073 states. [2019-12-07 18:52:15,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38073 to 30077. [2019-12-07 18:52:15,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30077 states. [2019-12-07 18:52:15,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30077 states to 30077 states and 89125 transitions. [2019-12-07 18:52:15,648 INFO L78 Accepts]: Start accepts. Automaton has 30077 states and 89125 transitions. Word has length 72 [2019-12-07 18:52:15,648 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:15,649 INFO L462 AbstractCegarLoop]: Abstraction has 30077 states and 89125 transitions. [2019-12-07 18:52:15,649 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 18:52:15,649 INFO L276 IsEmpty]: Start isEmpty. Operand 30077 states and 89125 transitions. [2019-12-07 18:52:15,678 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:52:15,678 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:15,678 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:15,678 INFO L410 AbstractCegarLoop]: === Iteration 46 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:15,679 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:15,679 INFO L82 PathProgramCache]: Analyzing trace with hash 1288193291, now seen corresponding path program 39 times [2019-12-07 18:52:15,679 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:15,679 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876495268] [2019-12-07 18:52:15,679 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:15,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:16,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:16,098 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1876495268] [2019-12-07 18:52:16,098 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:16,098 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2019-12-07 18:52:16,099 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1692911660] [2019-12-07 18:52:16,099 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-12-07 18:52:16,099 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:16,099 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 18:52:16,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=448, Unknown=0, NotChecked=0, Total=506 [2019-12-07 18:52:16,099 INFO L87 Difference]: Start difference. First operand 30077 states and 89125 transitions. Second operand 23 states. [2019-12-07 18:52:18,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:18,865 INFO L93 Difference]: Finished difference Result 41280 states and 121010 transitions. [2019-12-07 18:52:18,865 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2019-12-07 18:52:18,865 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 72 [2019-12-07 18:52:18,865 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:18,905 INFO L225 Difference]: With dead ends: 41280 [2019-12-07 18:52:18,905 INFO L226 Difference]: Without dead ends: 38099 [2019-12-07 18:52:18,905 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 684 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=321, Invalid=2541, Unknown=0, NotChecked=0, Total=2862 [2019-12-07 18:52:19,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38099 states. [2019-12-07 18:52:19,328 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38099 to 29872. [2019-12-07 18:52:19,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29872 states. [2019-12-07 18:52:19,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29872 states to 29872 states and 88536 transitions. [2019-12-07 18:52:19,378 INFO L78 Accepts]: Start accepts. Automaton has 29872 states and 88536 transitions. Word has length 72 [2019-12-07 18:52:19,378 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:19,378 INFO L462 AbstractCegarLoop]: Abstraction has 29872 states and 88536 transitions. [2019-12-07 18:52:19,378 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-12-07 18:52:19,378 INFO L276 IsEmpty]: Start isEmpty. Operand 29872 states and 88536 transitions. [2019-12-07 18:52:19,408 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:52:19,408 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:19,408 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:19,408 INFO L410 AbstractCegarLoop]: === Iteration 47 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:19,408 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:19,408 INFO L82 PathProgramCache]: Analyzing trace with hash -1270990145, now seen corresponding path program 40 times [2019-12-07 18:52:19,409 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:19,409 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1222987905] [2019-12-07 18:52:19,409 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:19,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:20,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:20,306 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1222987905] [2019-12-07 18:52:20,306 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:20,306 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [25] imperfect sequences [] total 25 [2019-12-07 18:52:20,306 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1000199684] [2019-12-07 18:52:20,306 INFO L442 AbstractCegarLoop]: Interpolant automaton has 27 states [2019-12-07 18:52:20,306 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:20,307 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2019-12-07 18:52:20,307 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=628, Unknown=0, NotChecked=0, Total=702 [2019-12-07 18:52:20,307 INFO L87 Difference]: Start difference. First operand 29872 states and 88536 transitions. Second operand 27 states. [2019-12-07 18:52:27,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:27,114 INFO L93 Difference]: Finished difference Result 39425 states and 116239 transitions. [2019-12-07 18:52:27,114 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2019-12-07 18:52:27,114 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 72 [2019-12-07 18:52:27,114 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:27,158 INFO L225 Difference]: With dead ends: 39425 [2019-12-07 18:52:27,158 INFO L226 Difference]: Without dead ends: 38118 [2019-12-07 18:52:27,158 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1423 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=615, Invalid=4935, Unknown=0, NotChecked=0, Total=5550 [2019-12-07 18:52:27,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38118 states. [2019-12-07 18:52:27,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38118 to 31124. [2019-12-07 18:52:27,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31124 states. [2019-12-07 18:52:27,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31124 states to 31124 states and 92251 transitions. [2019-12-07 18:52:27,654 INFO L78 Accepts]: Start accepts. Automaton has 31124 states and 92251 transitions. Word has length 72 [2019-12-07 18:52:27,654 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:27,654 INFO L462 AbstractCegarLoop]: Abstraction has 31124 states and 92251 transitions. [2019-12-07 18:52:27,654 INFO L463 AbstractCegarLoop]: Interpolant automaton has 27 states. [2019-12-07 18:52:27,654 INFO L276 IsEmpty]: Start isEmpty. Operand 31124 states and 92251 transitions. [2019-12-07 18:52:27,685 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:52:27,685 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:27,685 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:27,685 INFO L410 AbstractCegarLoop]: === Iteration 48 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:27,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:27,685 INFO L82 PathProgramCache]: Analyzing trace with hash 1137499281, now seen corresponding path program 41 times [2019-12-07 18:52:27,685 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:27,685 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [697052856] [2019-12-07 18:52:27,685 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:27,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:28,078 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:28,078 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [697052856] [2019-12-07 18:52:28,079 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:28,079 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2019-12-07 18:52:28,079 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1779980715] [2019-12-07 18:52:28,079 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 18:52:28,079 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:28,079 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 18:52:28,079 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=300, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:52:28,079 INFO L87 Difference]: Start difference. First operand 31124 states and 92251 transitions. Second operand 19 states. [2019-12-07 18:52:30,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:30,278 INFO L93 Difference]: Finished difference Result 33572 states and 98716 transitions. [2019-12-07 18:52:30,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2019-12-07 18:52:30,278 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 72 [2019-12-07 18:52:30,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:30,316 INFO L225 Difference]: With dead ends: 33572 [2019-12-07 18:52:30,316 INFO L226 Difference]: Without dead ends: 33524 [2019-12-07 18:52:30,317 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 553 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=308, Invalid=2242, Unknown=0, NotChecked=0, Total=2550 [2019-12-07 18:52:30,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33524 states. [2019-12-07 18:52:30,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33524 to 31130. [2019-12-07 18:52:30,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31130 states. [2019-12-07 18:52:30,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31130 states to 31130 states and 92263 transitions. [2019-12-07 18:52:30,779 INFO L78 Accepts]: Start accepts. Automaton has 31130 states and 92263 transitions. Word has length 72 [2019-12-07 18:52:30,779 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:30,779 INFO L462 AbstractCegarLoop]: Abstraction has 31130 states and 92263 transitions. [2019-12-07 18:52:30,779 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 18:52:30,779 INFO L276 IsEmpty]: Start isEmpty. Operand 31130 states and 92263 transitions. [2019-12-07 18:52:30,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:52:30,810 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:30,810 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:30,810 INFO L410 AbstractCegarLoop]: === Iteration 49 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:30,810 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:30,810 INFO L82 PathProgramCache]: Analyzing trace with hash -116411483, now seen corresponding path program 42 times [2019-12-07 18:52:30,810 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:30,810 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [18443657] [2019-12-07 18:52:30,811 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:30,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:31,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:31,348 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [18443657] [2019-12-07 18:52:31,348 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:31,348 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2019-12-07 18:52:31,348 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1419796526] [2019-12-07 18:52:31,348 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-12-07 18:52:31,348 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:31,348 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 18:52:31,348 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=447, Unknown=0, NotChecked=0, Total=506 [2019-12-07 18:52:31,348 INFO L87 Difference]: Start difference. First operand 31130 states and 92263 transitions. Second operand 23 states. [2019-12-07 18:52:36,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:36,268 INFO L93 Difference]: Finished difference Result 42740 states and 126010 transitions. [2019-12-07 18:52:36,268 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2019-12-07 18:52:36,268 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 72 [2019-12-07 18:52:36,269 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:36,325 INFO L225 Difference]: With dead ends: 42740 [2019-12-07 18:52:36,325 INFO L226 Difference]: Without dead ends: 40796 [2019-12-07 18:52:36,325 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 578 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=326, Invalid=2224, Unknown=0, NotChecked=0, Total=2550 [2019-12-07 18:52:36,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40796 states. [2019-12-07 18:52:36,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40796 to 33257. [2019-12-07 18:52:36,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33257 states. [2019-12-07 18:52:36,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33257 states to 33257 states and 98223 transitions. [2019-12-07 18:52:36,858 INFO L78 Accepts]: Start accepts. Automaton has 33257 states and 98223 transitions. Word has length 72 [2019-12-07 18:52:36,858 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:36,858 INFO L462 AbstractCegarLoop]: Abstraction has 33257 states and 98223 transitions. [2019-12-07 18:52:36,858 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-12-07 18:52:36,858 INFO L276 IsEmpty]: Start isEmpty. Operand 33257 states and 98223 transitions. [2019-12-07 18:52:36,890 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:52:36,890 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:36,891 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:36,891 INFO L410 AbstractCegarLoop]: === Iteration 50 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:36,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:36,891 INFO L82 PathProgramCache]: Analyzing trace with hash 290754697, now seen corresponding path program 43 times [2019-12-07 18:52:36,891 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:36,891 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1926418397] [2019-12-07 18:52:36,891 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:36,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:37,319 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:37,319 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1926418397] [2019-12-07 18:52:37,319 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:37,319 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2019-12-07 18:52:37,319 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [905743454] [2019-12-07 18:52:37,320 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 18:52:37,320 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:37,320 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 18:52:37,320 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=297, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:52:37,320 INFO L87 Difference]: Start difference. First operand 33257 states and 98223 transitions. Second operand 19 states. [2019-12-07 18:52:38,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:38,612 INFO L93 Difference]: Finished difference Result 36870 states and 108534 transitions. [2019-12-07 18:52:38,612 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-12-07 18:52:38,612 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 72 [2019-12-07 18:52:38,612 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:38,649 INFO L225 Difference]: With dead ends: 36870 [2019-12-07 18:52:38,649 INFO L226 Difference]: Without dead ends: 36771 [2019-12-07 18:52:38,649 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 108 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=102, Invalid=710, Unknown=0, NotChecked=0, Total=812 [2019-12-07 18:52:38,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36771 states. [2019-12-07 18:52:39,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36771 to 34131. [2019-12-07 18:52:39,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34131 states. [2019-12-07 18:52:39,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34131 states to 34131 states and 100884 transitions. [2019-12-07 18:52:39,131 INFO L78 Accepts]: Start accepts. Automaton has 34131 states and 100884 transitions. Word has length 72 [2019-12-07 18:52:39,131 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:39,131 INFO L462 AbstractCegarLoop]: Abstraction has 34131 states and 100884 transitions. [2019-12-07 18:52:39,131 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 18:52:39,131 INFO L276 IsEmpty]: Start isEmpty. Operand 34131 states and 100884 transitions. [2019-12-07 18:52:39,164 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:52:39,164 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:39,165 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:39,165 INFO L410 AbstractCegarLoop]: === Iteration 51 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:39,165 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:39,165 INFO L82 PathProgramCache]: Analyzing trace with hash -1261826935, now seen corresponding path program 44 times [2019-12-07 18:52:39,165 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:39,165 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1378705940] [2019-12-07 18:52:39,165 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:39,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:39,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:39,653 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1378705940] [2019-12-07 18:52:39,653 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:39,653 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2019-12-07 18:52:39,653 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1211648858] [2019-12-07 18:52:39,654 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-12-07 18:52:39,654 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:39,654 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 18:52:39,654 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=449, Unknown=0, NotChecked=0, Total=506 [2019-12-07 18:52:39,654 INFO L87 Difference]: Start difference. First operand 34131 states and 100884 transitions. Second operand 23 states. [2019-12-07 18:52:41,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:41,410 INFO L93 Difference]: Finished difference Result 37495 states and 110554 transitions. [2019-12-07 18:52:41,410 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-12-07 18:52:41,411 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 72 [2019-12-07 18:52:41,411 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:41,453 INFO L225 Difference]: With dead ends: 37495 [2019-12-07 18:52:41,453 INFO L226 Difference]: Without dead ends: 37259 [2019-12-07 18:52:41,453 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 262 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=181, Invalid=1301, Unknown=0, NotChecked=0, Total=1482 [2019-12-07 18:52:41,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37259 states. [2019-12-07 18:52:41,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37259 to 34143. [2019-12-07 18:52:41,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34143 states. [2019-12-07 18:52:41,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34143 states to 34143 states and 101124 transitions. [2019-12-07 18:52:41,928 INFO L78 Accepts]: Start accepts. Automaton has 34143 states and 101124 transitions. Word has length 72 [2019-12-07 18:52:41,928 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:41,928 INFO L462 AbstractCegarLoop]: Abstraction has 34143 states and 101124 transitions. [2019-12-07 18:52:41,928 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-12-07 18:52:41,928 INFO L276 IsEmpty]: Start isEmpty. Operand 34143 states and 101124 transitions. [2019-12-07 18:52:41,960 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:52:41,960 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:41,960 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:41,960 INFO L410 AbstractCegarLoop]: === Iteration 52 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:41,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:41,960 INFO L82 PathProgramCache]: Analyzing trace with hash 1152058709, now seen corresponding path program 45 times [2019-12-07 18:52:41,960 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:41,960 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211612407] [2019-12-07 18:52:41,961 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:41,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:42,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:42,935 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1211612407] [2019-12-07 18:52:42,935 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:42,935 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [25] imperfect sequences [] total 25 [2019-12-07 18:52:42,935 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1574701120] [2019-12-07 18:52:42,935 INFO L442 AbstractCegarLoop]: Interpolant automaton has 27 states [2019-12-07 18:52:42,935 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:42,935 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2019-12-07 18:52:42,935 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=628, Unknown=0, NotChecked=0, Total=702 [2019-12-07 18:52:42,936 INFO L87 Difference]: Start difference. First operand 34143 states and 101124 transitions. Second operand 27 states. [2019-12-07 18:52:52,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:52:52,544 INFO L93 Difference]: Finished difference Result 39388 states and 114386 transitions. [2019-12-07 18:52:52,544 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2019-12-07 18:52:52,545 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 72 [2019-12-07 18:52:52,545 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:52:52,599 INFO L225 Difference]: With dead ends: 39388 [2019-12-07 18:52:52,599 INFO L226 Difference]: Without dead ends: 39333 [2019-12-07 18:52:52,599 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 4 SyntacticMatches, 4 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1023 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=446, Invalid=3976, Unknown=0, NotChecked=0, Total=4422 [2019-12-07 18:52:52,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39333 states. [2019-12-07 18:52:53,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39333 to 35266. [2019-12-07 18:52:53,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35266 states. [2019-12-07 18:52:53,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35266 states to 35266 states and 103899 transitions. [2019-12-07 18:52:53,115 INFO L78 Accepts]: Start accepts. Automaton has 35266 states and 103899 transitions. Word has length 72 [2019-12-07 18:52:53,115 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:52:53,115 INFO L462 AbstractCegarLoop]: Abstraction has 35266 states and 103899 transitions. [2019-12-07 18:52:53,115 INFO L463 AbstractCegarLoop]: Interpolant automaton has 27 states. [2019-12-07 18:52:53,115 INFO L276 IsEmpty]: Start isEmpty. Operand 35266 states and 103899 transitions. [2019-12-07 18:52:53,149 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:52:53,149 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:52:53,149 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:52:53,149 INFO L410 AbstractCegarLoop]: === Iteration 53 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:52:53,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:52:53,149 INFO L82 PathProgramCache]: Analyzing trace with hash 242039463, now seen corresponding path program 46 times [2019-12-07 18:52:53,149 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:52:53,149 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1612468571] [2019-12-07 18:52:53,149 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:52:53,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:52:54,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:52:54,696 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1612468571] [2019-12-07 18:52:54,696 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:52:54,696 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [28] imperfect sequences [] total 28 [2019-12-07 18:52:54,696 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1327838949] [2019-12-07 18:52:54,696 INFO L442 AbstractCegarLoop]: Interpolant automaton has 30 states [2019-12-07 18:52:54,696 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:52:54,696 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2019-12-07 18:52:54,696 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=795, Unknown=0, NotChecked=0, Total=870 [2019-12-07 18:52:54,696 INFO L87 Difference]: Start difference. First operand 35266 states and 103899 transitions. Second operand 30 states. [2019-12-07 18:53:04,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:53:04,980 INFO L93 Difference]: Finished difference Result 39424 states and 114557 transitions. [2019-12-07 18:53:04,981 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2019-12-07 18:53:04,981 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 72 [2019-12-07 18:53:04,981 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:53:05,025 INFO L225 Difference]: With dead ends: 39424 [2019-12-07 18:53:05,025 INFO L226 Difference]: Without dead ends: 39403 [2019-12-07 18:53:05,026 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 77 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1511 ImplicationChecksByTransitivity, 4.4s TimeCoverageRelationStatistics Valid=579, Invalid=5583, Unknown=0, NotChecked=0, Total=6162 [2019-12-07 18:53:05,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39403 states. [2019-12-07 18:53:05,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39403 to 35263. [2019-12-07 18:53:05,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35263 states. [2019-12-07 18:53:05,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35263 states to 35263 states and 103893 transitions. [2019-12-07 18:53:05,620 INFO L78 Accepts]: Start accepts. Automaton has 35263 states and 103893 transitions. Word has length 72 [2019-12-07 18:53:05,620 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:53:05,620 INFO L462 AbstractCegarLoop]: Abstraction has 35263 states and 103893 transitions. [2019-12-07 18:53:05,620 INFO L463 AbstractCegarLoop]: Interpolant automaton has 30 states. [2019-12-07 18:53:05,621 INFO L276 IsEmpty]: Start isEmpty. Operand 35263 states and 103893 transitions. [2019-12-07 18:53:05,654 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:53:05,654 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:53:05,654 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:53:05,654 INFO L410 AbstractCegarLoop]: === Iteration 54 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:53:05,654 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:53:05,655 INFO L82 PathProgramCache]: Analyzing trace with hash -589106651, now seen corresponding path program 47 times [2019-12-07 18:53:05,655 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:53:05,655 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1031516210] [2019-12-07 18:53:05,655 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:53:05,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:53:06,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:53:06,399 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1031516210] [2019-12-07 18:53:06,399 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:53:06,399 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 18:53:06,399 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1516066927] [2019-12-07 18:53:06,399 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 18:53:06,400 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:53:06,400 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 18:53:06,400 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=491, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:53:06,400 INFO L87 Difference]: Start difference. First operand 35263 states and 103893 transitions. Second operand 24 states. [2019-12-07 18:53:09,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:53:09,928 INFO L93 Difference]: Finished difference Result 43039 states and 124403 transitions. [2019-12-07 18:53:09,928 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2019-12-07 18:53:09,928 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 18:53:09,929 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:53:09,981 INFO L225 Difference]: With dead ends: 43039 [2019-12-07 18:53:09,981 INFO L226 Difference]: Without dead ends: 42959 [2019-12-07 18:53:09,981 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 551 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=318, Invalid=2232, Unknown=0, NotChecked=0, Total=2550 [2019-12-07 18:53:10,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42959 states. [2019-12-07 18:53:10,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42959 to 34925. [2019-12-07 18:53:10,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34925 states. [2019-12-07 18:53:10,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34925 states to 34925 states and 103029 transitions. [2019-12-07 18:53:10,546 INFO L78 Accepts]: Start accepts. Automaton has 34925 states and 103029 transitions. Word has length 72 [2019-12-07 18:53:10,547 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:53:10,547 INFO L462 AbstractCegarLoop]: Abstraction has 34925 states and 103029 transitions. [2019-12-07 18:53:10,547 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 18:53:10,547 INFO L276 IsEmpty]: Start isEmpty. Operand 34925 states and 103029 transitions. [2019-12-07 18:53:10,580 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:53:10,580 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:53:10,580 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:53:10,580 INFO L410 AbstractCegarLoop]: === Iteration 55 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:53:10,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:53:10,580 INFO L82 PathProgramCache]: Analyzing trace with hash -790438143, now seen corresponding path program 48 times [2019-12-07 18:53:10,581 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:53:10,581 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125226966] [2019-12-07 18:53:10,581 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:53:10,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:53:11,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:53:11,190 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [125226966] [2019-12-07 18:53:11,190 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:53:11,190 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2019-12-07 18:53:11,190 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [494284699] [2019-12-07 18:53:11,190 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-12-07 18:53:11,190 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:53:11,191 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 18:53:11,191 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=538, Unknown=0, NotChecked=0, Total=600 [2019-12-07 18:53:11,191 INFO L87 Difference]: Start difference. First operand 34925 states and 103029 transitions. Second operand 25 states. [2019-12-07 18:53:16,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:53:16,438 INFO L93 Difference]: Finished difference Result 44417 states and 128341 transitions. [2019-12-07 18:53:16,439 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2019-12-07 18:53:16,439 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 72 [2019-12-07 18:53:16,439 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:53:16,499 INFO L225 Difference]: With dead ends: 44417 [2019-12-07 18:53:16,499 INFO L226 Difference]: Without dead ends: 44259 [2019-12-07 18:53:16,499 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 613 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=305, Invalid=2557, Unknown=0, NotChecked=0, Total=2862 [2019-12-07 18:53:16,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44259 states. [2019-12-07 18:53:17,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44259 to 36169. [2019-12-07 18:53:17,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36169 states. [2019-12-07 18:53:17,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36169 states to 36169 states and 106302 transitions. [2019-12-07 18:53:17,176 INFO L78 Accepts]: Start accepts. Automaton has 36169 states and 106302 transitions. Word has length 72 [2019-12-07 18:53:17,176 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:53:17,176 INFO L462 AbstractCegarLoop]: Abstraction has 36169 states and 106302 transitions. [2019-12-07 18:53:17,176 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-12-07 18:53:17,176 INFO L276 IsEmpty]: Start isEmpty. Operand 36169 states and 106302 transitions. [2019-12-07 18:53:17,207 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:53:17,207 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:53:17,207 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:53:17,207 INFO L410 AbstractCegarLoop]: === Iteration 56 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:53:17,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:53:17,208 INFO L82 PathProgramCache]: Analyzing trace with hash 1181142559, now seen corresponding path program 49 times [2019-12-07 18:53:17,208 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:53:17,208 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1923145014] [2019-12-07 18:53:17,208 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:53:17,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:53:17,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:53:17,807 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1923145014] [2019-12-07 18:53:17,807 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:53:17,807 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 18:53:17,807 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1048684917] [2019-12-07 18:53:17,807 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 18:53:17,807 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:53:17,808 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 18:53:17,808 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=490, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:53:17,808 INFO L87 Difference]: Start difference. First operand 36169 states and 106302 transitions. Second operand 24 states. [2019-12-07 18:53:21,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:53:21,515 INFO L93 Difference]: Finished difference Result 43608 states and 125879 transitions. [2019-12-07 18:53:21,516 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2019-12-07 18:53:21,516 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 18:53:21,516 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:53:21,568 INFO L225 Difference]: With dead ends: 43608 [2019-12-07 18:53:21,568 INFO L226 Difference]: Without dead ends: 41225 [2019-12-07 18:53:21,568 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 523 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=319, Invalid=2131, Unknown=0, NotChecked=0, Total=2450 [2019-12-07 18:53:21,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41225 states. [2019-12-07 18:53:22,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41225 to 32825. [2019-12-07 18:53:22,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32825 states. [2019-12-07 18:53:22,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32825 states to 32825 states and 97255 transitions. [2019-12-07 18:53:22,117 INFO L78 Accepts]: Start accepts. Automaton has 32825 states and 97255 transitions. Word has length 72 [2019-12-07 18:53:22,117 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:53:22,117 INFO L462 AbstractCegarLoop]: Abstraction has 32825 states and 97255 transitions. [2019-12-07 18:53:22,117 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 18:53:22,117 INFO L276 IsEmpty]: Start isEmpty. Operand 32825 states and 97255 transitions. [2019-12-07 18:53:22,148 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:53:22,149 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:53:22,149 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:53:22,149 INFO L410 AbstractCegarLoop]: === Iteration 57 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:53:22,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:53:22,149 INFO L82 PathProgramCache]: Analyzing trace with hash -1486247291, now seen corresponding path program 50 times [2019-12-07 18:53:22,149 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:53:22,149 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1833434366] [2019-12-07 18:53:22,149 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:53:22,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:53:23,203 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:53:23,203 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1833434366] [2019-12-07 18:53:23,203 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:53:23,203 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [24] imperfect sequences [] total 24 [2019-12-07 18:53:23,203 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1311846905] [2019-12-07 18:53:23,203 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-12-07 18:53:23,204 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:53:23,204 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-12-07 18:53:23,204 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=589, Unknown=0, NotChecked=0, Total=650 [2019-12-07 18:53:23,204 INFO L87 Difference]: Start difference. First operand 32825 states and 97255 transitions. Second operand 26 states. [2019-12-07 18:53:32,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:53:32,469 INFO L93 Difference]: Finished difference Result 34440 states and 101268 transitions. [2019-12-07 18:53:32,469 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2019-12-07 18:53:32,469 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 72 [2019-12-07 18:53:32,469 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:53:32,509 INFO L225 Difference]: With dead ends: 34440 [2019-12-07 18:53:32,509 INFO L226 Difference]: Without dead ends: 34376 [2019-12-07 18:53:32,509 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 5 SyntacticMatches, 2 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 727 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=313, Invalid=3109, Unknown=0, NotChecked=0, Total=3422 [2019-12-07 18:53:32,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34376 states. [2019-12-07 18:53:32,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34376 to 33127. [2019-12-07 18:53:32,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33127 states. [2019-12-07 18:53:32,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33127 states to 33127 states and 97967 transitions. [2019-12-07 18:53:32,999 INFO L78 Accepts]: Start accepts. Automaton has 33127 states and 97967 transitions. Word has length 72 [2019-12-07 18:53:32,999 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:53:32,999 INFO L462 AbstractCegarLoop]: Abstraction has 33127 states and 97967 transitions. [2019-12-07 18:53:32,999 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-12-07 18:53:32,999 INFO L276 IsEmpty]: Start isEmpty. Operand 33127 states and 97967 transitions. [2019-12-07 18:53:33,098 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:53:33,098 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:53:33,098 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:53:33,098 INFO L410 AbstractCegarLoop]: === Iteration 58 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:53:33,099 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:53:33,099 INFO L82 PathProgramCache]: Analyzing trace with hash 1189499249, now seen corresponding path program 51 times [2019-12-07 18:53:33,099 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:53:33,099 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1783425351] [2019-12-07 18:53:33,099 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:53:33,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:53:33,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:53:33,661 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1783425351] [2019-12-07 18:53:33,661 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:53:33,661 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2019-12-07 18:53:33,661 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [645330633] [2019-12-07 18:53:33,661 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-12-07 18:53:33,661 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:53:33,661 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 18:53:33,661 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=542, Unknown=0, NotChecked=0, Total=600 [2019-12-07 18:53:33,661 INFO L87 Difference]: Start difference. First operand 33127 states and 97967 transitions. Second operand 25 states. [2019-12-07 18:53:35,966 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:53:35,966 INFO L93 Difference]: Finished difference Result 35767 states and 104789 transitions. [2019-12-07 18:53:35,966 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-12-07 18:53:35,966 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 72 [2019-12-07 18:53:35,966 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:53:36,006 INFO L225 Difference]: With dead ends: 35767 [2019-12-07 18:53:36,006 INFO L226 Difference]: Without dead ends: 35235 [2019-12-07 18:53:36,006 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 341 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=190, Invalid=1702, Unknown=0, NotChecked=0, Total=1892 [2019-12-07 18:53:36,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35235 states. [2019-12-07 18:53:36,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35235 to 33355. [2019-12-07 18:53:36,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33355 states. [2019-12-07 18:53:36,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33355 states to 33355 states and 98559 transitions. [2019-12-07 18:53:36,483 INFO L78 Accepts]: Start accepts. Automaton has 33355 states and 98559 transitions. Word has length 72 [2019-12-07 18:53:36,483 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:53:36,483 INFO L462 AbstractCegarLoop]: Abstraction has 33355 states and 98559 transitions. [2019-12-07 18:53:36,483 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-12-07 18:53:36,483 INFO L276 IsEmpty]: Start isEmpty. Operand 33355 states and 98559 transitions. [2019-12-07 18:53:36,515 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:53:36,515 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:53:36,515 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:53:36,515 INFO L410 AbstractCegarLoop]: === Iteration 59 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:53:36,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:53:36,515 INFO L82 PathProgramCache]: Analyzing trace with hash 1551628491, now seen corresponding path program 52 times [2019-12-07 18:53:36,515 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:53:36,515 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [717340542] [2019-12-07 18:53:36,515 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:53:36,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:53:36,684 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:53:36,684 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [717340542] [2019-12-07 18:53:36,684 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:53:36,684 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 18:53:36,684 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1431308063] [2019-12-07 18:53:36,685 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 18:53:36,685 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:53:36,685 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 18:53:36,685 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:53:36,685 INFO L87 Difference]: Start difference. First operand 33355 states and 98559 transitions. Second operand 12 states. [2019-12-07 18:53:37,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:53:37,412 INFO L93 Difference]: Finished difference Result 42934 states and 125916 transitions. [2019-12-07 18:53:37,413 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 18:53:37,413 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 72 [2019-12-07 18:53:37,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:53:37,462 INFO L225 Difference]: With dead ends: 42934 [2019-12-07 18:53:37,462 INFO L226 Difference]: Without dead ends: 39297 [2019-12-07 18:53:37,462 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 85 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=114, Invalid=486, Unknown=0, NotChecked=0, Total=600 [2019-12-07 18:53:37,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39297 states. [2019-12-07 18:53:37,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39297 to 32551. [2019-12-07 18:53:37,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32551 states. [2019-12-07 18:53:37,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32551 states to 32551 states and 96419 transitions. [2019-12-07 18:53:37,959 INFO L78 Accepts]: Start accepts. Automaton has 32551 states and 96419 transitions. Word has length 72 [2019-12-07 18:53:37,959 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:53:37,959 INFO L462 AbstractCegarLoop]: Abstraction has 32551 states and 96419 transitions. [2019-12-07 18:53:37,960 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 18:53:37,960 INFO L276 IsEmpty]: Start isEmpty. Operand 32551 states and 96419 transitions. [2019-12-07 18:53:37,990 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:53:37,990 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:53:37,990 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:53:37,990 INFO L410 AbstractCegarLoop]: === Iteration 60 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:53:37,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:53:37,990 INFO L82 PathProgramCache]: Analyzing trace with hash 2119557665, now seen corresponding path program 53 times [2019-12-07 18:53:37,991 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:53:37,991 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [509368302] [2019-12-07 18:53:37,991 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:53:38,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:53:38,555 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:53:38,555 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [509368302] [2019-12-07 18:53:38,555 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:53:38,555 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 18:53:38,555 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1744993820] [2019-12-07 18:53:38,555 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 18:53:38,555 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:53:38,556 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 18:53:38,556 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=491, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:53:38,556 INFO L87 Difference]: Start difference. First operand 32551 states and 96419 transitions. Second operand 24 states. [2019-12-07 18:53:43,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:53:43,615 INFO L93 Difference]: Finished difference Result 42974 states and 125618 transitions. [2019-12-07 18:53:43,615 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2019-12-07 18:53:43,616 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 18:53:43,616 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:53:43,660 INFO L225 Difference]: With dead ends: 42974 [2019-12-07 18:53:43,660 INFO L226 Difference]: Without dead ends: 41106 [2019-12-07 18:53:43,661 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 856 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=428, Invalid=3112, Unknown=0, NotChecked=0, Total=3540 [2019-12-07 18:53:43,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41106 states. [2019-12-07 18:53:44,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41106 to 33217. [2019-12-07 18:53:44,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33217 states. [2019-12-07 18:53:44,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33217 states to 33217 states and 98446 transitions. [2019-12-07 18:53:44,171 INFO L78 Accepts]: Start accepts. Automaton has 33217 states and 98446 transitions. Word has length 72 [2019-12-07 18:53:44,171 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:53:44,171 INFO L462 AbstractCegarLoop]: Abstraction has 33217 states and 98446 transitions. [2019-12-07 18:53:44,171 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 18:53:44,171 INFO L276 IsEmpty]: Start isEmpty. Operand 33217 states and 98446 transitions. [2019-12-07 18:53:44,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:53:44,203 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:53:44,203 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:53:44,203 INFO L410 AbstractCegarLoop]: === Iteration 61 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:53:44,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:53:44,203 INFO L82 PathProgramCache]: Analyzing trace with hash -1768243451, now seen corresponding path program 54 times [2019-12-07 18:53:44,204 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:53:44,204 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815775991] [2019-12-07 18:53:44,204 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:53:44,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:53:44,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:53:44,632 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1815775991] [2019-12-07 18:53:44,632 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:53:44,633 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2019-12-07 18:53:44,633 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1913251074] [2019-12-07 18:53:44,633 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 18:53:44,633 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:53:44,633 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 18:53:44,633 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=297, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:53:44,633 INFO L87 Difference]: Start difference. First operand 33217 states and 98446 transitions. Second operand 19 states. [2019-12-07 18:53:45,966 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:53:45,966 INFO L93 Difference]: Finished difference Result 40589 states and 120381 transitions. [2019-12-07 18:53:45,966 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-12-07 18:53:45,966 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 72 [2019-12-07 18:53:45,967 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:53:46,013 INFO L225 Difference]: With dead ends: 40589 [2019-12-07 18:53:46,014 INFO L226 Difference]: Without dead ends: 40490 [2019-12-07 18:53:46,014 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 148 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=128, Invalid=864, Unknown=0, NotChecked=0, Total=992 [2019-12-07 18:53:46,123 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40490 states. [2019-12-07 18:53:46,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40490 to 33942. [2019-12-07 18:53:46,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33942 states. [2019-12-07 18:53:46,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33942 states to 33942 states and 100639 transitions. [2019-12-07 18:53:46,545 INFO L78 Accepts]: Start accepts. Automaton has 33942 states and 100639 transitions. Word has length 72 [2019-12-07 18:53:46,545 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:53:46,545 INFO L462 AbstractCegarLoop]: Abstraction has 33942 states and 100639 transitions. [2019-12-07 18:53:46,545 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 18:53:46,545 INFO L276 IsEmpty]: Start isEmpty. Operand 33942 states and 100639 transitions. [2019-12-07 18:53:46,577 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:53:46,577 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:53:46,578 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:53:46,578 INFO L410 AbstractCegarLoop]: === Iteration 62 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:53:46,578 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:53:46,578 INFO L82 PathProgramCache]: Analyzing trace with hash 974142213, now seen corresponding path program 55 times [2019-12-07 18:53:46,578 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:53:46,578 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267405007] [2019-12-07 18:53:46,578 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:53:46,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:53:46,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:53:46,754 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [267405007] [2019-12-07 18:53:46,755 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:53:46,755 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 18:53:46,755 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [330874555] [2019-12-07 18:53:46,755 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 18:53:46,755 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:53:46,755 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 18:53:46,755 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=154, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:53:46,755 INFO L87 Difference]: Start difference. First operand 33942 states and 100639 transitions. Second operand 14 states. [2019-12-07 18:53:47,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:53:47,863 INFO L93 Difference]: Finished difference Result 41576 states and 122890 transitions. [2019-12-07 18:53:47,863 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-12-07 18:53:47,863 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 72 [2019-12-07 18:53:47,863 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:53:47,908 INFO L225 Difference]: With dead ends: 41576 [2019-12-07 18:53:47,908 INFO L226 Difference]: Without dead ends: 38843 [2019-12-07 18:53:47,909 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 75 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=97, Invalid=503, Unknown=0, NotChecked=0, Total=600 [2019-12-07 18:53:48,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38843 states. [2019-12-07 18:53:48,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38843 to 34582. [2019-12-07 18:53:48,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34582 states. [2019-12-07 18:53:48,396 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34582 states to 34582 states and 102616 transitions. [2019-12-07 18:53:48,397 INFO L78 Accepts]: Start accepts. Automaton has 34582 states and 102616 transitions. Word has length 72 [2019-12-07 18:53:48,397 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:53:48,397 INFO L462 AbstractCegarLoop]: Abstraction has 34582 states and 102616 transitions. [2019-12-07 18:53:48,397 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 18:53:48,397 INFO L276 IsEmpty]: Start isEmpty. Operand 34582 states and 102616 transitions. [2019-12-07 18:53:48,429 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:53:48,430 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:53:48,430 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:53:48,430 INFO L410 AbstractCegarLoop]: === Iteration 63 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:53:48,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:53:48,430 INFO L82 PathProgramCache]: Analyzing trace with hash -906939439, now seen corresponding path program 56 times [2019-12-07 18:53:48,430 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:53:48,430 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [871071533] [2019-12-07 18:53:48,430 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:53:48,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:53:48,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:53:48,697 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [871071533] [2019-12-07 18:53:48,697 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:53:48,697 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 18:53:48,697 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1505937886] [2019-12-07 18:53:48,697 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 18:53:48,697 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:53:48,697 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 18:53:48,698 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:53:48,698 INFO L87 Difference]: Start difference. First operand 34582 states and 102616 transitions. Second operand 16 states. [2019-12-07 18:53:50,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:53:50,561 INFO L93 Difference]: Finished difference Result 41006 states and 121012 transitions. [2019-12-07 18:53:50,562 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2019-12-07 18:53:50,562 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2019-12-07 18:53:50,562 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:53:50,607 INFO L225 Difference]: With dead ends: 41006 [2019-12-07 18:53:50,607 INFO L226 Difference]: Without dead ends: 38621 [2019-12-07 18:53:50,607 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 217 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=193, Invalid=1139, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 18:53:50,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38621 states. [2019-12-07 18:53:51,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38621 to 34668. [2019-12-07 18:53:51,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34668 states. [2019-12-07 18:53:51,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34668 states to 34668 states and 102759 transitions. [2019-12-07 18:53:51,142 INFO L78 Accepts]: Start accepts. Automaton has 34668 states and 102759 transitions. Word has length 72 [2019-12-07 18:53:51,142 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:53:51,142 INFO L462 AbstractCegarLoop]: Abstraction has 34668 states and 102759 transitions. [2019-12-07 18:53:51,142 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 18:53:51,142 INFO L276 IsEmpty]: Start isEmpty. Operand 34668 states and 102759 transitions. [2019-12-07 18:53:51,175 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:53:51,175 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:53:51,175 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:53:51,175 INFO L410 AbstractCegarLoop]: === Iteration 64 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:53:51,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:53:51,176 INFO L82 PathProgramCache]: Analyzing trace with hash 691619821, now seen corresponding path program 57 times [2019-12-07 18:53:51,176 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:53:51,176 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1582595934] [2019-12-07 18:53:51,176 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:53:51,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:53:51,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:53:51,524 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1582595934] [2019-12-07 18:53:51,524 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:53:51,524 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 18:53:51,524 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [769350094] [2019-12-07 18:53:51,525 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 18:53:51,525 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:53:51,525 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 18:53:51,525 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2019-12-07 18:53:51,525 INFO L87 Difference]: Start difference. First operand 34668 states and 102759 transitions. Second operand 17 states. [2019-12-07 18:53:53,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:53:53,518 INFO L93 Difference]: Finished difference Result 46378 states and 136446 transitions. [2019-12-07 18:53:53,518 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-12-07 18:53:53,518 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 72 [2019-12-07 18:53:53,519 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:53:53,570 INFO L225 Difference]: With dead ends: 46378 [2019-12-07 18:53:53,571 INFO L226 Difference]: Without dead ends: 44979 [2019-12-07 18:53:53,571 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 339 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=240, Invalid=1566, Unknown=0, NotChecked=0, Total=1806 [2019-12-07 18:53:53,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44979 states. [2019-12-07 18:53:54,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44979 to 38357. [2019-12-07 18:53:54,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38357 states. [2019-12-07 18:53:54,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38357 states to 38357 states and 114527 transitions. [2019-12-07 18:53:54,155 INFO L78 Accepts]: Start accepts. Automaton has 38357 states and 114527 transitions. Word has length 72 [2019-12-07 18:53:54,155 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:53:54,155 INFO L462 AbstractCegarLoop]: Abstraction has 38357 states and 114527 transitions. [2019-12-07 18:53:54,155 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 18:53:54,155 INFO L276 IsEmpty]: Start isEmpty. Operand 38357 states and 114527 transitions. [2019-12-07 18:53:54,191 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:53:54,191 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:53:54,191 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:53:54,191 INFO L410 AbstractCegarLoop]: === Iteration 65 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:53:54,191 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:53:54,192 INFO L82 PathProgramCache]: Analyzing trace with hash 720703671, now seen corresponding path program 58 times [2019-12-07 18:53:54,192 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:53:54,192 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [176962848] [2019-12-07 18:53:54,192 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:53:54,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:53:54,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:53:54,490 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [176962848] [2019-12-07 18:53:54,491 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:53:54,491 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 18:53:54,491 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [566460631] [2019-12-07 18:53:54,491 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 18:53:54,491 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:53:54,491 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 18:53:54,491 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:53:54,491 INFO L87 Difference]: Start difference. First operand 38357 states and 114527 transitions. Second operand 16 states. [2019-12-07 18:53:59,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:53:59,332 INFO L93 Difference]: Finished difference Result 47411 states and 140421 transitions. [2019-12-07 18:53:59,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2019-12-07 18:53:59,333 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2019-12-07 18:53:59,333 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:53:59,384 INFO L225 Difference]: With dead ends: 47411 [2019-12-07 18:53:59,384 INFO L226 Difference]: Without dead ends: 43227 [2019-12-07 18:53:59,384 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 432 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=270, Invalid=1800, Unknown=0, NotChecked=0, Total=2070 [2019-12-07 18:53:59,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43227 states. [2019-12-07 18:53:59,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43227 to 39182. [2019-12-07 18:53:59,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39182 states. [2019-12-07 18:53:59,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39182 states to 39182 states and 116859 transitions. [2019-12-07 18:53:59,966 INFO L78 Accepts]: Start accepts. Automaton has 39182 states and 116859 transitions. Word has length 72 [2019-12-07 18:53:59,966 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:53:59,966 INFO L462 AbstractCegarLoop]: Abstraction has 39182 states and 116859 transitions. [2019-12-07 18:53:59,966 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 18:53:59,966 INFO L276 IsEmpty]: Start isEmpty. Operand 39182 states and 116859 transitions. [2019-12-07 18:54:00,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:54:00,003 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:54:00,003 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:54:00,003 INFO L410 AbstractCegarLoop]: === Iteration 66 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:54:00,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:54:00,003 INFO L82 PathProgramCache]: Analyzing trace with hash 1851273787, now seen corresponding path program 59 times [2019-12-07 18:54:00,004 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:54:00,004 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [820553359] [2019-12-07 18:54:00,004 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:54:00,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:54:00,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:54:00,276 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [820553359] [2019-12-07 18:54:00,276 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:54:00,276 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 18:54:00,276 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2077931412] [2019-12-07 18:54:00,276 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 18:54:00,276 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:54:00,276 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 18:54:00,277 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2019-12-07 18:54:00,277 INFO L87 Difference]: Start difference. First operand 39182 states and 116859 transitions. Second operand 17 states. [2019-12-07 18:54:01,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:54:01,953 INFO L93 Difference]: Finished difference Result 42404 states and 125459 transitions. [2019-12-07 18:54:01,953 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2019-12-07 18:54:01,954 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 72 [2019-12-07 18:54:01,954 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:54:02,001 INFO L225 Difference]: With dead ends: 42404 [2019-12-07 18:54:02,001 INFO L226 Difference]: Without dead ends: 41037 [2019-12-07 18:54:02,002 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 185 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=163, Invalid=1027, Unknown=0, NotChecked=0, Total=1190 [2019-12-07 18:54:02,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41037 states. [2019-12-07 18:54:02,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41037 to 38866. [2019-12-07 18:54:02,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38866 states. [2019-12-07 18:54:02,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38866 states to 38866 states and 115877 transitions. [2019-12-07 18:54:02,552 INFO L78 Accepts]: Start accepts. Automaton has 38866 states and 115877 transitions. Word has length 72 [2019-12-07 18:54:02,552 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:54:02,552 INFO L462 AbstractCegarLoop]: Abstraction has 38866 states and 115877 transitions. [2019-12-07 18:54:02,552 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 18:54:02,552 INFO L276 IsEmpty]: Start isEmpty. Operand 38866 states and 115877 transitions. [2019-12-07 18:54:02,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:54:02,589 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:54:02,589 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:54:02,589 INFO L410 AbstractCegarLoop]: === Iteration 67 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:54:02,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:54:02,589 INFO L82 PathProgramCache]: Analyzing trace with hash 655404031, now seen corresponding path program 60 times [2019-12-07 18:54:02,590 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:54:02,590 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [937470176] [2019-12-07 18:54:02,590 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:54:02,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:54:02,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:54:02,802 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [937470176] [2019-12-07 18:54:02,802 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:54:02,802 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 18:54:02,802 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [124291342] [2019-12-07 18:54:02,803 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 18:54:02,803 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:54:02,803 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 18:54:02,803 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=179, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:54:02,803 INFO L87 Difference]: Start difference. First operand 38866 states and 115877 transitions. Second operand 15 states. [2019-12-07 18:54:04,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:54:04,757 INFO L93 Difference]: Finished difference Result 44157 states and 130910 transitions. [2019-12-07 18:54:04,757 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2019-12-07 18:54:04,757 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 72 [2019-12-07 18:54:04,757 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:54:04,807 INFO L225 Difference]: With dead ends: 44157 [2019-12-07 18:54:04,808 INFO L226 Difference]: Without dead ends: 41355 [2019-12-07 18:54:04,808 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 159 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=164, Invalid=892, Unknown=0, NotChecked=0, Total=1056 [2019-12-07 18:54:04,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41355 states. [2019-12-07 18:54:05,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41355 to 38605. [2019-12-07 18:54:05,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38605 states. [2019-12-07 18:54:05,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38605 states to 38605 states and 115086 transitions. [2019-12-07 18:54:05,338 INFO L78 Accepts]: Start accepts. Automaton has 38605 states and 115086 transitions. Word has length 72 [2019-12-07 18:54:05,338 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:54:05,338 INFO L462 AbstractCegarLoop]: Abstraction has 38605 states and 115086 transitions. [2019-12-07 18:54:05,339 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 18:54:05,339 INFO L276 IsEmpty]: Start isEmpty. Operand 38605 states and 115086 transitions. [2019-12-07 18:54:05,375 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:54:05,375 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:54:05,375 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:54:05,376 INFO L410 AbstractCegarLoop]: === Iteration 68 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:54:05,376 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:54:05,376 INFO L82 PathProgramCache]: Analyzing trace with hash 593122915, now seen corresponding path program 61 times [2019-12-07 18:54:05,376 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:54:05,376 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1411291730] [2019-12-07 18:54:05,376 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:54:05,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:54:05,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:54:05,866 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1411291730] [2019-12-07 18:54:05,866 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:54:05,866 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 18:54:05,866 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [675154665] [2019-12-07 18:54:05,866 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 18:54:05,866 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:54:05,867 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 18:54:05,867 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=267, Unknown=0, NotChecked=0, Total=306 [2019-12-07 18:54:05,867 INFO L87 Difference]: Start difference. First operand 38605 states and 115086 transitions. Second operand 18 states. [2019-12-07 18:54:08,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:54:08,257 INFO L93 Difference]: Finished difference Result 42102 states and 124403 transitions. [2019-12-07 18:54:08,257 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-12-07 18:54:08,257 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 72 [2019-12-07 18:54:08,257 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:54:08,307 INFO L225 Difference]: With dead ends: 42102 [2019-12-07 18:54:08,307 INFO L226 Difference]: Without dead ends: 40544 [2019-12-07 18:54:08,307 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 365 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=251, Invalid=1729, Unknown=0, NotChecked=0, Total=1980 [2019-12-07 18:54:08,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40544 states. [2019-12-07 18:54:08,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40544 to 38193. [2019-12-07 18:54:08,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38193 states. [2019-12-07 18:54:08,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38193 states to 38193 states and 113921 transitions. [2019-12-07 18:54:08,867 INFO L78 Accepts]: Start accepts. Automaton has 38193 states and 113921 transitions. Word has length 72 [2019-12-07 18:54:08,867 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:54:08,867 INFO L462 AbstractCegarLoop]: Abstraction has 38193 states and 113921 transitions. [2019-12-07 18:54:08,867 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 18:54:08,867 INFO L276 IsEmpty]: Start isEmpty. Operand 38193 states and 113921 transitions. [2019-12-07 18:54:08,900 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:54:08,900 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:54:08,900 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:54:08,900 INFO L410 AbstractCegarLoop]: === Iteration 69 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:54:08,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:54:08,900 INFO L82 PathProgramCache]: Analyzing trace with hash -1297925903, now seen corresponding path program 62 times [2019-12-07 18:54:08,900 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:54:08,900 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1673612015] [2019-12-07 18:54:08,901 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:54:08,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:54:09,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:54:09,172 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1673612015] [2019-12-07 18:54:09,172 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:54:09,172 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 18:54:09,172 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [860252030] [2019-12-07 18:54:09,172 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 18:54:09,172 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:54:09,173 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 18:54:09,173 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:54:09,173 INFO L87 Difference]: Start difference. First operand 38193 states and 113921 transitions. Second operand 16 states. [2019-12-07 18:54:11,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:54:11,525 INFO L93 Difference]: Finished difference Result 41591 states and 123160 transitions. [2019-12-07 18:54:11,525 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2019-12-07 18:54:11,525 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2019-12-07 18:54:11,525 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:54:11,573 INFO L225 Difference]: With dead ends: 41591 [2019-12-07 18:54:11,573 INFO L226 Difference]: Without dead ends: 40563 [2019-12-07 18:54:11,573 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 197 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=181, Invalid=1079, Unknown=0, NotChecked=0, Total=1260 [2019-12-07 18:54:11,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40563 states. [2019-12-07 18:54:12,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40563 to 38099. [2019-12-07 18:54:12,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38099 states. [2019-12-07 18:54:12,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38099 states to 38099 states and 113618 transitions. [2019-12-07 18:54:12,101 INFO L78 Accepts]: Start accepts. Automaton has 38099 states and 113618 transitions. Word has length 72 [2019-12-07 18:54:12,101 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:54:12,101 INFO L462 AbstractCegarLoop]: Abstraction has 38099 states and 113618 transitions. [2019-12-07 18:54:12,101 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 18:54:12,101 INFO L276 IsEmpty]: Start isEmpty. Operand 38099 states and 113618 transitions. [2019-12-07 18:54:12,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:54:12,138 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:54:12,138 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:54:12,138 INFO L410 AbstractCegarLoop]: === Iteration 70 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:54:12,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:54:12,138 INFO L82 PathProgramCache]: Analyzing trace with hash 867471333, now seen corresponding path program 63 times [2019-12-07 18:54:12,138 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:54:12,138 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1232135278] [2019-12-07 18:54:12,139 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:54:12,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:54:12,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:54:12,463 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1232135278] [2019-12-07 18:54:12,464 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:54:12,464 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 18:54:12,464 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [734719618] [2019-12-07 18:54:12,464 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 18:54:12,464 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:54:12,464 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 18:54:12,464 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=235, Unknown=0, NotChecked=0, Total=272 [2019-12-07 18:54:12,464 INFO L87 Difference]: Start difference. First operand 38099 states and 113618 transitions. Second operand 17 states. [2019-12-07 18:54:14,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:54:14,919 INFO L93 Difference]: Finished difference Result 43780 states and 128210 transitions. [2019-12-07 18:54:14,919 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2019-12-07 18:54:14,919 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 72 [2019-12-07 18:54:14,920 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:54:14,970 INFO L225 Difference]: With dead ends: 43780 [2019-12-07 18:54:14,970 INFO L226 Difference]: Without dead ends: 41600 [2019-12-07 18:54:14,970 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 247 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=205, Invalid=1277, Unknown=0, NotChecked=0, Total=1482 [2019-12-07 18:54:15,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41600 states. [2019-12-07 18:54:15,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41600 to 36018. [2019-12-07 18:54:15,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36018 states. [2019-12-07 18:54:15,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36018 states to 36018 states and 106334 transitions. [2019-12-07 18:54:15,511 INFO L78 Accepts]: Start accepts. Automaton has 36018 states and 106334 transitions. Word has length 72 [2019-12-07 18:54:15,511 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:54:15,511 INFO L462 AbstractCegarLoop]: Abstraction has 36018 states and 106334 transitions. [2019-12-07 18:54:15,511 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 18:54:15,511 INFO L276 IsEmpty]: Start isEmpty. Operand 36018 states and 106334 transitions. [2019-12-07 18:54:15,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:54:15,545 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:54:15,545 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:54:15,545 INFO L410 AbstractCegarLoop]: === Iteration 71 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:54:15,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:54:15,546 INFO L82 PathProgramCache]: Analyzing trace with hash 1595227909, now seen corresponding path program 64 times [2019-12-07 18:54:15,546 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:54:15,546 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [240209617] [2019-12-07 18:54:15,546 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:54:15,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:54:16,151 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:54:16,151 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [240209617] [2019-12-07 18:54:16,151 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:54:16,152 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [24] imperfect sequences [] total 24 [2019-12-07 18:54:16,152 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1750548236] [2019-12-07 18:54:16,152 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-12-07 18:54:16,152 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:54:16,152 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-12-07 18:54:16,152 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=587, Unknown=0, NotChecked=0, Total=650 [2019-12-07 18:54:16,152 INFO L87 Difference]: Start difference. First operand 36018 states and 106334 transitions. Second operand 26 states. [2019-12-07 18:54:23,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:54:23,921 INFO L93 Difference]: Finished difference Result 55090 states and 160477 transitions. [2019-12-07 18:54:23,922 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2019-12-07 18:54:23,922 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 72 [2019-12-07 18:54:23,922 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:54:23,989 INFO L225 Difference]: With dead ends: 55090 [2019-12-07 18:54:23,989 INFO L226 Difference]: Without dead ends: 52612 [2019-12-07 18:54:23,989 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1000 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=419, Invalid=3741, Unknown=0, NotChecked=0, Total=4160 [2019-12-07 18:54:24,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52612 states. [2019-12-07 18:54:24,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52612 to 37047. [2019-12-07 18:54:24,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37047 states. [2019-12-07 18:54:24,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37047 states to 37047 states and 109401 transitions. [2019-12-07 18:54:24,655 INFO L78 Accepts]: Start accepts. Automaton has 37047 states and 109401 transitions. Word has length 72 [2019-12-07 18:54:24,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:54:24,655 INFO L462 AbstractCegarLoop]: Abstraction has 37047 states and 109401 transitions. [2019-12-07 18:54:24,655 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-12-07 18:54:24,655 INFO L276 IsEmpty]: Start isEmpty. Operand 37047 states and 109401 transitions. [2019-12-07 18:54:24,689 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:54:24,690 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:54:24,690 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:54:24,690 INFO L410 AbstractCegarLoop]: === Iteration 72 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:54:24,690 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:54:24,690 INFO L82 PathProgramCache]: Analyzing trace with hash -963955527, now seen corresponding path program 65 times [2019-12-07 18:54:24,690 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:54:24,690 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1668392688] [2019-12-07 18:54:24,691 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:54:24,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:54:25,364 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:54:25,364 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1668392688] [2019-12-07 18:54:25,364 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:54:25,364 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [24] imperfect sequences [] total 24 [2019-12-07 18:54:25,364 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2018775570] [2019-12-07 18:54:25,364 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-12-07 18:54:25,364 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:54:25,364 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-12-07 18:54:25,365 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=589, Unknown=0, NotChecked=0, Total=650 [2019-12-07 18:54:25,365 INFO L87 Difference]: Start difference. First operand 37047 states and 109401 transitions. Second operand 26 states. [2019-12-07 18:54:33,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:54:33,856 INFO L93 Difference]: Finished difference Result 55334 states and 161374 transitions. [2019-12-07 18:54:33,856 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2019-12-07 18:54:33,856 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 72 [2019-12-07 18:54:33,856 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:54:33,935 INFO L225 Difference]: With dead ends: 55334 [2019-12-07 18:54:33,935 INFO L226 Difference]: Without dead ends: 53488 [2019-12-07 18:54:33,935 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 4 SyntacticMatches, 4 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1219 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=450, Invalid=4520, Unknown=0, NotChecked=0, Total=4970 [2019-12-07 18:54:34,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53488 states. [2019-12-07 18:54:34,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53488 to 39689. [2019-12-07 18:54:34,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39689 states. [2019-12-07 18:54:34,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39689 states to 39689 states and 117251 transitions. [2019-12-07 18:54:34,588 INFO L78 Accepts]: Start accepts. Automaton has 39689 states and 117251 transitions. Word has length 72 [2019-12-07 18:54:34,588 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:54:34,588 INFO L462 AbstractCegarLoop]: Abstraction has 39689 states and 117251 transitions. [2019-12-07 18:54:34,588 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-12-07 18:54:34,588 INFO L276 IsEmpty]: Start isEmpty. Operand 39689 states and 117251 transitions. [2019-12-07 18:54:34,626 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:54:34,626 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:54:34,626 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:54:34,626 INFO L410 AbstractCegarLoop]: === Iteration 73 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:54:34,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:54:34,627 INFO L82 PathProgramCache]: Analyzing trace with hash 663222811, now seen corresponding path program 66 times [2019-12-07 18:54:34,627 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:54:34,627 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2012841929] [2019-12-07 18:54:34,627 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:54:34,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:54:35,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:54:35,142 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2012841929] [2019-12-07 18:54:35,142 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:54:35,143 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 18:54:35,143 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [216949271] [2019-12-07 18:54:35,143 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 18:54:35,143 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:54:35,143 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 18:54:35,143 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=492, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:54:35,143 INFO L87 Difference]: Start difference. First operand 39689 states and 117251 transitions. Second operand 24 states. [2019-12-07 18:54:45,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:54:45,422 INFO L93 Difference]: Finished difference Result 61918 states and 181349 transitions. [2019-12-07 18:54:45,422 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2019-12-07 18:54:45,423 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 18:54:45,423 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:54:45,498 INFO L225 Difference]: With dead ends: 61918 [2019-12-07 18:54:45,498 INFO L226 Difference]: Without dead ends: 52741 [2019-12-07 18:54:45,499 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1317 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=501, Invalid=4469, Unknown=0, NotChecked=0, Total=4970 [2019-12-07 18:54:45,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52741 states. [2019-12-07 18:54:46,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52741 to 37683. [2019-12-07 18:54:46,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37683 states. [2019-12-07 18:54:46,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37683 states to 37683 states and 111128 transitions. [2019-12-07 18:54:46,151 INFO L78 Accepts]: Start accepts. Automaton has 37683 states and 111128 transitions. Word has length 72 [2019-12-07 18:54:46,151 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:54:46,151 INFO L462 AbstractCegarLoop]: Abstraction has 37683 states and 111128 transitions. [2019-12-07 18:54:46,151 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 18:54:46,151 INFO L276 IsEmpty]: Start isEmpty. Operand 37683 states and 111128 transitions. [2019-12-07 18:54:46,187 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:54:46,187 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:54:46,187 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:54:46,187 INFO L410 AbstractCegarLoop]: === Iteration 74 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:54:46,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:54:46,188 INFO L82 PathProgramCache]: Analyzing trace with hash -1546179521, now seen corresponding path program 67 times [2019-12-07 18:54:46,188 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:54:46,188 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [736643912] [2019-12-07 18:54:46,188 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:54:46,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:54:46,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:54:46,385 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [736643912] [2019-12-07 18:54:46,385 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:54:46,385 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 18:54:46,385 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1867288819] [2019-12-07 18:54:46,386 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 18:54:46,386 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:54:46,386 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 18:54:46,386 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=130, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:54:46,386 INFO L87 Difference]: Start difference. First operand 37683 states and 111128 transitions. Second operand 13 states. [2019-12-07 18:54:48,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:54:48,001 INFO L93 Difference]: Finished difference Result 45510 states and 133174 transitions. [2019-12-07 18:54:48,001 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 18:54:48,001 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 72 [2019-12-07 18:54:48,001 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:54:48,051 INFO L225 Difference]: With dead ends: 45510 [2019-12-07 18:54:48,051 INFO L226 Difference]: Without dead ends: 43258 [2019-12-07 18:54:48,051 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 101 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=121, Invalid=581, Unknown=0, NotChecked=0, Total=702 [2019-12-07 18:54:48,162 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43258 states. [2019-12-07 18:54:48,550 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43258 to 37803. [2019-12-07 18:54:48,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37803 states. [2019-12-07 18:54:48,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37803 states to 37803 states and 111522 transitions. [2019-12-07 18:54:48,611 INFO L78 Accepts]: Start accepts. Automaton has 37803 states and 111522 transitions. Word has length 72 [2019-12-07 18:54:48,611 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:54:48,611 INFO L462 AbstractCegarLoop]: Abstraction has 37803 states and 111522 transitions. [2019-12-07 18:54:48,611 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 18:54:48,611 INFO L276 IsEmpty]: Start isEmpty. Operand 37803 states and 111522 transitions. [2019-12-07 18:54:48,646 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:54:48,646 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:54:48,646 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:54:48,646 INFO L410 AbstractCegarLoop]: === Iteration 75 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:54:48,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:54:48,647 INFO L82 PathProgramCache]: Analyzing trace with hash 2067322597, now seen corresponding path program 68 times [2019-12-07 18:54:48,647 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:54:48,647 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557836450] [2019-12-07 18:54:48,647 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:54:48,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:54:48,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:54:48,826 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [557836450] [2019-12-07 18:54:48,826 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:54:48,826 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 18:54:48,826 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1205654137] [2019-12-07 18:54:48,826 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 18:54:48,826 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:54:48,827 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 18:54:48,827 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=154, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:54:48,827 INFO L87 Difference]: Start difference. First operand 37803 states and 111522 transitions. Second operand 14 states. [2019-12-07 18:54:52,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:54:52,034 INFO L93 Difference]: Finished difference Result 41257 states and 120463 transitions. [2019-12-07 18:54:52,034 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 18:54:52,034 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 72 [2019-12-07 18:54:52,034 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:54:52,081 INFO L225 Difference]: With dead ends: 41257 [2019-12-07 18:54:52,081 INFO L226 Difference]: Without dead ends: 41101 [2019-12-07 18:54:52,081 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 138 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=154, Invalid=776, Unknown=0, NotChecked=0, Total=930 [2019-12-07 18:54:52,190 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41101 states. [2019-12-07 18:54:52,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41101 to 37741. [2019-12-07 18:54:52,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37741 states. [2019-12-07 18:54:52,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37741 states to 37741 states and 111345 transitions. [2019-12-07 18:54:52,629 INFO L78 Accepts]: Start accepts. Automaton has 37741 states and 111345 transitions. Word has length 72 [2019-12-07 18:54:52,630 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:54:52,630 INFO L462 AbstractCegarLoop]: Abstraction has 37741 states and 111345 transitions. [2019-12-07 18:54:52,630 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 18:54:52,630 INFO L276 IsEmpty]: Start isEmpty. Operand 37741 states and 111345 transitions. [2019-12-07 18:54:52,665 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:54:52,665 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:54:52,665 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:54:52,665 INFO L410 AbstractCegarLoop]: === Iteration 76 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:54:52,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:54:52,665 INFO L82 PathProgramCache]: Analyzing trace with hash 187048729, now seen corresponding path program 69 times [2019-12-07 18:54:52,666 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:54:52,666 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387888815] [2019-12-07 18:54:52,666 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:54:52,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:54:52,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:54:52,899 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387888815] [2019-12-07 18:54:52,900 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:54:52,900 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 18:54:52,900 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [601295702] [2019-12-07 18:54:52,900 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 18:54:52,900 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:54:52,900 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 18:54:52,900 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:54:52,900 INFO L87 Difference]: Start difference. First operand 37741 states and 111345 transitions. Second operand 16 states. [2019-12-07 18:54:55,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:54:55,337 INFO L93 Difference]: Finished difference Result 42138 states and 123025 transitions. [2019-12-07 18:54:55,337 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2019-12-07 18:54:55,337 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2019-12-07 18:54:55,337 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:54:55,384 INFO L225 Difference]: With dead ends: 42138 [2019-12-07 18:54:55,384 INFO L226 Difference]: Without dead ends: 41325 [2019-12-07 18:54:55,384 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 220 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=188, Invalid=1144, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 18:54:55,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41325 states. [2019-12-07 18:54:55,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41325 to 37909. [2019-12-07 18:54:55,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37909 states. [2019-12-07 18:54:55,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37909 states to 37909 states and 111818 transitions. [2019-12-07 18:54:55,950 INFO L78 Accepts]: Start accepts. Automaton has 37909 states and 111818 transitions. Word has length 72 [2019-12-07 18:54:55,950 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:54:55,951 INFO L462 AbstractCegarLoop]: Abstraction has 37909 states and 111818 transitions. [2019-12-07 18:54:55,951 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 18:54:55,951 INFO L276 IsEmpty]: Start isEmpty. Operand 37909 states and 111818 transitions. [2019-12-07 18:54:55,986 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:54:55,986 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:54:55,986 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:54:55,986 INFO L410 AbstractCegarLoop]: === Iteration 77 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:54:55,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:54:55,986 INFO L82 PathProgramCache]: Analyzing trace with hash 557319885, now seen corresponding path program 70 times [2019-12-07 18:54:55,987 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:54:55,987 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1637480628] [2019-12-07 18:54:55,987 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:54:56,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:54:57,555 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:54:57,555 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1637480628] [2019-12-07 18:54:57,555 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:54:57,555 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [30] imperfect sequences [] total 30 [2019-12-07 18:54:57,555 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1999207995] [2019-12-07 18:54:57,555 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2019-12-07 18:54:57,555 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:54:57,555 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2019-12-07 18:54:57,555 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=88, Invalid=904, Unknown=0, NotChecked=0, Total=992 [2019-12-07 18:54:57,556 INFO L87 Difference]: Start difference. First operand 37909 states and 111818 transitions. Second operand 32 states. [2019-12-07 18:55:22,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:22,332 INFO L93 Difference]: Finished difference Result 46420 states and 136758 transitions. [2019-12-07 18:55:22,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 119 states. [2019-12-07 18:55:22,333 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 72 [2019-12-07 18:55:22,333 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:22,390 INFO L225 Difference]: With dead ends: 46420 [2019-12-07 18:55:22,390 INFO L226 Difference]: Without dead ends: 45357 [2019-12-07 18:55:22,391 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 5 SyntacticMatches, 7 SemanticMatches, 124 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4829 ImplicationChecksByTransitivity, 7.9s TimeCoverageRelationStatistics Valid=1533, Invalid=14217, Unknown=0, NotChecked=0, Total=15750 [2019-12-07 18:55:22,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45357 states. [2019-12-07 18:55:22,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45357 to 41475. [2019-12-07 18:55:22,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41475 states. [2019-12-07 18:55:23,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41475 states to 41475 states and 122849 transitions. [2019-12-07 18:55:23,047 INFO L78 Accepts]: Start accepts. Automaton has 41475 states and 122849 transitions. Word has length 72 [2019-12-07 18:55:23,047 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:23,047 INFO L462 AbstractCegarLoop]: Abstraction has 41475 states and 122849 transitions. [2019-12-07 18:55:23,047 INFO L463 AbstractCegarLoop]: Interpolant automaton has 32 states. [2019-12-07 18:55:23,047 INFO L276 IsEmpty]: Start isEmpty. Operand 41475 states and 122849 transitions. [2019-12-07 18:55:23,086 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:55:23,086 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:23,086 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:23,086 INFO L410 AbstractCegarLoop]: === Iteration 78 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:23,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:23,086 INFO L82 PathProgramCache]: Analyzing trace with hash 664104829, now seen corresponding path program 71 times [2019-12-07 18:55:23,087 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:23,087 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1205199662] [2019-12-07 18:55:23,087 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:23,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:23,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:23,594 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1205199662] [2019-12-07 18:55:23,594 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:23,594 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 18:55:23,594 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [246472991] [2019-12-07 18:55:23,594 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 18:55:23,594 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:23,594 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 18:55:23,594 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=490, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:55:23,594 INFO L87 Difference]: Start difference. First operand 41475 states and 122849 transitions. Second operand 24 states. [2019-12-07 18:55:26,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:26,070 INFO L93 Difference]: Finished difference Result 53070 states and 156906 transitions. [2019-12-07 18:55:26,071 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-12-07 18:55:26,071 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 18:55:26,071 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:26,138 INFO L225 Difference]: With dead ends: 53070 [2019-12-07 18:55:26,138 INFO L226 Difference]: Without dead ends: 47294 [2019-12-07 18:55:26,138 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 556 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=294, Invalid=2256, Unknown=0, NotChecked=0, Total=2550 [2019-12-07 18:55:26,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47294 states. [2019-12-07 18:55:26,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47294 to 40719. [2019-12-07 18:55:26,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40719 states. [2019-12-07 18:55:26,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40719 states to 40719 states and 120075 transitions. [2019-12-07 18:55:26,770 INFO L78 Accepts]: Start accepts. Automaton has 40719 states and 120075 transitions. Word has length 72 [2019-12-07 18:55:26,770 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:26,770 INFO L462 AbstractCegarLoop]: Abstraction has 40719 states and 120075 transitions. [2019-12-07 18:55:26,770 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 18:55:26,770 INFO L276 IsEmpty]: Start isEmpty. Operand 40719 states and 120075 transitions. [2019-12-07 18:55:26,808 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:55:26,808 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:26,808 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:26,808 INFO L410 AbstractCegarLoop]: === Iteration 79 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:26,808 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:26,808 INFO L82 PathProgramCache]: Analyzing trace with hash -1895078607, now seen corresponding path program 72 times [2019-12-07 18:55:26,809 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:26,809 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1207589709] [2019-12-07 18:55:26,809 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:26,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:27,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:27,298 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1207589709] [2019-12-07 18:55:27,298 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:27,298 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 18:55:27,298 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [801498114] [2019-12-07 18:55:27,298 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 18:55:27,298 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:27,298 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 18:55:27,298 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=265, Unknown=0, NotChecked=0, Total=306 [2019-12-07 18:55:27,298 INFO L87 Difference]: Start difference. First operand 40719 states and 120075 transitions. Second operand 18 states. [2019-12-07 18:55:33,075 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:33,075 INFO L93 Difference]: Finished difference Result 44303 states and 129487 transitions. [2019-12-07 18:55:33,075 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-12-07 18:55:33,076 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 72 [2019-12-07 18:55:33,076 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:33,140 INFO L225 Difference]: With dead ends: 44303 [2019-12-07 18:55:33,140 INFO L226 Difference]: Without dead ends: 43804 [2019-12-07 18:55:33,141 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 319 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=259, Invalid=1547, Unknown=0, NotChecked=0, Total=1806 [2019-12-07 18:55:33,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43804 states. [2019-12-07 18:55:33,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43804 to 40505. [2019-12-07 18:55:33,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40505 states. [2019-12-07 18:55:33,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40505 states to 40505 states and 119458 transitions. [2019-12-07 18:55:33,730 INFO L78 Accepts]: Start accepts. Automaton has 40505 states and 119458 transitions. Word has length 72 [2019-12-07 18:55:33,730 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:33,730 INFO L462 AbstractCegarLoop]: Abstraction has 40505 states and 119458 transitions. [2019-12-07 18:55:33,730 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 18:55:33,730 INFO L276 IsEmpty]: Start isEmpty. Operand 40505 states and 119458 transitions. [2019-12-07 18:55:33,768 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:55:33,769 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:33,769 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:33,769 INFO L410 AbstractCegarLoop]: === Iteration 80 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:33,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:33,769 INFO L82 PathProgramCache]: Analyzing trace with hash -2115188337, now seen corresponding path program 73 times [2019-12-07 18:55:33,769 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:33,769 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [48044712] [2019-12-07 18:55:33,769 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:33,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:34,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:34,098 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [48044712] [2019-12-07 18:55:34,098 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:34,098 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 18:55:34,098 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [212271221] [2019-12-07 18:55:34,099 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 18:55:34,099 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:34,099 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 18:55:34,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=268, Unknown=0, NotChecked=0, Total=306 [2019-12-07 18:55:34,099 INFO L87 Difference]: Start difference. First operand 40505 states and 119458 transitions. Second operand 18 states. [2019-12-07 18:55:36,677 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:36,677 INFO L93 Difference]: Finished difference Result 43238 states and 126305 transitions. [2019-12-07 18:55:36,677 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-12-07 18:55:36,678 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 72 [2019-12-07 18:55:36,678 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:36,727 INFO L225 Difference]: With dead ends: 43238 [2019-12-07 18:55:36,727 INFO L226 Difference]: Without dead ends: 42961 [2019-12-07 18:55:36,728 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 340 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=235, Invalid=1571, Unknown=0, NotChecked=0, Total=1806 [2019-12-07 18:55:36,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42961 states. [2019-12-07 18:55:37,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42961 to 40555. [2019-12-07 18:55:37,252 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40555 states. [2019-12-07 18:55:37,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40555 states to 40555 states and 119576 transitions. [2019-12-07 18:55:37,315 INFO L78 Accepts]: Start accepts. Automaton has 40555 states and 119576 transitions. Word has length 72 [2019-12-07 18:55:37,315 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:37,315 INFO L462 AbstractCegarLoop]: Abstraction has 40555 states and 119576 transitions. [2019-12-07 18:55:37,315 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 18:55:37,315 INFO L276 IsEmpty]: Start isEmpty. Operand 40555 states and 119576 transitions. [2019-12-07 18:55:37,352 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:55:37,352 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:37,353 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:37,353 INFO L410 AbstractCegarLoop]: === Iteration 81 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:37,353 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:37,353 INFO L82 PathProgramCache]: Analyzing trace with hash -1868459225, now seen corresponding path program 74 times [2019-12-07 18:55:37,353 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:37,353 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952678804] [2019-12-07 18:55:37,353 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:37,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:37,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:37,572 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952678804] [2019-12-07 18:55:37,572 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:37,572 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 18:55:37,572 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2023803260] [2019-12-07 18:55:37,572 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 18:55:37,572 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:37,572 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 18:55:37,572 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=179, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:55:37,572 INFO L87 Difference]: Start difference. First operand 40555 states and 119576 transitions. Second operand 15 states. [2019-12-07 18:55:38,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:38,842 INFO L93 Difference]: Finished difference Result 44353 states and 129260 transitions. [2019-12-07 18:55:38,842 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2019-12-07 18:55:38,842 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 72 [2019-12-07 18:55:38,842 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:38,889 INFO L225 Difference]: With dead ends: 44353 [2019-12-07 18:55:38,889 INFO L226 Difference]: Without dead ends: 44021 [2019-12-07 18:55:38,889 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 260 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=187, Invalid=1145, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 18:55:38,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44021 states. [2019-12-07 18:55:39,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44021 to 40565. [2019-12-07 18:55:39,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40565 states. [2019-12-07 18:55:39,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40565 states to 40565 states and 119590 transitions. [2019-12-07 18:55:39,476 INFO L78 Accepts]: Start accepts. Automaton has 40565 states and 119590 transitions. Word has length 72 [2019-12-07 18:55:39,477 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:39,477 INFO L462 AbstractCegarLoop]: Abstraction has 40565 states and 119590 transitions. [2019-12-07 18:55:39,477 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 18:55:39,477 INFO L276 IsEmpty]: Start isEmpty. Operand 40565 states and 119590 transitions. [2019-12-07 18:55:39,514 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:55:39,514 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:39,514 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:39,515 INFO L410 AbstractCegarLoop]: === Iteration 82 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:39,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:39,515 INFO L82 PathProgramCache]: Analyzing trace with hash -1511141711, now seen corresponding path program 75 times [2019-12-07 18:55:39,515 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:39,515 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [368655415] [2019-12-07 18:55:39,515 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:39,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:39,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:39,663 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [368655415] [2019-12-07 18:55:39,663 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:39,664 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 18:55:39,664 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [818428990] [2019-12-07 18:55:39,664 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 18:55:39,664 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:39,664 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 18:55:39,664 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:55:39,664 INFO L87 Difference]: Start difference. First operand 40565 states and 119590 transitions. Second operand 12 states. [2019-12-07 18:55:40,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:40,100 INFO L93 Difference]: Finished difference Result 45336 states and 133456 transitions. [2019-12-07 18:55:40,100 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 18:55:40,100 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 72 [2019-12-07 18:55:40,100 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:40,149 INFO L225 Difference]: With dead ends: 45336 [2019-12-07 18:55:40,149 INFO L226 Difference]: Without dead ends: 43131 [2019-12-07 18:55:40,149 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=83, Invalid=379, Unknown=0, NotChecked=0, Total=462 [2019-12-07 18:55:40,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43131 states. [2019-12-07 18:55:40,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43131 to 39520. [2019-12-07 18:55:40,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39520 states. [2019-12-07 18:55:40,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39520 states to 39520 states and 116309 transitions. [2019-12-07 18:55:40,714 INFO L78 Accepts]: Start accepts. Automaton has 39520 states and 116309 transitions. Word has length 72 [2019-12-07 18:55:40,714 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:40,714 INFO L462 AbstractCegarLoop]: Abstraction has 39520 states and 116309 transitions. [2019-12-07 18:55:40,714 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 18:55:40,714 INFO L276 IsEmpty]: Start isEmpty. Operand 39520 states and 116309 transitions. [2019-12-07 18:55:40,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:55:40,750 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:40,750 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:40,750 INFO L410 AbstractCegarLoop]: === Iteration 83 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:40,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:40,750 INFO L82 PathProgramCache]: Analyzing trace with hash 1552027135, now seen corresponding path program 76 times [2019-12-07 18:55:40,750 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:40,750 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [738548457] [2019-12-07 18:55:40,751 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:40,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:41,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:41,053 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [738548457] [2019-12-07 18:55:41,053 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:41,053 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 18:55:41,053 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1259707322] [2019-12-07 18:55:41,053 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 18:55:41,053 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:41,054 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 18:55:41,054 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:55:41,054 INFO L87 Difference]: Start difference. First operand 39520 states and 116309 transitions. Second operand 16 states. [2019-12-07 18:55:42,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:42,540 INFO L93 Difference]: Finished difference Result 42893 states and 125062 transitions. [2019-12-07 18:55:42,540 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-12-07 18:55:42,540 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2019-12-07 18:55:42,540 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:42,590 INFO L225 Difference]: With dead ends: 42893 [2019-12-07 18:55:42,590 INFO L226 Difference]: Without dead ends: 42845 [2019-12-07 18:55:42,590 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 205 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=168, Invalid=1022, Unknown=0, NotChecked=0, Total=1190 [2019-12-07 18:55:42,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42845 states. [2019-12-07 18:55:43,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42845 to 39493. [2019-12-07 18:55:43,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39493 states. [2019-12-07 18:55:43,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39493 states to 39493 states and 116271 transitions. [2019-12-07 18:55:43,161 INFO L78 Accepts]: Start accepts. Automaton has 39493 states and 116271 transitions. Word has length 72 [2019-12-07 18:55:43,161 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:43,161 INFO L462 AbstractCegarLoop]: Abstraction has 39493 states and 116271 transitions. [2019-12-07 18:55:43,161 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 18:55:43,161 INFO L276 IsEmpty]: Start isEmpty. Operand 39493 states and 116271 transitions. [2019-12-07 18:55:43,198 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:55:43,198 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:43,198 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:43,198 INFO L410 AbstractCegarLoop]: === Iteration 84 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:43,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:43,198 INFO L82 PathProgramCache]: Analyzing trace with hash -1917238199, now seen corresponding path program 77 times [2019-12-07 18:55:43,198 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:43,199 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517799662] [2019-12-07 18:55:43,199 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:43,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:43,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:43,545 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1517799662] [2019-12-07 18:55:43,545 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:43,545 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2019-12-07 18:55:43,545 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1989886599] [2019-12-07 18:55:43,545 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 18:55:43,545 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:43,545 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 18:55:43,546 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=367, Unknown=0, NotChecked=0, Total=420 [2019-12-07 18:55:43,546 INFO L87 Difference]: Start difference. First operand 39493 states and 116271 transitions. Second operand 21 states. [2019-12-07 18:55:45,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:45,243 INFO L93 Difference]: Finished difference Result 58040 states and 169760 transitions. [2019-12-07 18:55:45,243 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2019-12-07 18:55:45,243 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 72 [2019-12-07 18:55:45,243 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:45,316 INFO L225 Difference]: With dead ends: 58040 [2019-12-07 18:55:45,316 INFO L226 Difference]: Without dead ends: 56681 [2019-12-07 18:55:45,316 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 417 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=198, Invalid=1608, Unknown=0, NotChecked=0, Total=1806 [2019-12-07 18:55:45,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56681 states. [2019-12-07 18:55:45,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56681 to 39560. [2019-12-07 18:55:45,915 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39560 states. [2019-12-07 18:55:45,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39560 states to 39560 states and 116424 transitions. [2019-12-07 18:55:45,976 INFO L78 Accepts]: Start accepts. Automaton has 39560 states and 116424 transitions. Word has length 72 [2019-12-07 18:55:45,976 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:45,976 INFO L462 AbstractCegarLoop]: Abstraction has 39560 states and 116424 transitions. [2019-12-07 18:55:45,976 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 18:55:45,976 INFO L276 IsEmpty]: Start isEmpty. Operand 39560 states and 116424 transitions. [2019-12-07 18:55:46,013 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:55:46,013 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:46,013 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:46,013 INFO L410 AbstractCegarLoop]: === Iteration 85 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:46,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:46,014 INFO L82 PathProgramCache]: Analyzing trace with hash -1448284485, now seen corresponding path program 78 times [2019-12-07 18:55:46,014 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:46,014 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1939890996] [2019-12-07 18:55:46,014 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:46,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:46,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:46,492 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1939890996] [2019-12-07 18:55:46,492 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:46,492 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 18:55:46,492 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1214215619] [2019-12-07 18:55:46,492 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 18:55:46,492 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:46,492 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 18:55:46,492 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=492, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:55:46,492 INFO L87 Difference]: Start difference. First operand 39560 states and 116424 transitions. Second operand 24 states. [2019-12-07 18:55:49,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:49,232 INFO L93 Difference]: Finished difference Result 55687 states and 162880 transitions. [2019-12-07 18:55:49,232 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2019-12-07 18:55:49,232 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 18:55:49,232 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:49,278 INFO L225 Difference]: With dead ends: 55687 [2019-12-07 18:55:49,279 INFO L226 Difference]: Without dead ends: 47091 [2019-12-07 18:55:49,279 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 0 SyntacticMatches, 3 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 898 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=384, Invalid=3276, Unknown=0, NotChecked=0, Total=3660 [2019-12-07 18:55:49,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47091 states. [2019-12-07 18:55:49,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47091 to 37259. [2019-12-07 18:55:49,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37259 states. [2019-12-07 18:55:49,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37259 states to 37259 states and 110203 transitions. [2019-12-07 18:55:49,858 INFO L78 Accepts]: Start accepts. Automaton has 37259 states and 110203 transitions. Word has length 72 [2019-12-07 18:55:49,858 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:49,858 INFO L462 AbstractCegarLoop]: Abstraction has 37259 states and 110203 transitions. [2019-12-07 18:55:49,858 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 18:55:49,858 INFO L276 IsEmpty]: Start isEmpty. Operand 37259 states and 110203 transitions. [2019-12-07 18:55:49,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:55:49,893 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:49,893 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:49,893 INFO L410 AbstractCegarLoop]: === Iteration 86 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:49,893 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:49,894 INFO L82 PathProgramCache]: Analyzing trace with hash 1732953689, now seen corresponding path program 79 times [2019-12-07 18:55:49,894 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:49,894 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [990759940] [2019-12-07 18:55:49,894 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:49,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:50,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:50,189 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [990759940] [2019-12-07 18:55:50,190 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:50,190 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 18:55:50,190 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1183933455] [2019-12-07 18:55:50,190 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 18:55:50,190 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:50,190 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 18:55:50,190 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=267, Unknown=0, NotChecked=0, Total=306 [2019-12-07 18:55:50,190 INFO L87 Difference]: Start difference. First operand 37259 states and 110203 transitions. Second operand 18 states. [2019-12-07 18:55:51,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:51,782 INFO L93 Difference]: Finished difference Result 40234 states and 117404 transitions. [2019-12-07 18:55:51,782 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-12-07 18:55:51,782 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 72 [2019-12-07 18:55:51,782 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:51,828 INFO L225 Difference]: With dead ends: 40234 [2019-12-07 18:55:51,828 INFO L226 Difference]: Without dead ends: 39782 [2019-12-07 18:55:51,828 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 274 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=206, Invalid=1276, Unknown=0, NotChecked=0, Total=1482 [2019-12-07 18:55:51,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39782 states. [2019-12-07 18:55:52,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39782 to 37337. [2019-12-07 18:55:52,307 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37337 states. [2019-12-07 18:55:52,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37337 states to 37337 states and 110328 transitions. [2019-12-07 18:55:52,367 INFO L78 Accepts]: Start accepts. Automaton has 37337 states and 110328 transitions. Word has length 72 [2019-12-07 18:55:52,367 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:52,367 INFO L462 AbstractCegarLoop]: Abstraction has 37337 states and 110328 transitions. [2019-12-07 18:55:52,367 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 18:55:52,367 INFO L276 IsEmpty]: Start isEmpty. Operand 37337 states and 110328 transitions. [2019-12-07 18:55:52,402 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:55:52,402 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:52,403 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:52,403 INFO L410 AbstractCegarLoop]: === Iteration 87 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:52,403 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:52,403 INFO L82 PathProgramCache]: Analyzing trace with hash 858472753, now seen corresponding path program 80 times [2019-12-07 18:55:52,403 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:52,403 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1980338540] [2019-12-07 18:55:52,403 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:52,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:52,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:52,875 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1980338540] [2019-12-07 18:55:52,876 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:52,876 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2019-12-07 18:55:52,876 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [320667504] [2019-12-07 18:55:52,876 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-12-07 18:55:52,876 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:52,876 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 18:55:52,876 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=537, Unknown=0, NotChecked=0, Total=600 [2019-12-07 18:55:52,876 INFO L87 Difference]: Start difference. First operand 37337 states and 110328 transitions. Second operand 25 states. [2019-12-07 18:55:57,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:57,886 INFO L93 Difference]: Finished difference Result 44126 states and 128196 transitions. [2019-12-07 18:55:57,887 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2019-12-07 18:55:57,887 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 72 [2019-12-07 18:55:57,887 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:57,948 INFO L225 Difference]: With dead ends: 44126 [2019-12-07 18:55:57,948 INFO L226 Difference]: Without dead ends: 43644 [2019-12-07 18:55:57,949 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 837 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=374, Invalid=3166, Unknown=0, NotChecked=0, Total=3540 [2019-12-07 18:55:58,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43644 states. [2019-12-07 18:55:58,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43644 to 37261. [2019-12-07 18:55:58,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37261 states. [2019-12-07 18:55:58,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37261 states to 37261 states and 110206 transitions. [2019-12-07 18:55:58,551 INFO L78 Accepts]: Start accepts. Automaton has 37261 states and 110206 transitions. Word has length 72 [2019-12-07 18:55:58,551 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:58,551 INFO L462 AbstractCegarLoop]: Abstraction has 37261 states and 110206 transitions. [2019-12-07 18:55:58,551 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-12-07 18:55:58,551 INFO L276 IsEmpty]: Start isEmpty. Operand 37261 states and 110206 transitions. [2019-12-07 18:55:58,587 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:55:58,587 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:58,587 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:58,587 INFO L410 AbstractCegarLoop]: === Iteration 88 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:58,587 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:58,587 INFO L82 PathProgramCache]: Analyzing trace with hash 401131077, now seen corresponding path program 81 times [2019-12-07 18:55:58,587 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:58,588 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1496489073] [2019-12-07 18:55:58,588 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:58,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:58,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:58,814 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1496489073] [2019-12-07 18:55:58,814 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:58,814 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 18:55:58,814 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1514998102] [2019-12-07 18:55:58,814 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 18:55:58,814 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:58,815 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 18:55:58,815 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=235, Unknown=0, NotChecked=0, Total=272 [2019-12-07 18:55:58,815 INFO L87 Difference]: Start difference. First operand 37261 states and 110206 transitions. Second operand 17 states. [2019-12-07 18:56:03,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:03,656 INFO L93 Difference]: Finished difference Result 45076 states and 131859 transitions. [2019-12-07 18:56:03,657 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2019-12-07 18:56:03,657 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 72 [2019-12-07 18:56:03,657 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:03,702 INFO L225 Difference]: With dead ends: 45076 [2019-12-07 18:56:03,703 INFO L226 Difference]: Without dead ends: 41539 [2019-12-07 18:56:03,703 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 505 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=323, Invalid=1933, Unknown=0, NotChecked=0, Total=2256 [2019-12-07 18:56:03,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41539 states. [2019-12-07 18:56:04,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41539 to 37767. [2019-12-07 18:56:04,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37767 states. [2019-12-07 18:56:04,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37767 states to 37767 states and 111511 transitions. [2019-12-07 18:56:04,247 INFO L78 Accepts]: Start accepts. Automaton has 37767 states and 111511 transitions. Word has length 72 [2019-12-07 18:56:04,247 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:04,247 INFO L462 AbstractCegarLoop]: Abstraction has 37767 states and 111511 transitions. [2019-12-07 18:56:04,247 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 18:56:04,247 INFO L276 IsEmpty]: Start isEmpty. Operand 37767 states and 111511 transitions. [2019-12-07 18:56:04,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:56:04,282 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:04,282 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:04,282 INFO L410 AbstractCegarLoop]: === Iteration 89 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:04,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:04,283 INFO L82 PathProgramCache]: Analyzing trace with hash -473349859, now seen corresponding path program 82 times [2019-12-07 18:56:04,283 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:04,283 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1753763330] [2019-12-07 18:56:04,283 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:04,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:04,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:04,689 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1753763330] [2019-12-07 18:56:04,689 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:04,689 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [20] imperfect sequences [] total 20 [2019-12-07 18:56:04,689 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [770115744] [2019-12-07 18:56:04,689 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-12-07 18:56:04,689 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:04,689 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-12-07 18:56:04,689 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=406, Unknown=0, NotChecked=0, Total=462 [2019-12-07 18:56:04,689 INFO L87 Difference]: Start difference. First operand 37767 states and 111511 transitions. Second operand 22 states. [2019-12-07 18:56:06,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:06,555 INFO L93 Difference]: Finished difference Result 44469 states and 129248 transitions. [2019-12-07 18:56:06,556 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2019-12-07 18:56:06,556 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 72 [2019-12-07 18:56:06,556 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:06,606 INFO L225 Difference]: With dead ends: 44469 [2019-12-07 18:56:06,606 INFO L226 Difference]: Without dead ends: 44401 [2019-12-07 18:56:06,606 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 384 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=223, Invalid=1583, Unknown=0, NotChecked=0, Total=1806 [2019-12-07 18:56:06,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44401 states. [2019-12-07 18:56:07,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44401 to 37725. [2019-12-07 18:56:07,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37725 states. [2019-12-07 18:56:07,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37725 states to 37725 states and 111449 transitions. [2019-12-07 18:56:07,196 INFO L78 Accepts]: Start accepts. Automaton has 37725 states and 111449 transitions. Word has length 72 [2019-12-07 18:56:07,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:07,196 INFO L462 AbstractCegarLoop]: Abstraction has 37725 states and 111449 transitions. [2019-12-07 18:56:07,196 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-12-07 18:56:07,196 INFO L276 IsEmpty]: Start isEmpty. Operand 37725 states and 111449 transitions. [2019-12-07 18:56:07,231 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:56:07,232 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:07,232 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:07,232 INFO L410 AbstractCegarLoop]: === Iteration 90 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:07,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:07,232 INFO L82 PathProgramCache]: Analyzing trace with hash -339609475, now seen corresponding path program 83 times [2019-12-07 18:56:07,232 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:07,232 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [778237981] [2019-12-07 18:56:07,232 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:07,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:07,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:07,588 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [778237981] [2019-12-07 18:56:07,588 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:07,588 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2019-12-07 18:56:07,589 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [808754344] [2019-12-07 18:56:07,589 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 18:56:07,589 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:07,589 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 18:56:07,589 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=368, Unknown=0, NotChecked=0, Total=420 [2019-12-07 18:56:07,589 INFO L87 Difference]: Start difference. First operand 37725 states and 111449 transitions. Second operand 21 states. [2019-12-07 18:56:09,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:09,464 INFO L93 Difference]: Finished difference Result 56182 states and 164635 transitions. [2019-12-07 18:56:09,464 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2019-12-07 18:56:09,464 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 72 [2019-12-07 18:56:09,464 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:09,534 INFO L225 Difference]: With dead ends: 56182 [2019-12-07 18:56:09,534 INFO L226 Difference]: Without dead ends: 54823 [2019-12-07 18:56:09,534 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 553 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=254, Invalid=2098, Unknown=0, NotChecked=0, Total=2352 [2019-12-07 18:56:09,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54823 states. [2019-12-07 18:56:10,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54823 to 38093. [2019-12-07 18:56:10,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38093 states. [2019-12-07 18:56:10,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38093 states to 38093 states and 112309 transitions. [2019-12-07 18:56:10,182 INFO L78 Accepts]: Start accepts. Automaton has 38093 states and 112309 transitions. Word has length 72 [2019-12-07 18:56:10,183 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:10,183 INFO L462 AbstractCegarLoop]: Abstraction has 38093 states and 112309 transitions. [2019-12-07 18:56:10,183 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 18:56:10,183 INFO L276 IsEmpty]: Start isEmpty. Operand 38093 states and 112309 transitions. [2019-12-07 18:56:10,219 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:56:10,219 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:10,219 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:10,219 INFO L410 AbstractCegarLoop]: === Iteration 91 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:10,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:10,220 INFO L82 PathProgramCache]: Analyzing trace with hash 129344239, now seen corresponding path program 84 times [2019-12-07 18:56:10,220 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:10,220 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290493235] [2019-12-07 18:56:10,220 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:10,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:10,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:10,620 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1290493235] [2019-12-07 18:56:10,621 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:10,621 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2019-12-07 18:56:10,621 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953839090] [2019-12-07 18:56:10,621 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 18:56:10,621 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:10,621 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 18:56:10,621 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=300, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:56:10,621 INFO L87 Difference]: Start difference. First operand 38093 states and 112309 transitions. Second operand 19 states. [2019-12-07 18:56:11,413 WARN L192 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 33 DAG size of output: 30 [2019-12-07 18:56:11,799 WARN L192 SmtUtils]: Spent 153.00 ms on a formula simplification. DAG size of input: 39 DAG size of output: 36 [2019-12-07 18:56:12,892 WARN L192 SmtUtils]: Spent 143.00 ms on a formula simplification. DAG size of input: 35 DAG size of output: 32 [2019-12-07 18:56:14,061 WARN L192 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 37 DAG size of output: 34 [2019-12-07 18:56:16,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:16,133 INFO L93 Difference]: Finished difference Result 43883 states and 126749 transitions. [2019-12-07 18:56:16,133 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2019-12-07 18:56:16,133 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 72 [2019-12-07 18:56:16,133 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:16,181 INFO L225 Difference]: With dead ends: 43883 [2019-12-07 18:56:16,182 INFO L226 Difference]: Without dead ends: 43423 [2019-12-07 18:56:16,182 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 802 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=447, Invalid=2975, Unknown=0, NotChecked=0, Total=3422 [2019-12-07 18:56:16,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43423 states. [2019-12-07 18:56:16,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43423 to 37820. [2019-12-07 18:56:16,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37820 states. [2019-12-07 18:56:16,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37820 states to 37820 states and 111636 transitions. [2019-12-07 18:56:16,750 INFO L78 Accepts]: Start accepts. Automaton has 37820 states and 111636 transitions. Word has length 72 [2019-12-07 18:56:16,750 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:16,750 INFO L462 AbstractCegarLoop]: Abstraction has 37820 states and 111636 transitions. [2019-12-07 18:56:16,750 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 18:56:16,750 INFO L276 IsEmpty]: Start isEmpty. Operand 37820 states and 111636 transitions. [2019-12-07 18:56:16,786 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:56:16,786 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:16,787 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:16,787 INFO L410 AbstractCegarLoop]: === Iteration 92 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:16,787 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:16,787 INFO L82 PathProgramCache]: Analyzing trace with hash -1858865819, now seen corresponding path program 85 times [2019-12-07 18:56:16,787 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:16,787 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1883190106] [2019-12-07 18:56:16,787 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:16,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:17,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:17,417 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1883190106] [2019-12-07 18:56:17,417 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:17,417 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [24] imperfect sequences [] total 24 [2019-12-07 18:56:17,417 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [296616366] [2019-12-07 18:56:17,418 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-12-07 18:56:17,418 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:17,418 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-12-07 18:56:17,418 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=584, Unknown=0, NotChecked=0, Total=650 [2019-12-07 18:56:17,418 INFO L87 Difference]: Start difference. First operand 37820 states and 111636 transitions. Second operand 26 states. [2019-12-07 18:56:21,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:21,579 INFO L93 Difference]: Finished difference Result 44066 states and 128130 transitions. [2019-12-07 18:56:21,580 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2019-12-07 18:56:21,580 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 72 [2019-12-07 18:56:21,580 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:21,640 INFO L225 Difference]: With dead ends: 44066 [2019-12-07 18:56:21,641 INFO L226 Difference]: Without dead ends: 43998 [2019-12-07 18:56:21,641 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 534 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=251, Invalid=2101, Unknown=0, NotChecked=0, Total=2352 [2019-12-07 18:56:21,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43998 states. [2019-12-07 18:56:22,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43998 to 37764. [2019-12-07 18:56:22,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37764 states. [2019-12-07 18:56:22,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37764 states to 37764 states and 111543 transitions. [2019-12-07 18:56:22,224 INFO L78 Accepts]: Start accepts. Automaton has 37764 states and 111543 transitions. Word has length 72 [2019-12-07 18:56:22,224 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:22,224 INFO L462 AbstractCegarLoop]: Abstraction has 37764 states and 111543 transitions. [2019-12-07 18:56:22,224 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-12-07 18:56:22,224 INFO L276 IsEmpty]: Start isEmpty. Operand 37764 states and 111543 transitions. [2019-12-07 18:56:22,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:56:22,260 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:22,260 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:22,260 INFO L410 AbstractCegarLoop]: === Iteration 93 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:22,260 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:22,260 INFO L82 PathProgramCache]: Analyzing trace with hash -558986371, now seen corresponding path program 86 times [2019-12-07 18:56:22,260 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:22,260 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [262273845] [2019-12-07 18:56:22,261 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:22,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:22,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:22,496 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [262273845] [2019-12-07 18:56:22,496 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:22,496 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 18:56:22,496 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1562823074] [2019-12-07 18:56:22,497 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 18:56:22,497 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:22,497 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 18:56:22,497 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=178, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:56:22,497 INFO L87 Difference]: Start difference. First operand 37764 states and 111543 transitions. Second operand 15 states. [2019-12-07 18:56:23,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:23,580 INFO L93 Difference]: Finished difference Result 49276 states and 144936 transitions. [2019-12-07 18:56:23,580 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 18:56:23,581 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 72 [2019-12-07 18:56:23,581 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:23,635 INFO L225 Difference]: With dead ends: 49276 [2019-12-07 18:56:23,635 INFO L226 Difference]: Without dead ends: 46626 [2019-12-07 18:56:23,636 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 92 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=107, Invalid=543, Unknown=0, NotChecked=0, Total=650 [2019-12-07 18:56:23,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46626 states. [2019-12-07 18:56:24,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46626 to 38126. [2019-12-07 18:56:24,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38126 states. [2019-12-07 18:56:24,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38126 states to 38126 states and 112384 transitions. [2019-12-07 18:56:24,199 INFO L78 Accepts]: Start accepts. Automaton has 38126 states and 112384 transitions. Word has length 72 [2019-12-07 18:56:24,199 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:24,199 INFO L462 AbstractCegarLoop]: Abstraction has 38126 states and 112384 transitions. [2019-12-07 18:56:24,199 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 18:56:24,199 INFO L276 IsEmpty]: Start isEmpty. Operand 38126 states and 112384 transitions. [2019-12-07 18:56:24,234 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:56:24,234 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:24,234 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:24,235 INFO L410 AbstractCegarLoop]: === Iteration 94 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:24,235 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:24,235 INFO L82 PathProgramCache]: Analyzing trace with hash -90032657, now seen corresponding path program 87 times [2019-12-07 18:56:24,235 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:24,235 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [652366526] [2019-12-07 18:56:24,235 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:24,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:24,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:24,603 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [652366526] [2019-12-07 18:56:24,603 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:24,603 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2019-12-07 18:56:24,603 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [78098647] [2019-12-07 18:56:24,604 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 18:56:24,604 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:24,604 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 18:56:24,604 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=300, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:56:24,604 INFO L87 Difference]: Start difference. First operand 38126 states and 112384 transitions. Second operand 19 states. [2019-12-07 18:56:27,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:27,280 INFO L93 Difference]: Finished difference Result 42721 states and 124121 transitions. [2019-12-07 18:56:27,280 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-12-07 18:56:27,281 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 72 [2019-12-07 18:56:27,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:27,329 INFO L225 Difference]: With dead ends: 42721 [2019-12-07 18:56:27,329 INFO L226 Difference]: Without dead ends: 42397 [2019-12-07 18:56:27,329 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 432 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=281, Invalid=1881, Unknown=0, NotChecked=0, Total=2162 [2019-12-07 18:56:27,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42397 states. [2019-12-07 18:56:27,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42397 to 37800. [2019-12-07 18:56:27,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37800 states. [2019-12-07 18:56:27,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37800 states to 37800 states and 111589 transitions. [2019-12-07 18:56:27,909 INFO L78 Accepts]: Start accepts. Automaton has 37800 states and 111589 transitions. Word has length 72 [2019-12-07 18:56:27,909 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:27,909 INFO L462 AbstractCegarLoop]: Abstraction has 37800 states and 111589 transitions. [2019-12-07 18:56:27,909 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 18:56:27,909 INFO L276 IsEmpty]: Start isEmpty. Operand 37800 states and 111589 transitions. [2019-12-07 18:56:27,944 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:56:27,944 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:27,945 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:27,945 INFO L410 AbstractCegarLoop]: === Iteration 95 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:27,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:27,945 INFO L82 PathProgramCache]: Analyzing trace with hash -846444265, now seen corresponding path program 88 times [2019-12-07 18:56:27,945 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:27,945 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1454346718] [2019-12-07 18:56:27,945 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:27,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:28,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:28,207 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1454346718] [2019-12-07 18:56:28,207 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:28,207 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 18:56:28,207 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1485379123] [2019-12-07 18:56:28,207 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 18:56:28,208 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:28,208 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 18:56:28,208 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:56:28,208 INFO L87 Difference]: Start difference. First operand 37800 states and 111589 transitions. Second operand 16 states. [2019-12-07 18:56:29,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:29,444 INFO L93 Difference]: Finished difference Result 45965 states and 135164 transitions. [2019-12-07 18:56:29,444 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-12-07 18:56:29,444 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2019-12-07 18:56:29,444 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:29,495 INFO L225 Difference]: With dead ends: 45965 [2019-12-07 18:56:29,495 INFO L226 Difference]: Without dead ends: 44667 [2019-12-07 18:56:29,495 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 190 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=184, Invalid=938, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 18:56:29,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44667 states. [2019-12-07 18:56:29,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44667 to 37779. [2019-12-07 18:56:29,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37779 states. [2019-12-07 18:56:30,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37779 states to 37779 states and 111542 transitions. [2019-12-07 18:56:30,034 INFO L78 Accepts]: Start accepts. Automaton has 37779 states and 111542 transitions. Word has length 72 [2019-12-07 18:56:30,034 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:30,034 INFO L462 AbstractCegarLoop]: Abstraction has 37779 states and 111542 transitions. [2019-12-07 18:56:30,034 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 18:56:30,034 INFO L276 IsEmpty]: Start isEmpty. Operand 37779 states and 111542 transitions. [2019-12-07 18:56:30,068 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:56:30,068 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:30,068 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:30,069 INFO L410 AbstractCegarLoop]: === Iteration 96 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:30,069 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:30,069 INFO L82 PathProgramCache]: Analyzing trace with hash -2078242715, now seen corresponding path program 89 times [2019-12-07 18:56:30,069 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:30,069 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [216965826] [2019-12-07 18:56:30,069 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:30,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:30,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:30,972 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [216965826] [2019-12-07 18:56:30,972 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:30,972 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [26] imperfect sequences [] total 26 [2019-12-07 18:56:30,972 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1539935418] [2019-12-07 18:56:30,972 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2019-12-07 18:56:30,972 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:30,972 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2019-12-07 18:56:30,972 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=70, Invalid=686, Unknown=0, NotChecked=0, Total=756 [2019-12-07 18:56:30,973 INFO L87 Difference]: Start difference. First operand 37779 states and 111542 transitions. Second operand 28 states. [2019-12-07 18:56:33,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:33,653 INFO L93 Difference]: Finished difference Result 41327 states and 120505 transitions. [2019-12-07 18:56:33,653 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-12-07 18:56:33,653 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 72 [2019-12-07 18:56:33,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:33,700 INFO L225 Difference]: With dead ends: 41327 [2019-12-07 18:56:33,700 INFO L226 Difference]: Without dead ends: 41003 [2019-12-07 18:56:33,700 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 550 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=347, Invalid=2623, Unknown=0, NotChecked=0, Total=2970 [2019-12-07 18:56:33,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41003 states. [2019-12-07 18:56:34,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41003 to 37430. [2019-12-07 18:56:34,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37430 states. [2019-12-07 18:56:34,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37430 states to 37430 states and 110608 transitions. [2019-12-07 18:56:34,254 INFO L78 Accepts]: Start accepts. Automaton has 37430 states and 110608 transitions. Word has length 72 [2019-12-07 18:56:34,254 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:34,254 INFO L462 AbstractCegarLoop]: Abstraction has 37430 states and 110608 transitions. [2019-12-07 18:56:34,254 INFO L463 AbstractCegarLoop]: Interpolant automaton has 28 states. [2019-12-07 18:56:34,254 INFO L276 IsEmpty]: Start isEmpty. Operand 37430 states and 110608 transitions. [2019-12-07 18:56:34,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 18:56:34,289 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:34,289 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:34,289 INFO L410 AbstractCegarLoop]: === Iteration 97 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:34,289 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:34,289 INFO L82 PathProgramCache]: Analyzing trace with hash 959991305, now seen corresponding path program 90 times [2019-12-07 18:56:34,289 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:34,289 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1978920567] [2019-12-07 18:56:34,290 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:34,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:56:34,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:56:34,382 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:56:34,382 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 18:56:34,385 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1160] [1160] ULTIMATE.startENTRY-->L838: Formula: (let ((.cse1 (store |v_#valid_73| 0 0))) (let ((.cse0 (store .cse1 |v_~#x~0.base_244| 1))) (and (= v_~__unbuffered_cnt~0_104 0) (= 0 v_~x$r_buff0_thd3~0_278) (= 0 v_~__unbuffered_p2_EAX$r_buff0_thd1~0_8) (= v_~main$tmp_guard1~0_31 0) (= |v_#NULL.offset_6| 0) (= 0 v_~__unbuffered_p2_EAX$w_buff0~0_7) (= (select (select |v_#memory_int_395| |v_~#x~0.base_244|) |v_~#x~0.offset_244|) 0) (= v_~x$r_buff1_thd0~0_77 0) (= 0 v_~__unbuffered_p2_EAX$r_buff0_thd2~0_8) (= 0 v_~__unbuffered_p2_EAX$w_buff0_used~0_7) (= 0 v_~__unbuffered_p2_EAX$w_buff1~0_7) (= 0 v_~x$w_buff1~0_137) (= 0 |v_~#x~0.offset_244|) (= (select .cse0 |v_ULTIMATE.start_main_~#t2461~0.base_22|) 0) (= 0 v_~x$read_delayed_var~0.base_7) (= 0 v_~__unbuffered_p0_EAX~0_70) (= v_~x$r_buff1_thd2~0_55 0) (= 0 v_~__unbuffered_p2_EAX$r_buff0_thd3~0_6) (= v_~weak$$choice2~0_140 0) (= 0 v_~x$read_delayed~0_8) (= v_~x$mem_tmp~0_82 0) (= v_~__unbuffered_p2_EBX~0_33 0) (= 0 v_~x$r_buff0_thd0~0_89) (= |v_#length_36| (store (store |v_#length_37| |v_~#x~0.base_244| 4) |v_ULTIMATE.start_main_~#t2461~0.base_22| 4)) (= 0 v_~x$w_buff1_used~0_483) (= 0 v_~__unbuffered_p2_EAX$mem_tmp~0_8) (= v_~main$tmp_guard0~0_33 0) (= 0 v_~x$w_buff0~0_164) (= 0 v_~x$r_buff1_thd3~0_181) (= |v_#valid_71| (store .cse0 |v_ULTIMATE.start_main_~#t2461~0.base_22| 1)) (= v_~y~0_51 0) (= 0 v_~x$read_delayed_var~0.offset_7) (< |v_#StackHeapBarrier_24| |v_~#x~0.base_244|) (= 0 v_~x$w_buff0_used~0_778) (= v_~x$r_buff0_thd1~0_285 0) (= 0 v_~__unbuffered_p2_EAX$r_buff1_thd1~0_7) (< 0 |v_#StackHeapBarrier_24|) (= 0 v_~__unbuffered_p2_EAX$flush_delayed~0_7) (= 0 (select .cse1 |v_~#x~0.base_244|)) (= 0 v_~__unbuffered_p2_EAX$r_buff1_thd2~0_7) (= 0 v_~__unbuffered_p2_EAX~0_77) (= 0 v_~__unbuffered_p2_EAX$read_delayed_var~0.offset_44) (= 0 v_~__unbuffered_p2_EAX$r_buff1_thd0~0_6) (= 0 v_~__unbuffered_p2_EAX$w_buff1_used~0_7) (= |v_ULTIMATE.start_main_~#t2461~0.offset_17| 0) (= 0 v_~weak$$choice0~0_74) (= 0 v_~weak$$choice1~0_28) (= v_~__unbuffered_p2_EAX$read_delayed~0_57 0) (= 0 |v_#NULL.base_6|) (= 0 v_~__unbuffered_p2_EAX$read_delayed_var~0.base_44) (= |v_#memory_int_394| (store |v_#memory_int_395| |v_ULTIMATE.start_main_~#t2461~0.base_22| (store (select |v_#memory_int_395| |v_ULTIMATE.start_main_~#t2461~0.base_22|) |v_ULTIMATE.start_main_~#t2461~0.offset_17| 0))) (< |v_#StackHeapBarrier_24| |v_ULTIMATE.start_main_~#t2461~0.base_22|) (= 0 v_~__unbuffered_p2_EAX$r_buff0_thd0~0_8) (= v_~x$r_buff1_thd1~0_182 0) (= v_~x$flush_delayed~0_108 0) (= 0 v_~__unbuffered_p2_EAX$r_buff1_thd3~0_7) (= 0 v_~x$r_buff0_thd2~0_71)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_24|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_395|, #length=|v_#length_37|} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_164, ~x$flush_delayed~0=v_~x$flush_delayed~0_108, ~__unbuffered_p2_EAX$read_delayed_var~0.offset=v_~__unbuffered_p2_EAX$read_delayed_var~0.offset_44, ~__unbuffered_p2_EAX$read_delayed_var~0.base=v_~__unbuffered_p2_EAX$read_delayed_var~0.base_44, #NULL.offset=|v_#NULL.offset_6|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_182, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_278, ULTIMATE.start_main_#t~nondet72=|v_ULTIMATE.start_main_#t~nondet72_7|, ULTIMATE.start_main_~#t2461~0.base=|v_ULTIMATE.start_main_~#t2461~0.base_22|, ~weak$$choice1~0=v_~weak$$choice1~0_28, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_70, ~__unbuffered_p2_EAX$w_buff0_used~0=v_~__unbuffered_p2_EAX$w_buff0_used~0_7, #length=|v_#length_36|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_77, ~__unbuffered_p2_EAX$r_buff1_thd2~0=v_~__unbuffered_p2_EAX$r_buff1_thd2~0_7, ULTIMATE.start_main_~#t2461~0.offset=|v_ULTIMATE.start_main_~#t2461~0.offset_17|, ~__unbuffered_p2_EAX$r_buff0_thd0~0=v_~__unbuffered_p2_EAX$r_buff0_thd0~0_8, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_89, ~__unbuffered_p2_EAX$w_buff0~0=v_~__unbuffered_p2_EAX$w_buff0~0_7, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_33, ~#x~0.offset=|v_~#x~0.offset_244|, ~x$w_buff1~0=v_~x$w_buff1~0_137, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_483, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_55, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_21|, ULTIMATE.start_main_#t~ite77=|v_ULTIMATE.start_main_#t~ite77_115|, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_21|, ULTIMATE.start_main_#t~nondet81=|v_ULTIMATE.start_main_#t~nondet81_33|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_7, ULTIMATE.start_main_#t~ite84=|v_ULTIMATE.start_main_#t~ite84_51|, ~weak$$choice0~0=v_~weak$$choice0~0_74, #StackHeapBarrier=|v_#StackHeapBarrier_24|, ULTIMATE.start_main_#t~ite80=|v_ULTIMATE.start_main_#t~ite80_32|, ~__unbuffered_p2_EAX$r_buff0_thd1~0=v_~__unbuffered_p2_EAX$r_buff0_thd1~0_8, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_104, ~__unbuffered_p2_EAX$r_buff1_thd3~0=v_~__unbuffered_p2_EAX$r_buff1_thd3~0_7, ULTIMATE.start_main_~#t2463~0.offset=|v_ULTIMATE.start_main_~#t2463~0.offset_21|, ULTIMATE.start_main_~#t2462~0.offset=|v_ULTIMATE.start_main_~#t2462~0.offset_28|, ~__unbuffered_p2_EAX$w_buff1~0=v_~__unbuffered_p2_EAX$w_buff1~0_7, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_285, ULTIMATE.start_main_#t~nondet73=|v_ULTIMATE.start_main_#t~nondet73_20|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_181, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_31, ~x$mem_tmp~0=v_~x$mem_tmp~0_82, ULTIMATE.start_main_#t~nondet71=|v_ULTIMATE.start_main_#t~nondet71_8|, ULTIMATE.start_main_~#t2462~0.base=|v_ULTIMATE.start_main_~#t2462~0.base_31|, ~__unbuffered_p2_EAX$w_buff1_used~0=v_~__unbuffered_p2_EAX$w_buff1_used~0_7, ~__unbuffered_p2_EAX$r_buff0_thd2~0=v_~__unbuffered_p2_EAX$r_buff0_thd2~0_8, ~__unbuffered_p2_EAX$r_buff1_thd0~0=v_~__unbuffered_p2_EAX$r_buff1_thd0~0_6, ~y~0=v_~y~0_51, ULTIMATE.start_main_#t~mem74=|v_ULTIMATE.start_main_#t~mem74_20|, ~__unbuffered_p2_EAX$mem_tmp~0=v_~__unbuffered_p2_EAX$mem_tmp~0_8, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_33, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_77, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_71, ULTIMATE.start_main_#t~ite78=|v_ULTIMATE.start_main_#t~ite78_299|, ~__unbuffered_p2_EAX$flush_delayed~0=v_~__unbuffered_p2_EAX$flush_delayed~0_7, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_24|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_778, ~__unbuffered_p2_EAX$read_delayed~0=v_~__unbuffered_p2_EAX$read_delayed~0_57, ULTIMATE.start_main_#t~ite83=|v_ULTIMATE.start_main_#t~ite83_50|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_7, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, #valid=|v_#valid_71|, ULTIMATE.start_main_#t~mem82=|v_ULTIMATE.start_main_#t~mem82_37|, #memory_int=|v_#memory_int_394|, ~#x~0.base=|v_~#x~0.base_244|, ULTIMATE.start_main_~#t2463~0.base=|v_ULTIMATE.start_main_~#t2463~0.base_24|, ~__unbuffered_p2_EAX$r_buff1_thd1~0=v_~__unbuffered_p2_EAX$r_buff1_thd1~0_7, ~__unbuffered_p2_EAX$r_buff0_thd3~0=v_~__unbuffered_p2_EAX$r_buff0_thd3~0_6, ~weak$$choice2~0=v_~weak$$choice2~0_140, ~x$read_delayed~0=v_~x$read_delayed~0_8} AuxVars[] AssignedVars[~x$w_buff0~0, ~x$flush_delayed~0, ~__unbuffered_p2_EAX$read_delayed_var~0.offset, ~__unbuffered_p2_EAX$read_delayed_var~0.base, #NULL.offset, ~x$r_buff1_thd1~0, ~x$r_buff0_thd3~0, ULTIMATE.start_main_#t~nondet72, ULTIMATE.start_main_~#t2461~0.base, ~weak$$choice1~0, ~__unbuffered_p0_EAX~0, ~__unbuffered_p2_EAX$w_buff0_used~0, #length, ~__unbuffered_p2_EAX~0, ~__unbuffered_p2_EAX$r_buff1_thd2~0, ULTIMATE.start_main_~#t2461~0.offset, ~__unbuffered_p2_EAX$r_buff0_thd0~0, ~x$r_buff0_thd0~0, ~__unbuffered_p2_EAX$w_buff0~0, ~__unbuffered_p2_EBX~0, ~#x~0.offset, ~x$w_buff1~0, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite79, ULTIMATE.start_main_#t~ite77, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~nondet81, ~x$read_delayed_var~0.base, ULTIMATE.start_main_#t~ite84, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite80, ~__unbuffered_p2_EAX$r_buff0_thd1~0, ~__unbuffered_cnt~0, ~__unbuffered_p2_EAX$r_buff1_thd3~0, ULTIMATE.start_main_~#t2463~0.offset, ULTIMATE.start_main_~#t2462~0.offset, ~__unbuffered_p2_EAX$w_buff1~0, ~x$r_buff0_thd1~0, ULTIMATE.start_main_#t~nondet73, ~x$r_buff1_thd3~0, ~main$tmp_guard1~0, ~x$mem_tmp~0, ULTIMATE.start_main_#t~nondet71, ULTIMATE.start_main_~#t2462~0.base, ~__unbuffered_p2_EAX$w_buff1_used~0, ~__unbuffered_p2_EAX$r_buff0_thd2~0, ~__unbuffered_p2_EAX$r_buff1_thd0~0, ~y~0, ULTIMATE.start_main_#t~mem74, ~__unbuffered_p2_EAX$mem_tmp~0, ~main$tmp_guard0~0, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite78, ~__unbuffered_p2_EAX$flush_delayed~0, #NULL.base, ULTIMATE.start_main_#t~ite76, ~x$w_buff0_used~0, ~__unbuffered_p2_EAX$read_delayed~0, ULTIMATE.start_main_#t~ite83, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_#res, #valid, ULTIMATE.start_main_#t~mem82, #memory_int, ~#x~0.base, ULTIMATE.start_main_~#t2463~0.base, ~__unbuffered_p2_EAX$r_buff1_thd1~0, ~__unbuffered_p2_EAX$r_buff0_thd3~0, ~weak$$choice2~0, ~x$read_delayed~0] because there is no mapped edge [2019-12-07 18:56:34,386 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1126] [1126] L838-1-->L840: Formula: (and (not (= |v_ULTIMATE.start_main_~#t2462~0.base_23| 0)) (= |v_ULTIMATE.start_main_~#t2462~0.offset_22| 0) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t2462~0.base_23|) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t2462~0.base_23|)) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t2462~0.base_23| 4)) (= (store |v_#memory_int_282| |v_ULTIMATE.start_main_~#t2462~0.base_23| (store (select |v_#memory_int_282| |v_ULTIMATE.start_main_~#t2462~0.base_23|) |v_ULTIMATE.start_main_~#t2462~0.offset_22| 1)) |v_#memory_int_281|) (= (store |v_#valid_36| |v_ULTIMATE.start_main_~#t2462~0.base_23| 1) |v_#valid_35|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_282|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_~#t2462~0.base=|v_ULTIMATE.start_main_~#t2462~0.base_23|, ULTIMATE.start_main_~#t2462~0.offset=|v_ULTIMATE.start_main_~#t2462~0.offset_22|, #StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_281|, #length=|v_#length_21|, ULTIMATE.start_main_#t~nondet71=|v_ULTIMATE.start_main_#t~nondet71_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2462~0.base, ULTIMATE.start_main_~#t2462~0.offset, #valid, #memory_int, #length, ULTIMATE.start_main_#t~nondet71] because there is no mapped edge [2019-12-07 18:56:34,386 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1125] [1125] L840-1-->L842: Formula: (and (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t2463~0.base_14| 4)) (= 0 |v_ULTIMATE.start_main_~#t2463~0.offset_14|) (not (= 0 |v_ULTIMATE.start_main_~#t2463~0.base_14|)) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t2463~0.base_14|) (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2463~0.base_14| 1)) (= (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2463~0.base_14|) 0) (= |v_#memory_int_279| (store |v_#memory_int_280| |v_ULTIMATE.start_main_~#t2463~0.base_14| (store (select |v_#memory_int_280| |v_ULTIMATE.start_main_~#t2463~0.base_14|) |v_ULTIMATE.start_main_~#t2463~0.offset_14| 2)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_280|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_279|, ULTIMATE.start_main_~#t2463~0.base=|v_ULTIMATE.start_main_~#t2463~0.base_14|, #length=|v_#length_19|, ULTIMATE.start_main_#t~nondet72=|v_ULTIMATE.start_main_#t~nondet72_3|, ULTIMATE.start_main_~#t2463~0.offset=|v_ULTIMATE.start_main_~#t2463~0.offset_14|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_~#t2463~0.base, #length, ULTIMATE.start_main_#t~nondet72, ULTIMATE.start_main_~#t2463~0.offset] because there is no mapped edge [2019-12-07 18:56:34,389 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1087] [1087] L780-2-->L780-4: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff1_used~0_In1495784125 256))) (.cse1 (= 0 (mod ~x$r_buff1_thd2~0_In1495784125 256)))) (or (and (= |P1Thread1of1ForFork1_#t~mem30_Out1495784125| |P1Thread1of1ForFork1_#t~ite31_Out1495784125|) (or .cse0 .cse1) (= (select (select |#memory_int_In1495784125| |~#x~0.base_In1495784125|) |~#x~0.offset_In1495784125|) |P1Thread1of1ForFork1_#t~mem30_Out1495784125|)) (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork1_#t~mem30_In1495784125| |P1Thread1of1ForFork1_#t~mem30_Out1495784125|) (= ~x$w_buff1~0_In1495784125 |P1Thread1of1ForFork1_#t~ite31_Out1495784125|)))) InVars {P1Thread1of1ForFork1_#t~mem30=|P1Thread1of1ForFork1_#t~mem30_In1495784125|, ~#x~0.offset=|~#x~0.offset_In1495784125|, ~x$w_buff1~0=~x$w_buff1~0_In1495784125, ~#x~0.base=|~#x~0.base_In1495784125|, #memory_int=|#memory_int_In1495784125|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1495784125, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1495784125} OutVars{P1Thread1of1ForFork1_#t~mem30=|P1Thread1of1ForFork1_#t~mem30_Out1495784125|, P1Thread1of1ForFork1_#t~ite31=|P1Thread1of1ForFork1_#t~ite31_Out1495784125|, ~#x~0.offset=|~#x~0.offset_In1495784125|, ~x$w_buff1~0=~x$w_buff1~0_In1495784125, ~#x~0.base=|~#x~0.base_In1495784125|, #memory_int=|#memory_int_In1495784125|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1495784125, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1495784125} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~mem30, P1Thread1of1ForFork1_#t~ite31] because there is no mapped edge [2019-12-07 18:56:34,390 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1014] [1014] L780-4-->L781: Formula: (= (store |v_#memory_int_69| |v_~#x~0.base_42| (store (select |v_#memory_int_69| |v_~#x~0.base_42|) |v_~#x~0.offset_42| |v_P1Thread1of1ForFork1_#t~ite31_6|)) |v_#memory_int_68|) InVars {~#x~0.offset=|v_~#x~0.offset_42|, P1Thread1of1ForFork1_#t~ite31=|v_P1Thread1of1ForFork1_#t~ite31_6|, #memory_int=|v_#memory_int_69|, ~#x~0.base=|v_~#x~0.base_42|} OutVars{P1Thread1of1ForFork1_#t~mem30=|v_P1Thread1of1ForFork1_#t~mem30_3|, ~#x~0.offset=|v_~#x~0.offset_42|, P1Thread1of1ForFork1_#t~ite31=|v_P1Thread1of1ForFork1_#t~ite31_5|, #memory_int=|v_#memory_int_68|, ~#x~0.base=|v_~#x~0.base_42|, P1Thread1of1ForFork1_#t~ite32=|v_P1Thread1of1ForFork1_#t~ite32_7|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~mem30, P1Thread1of1ForFork1_#t~ite31, #memory_int, P1Thread1of1ForFork1_#t~ite32] because there is no mapped edge [2019-12-07 18:56:34,390 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1084] [1084] L781-->L781-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-1793927059 256))) (.cse0 (= 0 (mod ~x$r_buff0_thd2~0_In-1793927059 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite33_Out-1793927059|)) (and (= ~x$w_buff0_used~0_In-1793927059 |P1Thread1of1ForFork1_#t~ite33_Out-1793927059|) (or .cse1 .cse0)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1793927059, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1793927059} OutVars{P1Thread1of1ForFork1_#t~ite33=|P1Thread1of1ForFork1_#t~ite33_Out-1793927059|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1793927059, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1793927059} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite33] because there is no mapped edge [2019-12-07 18:56:34,390 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1081] [1081] L782-->L782-2: Formula: (let ((.cse2 (= (mod ~x$r_buff1_thd2~0_In-1074243129 256) 0)) (.cse3 (= (mod ~x$w_buff1_used~0_In-1074243129 256) 0)) (.cse1 (= 0 (mod ~x$r_buff0_thd2~0_In-1074243129 256))) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In-1074243129 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite34_Out-1074243129|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (= ~x$w_buff1_used~0_In-1074243129 |P1Thread1of1ForFork1_#t~ite34_Out-1074243129|) (or .cse1 .cse0)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1074243129, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1074243129, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1074243129, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1074243129} OutVars{P1Thread1of1ForFork1_#t~ite34=|P1Thread1of1ForFork1_#t~ite34_Out-1074243129|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1074243129, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1074243129, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1074243129, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1074243129} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite34] because there is no mapped edge [2019-12-07 18:56:34,391 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1093] [1093] L783-->L784: Formula: (let ((.cse0 (= ~x$r_buff0_thd2~0_In338929219 ~x$r_buff0_thd2~0_Out338929219)) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In338929219 256))) (.cse2 (= 0 (mod ~x$r_buff0_thd2~0_In338929219 256)))) (or (and .cse0 .cse1) (and .cse2 .cse0) (and (not .cse1) (not .cse2) (= 0 ~x$r_buff0_thd2~0_Out338929219)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In338929219, ~x$w_buff0_used~0=~x$w_buff0_used~0_In338929219} OutVars{P1Thread1of1ForFork1_#t~ite35=|P1Thread1of1ForFork1_#t~ite35_Out338929219|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out338929219, ~x$w_buff0_used~0=~x$w_buff0_used~0_In338929219} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite35, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-12-07 18:56:34,391 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1097] [1097] L784-->L784-2: Formula: (let ((.cse3 (= 0 (mod ~x$w_buff0_used~0_In1457637989 256))) (.cse2 (= 0 (mod ~x$r_buff0_thd2~0_In1457637989 256))) (.cse1 (= 0 (mod ~x$r_buff1_thd2~0_In1457637989 256))) (.cse0 (= 0 (mod ~x$w_buff1_used~0_In1457637989 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~x$r_buff1_thd2~0_In1457637989 |P1Thread1of1ForFork1_#t~ite36_Out1457637989|)) (and (= 0 |P1Thread1of1ForFork1_#t~ite36_Out1457637989|) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In1457637989, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1457637989, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1457637989, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1457637989} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In1457637989, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1457637989, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1457637989, P1Thread1of1ForFork1_#t~ite36=|P1Thread1of1ForFork1_#t~ite36_Out1457637989|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1457637989} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite36] because there is no mapped edge [2019-12-07 18:56:34,394 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1032] [1032] L803-->L804: Formula: (and (= v_~x$r_buff0_thd3~0_105 v_~x$r_buff0_thd3~0_104) (not (= (mod v_~weak$$choice2~0_77 256) 0))) InVars {~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_105, ~weak$$choice2~0=v_~weak$$choice2~0_77} OutVars{P2Thread1of1ForFork2_#t~ite56=|v_P2Thread1of1ForFork2_#t~ite56_9|, P2Thread1of1ForFork2_#t~ite57=|v_P2Thread1of1ForFork2_#t~ite57_9|, P2Thread1of1ForFork2_#t~ite55=|v_P2Thread1of1ForFork2_#t~ite55_10|, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_104, ~weak$$choice2~0=v_~weak$$choice2~0_77} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite56, P2Thread1of1ForFork2_#t~ite57, P2Thread1of1ForFork2_#t~ite55, ~x$r_buff0_thd3~0] because there is no mapped edge [2019-12-07 18:56:34,395 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1083] [1083] L808-->L808-2: Formula: (let ((.cse0 (= (mod ~x$flush_delayed~0_In-560668195 256) 0))) (or (and .cse0 (= |P2Thread1of1ForFork2_#t~mem62_Out-560668195| (select (select |#memory_int_In-560668195| |~#x~0.base_In-560668195|) |~#x~0.offset_In-560668195|)) (= |P2Thread1of1ForFork2_#t~mem62_Out-560668195| |P2Thread1of1ForFork2_#t~ite63_Out-560668195|)) (and (not .cse0) (= |P2Thread1of1ForFork2_#t~ite63_Out-560668195| ~x$mem_tmp~0_In-560668195) (= |P2Thread1of1ForFork2_#t~mem62_In-560668195| |P2Thread1of1ForFork2_#t~mem62_Out-560668195|)))) InVars {~x$flush_delayed~0=~x$flush_delayed~0_In-560668195, ~#x~0.offset=|~#x~0.offset_In-560668195|, ~#x~0.base=|~#x~0.base_In-560668195|, #memory_int=|#memory_int_In-560668195|, ~x$mem_tmp~0=~x$mem_tmp~0_In-560668195, P2Thread1of1ForFork2_#t~mem62=|P2Thread1of1ForFork2_#t~mem62_In-560668195|} OutVars{~x$flush_delayed~0=~x$flush_delayed~0_In-560668195, ~#x~0.offset=|~#x~0.offset_In-560668195|, P2Thread1of1ForFork2_#t~ite63=|P2Thread1of1ForFork2_#t~ite63_Out-560668195|, ~#x~0.base=|~#x~0.base_In-560668195|, #memory_int=|#memory_int_In-560668195|, ~x$mem_tmp~0=~x$mem_tmp~0_In-560668195, P2Thread1of1ForFork2_#t~mem62=|P2Thread1of1ForFork2_#t~mem62_Out-560668195|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite63, P2Thread1of1ForFork2_#t~mem62] because there is no mapped edge [2019-12-07 18:56:34,398 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1079] [1079] L815-2-->L815-4: Formula: (let ((.cse1 (= (mod ~x$r_buff1_thd3~0_In-251084033 256) 0)) (.cse0 (= 0 (mod ~x$w_buff1_used~0_In-251084033 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite65_Out-251084033| ~x$w_buff1~0_In-251084033) (= |P2Thread1of1ForFork2_#t~mem64_In-251084033| |P2Thread1of1ForFork2_#t~mem64_Out-251084033|) (not .cse0) (not .cse1)) (and (= |P2Thread1of1ForFork2_#t~ite65_Out-251084033| |P2Thread1of1ForFork2_#t~mem64_Out-251084033|) (= (select (select |#memory_int_In-251084033| |~#x~0.base_In-251084033|) |~#x~0.offset_In-251084033|) |P2Thread1of1ForFork2_#t~mem64_Out-251084033|) (or .cse1 .cse0)))) InVars {~#x~0.offset=|~#x~0.offset_In-251084033|, ~x$w_buff1~0=~x$w_buff1~0_In-251084033, ~#x~0.base=|~#x~0.base_In-251084033|, #memory_int=|#memory_int_In-251084033|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-251084033, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-251084033, P2Thread1of1ForFork2_#t~mem64=|P2Thread1of1ForFork2_#t~mem64_In-251084033|} OutVars{P2Thread1of1ForFork2_#t~ite65=|P2Thread1of1ForFork2_#t~ite65_Out-251084033|, ~#x~0.offset=|~#x~0.offset_In-251084033|, ~x$w_buff1~0=~x$w_buff1~0_In-251084033, ~#x~0.base=|~#x~0.base_In-251084033|, #memory_int=|#memory_int_In-251084033|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-251084033, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-251084033, P2Thread1of1ForFork2_#t~mem64=|P2Thread1of1ForFork2_#t~mem64_Out-251084033|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite65, P2Thread1of1ForFork2_#t~mem64] because there is no mapped edge [2019-12-07 18:56:34,398 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1033] [1033] L815-4-->L816: Formula: (= (store |v_#memory_int_131| |v_~#x~0.base_85| (store (select |v_#memory_int_131| |v_~#x~0.base_85|) |v_~#x~0.offset_85| |v_P2Thread1of1ForFork2_#t~ite65_10|)) |v_#memory_int_130|) InVars {P2Thread1of1ForFork2_#t~ite65=|v_P2Thread1of1ForFork2_#t~ite65_10|, ~#x~0.offset=|v_~#x~0.offset_85|, #memory_int=|v_#memory_int_131|, ~#x~0.base=|v_~#x~0.base_85|} OutVars{P2Thread1of1ForFork2_#t~ite65=|v_P2Thread1of1ForFork2_#t~ite65_9|, P2Thread1of1ForFork2_#t~ite66=|v_P2Thread1of1ForFork2_#t~ite66_5|, ~#x~0.offset=|v_~#x~0.offset_85|, #memory_int=|v_#memory_int_130|, ~#x~0.base=|v_~#x~0.base_85|, P2Thread1of1ForFork2_#t~mem64=|v_P2Thread1of1ForFork2_#t~mem64_5|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite65, P2Thread1of1ForFork2_#t~ite66, #memory_int, P2Thread1of1ForFork2_#t~mem64] because there is no mapped edge [2019-12-07 18:56:34,399 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1086] [1086] L816-->L816-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In2103464658 256) 0)) (.cse1 (= 0 (mod ~x$r_buff0_thd3~0_In2103464658 256)))) (or (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork2_#t~ite67_Out2103464658| 0)) (and (= |P2Thread1of1ForFork2_#t~ite67_Out2103464658| ~x$w_buff0_used~0_In2103464658) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In2103464658, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2103464658} OutVars{P2Thread1of1ForFork2_#t~ite67=|P2Thread1of1ForFork2_#t~ite67_Out2103464658|, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In2103464658, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2103464658} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite67] because there is no mapped edge [2019-12-07 18:56:34,399 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1095] [1095] L817-->L817-2: Formula: (let ((.cse2 (= 0 (mod ~x$r_buff1_thd3~0_In101978025 256))) (.cse3 (= (mod ~x$w_buff1_used~0_In101978025 256) 0)) (.cse1 (= 0 (mod ~x$r_buff0_thd3~0_In101978025 256))) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In101978025 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~x$w_buff1_used~0_In101978025 |P2Thread1of1ForFork2_#t~ite68_Out101978025|)) (and (= |P2Thread1of1ForFork2_#t~ite68_Out101978025| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In101978025, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In101978025, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In101978025, ~x$w_buff0_used~0=~x$w_buff0_used~0_In101978025} OutVars{P2Thread1of1ForFork2_#t~ite68=|P2Thread1of1ForFork2_#t~ite68_Out101978025|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In101978025, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In101978025, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In101978025, ~x$w_buff0_used~0=~x$w_buff0_used~0_In101978025} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite68] because there is no mapped edge [2019-12-07 18:56:34,400 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1077] [1077] L818-->L819: Formula: (let ((.cse0 (= ~x$r_buff0_thd3~0_Out1082002173 ~x$r_buff0_thd3~0_In1082002173)) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In1082002173 256))) (.cse2 (= (mod ~x$r_buff0_thd3~0_In1082002173 256) 0))) (or (and .cse0 .cse1) (and .cse2 .cse0) (and (not .cse1) (not .cse2) (= ~x$r_buff0_thd3~0_Out1082002173 0)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1082002173, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1082002173} OutVars{P2Thread1of1ForFork2_#t~ite69=|P2Thread1of1ForFork2_#t~ite69_Out1082002173|, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_Out1082002173, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1082002173} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite69, ~x$r_buff0_thd3~0] because there is no mapped edge [2019-12-07 18:56:34,400 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1089] [1089] L819-->L819-2: Formula: (let ((.cse2 (= (mod ~x$w_buff0_used~0_In-113344584 256) 0)) (.cse3 (= 0 (mod ~x$r_buff0_thd3~0_In-113344584 256))) (.cse0 (= (mod ~x$r_buff1_thd3~0_In-113344584 256) 0)) (.cse1 (= (mod ~x$w_buff1_used~0_In-113344584 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite70_Out-113344584| ~x$r_buff1_thd3~0_In-113344584) (or .cse2 .cse3)) (and (= |P2Thread1of1ForFork2_#t~ite70_Out-113344584| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-113344584, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-113344584, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-113344584, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-113344584} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-113344584, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-113344584, P2Thread1of1ForFork2_#t~ite70=|P2Thread1of1ForFork2_#t~ite70_Out-113344584|, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-113344584, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-113344584} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite70] because there is no mapped edge [2019-12-07 18:56:34,400 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1122] [1122] L819-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite70_34| v_~x$r_buff1_thd3~0_127) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_67 (+ v_~__unbuffered_cnt~0_68 1))) InVars {P2Thread1of1ForFork2_#t~ite70=|v_P2Thread1of1ForFork2_#t~ite70_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_68} OutVars{~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_127, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, P2Thread1of1ForFork2_#t~ite70=|v_P2Thread1of1ForFork2_#t~ite70_33|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[~x$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, P2Thread1of1ForFork2_#t~ite70, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 18:56:34,403 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1041] [1041] L761-->L762: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_97 256))) (= v_~x$r_buff0_thd1~0_107 v_~x$r_buff0_thd1~0_106)) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_107, ~weak$$choice2~0=v_~weak$$choice2~0_97} OutVars{P0Thread1of1ForFork0_#t~ite22=|v_P0Thread1of1ForFork0_#t~ite22_7|, P0Thread1of1ForFork0_#t~ite21=|v_P0Thread1of1ForFork0_#t~ite21_9|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_106, ~weak$$choice2~0=v_~weak$$choice2~0_97, P0Thread1of1ForFork0_#t~ite23=|v_P0Thread1of1ForFork0_#t~ite23_7|} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite22, P0Thread1of1ForFork0_#t~ite21, ~x$r_buff0_thd1~0, P0Thread1of1ForFork0_#t~ite23] because there is no mapped edge [2019-12-07 18:56:34,404 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1075] [1075] L764-->L764-2: Formula: (let ((.cse0 (= 0 (mod ~x$flush_delayed~0_In923288712 256)))) (or (and (= |P0Thread1of1ForFork0_#t~mem28_In923288712| |P0Thread1of1ForFork0_#t~mem28_Out923288712|) (not .cse0) (= ~x$mem_tmp~0_In923288712 |P0Thread1of1ForFork0_#t~ite29_Out923288712|)) (and (= |P0Thread1of1ForFork0_#t~mem28_Out923288712| (select (select |#memory_int_In923288712| |~#x~0.base_In923288712|) |~#x~0.offset_In923288712|)) (= |P0Thread1of1ForFork0_#t~mem28_Out923288712| |P0Thread1of1ForFork0_#t~ite29_Out923288712|) .cse0))) InVars {P0Thread1of1ForFork0_#t~mem28=|P0Thread1of1ForFork0_#t~mem28_In923288712|, ~x$flush_delayed~0=~x$flush_delayed~0_In923288712, ~#x~0.offset=|~#x~0.offset_In923288712|, ~#x~0.base=|~#x~0.base_In923288712|, #memory_int=|#memory_int_In923288712|, ~x$mem_tmp~0=~x$mem_tmp~0_In923288712} OutVars{P0Thread1of1ForFork0_#t~mem28=|P0Thread1of1ForFork0_#t~mem28_Out923288712|, ~x$flush_delayed~0=~x$flush_delayed~0_In923288712, ~#x~0.offset=|~#x~0.offset_In923288712|, P0Thread1of1ForFork0_#t~ite29=|P0Thread1of1ForFork0_#t~ite29_Out923288712|, ~#x~0.base=|~#x~0.base_In923288712|, #memory_int=|#memory_int_In923288712|, ~x$mem_tmp~0=~x$mem_tmp~0_In923288712} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~mem28, P0Thread1of1ForFork0_#t~ite29] because there is no mapped edge [2019-12-07 18:56:34,404 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1117] [1117] L764-2-->P0EXIT: Formula: (and (= |v_#memory_int_248| (store |v_#memory_int_249| |v_~#x~0.base_160| (store (select |v_#memory_int_249| |v_~#x~0.base_160|) |v_~#x~0.offset_160| |v_P0Thread1of1ForFork0_#t~ite29_28|))) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_49 (+ v_~__unbuffered_cnt~0_50 1)) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= v_~x$flush_delayed~0_92 0)) InVars {~#x~0.offset=|v_~#x~0.offset_160|, P0Thread1of1ForFork0_#t~ite29=|v_P0Thread1of1ForFork0_#t~ite29_28|, #memory_int=|v_#memory_int_249|, ~#x~0.base=|v_~#x~0.base_160|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_50} OutVars{P0Thread1of1ForFork0_#t~mem28=|v_P0Thread1of1ForFork0_#t~mem28_17|, P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, ~x$flush_delayed~0=v_~x$flush_delayed~0_92, ~#x~0.offset=|v_~#x~0.offset_160|, P0Thread1of1ForFork0_#t~ite29=|v_P0Thread1of1ForFork0_#t~ite29_27|, #memory_int=|v_#memory_int_248|, ~#x~0.base=|v_~#x~0.base_160|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_49} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~mem28, P0Thread1of1ForFork0_#res.offset, ~x$flush_delayed~0, P0Thread1of1ForFork0_#t~ite29, #memory_int, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 18:56:34,404 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1103] [1103] L784-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= v_~x$r_buff1_thd2~0_28 |v_P1Thread1of1ForFork1_#t~ite36_22|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_40 1) v_~__unbuffered_cnt~0_39)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40, P1Thread1of1ForFork1_#t~ite36=|v_P1Thread1of1ForFork1_#t~ite36_22|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_28, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_39, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|, P1Thread1of1ForFork1_#t~ite36=|v_P1Thread1of1ForFork1_#t~ite36_21|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#res.base, P1Thread1of1ForFork1_#t~ite36] because there is no mapped edge [2019-12-07 18:56:34,405 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [984] [984] L846-->L848-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_118 256) 0) (= (mod v_~x$r_buff0_thd0~0_14 256) 0)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_118} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_118} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 18:56:34,405 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1098] [1098] L848-2-->L848-5: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff1_thd0~0_In1157152436 256))) (.cse0 (= (mod ~x$w_buff1_used~0_In1157152436 256) 0)) (.cse2 (= |ULTIMATE.start_main_#t~ite75_Out1157152436| |ULTIMATE.start_main_#t~ite76_Out1157152436|))) (or (and (not .cse0) (= ~x$w_buff1~0_In1157152436 |ULTIMATE.start_main_#t~ite75_Out1157152436|) (not .cse1) (= |ULTIMATE.start_main_#t~mem74_In1157152436| |ULTIMATE.start_main_#t~mem74_Out1157152436|) .cse2) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~mem74_Out1157152436| (select (select |#memory_int_In1157152436| |~#x~0.base_In1157152436|) |~#x~0.offset_In1157152436|)) (= |ULTIMATE.start_main_#t~mem74_Out1157152436| |ULTIMATE.start_main_#t~ite75_Out1157152436|) .cse2))) InVars {~#x~0.offset=|~#x~0.offset_In1157152436|, ULTIMATE.start_main_#t~mem74=|ULTIMATE.start_main_#t~mem74_In1157152436|, ~x$w_buff1~0=~x$w_buff1~0_In1157152436, ~#x~0.base=|~#x~0.base_In1157152436|, #memory_int=|#memory_int_In1157152436|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1157152436, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1157152436} OutVars{ULTIMATE.start_main_#t~mem74=|ULTIMATE.start_main_#t~mem74_Out1157152436|, ~#x~0.offset=|~#x~0.offset_In1157152436|, ~x$w_buff1~0=~x$w_buff1~0_In1157152436, ~#x~0.base=|~#x~0.base_In1157152436|, #memory_int=|#memory_int_In1157152436|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1157152436, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1157152436, ULTIMATE.start_main_#t~ite75=|ULTIMATE.start_main_#t~ite75_Out1157152436|, ULTIMATE.start_main_#t~ite76=|ULTIMATE.start_main_#t~ite76_Out1157152436|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem74, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~ite76] because there is no mapped edge [2019-12-07 18:56:34,405 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1080] [1080] L849-->L849-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In-509860780 256) 0)) (.cse1 (= (mod ~x$r_buff0_thd0~0_In-509860780 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite77_Out-509860780| ~x$w_buff0_used~0_In-509860780) (or .cse0 .cse1)) (and (not .cse0) (= |ULTIMATE.start_main_#t~ite77_Out-509860780| 0) (not .cse1)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-509860780, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-509860780} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-509860780, ULTIMATE.start_main_#t~ite77=|ULTIMATE.start_main_#t~ite77_Out-509860780|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-509860780} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite77] because there is no mapped edge [2019-12-07 18:56:34,406 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1082] [1082] L850-->L850-2: Formula: (let ((.cse0 (= (mod ~x$r_buff0_thd0~0_In-1588447602 256) 0)) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In-1588447602 256))) (.cse2 (= 0 (mod ~x$r_buff1_thd0~0_In-1588447602 256))) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In-1588447602 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite78_Out-1588447602| ~x$w_buff1_used~0_In-1588447602)) (and (= |ULTIMATE.start_main_#t~ite78_Out-1588447602| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1588447602, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1588447602, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1588447602, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1588447602} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1588447602, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1588447602, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1588447602, ULTIMATE.start_main_#t~ite78=|ULTIMATE.start_main_#t~ite78_Out-1588447602|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1588447602} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite78] because there is no mapped edge [2019-12-07 18:56:34,406 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1078] [1078] L851-->L852: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd0~0_In-560048461 256) 0)) (.cse0 (= (mod ~x$w_buff0_used~0_In-560048461 256) 0)) (.cse2 (= ~x$r_buff0_thd0~0_In-560048461 ~x$r_buff0_thd0~0_Out-560048461))) (or (and (not .cse0) (not .cse1) (= 0 ~x$r_buff0_thd0~0_Out-560048461)) (and .cse1 .cse2) (and .cse0 .cse2))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-560048461, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-560048461} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_Out-560048461, ULTIMATE.start_main_#t~ite79=|ULTIMATE.start_main_#t~ite79_Out-560048461|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-560048461} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite79] because there is no mapped edge [2019-12-07 18:56:34,407 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1096] [1096] L852-->L856: Formula: (let ((.cse4 (= ~x$r_buff1_thd0~0_Out-1607730897 0)) (.cse6 (= 0 (mod ~x$r_buff0_thd0~0_In-1607730897 256))) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In-1607730897 256))) (.cse0 (= |ULTIMATE.start_main_#t~nondet81_In-1607730897| ~weak$$choice1~0_Out-1607730897)) (.cse1 (= (mod ~x$w_buff0_used~0_In-1607730897 256) 0)) (.cse5 (= (mod ~x$r_buff1_thd0~0_In-1607730897 256) 0)) (.cse2 (= ~x$r_buff1_thd0~0_Out-1607730897 ~x$r_buff1_thd0~0_In-1607730897))) (or (and .cse0 .cse1 .cse2 .cse3) (and .cse4 .cse0 (not .cse5) (not .cse3)) (and .cse0 .cse5 .cse2 .cse6) (and .cse4 (not .cse6) .cse0 (not .cse1)) (and .cse0 .cse2 .cse6 .cse3) (and .cse0 .cse1 .cse5 .cse2))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1607730897, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1607730897, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1607730897, ULTIMATE.start_main_#t~nondet81=|ULTIMATE.start_main_#t~nondet81_In-1607730897|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1607730897} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1607730897, ~weak$$choice1~0=~weak$$choice1~0_Out-1607730897, ULTIMATE.start_main_#t~ite80=|ULTIMATE.start_main_#t~ite80_Out-1607730897|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1607730897, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_Out-1607730897, ULTIMATE.start_main_#t~nondet81=|ULTIMATE.start_main_#t~nondet81_Out-1607730897|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1607730897} AuxVars[] AssignedVars[~weak$$choice1~0, ULTIMATE.start_main_#t~ite80, ~x$r_buff1_thd0~0, ULTIMATE.start_main_#t~nondet81] because there is no mapped edge [2019-12-07 18:56:34,407 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1069] [1069] L856-->L856-3: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice1~0_In-1414484392 256))) (.cse1 (not (= (mod ~__unbuffered_p2_EAX$read_delayed~0_In-1414484392 256) 0)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~mem82_Out-1414484392| |ULTIMATE.start_main_#t~ite83_Out-1414484392|) (= (select (select |#memory_int_In-1414484392| ~__unbuffered_p2_EAX$read_delayed_var~0.base_In-1414484392) ~__unbuffered_p2_EAX$read_delayed_var~0.offset_In-1414484392) |ULTIMATE.start_main_#t~mem82_Out-1414484392|) .cse1) (and (= ~__unbuffered_p2_EAX~0_In-1414484392 |ULTIMATE.start_main_#t~ite83_Out-1414484392|) (= |ULTIMATE.start_main_#t~mem82_In-1414484392| |ULTIMATE.start_main_#t~mem82_Out-1414484392|) .cse0 .cse1))) InVars {~weak$$choice1~0=~weak$$choice1~0_In-1414484392, ~__unbuffered_p2_EAX$read_delayed_var~0.offset=~__unbuffered_p2_EAX$read_delayed_var~0.offset_In-1414484392, ~__unbuffered_p2_EAX$read_delayed_var~0.base=~__unbuffered_p2_EAX$read_delayed_var~0.base_In-1414484392, ULTIMATE.start_main_#t~mem82=|ULTIMATE.start_main_#t~mem82_In-1414484392|, #memory_int=|#memory_int_In-1414484392|, ~__unbuffered_p2_EAX~0=~__unbuffered_p2_EAX~0_In-1414484392, ~__unbuffered_p2_EAX$read_delayed~0=~__unbuffered_p2_EAX$read_delayed~0_In-1414484392} OutVars{ULTIMATE.start_main_#t~ite83=|ULTIMATE.start_main_#t~ite83_Out-1414484392|, ~weak$$choice1~0=~weak$$choice1~0_In-1414484392, ~__unbuffered_p2_EAX$read_delayed_var~0.offset=~__unbuffered_p2_EAX$read_delayed_var~0.offset_In-1414484392, ULTIMATE.start_main_#t~mem82=|ULTIMATE.start_main_#t~mem82_Out-1414484392|, ~__unbuffered_p2_EAX$read_delayed_var~0.base=~__unbuffered_p2_EAX$read_delayed_var~0.base_In-1414484392, #memory_int=|#memory_int_In-1414484392|, ~__unbuffered_p2_EAX~0=~__unbuffered_p2_EAX~0_In-1414484392, ~__unbuffered_p2_EAX$read_delayed~0=~__unbuffered_p2_EAX$read_delayed~0_In-1414484392} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite83, ULTIMATE.start_main_#t~mem82] because there is no mapped edge [2019-12-07 18:56:34,407 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1130] [1130] L856-3-->L5: Formula: (and (= (mod v_~main$tmp_guard1~0_21 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|) (let ((.cse3 (= v_~__unbuffered_p2_EBX~0_21 0)) (.cse1 (= 1 v_~__unbuffered_p2_EAX~0_46)) (.cse0 (= v_~main$tmp_guard1~0_21 1)) (.cse4 (= 0 v_~__unbuffered_p0_EAX~0_48)) (.cse2 (= |v_ULTIMATE.start_main_#t~ite83_36| v_~__unbuffered_p2_EAX~0_46))) (or (and .cse0 (not .cse1) .cse2) (and .cse0 (not .cse3) .cse2) (and (= v_~main$tmp_guard1~0_21 0) .cse3 .cse1 .cse4 .cse2) (and .cse0 (not .cse4) .cse2)))) InVars {~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_48, ULTIMATE.start_main_#t~ite83=|v_ULTIMATE.start_main_#t~ite83_36|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_21} OutVars{ULTIMATE.start_main_#t~ite84=|v_ULTIMATE.start_main_#t~ite84_33|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_48, ULTIMATE.start_main_#t~ite83=|v_ULTIMATE.start_main_#t~ite83_35|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_21, ULTIMATE.start_main_#t~mem82=|v_ULTIMATE.start_main_#t~mem82_27|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_46, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite84, ULTIMATE.start_main_#t~ite83, ULTIMATE.start___VERIFIER_assert_~expression, ULTIMATE.start_main_#t~mem82, ~main$tmp_guard1~0, ~__unbuffered_p2_EAX~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:56:34,407 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1131] [1131] L5-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:56:34,473 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 06:56:34 BasicIcfg [2019-12-07 18:56:34,473 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 18:56:34,474 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:56:34,474 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:56:34,474 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:56:34,474 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:47:16" (3/4) ... [2019-12-07 18:56:34,476 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 18:56:34,476 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1160] [1160] ULTIMATE.startENTRY-->L838: Formula: (let ((.cse1 (store |v_#valid_73| 0 0))) (let ((.cse0 (store .cse1 |v_~#x~0.base_244| 1))) (and (= v_~__unbuffered_cnt~0_104 0) (= 0 v_~x$r_buff0_thd3~0_278) (= 0 v_~__unbuffered_p2_EAX$r_buff0_thd1~0_8) (= v_~main$tmp_guard1~0_31 0) (= |v_#NULL.offset_6| 0) (= 0 v_~__unbuffered_p2_EAX$w_buff0~0_7) (= (select (select |v_#memory_int_395| |v_~#x~0.base_244|) |v_~#x~0.offset_244|) 0) (= v_~x$r_buff1_thd0~0_77 0) (= 0 v_~__unbuffered_p2_EAX$r_buff0_thd2~0_8) (= 0 v_~__unbuffered_p2_EAX$w_buff0_used~0_7) (= 0 v_~__unbuffered_p2_EAX$w_buff1~0_7) (= 0 v_~x$w_buff1~0_137) (= 0 |v_~#x~0.offset_244|) (= (select .cse0 |v_ULTIMATE.start_main_~#t2461~0.base_22|) 0) (= 0 v_~x$read_delayed_var~0.base_7) (= 0 v_~__unbuffered_p0_EAX~0_70) (= v_~x$r_buff1_thd2~0_55 0) (= 0 v_~__unbuffered_p2_EAX$r_buff0_thd3~0_6) (= v_~weak$$choice2~0_140 0) (= 0 v_~x$read_delayed~0_8) (= v_~x$mem_tmp~0_82 0) (= v_~__unbuffered_p2_EBX~0_33 0) (= 0 v_~x$r_buff0_thd0~0_89) (= |v_#length_36| (store (store |v_#length_37| |v_~#x~0.base_244| 4) |v_ULTIMATE.start_main_~#t2461~0.base_22| 4)) (= 0 v_~x$w_buff1_used~0_483) (= 0 v_~__unbuffered_p2_EAX$mem_tmp~0_8) (= v_~main$tmp_guard0~0_33 0) (= 0 v_~x$w_buff0~0_164) (= 0 v_~x$r_buff1_thd3~0_181) (= |v_#valid_71| (store .cse0 |v_ULTIMATE.start_main_~#t2461~0.base_22| 1)) (= v_~y~0_51 0) (= 0 v_~x$read_delayed_var~0.offset_7) (< |v_#StackHeapBarrier_24| |v_~#x~0.base_244|) (= 0 v_~x$w_buff0_used~0_778) (= v_~x$r_buff0_thd1~0_285 0) (= 0 v_~__unbuffered_p2_EAX$r_buff1_thd1~0_7) (< 0 |v_#StackHeapBarrier_24|) (= 0 v_~__unbuffered_p2_EAX$flush_delayed~0_7) (= 0 (select .cse1 |v_~#x~0.base_244|)) (= 0 v_~__unbuffered_p2_EAX$r_buff1_thd2~0_7) (= 0 v_~__unbuffered_p2_EAX~0_77) (= 0 v_~__unbuffered_p2_EAX$read_delayed_var~0.offset_44) (= 0 v_~__unbuffered_p2_EAX$r_buff1_thd0~0_6) (= 0 v_~__unbuffered_p2_EAX$w_buff1_used~0_7) (= |v_ULTIMATE.start_main_~#t2461~0.offset_17| 0) (= 0 v_~weak$$choice0~0_74) (= 0 v_~weak$$choice1~0_28) (= v_~__unbuffered_p2_EAX$read_delayed~0_57 0) (= 0 |v_#NULL.base_6|) (= 0 v_~__unbuffered_p2_EAX$read_delayed_var~0.base_44) (= |v_#memory_int_394| (store |v_#memory_int_395| |v_ULTIMATE.start_main_~#t2461~0.base_22| (store (select |v_#memory_int_395| |v_ULTIMATE.start_main_~#t2461~0.base_22|) |v_ULTIMATE.start_main_~#t2461~0.offset_17| 0))) (< |v_#StackHeapBarrier_24| |v_ULTIMATE.start_main_~#t2461~0.base_22|) (= 0 v_~__unbuffered_p2_EAX$r_buff0_thd0~0_8) (= v_~x$r_buff1_thd1~0_182 0) (= v_~x$flush_delayed~0_108 0) (= 0 v_~__unbuffered_p2_EAX$r_buff1_thd3~0_7) (= 0 v_~x$r_buff0_thd2~0_71)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_24|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_395|, #length=|v_#length_37|} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_164, ~x$flush_delayed~0=v_~x$flush_delayed~0_108, ~__unbuffered_p2_EAX$read_delayed_var~0.offset=v_~__unbuffered_p2_EAX$read_delayed_var~0.offset_44, ~__unbuffered_p2_EAX$read_delayed_var~0.base=v_~__unbuffered_p2_EAX$read_delayed_var~0.base_44, #NULL.offset=|v_#NULL.offset_6|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_182, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_278, ULTIMATE.start_main_#t~nondet72=|v_ULTIMATE.start_main_#t~nondet72_7|, ULTIMATE.start_main_~#t2461~0.base=|v_ULTIMATE.start_main_~#t2461~0.base_22|, ~weak$$choice1~0=v_~weak$$choice1~0_28, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_70, ~__unbuffered_p2_EAX$w_buff0_used~0=v_~__unbuffered_p2_EAX$w_buff0_used~0_7, #length=|v_#length_36|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_77, ~__unbuffered_p2_EAX$r_buff1_thd2~0=v_~__unbuffered_p2_EAX$r_buff1_thd2~0_7, ULTIMATE.start_main_~#t2461~0.offset=|v_ULTIMATE.start_main_~#t2461~0.offset_17|, ~__unbuffered_p2_EAX$r_buff0_thd0~0=v_~__unbuffered_p2_EAX$r_buff0_thd0~0_8, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_89, ~__unbuffered_p2_EAX$w_buff0~0=v_~__unbuffered_p2_EAX$w_buff0~0_7, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_33, ~#x~0.offset=|v_~#x~0.offset_244|, ~x$w_buff1~0=v_~x$w_buff1~0_137, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_483, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_55, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_21|, ULTIMATE.start_main_#t~ite77=|v_ULTIMATE.start_main_#t~ite77_115|, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_21|, ULTIMATE.start_main_#t~nondet81=|v_ULTIMATE.start_main_#t~nondet81_33|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_7, ULTIMATE.start_main_#t~ite84=|v_ULTIMATE.start_main_#t~ite84_51|, ~weak$$choice0~0=v_~weak$$choice0~0_74, #StackHeapBarrier=|v_#StackHeapBarrier_24|, ULTIMATE.start_main_#t~ite80=|v_ULTIMATE.start_main_#t~ite80_32|, ~__unbuffered_p2_EAX$r_buff0_thd1~0=v_~__unbuffered_p2_EAX$r_buff0_thd1~0_8, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_104, ~__unbuffered_p2_EAX$r_buff1_thd3~0=v_~__unbuffered_p2_EAX$r_buff1_thd3~0_7, ULTIMATE.start_main_~#t2463~0.offset=|v_ULTIMATE.start_main_~#t2463~0.offset_21|, ULTIMATE.start_main_~#t2462~0.offset=|v_ULTIMATE.start_main_~#t2462~0.offset_28|, ~__unbuffered_p2_EAX$w_buff1~0=v_~__unbuffered_p2_EAX$w_buff1~0_7, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_285, ULTIMATE.start_main_#t~nondet73=|v_ULTIMATE.start_main_#t~nondet73_20|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_181, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_31, ~x$mem_tmp~0=v_~x$mem_tmp~0_82, ULTIMATE.start_main_#t~nondet71=|v_ULTIMATE.start_main_#t~nondet71_8|, ULTIMATE.start_main_~#t2462~0.base=|v_ULTIMATE.start_main_~#t2462~0.base_31|, ~__unbuffered_p2_EAX$w_buff1_used~0=v_~__unbuffered_p2_EAX$w_buff1_used~0_7, ~__unbuffered_p2_EAX$r_buff0_thd2~0=v_~__unbuffered_p2_EAX$r_buff0_thd2~0_8, ~__unbuffered_p2_EAX$r_buff1_thd0~0=v_~__unbuffered_p2_EAX$r_buff1_thd0~0_6, ~y~0=v_~y~0_51, ULTIMATE.start_main_#t~mem74=|v_ULTIMATE.start_main_#t~mem74_20|, ~__unbuffered_p2_EAX$mem_tmp~0=v_~__unbuffered_p2_EAX$mem_tmp~0_8, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_33, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_77, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_71, ULTIMATE.start_main_#t~ite78=|v_ULTIMATE.start_main_#t~ite78_299|, ~__unbuffered_p2_EAX$flush_delayed~0=v_~__unbuffered_p2_EAX$flush_delayed~0_7, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_24|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_778, ~__unbuffered_p2_EAX$read_delayed~0=v_~__unbuffered_p2_EAX$read_delayed~0_57, ULTIMATE.start_main_#t~ite83=|v_ULTIMATE.start_main_#t~ite83_50|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_7, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, #valid=|v_#valid_71|, ULTIMATE.start_main_#t~mem82=|v_ULTIMATE.start_main_#t~mem82_37|, #memory_int=|v_#memory_int_394|, ~#x~0.base=|v_~#x~0.base_244|, ULTIMATE.start_main_~#t2463~0.base=|v_ULTIMATE.start_main_~#t2463~0.base_24|, ~__unbuffered_p2_EAX$r_buff1_thd1~0=v_~__unbuffered_p2_EAX$r_buff1_thd1~0_7, ~__unbuffered_p2_EAX$r_buff0_thd3~0=v_~__unbuffered_p2_EAX$r_buff0_thd3~0_6, ~weak$$choice2~0=v_~weak$$choice2~0_140, ~x$read_delayed~0=v_~x$read_delayed~0_8} AuxVars[] AssignedVars[~x$w_buff0~0, ~x$flush_delayed~0, ~__unbuffered_p2_EAX$read_delayed_var~0.offset, ~__unbuffered_p2_EAX$read_delayed_var~0.base, #NULL.offset, ~x$r_buff1_thd1~0, ~x$r_buff0_thd3~0, ULTIMATE.start_main_#t~nondet72, ULTIMATE.start_main_~#t2461~0.base, ~weak$$choice1~0, ~__unbuffered_p0_EAX~0, ~__unbuffered_p2_EAX$w_buff0_used~0, #length, ~__unbuffered_p2_EAX~0, ~__unbuffered_p2_EAX$r_buff1_thd2~0, ULTIMATE.start_main_~#t2461~0.offset, ~__unbuffered_p2_EAX$r_buff0_thd0~0, ~x$r_buff0_thd0~0, ~__unbuffered_p2_EAX$w_buff0~0, ~__unbuffered_p2_EBX~0, ~#x~0.offset, ~x$w_buff1~0, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite79, ULTIMATE.start_main_#t~ite77, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~nondet81, ~x$read_delayed_var~0.base, ULTIMATE.start_main_#t~ite84, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite80, ~__unbuffered_p2_EAX$r_buff0_thd1~0, ~__unbuffered_cnt~0, ~__unbuffered_p2_EAX$r_buff1_thd3~0, ULTIMATE.start_main_~#t2463~0.offset, ULTIMATE.start_main_~#t2462~0.offset, ~__unbuffered_p2_EAX$w_buff1~0, ~x$r_buff0_thd1~0, ULTIMATE.start_main_#t~nondet73, ~x$r_buff1_thd3~0, ~main$tmp_guard1~0, ~x$mem_tmp~0, ULTIMATE.start_main_#t~nondet71, ULTIMATE.start_main_~#t2462~0.base, ~__unbuffered_p2_EAX$w_buff1_used~0, ~__unbuffered_p2_EAX$r_buff0_thd2~0, ~__unbuffered_p2_EAX$r_buff1_thd0~0, ~y~0, ULTIMATE.start_main_#t~mem74, ~__unbuffered_p2_EAX$mem_tmp~0, ~main$tmp_guard0~0, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite78, ~__unbuffered_p2_EAX$flush_delayed~0, #NULL.base, ULTIMATE.start_main_#t~ite76, ~x$w_buff0_used~0, ~__unbuffered_p2_EAX$read_delayed~0, ULTIMATE.start_main_#t~ite83, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_#res, #valid, ULTIMATE.start_main_#t~mem82, #memory_int, ~#x~0.base, ULTIMATE.start_main_~#t2463~0.base, ~__unbuffered_p2_EAX$r_buff1_thd1~0, ~__unbuffered_p2_EAX$r_buff0_thd3~0, ~weak$$choice2~0, ~x$read_delayed~0] because there is no mapped edge [2019-12-07 18:56:34,477 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1126] [1126] L838-1-->L840: Formula: (and (not (= |v_ULTIMATE.start_main_~#t2462~0.base_23| 0)) (= |v_ULTIMATE.start_main_~#t2462~0.offset_22| 0) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t2462~0.base_23|) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t2462~0.base_23|)) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t2462~0.base_23| 4)) (= (store |v_#memory_int_282| |v_ULTIMATE.start_main_~#t2462~0.base_23| (store (select |v_#memory_int_282| |v_ULTIMATE.start_main_~#t2462~0.base_23|) |v_ULTIMATE.start_main_~#t2462~0.offset_22| 1)) |v_#memory_int_281|) (= (store |v_#valid_36| |v_ULTIMATE.start_main_~#t2462~0.base_23| 1) |v_#valid_35|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_282|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_~#t2462~0.base=|v_ULTIMATE.start_main_~#t2462~0.base_23|, ULTIMATE.start_main_~#t2462~0.offset=|v_ULTIMATE.start_main_~#t2462~0.offset_22|, #StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_281|, #length=|v_#length_21|, ULTIMATE.start_main_#t~nondet71=|v_ULTIMATE.start_main_#t~nondet71_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2462~0.base, ULTIMATE.start_main_~#t2462~0.offset, #valid, #memory_int, #length, ULTIMATE.start_main_#t~nondet71] because there is no mapped edge [2019-12-07 18:56:34,477 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1125] [1125] L840-1-->L842: Formula: (and (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t2463~0.base_14| 4)) (= 0 |v_ULTIMATE.start_main_~#t2463~0.offset_14|) (not (= 0 |v_ULTIMATE.start_main_~#t2463~0.base_14|)) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t2463~0.base_14|) (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2463~0.base_14| 1)) (= (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2463~0.base_14|) 0) (= |v_#memory_int_279| (store |v_#memory_int_280| |v_ULTIMATE.start_main_~#t2463~0.base_14| (store (select |v_#memory_int_280| |v_ULTIMATE.start_main_~#t2463~0.base_14|) |v_ULTIMATE.start_main_~#t2463~0.offset_14| 2)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_280|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_279|, ULTIMATE.start_main_~#t2463~0.base=|v_ULTIMATE.start_main_~#t2463~0.base_14|, #length=|v_#length_19|, ULTIMATE.start_main_#t~nondet72=|v_ULTIMATE.start_main_#t~nondet72_3|, ULTIMATE.start_main_~#t2463~0.offset=|v_ULTIMATE.start_main_~#t2463~0.offset_14|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_~#t2463~0.base, #length, ULTIMATE.start_main_#t~nondet72, ULTIMATE.start_main_~#t2463~0.offset] because there is no mapped edge [2019-12-07 18:56:34,480 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1087] [1087] L780-2-->L780-4: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff1_used~0_In1495784125 256))) (.cse1 (= 0 (mod ~x$r_buff1_thd2~0_In1495784125 256)))) (or (and (= |P1Thread1of1ForFork1_#t~mem30_Out1495784125| |P1Thread1of1ForFork1_#t~ite31_Out1495784125|) (or .cse0 .cse1) (= (select (select |#memory_int_In1495784125| |~#x~0.base_In1495784125|) |~#x~0.offset_In1495784125|) |P1Thread1of1ForFork1_#t~mem30_Out1495784125|)) (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork1_#t~mem30_In1495784125| |P1Thread1of1ForFork1_#t~mem30_Out1495784125|) (= ~x$w_buff1~0_In1495784125 |P1Thread1of1ForFork1_#t~ite31_Out1495784125|)))) InVars {P1Thread1of1ForFork1_#t~mem30=|P1Thread1of1ForFork1_#t~mem30_In1495784125|, ~#x~0.offset=|~#x~0.offset_In1495784125|, ~x$w_buff1~0=~x$w_buff1~0_In1495784125, ~#x~0.base=|~#x~0.base_In1495784125|, #memory_int=|#memory_int_In1495784125|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1495784125, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1495784125} OutVars{P1Thread1of1ForFork1_#t~mem30=|P1Thread1of1ForFork1_#t~mem30_Out1495784125|, P1Thread1of1ForFork1_#t~ite31=|P1Thread1of1ForFork1_#t~ite31_Out1495784125|, ~#x~0.offset=|~#x~0.offset_In1495784125|, ~x$w_buff1~0=~x$w_buff1~0_In1495784125, ~#x~0.base=|~#x~0.base_In1495784125|, #memory_int=|#memory_int_In1495784125|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1495784125, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1495784125} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~mem30, P1Thread1of1ForFork1_#t~ite31] because there is no mapped edge [2019-12-07 18:56:34,480 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1014] [1014] L780-4-->L781: Formula: (= (store |v_#memory_int_69| |v_~#x~0.base_42| (store (select |v_#memory_int_69| |v_~#x~0.base_42|) |v_~#x~0.offset_42| |v_P1Thread1of1ForFork1_#t~ite31_6|)) |v_#memory_int_68|) InVars {~#x~0.offset=|v_~#x~0.offset_42|, P1Thread1of1ForFork1_#t~ite31=|v_P1Thread1of1ForFork1_#t~ite31_6|, #memory_int=|v_#memory_int_69|, ~#x~0.base=|v_~#x~0.base_42|} OutVars{P1Thread1of1ForFork1_#t~mem30=|v_P1Thread1of1ForFork1_#t~mem30_3|, ~#x~0.offset=|v_~#x~0.offset_42|, P1Thread1of1ForFork1_#t~ite31=|v_P1Thread1of1ForFork1_#t~ite31_5|, #memory_int=|v_#memory_int_68|, ~#x~0.base=|v_~#x~0.base_42|, P1Thread1of1ForFork1_#t~ite32=|v_P1Thread1of1ForFork1_#t~ite32_7|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~mem30, P1Thread1of1ForFork1_#t~ite31, #memory_int, P1Thread1of1ForFork1_#t~ite32] because there is no mapped edge [2019-12-07 18:56:34,480 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1084] [1084] L781-->L781-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-1793927059 256))) (.cse0 (= 0 (mod ~x$r_buff0_thd2~0_In-1793927059 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite33_Out-1793927059|)) (and (= ~x$w_buff0_used~0_In-1793927059 |P1Thread1of1ForFork1_#t~ite33_Out-1793927059|) (or .cse1 .cse0)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1793927059, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1793927059} OutVars{P1Thread1of1ForFork1_#t~ite33=|P1Thread1of1ForFork1_#t~ite33_Out-1793927059|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1793927059, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1793927059} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite33] because there is no mapped edge [2019-12-07 18:56:34,480 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1081] [1081] L782-->L782-2: Formula: (let ((.cse2 (= (mod ~x$r_buff1_thd2~0_In-1074243129 256) 0)) (.cse3 (= (mod ~x$w_buff1_used~0_In-1074243129 256) 0)) (.cse1 (= 0 (mod ~x$r_buff0_thd2~0_In-1074243129 256))) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In-1074243129 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite34_Out-1074243129|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (= ~x$w_buff1_used~0_In-1074243129 |P1Thread1of1ForFork1_#t~ite34_Out-1074243129|) (or .cse1 .cse0)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1074243129, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1074243129, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1074243129, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1074243129} OutVars{P1Thread1of1ForFork1_#t~ite34=|P1Thread1of1ForFork1_#t~ite34_Out-1074243129|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1074243129, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1074243129, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1074243129, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1074243129} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite34] because there is no mapped edge [2019-12-07 18:56:34,481 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1093] [1093] L783-->L784: Formula: (let ((.cse0 (= ~x$r_buff0_thd2~0_In338929219 ~x$r_buff0_thd2~0_Out338929219)) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In338929219 256))) (.cse2 (= 0 (mod ~x$r_buff0_thd2~0_In338929219 256)))) (or (and .cse0 .cse1) (and .cse2 .cse0) (and (not .cse1) (not .cse2) (= 0 ~x$r_buff0_thd2~0_Out338929219)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In338929219, ~x$w_buff0_used~0=~x$w_buff0_used~0_In338929219} OutVars{P1Thread1of1ForFork1_#t~ite35=|P1Thread1of1ForFork1_#t~ite35_Out338929219|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out338929219, ~x$w_buff0_used~0=~x$w_buff0_used~0_In338929219} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite35, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-12-07 18:56:34,481 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1097] [1097] L784-->L784-2: Formula: (let ((.cse3 (= 0 (mod ~x$w_buff0_used~0_In1457637989 256))) (.cse2 (= 0 (mod ~x$r_buff0_thd2~0_In1457637989 256))) (.cse1 (= 0 (mod ~x$r_buff1_thd2~0_In1457637989 256))) (.cse0 (= 0 (mod ~x$w_buff1_used~0_In1457637989 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~x$r_buff1_thd2~0_In1457637989 |P1Thread1of1ForFork1_#t~ite36_Out1457637989|)) (and (= 0 |P1Thread1of1ForFork1_#t~ite36_Out1457637989|) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In1457637989, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1457637989, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1457637989, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1457637989} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In1457637989, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1457637989, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1457637989, P1Thread1of1ForFork1_#t~ite36=|P1Thread1of1ForFork1_#t~ite36_Out1457637989|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1457637989} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite36] because there is no mapped edge [2019-12-07 18:56:34,484 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1032] [1032] L803-->L804: Formula: (and (= v_~x$r_buff0_thd3~0_105 v_~x$r_buff0_thd3~0_104) (not (= (mod v_~weak$$choice2~0_77 256) 0))) InVars {~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_105, ~weak$$choice2~0=v_~weak$$choice2~0_77} OutVars{P2Thread1of1ForFork2_#t~ite56=|v_P2Thread1of1ForFork2_#t~ite56_9|, P2Thread1of1ForFork2_#t~ite57=|v_P2Thread1of1ForFork2_#t~ite57_9|, P2Thread1of1ForFork2_#t~ite55=|v_P2Thread1of1ForFork2_#t~ite55_10|, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_104, ~weak$$choice2~0=v_~weak$$choice2~0_77} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite56, P2Thread1of1ForFork2_#t~ite57, P2Thread1of1ForFork2_#t~ite55, ~x$r_buff0_thd3~0] because there is no mapped edge [2019-12-07 18:56:34,485 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1083] [1083] L808-->L808-2: Formula: (let ((.cse0 (= (mod ~x$flush_delayed~0_In-560668195 256) 0))) (or (and .cse0 (= |P2Thread1of1ForFork2_#t~mem62_Out-560668195| (select (select |#memory_int_In-560668195| |~#x~0.base_In-560668195|) |~#x~0.offset_In-560668195|)) (= |P2Thread1of1ForFork2_#t~mem62_Out-560668195| |P2Thread1of1ForFork2_#t~ite63_Out-560668195|)) (and (not .cse0) (= |P2Thread1of1ForFork2_#t~ite63_Out-560668195| ~x$mem_tmp~0_In-560668195) (= |P2Thread1of1ForFork2_#t~mem62_In-560668195| |P2Thread1of1ForFork2_#t~mem62_Out-560668195|)))) InVars {~x$flush_delayed~0=~x$flush_delayed~0_In-560668195, ~#x~0.offset=|~#x~0.offset_In-560668195|, ~#x~0.base=|~#x~0.base_In-560668195|, #memory_int=|#memory_int_In-560668195|, ~x$mem_tmp~0=~x$mem_tmp~0_In-560668195, P2Thread1of1ForFork2_#t~mem62=|P2Thread1of1ForFork2_#t~mem62_In-560668195|} OutVars{~x$flush_delayed~0=~x$flush_delayed~0_In-560668195, ~#x~0.offset=|~#x~0.offset_In-560668195|, P2Thread1of1ForFork2_#t~ite63=|P2Thread1of1ForFork2_#t~ite63_Out-560668195|, ~#x~0.base=|~#x~0.base_In-560668195|, #memory_int=|#memory_int_In-560668195|, ~x$mem_tmp~0=~x$mem_tmp~0_In-560668195, P2Thread1of1ForFork2_#t~mem62=|P2Thread1of1ForFork2_#t~mem62_Out-560668195|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite63, P2Thread1of1ForFork2_#t~mem62] because there is no mapped edge [2019-12-07 18:56:34,488 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1079] [1079] L815-2-->L815-4: Formula: (let ((.cse1 (= (mod ~x$r_buff1_thd3~0_In-251084033 256) 0)) (.cse0 (= 0 (mod ~x$w_buff1_used~0_In-251084033 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite65_Out-251084033| ~x$w_buff1~0_In-251084033) (= |P2Thread1of1ForFork2_#t~mem64_In-251084033| |P2Thread1of1ForFork2_#t~mem64_Out-251084033|) (not .cse0) (not .cse1)) (and (= |P2Thread1of1ForFork2_#t~ite65_Out-251084033| |P2Thread1of1ForFork2_#t~mem64_Out-251084033|) (= (select (select |#memory_int_In-251084033| |~#x~0.base_In-251084033|) |~#x~0.offset_In-251084033|) |P2Thread1of1ForFork2_#t~mem64_Out-251084033|) (or .cse1 .cse0)))) InVars {~#x~0.offset=|~#x~0.offset_In-251084033|, ~x$w_buff1~0=~x$w_buff1~0_In-251084033, ~#x~0.base=|~#x~0.base_In-251084033|, #memory_int=|#memory_int_In-251084033|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-251084033, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-251084033, P2Thread1of1ForFork2_#t~mem64=|P2Thread1of1ForFork2_#t~mem64_In-251084033|} OutVars{P2Thread1of1ForFork2_#t~ite65=|P2Thread1of1ForFork2_#t~ite65_Out-251084033|, ~#x~0.offset=|~#x~0.offset_In-251084033|, ~x$w_buff1~0=~x$w_buff1~0_In-251084033, ~#x~0.base=|~#x~0.base_In-251084033|, #memory_int=|#memory_int_In-251084033|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-251084033, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-251084033, P2Thread1of1ForFork2_#t~mem64=|P2Thread1of1ForFork2_#t~mem64_Out-251084033|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite65, P2Thread1of1ForFork2_#t~mem64] because there is no mapped edge [2019-12-07 18:56:34,488 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1033] [1033] L815-4-->L816: Formula: (= (store |v_#memory_int_131| |v_~#x~0.base_85| (store (select |v_#memory_int_131| |v_~#x~0.base_85|) |v_~#x~0.offset_85| |v_P2Thread1of1ForFork2_#t~ite65_10|)) |v_#memory_int_130|) InVars {P2Thread1of1ForFork2_#t~ite65=|v_P2Thread1of1ForFork2_#t~ite65_10|, ~#x~0.offset=|v_~#x~0.offset_85|, #memory_int=|v_#memory_int_131|, ~#x~0.base=|v_~#x~0.base_85|} OutVars{P2Thread1of1ForFork2_#t~ite65=|v_P2Thread1of1ForFork2_#t~ite65_9|, P2Thread1of1ForFork2_#t~ite66=|v_P2Thread1of1ForFork2_#t~ite66_5|, ~#x~0.offset=|v_~#x~0.offset_85|, #memory_int=|v_#memory_int_130|, ~#x~0.base=|v_~#x~0.base_85|, P2Thread1of1ForFork2_#t~mem64=|v_P2Thread1of1ForFork2_#t~mem64_5|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite65, P2Thread1of1ForFork2_#t~ite66, #memory_int, P2Thread1of1ForFork2_#t~mem64] because there is no mapped edge [2019-12-07 18:56:34,489 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1086] [1086] L816-->L816-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In2103464658 256) 0)) (.cse1 (= 0 (mod ~x$r_buff0_thd3~0_In2103464658 256)))) (or (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork2_#t~ite67_Out2103464658| 0)) (and (= |P2Thread1of1ForFork2_#t~ite67_Out2103464658| ~x$w_buff0_used~0_In2103464658) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In2103464658, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2103464658} OutVars{P2Thread1of1ForFork2_#t~ite67=|P2Thread1of1ForFork2_#t~ite67_Out2103464658|, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In2103464658, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2103464658} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite67] because there is no mapped edge [2019-12-07 18:56:34,489 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1095] [1095] L817-->L817-2: Formula: (let ((.cse2 (= 0 (mod ~x$r_buff1_thd3~0_In101978025 256))) (.cse3 (= (mod ~x$w_buff1_used~0_In101978025 256) 0)) (.cse1 (= 0 (mod ~x$r_buff0_thd3~0_In101978025 256))) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In101978025 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~x$w_buff1_used~0_In101978025 |P2Thread1of1ForFork2_#t~ite68_Out101978025|)) (and (= |P2Thread1of1ForFork2_#t~ite68_Out101978025| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In101978025, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In101978025, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In101978025, ~x$w_buff0_used~0=~x$w_buff0_used~0_In101978025} OutVars{P2Thread1of1ForFork2_#t~ite68=|P2Thread1of1ForFork2_#t~ite68_Out101978025|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In101978025, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In101978025, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In101978025, ~x$w_buff0_used~0=~x$w_buff0_used~0_In101978025} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite68] because there is no mapped edge [2019-12-07 18:56:34,490 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1077] [1077] L818-->L819: Formula: (let ((.cse0 (= ~x$r_buff0_thd3~0_Out1082002173 ~x$r_buff0_thd3~0_In1082002173)) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In1082002173 256))) (.cse2 (= (mod ~x$r_buff0_thd3~0_In1082002173 256) 0))) (or (and .cse0 .cse1) (and .cse2 .cse0) (and (not .cse1) (not .cse2) (= ~x$r_buff0_thd3~0_Out1082002173 0)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1082002173, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1082002173} OutVars{P2Thread1of1ForFork2_#t~ite69=|P2Thread1of1ForFork2_#t~ite69_Out1082002173|, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_Out1082002173, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1082002173} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite69, ~x$r_buff0_thd3~0] because there is no mapped edge [2019-12-07 18:56:34,490 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1089] [1089] L819-->L819-2: Formula: (let ((.cse2 (= (mod ~x$w_buff0_used~0_In-113344584 256) 0)) (.cse3 (= 0 (mod ~x$r_buff0_thd3~0_In-113344584 256))) (.cse0 (= (mod ~x$r_buff1_thd3~0_In-113344584 256) 0)) (.cse1 (= (mod ~x$w_buff1_used~0_In-113344584 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite70_Out-113344584| ~x$r_buff1_thd3~0_In-113344584) (or .cse2 .cse3)) (and (= |P2Thread1of1ForFork2_#t~ite70_Out-113344584| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-113344584, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-113344584, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-113344584, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-113344584} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-113344584, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-113344584, P2Thread1of1ForFork2_#t~ite70=|P2Thread1of1ForFork2_#t~ite70_Out-113344584|, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-113344584, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-113344584} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite70] because there is no mapped edge [2019-12-07 18:56:34,490 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1122] [1122] L819-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite70_34| v_~x$r_buff1_thd3~0_127) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_67 (+ v_~__unbuffered_cnt~0_68 1))) InVars {P2Thread1of1ForFork2_#t~ite70=|v_P2Thread1of1ForFork2_#t~ite70_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_68} OutVars{~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_127, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, P2Thread1of1ForFork2_#t~ite70=|v_P2Thread1of1ForFork2_#t~ite70_33|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[~x$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, P2Thread1of1ForFork2_#t~ite70, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 18:56:34,492 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1041] [1041] L761-->L762: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_97 256))) (= v_~x$r_buff0_thd1~0_107 v_~x$r_buff0_thd1~0_106)) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_107, ~weak$$choice2~0=v_~weak$$choice2~0_97} OutVars{P0Thread1of1ForFork0_#t~ite22=|v_P0Thread1of1ForFork0_#t~ite22_7|, P0Thread1of1ForFork0_#t~ite21=|v_P0Thread1of1ForFork0_#t~ite21_9|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_106, ~weak$$choice2~0=v_~weak$$choice2~0_97, P0Thread1of1ForFork0_#t~ite23=|v_P0Thread1of1ForFork0_#t~ite23_7|} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite22, P0Thread1of1ForFork0_#t~ite21, ~x$r_buff0_thd1~0, P0Thread1of1ForFork0_#t~ite23] because there is no mapped edge [2019-12-07 18:56:34,493 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1075] [1075] L764-->L764-2: Formula: (let ((.cse0 (= 0 (mod ~x$flush_delayed~0_In923288712 256)))) (or (and (= |P0Thread1of1ForFork0_#t~mem28_In923288712| |P0Thread1of1ForFork0_#t~mem28_Out923288712|) (not .cse0) (= ~x$mem_tmp~0_In923288712 |P0Thread1of1ForFork0_#t~ite29_Out923288712|)) (and (= |P0Thread1of1ForFork0_#t~mem28_Out923288712| (select (select |#memory_int_In923288712| |~#x~0.base_In923288712|) |~#x~0.offset_In923288712|)) (= |P0Thread1of1ForFork0_#t~mem28_Out923288712| |P0Thread1of1ForFork0_#t~ite29_Out923288712|) .cse0))) InVars {P0Thread1of1ForFork0_#t~mem28=|P0Thread1of1ForFork0_#t~mem28_In923288712|, ~x$flush_delayed~0=~x$flush_delayed~0_In923288712, ~#x~0.offset=|~#x~0.offset_In923288712|, ~#x~0.base=|~#x~0.base_In923288712|, #memory_int=|#memory_int_In923288712|, ~x$mem_tmp~0=~x$mem_tmp~0_In923288712} OutVars{P0Thread1of1ForFork0_#t~mem28=|P0Thread1of1ForFork0_#t~mem28_Out923288712|, ~x$flush_delayed~0=~x$flush_delayed~0_In923288712, ~#x~0.offset=|~#x~0.offset_In923288712|, P0Thread1of1ForFork0_#t~ite29=|P0Thread1of1ForFork0_#t~ite29_Out923288712|, ~#x~0.base=|~#x~0.base_In923288712|, #memory_int=|#memory_int_In923288712|, ~x$mem_tmp~0=~x$mem_tmp~0_In923288712} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~mem28, P0Thread1of1ForFork0_#t~ite29] because there is no mapped edge [2019-12-07 18:56:34,494 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1117] [1117] L764-2-->P0EXIT: Formula: (and (= |v_#memory_int_248| (store |v_#memory_int_249| |v_~#x~0.base_160| (store (select |v_#memory_int_249| |v_~#x~0.base_160|) |v_~#x~0.offset_160| |v_P0Thread1of1ForFork0_#t~ite29_28|))) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_49 (+ v_~__unbuffered_cnt~0_50 1)) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= v_~x$flush_delayed~0_92 0)) InVars {~#x~0.offset=|v_~#x~0.offset_160|, P0Thread1of1ForFork0_#t~ite29=|v_P0Thread1of1ForFork0_#t~ite29_28|, #memory_int=|v_#memory_int_249|, ~#x~0.base=|v_~#x~0.base_160|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_50} OutVars{P0Thread1of1ForFork0_#t~mem28=|v_P0Thread1of1ForFork0_#t~mem28_17|, P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, ~x$flush_delayed~0=v_~x$flush_delayed~0_92, ~#x~0.offset=|v_~#x~0.offset_160|, P0Thread1of1ForFork0_#t~ite29=|v_P0Thread1of1ForFork0_#t~ite29_27|, #memory_int=|v_#memory_int_248|, ~#x~0.base=|v_~#x~0.base_160|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_49} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~mem28, P0Thread1of1ForFork0_#res.offset, ~x$flush_delayed~0, P0Thread1of1ForFork0_#t~ite29, #memory_int, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 18:56:34,494 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1103] [1103] L784-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= v_~x$r_buff1_thd2~0_28 |v_P1Thread1of1ForFork1_#t~ite36_22|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_40 1) v_~__unbuffered_cnt~0_39)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40, P1Thread1of1ForFork1_#t~ite36=|v_P1Thread1of1ForFork1_#t~ite36_22|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_28, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_39, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|, P1Thread1of1ForFork1_#t~ite36=|v_P1Thread1of1ForFork1_#t~ite36_21|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#res.base, P1Thread1of1ForFork1_#t~ite36] because there is no mapped edge [2019-12-07 18:56:34,494 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [984] [984] L846-->L848-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_118 256) 0) (= (mod v_~x$r_buff0_thd0~0_14 256) 0)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_118} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_118} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 18:56:34,494 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1098] [1098] L848-2-->L848-5: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff1_thd0~0_In1157152436 256))) (.cse0 (= (mod ~x$w_buff1_used~0_In1157152436 256) 0)) (.cse2 (= |ULTIMATE.start_main_#t~ite75_Out1157152436| |ULTIMATE.start_main_#t~ite76_Out1157152436|))) (or (and (not .cse0) (= ~x$w_buff1~0_In1157152436 |ULTIMATE.start_main_#t~ite75_Out1157152436|) (not .cse1) (= |ULTIMATE.start_main_#t~mem74_In1157152436| |ULTIMATE.start_main_#t~mem74_Out1157152436|) .cse2) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~mem74_Out1157152436| (select (select |#memory_int_In1157152436| |~#x~0.base_In1157152436|) |~#x~0.offset_In1157152436|)) (= |ULTIMATE.start_main_#t~mem74_Out1157152436| |ULTIMATE.start_main_#t~ite75_Out1157152436|) .cse2))) InVars {~#x~0.offset=|~#x~0.offset_In1157152436|, ULTIMATE.start_main_#t~mem74=|ULTIMATE.start_main_#t~mem74_In1157152436|, ~x$w_buff1~0=~x$w_buff1~0_In1157152436, ~#x~0.base=|~#x~0.base_In1157152436|, #memory_int=|#memory_int_In1157152436|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1157152436, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1157152436} OutVars{ULTIMATE.start_main_#t~mem74=|ULTIMATE.start_main_#t~mem74_Out1157152436|, ~#x~0.offset=|~#x~0.offset_In1157152436|, ~x$w_buff1~0=~x$w_buff1~0_In1157152436, ~#x~0.base=|~#x~0.base_In1157152436|, #memory_int=|#memory_int_In1157152436|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1157152436, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1157152436, ULTIMATE.start_main_#t~ite75=|ULTIMATE.start_main_#t~ite75_Out1157152436|, ULTIMATE.start_main_#t~ite76=|ULTIMATE.start_main_#t~ite76_Out1157152436|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem74, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~ite76] because there is no mapped edge [2019-12-07 18:56:34,495 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1080] [1080] L849-->L849-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In-509860780 256) 0)) (.cse1 (= (mod ~x$r_buff0_thd0~0_In-509860780 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite77_Out-509860780| ~x$w_buff0_used~0_In-509860780) (or .cse0 .cse1)) (and (not .cse0) (= |ULTIMATE.start_main_#t~ite77_Out-509860780| 0) (not .cse1)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-509860780, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-509860780} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-509860780, ULTIMATE.start_main_#t~ite77=|ULTIMATE.start_main_#t~ite77_Out-509860780|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-509860780} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite77] because there is no mapped edge [2019-12-07 18:56:34,495 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1082] [1082] L850-->L850-2: Formula: (let ((.cse0 (= (mod ~x$r_buff0_thd0~0_In-1588447602 256) 0)) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In-1588447602 256))) (.cse2 (= 0 (mod ~x$r_buff1_thd0~0_In-1588447602 256))) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In-1588447602 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite78_Out-1588447602| ~x$w_buff1_used~0_In-1588447602)) (and (= |ULTIMATE.start_main_#t~ite78_Out-1588447602| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1588447602, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1588447602, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1588447602, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1588447602} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1588447602, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1588447602, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1588447602, ULTIMATE.start_main_#t~ite78=|ULTIMATE.start_main_#t~ite78_Out-1588447602|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1588447602} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite78] because there is no mapped edge [2019-12-07 18:56:34,496 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1078] [1078] L851-->L852: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd0~0_In-560048461 256) 0)) (.cse0 (= (mod ~x$w_buff0_used~0_In-560048461 256) 0)) (.cse2 (= ~x$r_buff0_thd0~0_In-560048461 ~x$r_buff0_thd0~0_Out-560048461))) (or (and (not .cse0) (not .cse1) (= 0 ~x$r_buff0_thd0~0_Out-560048461)) (and .cse1 .cse2) (and .cse0 .cse2))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-560048461, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-560048461} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_Out-560048461, ULTIMATE.start_main_#t~ite79=|ULTIMATE.start_main_#t~ite79_Out-560048461|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-560048461} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite79] because there is no mapped edge [2019-12-07 18:56:34,496 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1096] [1096] L852-->L856: Formula: (let ((.cse4 (= ~x$r_buff1_thd0~0_Out-1607730897 0)) (.cse6 (= 0 (mod ~x$r_buff0_thd0~0_In-1607730897 256))) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In-1607730897 256))) (.cse0 (= |ULTIMATE.start_main_#t~nondet81_In-1607730897| ~weak$$choice1~0_Out-1607730897)) (.cse1 (= (mod ~x$w_buff0_used~0_In-1607730897 256) 0)) (.cse5 (= (mod ~x$r_buff1_thd0~0_In-1607730897 256) 0)) (.cse2 (= ~x$r_buff1_thd0~0_Out-1607730897 ~x$r_buff1_thd0~0_In-1607730897))) (or (and .cse0 .cse1 .cse2 .cse3) (and .cse4 .cse0 (not .cse5) (not .cse3)) (and .cse0 .cse5 .cse2 .cse6) (and .cse4 (not .cse6) .cse0 (not .cse1)) (and .cse0 .cse2 .cse6 .cse3) (and .cse0 .cse1 .cse5 .cse2))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1607730897, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1607730897, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1607730897, ULTIMATE.start_main_#t~nondet81=|ULTIMATE.start_main_#t~nondet81_In-1607730897|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1607730897} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1607730897, ~weak$$choice1~0=~weak$$choice1~0_Out-1607730897, ULTIMATE.start_main_#t~ite80=|ULTIMATE.start_main_#t~ite80_Out-1607730897|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1607730897, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_Out-1607730897, ULTIMATE.start_main_#t~nondet81=|ULTIMATE.start_main_#t~nondet81_Out-1607730897|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1607730897} AuxVars[] AssignedVars[~weak$$choice1~0, ULTIMATE.start_main_#t~ite80, ~x$r_buff1_thd0~0, ULTIMATE.start_main_#t~nondet81] because there is no mapped edge [2019-12-07 18:56:34,496 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1069] [1069] L856-->L856-3: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice1~0_In-1414484392 256))) (.cse1 (not (= (mod ~__unbuffered_p2_EAX$read_delayed~0_In-1414484392 256) 0)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~mem82_Out-1414484392| |ULTIMATE.start_main_#t~ite83_Out-1414484392|) (= (select (select |#memory_int_In-1414484392| ~__unbuffered_p2_EAX$read_delayed_var~0.base_In-1414484392) ~__unbuffered_p2_EAX$read_delayed_var~0.offset_In-1414484392) |ULTIMATE.start_main_#t~mem82_Out-1414484392|) .cse1) (and (= ~__unbuffered_p2_EAX~0_In-1414484392 |ULTIMATE.start_main_#t~ite83_Out-1414484392|) (= |ULTIMATE.start_main_#t~mem82_In-1414484392| |ULTIMATE.start_main_#t~mem82_Out-1414484392|) .cse0 .cse1))) InVars {~weak$$choice1~0=~weak$$choice1~0_In-1414484392, ~__unbuffered_p2_EAX$read_delayed_var~0.offset=~__unbuffered_p2_EAX$read_delayed_var~0.offset_In-1414484392, ~__unbuffered_p2_EAX$read_delayed_var~0.base=~__unbuffered_p2_EAX$read_delayed_var~0.base_In-1414484392, ULTIMATE.start_main_#t~mem82=|ULTIMATE.start_main_#t~mem82_In-1414484392|, #memory_int=|#memory_int_In-1414484392|, ~__unbuffered_p2_EAX~0=~__unbuffered_p2_EAX~0_In-1414484392, ~__unbuffered_p2_EAX$read_delayed~0=~__unbuffered_p2_EAX$read_delayed~0_In-1414484392} OutVars{ULTIMATE.start_main_#t~ite83=|ULTIMATE.start_main_#t~ite83_Out-1414484392|, ~weak$$choice1~0=~weak$$choice1~0_In-1414484392, ~__unbuffered_p2_EAX$read_delayed_var~0.offset=~__unbuffered_p2_EAX$read_delayed_var~0.offset_In-1414484392, ULTIMATE.start_main_#t~mem82=|ULTIMATE.start_main_#t~mem82_Out-1414484392|, ~__unbuffered_p2_EAX$read_delayed_var~0.base=~__unbuffered_p2_EAX$read_delayed_var~0.base_In-1414484392, #memory_int=|#memory_int_In-1414484392|, ~__unbuffered_p2_EAX~0=~__unbuffered_p2_EAX~0_In-1414484392, ~__unbuffered_p2_EAX$read_delayed~0=~__unbuffered_p2_EAX$read_delayed~0_In-1414484392} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite83, ULTIMATE.start_main_#t~mem82] because there is no mapped edge [2019-12-07 18:56:34,496 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1130] [1130] L856-3-->L5: Formula: (and (= (mod v_~main$tmp_guard1~0_21 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|) (let ((.cse3 (= v_~__unbuffered_p2_EBX~0_21 0)) (.cse1 (= 1 v_~__unbuffered_p2_EAX~0_46)) (.cse0 (= v_~main$tmp_guard1~0_21 1)) (.cse4 (= 0 v_~__unbuffered_p0_EAX~0_48)) (.cse2 (= |v_ULTIMATE.start_main_#t~ite83_36| v_~__unbuffered_p2_EAX~0_46))) (or (and .cse0 (not .cse1) .cse2) (and .cse0 (not .cse3) .cse2) (and (= v_~main$tmp_guard1~0_21 0) .cse3 .cse1 .cse4 .cse2) (and .cse0 (not .cse4) .cse2)))) InVars {~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_48, ULTIMATE.start_main_#t~ite83=|v_ULTIMATE.start_main_#t~ite83_36|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_21} OutVars{ULTIMATE.start_main_#t~ite84=|v_ULTIMATE.start_main_#t~ite84_33|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_48, ULTIMATE.start_main_#t~ite83=|v_ULTIMATE.start_main_#t~ite83_35|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_21, ULTIMATE.start_main_#t~mem82=|v_ULTIMATE.start_main_#t~mem82_27|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_46, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite84, ULTIMATE.start_main_#t~ite83, ULTIMATE.start___VERIFIER_assert_~expression, ULTIMATE.start_main_#t~mem82, ~main$tmp_guard1~0, ~__unbuffered_p2_EAX~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:56:34,497 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1131] [1131] L5-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:56:34,569 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_6f9e0693-3f0e-474e-9592-a620d1d4cf1b/bin/uautomizer/witness.graphml [2019-12-07 18:56:34,569 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:56:34,570 INFO L168 Benchmark]: Toolchain (without parser) took 559489.86 ms. Allocated memory was 1.0 GB in the beginning and 6.2 GB in the end (delta: 5.1 GB). Free memory was 934.4 MB in the beginning and 1.1 GB in the end (delta: -159.8 MB). Peak memory consumption was 5.0 GB. Max. memory is 11.5 GB. [2019-12-07 18:56:34,570 INFO L168 Benchmark]: CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 955.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:56:34,570 INFO L168 Benchmark]: CACSL2BoogieTranslator took 399.09 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 109.6 MB). Free memory was 934.4 MB in the beginning and 1.1 GB in the end (delta: -137.4 MB). Peak memory consumption was 18.5 MB. Max. memory is 11.5 GB. [2019-12-07 18:56:34,570 INFO L168 Benchmark]: Boogie Procedure Inliner took 37.87 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:56:34,570 INFO L168 Benchmark]: Boogie Preprocessor took 29.57 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:56:34,571 INFO L168 Benchmark]: RCFGBuilder took 485.02 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 999.4 MB in the end (delta: 67.0 MB). Peak memory consumption was 67.0 MB. Max. memory is 11.5 GB. [2019-12-07 18:56:34,571 INFO L168 Benchmark]: TraceAbstraction took 558440.13 ms. Allocated memory was 1.1 GB in the beginning and 6.2 GB in the end (delta: 5.0 GB). Free memory was 999.4 MB in the beginning and 1.2 GB in the end (delta: -183.7 MB). Peak memory consumption was 4.9 GB. Max. memory is 11.5 GB. [2019-12-07 18:56:34,571 INFO L168 Benchmark]: Witness Printer took 95.17 ms. Allocated memory is still 6.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 88.8 MB). Peak memory consumption was 88.8 MB. Max. memory is 11.5 GB. [2019-12-07 18:56:34,572 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 955.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 399.09 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 109.6 MB). Free memory was 934.4 MB in the beginning and 1.1 GB in the end (delta: -137.4 MB). Peak memory consumption was 18.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 37.87 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 29.57 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 485.02 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 999.4 MB in the end (delta: 67.0 MB). Peak memory consumption was 67.0 MB. Max. memory is 11.5 GB. * TraceAbstraction took 558440.13 ms. Allocated memory was 1.1 GB in the beginning and 6.2 GB in the end (delta: 5.0 GB). Free memory was 999.4 MB in the beginning and 1.2 GB in the end (delta: -183.7 MB). Peak memory consumption was 4.9 GB. Max. memory is 11.5 GB. * Witness Printer took 95.17 ms. Allocated memory is still 6.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 88.8 MB). Peak memory consumption was 88.8 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 4.3s, 223 ProgramPointsBefore, 117 ProgramPointsAfterwards, 276 TransitionsBefore, 138 TransitionsAfterwards, 32976 CoEnabledTransitionPairs, 8 FixpointIterations, 50 TrivialSequentialCompositions, 34 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 62 ConcurrentYvCompositions, 36 ChoiceCompositions, 12209 VarBasedMoverChecksPositive, 278 VarBasedMoverChecksNegative, 32 SemBasedMoverChecksPositive, 347 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.0s, 0 MoverChecksTotal, 183707 CheckedPairsTotal, 146 TotalNumberOfCompositions - CounterExampleResult [Line: 5]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L838] FCALL, FORK 0 pthread_create(&t2461, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L840] FCALL, FORK 0 pthread_create(&t2462, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L842] FCALL, FORK 0 pthread_create(&t2463, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L794] 3 weak$$choice0 = __VERIFIER_nondet_bool() [L795] 3 weak$$choice2 = __VERIFIER_nondet_bool() [L796] 3 x$flush_delayed = weak$$choice2 [L797] EXPR 3 \read(x) [L797] 3 x$mem_tmp = x [L777] 2 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice1=0, weak$$choice2=1, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L780] 2 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice1=0, weak$$choice2=1, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L798] EXPR 3 !x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : x$w_buff1) [L798] EXPR 3 \read(x) [L798] EXPR 3 !x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : x$w_buff1) VAL [!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : x$w_buff1)=1, \read(x)=1, __unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice1=0, weak$$choice2=1, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L798] 3 x = !x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : x$w_buff1) [L781] 2 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L782] 2 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L799] EXPR 3 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : x$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : x$w_buff0))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L799] 3 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : x$w_buff0)) [L800] EXPR 3 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff1 : x$w_buff1)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff1 : x$w_buff1))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L800] 3 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff1 : x$w_buff1)) [L801] EXPR 3 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$w_buff0_used)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$w_buff0_used))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L801] 3 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$w_buff0_used)) [L802] EXPR 3 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : (_Bool)0))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L802] 3 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L804] EXPR 3 weak$$choice2 ? x$r_buff1_thd3 : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$r_buff1_thd3 : (x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$r_buff1_thd3 : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$r_buff1_thd3 : (x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : (_Bool)0))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L804] 3 x$r_buff1_thd3 = weak$$choice2 ? x$r_buff1_thd3 : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$r_buff1_thd3 : (x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L805] 3 __unbuffered_p2_EAX$read_delayed = (_Bool)1 [L806] 3 __unbuffered_p2_EAX$read_delayed_var = &x [L807] EXPR 3 \read(x) [L807] 3 __unbuffered_p2_EAX = x [L808] 3 x = x$flush_delayed ? x$mem_tmp : x [L809] 3 x$flush_delayed = (_Bool)0 [L812] 3 __unbuffered_p2_EBX = y VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={6:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice1=0, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L747] 1 y = 1 [L752] 1 weak$$choice0 = __VERIFIER_nondet_bool() [L753] 1 weak$$choice2 = __VERIFIER_nondet_bool() [L754] 1 x$flush_delayed = weak$$choice2 [L755] EXPR 1 \read(x) [L755] 1 x$mem_tmp = x [L756] EXPR 1 !x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : x$w_buff1) [L756] EXPR 1 \read(x) [L756] EXPR 1 !x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : x$w_buff1) VAL [!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : x$w_buff1)=0, \read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={6:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice1=0, weak$$choice2=1, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L756] 1 x = !x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : x$w_buff1) [L757] EXPR 1 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : x$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={6:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : x$w_buff0))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L815] 3 x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd3 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={6:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : x$w_buff0))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L757] 1 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : x$w_buff0)) [L816] 3 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$w_buff0_used [L817] 3 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd3 || x$w_buff1_used && x$r_buff1_thd3 ? (_Bool)0 : x$w_buff1_used [L758] EXPR 1 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff1 : x$w_buff1)) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={6:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff1 : x$w_buff1))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L758] 1 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff1 : x$w_buff1)) [L759] EXPR 1 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used)) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={6:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L759] 1 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used)) [L760] EXPR 1 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={6:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : (_Bool)0))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L760] 1 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : (_Bool)0)) [L762] EXPR 1 weak$$choice2 ? x$r_buff1_thd1 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$r_buff1_thd1 : (x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={6:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$r_buff1_thd1 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$r_buff1_thd1 : (x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : (_Bool)0))=0, x={6:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L762] 1 x$r_buff1_thd1 = weak$$choice2 ? x$r_buff1_thd1 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$r_buff1_thd1 : (x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : (_Bool)0)) [L763] EXPR 1 \read(x) [L763] 1 __unbuffered_p0_EAX = x [L844] 0 main$tmp_guard0 = __unbuffered_cnt == 3 VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={6:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=8, weak$$choice1=0, weak$$choice2=1, x={6:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L848] 0 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L849] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L850] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 214 locations, 1 error locations. Result: UNSAFE, OverallTime: 558.2s, OverallIterations: 97, TraceHistogramMax: 1, AutomataDifference: 345.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 29839 SDtfs, 57488 SDslu, 350738 SDs, 0 SdLazy, 262459 SolverSat, 6255 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 198.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 4469 GetRequests, 249 SyntacticMatches, 126 SemanticMatches, 4094 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 50436 ImplicationChecksByTransitivity, 124.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=300418occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 76.1s AutomataMinimizationTime, 96 MinimizatonAttempts, 477766 StatesRemovedByMinimization, 88 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.2s SsaConstructionTime, 1.8s SatisfiabilityAnalysisTime, 39.7s InterpolantComputationTime, 6758 NumberOfCodeBlocks, 6758 NumberOfCodeBlocksAsserted, 97 NumberOfCheckSat, 6590 ConstructedInterpolants, 0 QuantifiedInterpolants, 8642820 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 96 InterpolantComputations, 96 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...