./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe028_rmo.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_b4a9cf03-0b0a-4e8f-b082-244f8da00a06/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_b4a9cf03-0b0a-4e8f-b082-244f8da00a06/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_b4a9cf03-0b0a-4e8f-b082-244f8da00a06/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_b4a9cf03-0b0a-4e8f-b082-244f8da00a06/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe028_rmo.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_b4a9cf03-0b0a-4e8f-b082-244f8da00a06/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_b4a9cf03-0b0a-4e8f-b082-244f8da00a06/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 7691712e227ff65b6d2a01f318faf99cbd68ed56 ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 17:36:32,756 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 17:36:32,757 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 17:36:32,765 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 17:36:32,765 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 17:36:32,766 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 17:36:32,767 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 17:36:32,768 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 17:36:32,769 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 17:36:32,770 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 17:36:32,771 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 17:36:32,771 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 17:36:32,772 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 17:36:32,772 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 17:36:32,773 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 17:36:32,774 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 17:36:32,774 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 17:36:32,775 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 17:36:32,776 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 17:36:32,778 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 17:36:32,779 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 17:36:32,780 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 17:36:32,780 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 17:36:32,781 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 17:36:32,782 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 17:36:32,782 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 17:36:32,783 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 17:36:32,783 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 17:36:32,783 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 17:36:32,784 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 17:36:32,784 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 17:36:32,784 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 17:36:32,785 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 17:36:32,785 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 17:36:32,786 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 17:36:32,786 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 17:36:32,786 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 17:36:32,786 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 17:36:32,787 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 17:36:32,787 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 17:36:32,787 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 17:36:32,788 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_b4a9cf03-0b0a-4e8f-b082-244f8da00a06/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 17:36:32,797 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 17:36:32,797 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 17:36:32,798 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 17:36:32,798 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 17:36:32,798 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 17:36:32,798 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 17:36:32,798 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 17:36:32,798 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 17:36:32,799 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 17:36:32,799 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 17:36:32,799 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 17:36:32,799 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 17:36:32,799 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 17:36:32,799 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 17:36:32,799 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 17:36:32,799 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 17:36:32,799 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 17:36:32,799 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 17:36:32,800 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 17:36:32,800 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 17:36:32,800 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 17:36:32,800 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:36:32,800 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 17:36:32,800 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 17:36:32,800 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 17:36:32,800 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 17:36:32,800 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 17:36:32,801 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 17:36:32,801 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 17:36:32,801 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_b4a9cf03-0b0a-4e8f-b082-244f8da00a06/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 7691712e227ff65b6d2a01f318faf99cbd68ed56 [2019-12-07 17:36:32,900 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 17:36:32,908 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 17:36:32,911 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 17:36:32,912 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 17:36:32,913 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 17:36:32,913 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_b4a9cf03-0b0a-4e8f-b082-244f8da00a06/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe028_rmo.opt.i [2019-12-07 17:36:32,956 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_b4a9cf03-0b0a-4e8f-b082-244f8da00a06/bin/uautomizer/data/e058d96fe/af4f437f81fb45c68cbc17115b0fee60/FLAG2c6b5ca89 [2019-12-07 17:36:33,388 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 17:36:33,388 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_b4a9cf03-0b0a-4e8f-b082-244f8da00a06/sv-benchmarks/c/pthread-wmm/safe028_rmo.opt.i [2019-12-07 17:36:33,399 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_b4a9cf03-0b0a-4e8f-b082-244f8da00a06/bin/uautomizer/data/e058d96fe/af4f437f81fb45c68cbc17115b0fee60/FLAG2c6b5ca89 [2019-12-07 17:36:33,755 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_b4a9cf03-0b0a-4e8f-b082-244f8da00a06/bin/uautomizer/data/e058d96fe/af4f437f81fb45c68cbc17115b0fee60 [2019-12-07 17:36:33,761 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 17:36:33,763 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 17:36:33,764 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 17:36:33,764 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 17:36:33,769 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 17:36:33,769 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:36:33" (1/1) ... [2019-12-07 17:36:33,772 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@375546ab and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:36:33, skipping insertion in model container [2019-12-07 17:36:33,772 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:36:33" (1/1) ... [2019-12-07 17:36:33,777 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 17:36:33,805 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 17:36:34,067 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:36:34,074 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 17:36:34,119 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:36:34,168 INFO L208 MainTranslator]: Completed translation [2019-12-07 17:36:34,169 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:36:34 WrapperNode [2019-12-07 17:36:34,169 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 17:36:34,169 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 17:36:34,170 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 17:36:34,170 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 17:36:34,175 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:36:34" (1/1) ... [2019-12-07 17:36:34,189 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:36:34" (1/1) ... [2019-12-07 17:36:34,206 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 17:36:34,207 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 17:36:34,207 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 17:36:34,207 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 17:36:34,213 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:36:34" (1/1) ... [2019-12-07 17:36:34,213 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:36:34" (1/1) ... [2019-12-07 17:36:34,218 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:36:34" (1/1) ... [2019-12-07 17:36:34,219 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:36:34" (1/1) ... [2019-12-07 17:36:34,231 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:36:34" (1/1) ... [2019-12-07 17:36:34,234 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:36:34" (1/1) ... [2019-12-07 17:36:34,237 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:36:34" (1/1) ... [2019-12-07 17:36:34,241 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 17:36:34,241 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 17:36:34,241 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 17:36:34,241 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 17:36:34,242 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:36:34" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b4a9cf03-0b0a-4e8f-b082-244f8da00a06/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:36:34,283 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-12-07 17:36:34,283 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 17:36:34,283 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 17:36:34,283 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 17:36:34,283 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 17:36:34,283 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 17:36:34,284 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 17:36:34,284 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 17:36:34,284 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 17:36:34,284 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 17:36:34,284 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 17:36:34,284 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2019-12-07 17:36:34,284 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 17:36:34,284 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 17:36:34,284 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 17:36:34,285 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 17:36:34,710 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 17:36:34,711 INFO L287 CfgBuilder]: Removed 6 assume(true) statements. [2019-12-07 17:36:34,711 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:36:34 BoogieIcfgContainer [2019-12-07 17:36:34,712 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 17:36:34,712 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 17:36:34,712 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 17:36:34,714 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 17:36:34,714 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 05:36:33" (1/3) ... [2019-12-07 17:36:34,715 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1d63ec22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:36:34, skipping insertion in model container [2019-12-07 17:36:34,715 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:36:34" (2/3) ... [2019-12-07 17:36:34,715 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1d63ec22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:36:34, skipping insertion in model container [2019-12-07 17:36:34,715 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:36:34" (3/3) ... [2019-12-07 17:36:34,716 INFO L109 eAbstractionObserver]: Analyzing ICFG safe028_rmo.opt.i [2019-12-07 17:36:34,722 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 17:36:34,722 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 17:36:34,727 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-12-07 17:36:34,727 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 17:36:34,756 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,756 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~nondet3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,756 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~nondet4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,756 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,756 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~mem5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,757 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,757 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~nondet3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,757 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~nondet4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,757 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,757 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,757 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~mem6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,758 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,758 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,758 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,758 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~mem6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,758 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,758 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,758 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,758 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,758 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,758 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,759 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,759 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,759 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,759 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,759 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,759 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,759 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,759 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,759 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,760 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,760 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,760 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,760 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,760 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,760 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,760 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,760 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,760 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,761 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,761 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,761 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,761 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,761 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,761 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,761 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,761 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,761 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,761 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,762 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,762 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,762 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,762 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,762 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,762 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,762 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,762 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,762 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,762 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,763 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,763 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,763 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,763 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,763 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,763 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,763 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,763 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,763 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,764 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,764 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,764 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,764 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,764 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,764 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,764 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,764 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,764 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,765 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,765 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,765 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,765 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,765 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,765 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~mem27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,765 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,765 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,765 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,765 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,766 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~mem28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,766 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,766 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,766 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,766 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,766 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,766 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,766 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~mem28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,766 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,767 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,767 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,767 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,767 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,767 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,767 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,767 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,767 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,768 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,768 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,768 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,768 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,768 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,768 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,768 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,768 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,768 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,769 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,769 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,769 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,769 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,769 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,769 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,769 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,769 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,769 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,769 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,770 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,770 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,770 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,770 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,770 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,770 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,770 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,770 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,770 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,771 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,771 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,771 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~nondet37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,771 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~nondet38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,771 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,771 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,772 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~nondet37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,772 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,772 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~nondet38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,772 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,772 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,772 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,772 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,772 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,772 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,772 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,773 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,773 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,773 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,773 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,773 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,773 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,773 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,773 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,773 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,773 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,774 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,774 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,774 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,774 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,774 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,774 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,774 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,774 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,774 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,774 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,774 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,775 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,775 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,775 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,775 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,775 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,775 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,775 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,775 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,775 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,776 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,776 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,776 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,776 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,776 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,776 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,776 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,776 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,776 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,776 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,777 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,777 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,777 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,777 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,777 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,777 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite57| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,777 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,777 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,777 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,777 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,778 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite57| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,778 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,778 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite57| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,778 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,778 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,778 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,778 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,778 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,778 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,778 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite57| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,778 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,779 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,779 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,779 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,779 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,779 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,779 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,779 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,779 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,779 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,779 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,780 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,780 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,780 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,780 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,780 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,780 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,780 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,780 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,780 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,780 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,781 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,781 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,781 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,781 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,781 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,781 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,781 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,781 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,781 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,781 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite67| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,781 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite67| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,782 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,782 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,782 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite67| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,782 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite67| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,782 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite68| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,782 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite68| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,782 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite68| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,782 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite68| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,782 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite69| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,782 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite69| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,783 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite69| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,783 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite69| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,783 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite70| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,783 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite70| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,783 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite70| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,783 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite70| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,783 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,783 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:36:34,794 INFO L249 AbstractCegarLoop]: Starting to check reachability of 4 error locations. [2019-12-07 17:36:34,807 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 17:36:34,807 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 17:36:34,807 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 17:36:34,807 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 17:36:34,807 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 17:36:34,807 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 17:36:34,808 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 17:36:34,808 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 17:36:34,819 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 223 places, 276 transitions [2019-12-07 17:36:34,821 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 223 places, 276 transitions [2019-12-07 17:36:34,896 INFO L134 PetriNetUnfolder]: 63/273 cut-off events. [2019-12-07 17:36:34,896 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 17:36:34,908 INFO L76 FinitePrefix]: Finished finitePrefix Result has 283 conditions, 273 events. 63/273 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 14. Compared 1060 event pairs. 9/218 useless extension candidates. Maximal degree in co-relation 225. Up to 2 conditions per place. [2019-12-07 17:36:34,940 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 223 places, 276 transitions [2019-12-07 17:36:34,990 INFO L134 PetriNetUnfolder]: 63/273 cut-off events. [2019-12-07 17:36:34,990 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 17:36:35,001 INFO L76 FinitePrefix]: Finished finitePrefix Result has 283 conditions, 273 events. 63/273 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 14. Compared 1060 event pairs. 9/218 useless extension candidates. Maximal degree in co-relation 225. Up to 2 conditions per place. [2019-12-07 17:36:35,031 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 32976 [2019-12-07 17:36:35,032 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 17:36:39,030 WARN L192 SmtUtils]: Spent 325.00 ms on a formula simplification. DAG size of input: 136 DAG size of output: 132 [2019-12-07 17:36:39,187 WARN L192 SmtUtils]: Spent 155.00 ms on a formula simplification that was a NOOP. DAG size: 130 [2019-12-07 17:36:39,216 INFO L206 etLargeBlockEncoding]: Checked pairs total: 183707 [2019-12-07 17:36:39,216 INFO L214 etLargeBlockEncoding]: Total number of compositions: 146 [2019-12-07 17:36:39,219 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 117 places, 138 transitions [2019-12-07 17:38:12,246 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 300418 states. [2019-12-07 17:38:12,247 INFO L276 IsEmpty]: Start isEmpty. Operand 300418 states. [2019-12-07 17:38:12,287 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2019-12-07 17:38:12,287 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:38:12,288 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:38:12,288 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:38:12,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:38:12,292 INFO L82 PathProgramCache]: Analyzing trace with hash -2075695311, now seen corresponding path program 1 times [2019-12-07 17:38:12,298 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:38:12,298 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317791173] [2019-12-07 17:38:12,298 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:38:12,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:38:12,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:38:12,505 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317791173] [2019-12-07 17:38:12,505 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:38:12,506 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:38:12,506 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1990279489] [2019-12-07 17:38:12,510 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:38:12,510 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:38:12,519 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:38:12,519 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:38:12,521 INFO L87 Difference]: Start difference. First operand 300418 states. Second operand 3 states. [2019-12-07 17:38:14,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:38:14,094 INFO L93 Difference]: Finished difference Result 300418 states and 1374458 transitions. [2019-12-07 17:38:14,095 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:38:14,096 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 17 [2019-12-07 17:38:14,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:38:15,294 INFO L225 Difference]: With dead ends: 300418 [2019-12-07 17:38:15,295 INFO L226 Difference]: Without dead ends: 281698 [2019-12-07 17:38:15,296 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:38:40,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281698 states. [2019-12-07 17:38:44,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281698 to 281698. [2019-12-07 17:38:44,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 281698 states. [2019-12-07 17:38:45,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 281698 states to 281698 states and 1288736 transitions. [2019-12-07 17:38:45,238 INFO L78 Accepts]: Start accepts. Automaton has 281698 states and 1288736 transitions. Word has length 17 [2019-12-07 17:38:45,239 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:38:45,239 INFO L462 AbstractCegarLoop]: Abstraction has 281698 states and 1288736 transitions. [2019-12-07 17:38:45,239 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:38:45,239 INFO L276 IsEmpty]: Start isEmpty. Operand 281698 states and 1288736 transitions. [2019-12-07 17:38:45,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2019-12-07 17:38:45,266 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:38:45,266 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:38:45,266 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:38:45,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:38:45,266 INFO L82 PathProgramCache]: Analyzing trace with hash 1282420922, now seen corresponding path program 1 times [2019-12-07 17:38:45,267 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:38:45,267 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1465635230] [2019-12-07 17:38:45,267 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:38:45,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:38:45,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:38:45,336 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1465635230] [2019-12-07 17:38:45,336 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:38:45,336 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:38:45,336 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1542321223] [2019-12-07 17:38:45,337 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:38:45,337 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:38:45,337 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:38:45,337 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:38:45,338 INFO L87 Difference]: Start difference. First operand 281698 states and 1288736 transitions. Second operand 4 states. [2019-12-07 17:38:45,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:38:45,647 INFO L93 Difference]: Finished difference Result 71266 states and 271018 transitions. [2019-12-07 17:38:45,648 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 17:38:45,648 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 18 [2019-12-07 17:38:45,648 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:38:45,761 INFO L225 Difference]: With dead ends: 71266 [2019-12-07 17:38:45,762 INFO L226 Difference]: Without dead ends: 52546 [2019-12-07 17:38:45,762 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:38:46,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52546 states. [2019-12-07 17:38:46,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52546 to 52546. [2019-12-07 17:38:46,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52546 states. [2019-12-07 17:38:46,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52546 states to 52546 states and 187648 transitions. [2019-12-07 17:38:46,961 INFO L78 Accepts]: Start accepts. Automaton has 52546 states and 187648 transitions. Word has length 18 [2019-12-07 17:38:46,962 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:38:46,962 INFO L462 AbstractCegarLoop]: Abstraction has 52546 states and 187648 transitions. [2019-12-07 17:38:46,962 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:38:46,962 INFO L276 IsEmpty]: Start isEmpty. Operand 52546 states and 187648 transitions. [2019-12-07 17:38:46,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 17:38:46,980 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:38:46,980 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:38:46,981 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:38:46,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:38:46,981 INFO L82 PathProgramCache]: Analyzing trace with hash 285755223, now seen corresponding path program 1 times [2019-12-07 17:38:46,981 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:38:46,981 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [326085060] [2019-12-07 17:38:46,981 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:38:47,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:38:47,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:38:47,052 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [326085060] [2019-12-07 17:38:47,052 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:38:47,052 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:38:47,052 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1877376817] [2019-12-07 17:38:47,052 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:38:47,052 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:38:47,052 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:38:47,053 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:38:47,053 INFO L87 Difference]: Start difference. First operand 52546 states and 187648 transitions. Second operand 3 states. [2019-12-07 17:38:47,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:38:47,230 INFO L93 Difference]: Finished difference Result 49978 states and 176124 transitions. [2019-12-07 17:38:47,231 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:38:47,231 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-12-07 17:38:47,231 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:38:47,354 INFO L225 Difference]: With dead ends: 49978 [2019-12-07 17:38:47,355 INFO L226 Difference]: Without dead ends: 49978 [2019-12-07 17:38:47,355 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:38:49,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49978 states. [2019-12-07 17:38:50,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49978 to 49978. [2019-12-07 17:38:50,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49978 states. [2019-12-07 17:38:50,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49978 states to 49978 states and 176124 transitions. [2019-12-07 17:38:50,207 INFO L78 Accepts]: Start accepts. Automaton has 49978 states and 176124 transitions. Word has length 28 [2019-12-07 17:38:50,207 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:38:50,207 INFO L462 AbstractCegarLoop]: Abstraction has 49978 states and 176124 transitions. [2019-12-07 17:38:50,207 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:38:50,207 INFO L276 IsEmpty]: Start isEmpty. Operand 49978 states and 176124 transitions. [2019-12-07 17:38:50,224 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-12-07 17:38:50,224 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:38:50,224 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:38:50,224 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:38:50,224 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:38:50,224 INFO L82 PathProgramCache]: Analyzing trace with hash -1493897438, now seen corresponding path program 1 times [2019-12-07 17:38:50,225 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:38:50,225 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305037633] [2019-12-07 17:38:50,225 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:38:50,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:38:50,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:38:50,315 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1305037633] [2019-12-07 17:38:50,315 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:38:50,315 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:38:50,316 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1422384925] [2019-12-07 17:38:50,316 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:38:50,316 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:38:50,316 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:38:50,317 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:38:50,317 INFO L87 Difference]: Start difference. First operand 49978 states and 176124 transitions. Second operand 5 states. [2019-12-07 17:38:50,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:38:50,420 INFO L93 Difference]: Finished difference Result 21608 states and 73711 transitions. [2019-12-07 17:38:50,420 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:38:50,420 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 29 [2019-12-07 17:38:50,420 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:38:50,450 INFO L225 Difference]: With dead ends: 21608 [2019-12-07 17:38:50,450 INFO L226 Difference]: Without dead ends: 19332 [2019-12-07 17:38:50,450 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:38:50,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19332 states. [2019-12-07 17:38:50,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19332 to 19332. [2019-12-07 17:38:50,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19332 states. [2019-12-07 17:38:50,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19332 states to 19332 states and 65883 transitions. [2019-12-07 17:38:50,879 INFO L78 Accepts]: Start accepts. Automaton has 19332 states and 65883 transitions. Word has length 29 [2019-12-07 17:38:50,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:38:50,879 INFO L462 AbstractCegarLoop]: Abstraction has 19332 states and 65883 transitions. [2019-12-07 17:38:50,879 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:38:50,879 INFO L276 IsEmpty]: Start isEmpty. Operand 19332 states and 65883 transitions. [2019-12-07 17:38:50,904 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-12-07 17:38:50,904 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:38:50,904 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:38:50,904 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:38:50,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:38:50,905 INFO L82 PathProgramCache]: Analyzing trace with hash -541366890, now seen corresponding path program 1 times [2019-12-07 17:38:50,905 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:38:50,905 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [993017693] [2019-12-07 17:38:50,905 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:38:50,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:38:50,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:38:50,978 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [993017693] [2019-12-07 17:38:50,978 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:38:50,978 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:38:50,978 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1714285213] [2019-12-07 17:38:50,979 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:38:50,979 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:38:50,979 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:38:50,979 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:38:50,979 INFO L87 Difference]: Start difference. First operand 19332 states and 65883 transitions. Second operand 6 states. [2019-12-07 17:38:51,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:38:51,072 INFO L93 Difference]: Finished difference Result 18215 states and 63249 transitions. [2019-12-07 17:38:51,072 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:38:51,072 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 45 [2019-12-07 17:38:51,072 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:38:51,097 INFO L225 Difference]: With dead ends: 18215 [2019-12-07 17:38:51,097 INFO L226 Difference]: Without dead ends: 18128 [2019-12-07 17:38:51,097 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:38:51,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18128 states. [2019-12-07 17:38:51,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18128 to 18128. [2019-12-07 17:38:51,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18128 states. [2019-12-07 17:38:51,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18128 states to 18128 states and 63053 transitions. [2019-12-07 17:38:51,490 INFO L78 Accepts]: Start accepts. Automaton has 18128 states and 63053 transitions. Word has length 45 [2019-12-07 17:38:51,491 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:38:51,491 INFO L462 AbstractCegarLoop]: Abstraction has 18128 states and 63053 transitions. [2019-12-07 17:38:51,491 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:38:51,491 INFO L276 IsEmpty]: Start isEmpty. Operand 18128 states and 63053 transitions. [2019-12-07 17:38:51,514 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 17:38:51,514 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:38:51,514 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:38:51,514 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:38:51,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:38:51,515 INFO L82 PathProgramCache]: Analyzing trace with hash -1488532936, now seen corresponding path program 1 times [2019-12-07 17:38:51,515 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:38:51,515 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [50118678] [2019-12-07 17:38:51,515 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:38:51,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:38:51,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:38:51,579 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [50118678] [2019-12-07 17:38:51,580 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:38:51,580 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:38:51,580 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2114923631] [2019-12-07 17:38:51,580 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:38:51,580 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:38:51,580 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:38:51,580 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:38:51,581 INFO L87 Difference]: Start difference. First operand 18128 states and 63053 transitions. Second operand 3 states. [2019-12-07 17:38:51,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:38:51,659 INFO L93 Difference]: Finished difference Result 17744 states and 61429 transitions. [2019-12-07 17:38:51,659 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:38:51,659 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 70 [2019-12-07 17:38:51,660 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:38:51,684 INFO L225 Difference]: With dead ends: 17744 [2019-12-07 17:38:51,684 INFO L226 Difference]: Without dead ends: 17744 [2019-12-07 17:38:51,684 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:38:51,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17744 states. [2019-12-07 17:38:52,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17744 to 17744. [2019-12-07 17:38:52,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17744 states. [2019-12-07 17:38:52,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17744 states to 17744 states and 61429 transitions. [2019-12-07 17:38:52,074 INFO L78 Accepts]: Start accepts. Automaton has 17744 states and 61429 transitions. Word has length 70 [2019-12-07 17:38:52,074 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:38:52,074 INFO L462 AbstractCegarLoop]: Abstraction has 17744 states and 61429 transitions. [2019-12-07 17:38:52,074 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:38:52,074 INFO L276 IsEmpty]: Start isEmpty. Operand 17744 states and 61429 transitions. [2019-12-07 17:38:52,095 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-12-07 17:38:52,095 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:38:52,095 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:38:52,095 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:38:52,095 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:38:52,096 INFO L82 PathProgramCache]: Analyzing trace with hash 726610784, now seen corresponding path program 1 times [2019-12-07 17:38:52,096 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:38:52,096 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [220573051] [2019-12-07 17:38:52,096 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:38:52,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:38:52,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:38:52,148 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [220573051] [2019-12-07 17:38:52,148 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:38:52,148 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:38:52,148 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1165491234] [2019-12-07 17:38:52,149 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:38:52,149 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:38:52,149 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:38:52,149 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:38:52,149 INFO L87 Difference]: Start difference. First operand 17744 states and 61429 transitions. Second operand 3 states. [2019-12-07 17:38:52,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:38:52,203 INFO L93 Difference]: Finished difference Result 17743 states and 61427 transitions. [2019-12-07 17:38:52,203 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:38:52,203 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 71 [2019-12-07 17:38:52,204 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:38:52,235 INFO L225 Difference]: With dead ends: 17743 [2019-12-07 17:38:52,235 INFO L226 Difference]: Without dead ends: 17743 [2019-12-07 17:38:52,235 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:38:52,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17743 states. [2019-12-07 17:38:52,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17743 to 17743. [2019-12-07 17:38:52,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17743 states. [2019-12-07 17:38:52,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17743 states to 17743 states and 61427 transitions. [2019-12-07 17:38:52,616 INFO L78 Accepts]: Start accepts. Automaton has 17743 states and 61427 transitions. Word has length 71 [2019-12-07 17:38:52,616 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:38:52,616 INFO L462 AbstractCegarLoop]: Abstraction has 17743 states and 61427 transitions. [2019-12-07 17:38:52,617 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:38:52,617 INFO L276 IsEmpty]: Start isEmpty. Operand 17743 states and 61427 transitions. [2019-12-07 17:38:52,635 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:38:52,635 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:38:52,635 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:38:52,635 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:38:52,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:38:52,636 INFO L82 PathProgramCache]: Analyzing trace with hash 1049534817, now seen corresponding path program 1 times [2019-12-07 17:38:52,636 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:38:52,636 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1519710309] [2019-12-07 17:38:52,636 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:38:52,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:38:52,731 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:38:52,731 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1519710309] [2019-12-07 17:38:52,731 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:38:52,731 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:38:52,731 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [204450954] [2019-12-07 17:38:52,732 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:38:52,732 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:38:52,732 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:38:52,732 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:38:52,732 INFO L87 Difference]: Start difference. First operand 17743 states and 61427 transitions. Second operand 6 states. [2019-12-07 17:38:52,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:38:52,808 INFO L93 Difference]: Finished difference Result 21847 states and 74322 transitions. [2019-12-07 17:38:52,808 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:38:52,809 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 72 [2019-12-07 17:38:52,809 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:38:52,813 INFO L225 Difference]: With dead ends: 21847 [2019-12-07 17:38:52,813 INFO L226 Difference]: Without dead ends: 4661 [2019-12-07 17:38:52,814 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 17:38:52,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4661 states. [2019-12-07 17:38:52,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4661 to 4661. [2019-12-07 17:38:52,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4661 states. [2019-12-07 17:38:52,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4661 states to 4661 states and 14222 transitions. [2019-12-07 17:38:52,883 INFO L78 Accepts]: Start accepts. Automaton has 4661 states and 14222 transitions. Word has length 72 [2019-12-07 17:38:52,883 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:38:52,883 INFO L462 AbstractCegarLoop]: Abstraction has 4661 states and 14222 transitions. [2019-12-07 17:38:52,883 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:38:52,883 INFO L276 IsEmpty]: Start isEmpty. Operand 4661 states and 14222 transitions. [2019-12-07 17:38:52,886 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:38:52,886 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:38:52,886 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:38:52,886 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:38:52,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:38:52,887 INFO L82 PathProgramCache]: Analyzing trace with hash 1176538835, now seen corresponding path program 2 times [2019-12-07 17:38:52,887 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:38:52,887 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1648578080] [2019-12-07 17:38:52,887 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:38:52,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:38:53,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:38:53,313 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1648578080] [2019-12-07 17:38:53,313 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:38:53,314 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 17:38:53,314 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1474244842] [2019-12-07 17:38:53,314 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 17:38:53,314 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:38:53,314 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 17:38:53,314 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2019-12-07 17:38:53,315 INFO L87 Difference]: Start difference. First operand 4661 states and 14222 transitions. Second operand 17 states. [2019-12-07 17:38:56,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:38:56,007 INFO L93 Difference]: Finished difference Result 10500 states and 31573 transitions. [2019-12-07 17:38:56,007 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-12-07 17:38:56,007 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 72 [2019-12-07 17:38:56,007 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:38:56,014 INFO L225 Difference]: With dead ends: 10500 [2019-12-07 17:38:56,014 INFO L226 Difference]: Without dead ends: 7615 [2019-12-07 17:38:56,015 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 285 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=203, Invalid=1279, Unknown=0, NotChecked=0, Total=1482 [2019-12-07 17:38:56,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7615 states. [2019-12-07 17:38:56,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7615 to 6752. [2019-12-07 17:38:56,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6752 states. [2019-12-07 17:38:56,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6752 states to 6752 states and 20350 transitions. [2019-12-07 17:38:56,129 INFO L78 Accepts]: Start accepts. Automaton has 6752 states and 20350 transitions. Word has length 72 [2019-12-07 17:38:56,129 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:38:56,129 INFO L462 AbstractCegarLoop]: Abstraction has 6752 states and 20350 transitions. [2019-12-07 17:38:56,129 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 17:38:56,129 INFO L276 IsEmpty]: Start isEmpty. Operand 6752 states and 20350 transitions. [2019-12-07 17:38:56,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:38:56,135 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:38:56,136 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:38:56,136 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:38:56,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:38:56,136 INFO L82 PathProgramCache]: Analyzing trace with hash -631520119, now seen corresponding path program 3 times [2019-12-07 17:38:56,136 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:38:56,136 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1351725640] [2019-12-07 17:38:56,136 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:38:56,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:38:56,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:38:56,522 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1351725640] [2019-12-07 17:38:56,522 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:38:56,522 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2019-12-07 17:38:56,522 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [715156470] [2019-12-07 17:38:56,523 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 17:38:56,523 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:38:56,523 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 17:38:56,523 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=369, Unknown=0, NotChecked=0, Total=420 [2019-12-07 17:38:56,523 INFO L87 Difference]: Start difference. First operand 6752 states and 20350 transitions. Second operand 21 states. [2019-12-07 17:38:57,300 WARN L192 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 22 DAG size of output: 21 [2019-12-07 17:38:58,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:38:58,161 INFO L93 Difference]: Finished difference Result 13063 states and 39265 transitions. [2019-12-07 17:38:58,161 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2019-12-07 17:38:58,161 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 72 [2019-12-07 17:38:58,161 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:38:58,172 INFO L225 Difference]: With dead ends: 13063 [2019-12-07 17:38:58,173 INFO L226 Difference]: Without dead ends: 11704 [2019-12-07 17:38:58,173 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 239 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=141, Invalid=1049, Unknown=0, NotChecked=0, Total=1190 [2019-12-07 17:38:58,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11704 states. [2019-12-07 17:38:58,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11704 to 9701. [2019-12-07 17:38:58,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9701 states. [2019-12-07 17:38:58,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9701 states to 9701 states and 29220 transitions. [2019-12-07 17:38:58,323 INFO L78 Accepts]: Start accepts. Automaton has 9701 states and 29220 transitions. Word has length 72 [2019-12-07 17:38:58,323 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:38:58,323 INFO L462 AbstractCegarLoop]: Abstraction has 9701 states and 29220 transitions. [2019-12-07 17:38:58,323 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 17:38:58,324 INFO L276 IsEmpty]: Start isEmpty. Operand 9701 states and 29220 transitions. [2019-12-07 17:38:58,331 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:38:58,331 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:38:58,332 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:38:58,332 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:38:58,332 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:38:58,332 INFO L82 PathProgramCache]: Analyzing trace with hash -162566405, now seen corresponding path program 4 times [2019-12-07 17:38:58,332 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:38:58,332 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2099546031] [2019-12-07 17:38:58,332 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:38:58,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:38:58,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:38:58,866 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2099546031] [2019-12-07 17:38:58,866 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:38:58,866 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2019-12-07 17:38:58,866 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1196811978] [2019-12-07 17:38:58,867 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-12-07 17:38:58,867 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:38:58,867 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 17:38:58,867 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=541, Unknown=0, NotChecked=0, Total=600 [2019-12-07 17:38:58,867 INFO L87 Difference]: Start difference. First operand 9701 states and 29220 transitions. Second operand 25 states. [2019-12-07 17:39:01,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:39:01,981 INFO L93 Difference]: Finished difference Result 20224 states and 60863 transitions. [2019-12-07 17:39:01,981 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2019-12-07 17:39:01,981 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 72 [2019-12-07 17:39:01,981 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:39:02,000 INFO L225 Difference]: With dead ends: 20224 [2019-12-07 17:39:02,000 INFO L226 Difference]: Without dead ends: 17841 [2019-12-07 17:39:02,001 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1017 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=392, Invalid=3768, Unknown=0, NotChecked=0, Total=4160 [2019-12-07 17:39:02,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17841 states. [2019-12-07 17:39:02,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17841 to 11149. [2019-12-07 17:39:02,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11149 states. [2019-12-07 17:39:02,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11149 states to 11149 states and 33747 transitions. [2019-12-07 17:39:02,198 INFO L78 Accepts]: Start accepts. Automaton has 11149 states and 33747 transitions. Word has length 72 [2019-12-07 17:39:02,198 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:39:02,198 INFO L462 AbstractCegarLoop]: Abstraction has 11149 states and 33747 transitions. [2019-12-07 17:39:02,198 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-12-07 17:39:02,199 INFO L276 IsEmpty]: Start isEmpty. Operand 11149 states and 33747 transitions. [2019-12-07 17:39:02,208 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:39:02,209 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:39:02,209 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:39:02,209 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:39:02,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:39:02,209 INFO L82 PathProgramCache]: Analyzing trace with hash 210711269, now seen corresponding path program 5 times [2019-12-07 17:39:02,209 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:39:02,210 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1073521569] [2019-12-07 17:39:02,210 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:39:02,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:39:03,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:39:03,154 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1073521569] [2019-12-07 17:39:03,154 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:39:03,154 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2019-12-07 17:39:03,154 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1172622426] [2019-12-07 17:39:03,154 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-12-07 17:39:03,154 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:39:03,154 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 17:39:03,155 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=445, Unknown=0, NotChecked=0, Total=506 [2019-12-07 17:39:03,155 INFO L87 Difference]: Start difference. First operand 11149 states and 33747 transitions. Second operand 23 states. [2019-12-07 17:39:07,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:39:07,290 INFO L93 Difference]: Finished difference Result 20048 states and 60244 transitions. [2019-12-07 17:39:07,290 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2019-12-07 17:39:07,290 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 72 [2019-12-07 17:39:07,290 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:39:07,308 INFO L225 Difference]: With dead ends: 20048 [2019-12-07 17:39:07,308 INFO L226 Difference]: Without dead ends: 17720 [2019-12-07 17:39:07,309 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 558 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=323, Invalid=2127, Unknown=0, NotChecked=0, Total=2450 [2019-12-07 17:39:07,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17720 states. [2019-12-07 17:39:07,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17720 to 14378. [2019-12-07 17:39:07,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14378 states. [2019-12-07 17:39:07,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14378 states to 14378 states and 42511 transitions. [2019-12-07 17:39:07,534 INFO L78 Accepts]: Start accepts. Automaton has 14378 states and 42511 transitions. Word has length 72 [2019-12-07 17:39:07,535 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:39:07,535 INFO L462 AbstractCegarLoop]: Abstraction has 14378 states and 42511 transitions. [2019-12-07 17:39:07,535 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-12-07 17:39:07,535 INFO L276 IsEmpty]: Start isEmpty. Operand 14378 states and 42511 transitions. [2019-12-07 17:39:07,548 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:39:07,548 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:39:07,548 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:39:07,548 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:39:07,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:39:07,548 INFO L82 PathProgramCache]: Analyzing trace with hash 617877449, now seen corresponding path program 6 times [2019-12-07 17:39:07,548 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:39:07,549 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [164543941] [2019-12-07 17:39:07,549 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:39:07,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:39:08,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:39:08,301 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [164543941] [2019-12-07 17:39:08,301 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:39:08,301 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2019-12-07 17:39:08,301 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1748190540] [2019-12-07 17:39:08,302 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 17:39:08,302 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:39:08,302 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 17:39:08,302 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=374, Unknown=0, NotChecked=0, Total=420 [2019-12-07 17:39:08,302 INFO L87 Difference]: Start difference. First operand 14378 states and 42511 transitions. Second operand 21 states. [2019-12-07 17:39:11,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:39:11,057 INFO L93 Difference]: Finished difference Result 17139 states and 50469 transitions. [2019-12-07 17:39:11,057 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-12-07 17:39:11,057 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 72 [2019-12-07 17:39:11,057 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:39:11,074 INFO L225 Difference]: With dead ends: 17139 [2019-12-07 17:39:11,074 INFO L226 Difference]: Without dead ends: 17077 [2019-12-07 17:39:11,075 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 233 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=171, Invalid=1389, Unknown=0, NotChecked=0, Total=1560 [2019-12-07 17:39:11,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17077 states. [2019-12-07 17:39:11,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17077 to 15217. [2019-12-07 17:39:11,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15217 states. [2019-12-07 17:39:11,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15217 states to 15217 states and 44989 transitions. [2019-12-07 17:39:11,305 INFO L78 Accepts]: Start accepts. Automaton has 15217 states and 44989 transitions. Word has length 72 [2019-12-07 17:39:11,306 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:39:11,306 INFO L462 AbstractCegarLoop]: Abstraction has 15217 states and 44989 transitions. [2019-12-07 17:39:11,306 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 17:39:11,306 INFO L276 IsEmpty]: Start isEmpty. Operand 15217 states and 44989 transitions. [2019-12-07 17:39:11,320 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:39:11,320 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:39:11,320 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:39:11,320 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:39:11,320 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:39:11,320 INFO L82 PathProgramCache]: Analyzing trace with hash -934704183, now seen corresponding path program 7 times [2019-12-07 17:39:11,320 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:39:11,321 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070461382] [2019-12-07 17:39:11,321 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:39:11,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:39:11,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:39:11,511 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2070461382] [2019-12-07 17:39:11,511 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:39:11,511 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 17:39:11,511 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [649763015] [2019-12-07 17:39:11,512 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 17:39:11,512 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:39:11,512 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 17:39:11,512 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2019-12-07 17:39:11,512 INFO L87 Difference]: Start difference. First operand 15217 states and 44989 transitions. Second operand 12 states. [2019-12-07 17:39:12,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:39:12,477 INFO L93 Difference]: Finished difference Result 23491 states and 69254 transitions. [2019-12-07 17:39:12,477 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 17:39:12,477 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 72 [2019-12-07 17:39:12,477 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:39:12,497 INFO L225 Difference]: With dead ends: 23491 [2019-12-07 17:39:12,497 INFO L226 Difference]: Without dead ends: 20329 [2019-12-07 17:39:12,498 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 67 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=104, Invalid=402, Unknown=0, NotChecked=0, Total=506 [2019-12-07 17:39:12,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20329 states. [2019-12-07 17:39:12,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20329 to 16978. [2019-12-07 17:39:12,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16978 states. [2019-12-07 17:39:12,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16978 states to 16978 states and 50219 transitions. [2019-12-07 17:39:12,751 INFO L78 Accepts]: Start accepts. Automaton has 16978 states and 50219 transitions. Word has length 72 [2019-12-07 17:39:12,751 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:39:12,751 INFO L462 AbstractCegarLoop]: Abstraction has 16978 states and 50219 transitions. [2019-12-07 17:39:12,751 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 17:39:12,751 INFO L276 IsEmpty]: Start isEmpty. Operand 16978 states and 50219 transitions. [2019-12-07 17:39:12,766 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:39:12,766 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:39:12,766 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:39:12,767 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:39:12,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:39:12,767 INFO L82 PathProgramCache]: Analyzing trace with hash 1479181461, now seen corresponding path program 8 times [2019-12-07 17:39:12,767 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:39:12,767 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1237089403] [2019-12-07 17:39:12,767 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:39:12,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:39:13,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:39:13,670 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1237089403] [2019-12-07 17:39:13,670 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:39:13,670 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [24] imperfect sequences [] total 24 [2019-12-07 17:39:13,670 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [905626337] [2019-12-07 17:39:13,671 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-12-07 17:39:13,671 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:39:13,671 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-12-07 17:39:13,671 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=69, Invalid=581, Unknown=0, NotChecked=0, Total=650 [2019-12-07 17:39:13,671 INFO L87 Difference]: Start difference. First operand 16978 states and 50219 transitions. Second operand 26 states. [2019-12-07 17:39:17,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:39:17,562 INFO L93 Difference]: Finished difference Result 21077 states and 61027 transitions. [2019-12-07 17:39:17,562 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2019-12-07 17:39:17,562 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 72 [2019-12-07 17:39:17,562 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:39:17,583 INFO L225 Difference]: With dead ends: 21077 [2019-12-07 17:39:17,583 INFO L226 Difference]: Without dead ends: 21037 [2019-12-07 17:39:17,585 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 5 SyntacticMatches, 4 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 829 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=379, Invalid=3281, Unknown=0, NotChecked=0, Total=3660 [2019-12-07 17:39:17,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21037 states. [2019-12-07 17:39:17,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21037 to 18563. [2019-12-07 17:39:17,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18563 states. [2019-12-07 17:39:17,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18563 states to 18563 states and 54555 transitions. [2019-12-07 17:39:17,929 INFO L78 Accepts]: Start accepts. Automaton has 18563 states and 54555 transitions. Word has length 72 [2019-12-07 17:39:17,929 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:39:17,929 INFO L462 AbstractCegarLoop]: Abstraction has 18563 states and 54555 transitions. [2019-12-07 17:39:17,929 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-12-07 17:39:17,929 INFO L276 IsEmpty]: Start isEmpty. Operand 18563 states and 54555 transitions. [2019-12-07 17:39:17,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:39:17,947 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:39:17,947 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:39:17,947 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:39:17,948 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:39:17,948 INFO L82 PathProgramCache]: Analyzing trace with hash 569162215, now seen corresponding path program 9 times [2019-12-07 17:39:17,948 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:39:17,948 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1116744598] [2019-12-07 17:39:17,948 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:39:17,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:39:19,078 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:39:19,078 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1116744598] [2019-12-07 17:39:19,078 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:39:19,078 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2019-12-07 17:39:19,078 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [152269967] [2019-12-07 17:39:19,078 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-12-07 17:39:19,079 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:39:19,079 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 17:39:19,079 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=538, Unknown=0, NotChecked=0, Total=600 [2019-12-07 17:39:19,079 INFO L87 Difference]: Start difference. First operand 18563 states and 54555 transitions. Second operand 25 states. [2019-12-07 17:39:22,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:39:22,949 INFO L93 Difference]: Finished difference Result 22486 states and 64836 transitions. [2019-12-07 17:39:22,949 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-12-07 17:39:22,950 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 72 [2019-12-07 17:39:22,950 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:39:22,993 INFO L225 Difference]: With dead ends: 22486 [2019-12-07 17:39:22,993 INFO L226 Difference]: Without dead ends: 22451 [2019-12-07 17:39:22,994 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 347 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=189, Invalid=1617, Unknown=0, NotChecked=0, Total=1806 [2019-12-07 17:39:23,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22451 states. [2019-12-07 17:39:23,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22451 to 19105. [2019-12-07 17:39:23,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19105 states. [2019-12-07 17:39:23,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19105 states to 19105 states and 55776 transitions. [2019-12-07 17:39:23,280 INFO L78 Accepts]: Start accepts. Automaton has 19105 states and 55776 transitions. Word has length 72 [2019-12-07 17:39:23,280 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:39:23,280 INFO L462 AbstractCegarLoop]: Abstraction has 19105 states and 55776 transitions. [2019-12-07 17:39:23,280 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-12-07 17:39:23,280 INFO L276 IsEmpty]: Start isEmpty. Operand 19105 states and 55776 transitions. [2019-12-07 17:39:23,297 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:39:23,297 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:39:23,298 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:39:23,298 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:39:23,298 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:39:23,298 INFO L82 PathProgramCache]: Analyzing trace with hash -463315391, now seen corresponding path program 10 times [2019-12-07 17:39:23,298 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:39:23,298 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1087818319] [2019-12-07 17:39:23,298 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:39:23,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:39:25,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:39:25,419 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1087818319] [2019-12-07 17:39:25,419 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:39:25,419 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [32] imperfect sequences [] total 32 [2019-12-07 17:39:25,419 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1426273321] [2019-12-07 17:39:25,419 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2019-12-07 17:39:25,419 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:39:25,419 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2019-12-07 17:39:25,420 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=94, Invalid=1028, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 17:39:25,420 INFO L87 Difference]: Start difference. First operand 19105 states and 55776 transitions. Second operand 34 states. [2019-12-07 17:39:30,305 WARN L192 SmtUtils]: Spent 129.00 ms on a formula simplification. DAG size of input: 37 DAG size of output: 36 [2019-12-07 17:39:31,001 WARN L192 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 33 DAG size of output: 32 [2019-12-07 17:39:34,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:39:34,382 INFO L93 Difference]: Finished difference Result 22605 states and 64095 transitions. [2019-12-07 17:39:34,382 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2019-12-07 17:39:34,382 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 72 [2019-12-07 17:39:34,382 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:39:34,402 INFO L225 Difference]: With dead ends: 22605 [2019-12-07 17:39:34,402 INFO L226 Difference]: Without dead ends: 22463 [2019-12-07 17:39:34,405 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 107 GetRequests, 9 SyntacticMatches, 1 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2513 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=816, Invalid=8886, Unknown=0, NotChecked=0, Total=9702 [2019-12-07 17:39:34,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22463 states. [2019-12-07 17:39:34,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22463 to 21365. [2019-12-07 17:39:34,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21365 states. [2019-12-07 17:39:34,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21365 states to 21365 states and 61349 transitions. [2019-12-07 17:39:34,702 INFO L78 Accepts]: Start accepts. Automaton has 21365 states and 61349 transitions. Word has length 72 [2019-12-07 17:39:34,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:39:34,702 INFO L462 AbstractCegarLoop]: Abstraction has 21365 states and 61349 transitions. [2019-12-07 17:39:34,702 INFO L463 AbstractCegarLoop]: Interpolant automaton has 34 states. [2019-12-07 17:39:34,702 INFO L276 IsEmpty]: Start isEmpty. Operand 21365 states and 61349 transitions. [2019-12-07 17:39:34,722 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:39:34,722 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:39:34,722 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:39:34,722 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:39:34,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:39:34,723 INFO L82 PathProgramCache]: Analyzing trace with hash -259923749, now seen corresponding path program 11 times [2019-12-07 17:39:34,723 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:39:34,723 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032035786] [2019-12-07 17:39:34,723 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:39:34,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:39:35,039 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:39:35,039 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2032035786] [2019-12-07 17:39:35,040 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:39:35,040 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 17:39:35,040 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [180060346] [2019-12-07 17:39:35,040 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 17:39:35,040 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:39:35,040 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 17:39:35,040 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=205, Unknown=0, NotChecked=0, Total=240 [2019-12-07 17:39:35,040 INFO L87 Difference]: Start difference. First operand 21365 states and 61349 transitions. Second operand 16 states. [2019-12-07 17:39:37,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:39:37,157 INFO L93 Difference]: Finished difference Result 28782 states and 82684 transitions. [2019-12-07 17:39:37,158 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2019-12-07 17:39:37,158 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2019-12-07 17:39:37,158 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:39:37,204 INFO L225 Difference]: With dead ends: 28782 [2019-12-07 17:39:37,204 INFO L226 Difference]: Without dead ends: 25514 [2019-12-07 17:39:37,205 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 188 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=181, Invalid=1009, Unknown=0, NotChecked=0, Total=1190 [2019-12-07 17:39:37,277 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25514 states. [2019-12-07 17:39:37,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25514 to 21704. [2019-12-07 17:39:37,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21704 states. [2019-12-07 17:39:37,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21704 states to 21704 states and 62667 transitions. [2019-12-07 17:39:37,531 INFO L78 Accepts]: Start accepts. Automaton has 21704 states and 62667 transitions. Word has length 72 [2019-12-07 17:39:37,531 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:39:37,531 INFO L462 AbstractCegarLoop]: Abstraction has 21704 states and 62667 transitions. [2019-12-07 17:39:37,531 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 17:39:37,531 INFO L276 IsEmpty]: Start isEmpty. Operand 21704 states and 62667 transitions. [2019-12-07 17:39:37,552 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:39:37,552 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:39:37,552 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:39:37,552 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:39:37,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:39:37,552 INFO L82 PathProgramCache]: Analyzing trace with hash 1135243869, now seen corresponding path program 12 times [2019-12-07 17:39:37,552 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:39:37,552 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1683999613] [2019-12-07 17:39:37,553 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:39:37,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:39:37,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:39:37,879 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1683999613] [2019-12-07 17:39:37,879 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:39:37,879 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 17:39:37,879 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [868817041] [2019-12-07 17:39:37,880 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 17:39:37,880 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:39:37,880 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 17:39:37,880 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=234, Unknown=0, NotChecked=0, Total=272 [2019-12-07 17:39:37,880 INFO L87 Difference]: Start difference. First operand 21704 states and 62667 transitions. Second operand 17 states. [2019-12-07 17:39:39,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:39:39,669 INFO L93 Difference]: Finished difference Result 27737 states and 79121 transitions. [2019-12-07 17:39:39,669 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2019-12-07 17:39:39,670 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 72 [2019-12-07 17:39:39,670 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:39:39,699 INFO L225 Difference]: With dead ends: 27737 [2019-12-07 17:39:39,699 INFO L226 Difference]: Without dead ends: 26035 [2019-12-07 17:39:39,700 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 291 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=236, Invalid=1404, Unknown=0, NotChecked=0, Total=1640 [2019-12-07 17:39:39,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26035 states. [2019-12-07 17:39:39,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26035 to 22146. [2019-12-07 17:39:39,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22146 states. [2019-12-07 17:39:40,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22146 states to 22146 states and 63937 transitions. [2019-12-07 17:39:40,137 INFO L78 Accepts]: Start accepts. Automaton has 22146 states and 63937 transitions. Word has length 72 [2019-12-07 17:39:40,137 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:39:40,137 INFO L462 AbstractCegarLoop]: Abstraction has 22146 states and 63937 transitions. [2019-12-07 17:39:40,137 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 17:39:40,137 INFO L276 IsEmpty]: Start isEmpty. Operand 22146 states and 63937 transitions. [2019-12-07 17:39:40,155 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:39:40,155 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:39:40,155 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:39:40,156 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:39:40,156 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:39:40,156 INFO L82 PathProgramCache]: Analyzing trace with hash -2029153311, now seen corresponding path program 13 times [2019-12-07 17:39:40,156 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:39:40,156 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1849641637] [2019-12-07 17:39:40,156 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:39:40,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:39:40,691 WARN L192 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 32 [2019-12-07 17:39:40,871 WARN L192 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 28 [2019-12-07 17:39:41,047 WARN L192 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 30 [2019-12-07 17:39:41,235 WARN L192 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 28 [2019-12-07 17:39:42,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:39:42,376 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1849641637] [2019-12-07 17:39:42,376 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:39:42,377 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [27] imperfect sequences [] total 27 [2019-12-07 17:39:42,377 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [654178305] [2019-12-07 17:39:42,377 INFO L442 AbstractCegarLoop]: Interpolant automaton has 29 states [2019-12-07 17:39:42,377 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:39:42,377 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2019-12-07 17:39:42,377 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=733, Unknown=0, NotChecked=0, Total=812 [2019-12-07 17:39:42,378 INFO L87 Difference]: Start difference. First operand 22146 states and 63937 transitions. Second operand 29 states. [2019-12-07 17:39:50,663 WARN L192 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 38 [2019-12-07 17:39:51,230 WARN L192 SmtUtils]: Spent 136.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 38 [2019-12-07 17:39:51,673 WARN L192 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 35 DAG size of output: 31 [2019-12-07 17:39:52,493 WARN L192 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 33 DAG size of output: 29 [2019-12-07 17:39:53,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:39:53,323 INFO L93 Difference]: Finished difference Result 27033 states and 76713 transitions. [2019-12-07 17:39:53,324 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2019-12-07 17:39:53,324 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 72 [2019-12-07 17:39:53,325 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:39:53,371 INFO L225 Difference]: With dead ends: 27033 [2019-12-07 17:39:53,371 INFO L226 Difference]: Without dead ends: 26692 [2019-12-07 17:39:53,374 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 92 GetRequests, 2 SyntacticMatches, 7 SemanticMatches, 83 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1905 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=759, Invalid=6381, Unknown=0, NotChecked=0, Total=7140 [2019-12-07 17:39:53,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26692 states. [2019-12-07 17:39:53,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26692 to 23401. [2019-12-07 17:39:53,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23401 states. [2019-12-07 17:39:53,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23401 states to 23401 states and 67156 transitions. [2019-12-07 17:39:53,710 INFO L78 Accepts]: Start accepts. Automaton has 23401 states and 67156 transitions. Word has length 72 [2019-12-07 17:39:53,711 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:39:53,711 INFO L462 AbstractCegarLoop]: Abstraction has 23401 states and 67156 transitions. [2019-12-07 17:39:53,711 INFO L463 AbstractCegarLoop]: Interpolant automaton has 29 states. [2019-12-07 17:39:53,711 INFO L276 IsEmpty]: Start isEmpty. Operand 23401 states and 67156 transitions. [2019-12-07 17:39:53,730 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:39:53,731 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:39:53,731 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:39:53,731 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:39:53,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:39:53,731 INFO L82 PathProgramCache]: Analyzing trace with hash -57572609, now seen corresponding path program 14 times [2019-12-07 17:39:53,731 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:39:53,731 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1851288104] [2019-12-07 17:39:53,731 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:39:53,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:39:54,622 WARN L192 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 28 [2019-12-07 17:39:54,895 WARN L192 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 30 [2019-12-07 17:39:55,327 WARN L192 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 42 DAG size of output: 25 [2019-12-07 17:39:56,195 WARN L192 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 38 DAG size of output: 21 [2019-12-07 17:39:56,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:39:56,516 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1851288104] [2019-12-07 17:39:56,516 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:39:56,516 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [29] imperfect sequences [] total 29 [2019-12-07 17:39:56,516 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1107474908] [2019-12-07 17:39:56,517 INFO L442 AbstractCegarLoop]: Interpolant automaton has 31 states [2019-12-07 17:39:56,517 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:39:56,517 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2019-12-07 17:39:56,517 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=848, Unknown=0, NotChecked=0, Total=930 [2019-12-07 17:39:56,517 INFO L87 Difference]: Start difference. First operand 23401 states and 67156 transitions. Second operand 31 states. [2019-12-07 17:39:56,800 WARN L192 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 29 DAG size of output: 28 [2019-12-07 17:39:57,544 WARN L192 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 31 DAG size of output: 30 [2019-12-07 17:39:57,922 WARN L192 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 33 DAG size of output: 32 [2019-12-07 17:39:58,374 WARN L192 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 26 DAG size of output: 25 [2019-12-07 17:40:05,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:40:05,513 INFO L93 Difference]: Finished difference Result 25820 states and 73608 transitions. [2019-12-07 17:40:05,514 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2019-12-07 17:40:05,514 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 72 [2019-12-07 17:40:05,514 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:40:05,552 INFO L225 Difference]: With dead ends: 25820 [2019-12-07 17:40:05,553 INFO L226 Difference]: Without dead ends: 25355 [2019-12-07 17:40:05,554 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 83 GetRequests, 1 SyntacticMatches, 9 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1250 ImplicationChecksByTransitivity, 5.6s TimeCoverageRelationStatistics Valid=576, Invalid=4974, Unknown=0, NotChecked=0, Total=5550 [2019-12-07 17:40:05,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25355 states. [2019-12-07 17:40:05,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25355 to 23236. [2019-12-07 17:40:05,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23236 states. [2019-12-07 17:40:05,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23236 states to 23236 states and 66646 transitions. [2019-12-07 17:40:05,875 INFO L78 Accepts]: Start accepts. Automaton has 23236 states and 66646 transitions. Word has length 72 [2019-12-07 17:40:05,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:40:05,875 INFO L462 AbstractCegarLoop]: Abstraction has 23236 states and 66646 transitions. [2019-12-07 17:40:05,875 INFO L463 AbstractCegarLoop]: Interpolant automaton has 31 states. [2019-12-07 17:40:05,875 INFO L276 IsEmpty]: Start isEmpty. Operand 23236 states and 66646 transitions. [2019-12-07 17:40:05,895 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:40:05,895 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:40:05,895 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:40:05,895 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:40:05,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:40:05,895 INFO L82 PathProgramCache]: Analyzing trace with hash 1204180293, now seen corresponding path program 15 times [2019-12-07 17:40:05,895 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:40:05,896 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1292617219] [2019-12-07 17:40:05,896 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:40:05,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:40:06,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:40:06,467 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1292617219] [2019-12-07 17:40:06,467 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:40:06,467 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2019-12-07 17:40:06,468 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [456945594] [2019-12-07 17:40:06,468 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-12-07 17:40:06,468 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:40:06,468 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 17:40:06,468 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=445, Unknown=0, NotChecked=0, Total=506 [2019-12-07 17:40:06,468 INFO L87 Difference]: Start difference. First operand 23236 states and 66646 transitions. Second operand 23 states. [2019-12-07 17:40:08,085 WARN L192 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 32 DAG size of output: 29 [2019-12-07 17:40:08,315 WARN L192 SmtUtils]: Spent 125.00 ms on a formula simplification. DAG size of input: 30 DAG size of output: 27 [2019-12-07 17:40:08,505 WARN L192 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 28 DAG size of output: 27 [2019-12-07 17:40:08,818 WARN L192 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 26 DAG size of output: 25 [2019-12-07 17:40:11,071 WARN L192 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 27 DAG size of output: 25 [2019-12-07 17:40:11,422 WARN L192 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 30 DAG size of output: 27 [2019-12-07 17:40:12,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:40:12,184 INFO L93 Difference]: Finished difference Result 27568 states and 77987 transitions. [2019-12-07 17:40:12,184 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2019-12-07 17:40:12,185 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 72 [2019-12-07 17:40:12,185 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:40:12,209 INFO L225 Difference]: With dead ends: 27568 [2019-12-07 17:40:12,209 INFO L226 Difference]: Without dead ends: 23063 [2019-12-07 17:40:12,210 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 552 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=342, Invalid=2108, Unknown=0, NotChecked=0, Total=2450 [2019-12-07 17:40:12,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23063 states. [2019-12-07 17:40:12,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23063 to 16063. [2019-12-07 17:40:12,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16063 states. [2019-12-07 17:40:12,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16063 states to 16063 states and 47296 transitions. [2019-12-07 17:40:12,483 INFO L78 Accepts]: Start accepts. Automaton has 16063 states and 47296 transitions. Word has length 72 [2019-12-07 17:40:12,483 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:40:12,483 INFO L462 AbstractCegarLoop]: Abstraction has 16063 states and 47296 transitions. [2019-12-07 17:40:12,483 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-12-07 17:40:12,483 INFO L276 IsEmpty]: Start isEmpty. Operand 16063 states and 47296 transitions. [2019-12-07 17:40:12,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:40:12,498 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:40:12,498 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:40:12,498 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:40:12,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:40:12,498 INFO L82 PathProgramCache]: Analyzing trace with hash -36947753, now seen corresponding path program 16 times [2019-12-07 17:40:12,498 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:40:12,498 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1136568787] [2019-12-07 17:40:12,498 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:40:12,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:40:12,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:40:12,622 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1136568787] [2019-12-07 17:40:12,622 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:40:12,622 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 17:40:12,623 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [986884843] [2019-12-07 17:40:12,623 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 17:40:12,623 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:40:12,623 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 17:40:12,623 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2019-12-07 17:40:12,623 INFO L87 Difference]: Start difference. First operand 16063 states and 47296 transitions. Second operand 12 states. [2019-12-07 17:40:13,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:40:13,080 INFO L93 Difference]: Finished difference Result 25413 states and 74876 transitions. [2019-12-07 17:40:13,081 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 17:40:13,081 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 72 [2019-12-07 17:40:13,081 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:40:13,105 INFO L225 Difference]: With dead ends: 25413 [2019-12-07 17:40:13,105 INFO L226 Difference]: Without dead ends: 21528 [2019-12-07 17:40:13,105 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 82 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=87, Invalid=419, Unknown=0, NotChecked=0, Total=506 [2019-12-07 17:40:13,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21528 states. [2019-12-07 17:40:13,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21528 to 17232. [2019-12-07 17:40:13,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17232 states. [2019-12-07 17:40:13,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17232 states to 17232 states and 50462 transitions. [2019-12-07 17:40:13,362 INFO L78 Accepts]: Start accepts. Automaton has 17232 states and 50462 transitions. Word has length 72 [2019-12-07 17:40:13,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:40:13,363 INFO L462 AbstractCegarLoop]: Abstraction has 17232 states and 50462 transitions. [2019-12-07 17:40:13,363 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 17:40:13,363 INFO L276 IsEmpty]: Start isEmpty. Operand 17232 states and 50462 transitions. [2019-12-07 17:40:13,377 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:40:13,378 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:40:13,378 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:40:13,378 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:40:13,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:40:13,378 INFO L82 PathProgramCache]: Analyzing trace with hash -1848286879, now seen corresponding path program 17 times [2019-12-07 17:40:13,378 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:40:13,378 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [554544752] [2019-12-07 17:40:13,378 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:40:13,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:40:13,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:40:13,707 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [554544752] [2019-12-07 17:40:13,708 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:40:13,708 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 17:40:13,708 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [471528119] [2019-12-07 17:40:13,708 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 17:40:13,708 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:40:13,708 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 17:40:13,708 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2019-12-07 17:40:13,709 INFO L87 Difference]: Start difference. First operand 17232 states and 50462 transitions. Second operand 16 states. [2019-12-07 17:40:15,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:40:15,020 INFO L93 Difference]: Finished difference Result 26240 states and 76445 transitions. [2019-12-07 17:40:15,020 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-12-07 17:40:15,020 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2019-12-07 17:40:15,020 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:40:15,041 INFO L225 Difference]: With dead ends: 26240 [2019-12-07 17:40:15,041 INFO L226 Difference]: Without dead ends: 20902 [2019-12-07 17:40:15,042 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 186 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=155, Invalid=967, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 17:40:15,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20902 states. [2019-12-07 17:40:15,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20902 to 17131. [2019-12-07 17:40:15,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17131 states. [2019-12-07 17:40:15,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17131 states to 17131 states and 50173 transitions. [2019-12-07 17:40:15,300 INFO L78 Accepts]: Start accepts. Automaton has 17131 states and 50173 transitions. Word has length 72 [2019-12-07 17:40:15,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:40:15,300 INFO L462 AbstractCegarLoop]: Abstraction has 17131 states and 50173 transitions. [2019-12-07 17:40:15,301 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 17:40:15,301 INFO L276 IsEmpty]: Start isEmpty. Operand 17131 states and 50173 transitions. [2019-12-07 17:40:15,315 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:40:15,315 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:40:15,315 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:40:15,316 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:40:15,316 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:40:15,316 INFO L82 PathProgramCache]: Analyzing trace with hash 982526783, now seen corresponding path program 18 times [2019-12-07 17:40:15,316 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:40:15,316 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [344966266] [2019-12-07 17:40:15,316 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:40:15,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:40:15,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:40:15,753 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [344966266] [2019-12-07 17:40:15,753 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:40:15,753 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [20] imperfect sequences [] total 20 [2019-12-07 17:40:15,753 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1709199351] [2019-12-07 17:40:15,753 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-12-07 17:40:15,753 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:40:15,753 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-12-07 17:40:15,753 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=404, Unknown=0, NotChecked=0, Total=462 [2019-12-07 17:40:15,754 INFO L87 Difference]: Start difference. First operand 17131 states and 50173 transitions. Second operand 22 states. [2019-12-07 17:40:17,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:40:17,276 INFO L93 Difference]: Finished difference Result 28620 states and 83644 transitions. [2019-12-07 17:40:17,276 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-12-07 17:40:17,277 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 72 [2019-12-07 17:40:17,277 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:40:17,305 INFO L225 Difference]: With dead ends: 28620 [2019-12-07 17:40:17,305 INFO L226 Difference]: Without dead ends: 24138 [2019-12-07 17:40:17,306 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 448 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=239, Invalid=1741, Unknown=0, NotChecked=0, Total=1980 [2019-12-07 17:40:17,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24138 states. [2019-12-07 17:40:17,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24138 to 18356. [2019-12-07 17:40:17,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18356 states. [2019-12-07 17:40:17,596 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18356 states to 18356 states and 53974 transitions. [2019-12-07 17:40:17,596 INFO L78 Accepts]: Start accepts. Automaton has 18356 states and 53974 transitions. Word has length 72 [2019-12-07 17:40:17,597 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:40:17,597 INFO L462 AbstractCegarLoop]: Abstraction has 18356 states and 53974 transitions. [2019-12-07 17:40:17,597 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-12-07 17:40:17,597 INFO L276 IsEmpty]: Start isEmpty. Operand 18356 states and 53974 transitions. [2019-12-07 17:40:17,613 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:40:17,613 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:40:17,613 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:40:17,614 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:40:17,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:40:17,614 INFO L82 PathProgramCache]: Analyzing trace with hash -970803151, now seen corresponding path program 19 times [2019-12-07 17:40:17,614 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:40:17,614 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [12899852] [2019-12-07 17:40:17,614 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:40:17,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:40:17,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:40:17,918 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [12899852] [2019-12-07 17:40:17,918 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:40:17,918 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 17:40:17,918 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [391918973] [2019-12-07 17:40:17,918 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 17:40:17,919 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:40:17,919 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 17:40:17,919 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=235, Unknown=0, NotChecked=0, Total=272 [2019-12-07 17:40:17,919 INFO L87 Difference]: Start difference. First operand 18356 states and 53974 transitions. Second operand 17 states. [2019-12-07 17:40:19,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:40:19,380 INFO L93 Difference]: Finished difference Result 25480 states and 74567 transitions. [2019-12-07 17:40:19,381 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-12-07 17:40:19,381 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 72 [2019-12-07 17:40:19,381 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:40:19,405 INFO L225 Difference]: With dead ends: 25480 [2019-12-07 17:40:19,406 INFO L226 Difference]: Without dead ends: 22459 [2019-12-07 17:40:19,406 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 222 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=185, Invalid=1147, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 17:40:19,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22459 states. [2019-12-07 17:40:19,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22459 to 18758. [2019-12-07 17:40:19,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18758 states. [2019-12-07 17:40:19,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18758 states to 18758 states and 55158 transitions. [2019-12-07 17:40:19,681 INFO L78 Accepts]: Start accepts. Automaton has 18758 states and 55158 transitions. Word has length 72 [2019-12-07 17:40:19,681 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:40:19,681 INFO L462 AbstractCegarLoop]: Abstraction has 18758 states and 55158 transitions. [2019-12-07 17:40:19,681 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 17:40:19,681 INFO L276 IsEmpty]: Start isEmpty. Operand 18758 states and 55158 transitions. [2019-12-07 17:40:19,698 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:40:19,698 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:40:19,698 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:40:19,698 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:40:19,698 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:40:19,699 INFO L82 PathProgramCache]: Analyzing trace with hash 1194594085, now seen corresponding path program 20 times [2019-12-07 17:40:19,699 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:40:19,699 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [945809647] [2019-12-07 17:40:19,699 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:40:19,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:40:19,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:40:19,941 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [945809647] [2019-12-07 17:40:19,941 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:40:19,941 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 17:40:19,941 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [315233610] [2019-12-07 17:40:19,941 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 17:40:19,941 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:40:19,941 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 17:40:19,941 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2019-12-07 17:40:19,942 INFO L87 Difference]: Start difference. First operand 18758 states and 55158 transitions. Second operand 17 states. [2019-12-07 17:40:21,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:40:21,311 INFO L93 Difference]: Finished difference Result 21891 states and 63117 transitions. [2019-12-07 17:40:21,311 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 17:40:21,311 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 72 [2019-12-07 17:40:21,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:40:21,332 INFO L225 Difference]: With dead ends: 21891 [2019-12-07 17:40:21,332 INFO L226 Difference]: Without dead ends: 21383 [2019-12-07 17:40:21,333 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 153 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=134, Invalid=858, Unknown=0, NotChecked=0, Total=992 [2019-12-07 17:40:21,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21383 states. [2019-12-07 17:40:21,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21383 to 18604. [2019-12-07 17:40:21,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18604 states. [2019-12-07 17:40:21,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18604 states to 18604 states and 54665 transitions. [2019-12-07 17:40:21,611 INFO L78 Accepts]: Start accepts. Automaton has 18604 states and 54665 transitions. Word has length 72 [2019-12-07 17:40:21,612 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:40:21,612 INFO L462 AbstractCegarLoop]: Abstraction has 18604 states and 54665 transitions. [2019-12-07 17:40:21,612 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 17:40:21,612 INFO L276 IsEmpty]: Start isEmpty. Operand 18604 states and 54665 transitions. [2019-12-07 17:40:21,629 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:40:21,629 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:40:21,629 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:40:21,629 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:40:21,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:40:21,630 INFO L82 PathProgramCache]: Analyzing trace with hash -460633563, now seen corresponding path program 21 times [2019-12-07 17:40:21,630 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:40:21,630 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [937325193] [2019-12-07 17:40:21,630 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:40:21,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:40:21,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:40:21,877 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [937325193] [2019-12-07 17:40:21,877 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:40:21,877 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 17:40:21,877 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [911284914] [2019-12-07 17:40:21,878 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 17:40:21,878 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:40:21,878 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 17:40:21,878 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-12-07 17:40:21,878 INFO L87 Difference]: Start difference. First operand 18604 states and 54665 transitions. Second operand 16 states. [2019-12-07 17:40:23,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:40:23,252 INFO L93 Difference]: Finished difference Result 24426 states and 70689 transitions. [2019-12-07 17:40:23,252 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2019-12-07 17:40:23,252 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2019-12-07 17:40:23,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:40:23,275 INFO L225 Difference]: With dead ends: 24426 [2019-12-07 17:40:23,275 INFO L226 Difference]: Without dead ends: 22388 [2019-12-07 17:40:23,276 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 244 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=184, Invalid=1148, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 17:40:23,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22388 states. [2019-12-07 17:40:23,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22388 to 17764. [2019-12-07 17:40:23,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17764 states. [2019-12-07 17:40:23,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17764 states to 17764 states and 52366 transitions. [2019-12-07 17:40:23,542 INFO L78 Accepts]: Start accepts. Automaton has 17764 states and 52366 transitions. Word has length 72 [2019-12-07 17:40:23,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:40:23,542 INFO L462 AbstractCegarLoop]: Abstraction has 17764 states and 52366 transitions. [2019-12-07 17:40:23,542 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 17:40:23,542 INFO L276 IsEmpty]: Start isEmpty. Operand 17764 states and 52366 transitions. [2019-12-07 17:40:23,558 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:40:23,558 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:40:23,558 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:40:23,558 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:40:23,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:40:23,559 INFO L82 PathProgramCache]: Analyzing trace with hash 1527218387, now seen corresponding path program 22 times [2019-12-07 17:40:23,559 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:40:23,559 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [986548985] [2019-12-07 17:40:23,559 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:40:23,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:40:23,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:40:23,704 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [986548985] [2019-12-07 17:40:23,704 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:40:23,704 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 17:40:23,704 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1129858599] [2019-12-07 17:40:23,705 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 17:40:23,705 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:40:23,705 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 17:40:23,705 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=130, Unknown=0, NotChecked=0, Total=156 [2019-12-07 17:40:23,705 INFO L87 Difference]: Start difference. First operand 17764 states and 52366 transitions. Second operand 13 states. [2019-12-07 17:40:24,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:40:24,624 INFO L93 Difference]: Finished difference Result 23531 states and 69436 transitions. [2019-12-07 17:40:24,624 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 17:40:24,624 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 72 [2019-12-07 17:40:24,625 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:40:24,651 INFO L225 Difference]: With dead ends: 23531 [2019-12-07 17:40:24,652 INFO L226 Difference]: Without dead ends: 21351 [2019-12-07 17:40:24,652 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 80 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=98, Invalid=454, Unknown=0, NotChecked=0, Total=552 [2019-12-07 17:40:24,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21351 states. [2019-12-07 17:40:24,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21351 to 17655. [2019-12-07 17:40:24,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17655 states. [2019-12-07 17:40:24,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17655 states to 17655 states and 52020 transitions. [2019-12-07 17:40:24,917 INFO L78 Accepts]: Start accepts. Automaton has 17655 states and 52020 transitions. Word has length 72 [2019-12-07 17:40:24,917 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:40:24,917 INFO L462 AbstractCegarLoop]: Abstraction has 17655 states and 52020 transitions. [2019-12-07 17:40:24,917 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 17:40:24,917 INFO L276 IsEmpty]: Start isEmpty. Operand 17655 states and 52020 transitions. [2019-12-07 17:40:24,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:40:24,933 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:40:24,933 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:40:24,933 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:40:24,933 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:40:24,933 INFO L82 PathProgramCache]: Analyzing trace with hash 1219459465, now seen corresponding path program 23 times [2019-12-07 17:40:24,933 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:40:24,934 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1945582356] [2019-12-07 17:40:24,934 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:40:24,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:40:25,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:40:25,604 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1945582356] [2019-12-07 17:40:25,604 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:40:25,604 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [24] imperfect sequences [] total 24 [2019-12-07 17:40:25,604 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [388665121] [2019-12-07 17:40:25,605 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-12-07 17:40:25,605 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:40:25,605 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-12-07 17:40:25,605 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=69, Invalid=581, Unknown=0, NotChecked=0, Total=650 [2019-12-07 17:40:25,605 INFO L87 Difference]: Start difference. First operand 17655 states and 52020 transitions. Second operand 26 states. [2019-12-07 17:40:29,068 WARN L192 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 31 DAG size of output: 29 [2019-12-07 17:40:29,621 WARN L192 SmtUtils]: Spent 115.00 ms on a formula simplification that was a NOOP. DAG size: 37 [2019-12-07 17:40:30,129 WARN L192 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 31 DAG size of output: 29 [2019-12-07 17:40:30,356 WARN L192 SmtUtils]: Spent 118.00 ms on a formula simplification that was a NOOP. DAG size: 31 [2019-12-07 17:40:30,662 WARN L192 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 32 DAG size of output: 30 [2019-12-07 17:40:31,025 WARN L192 SmtUtils]: Spent 188.00 ms on a formula simplification. DAG size of input: 35 DAG size of output: 32 [2019-12-07 17:40:31,363 WARN L192 SmtUtils]: Spent 174.00 ms on a formula simplification. DAG size of input: 38 DAG size of output: 34 [2019-12-07 17:40:31,827 WARN L192 SmtUtils]: Spent 177.00 ms on a formula simplification. DAG size of input: 40 DAG size of output: 37 [2019-12-07 17:40:32,442 WARN L192 SmtUtils]: Spent 184.00 ms on a formula simplification. DAG size of input: 35 DAG size of output: 32 [2019-12-07 17:40:33,828 WARN L192 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 34 DAG size of output: 32 [2019-12-07 17:40:37,278 WARN L192 SmtUtils]: Spent 207.00 ms on a formula simplification. DAG size of input: 39 DAG size of output: 35 [2019-12-07 17:40:37,659 WARN L192 SmtUtils]: Spent 284.00 ms on a formula simplification. DAG size of input: 38 DAG size of output: 36 [2019-12-07 17:40:37,988 WARN L192 SmtUtils]: Spent 215.00 ms on a formula simplification. DAG size of input: 39 DAG size of output: 35 [2019-12-07 17:40:38,342 WARN L192 SmtUtils]: Spent 266.00 ms on a formula simplification. DAG size of input: 40 DAG size of output: 35 [2019-12-07 17:40:39,081 WARN L192 SmtUtils]: Spent 276.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 38 [2019-12-07 17:40:39,595 WARN L192 SmtUtils]: Spent 286.00 ms on a formula simplification. DAG size of input: 42 DAG size of output: 39 [2019-12-07 17:40:39,917 WARN L192 SmtUtils]: Spent 197.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 38 [2019-12-07 17:40:40,893 WARN L192 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 45 DAG size of output: 40 [2019-12-07 17:40:41,362 WARN L192 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 40 [2019-12-07 17:40:41,988 WARN L192 SmtUtils]: Spent 344.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 43 [2019-12-07 17:40:42,435 WARN L192 SmtUtils]: Spent 311.00 ms on a formula simplification. DAG size of input: 45 DAG size of output: 42 [2019-12-07 17:40:42,787 WARN L192 SmtUtils]: Spent 110.00 ms on a formula simplification that was a NOOP. DAG size: 30 [2019-12-07 17:40:43,728 WARN L192 SmtUtils]: Spent 213.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 36 [2019-12-07 17:40:44,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:40:44,305 INFO L93 Difference]: Finished difference Result 34982 states and 103225 transitions. [2019-12-07 17:40:44,305 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2019-12-07 17:40:44,306 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 72 [2019-12-07 17:40:44,306 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:40:44,358 INFO L225 Difference]: With dead ends: 34982 [2019-12-07 17:40:44,358 INFO L226 Difference]: Without dead ends: 34794 [2019-12-07 17:40:44,359 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 95 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2797 ImplicationChecksByTransitivity, 9.7s TimeCoverageRelationStatistics Valid=951, Invalid=8361, Unknown=0, NotChecked=0, Total=9312 [2019-12-07 17:40:44,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34794 states. [2019-12-07 17:40:44,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34794 to 25987. [2019-12-07 17:40:44,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25987 states. [2019-12-07 17:40:44,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25987 states to 25987 states and 78350 transitions. [2019-12-07 17:40:44,890 INFO L78 Accepts]: Start accepts. Automaton has 25987 states and 78350 transitions. Word has length 72 [2019-12-07 17:40:44,891 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:40:44,891 INFO L462 AbstractCegarLoop]: Abstraction has 25987 states and 78350 transitions. [2019-12-07 17:40:44,891 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-12-07 17:40:44,891 INFO L276 IsEmpty]: Start isEmpty. Operand 25987 states and 78350 transitions. [2019-12-07 17:40:44,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:40:44,918 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:40:44,918 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:40:44,918 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:40:44,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:40:44,919 INFO L82 PathProgramCache]: Analyzing trace with hash -954954121, now seen corresponding path program 24 times [2019-12-07 17:40:44,919 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:40:44,919 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1361030997] [2019-12-07 17:40:44,919 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:40:44,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:40:46,144 WARN L192 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 29 [2019-12-07 17:40:47,323 WARN L192 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 37 DAG size of output: 25 [2019-12-07 17:40:48,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:40:48,053 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1361030997] [2019-12-07 17:40:48,053 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:40:48,053 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [31] imperfect sequences [] total 31 [2019-12-07 17:40:48,053 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1115255005] [2019-12-07 17:40:48,053 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2019-12-07 17:40:48,053 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:40:48,053 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2019-12-07 17:40:48,054 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=973, Unknown=0, NotChecked=0, Total=1056 [2019-12-07 17:40:48,054 INFO L87 Difference]: Start difference. First operand 25987 states and 78350 transitions. Second operand 33 states. [2019-12-07 17:41:03,301 WARN L192 SmtUtils]: Spent 105.00 ms on a formula simplification that was a NOOP. DAG size: 37 [2019-12-07 17:41:07,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:07,601 INFO L93 Difference]: Finished difference Result 37403 states and 112671 transitions. [2019-12-07 17:41:07,602 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 108 states. [2019-12-07 17:41:07,602 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 72 [2019-12-07 17:41:07,602 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:07,660 INFO L225 Difference]: With dead ends: 37403 [2019-12-07 17:41:07,660 INFO L226 Difference]: Without dead ends: 37181 [2019-12-07 17:41:07,661 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 127 GetRequests, 6 SyntacticMatches, 6 SemanticMatches, 115 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3874 ImplicationChecksByTransitivity, 8.4s TimeCoverageRelationStatistics Valid=1107, Invalid=12465, Unknown=0, NotChecked=0, Total=13572 [2019-12-07 17:41:07,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37181 states. [2019-12-07 17:41:08,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37181 to 33198. [2019-12-07 17:41:08,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33198 states. [2019-12-07 17:41:08,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33198 states to 33198 states and 100660 transitions. [2019-12-07 17:41:08,197 INFO L78 Accepts]: Start accepts. Automaton has 33198 states and 100660 transitions. Word has length 72 [2019-12-07 17:41:08,197 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:08,198 INFO L462 AbstractCegarLoop]: Abstraction has 33198 states and 100660 transitions. [2019-12-07 17:41:08,198 INFO L463 AbstractCegarLoop]: Interpolant automaton has 33 states. [2019-12-07 17:41:08,198 INFO L276 IsEmpty]: Start isEmpty. Operand 33198 states and 100660 transitions. [2019-12-07 17:41:08,231 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:41:08,231 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:08,231 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:08,231 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:08,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:08,232 INFO L82 PathProgramCache]: Analyzing trace with hash 661187463, now seen corresponding path program 25 times [2019-12-07 17:41:08,232 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:08,232 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1463392076] [2019-12-07 17:41:08,232 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:08,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:08,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:08,488 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1463392076] [2019-12-07 17:41:08,488 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:08,488 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 17:41:08,489 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2129968835] [2019-12-07 17:41:08,489 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 17:41:08,489 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:08,489 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 17:41:08,489 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2019-12-07 17:41:08,489 INFO L87 Difference]: Start difference. First operand 33198 states and 100660 transitions. Second operand 17 states. [2019-12-07 17:41:13,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:13,954 INFO L93 Difference]: Finished difference Result 47796 states and 146330 transitions. [2019-12-07 17:41:13,954 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-12-07 17:41:13,954 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 72 [2019-12-07 17:41:13,954 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:14,012 INFO L225 Difference]: With dead ends: 47796 [2019-12-07 17:41:14,013 INFO L226 Difference]: Without dead ends: 46545 [2019-12-07 17:41:14,013 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 439 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=256, Invalid=1724, Unknown=0, NotChecked=0, Total=1980 [2019-12-07 17:41:14,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46545 states. [2019-12-07 17:41:14,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46545 to 32255. [2019-12-07 17:41:14,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32255 states. [2019-12-07 17:41:14,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32255 states to 32255 states and 98019 transitions. [2019-12-07 17:41:14,601 INFO L78 Accepts]: Start accepts. Automaton has 32255 states and 98019 transitions. Word has length 72 [2019-12-07 17:41:14,601 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:14,601 INFO L462 AbstractCegarLoop]: Abstraction has 32255 states and 98019 transitions. [2019-12-07 17:41:14,601 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 17:41:14,601 INFO L276 IsEmpty]: Start isEmpty. Operand 32255 states and 98019 transitions. [2019-12-07 17:41:14,634 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:41:14,634 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:14,634 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:14,634 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:14,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:14,634 INFO L82 PathProgramCache]: Analyzing trace with hash 92504751, now seen corresponding path program 26 times [2019-12-07 17:41:14,634 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:14,635 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [919030266] [2019-12-07 17:41:14,635 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:14,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:15,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:15,128 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [919030266] [2019-12-07 17:41:15,128 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:15,128 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2019-12-07 17:41:15,128 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1073964855] [2019-12-07 17:41:15,128 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-12-07 17:41:15,128 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:15,128 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 17:41:15,128 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=447, Unknown=0, NotChecked=0, Total=506 [2019-12-07 17:41:15,128 INFO L87 Difference]: Start difference. First operand 32255 states and 98019 transitions. Second operand 23 states. [2019-12-07 17:41:18,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:18,209 INFO L93 Difference]: Finished difference Result 63258 states and 193764 transitions. [2019-12-07 17:41:18,209 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2019-12-07 17:41:18,209 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 72 [2019-12-07 17:41:18,209 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:18,282 INFO L225 Difference]: With dead ends: 63258 [2019-12-07 17:41:18,282 INFO L226 Difference]: Without dead ends: 52038 [2019-12-07 17:41:18,283 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 725 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=338, Invalid=2632, Unknown=0, NotChecked=0, Total=2970 [2019-12-07 17:41:18,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52038 states. [2019-12-07 17:41:18,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52038 to 38095. [2019-12-07 17:41:18,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38095 states. [2019-12-07 17:41:19,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38095 states to 38095 states and 115076 transitions. [2019-12-07 17:41:19,009 INFO L78 Accepts]: Start accepts. Automaton has 38095 states and 115076 transitions. Word has length 72 [2019-12-07 17:41:19,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:19,009 INFO L462 AbstractCegarLoop]: Abstraction has 38095 states and 115076 transitions. [2019-12-07 17:41:19,009 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-12-07 17:41:19,009 INFO L276 IsEmpty]: Start isEmpty. Operand 38095 states and 115076 transitions. [2019-12-07 17:41:19,048 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:41:19,048 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:19,048 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:19,048 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:19,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:19,049 INFO L82 PathProgramCache]: Analyzing trace with hash -1539543125, now seen corresponding path program 27 times [2019-12-07 17:41:19,049 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:19,049 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782564351] [2019-12-07 17:41:19,049 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:19,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:19,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:19,499 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [782564351] [2019-12-07 17:41:19,499 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:19,499 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2019-12-07 17:41:19,499 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2097714533] [2019-12-07 17:41:19,499 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-12-07 17:41:19,499 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:19,499 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 17:41:19,499 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=447, Unknown=0, NotChecked=0, Total=506 [2019-12-07 17:41:19,499 INFO L87 Difference]: Start difference. First operand 38095 states and 115076 transitions. Second operand 23 states. [2019-12-07 17:41:22,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:22,761 INFO L93 Difference]: Finished difference Result 65379 states and 198764 transitions. [2019-12-07 17:41:22,761 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2019-12-07 17:41:22,761 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 72 [2019-12-07 17:41:22,761 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:22,830 INFO L225 Difference]: With dead ends: 65379 [2019-12-07 17:41:22,831 INFO L226 Difference]: Without dead ends: 52369 [2019-12-07 17:41:22,831 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 66 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1069 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=495, Invalid=3537, Unknown=0, NotChecked=0, Total=4032 [2019-12-07 17:41:22,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52369 states. [2019-12-07 17:41:23,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52369 to 32375. [2019-12-07 17:41:23,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32375 states. [2019-12-07 17:41:23,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32375 states to 32375 states and 95790 transitions. [2019-12-07 17:41:23,459 INFO L78 Accepts]: Start accepts. Automaton has 32375 states and 95790 transitions. Word has length 72 [2019-12-07 17:41:23,459 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:23,459 INFO L462 AbstractCegarLoop]: Abstraction has 32375 states and 95790 transitions. [2019-12-07 17:41:23,459 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-12-07 17:41:23,459 INFO L276 IsEmpty]: Start isEmpty. Operand 32375 states and 95790 transitions. [2019-12-07 17:41:23,492 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:41:23,492 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:23,492 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:23,493 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:23,493 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:23,493 INFO L82 PathProgramCache]: Analyzing trace with hash 2021763371, now seen corresponding path program 28 times [2019-12-07 17:41:23,493 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:23,493 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [33907915] [2019-12-07 17:41:23,493 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:23,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:23,691 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:23,691 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [33907915] [2019-12-07 17:41:23,691 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:23,691 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 17:41:23,691 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [655417876] [2019-12-07 17:41:23,691 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 17:41:23,691 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:23,691 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 17:41:23,691 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=153, Unknown=0, NotChecked=0, Total=182 [2019-12-07 17:41:23,692 INFO L87 Difference]: Start difference. First operand 32375 states and 95790 transitions. Second operand 14 states. [2019-12-07 17:41:24,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:24,882 INFO L93 Difference]: Finished difference Result 40644 states and 120218 transitions. [2019-12-07 17:41:24,882 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-12-07 17:41:24,883 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 72 [2019-12-07 17:41:24,883 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:24,926 INFO L225 Difference]: With dead ends: 40644 [2019-12-07 17:41:24,927 INFO L226 Difference]: Without dead ends: 37517 [2019-12-07 17:41:24,927 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 202 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=157, Invalid=899, Unknown=0, NotChecked=0, Total=1056 [2019-12-07 17:41:25,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37517 states. [2019-12-07 17:41:25,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37517 to 31464. [2019-12-07 17:41:25,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31464 states. [2019-12-07 17:41:25,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31464 states to 31464 states and 92976 transitions. [2019-12-07 17:41:25,423 INFO L78 Accepts]: Start accepts. Automaton has 31464 states and 92976 transitions. Word has length 72 [2019-12-07 17:41:25,423 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:25,424 INFO L462 AbstractCegarLoop]: Abstraction has 31464 states and 92976 transitions. [2019-12-07 17:41:25,424 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 17:41:25,424 INFO L276 IsEmpty]: Start isEmpty. Operand 31464 states and 92976 transitions. [2019-12-07 17:41:25,454 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:41:25,455 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:25,455 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:25,455 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:25,455 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:25,455 INFO L82 PathProgramCache]: Analyzing trace with hash 870577009, now seen corresponding path program 29 times [2019-12-07 17:41:25,455 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:25,455 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1558139570] [2019-12-07 17:41:25,455 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:25,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:25,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:25,751 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1558139570] [2019-12-07 17:41:25,751 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:25,751 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 17:41:25,751 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [113925890] [2019-12-07 17:41:25,751 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 17:41:25,751 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:25,751 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 17:41:25,751 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=267, Unknown=0, NotChecked=0, Total=306 [2019-12-07 17:41:25,752 INFO L87 Difference]: Start difference. First operand 31464 states and 92976 transitions. Second operand 18 states. [2019-12-07 17:41:30,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:30,246 INFO L93 Difference]: Finished difference Result 43489 states and 127306 transitions. [2019-12-07 17:41:30,247 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2019-12-07 17:41:30,247 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 72 [2019-12-07 17:41:30,247 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:30,291 INFO L225 Difference]: With dead ends: 43489 [2019-12-07 17:41:30,291 INFO L226 Difference]: Without dead ends: 38819 [2019-12-07 17:41:30,292 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 792 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=362, Invalid=2830, Unknown=0, NotChecked=0, Total=3192 [2019-12-07 17:41:30,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38819 states. [2019-12-07 17:41:30,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38819 to 32092. [2019-12-07 17:41:30,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32092 states. [2019-12-07 17:41:30,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32092 states to 32092 states and 94598 transitions. [2019-12-07 17:41:30,794 INFO L78 Accepts]: Start accepts. Automaton has 32092 states and 94598 transitions. Word has length 72 [2019-12-07 17:41:30,794 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:30,794 INFO L462 AbstractCegarLoop]: Abstraction has 32092 states and 94598 transitions. [2019-12-07 17:41:30,794 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 17:41:30,794 INFO L276 IsEmpty]: Start isEmpty. Operand 32092 states and 94598 transitions. [2019-12-07 17:41:30,826 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:41:30,826 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:30,826 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:30,826 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:30,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:30,827 INFO L82 PathProgramCache]: Analyzing trace with hash 1240848165, now seen corresponding path program 30 times [2019-12-07 17:41:30,827 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:30,827 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [450654041] [2019-12-07 17:41:30,827 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:30,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:31,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:31,443 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [450654041] [2019-12-07 17:41:31,443 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:31,443 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2019-12-07 17:41:31,443 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1931941292] [2019-12-07 17:41:31,444 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-12-07 17:41:31,444 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:31,444 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 17:41:31,444 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=537, Unknown=0, NotChecked=0, Total=600 [2019-12-07 17:41:31,444 INFO L87 Difference]: Start difference. First operand 32092 states and 94598 transitions. Second operand 25 states. [2019-12-07 17:41:33,408 WARN L192 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 27 DAG size of output: 25 [2019-12-07 17:41:36,001 WARN L192 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 26 DAG size of output: 25 [2019-12-07 17:41:37,822 WARN L192 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 32 DAG size of output: 29 [2019-12-07 17:41:38,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:38,488 INFO L93 Difference]: Finished difference Result 45247 states and 132015 transitions. [2019-12-07 17:41:38,488 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2019-12-07 17:41:38,488 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 72 [2019-12-07 17:41:38,488 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:38,540 INFO L225 Difference]: With dead ends: 45247 [2019-12-07 17:41:38,540 INFO L226 Difference]: Without dead ends: 45103 [2019-12-07 17:41:38,540 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 86 GetRequests, 7 SyntacticMatches, 2 SemanticMatches, 77 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1661 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=579, Invalid=5583, Unknown=0, NotChecked=0, Total=6162 [2019-12-07 17:41:38,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45103 states. [2019-12-07 17:41:39,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45103 to 38875. [2019-12-07 17:41:39,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38875 states. [2019-12-07 17:41:39,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38875 states to 38875 states and 114818 transitions. [2019-12-07 17:41:39,164 INFO L78 Accepts]: Start accepts. Automaton has 38875 states and 114818 transitions. Word has length 72 [2019-12-07 17:41:39,164 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:39,164 INFO L462 AbstractCegarLoop]: Abstraction has 38875 states and 114818 transitions. [2019-12-07 17:41:39,164 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-12-07 17:41:39,164 INFO L276 IsEmpty]: Start isEmpty. Operand 38875 states and 114818 transitions. [2019-12-07 17:41:39,202 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:41:39,202 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:39,202 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:39,202 INFO L410 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:39,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:39,202 INFO L82 PathProgramCache]: Analyzing trace with hash 330828919, now seen corresponding path program 31 times [2019-12-07 17:41:39,202 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:39,203 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [878113607] [2019-12-07 17:41:39,203 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:39,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:39,759 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:39,759 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [878113607] [2019-12-07 17:41:39,759 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:39,759 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2019-12-07 17:41:39,760 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1156912] [2019-12-07 17:41:39,760 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-12-07 17:41:39,760 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:39,760 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 17:41:39,760 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=336, Unknown=0, NotChecked=0, Total=380 [2019-12-07 17:41:39,760 INFO L87 Difference]: Start difference. First operand 38875 states and 114818 transitions. Second operand 20 states. [2019-12-07 17:41:40,807 WARN L192 SmtUtils]: Spent 114.00 ms on a formula simplification. DAG size of input: 27 DAG size of output: 26 [2019-12-07 17:41:44,074 WARN L192 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 31 DAG size of output: 30 [2019-12-07 17:41:45,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:45,991 INFO L93 Difference]: Finished difference Result 44569 states and 130627 transitions. [2019-12-07 17:41:45,992 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2019-12-07 17:41:45,992 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 72 [2019-12-07 17:41:45,992 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:46,043 INFO L225 Difference]: With dead ends: 44569 [2019-12-07 17:41:46,043 INFO L226 Difference]: Without dead ends: 44126 [2019-12-07 17:41:46,043 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 955 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=440, Invalid=3342, Unknown=0, NotChecked=0, Total=3782 [2019-12-07 17:41:46,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44126 states. [2019-12-07 17:41:46,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44126 to 39983. [2019-12-07 17:41:46,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39983 states. [2019-12-07 17:41:46,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39983 states to 39983 states and 118247 transitions. [2019-12-07 17:41:46,638 INFO L78 Accepts]: Start accepts. Automaton has 39983 states and 118247 transitions. Word has length 72 [2019-12-07 17:41:46,638 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:46,638 INFO L462 AbstractCegarLoop]: Abstraction has 39983 states and 118247 transitions. [2019-12-07 17:41:46,638 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-12-07 17:41:46,638 INFO L276 IsEmpty]: Start isEmpty. Operand 39983 states and 118247 transitions. [2019-12-07 17:41:46,676 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:41:46,676 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:46,676 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:46,676 INFO L410 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:46,677 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:46,677 INFO L82 PathProgramCache]: Analyzing trace with hash 1269932015, now seen corresponding path program 32 times [2019-12-07 17:41:46,677 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:46,677 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [866497482] [2019-12-07 17:41:46,677 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:46,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:46,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:46,966 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [866497482] [2019-12-07 17:41:46,966 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:46,966 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2019-12-07 17:41:46,966 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1854503954] [2019-12-07 17:41:46,967 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 17:41:46,967 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:46,967 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 17:41:46,967 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=299, Unknown=0, NotChecked=0, Total=342 [2019-12-07 17:41:46,967 INFO L87 Difference]: Start difference. First operand 39983 states and 118247 transitions. Second operand 19 states. [2019-12-07 17:41:54,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:41:54,707 INFO L93 Difference]: Finished difference Result 44087 states and 128813 transitions. [2019-12-07 17:41:54,707 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2019-12-07 17:41:54,707 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 72 [2019-12-07 17:41:54,707 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:41:54,758 INFO L225 Difference]: With dead ends: 44087 [2019-12-07 17:41:54,758 INFO L226 Difference]: Without dead ends: 42658 [2019-12-07 17:41:54,759 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 6 SyntacticMatches, 2 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 632 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=312, Invalid=2444, Unknown=0, NotChecked=0, Total=2756 [2019-12-07 17:41:54,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42658 states. [2019-12-07 17:41:55,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42658 to 39551. [2019-12-07 17:41:55,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39551 states. [2019-12-07 17:41:55,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39551 states to 39551 states and 117046 transitions. [2019-12-07 17:41:55,347 INFO L78 Accepts]: Start accepts. Automaton has 39551 states and 117046 transitions. Word has length 72 [2019-12-07 17:41:55,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:41:55,348 INFO L462 AbstractCegarLoop]: Abstraction has 39551 states and 117046 transitions. [2019-12-07 17:41:55,348 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 17:41:55,348 INFO L276 IsEmpty]: Start isEmpty. Operand 39551 states and 117046 transitions. [2019-12-07 17:41:55,387 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:41:55,387 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:41:55,388 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:41:55,388 INFO L410 AbstractCegarLoop]: === Iteration 40 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:41:55,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:41:55,388 INFO L82 PathProgramCache]: Analyzing trace with hash -156257871, now seen corresponding path program 33 times [2019-12-07 17:41:55,388 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:41:55,388 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1024189539] [2019-12-07 17:41:55,388 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:41:55,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:41:57,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:41:57,227 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1024189539] [2019-12-07 17:41:57,227 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:41:57,227 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [29] imperfect sequences [] total 29 [2019-12-07 17:41:57,227 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1676771721] [2019-12-07 17:41:57,228 INFO L442 AbstractCegarLoop]: Interpolant automaton has 31 states [2019-12-07 17:41:57,228 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:41:57,228 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2019-12-07 17:41:57,228 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=81, Invalid=849, Unknown=0, NotChecked=0, Total=930 [2019-12-07 17:41:57,228 INFO L87 Difference]: Start difference. First operand 39551 states and 117046 transitions. Second operand 31 states. [2019-12-07 17:41:58,989 WARN L192 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 31 DAG size of output: 30 [2019-12-07 17:42:00,553 WARN L192 SmtUtils]: Spent 193.00 ms on a formula simplification. DAG size of input: 42 DAG size of output: 40 [2019-12-07 17:42:02,146 WARN L192 SmtUtils]: Spent 100.00 ms on a formula simplification that was a NOOP. DAG size: 34 [2019-12-07 17:42:03,130 WARN L192 SmtUtils]: Spent 189.00 ms on a formula simplification. DAG size of input: 35 DAG size of output: 34 [2019-12-07 17:42:06,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:42:06,514 INFO L93 Difference]: Finished difference Result 41348 states and 121584 transitions. [2019-12-07 17:42:06,514 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2019-12-07 17:42:06,514 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 72 [2019-12-07 17:42:06,515 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:42:06,562 INFO L225 Difference]: With dead ends: 41348 [2019-12-07 17:42:06,562 INFO L226 Difference]: Without dead ends: 41328 [2019-12-07 17:42:06,563 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 5 SyntacticMatches, 4 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 924 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=399, Invalid=4023, Unknown=0, NotChecked=0, Total=4422 [2019-12-07 17:42:06,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41328 states. [2019-12-07 17:42:07,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41328 to 39847. [2019-12-07 17:42:07,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39847 states. [2019-12-07 17:42:07,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39847 states to 39847 states and 117705 transitions. [2019-12-07 17:42:07,129 INFO L78 Accepts]: Start accepts. Automaton has 39847 states and 117705 transitions. Word has length 72 [2019-12-07 17:42:07,129 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:42:07,130 INFO L462 AbstractCegarLoop]: Abstraction has 39847 states and 117705 transitions. [2019-12-07 17:42:07,130 INFO L463 AbstractCegarLoop]: Interpolant automaton has 31 states. [2019-12-07 17:42:07,130 INFO L276 IsEmpty]: Start isEmpty. Operand 39847 states and 117705 transitions. [2019-12-07 17:42:07,168 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:42:07,168 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:42:07,168 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:42:07,168 INFO L410 AbstractCegarLoop]: === Iteration 41 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:42:07,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:42:07,169 INFO L82 PathProgramCache]: Analyzing trace with hash 1964295839, now seen corresponding path program 34 times [2019-12-07 17:42:07,169 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:42:07,169 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1774014714] [2019-12-07 17:42:07,169 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:42:07,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:42:07,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:42:07,811 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1774014714] [2019-12-07 17:42:07,811 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:42:07,811 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [24] imperfect sequences [] total 24 [2019-12-07 17:42:07,811 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1853683085] [2019-12-07 17:42:07,811 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-12-07 17:42:07,811 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:42:07,812 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-12-07 17:42:07,812 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=585, Unknown=0, NotChecked=0, Total=650 [2019-12-07 17:42:07,812 INFO L87 Difference]: Start difference. First operand 39847 states and 117705 transitions. Second operand 26 states. [2019-12-07 17:42:11,279 WARN L192 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 29 DAG size of output: 27 [2019-12-07 17:42:11,606 WARN L192 SmtUtils]: Spent 129.00 ms on a formula simplification. DAG size of input: 24 DAG size of output: 23 [2019-12-07 17:42:13,834 WARN L192 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 28 DAG size of output: 27 [2019-12-07 17:42:14,140 WARN L192 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 28 DAG size of output: 27 [2019-12-07 17:42:15,106 WARN L192 SmtUtils]: Spent 147.00 ms on a formula simplification. DAG size of input: 30 DAG size of output: 29 [2019-12-07 17:42:15,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:42:15,604 INFO L93 Difference]: Finished difference Result 59378 states and 175130 transitions. [2019-12-07 17:42:15,604 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2019-12-07 17:42:15,604 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 72 [2019-12-07 17:42:15,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:42:15,680 INFO L225 Difference]: With dead ends: 59378 [2019-12-07 17:42:15,681 INFO L226 Difference]: Without dead ends: 59015 [2019-12-07 17:42:15,681 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 66 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 893 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=373, Invalid=3409, Unknown=0, NotChecked=0, Total=3782 [2019-12-07 17:42:15,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59015 states. [2019-12-07 17:42:16,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59015 to 44662. [2019-12-07 17:42:16,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44662 states. [2019-12-07 17:42:16,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44662 states to 44662 states and 132796 transitions. [2019-12-07 17:42:16,432 INFO L78 Accepts]: Start accepts. Automaton has 44662 states and 132796 transitions. Word has length 72 [2019-12-07 17:42:16,432 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:42:16,432 INFO L462 AbstractCegarLoop]: Abstraction has 44662 states and 132796 transitions. [2019-12-07 17:42:16,432 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-12-07 17:42:16,432 INFO L276 IsEmpty]: Start isEmpty. Operand 44662 states and 132796 transitions. [2019-12-07 17:42:16,475 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:42:16,475 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:42:16,476 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:42:16,476 INFO L410 AbstractCegarLoop]: === Iteration 42 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:42:16,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:42:16,476 INFO L82 PathProgramCache]: Analyzing trace with hash 1606292991, now seen corresponding path program 35 times [2019-12-07 17:42:16,476 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:42:16,476 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [73280301] [2019-12-07 17:42:16,476 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:42:16,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:42:16,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:42:16,992 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [73280301] [2019-12-07 17:42:16,992 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:42:16,992 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 17:42:16,992 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [591737316] [2019-12-07 17:42:16,992 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 17:42:16,993 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:42:16,993 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 17:42:16,993 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=488, Unknown=0, NotChecked=0, Total=552 [2019-12-07 17:42:16,993 INFO L87 Difference]: Start difference. First operand 44662 states and 132796 transitions. Second operand 24 states. [2019-12-07 17:42:20,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:42:20,263 INFO L93 Difference]: Finished difference Result 59900 states and 177472 transitions. [2019-12-07 17:42:20,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2019-12-07 17:42:20,263 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 17:42:20,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:42:20,342 INFO L225 Difference]: With dead ends: 59900 [2019-12-07 17:42:20,342 INFO L226 Difference]: Without dead ends: 59074 [2019-12-07 17:42:20,343 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 783 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=342, Invalid=2850, Unknown=0, NotChecked=0, Total=3192 [2019-12-07 17:42:20,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59074 states. [2019-12-07 17:42:21,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59074 to 44667. [2019-12-07 17:42:21,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44667 states. [2019-12-07 17:42:21,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44667 states to 44667 states and 133275 transitions. [2019-12-07 17:42:21,109 INFO L78 Accepts]: Start accepts. Automaton has 44667 states and 133275 transitions. Word has length 72 [2019-12-07 17:42:21,109 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:42:21,109 INFO L462 AbstractCegarLoop]: Abstraction has 44667 states and 133275 transitions. [2019-12-07 17:42:21,109 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 17:42:21,109 INFO L276 IsEmpty]: Start isEmpty. Operand 44667 states and 133275 transitions. [2019-12-07 17:42:21,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:42:21,154 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:42:21,154 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:42:21,154 INFO L410 AbstractCegarLoop]: === Iteration 43 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:42:21,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:42:21,154 INFO L82 PathProgramCache]: Analyzing trace with hash -1283212585, now seen corresponding path program 36 times [2019-12-07 17:42:21,154 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:42:21,154 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [193848302] [2019-12-07 17:42:21,154 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:42:21,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:42:23,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:42:23,091 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [193848302] [2019-12-07 17:42:23,091 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:42:23,092 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [31] imperfect sequences [] total 31 [2019-12-07 17:42:23,092 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1308478871] [2019-12-07 17:42:23,092 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2019-12-07 17:42:23,092 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:42:23,092 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2019-12-07 17:42:23,092 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=86, Invalid=970, Unknown=0, NotChecked=0, Total=1056 [2019-12-07 17:42:23,092 INFO L87 Difference]: Start difference. First operand 44667 states and 133275 transitions. Second operand 33 states. [2019-12-07 17:42:27,431 WARN L192 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 31 DAG size of output: 30 [2019-12-07 17:42:27,798 WARN L192 SmtUtils]: Spent 199.00 ms on a formula simplification. DAG size of input: 35 DAG size of output: 32 [2019-12-07 17:42:38,742 WARN L192 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 29 DAG size of output: 27 [2019-12-07 17:42:46,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:42:46,233 INFO L93 Difference]: Finished difference Result 55889 states and 161970 transitions. [2019-12-07 17:42:46,233 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 134 states. [2019-12-07 17:42:46,233 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 72 [2019-12-07 17:42:46,233 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:42:46,298 INFO L225 Difference]: With dead ends: 55889 [2019-12-07 17:42:46,298 INFO L226 Difference]: Without dead ends: 55515 [2019-12-07 17:42:46,299 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 152 GetRequests, 7 SyntacticMatches, 7 SemanticMatches, 138 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6221 ImplicationChecksByTransitivity, 8.7s TimeCoverageRelationStatistics Valid=1450, Invalid=18010, Unknown=0, NotChecked=0, Total=19460 [2019-12-07 17:42:46,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55515 states. [2019-12-07 17:42:46,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55515 to 47072. [2019-12-07 17:42:46,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47072 states. [2019-12-07 17:42:47,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47072 states to 47072 states and 138565 transitions. [2019-12-07 17:42:47,053 INFO L78 Accepts]: Start accepts. Automaton has 47072 states and 138565 transitions. Word has length 72 [2019-12-07 17:42:47,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:42:47,053 INFO L462 AbstractCegarLoop]: Abstraction has 47072 states and 138565 transitions. [2019-12-07 17:42:47,053 INFO L463 AbstractCegarLoop]: Interpolant automaton has 33 states. [2019-12-07 17:42:47,053 INFO L276 IsEmpty]: Start isEmpty. Operand 47072 states and 138565 transitions. [2019-12-07 17:42:47,098 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:42:47,098 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:42:47,098 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:42:47,098 INFO L410 AbstractCegarLoop]: === Iteration 44 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:42:47,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:42:47,099 INFO L82 PathProgramCache]: Analyzing trace with hash -1741411957, now seen corresponding path program 37 times [2019-12-07 17:42:47,099 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:42:47,099 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [788793629] [2019-12-07 17:42:47,099 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:42:47,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:42:47,800 WARN L192 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 28 DAG size of output: 25 [2019-12-07 17:42:48,075 WARN L192 SmtUtils]: Spent 145.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 28 [2019-12-07 17:42:48,324 WARN L192 SmtUtils]: Spent 166.00 ms on a formula simplification. DAG size of input: 45 DAG size of output: 30 [2019-12-07 17:42:48,582 WARN L192 SmtUtils]: Spent 187.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 23 [2019-12-07 17:42:48,905 WARN L192 SmtUtils]: Spent 217.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 25 [2019-12-07 17:42:49,353 WARN L192 SmtUtils]: Spent 256.00 ms on a formula simplification. DAG size of input: 30 DAG size of output: 27 [2019-12-07 17:42:49,620 WARN L192 SmtUtils]: Spent 170.00 ms on a formula simplification. DAG size of input: 26 DAG size of output: 23 [2019-12-07 17:42:49,934 WARN L192 SmtUtils]: Spent 214.00 ms on a formula simplification. DAG size of input: 28 DAG size of output: 25 [2019-12-07 17:42:50,272 WARN L192 SmtUtils]: Spent 219.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 23 [2019-12-07 17:42:50,633 WARN L192 SmtUtils]: Spent 217.00 ms on a formula simplification. DAG size of input: 39 DAG size of output: 21 [2019-12-07 17:42:50,922 WARN L192 SmtUtils]: Spent 161.00 ms on a formula simplification. DAG size of input: 22 DAG size of output: 19 [2019-12-07 17:42:51,168 WARN L192 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 16 DAG size of output: 13 [2019-12-07 17:42:51,291 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:42:51,292 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [788793629] [2019-12-07 17:42:51,292 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:42:51,292 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [25] imperfect sequences [] total 25 [2019-12-07 17:42:51,292 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [493441190] [2019-12-07 17:42:51,292 INFO L442 AbstractCegarLoop]: Interpolant automaton has 27 states [2019-12-07 17:42:51,292 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:42:51,292 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2019-12-07 17:42:51,293 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=635, Unknown=0, NotChecked=0, Total=702 [2019-12-07 17:42:51,293 INFO L87 Difference]: Start difference. First operand 47072 states and 138565 transitions. Second operand 27 states. [2019-12-07 17:42:55,272 WARN L192 SmtUtils]: Spent 140.00 ms on a formula simplification that was a NOOP. DAG size: 41 [2019-12-07 17:42:56,004 WARN L192 SmtUtils]: Spent 179.00 ms on a formula simplification. DAG size of input: 32 DAG size of output: 30 [2019-12-07 17:42:58,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:42:58,576 INFO L93 Difference]: Finished difference Result 56015 states and 163002 transitions. [2019-12-07 17:42:58,576 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2019-12-07 17:42:58,576 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 72 [2019-12-07 17:42:58,576 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:42:58,642 INFO L225 Difference]: With dead ends: 56015 [2019-12-07 17:42:58,643 INFO L226 Difference]: Without dead ends: 54071 [2019-12-07 17:42:58,643 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 941 ImplicationChecksByTransitivity, 6.3s TimeCoverageRelationStatistics Valid=420, Invalid=3870, Unknown=0, NotChecked=0, Total=4290 [2019-12-07 17:42:58,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54071 states. [2019-12-07 17:42:59,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54071 to 47730. [2019-12-07 17:42:59,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47730 states. [2019-12-07 17:42:59,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47730 states to 47730 states and 140260 transitions. [2019-12-07 17:42:59,362 INFO L78 Accepts]: Start accepts. Automaton has 47730 states and 140260 transitions. Word has length 72 [2019-12-07 17:42:59,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:42:59,362 INFO L462 AbstractCegarLoop]: Abstraction has 47730 states and 140260 transitions. [2019-12-07 17:42:59,362 INFO L463 AbstractCegarLoop]: Interpolant automaton has 27 states. [2019-12-07 17:42:59,362 INFO L276 IsEmpty]: Start isEmpty. Operand 47730 states and 140260 transitions. [2019-12-07 17:42:59,407 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:42:59,407 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:42:59,407 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:42:59,408 INFO L410 AbstractCegarLoop]: === Iteration 45 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:42:59,408 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:42:59,408 INFO L82 PathProgramCache]: Analyzing trace with hash -1385014915, now seen corresponding path program 38 times [2019-12-07 17:42:59,408 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:42:59,408 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [671851049] [2019-12-07 17:42:59,408 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:42:59,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:42:59,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:42:59,726 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [671851049] [2019-12-07 17:42:59,726 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:42:59,726 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 17:42:59,726 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [720557766] [2019-12-07 17:42:59,726 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 17:42:59,726 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:42:59,726 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 17:42:59,726 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=266, Unknown=0, NotChecked=0, Total=306 [2019-12-07 17:42:59,727 INFO L87 Difference]: Start difference. First operand 47730 states and 140260 transitions. Second operand 18 states. [2019-12-07 17:43:03,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:43:03,487 INFO L93 Difference]: Finished difference Result 55711 states and 162831 transitions. [2019-12-07 17:43:03,487 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2019-12-07 17:43:03,487 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 72 [2019-12-07 17:43:03,487 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:43:03,556 INFO L225 Difference]: With dead ends: 55711 [2019-12-07 17:43:03,556 INFO L226 Difference]: Without dead ends: 51718 [2019-12-07 17:43:03,556 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 557 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=303, Invalid=2147, Unknown=0, NotChecked=0, Total=2450 [2019-12-07 17:43:03,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51718 states. [2019-12-07 17:43:04,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51718 to 46515. [2019-12-07 17:43:04,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46515 states. [2019-12-07 17:43:04,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46515 states to 46515 states and 136872 transitions. [2019-12-07 17:43:04,265 INFO L78 Accepts]: Start accepts. Automaton has 46515 states and 136872 transitions. Word has length 72 [2019-12-07 17:43:04,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:43:04,265 INFO L462 AbstractCegarLoop]: Abstraction has 46515 states and 136872 transitions. [2019-12-07 17:43:04,265 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 17:43:04,266 INFO L276 IsEmpty]: Start isEmpty. Operand 46515 states and 136872 transitions. [2019-12-07 17:43:04,310 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:43:04,310 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:43:04,310 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:43:04,310 INFO L410 AbstractCegarLoop]: === Iteration 46 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:43:04,310 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:43:04,311 INFO L82 PathProgramCache]: Analyzing trace with hash -1389596133, now seen corresponding path program 39 times [2019-12-07 17:43:04,311 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:43:04,311 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [888515739] [2019-12-07 17:43:04,311 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:43:04,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:43:04,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:43:04,940 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [888515739] [2019-12-07 17:43:04,940 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:43:04,941 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2019-12-07 17:43:04,941 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1645587436] [2019-12-07 17:43:04,941 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-12-07 17:43:04,941 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:43:04,941 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 17:43:04,941 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=536, Unknown=0, NotChecked=0, Total=600 [2019-12-07 17:43:04,941 INFO L87 Difference]: Start difference. First operand 46515 states and 136872 transitions. Second operand 25 states. [2019-12-07 17:43:09,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:43:09,277 INFO L93 Difference]: Finished difference Result 59627 states and 172093 transitions. [2019-12-07 17:43:09,277 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2019-12-07 17:43:09,278 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 72 [2019-12-07 17:43:09,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:43:09,424 INFO L225 Difference]: With dead ends: 59627 [2019-12-07 17:43:09,424 INFO L226 Difference]: Without dead ends: 54478 [2019-12-07 17:43:09,425 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 3 SyntacticMatches, 5 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1384 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=523, Invalid=4589, Unknown=0, NotChecked=0, Total=5112 [2019-12-07 17:43:09,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54478 states. [2019-12-07 17:43:10,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54478 to 43503. [2019-12-07 17:43:10,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43503 states. [2019-12-07 17:43:10,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43503 states to 43503 states and 127515 transitions. [2019-12-07 17:43:10,081 INFO L78 Accepts]: Start accepts. Automaton has 43503 states and 127515 transitions. Word has length 72 [2019-12-07 17:43:10,081 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:43:10,081 INFO L462 AbstractCegarLoop]: Abstraction has 43503 states and 127515 transitions. [2019-12-07 17:43:10,081 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-12-07 17:43:10,081 INFO L276 IsEmpty]: Start isEmpty. Operand 43503 states and 127515 transitions. [2019-12-07 17:43:10,123 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:43:10,123 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:43:10,123 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:43:10,124 INFO L410 AbstractCegarLoop]: === Iteration 47 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:43:10,124 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:43:10,124 INFO L82 PathProgramCache]: Analyzing trace with hash 63589539, now seen corresponding path program 40 times [2019-12-07 17:43:10,124 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:43:10,124 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1680545648] [2019-12-07 17:43:10,124 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:43:10,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:43:10,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:43:10,435 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1680545648] [2019-12-07 17:43:10,435 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:43:10,435 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 17:43:10,435 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1435947168] [2019-12-07 17:43:10,435 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 17:43:10,435 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:43:10,435 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 17:43:10,435 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=237, Unknown=0, NotChecked=0, Total=272 [2019-12-07 17:43:10,436 INFO L87 Difference]: Start difference. First operand 43503 states and 127515 transitions. Second operand 17 states. [2019-12-07 17:43:12,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:43:12,538 INFO L93 Difference]: Finished difference Result 50699 states and 147493 transitions. [2019-12-07 17:43:12,538 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2019-12-07 17:43:12,539 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 72 [2019-12-07 17:43:12,539 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:43:12,597 INFO L225 Difference]: With dead ends: 50699 [2019-12-07 17:43:12,598 INFO L226 Difference]: Without dead ends: 48923 [2019-12-07 17:43:12,598 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 3 SyntacticMatches, 4 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 581 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=291, Invalid=2159, Unknown=0, NotChecked=0, Total=2450 [2019-12-07 17:43:12,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48923 states. [2019-12-07 17:43:13,177 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48923 to 44004. [2019-12-07 17:43:13,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44004 states. [2019-12-07 17:43:13,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44004 states to 44004 states and 128825 transitions. [2019-12-07 17:43:13,250 INFO L78 Accepts]: Start accepts. Automaton has 44004 states and 128825 transitions. Word has length 72 [2019-12-07 17:43:13,250 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:43:13,250 INFO L462 AbstractCegarLoop]: Abstraction has 44004 states and 128825 transitions. [2019-12-07 17:43:13,250 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 17:43:13,250 INFO L276 IsEmpty]: Start isEmpty. Operand 44004 states and 128825 transitions. [2019-12-07 17:43:13,292 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:43:13,292 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:43:13,292 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:43:13,292 INFO L410 AbstractCegarLoop]: === Iteration 48 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:43:13,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:43:13,292 INFO L82 PathProgramCache]: Analyzing trace with hash -604204727, now seen corresponding path program 41 times [2019-12-07 17:43:13,292 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:43:13,292 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1624201944] [2019-12-07 17:43:13,292 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:43:13,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:43:13,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:43:13,821 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1624201944] [2019-12-07 17:43:13,821 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:43:13,822 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 17:43:13,822 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1665279274] [2019-12-07 17:43:13,822 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 17:43:13,822 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:43:13,822 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 17:43:13,822 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=494, Unknown=0, NotChecked=0, Total=552 [2019-12-07 17:43:13,822 INFO L87 Difference]: Start difference. First operand 44004 states and 128825 transitions. Second operand 24 states. [2019-12-07 17:43:18,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:43:18,362 INFO L93 Difference]: Finished difference Result 62408 states and 180152 transitions. [2019-12-07 17:43:18,363 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2019-12-07 17:43:18,364 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 17:43:18,364 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:43:18,456 INFO L225 Difference]: With dead ends: 62408 [2019-12-07 17:43:18,456 INFO L226 Difference]: Without dead ends: 58132 [2019-12-07 17:43:18,457 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 71 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1145 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=510, Invalid=3912, Unknown=0, NotChecked=0, Total=4422 [2019-12-07 17:43:18,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58132 states. [2019-12-07 17:43:19,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58132 to 45419. [2019-12-07 17:43:19,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45419 states. [2019-12-07 17:43:19,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45419 states to 45419 states and 133164 transitions. [2019-12-07 17:43:19,275 INFO L78 Accepts]: Start accepts. Automaton has 45419 states and 133164 transitions. Word has length 72 [2019-12-07 17:43:19,275 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:43:19,275 INFO L462 AbstractCegarLoop]: Abstraction has 45419 states and 133164 transitions. [2019-12-07 17:43:19,275 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 17:43:19,275 INFO L276 IsEmpty]: Start isEmpty. Operand 45419 states and 133164 transitions. [2019-12-07 17:43:19,317 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:43:19,317 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:43:19,317 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:43:19,317 INFO L410 AbstractCegarLoop]: === Iteration 49 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:43:19,318 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:43:19,318 INFO L82 PathProgramCache]: Analyzing trace with hash -1510907327, now seen corresponding path program 42 times [2019-12-07 17:43:19,318 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:43:19,318 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1863150447] [2019-12-07 17:43:19,318 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:43:19,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:43:19,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:43:19,690 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1863150447] [2019-12-07 17:43:19,690 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:43:19,690 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 17:43:19,690 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [93215546] [2019-12-07 17:43:19,690 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 17:43:19,690 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:43:19,690 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 17:43:19,690 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=266, Unknown=0, NotChecked=0, Total=306 [2019-12-07 17:43:19,690 INFO L87 Difference]: Start difference. First operand 45419 states and 133164 transitions. Second operand 18 states. [2019-12-07 17:43:21,656 WARN L192 SmtUtils]: Spent 103.00 ms on a formula simplification. DAG size of input: 28 DAG size of output: 23 [2019-12-07 17:43:26,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:43:26,154 INFO L93 Difference]: Finished difference Result 54575 states and 158747 transitions. [2019-12-07 17:43:26,154 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-12-07 17:43:26,154 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 72 [2019-12-07 17:43:26,154 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:43:26,218 INFO L225 Difference]: With dead ends: 54575 [2019-12-07 17:43:26,218 INFO L226 Difference]: Without dead ends: 49486 [2019-12-07 17:43:26,218 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 556 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=297, Invalid=2153, Unknown=0, NotChecked=0, Total=2450 [2019-12-07 17:43:26,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49486 states. [2019-12-07 17:43:26,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49486 to 43775. [2019-12-07 17:43:26,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43775 states. [2019-12-07 17:43:26,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43775 states to 43775 states and 128231 transitions. [2019-12-07 17:43:26,900 INFO L78 Accepts]: Start accepts. Automaton has 43775 states and 128231 transitions. Word has length 72 [2019-12-07 17:43:26,900 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:43:26,900 INFO L462 AbstractCegarLoop]: Abstraction has 43775 states and 128231 transitions. [2019-12-07 17:43:26,900 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 17:43:26,900 INFO L276 IsEmpty]: Start isEmpty. Operand 43775 states and 128231 transitions. [2019-12-07 17:43:26,943 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:43:26,943 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:43:26,944 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:43:26,944 INFO L410 AbstractCegarLoop]: === Iteration 50 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:43:26,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:43:26,944 INFO L82 PathProgramCache]: Analyzing trace with hash 1403411495, now seen corresponding path program 43 times [2019-12-07 17:43:26,944 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:43:26,944 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1906332598] [2019-12-07 17:43:26,944 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:43:26,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:43:27,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:43:27,430 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1906332598] [2019-12-07 17:43:27,430 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:43:27,430 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 17:43:27,430 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [507490958] [2019-12-07 17:43:27,430 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 17:43:27,430 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:43:27,430 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 17:43:27,431 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=495, Unknown=0, NotChecked=0, Total=552 [2019-12-07 17:43:27,431 INFO L87 Difference]: Start difference. First operand 43775 states and 128231 transitions. Second operand 24 states. [2019-12-07 17:43:31,739 WARN L192 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 24 DAG size of output: 23 [2019-12-07 17:43:32,039 WARN L192 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 24 DAG size of output: 23 [2019-12-07 17:43:32,673 WARN L192 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 26 DAG size of output: 25 [2019-12-07 17:43:34,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:43:34,226 INFO L93 Difference]: Finished difference Result 67173 states and 194887 transitions. [2019-12-07 17:43:34,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2019-12-07 17:43:34,226 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 17:43:34,227 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:43:34,308 INFO L225 Difference]: With dead ends: 67173 [2019-12-07 17:43:34,308 INFO L226 Difference]: Without dead ends: 64057 [2019-12-07 17:43:34,309 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 65 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 900 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=368, Invalid=3292, Unknown=0, NotChecked=0, Total=3660 [2019-12-07 17:43:34,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64057 states. [2019-12-07 17:43:35,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64057 to 46427. [2019-12-07 17:43:35,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46427 states. [2019-12-07 17:43:35,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46427 states to 46427 states and 136312 transitions. [2019-12-07 17:43:35,125 INFO L78 Accepts]: Start accepts. Automaton has 46427 states and 136312 transitions. Word has length 72 [2019-12-07 17:43:35,125 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:43:35,126 INFO L462 AbstractCegarLoop]: Abstraction has 46427 states and 136312 transitions. [2019-12-07 17:43:35,126 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 17:43:35,126 INFO L276 IsEmpty]: Start isEmpty. Operand 46427 states and 136312 transitions. [2019-12-07 17:43:35,170 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:43:35,170 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:43:35,170 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:43:35,170 INFO L410 AbstractCegarLoop]: === Iteration 51 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:43:35,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:43:35,171 INFO L82 PathProgramCache]: Analyzing trace with hash -1155771941, now seen corresponding path program 44 times [2019-12-07 17:43:35,171 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:43:35,171 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815439142] [2019-12-07 17:43:35,171 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:43:35,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:43:35,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:43:35,870 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [815439142] [2019-12-07 17:43:35,870 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:43:35,870 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 17:43:35,870 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [113667602] [2019-12-07 17:43:35,870 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 17:43:35,871 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:43:35,871 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 17:43:35,871 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=491, Unknown=0, NotChecked=0, Total=552 [2019-12-07 17:43:35,871 INFO L87 Difference]: Start difference. First operand 46427 states and 136312 transitions. Second operand 24 states. [2019-12-07 17:43:36,983 WARN L192 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 30 DAG size of output: 28 [2019-12-07 17:43:38,166 WARN L192 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 32 DAG size of output: 29 [2019-12-07 17:43:39,140 WARN L192 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 35 [2019-12-07 17:43:39,912 WARN L192 SmtUtils]: Spent 204.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 35 [2019-12-07 17:43:40,557 WARN L192 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 35 DAG size of output: 32 [2019-12-07 17:43:40,923 WARN L192 SmtUtils]: Spent 165.00 ms on a formula simplification. DAG size of input: 35 DAG size of output: 33 [2019-12-07 17:43:42,070 WARN L192 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 31 DAG size of output: 29 [2019-12-07 17:43:43,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:43:43,579 INFO L93 Difference]: Finished difference Result 50569 states and 147064 transitions. [2019-12-07 17:43:43,579 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2019-12-07 17:43:43,579 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 17:43:43,580 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:43:43,646 INFO L225 Difference]: With dead ends: 50569 [2019-12-07 17:43:43,646 INFO L226 Difference]: Without dead ends: 50258 [2019-12-07 17:43:43,647 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 5 SyntacticMatches, 4 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1244 ImplicationChecksByTransitivity, 4.1s TimeCoverageRelationStatistics Valid=624, Invalid=4346, Unknown=0, NotChecked=0, Total=4970 [2019-12-07 17:43:43,777 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50258 states. [2019-12-07 17:43:44,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50258 to 46338. [2019-12-07 17:43:44,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46338 states. [2019-12-07 17:43:44,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46338 states to 46338 states and 136101 transitions. [2019-12-07 17:43:44,331 INFO L78 Accepts]: Start accepts. Automaton has 46338 states and 136101 transitions. Word has length 72 [2019-12-07 17:43:44,331 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:43:44,331 INFO L462 AbstractCegarLoop]: Abstraction has 46338 states and 136101 transitions. [2019-12-07 17:43:44,331 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 17:43:44,331 INFO L276 IsEmpty]: Start isEmpty. Operand 46338 states and 136101 transitions. [2019-12-07 17:43:44,375 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:43:44,375 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:43:44,375 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:43:44,376 INFO L410 AbstractCegarLoop]: === Iteration 52 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:43:44,376 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:43:44,376 INFO L82 PathProgramCache]: Analyzing trace with hash -116411483, now seen corresponding path program 45 times [2019-12-07 17:43:44,376 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:43:44,376 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2129252008] [2019-12-07 17:43:44,376 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:43:44,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:43:45,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:43:45,471 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2129252008] [2019-12-07 17:43:45,471 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:43:45,471 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [26] imperfect sequences [] total 26 [2019-12-07 17:43:45,471 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1508034425] [2019-12-07 17:43:45,471 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2019-12-07 17:43:45,471 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:43:45,471 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2019-12-07 17:43:45,471 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=682, Unknown=0, NotChecked=0, Total=756 [2019-12-07 17:43:45,472 INFO L87 Difference]: Start difference. First operand 46338 states and 136101 transitions. Second operand 28 states. [2019-12-07 17:43:46,828 WARN L192 SmtUtils]: Spent 127.00 ms on a formula simplification. DAG size of input: 33 DAG size of output: 30 [2019-12-07 17:43:47,344 WARN L192 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 37 DAG size of output: 34 [2019-12-07 17:43:50,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:43:50,636 INFO L93 Difference]: Finished difference Result 52836 states and 155073 transitions. [2019-12-07 17:43:50,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2019-12-07 17:43:50,637 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 72 [2019-12-07 17:43:50,637 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:43:50,704 INFO L225 Difference]: With dead ends: 52836 [2019-12-07 17:43:50,704 INFO L226 Difference]: Without dead ends: 50028 [2019-12-07 17:43:50,705 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 671 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=404, Invalid=3256, Unknown=0, NotChecked=0, Total=3660 [2019-12-07 17:43:50,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50028 states. [2019-12-07 17:43:51,312 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50028 to 46669. [2019-12-07 17:43:51,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46669 states. [2019-12-07 17:43:51,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46669 states to 46669 states and 136961 transitions. [2019-12-07 17:43:51,389 INFO L78 Accepts]: Start accepts. Automaton has 46669 states and 136961 transitions. Word has length 72 [2019-12-07 17:43:51,389 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:43:51,390 INFO L462 AbstractCegarLoop]: Abstraction has 46669 states and 136961 transitions. [2019-12-07 17:43:51,390 INFO L463 AbstractCegarLoop]: Interpolant automaton has 28 states. [2019-12-07 17:43:51,390 INFO L276 IsEmpty]: Start isEmpty. Operand 46669 states and 136961 transitions. [2019-12-07 17:43:51,435 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:43:51,435 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:43:51,435 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:43:51,435 INFO L410 AbstractCegarLoop]: === Iteration 53 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:43:51,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:43:51,435 INFO L82 PathProgramCache]: Analyzing trace with hash -1202538871, now seen corresponding path program 46 times [2019-12-07 17:43:51,435 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:43:51,435 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1645522763] [2019-12-07 17:43:51,436 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:43:51,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:43:51,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:43:51,842 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1645522763] [2019-12-07 17:43:51,842 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:43:51,843 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 17:43:51,843 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [133699943] [2019-12-07 17:43:51,843 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 17:43:51,843 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:43:51,843 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 17:43:51,843 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=235, Unknown=0, NotChecked=0, Total=272 [2019-12-07 17:43:51,843 INFO L87 Difference]: Start difference. First operand 46669 states and 136961 transitions. Second operand 17 states. [2019-12-07 17:43:56,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:43:56,208 INFO L93 Difference]: Finished difference Result 56231 states and 164740 transitions. [2019-12-07 17:43:56,209 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2019-12-07 17:43:56,209 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 72 [2019-12-07 17:43:56,209 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:43:56,276 INFO L225 Difference]: With dead ends: 56231 [2019-12-07 17:43:56,276 INFO L226 Difference]: Without dead ends: 51044 [2019-12-07 17:43:56,277 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 357 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=252, Invalid=1640, Unknown=0, NotChecked=0, Total=1892 [2019-12-07 17:43:56,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51044 states. [2019-12-07 17:43:56,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51044 to 46532. [2019-12-07 17:43:56,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46532 states. [2019-12-07 17:43:56,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46532 states to 46532 states and 136395 transitions. [2019-12-07 17:43:56,971 INFO L78 Accepts]: Start accepts. Automaton has 46532 states and 136395 transitions. Word has length 72 [2019-12-07 17:43:56,971 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:43:56,971 INFO L462 AbstractCegarLoop]: Abstraction has 46532 states and 136395 transitions. [2019-12-07 17:43:56,971 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 17:43:56,971 INFO L276 IsEmpty]: Start isEmpty. Operand 46532 states and 136395 transitions. [2019-12-07 17:43:57,015 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:43:57,015 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:43:57,016 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:43:57,016 INFO L410 AbstractCegarLoop]: === Iteration 54 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:43:57,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:43:57,016 INFO L82 PathProgramCache]: Analyzing trace with hash 1551628491, now seen corresponding path program 47 times [2019-12-07 17:43:57,016 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:43:57,016 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1920941065] [2019-12-07 17:43:57,016 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:43:57,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:43:57,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:43:57,184 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1920941065] [2019-12-07 17:43:57,184 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:43:57,184 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 17:43:57,184 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [329489455] [2019-12-07 17:43:57,184 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 17:43:57,184 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:43:57,184 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 17:43:57,184 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=130, Unknown=0, NotChecked=0, Total=156 [2019-12-07 17:43:57,184 INFO L87 Difference]: Start difference. First operand 46532 states and 136395 transitions. Second operand 13 states. [2019-12-07 17:43:58,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:43:58,508 INFO L93 Difference]: Finished difference Result 59389 states and 172795 transitions. [2019-12-07 17:43:58,508 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 17:43:58,508 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 72 [2019-12-07 17:43:58,508 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:43:58,581 INFO L225 Difference]: With dead ends: 59389 [2019-12-07 17:43:58,581 INFO L226 Difference]: Without dead ends: 55898 [2019-12-07 17:43:58,581 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 85 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=101, Invalid=499, Unknown=0, NotChecked=0, Total=600 [2019-12-07 17:43:58,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55898 states. [2019-12-07 17:43:59,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55898 to 46766. [2019-12-07 17:43:59,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46766 states. [2019-12-07 17:43:59,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46766 states to 46766 states and 136971 transitions. [2019-12-07 17:43:59,300 INFO L78 Accepts]: Start accepts. Automaton has 46766 states and 136971 transitions. Word has length 72 [2019-12-07 17:43:59,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:43:59,301 INFO L462 AbstractCegarLoop]: Abstraction has 46766 states and 136971 transitions. [2019-12-07 17:43:59,301 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 17:43:59,301 INFO L276 IsEmpty]: Start isEmpty. Operand 46766 states and 136971 transitions. [2019-12-07 17:43:59,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:43:59,345 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:43:59,345 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:43:59,345 INFO L410 AbstractCegarLoop]: === Iteration 55 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:43:59,345 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:43:59,345 INFO L82 PathProgramCache]: Analyzing trace with hash -1084039497, now seen corresponding path program 48 times [2019-12-07 17:43:59,345 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:43:59,345 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418897307] [2019-12-07 17:43:59,346 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:43:59,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:44:00,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:44:00,282 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1418897307] [2019-12-07 17:44:00,282 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:44:00,282 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [24] imperfect sequences [] total 24 [2019-12-07 17:44:00,283 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [726559731] [2019-12-07 17:44:00,283 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-12-07 17:44:00,283 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:44:00,283 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-12-07 17:44:00,283 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=582, Unknown=0, NotChecked=0, Total=650 [2019-12-07 17:44:00,283 INFO L87 Difference]: Start difference. First operand 46766 states and 136971 transitions. Second operand 26 states. [2019-12-07 17:44:04,064 WARN L192 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 26 DAG size of output: 25 [2019-12-07 17:44:04,535 WARN L192 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 29 DAG size of output: 27 [2019-12-07 17:44:07,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:44:07,039 INFO L93 Difference]: Finished difference Result 54546 states and 158632 transitions. [2019-12-07 17:44:07,039 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2019-12-07 17:44:07,039 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 72 [2019-12-07 17:44:07,039 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:44:07,102 INFO L225 Difference]: With dead ends: 54546 [2019-12-07 17:44:07,102 INFO L226 Difference]: Without dead ends: 54458 [2019-12-07 17:44:07,102 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 5 SyntacticMatches, 5 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 949 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=428, Invalid=3604, Unknown=0, NotChecked=0, Total=4032 [2019-12-07 17:44:07,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54458 states. [2019-12-07 17:44:07,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54458 to 48421. [2019-12-07 17:44:07,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48421 states. [2019-12-07 17:44:07,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48421 states to 48421 states and 141922 transitions. [2019-12-07 17:44:07,837 INFO L78 Accepts]: Start accepts. Automaton has 48421 states and 141922 transitions. Word has length 72 [2019-12-07 17:44:07,837 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:44:07,837 INFO L462 AbstractCegarLoop]: Abstraction has 48421 states and 141922 transitions. [2019-12-07 17:44:07,837 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-12-07 17:44:07,837 INFO L276 IsEmpty]: Start isEmpty. Operand 48421 states and 141922 transitions. [2019-12-07 17:44:07,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:44:07,884 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:44:07,884 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:44:07,884 INFO L410 AbstractCegarLoop]: === Iteration 56 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:44:07,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:44:07,884 INFO L82 PathProgramCache]: Analyzing trace with hash 1537410035, now seen corresponding path program 49 times [2019-12-07 17:44:07,884 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:44:07,885 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764005455] [2019-12-07 17:44:07,885 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:44:07,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:44:08,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:44:08,188 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1764005455] [2019-12-07 17:44:08,188 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:44:08,188 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 17:44:08,189 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1920275944] [2019-12-07 17:44:08,189 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 17:44:08,189 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:44:08,189 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 17:44:08,189 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=178, Unknown=0, NotChecked=0, Total=210 [2019-12-07 17:44:08,189 INFO L87 Difference]: Start difference. First operand 48421 states and 141922 transitions. Second operand 15 states. [2019-12-07 17:44:09,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:44:09,818 INFO L93 Difference]: Finished difference Result 61428 states and 180573 transitions. [2019-12-07 17:44:09,818 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2019-12-07 17:44:09,818 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 72 [2019-12-07 17:44:09,818 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:44:09,900 INFO L225 Difference]: With dead ends: 61428 [2019-12-07 17:44:09,900 INFO L226 Difference]: Without dead ends: 60485 [2019-12-07 17:44:09,901 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 192 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=184, Invalid=1006, Unknown=0, NotChecked=0, Total=1190 [2019-12-07 17:44:10,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60485 states. [2019-12-07 17:44:10,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60485 to 54194. [2019-12-07 17:44:10,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54194 states. [2019-12-07 17:44:10,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54194 states to 54194 states and 160699 transitions. [2019-12-07 17:44:10,773 INFO L78 Accepts]: Start accepts. Automaton has 54194 states and 160699 transitions. Word has length 72 [2019-12-07 17:44:10,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:44:10,773 INFO L462 AbstractCegarLoop]: Abstraction has 54194 states and 160699 transitions. [2019-12-07 17:44:10,773 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 17:44:10,773 INFO L276 IsEmpty]: Start isEmpty. Operand 54194 states and 160699 transitions. [2019-12-07 17:44:10,837 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:44:10,837 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:44:10,837 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:44:10,837 INFO L410 AbstractCegarLoop]: === Iteration 57 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:44:10,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:44:10,838 INFO L82 PathProgramCache]: Analyzing trace with hash 981281827, now seen corresponding path program 50 times [2019-12-07 17:44:10,838 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:44:10,838 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [594558168] [2019-12-07 17:44:10,838 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:44:10,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:44:11,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:44:11,130 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [594558168] [2019-12-07 17:44:11,130 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:44:11,130 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 17:44:11,130 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1147554356] [2019-12-07 17:44:11,130 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 17:44:11,131 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:44:11,131 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 17:44:11,131 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=178, Unknown=0, NotChecked=0, Total=210 [2019-12-07 17:44:11,131 INFO L87 Difference]: Start difference. First operand 54194 states and 160699 transitions. Second operand 15 states. [2019-12-07 17:44:14,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:44:14,712 INFO L93 Difference]: Finished difference Result 60830 states and 178113 transitions. [2019-12-07 17:44:14,713 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-12-07 17:44:14,714 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 72 [2019-12-07 17:44:14,714 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:44:14,810 INFO L225 Difference]: With dead ends: 60830 [2019-12-07 17:44:14,810 INFO L226 Difference]: Without dead ends: 58209 [2019-12-07 17:44:14,810 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 176 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=178, Invalid=944, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 17:44:14,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58209 states. [2019-12-07 17:44:15,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58209 to 48687. [2019-12-07 17:44:15,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48687 states. [2019-12-07 17:44:15,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48687 states to 48687 states and 143281 transitions. [2019-12-07 17:44:15,591 INFO L78 Accepts]: Start accepts. Automaton has 48687 states and 143281 transitions. Word has length 72 [2019-12-07 17:44:15,591 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:44:15,591 INFO L462 AbstractCegarLoop]: Abstraction has 48687 states and 143281 transitions. [2019-12-07 17:44:15,591 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 17:44:15,591 INFO L276 IsEmpty]: Start isEmpty. Operand 48687 states and 143281 transitions. [2019-12-07 17:44:15,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:44:15,638 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:44:15,638 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:44:15,638 INFO L410 AbstractCegarLoop]: === Iteration 58 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:44:15,639 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:44:15,639 INFO L82 PathProgramCache]: Analyzing trace with hash 1089087959, now seen corresponding path program 51 times [2019-12-07 17:44:15,639 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:44:15,639 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [221679419] [2019-12-07 17:44:15,639 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:44:15,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:44:15,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:44:15,949 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [221679419] [2019-12-07 17:44:15,949 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:44:15,949 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 17:44:15,950 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [621900794] [2019-12-07 17:44:15,950 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 17:44:15,950 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:44:15,950 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 17:44:15,950 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-12-07 17:44:15,950 INFO L87 Difference]: Start difference. First operand 48687 states and 143281 transitions. Second operand 16 states. [2019-12-07 17:44:17,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:44:17,545 INFO L93 Difference]: Finished difference Result 55805 states and 161816 transitions. [2019-12-07 17:44:17,545 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2019-12-07 17:44:17,545 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2019-12-07 17:44:17,545 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:44:17,618 INFO L225 Difference]: With dead ends: 55805 [2019-12-07 17:44:17,618 INFO L226 Difference]: Without dead ends: 55769 [2019-12-07 17:44:17,619 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 180 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=180, Invalid=1010, Unknown=0, NotChecked=0, Total=1190 [2019-12-07 17:44:17,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55769 states. [2019-12-07 17:44:18,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55769 to 49767. [2019-12-07 17:44:18,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49767 states. [2019-12-07 17:44:18,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49767 states to 49767 states and 145875 transitions. [2019-12-07 17:44:18,407 INFO L78 Accepts]: Start accepts. Automaton has 49767 states and 145875 transitions. Word has length 72 [2019-12-07 17:44:18,407 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:44:18,407 INFO L462 AbstractCegarLoop]: Abstraction has 49767 states and 145875 transitions. [2019-12-07 17:44:18,407 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 17:44:18,407 INFO L276 IsEmpty]: Start isEmpty. Operand 49767 states and 145875 transitions. [2019-12-07 17:44:18,465 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:44:18,466 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:44:18,466 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:44:18,466 INFO L410 AbstractCegarLoop]: === Iteration 59 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:44:18,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:44:18,466 INFO L82 PathProgramCache]: Analyzing trace with hash 1118171809, now seen corresponding path program 52 times [2019-12-07 17:44:18,466 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:44:18,466 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1467200519] [2019-12-07 17:44:18,466 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:44:18,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:44:18,740 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:44:18,740 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1467200519] [2019-12-07 17:44:18,740 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:44:18,740 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 17:44:18,740 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [721381474] [2019-12-07 17:44:18,740 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 17:44:18,740 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:44:18,740 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 17:44:18,741 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2019-12-07 17:44:18,741 INFO L87 Difference]: Start difference. First operand 49767 states and 145875 transitions. Second operand 16 states. [2019-12-07 17:44:20,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:44:20,908 INFO L93 Difference]: Finished difference Result 53834 states and 156513 transitions. [2019-12-07 17:44:20,908 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2019-12-07 17:44:20,909 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2019-12-07 17:44:20,909 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:44:20,977 INFO L225 Difference]: With dead ends: 53834 [2019-12-07 17:44:20,977 INFO L226 Difference]: Without dead ends: 53539 [2019-12-07 17:44:20,977 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 258 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=217, Invalid=1265, Unknown=0, NotChecked=0, Total=1482 [2019-12-07 17:44:21,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53539 states. [2019-12-07 17:44:21,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53539 to 49701. [2019-12-07 17:44:21,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49701 states. [2019-12-07 17:44:21,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49701 states to 49701 states and 145726 transitions. [2019-12-07 17:44:21,749 INFO L78 Accepts]: Start accepts. Automaton has 49701 states and 145726 transitions. Word has length 72 [2019-12-07 17:44:21,749 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:44:21,749 INFO L462 AbstractCegarLoop]: Abstraction has 49701 states and 145726 transitions. [2019-12-07 17:44:21,749 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 17:44:21,749 INFO L276 IsEmpty]: Start isEmpty. Operand 49701 states and 145726 transitions. [2019-12-07 17:44:21,805 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:44:21,805 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:44:21,806 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:44:21,806 INFO L410 AbstractCegarLoop]: === Iteration 60 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:44:21,806 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:44:21,806 INFO L82 PathProgramCache]: Analyzing trace with hash 2119557665, now seen corresponding path program 53 times [2019-12-07 17:44:21,806 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:44:21,806 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [669598175] [2019-12-07 17:44:21,806 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:44:21,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:44:22,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:44:22,335 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [669598175] [2019-12-07 17:44:22,335 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:44:22,335 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 17:44:22,336 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [769520581] [2019-12-07 17:44:22,336 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 17:44:22,336 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:44:22,336 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 17:44:22,336 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=496, Unknown=0, NotChecked=0, Total=552 [2019-12-07 17:44:22,336 INFO L87 Difference]: Start difference. First operand 49701 states and 145726 transitions. Second operand 24 states. [2019-12-07 17:44:29,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:44:29,033 INFO L93 Difference]: Finished difference Result 66647 states and 194847 transitions. [2019-12-07 17:44:29,033 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2019-12-07 17:44:29,033 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 17:44:29,033 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:44:29,117 INFO L225 Difference]: With dead ends: 66647 [2019-12-07 17:44:29,117 INFO L226 Difference]: Without dead ends: 65288 [2019-12-07 17:44:29,117 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 550 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=273, Invalid=2379, Unknown=0, NotChecked=0, Total=2652 [2019-12-07 17:44:29,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65288 states. [2019-12-07 17:44:29,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65288 to 50781. [2019-12-07 17:44:29,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50781 states. [2019-12-07 17:44:30,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50781 states to 50781 states and 149033 transitions. [2019-12-07 17:44:30,083 INFO L78 Accepts]: Start accepts. Automaton has 50781 states and 149033 transitions. Word has length 72 [2019-12-07 17:44:30,083 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:44:30,083 INFO L462 AbstractCegarLoop]: Abstraction has 50781 states and 149033 transitions. [2019-12-07 17:44:30,083 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 17:44:30,083 INFO L276 IsEmpty]: Start isEmpty. Operand 50781 states and 149033 transitions. [2019-12-07 17:44:30,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:44:30,137 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:44:30,137 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:44:30,137 INFO L410 AbstractCegarLoop]: === Iteration 61 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:44:30,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:44:30,138 INFO L82 PathProgramCache]: Analyzing trace with hash 1033430277, now seen corresponding path program 54 times [2019-12-07 17:44:30,138 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:44:30,138 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [911082150] [2019-12-07 17:44:30,138 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:44:30,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:44:30,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:44:30,428 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [911082150] [2019-12-07 17:44:30,428 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:44:30,429 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 17:44:30,429 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [764841400] [2019-12-07 17:44:30,429 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 17:44:30,429 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:44:30,429 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 17:44:30,429 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-12-07 17:44:30,429 INFO L87 Difference]: Start difference. First operand 50781 states and 149033 transitions. Second operand 16 states. [2019-12-07 17:44:32,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:44:32,133 INFO L93 Difference]: Finished difference Result 63047 states and 183248 transitions. [2019-12-07 17:44:32,133 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2019-12-07 17:44:32,133 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2019-12-07 17:44:32,133 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:44:32,215 INFO L225 Difference]: With dead ends: 63047 [2019-12-07 17:44:32,215 INFO L226 Difference]: Without dead ends: 59451 [2019-12-07 17:44:32,215 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 272 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=208, Invalid=1274, Unknown=0, NotChecked=0, Total=1482 [2019-12-07 17:44:32,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59451 states. [2019-12-07 17:44:32,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59451 to 51381. [2019-12-07 17:44:32,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51381 states. [2019-12-07 17:44:33,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51381 states to 51381 states and 151043 transitions. [2019-12-07 17:44:33,039 INFO L78 Accepts]: Start accepts. Automaton has 51381 states and 151043 transitions. Word has length 72 [2019-12-07 17:44:33,039 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:44:33,039 INFO L462 AbstractCegarLoop]: Abstraction has 51381 states and 151043 transitions. [2019-12-07 17:44:33,039 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 17:44:33,039 INFO L276 IsEmpty]: Start isEmpty. Operand 51381 states and 151043 transitions. [2019-12-07 17:44:33,097 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:44:33,097 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:44:33,097 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:44:33,098 INFO L410 AbstractCegarLoop]: === Iteration 62 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:44:33,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:44:33,098 INFO L82 PathProgramCache]: Analyzing trace with hash -906939439, now seen corresponding path program 55 times [2019-12-07 17:44:33,098 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:44:33,098 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1473525639] [2019-12-07 17:44:33,098 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:44:33,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:44:33,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:44:33,445 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1473525639] [2019-12-07 17:44:33,446 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:44:33,446 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2019-12-07 17:44:33,446 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [344918598] [2019-12-07 17:44:33,446 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 17:44:33,446 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:44:33,446 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 17:44:33,446 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=302, Unknown=0, NotChecked=0, Total=342 [2019-12-07 17:44:33,446 INFO L87 Difference]: Start difference. First operand 51381 states and 151043 transitions. Second operand 19 states. [2019-12-07 17:44:37,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:44:37,188 INFO L93 Difference]: Finished difference Result 55085 states and 161006 transitions. [2019-12-07 17:44:37,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2019-12-07 17:44:37,189 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 72 [2019-12-07 17:44:37,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:44:37,279 INFO L225 Difference]: With dead ends: 55085 [2019-12-07 17:44:37,279 INFO L226 Difference]: Without dead ends: 55049 [2019-12-07 17:44:37,280 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 225 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=181, Invalid=1301, Unknown=0, NotChecked=0, Total=1482 [2019-12-07 17:44:37,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55049 states. [2019-12-07 17:44:37,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55049 to 51543. [2019-12-07 17:44:37,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51543 states. [2019-12-07 17:44:38,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51543 states to 51543 states and 151571 transitions. [2019-12-07 17:44:38,062 INFO L78 Accepts]: Start accepts. Automaton has 51543 states and 151571 transitions. Word has length 72 [2019-12-07 17:44:38,062 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:44:38,062 INFO L462 AbstractCegarLoop]: Abstraction has 51543 states and 151571 transitions. [2019-12-07 17:44:38,062 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 17:44:38,062 INFO L276 IsEmpty]: Start isEmpty. Operand 51543 states and 151571 transitions. [2019-12-07 17:44:38,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:44:38,120 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:44:38,120 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:44:38,120 INFO L410 AbstractCegarLoop]: === Iteration 63 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:44:38,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:44:38,121 INFO L82 PathProgramCache]: Analyzing trace with hash -877855589, now seen corresponding path program 56 times [2019-12-07 17:44:38,121 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:44:38,121 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [420437108] [2019-12-07 17:44:38,121 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:44:38,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:44:38,982 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:44:38,982 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [420437108] [2019-12-07 17:44:38,983 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:44:38,983 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [25] imperfect sequences [] total 25 [2019-12-07 17:44:38,983 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414134279] [2019-12-07 17:44:38,983 INFO L442 AbstractCegarLoop]: Interpolant automaton has 27 states [2019-12-07 17:44:38,983 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:44:38,983 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2019-12-07 17:44:38,983 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=637, Unknown=0, NotChecked=0, Total=702 [2019-12-07 17:44:38,983 INFO L87 Difference]: Start difference. First operand 51543 states and 151571 transitions. Second operand 27 states. [2019-12-07 17:44:40,716 WARN L192 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 28 DAG size of output: 27 [2019-12-07 17:44:40,976 WARN L192 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 26 DAG size of output: 25 [2019-12-07 17:44:41,198 WARN L192 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 28 DAG size of output: 27 [2019-12-07 17:44:41,445 WARN L192 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 29 DAG size of output: 27 [2019-12-07 17:44:41,921 WARN L192 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 26 DAG size of output: 25 [2019-12-07 17:44:42,420 WARN L192 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 27 DAG size of output: 25 [2019-12-07 17:44:42,925 WARN L192 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 29 DAG size of output: 27 [2019-12-07 17:44:43,265 WARN L192 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 32 DAG size of output: 29 [2019-12-07 17:44:43,700 WARN L192 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 30 DAG size of output: 27 [2019-12-07 17:44:44,422 WARN L192 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 30 DAG size of output: 27 [2019-12-07 17:44:45,545 WARN L192 SmtUtils]: Spent 167.00 ms on a formula simplification. DAG size of input: 33 DAG size of output: 29 [2019-12-07 17:44:46,980 WARN L192 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 32 DAG size of output: 29 [2019-12-07 17:44:50,075 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:44:50,075 INFO L93 Difference]: Finished difference Result 64723 states and 187684 transitions. [2019-12-07 17:44:50,075 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2019-12-07 17:44:50,075 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 72 [2019-12-07 17:44:50,075 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:44:50,153 INFO L225 Difference]: With dead ends: 64723 [2019-12-07 17:44:50,154 INFO L226 Difference]: Without dead ends: 62692 [2019-12-07 17:44:50,154 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 753 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=354, Invalid=3186, Unknown=0, NotChecked=0, Total=3540 [2019-12-07 17:44:50,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62692 states. [2019-12-07 17:44:50,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62692 to 52987. [2019-12-07 17:44:50,915 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52987 states. [2019-12-07 17:44:51,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52987 states to 52987 states and 155804 transitions. [2019-12-07 17:44:51,009 INFO L78 Accepts]: Start accepts. Automaton has 52987 states and 155804 transitions. Word has length 72 [2019-12-07 17:44:51,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:44:51,009 INFO L462 AbstractCegarLoop]: Abstraction has 52987 states and 155804 transitions. [2019-12-07 17:44:51,009 INFO L463 AbstractCegarLoop]: Interpolant automaton has 27 states. [2019-12-07 17:44:51,009 INFO L276 IsEmpty]: Start isEmpty. Operand 52987 states and 155804 transitions. [2019-12-07 17:44:51,070 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:44:51,070 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:44:51,070 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:44:51,071 INFO L410 AbstractCegarLoop]: === Iteration 64 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:44:51,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:44:51,071 INFO L82 PathProgramCache]: Analyzing trace with hash 182852623, now seen corresponding path program 57 times [2019-12-07 17:44:51,071 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:44:51,071 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [885635239] [2019-12-07 17:44:51,071 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:44:51,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:44:51,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:44:51,429 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [885635239] [2019-12-07 17:44:51,430 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:44:51,430 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 17:44:51,430 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [608955624] [2019-12-07 17:44:51,430 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 17:44:51,430 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:44:51,430 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 17:44:51,430 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=267, Unknown=0, NotChecked=0, Total=306 [2019-12-07 17:44:51,430 INFO L87 Difference]: Start difference. First operand 52987 states and 155804 transitions. Second operand 18 states. [2019-12-07 17:44:53,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:44:53,637 INFO L93 Difference]: Finished difference Result 57802 states and 168500 transitions. [2019-12-07 17:44:53,637 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2019-12-07 17:44:53,637 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 72 [2019-12-07 17:44:53,637 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:44:53,708 INFO L225 Difference]: With dead ends: 57802 [2019-12-07 17:44:53,709 INFO L226 Difference]: Without dead ends: 55847 [2019-12-07 17:44:53,709 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 359 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=257, Invalid=1723, Unknown=0, NotChecked=0, Total=1980 [2019-12-07 17:44:53,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55847 states. [2019-12-07 17:44:54,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55847 to 52700. [2019-12-07 17:44:54,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52700 states. [2019-12-07 17:44:54,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52700 states to 52700 states and 154884 transitions. [2019-12-07 17:44:54,527 INFO L78 Accepts]: Start accepts. Automaton has 52700 states and 154884 transitions. Word has length 72 [2019-12-07 17:44:54,527 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:44:54,527 INFO L462 AbstractCegarLoop]: Abstraction has 52700 states and 154884 transitions. [2019-12-07 17:44:54,527 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 17:44:54,528 INFO L276 IsEmpty]: Start isEmpty. Operand 52700 states and 154884 transitions. [2019-12-07 17:44:54,587 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:44:54,587 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:44:54,587 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:44:54,587 INFO L410 AbstractCegarLoop]: === Iteration 65 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:44:54,588 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:44:54,588 INFO L82 PathProgramCache]: Analyzing trace with hash 655404031, now seen corresponding path program 58 times [2019-12-07 17:44:54,588 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:44:54,588 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1780643607] [2019-12-07 17:44:54,588 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:44:54,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:44:54,803 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:44:54,803 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1780643607] [2019-12-07 17:44:54,803 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:44:54,803 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 17:44:54,803 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [827425792] [2019-12-07 17:44:54,803 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 17:44:54,803 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:44:54,804 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 17:44:54,804 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2019-12-07 17:44:54,804 INFO L87 Difference]: Start difference. First operand 52700 states and 154884 transitions. Second operand 16 states. [2019-12-07 17:44:56,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:44:56,215 INFO L93 Difference]: Finished difference Result 61781 states and 181502 transitions. [2019-12-07 17:44:56,215 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 17:44:56,215 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2019-12-07 17:44:56,215 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:44:56,288 INFO L225 Difference]: With dead ends: 61781 [2019-12-07 17:44:56,288 INFO L226 Difference]: Without dead ends: 58449 [2019-12-07 17:44:56,288 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 117 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=124, Invalid=746, Unknown=0, NotChecked=0, Total=870 [2019-12-07 17:44:56,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58449 states. [2019-12-07 17:44:56,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58449 to 52680. [2019-12-07 17:44:56,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52680 states. [2019-12-07 17:44:57,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52680 states to 52680 states and 154797 transitions. [2019-12-07 17:44:57,210 INFO L78 Accepts]: Start accepts. Automaton has 52680 states and 154797 transitions. Word has length 72 [2019-12-07 17:44:57,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:44:57,210 INFO L462 AbstractCegarLoop]: Abstraction has 52680 states and 154797 transitions. [2019-12-07 17:44:57,211 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 17:44:57,211 INFO L276 IsEmpty]: Start isEmpty. Operand 52680 states and 154797 transitions. [2019-12-07 17:44:57,265 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:44:57,265 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:44:57,265 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:44:57,265 INFO L410 AbstractCegarLoop]: === Iteration 66 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:44:57,265 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:44:57,266 INFO L82 PathProgramCache]: Analyzing trace with hash 1231833331, now seen corresponding path program 59 times [2019-12-07 17:44:57,266 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:44:57,266 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [892779074] [2019-12-07 17:44:57,266 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:44:57,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:44:57,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:44:57,825 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [892779074] [2019-12-07 17:44:57,825 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:44:57,826 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2019-12-07 17:44:57,826 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386366458] [2019-12-07 17:44:57,826 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-12-07 17:44:57,826 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:44:57,826 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 17:44:57,826 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=334, Unknown=0, NotChecked=0, Total=380 [2019-12-07 17:44:57,826 INFO L87 Difference]: Start difference. First operand 52680 states and 154797 transitions. Second operand 20 states. [2019-12-07 17:45:02,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:45:02,592 INFO L93 Difference]: Finished difference Result 65879 states and 193192 transitions. [2019-12-07 17:45:02,593 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-12-07 17:45:02,593 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 72 [2019-12-07 17:45:02,593 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:45:02,687 INFO L225 Difference]: With dead ends: 65879 [2019-12-07 17:45:02,687 INFO L226 Difference]: Without dead ends: 60304 [2019-12-07 17:45:02,687 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 427 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=284, Invalid=1972, Unknown=0, NotChecked=0, Total=2256 [2019-12-07 17:45:02,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60304 states. [2019-12-07 17:45:03,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60304 to 53561. [2019-12-07 17:45:03,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53561 states. [2019-12-07 17:45:03,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53561 states to 53561 states and 157185 transitions. [2019-12-07 17:45:03,547 INFO L78 Accepts]: Start accepts. Automaton has 53561 states and 157185 transitions. Word has length 72 [2019-12-07 17:45:03,547 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:45:03,547 INFO L462 AbstractCegarLoop]: Abstraction has 53561 states and 157185 transitions. [2019-12-07 17:45:03,547 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-12-07 17:45:03,547 INFO L276 IsEmpty]: Start isEmpty. Operand 53561 states and 157185 transitions. [2019-12-07 17:45:03,608 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:45:03,608 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:45:03,608 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:45:03,608 INFO L410 AbstractCegarLoop]: === Iteration 67 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:45:03,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:45:03,608 INFO L82 PathProgramCache]: Analyzing trace with hash 564039065, now seen corresponding path program 60 times [2019-12-07 17:45:03,608 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:45:03,609 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082795300] [2019-12-07 17:45:03,609 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:45:03,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:45:03,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:45:03,980 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2082795300] [2019-12-07 17:45:03,981 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:45:03,981 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2019-12-07 17:45:03,981 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [925569738] [2019-12-07 17:45:03,981 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 17:45:03,981 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:45:03,981 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 17:45:03,981 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=373, Unknown=0, NotChecked=0, Total=420 [2019-12-07 17:45:03,981 INFO L87 Difference]: Start difference. First operand 53561 states and 157185 transitions. Second operand 21 states. [2019-12-07 17:45:06,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:45:06,953 INFO L93 Difference]: Finished difference Result 57194 states and 166773 transitions. [2019-12-07 17:45:06,953 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2019-12-07 17:45:06,953 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 72 [2019-12-07 17:45:06,953 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:45:07,028 INFO L225 Difference]: With dead ends: 57194 [2019-12-07 17:45:07,028 INFO L226 Difference]: Without dead ends: 57144 [2019-12-07 17:45:07,028 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 610 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=327, Invalid=2753, Unknown=0, NotChecked=0, Total=3080 [2019-12-07 17:45:07,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57144 states. [2019-12-07 17:45:07,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57144 to 54097. [2019-12-07 17:45:07,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54097 states. [2019-12-07 17:45:07,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54097 states to 54097 states and 158662 transitions. [2019-12-07 17:45:07,859 INFO L78 Accepts]: Start accepts. Automaton has 54097 states and 158662 transitions. Word has length 72 [2019-12-07 17:45:07,859 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:45:07,859 INFO L462 AbstractCegarLoop]: Abstraction has 54097 states and 158662 transitions. [2019-12-07 17:45:07,859 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 17:45:07,859 INFO L276 IsEmpty]: Start isEmpty. Operand 54097 states and 158662 transitions. [2019-12-07 17:45:07,920 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:45:07,920 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:45:07,920 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:45:07,920 INFO L410 AbstractCegarLoop]: === Iteration 68 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:45:07,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:45:07,921 INFO L82 PathProgramCache]: Analyzing trace with hash 593122915, now seen corresponding path program 61 times [2019-12-07 17:45:07,921 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:45:07,921 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733476232] [2019-12-07 17:45:07,921 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:45:07,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:45:08,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:45:08,484 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1733476232] [2019-12-07 17:45:08,484 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:45:08,484 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2019-12-07 17:45:08,484 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [419683227] [2019-12-07 17:45:08,484 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-12-07 17:45:08,485 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:45:08,485 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 17:45:08,485 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=540, Unknown=0, NotChecked=0, Total=600 [2019-12-07 17:45:08,485 INFO L87 Difference]: Start difference. First operand 54097 states and 158662 transitions. Second operand 25 states. [2019-12-07 17:45:13,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:45:13,803 INFO L93 Difference]: Finished difference Result 78431 states and 228402 transitions. [2019-12-07 17:45:13,803 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2019-12-07 17:45:13,803 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 72 [2019-12-07 17:45:13,804 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:45:13,903 INFO L225 Difference]: With dead ends: 78431 [2019-12-07 17:45:13,903 INFO L226 Difference]: Without dead ends: 73415 [2019-12-07 17:45:13,904 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 71 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1153 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=501, Invalid=4055, Unknown=0, NotChecked=0, Total=4556 [2019-12-07 17:45:14,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73415 states. [2019-12-07 17:45:14,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73415 to 55136. [2019-12-07 17:45:14,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55136 states. [2019-12-07 17:45:14,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55136 states to 55136 states and 161828 transitions. [2019-12-07 17:45:14,904 INFO L78 Accepts]: Start accepts. Automaton has 55136 states and 161828 transitions. Word has length 72 [2019-12-07 17:45:14,904 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:45:14,904 INFO L462 AbstractCegarLoop]: Abstraction has 55136 states and 161828 transitions. [2019-12-07 17:45:14,904 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-12-07 17:45:14,904 INFO L276 IsEmpty]: Start isEmpty. Operand 55136 states and 161828 transitions. [2019-12-07 17:45:14,966 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:45:14,967 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:45:14,967 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:45:14,967 INFO L410 AbstractCegarLoop]: === Iteration 69 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:45:14,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:45:14,967 INFO L82 PathProgramCache]: Analyzing trace with hash -313579685, now seen corresponding path program 62 times [2019-12-07 17:45:14,967 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:45:14,967 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [229745203] [2019-12-07 17:45:14,967 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:45:14,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:45:15,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:45:15,253 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [229745203] [2019-12-07 17:45:15,254 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:45:15,254 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 17:45:15,254 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [351974868] [2019-12-07 17:45:15,254 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 17:45:15,254 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:45:15,254 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 17:45:15,254 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=235, Unknown=0, NotChecked=0, Total=272 [2019-12-07 17:45:15,254 INFO L87 Difference]: Start difference. First operand 55136 states and 161828 transitions. Second operand 17 states. [2019-12-07 17:45:17,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:45:17,742 INFO L93 Difference]: Finished difference Result 62483 states and 180295 transitions. [2019-12-07 17:45:17,743 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-12-07 17:45:17,743 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 72 [2019-12-07 17:45:17,743 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:45:17,826 INFO L225 Difference]: With dead ends: 62483 [2019-12-07 17:45:17,826 INFO L226 Difference]: Without dead ends: 58802 [2019-12-07 17:45:17,826 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 345 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=238, Invalid=1568, Unknown=0, NotChecked=0, Total=1806 [2019-12-07 17:45:17,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58802 states. [2019-12-07 17:45:18,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58802 to 51078. [2019-12-07 17:45:18,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51078 states. [2019-12-07 17:45:18,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51078 states to 51078 states and 150146 transitions. [2019-12-07 17:45:18,658 INFO L78 Accepts]: Start accepts. Automaton has 51078 states and 150146 transitions. Word has length 72 [2019-12-07 17:45:18,658 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:45:18,658 INFO L462 AbstractCegarLoop]: Abstraction has 51078 states and 150146 transitions. [2019-12-07 17:45:18,658 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 17:45:18,658 INFO L276 IsEmpty]: Start isEmpty. Operand 51078 states and 150146 transitions. [2019-12-07 17:45:18,716 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:45:18,716 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:45:18,716 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:45:18,716 INFO L410 AbstractCegarLoop]: === Iteration 70 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:45:18,716 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:45:18,716 INFO L82 PathProgramCache]: Analyzing trace with hash -1297925903, now seen corresponding path program 63 times [2019-12-07 17:45:18,717 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:45:18,717 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1600069389] [2019-12-07 17:45:18,717 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:45:18,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:45:19,255 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:45:19,255 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1600069389] [2019-12-07 17:45:19,255 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:45:19,255 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 17:45:19,255 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [601605556] [2019-12-07 17:45:19,256 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 17:45:19,256 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:45:19,256 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 17:45:19,256 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=492, Unknown=0, NotChecked=0, Total=552 [2019-12-07 17:45:19,256 INFO L87 Difference]: Start difference. First operand 51078 states and 150146 transitions. Second operand 24 states. [2019-12-07 17:45:23,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:45:23,062 INFO L93 Difference]: Finished difference Result 73598 states and 215297 transitions. [2019-12-07 17:45:23,062 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2019-12-07 17:45:23,062 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 17:45:23,062 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:45:23,150 INFO L225 Difference]: With dead ends: 73598 [2019-12-07 17:45:23,150 INFO L226 Difference]: Without dead ends: 68090 [2019-12-07 17:45:23,150 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 517 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=269, Invalid=2181, Unknown=0, NotChecked=0, Total=2450 [2019-12-07 17:45:23,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68090 states. [2019-12-07 17:45:23,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68090 to 50151. [2019-12-07 17:45:23,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50151 states. [2019-12-07 17:45:24,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50151 states to 50151 states and 146838 transitions. [2019-12-07 17:45:24,014 INFO L78 Accepts]: Start accepts. Automaton has 50151 states and 146838 transitions. Word has length 72 [2019-12-07 17:45:24,015 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:45:24,015 INFO L462 AbstractCegarLoop]: Abstraction has 50151 states and 146838 transitions. [2019-12-07 17:45:24,015 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 17:45:24,015 INFO L276 IsEmpty]: Start isEmpty. Operand 50151 states and 146838 transitions. [2019-12-07 17:45:24,071 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:45:24,071 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:45:24,072 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:45:24,072 INFO L410 AbstractCegarLoop]: === Iteration 71 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:45:24,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:45:24,072 INFO L82 PathProgramCache]: Analyzing trace with hash 867471333, now seen corresponding path program 64 times [2019-12-07 17:45:24,072 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:45:24,072 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [872230548] [2019-12-07 17:45:24,072 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:45:24,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:45:24,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:45:24,848 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [872230548] [2019-12-07 17:45:24,848 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:45:24,848 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2019-12-07 17:45:24,848 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2037952964] [2019-12-07 17:45:24,848 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-12-07 17:45:24,848 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:45:24,848 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 17:45:24,848 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=540, Unknown=0, NotChecked=0, Total=600 [2019-12-07 17:45:24,848 INFO L87 Difference]: Start difference. First operand 50151 states and 146838 transitions. Second operand 25 states. [2019-12-07 17:45:29,339 WARN L192 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 26 DAG size of output: 25 [2019-12-07 17:45:30,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:45:30,499 INFO L93 Difference]: Finished difference Result 73751 states and 212748 transitions. [2019-12-07 17:45:30,499 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2019-12-07 17:45:30,499 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 72 [2019-12-07 17:45:30,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:45:30,586 INFO L225 Difference]: With dead ends: 73751 [2019-12-07 17:45:30,586 INFO L226 Difference]: Without dead ends: 68524 [2019-12-07 17:45:30,586 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 620 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=311, Invalid=2769, Unknown=0, NotChecked=0, Total=3080 [2019-12-07 17:45:30,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68524 states. [2019-12-07 17:45:31,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68524 to 50657. [2019-12-07 17:45:31,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50657 states. [2019-12-07 17:45:31,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50657 states to 50657 states and 148275 transitions. [2019-12-07 17:45:31,473 INFO L78 Accepts]: Start accepts. Automaton has 50657 states and 148275 transitions. Word has length 72 [2019-12-07 17:45:31,473 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:45:31,473 INFO L462 AbstractCegarLoop]: Abstraction has 50657 states and 148275 transitions. [2019-12-07 17:45:31,473 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-12-07 17:45:31,473 INFO L276 IsEmpty]: Start isEmpty. Operand 50657 states and 148275 transitions. [2019-12-07 17:45:31,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:45:31,531 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:45:31,531 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:45:31,531 INFO L410 AbstractCegarLoop]: === Iteration 72 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:45:31,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:45:31,531 INFO L82 PathProgramCache]: Analyzing trace with hash -1691712103, now seen corresponding path program 65 times [2019-12-07 17:45:31,532 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:45:31,532 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [833951662] [2019-12-07 17:45:31,532 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:45:31,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:45:31,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:45:31,932 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [833951662] [2019-12-07 17:45:31,932 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:45:31,932 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 17:45:31,932 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1033915291] [2019-12-07 17:45:31,932 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 17:45:31,932 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:45:31,932 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 17:45:31,932 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=266, Unknown=0, NotChecked=0, Total=306 [2019-12-07 17:45:31,933 INFO L87 Difference]: Start difference. First operand 50657 states and 148275 transitions. Second operand 18 states. [2019-12-07 17:45:37,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:45:37,871 INFO L93 Difference]: Finished difference Result 58540 states and 170568 transitions. [2019-12-07 17:45:37,871 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2019-12-07 17:45:37,871 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 72 [2019-12-07 17:45:37,871 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:45:37,939 INFO L225 Difference]: With dead ends: 58540 [2019-12-07 17:45:37,939 INFO L226 Difference]: Without dead ends: 55380 [2019-12-07 17:45:37,940 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 475 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=295, Invalid=2057, Unknown=0, NotChecked=0, Total=2352 [2019-12-07 17:45:38,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55380 states. [2019-12-07 17:45:38,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55380 to 50673. [2019-12-07 17:45:38,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50673 states. [2019-12-07 17:45:38,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50673 states to 50673 states and 148304 transitions. [2019-12-07 17:45:38,708 INFO L78 Accepts]: Start accepts. Automaton has 50673 states and 148304 transitions. Word has length 72 [2019-12-07 17:45:38,708 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:45:38,708 INFO L462 AbstractCegarLoop]: Abstraction has 50673 states and 148304 transitions. [2019-12-07 17:45:38,708 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 17:45:38,708 INFO L276 IsEmpty]: Start isEmpty. Operand 50673 states and 148304 transitions. [2019-12-07 17:45:38,766 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:45:38,766 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:45:38,766 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:45:38,766 INFO L410 AbstractCegarLoop]: === Iteration 73 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:45:38,766 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:45:38,767 INFO L82 PathProgramCache]: Analyzing trace with hash -963955527, now seen corresponding path program 66 times [2019-12-07 17:45:38,767 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:45:38,767 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1663283381] [2019-12-07 17:45:38,767 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:45:38,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:45:39,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:45:39,906 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1663283381] [2019-12-07 17:45:39,906 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:45:39,906 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [27] imperfect sequences [] total 27 [2019-12-07 17:45:39,906 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [885099569] [2019-12-07 17:45:39,906 INFO L442 AbstractCegarLoop]: Interpolant automaton has 29 states [2019-12-07 17:45:39,906 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:45:39,906 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2019-12-07 17:45:39,907 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=737, Unknown=0, NotChecked=0, Total=812 [2019-12-07 17:45:39,907 INFO L87 Difference]: Start difference. First operand 50673 states and 148304 transitions. Second operand 29 states. [2019-12-07 17:45:45,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:45:45,160 INFO L93 Difference]: Finished difference Result 59051 states and 172159 transitions. [2019-12-07 17:45:45,160 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2019-12-07 17:45:45,161 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 72 [2019-12-07 17:45:45,161 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:45:45,233 INFO L225 Difference]: With dead ends: 59051 [2019-12-07 17:45:45,233 INFO L226 Difference]: Without dead ends: 56483 [2019-12-07 17:45:45,233 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 921 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=469, Invalid=3821, Unknown=0, NotChecked=0, Total=4290 [2019-12-07 17:45:45,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56483 states. [2019-12-07 17:45:45,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56483 to 51570. [2019-12-07 17:45:45,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51570 states. [2019-12-07 17:45:46,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51570 states to 51570 states and 150894 transitions. [2019-12-07 17:45:46,029 INFO L78 Accepts]: Start accepts. Automaton has 51570 states and 150894 transitions. Word has length 72 [2019-12-07 17:45:46,029 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:45:46,029 INFO L462 AbstractCegarLoop]: Abstraction has 51570 states and 150894 transitions. [2019-12-07 17:45:46,029 INFO L463 AbstractCegarLoop]: Interpolant automaton has 29 states. [2019-12-07 17:45:46,029 INFO L276 IsEmpty]: Start isEmpty. Operand 51570 states and 150894 transitions. [2019-12-07 17:45:46,087 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:45:46,087 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:45:46,087 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:45:46,087 INFO L410 AbstractCegarLoop]: === Iteration 74 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:45:46,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:45:46,088 INFO L82 PathProgramCache]: Analyzing trace with hash -1546179521, now seen corresponding path program 67 times [2019-12-07 17:45:46,088 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:45:46,088 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887184563] [2019-12-07 17:45:46,088 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:45:46,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:45:46,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:45:46,276 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1887184563] [2019-12-07 17:45:46,276 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:45:46,276 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 17:45:46,276 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2046087123] [2019-12-07 17:45:46,276 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 17:45:46,276 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:45:46,276 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 17:45:46,276 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=154, Unknown=0, NotChecked=0, Total=182 [2019-12-07 17:45:46,277 INFO L87 Difference]: Start difference. First operand 51570 states and 150894 transitions. Second operand 14 states. [2019-12-07 17:45:49,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:45:49,751 INFO L93 Difference]: Finished difference Result 58091 states and 168747 transitions. [2019-12-07 17:45:49,752 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 17:45:49,752 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 72 [2019-12-07 17:45:49,752 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:45:49,833 INFO L225 Difference]: With dead ends: 58091 [2019-12-07 17:45:49,833 INFO L226 Difference]: Without dead ends: 55716 [2019-12-07 17:45:49,833 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 138 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=154, Invalid=776, Unknown=0, NotChecked=0, Total=930 [2019-12-07 17:45:49,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55716 states. [2019-12-07 17:45:50,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55716 to 50563. [2019-12-07 17:45:50,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50563 states. [2019-12-07 17:45:50,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50563 states to 50563 states and 148125 transitions. [2019-12-07 17:45:50,665 INFO L78 Accepts]: Start accepts. Automaton has 50563 states and 148125 transitions. Word has length 72 [2019-12-07 17:45:50,665 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:45:50,665 INFO L462 AbstractCegarLoop]: Abstraction has 50563 states and 148125 transitions. [2019-12-07 17:45:50,665 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 17:45:50,665 INFO L276 IsEmpty]: Start isEmpty. Operand 50563 states and 148125 transitions. [2019-12-07 17:45:50,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:45:50,724 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:45:50,725 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:45:50,725 INFO L410 AbstractCegarLoop]: === Iteration 75 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:45:50,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:45:50,725 INFO L82 PathProgramCache]: Analyzing trace with hash 664104829, now seen corresponding path program 68 times [2019-12-07 17:45:50,725 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:45:50,725 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1132808372] [2019-12-07 17:45:50,725 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:45:50,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:45:51,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:45:51,313 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1132808372] [2019-12-07 17:45:51,313 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:45:51,313 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2019-12-07 17:45:51,313 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1131454738] [2019-12-07 17:45:51,313 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-12-07 17:45:51,314 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:45:51,314 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 17:45:51,314 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=539, Unknown=0, NotChecked=0, Total=600 [2019-12-07 17:45:51,314 INFO L87 Difference]: Start difference. First operand 50563 states and 148125 transitions. Second operand 25 states. [2019-12-07 17:45:54,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:45:54,476 INFO L93 Difference]: Finished difference Result 62121 states and 181999 transitions. [2019-12-07 17:45:54,476 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2019-12-07 17:45:54,476 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 72 [2019-12-07 17:45:54,476 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:45:54,553 INFO L225 Difference]: With dead ends: 62121 [2019-12-07 17:45:54,553 INFO L226 Difference]: Without dead ends: 60220 [2019-12-07 17:45:54,554 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 717 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=333, Invalid=2859, Unknown=0, NotChecked=0, Total=3192 [2019-12-07 17:45:54,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60220 states. [2019-12-07 17:45:55,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60220 to 51022. [2019-12-07 17:45:55,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51022 states. [2019-12-07 17:45:55,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51022 states to 51022 states and 149517 transitions. [2019-12-07 17:45:55,400 INFO L78 Accepts]: Start accepts. Automaton has 51022 states and 149517 transitions. Word has length 72 [2019-12-07 17:45:55,401 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:45:55,401 INFO L462 AbstractCegarLoop]: Abstraction has 51022 states and 149517 transitions. [2019-12-07 17:45:55,401 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-12-07 17:45:55,401 INFO L276 IsEmpty]: Start isEmpty. Operand 51022 states and 149517 transitions. [2019-12-07 17:45:55,458 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:45:55,458 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:45:55,459 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:45:55,459 INFO L410 AbstractCegarLoop]: === Iteration 76 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:45:55,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:45:55,459 INFO L82 PathProgramCache]: Analyzing trace with hash -1895078607, now seen corresponding path program 69 times [2019-12-07 17:45:55,459 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:45:55,459 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [384718212] [2019-12-07 17:45:55,459 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:45:55,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:45:56,078 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:45:56,078 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [384718212] [2019-12-07 17:45:56,078 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:45:56,078 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [24] imperfect sequences [] total 24 [2019-12-07 17:45:56,078 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1184386891] [2019-12-07 17:45:56,078 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-12-07 17:45:56,078 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:45:56,079 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-12-07 17:45:56,079 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=582, Unknown=0, NotChecked=0, Total=650 [2019-12-07 17:45:56,079 INFO L87 Difference]: Start difference. First operand 51022 states and 149517 transitions. Second operand 26 states. [2019-12-07 17:45:59,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:45:59,410 INFO L93 Difference]: Finished difference Result 61447 states and 180368 transitions. [2019-12-07 17:45:59,410 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2019-12-07 17:45:59,410 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 72 [2019-12-07 17:45:59,410 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:45:59,481 INFO L225 Difference]: With dead ends: 61447 [2019-12-07 17:45:59,481 INFO L226 Difference]: Without dead ends: 54418 [2019-12-07 17:45:59,482 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 638 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=337, Invalid=2633, Unknown=0, NotChecked=0, Total=2970 [2019-12-07 17:45:59,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54418 states. [2019-12-07 17:46:00,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54418 to 50861. [2019-12-07 17:46:00,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50861 states. [2019-12-07 17:46:00,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50861 states to 50861 states and 148966 transitions. [2019-12-07 17:46:00,330 INFO L78 Accepts]: Start accepts. Automaton has 50861 states and 148966 transitions. Word has length 72 [2019-12-07 17:46:00,330 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:46:00,330 INFO L462 AbstractCegarLoop]: Abstraction has 50861 states and 148966 transitions. [2019-12-07 17:46:00,330 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-12-07 17:46:00,330 INFO L276 IsEmpty]: Start isEmpty. Operand 50861 states and 148966 transitions. [2019-12-07 17:46:00,388 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:46:00,388 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:46:00,388 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:46:00,389 INFO L410 AbstractCegarLoop]: === Iteration 77 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:46:00,389 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:46:00,389 INFO L82 PathProgramCache]: Analyzing trace with hash -2008403393, now seen corresponding path program 70 times [2019-12-07 17:46:00,389 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:46:00,389 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305606024] [2019-12-07 17:46:00,390 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:46:00,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:46:00,633 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:46:00,633 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1305606024] [2019-12-07 17:46:00,633 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:46:00,634 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 17:46:00,634 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [264478581] [2019-12-07 17:46:00,634 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 17:46:00,634 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:46:00,634 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 17:46:00,634 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2019-12-07 17:46:00,634 INFO L87 Difference]: Start difference. First operand 50861 states and 148966 transitions. Second operand 16 states. [2019-12-07 17:46:03,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:46:03,260 INFO L93 Difference]: Finished difference Result 54691 states and 158803 transitions. [2019-12-07 17:46:03,260 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-12-07 17:46:03,260 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2019-12-07 17:46:03,260 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:46:03,329 INFO L225 Difference]: With dead ends: 54691 [2019-12-07 17:46:03,330 INFO L226 Difference]: Without dead ends: 54377 [2019-12-07 17:46:03,330 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 220 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=188, Invalid=1144, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 17:46:03,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54377 states. [2019-12-07 17:46:04,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54377 to 50804. [2019-12-07 17:46:04,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50804 states. [2019-12-07 17:46:04,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50804 states to 50804 states and 148786 transitions. [2019-12-07 17:46:04,113 INFO L78 Accepts]: Start accepts. Automaton has 50804 states and 148786 transitions. Word has length 72 [2019-12-07 17:46:04,113 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:46:04,113 INFO L462 AbstractCegarLoop]: Abstraction has 50804 states and 148786 transitions. [2019-12-07 17:46:04,113 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 17:46:04,114 INFO L276 IsEmpty]: Start isEmpty. Operand 50804 states and 148786 transitions. [2019-12-07 17:46:04,171 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:46:04,171 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:46:04,171 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:46:04,171 INFO L410 AbstractCegarLoop]: === Iteration 78 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:46:04,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:46:04,171 INFO L82 PathProgramCache]: Analyzing trace with hash -272619533, now seen corresponding path program 71 times [2019-12-07 17:46:04,172 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:46:04,172 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345065943] [2019-12-07 17:46:04,172 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:46:04,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:46:04,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:46:04,787 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1345065943] [2019-12-07 17:46:04,787 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:46:04,787 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [24] imperfect sequences [] total 24 [2019-12-07 17:46:04,787 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1755188711] [2019-12-07 17:46:04,788 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-12-07 17:46:04,788 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:46:04,788 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-12-07 17:46:04,788 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=584, Unknown=0, NotChecked=0, Total=650 [2019-12-07 17:46:04,788 INFO L87 Difference]: Start difference. First operand 50804 states and 148786 transitions. Second operand 26 states. [2019-12-07 17:46:07,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:46:07,853 INFO L93 Difference]: Finished difference Result 59934 states and 175291 transitions. [2019-12-07 17:46:07,854 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-12-07 17:46:07,854 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 72 [2019-12-07 17:46:07,854 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:46:07,927 INFO L225 Difference]: With dead ends: 59934 [2019-12-07 17:46:07,927 INFO L226 Difference]: Without dead ends: 54046 [2019-12-07 17:46:07,927 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 644 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=331, Invalid=2639, Unknown=0, NotChecked=0, Total=2970 [2019-12-07 17:46:08,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54046 states. [2019-12-07 17:46:08,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54046 to 50737. [2019-12-07 17:46:08,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50737 states. [2019-12-07 17:46:08,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50737 states to 50737 states and 148514 transitions. [2019-12-07 17:46:08,717 INFO L78 Accepts]: Start accepts. Automaton has 50737 states and 148514 transitions. Word has length 72 [2019-12-07 17:46:08,718 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:46:08,718 INFO L462 AbstractCegarLoop]: Abstraction has 50737 states and 148514 transitions. [2019-12-07 17:46:08,718 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-12-07 17:46:08,718 INFO L276 IsEmpty]: Start isEmpty. Operand 50737 states and 148514 transitions. [2019-12-07 17:46:08,775 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:46:08,775 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:46:08,775 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:46:08,776 INFO L410 AbstractCegarLoop]: === Iteration 79 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:46:08,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:46:08,776 INFO L82 PathProgramCache]: Analyzing trace with hash 958868615, now seen corresponding path program 72 times [2019-12-07 17:46:08,776 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:46:08,776 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574294324] [2019-12-07 17:46:08,776 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:46:08,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:46:09,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:46:09,258 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [574294324] [2019-12-07 17:46:09,258 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:46:09,258 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2019-12-07 17:46:09,258 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2045714202] [2019-12-07 17:46:09,258 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 17:46:09,258 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:46:09,258 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 17:46:09,258 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=298, Unknown=0, NotChecked=0, Total=342 [2019-12-07 17:46:09,259 INFO L87 Difference]: Start difference. First operand 50737 states and 148514 transitions. Second operand 19 states. [2019-12-07 17:46:13,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:46:13,898 INFO L93 Difference]: Finished difference Result 54679 states and 158619 transitions. [2019-12-07 17:46:13,899 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2019-12-07 17:46:13,899 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 72 [2019-12-07 17:46:13,900 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:46:13,969 INFO L225 Difference]: With dead ends: 54679 [2019-12-07 17:46:13,969 INFO L226 Difference]: Without dead ends: 54180 [2019-12-07 17:46:13,970 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 394 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=279, Invalid=1791, Unknown=0, NotChecked=0, Total=2070 [2019-12-07 17:46:14,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54180 states. [2019-12-07 17:46:14,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54180 to 50361. [2019-12-07 17:46:14,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50361 states. [2019-12-07 17:46:14,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50361 states to 50361 states and 147400 transitions. [2019-12-07 17:46:14,742 INFO L78 Accepts]: Start accepts. Automaton has 50361 states and 147400 transitions. Word has length 72 [2019-12-07 17:46:14,742 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:46:14,742 INFO L462 AbstractCegarLoop]: Abstraction has 50361 states and 147400 transitions. [2019-12-07 17:46:14,742 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 17:46:14,743 INFO L276 IsEmpty]: Start isEmpty. Operand 50361 states and 147400 transitions. [2019-12-07 17:46:14,800 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:46:14,800 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:46:14,800 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:46:14,800 INFO L410 AbstractCegarLoop]: === Iteration 80 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:46:14,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:46:14,801 INFO L82 PathProgramCache]: Analyzing trace with hash 1732953689, now seen corresponding path program 73 times [2019-12-07 17:46:14,801 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:46:14,801 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1003577193] [2019-12-07 17:46:14,801 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:46:14,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:46:15,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:46:15,265 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1003577193] [2019-12-07 17:46:15,265 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:46:15,265 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2019-12-07 17:46:15,266 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [86287720] [2019-12-07 17:46:15,266 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 17:46:15,266 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:46:15,266 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 17:46:15,266 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=494, Unknown=0, NotChecked=0, Total=552 [2019-12-07 17:46:15,266 INFO L87 Difference]: Start difference. First operand 50361 states and 147400 transitions. Second operand 24 states. [2019-12-07 17:46:19,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:46:19,086 INFO L93 Difference]: Finished difference Result 63776 states and 183274 transitions. [2019-12-07 17:46:19,086 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2019-12-07 17:46:19,086 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 72 [2019-12-07 17:46:19,086 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:46:19,167 INFO L225 Difference]: With dead ends: 63776 [2019-12-07 17:46:19,167 INFO L226 Difference]: Without dead ends: 63536 [2019-12-07 17:46:19,167 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 65 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1003 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=334, Invalid=3448, Unknown=0, NotChecked=0, Total=3782 [2019-12-07 17:46:19,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63536 states. [2019-12-07 17:46:19,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63536 to 50412. [2019-12-07 17:46:19,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50412 states. [2019-12-07 17:46:20,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50412 states to 50412 states and 147498 transitions. [2019-12-07 17:46:20,039 INFO L78 Accepts]: Start accepts. Automaton has 50412 states and 147498 transitions. Word has length 72 [2019-12-07 17:46:20,039 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:46:20,039 INFO L462 AbstractCegarLoop]: Abstraction has 50412 states and 147498 transitions. [2019-12-07 17:46:20,039 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 17:46:20,039 INFO L276 IsEmpty]: Start isEmpty. Operand 50412 states and 147498 transitions. [2019-12-07 17:46:20,097 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:46:20,097 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:46:20,097 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:46:20,097 INFO L410 AbstractCegarLoop]: === Iteration 81 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:46:20,097 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:46:20,097 INFO L82 PathProgramCache]: Analyzing trace with hash 2090271203, now seen corresponding path program 74 times [2019-12-07 17:46:20,097 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:46:20,098 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [608776156] [2019-12-07 17:46:20,098 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:46:20,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:46:20,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:46:20,456 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [608776156] [2019-12-07 17:46:20,456 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:46:20,456 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2019-12-07 17:46:20,456 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [998589350] [2019-12-07 17:46:20,456 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-12-07 17:46:20,456 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:46:20,456 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 17:46:20,457 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=331, Unknown=0, NotChecked=0, Total=380 [2019-12-07 17:46:20,457 INFO L87 Difference]: Start difference. First operand 50412 states and 147498 transitions. Second operand 20 states. [2019-12-07 17:46:21,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:46:21,906 INFO L93 Difference]: Finished difference Result 69821 states and 203785 transitions. [2019-12-07 17:46:21,906 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2019-12-07 17:46:21,906 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 72 [2019-12-07 17:46:21,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:46:21,990 INFO L225 Difference]: With dead ends: 69821 [2019-12-07 17:46:21,990 INFO L226 Difference]: Without dead ends: 65732 [2019-12-07 17:46:21,990 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 359 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=216, Invalid=1590, Unknown=0, NotChecked=0, Total=1806 [2019-12-07 17:46:22,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65732 states. [2019-12-07 17:46:22,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65732 to 50834. [2019-12-07 17:46:22,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50834 states. [2019-12-07 17:46:22,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50834 states to 50834 states and 148355 transitions. [2019-12-07 17:46:22,937 INFO L78 Accepts]: Start accepts. Automaton has 50834 states and 148355 transitions. Word has length 72 [2019-12-07 17:46:22,937 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:46:22,937 INFO L462 AbstractCegarLoop]: Abstraction has 50834 states and 148355 transitions. [2019-12-07 17:46:22,937 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-12-07 17:46:22,938 INFO L276 IsEmpty]: Start isEmpty. Operand 50834 states and 148355 transitions. [2019-12-07 17:46:22,993 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:46:22,994 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:46:22,994 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:46:22,994 INFO L410 AbstractCegarLoop]: === Iteration 82 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:46:22,994 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:46:22,994 INFO L82 PathProgramCache]: Analyzing trace with hash 858472753, now seen corresponding path program 75 times [2019-12-07 17:46:22,995 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:46:22,995 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498300559] [2019-12-07 17:46:22,995 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:46:23,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:46:23,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:46:23,468 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [498300559] [2019-12-07 17:46:23,469 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:46:23,469 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2019-12-07 17:46:23,469 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1215871345] [2019-12-07 17:46:23,469 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-12-07 17:46:23,469 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:46:23,469 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 17:46:23,469 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=537, Unknown=0, NotChecked=0, Total=600 [2019-12-07 17:46:23,469 INFO L87 Difference]: Start difference. First operand 50834 states and 148355 transitions. Second operand 25 states. [2019-12-07 17:46:26,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:46:26,250 INFO L93 Difference]: Finished difference Result 65915 states and 189732 transitions. [2019-12-07 17:46:26,250 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2019-12-07 17:46:26,250 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 72 [2019-12-07 17:46:26,250 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:46:26,319 INFO L225 Difference]: With dead ends: 65915 [2019-12-07 17:46:26,320 INFO L226 Difference]: Without dead ends: 55994 [2019-12-07 17:46:26,320 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 963 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=395, Invalid=3511, Unknown=0, NotChecked=0, Total=3906 [2019-12-07 17:46:26,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55994 states. [2019-12-07 17:46:26,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55994 to 42642. [2019-12-07 17:46:26,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42642 states. [2019-12-07 17:46:27,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42642 states to 42642 states and 125420 transitions. [2019-12-07 17:46:27,025 INFO L78 Accepts]: Start accepts. Automaton has 42642 states and 125420 transitions. Word has length 72 [2019-12-07 17:46:27,025 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:46:27,025 INFO L462 AbstractCegarLoop]: Abstraction has 42642 states and 125420 transitions. [2019-12-07 17:46:27,025 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-12-07 17:46:27,025 INFO L276 IsEmpty]: Start isEmpty. Operand 42642 states and 125420 transitions. [2019-12-07 17:46:27,066 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:46:27,066 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:46:27,066 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:46:27,066 INFO L410 AbstractCegarLoop]: === Iteration 83 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:46:27,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:46:27,066 INFO L82 PathProgramCache]: Analyzing trace with hash -473349859, now seen corresponding path program 76 times [2019-12-07 17:46:27,067 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:46:27,067 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [64228299] [2019-12-07 17:46:27,067 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:46:27,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:46:27,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:46:27,366 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [64228299] [2019-12-07 17:46:27,366 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:46:27,366 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 17:46:27,366 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1795094051] [2019-12-07 17:46:27,366 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 17:46:27,366 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:46:27,367 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 17:46:27,367 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=266, Unknown=0, NotChecked=0, Total=306 [2019-12-07 17:46:27,367 INFO L87 Difference]: Start difference. First operand 42642 states and 125420 transitions. Second operand 18 states. [2019-12-07 17:46:31,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:46:31,073 INFO L93 Difference]: Finished difference Result 49643 states and 144795 transitions. [2019-12-07 17:46:31,074 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-12-07 17:46:31,074 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 72 [2019-12-07 17:46:31,074 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:46:31,130 INFO L225 Difference]: With dead ends: 49643 [2019-12-07 17:46:31,130 INFO L226 Difference]: Without dead ends: 46844 [2019-12-07 17:46:31,131 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 587 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=366, Invalid=2286, Unknown=0, NotChecked=0, Total=2652 [2019-12-07 17:46:31,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46844 states. [2019-12-07 17:46:31,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46844 to 42622. [2019-12-07 17:46:31,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42622 states. [2019-12-07 17:46:31,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42622 states to 42622 states and 125398 transitions. [2019-12-07 17:46:31,785 INFO L78 Accepts]: Start accepts. Automaton has 42622 states and 125398 transitions. Word has length 72 [2019-12-07 17:46:31,785 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:46:31,785 INFO L462 AbstractCegarLoop]: Abstraction has 42622 states and 125398 transitions. [2019-12-07 17:46:31,785 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 17:46:31,785 INFO L276 IsEmpty]: Start isEmpty. Operand 42622 states and 125398 transitions. [2019-12-07 17:46:31,826 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-12-07 17:46:31,826 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:46:31,826 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:46:31,826 INFO L410 AbstractCegarLoop]: === Iteration 84 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:46:31,827 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:46:31,827 INFO L82 PathProgramCache]: Analyzing trace with hash 959991305, now seen corresponding path program 77 times [2019-12-07 17:46:31,827 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:46:31,827 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [467429201] [2019-12-07 17:46:31,827 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:46:31,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:46:31,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:46:31,936 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:46:31,936 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 17:46:31,938 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1160] [1160] ULTIMATE.startENTRY-->L838: Formula: (let ((.cse1 (store |v_#valid_73| 0 0))) (let ((.cse0 (store .cse1 |v_~#x~0.base_244| 1))) (and (< |v_#StackHeapBarrier_24| |v_ULTIMATE.start_main_~#t2464~0.base_22|) (= |v_#valid_71| (store .cse0 |v_ULTIMATE.start_main_~#t2464~0.base_22| 1)) (= v_~__unbuffered_cnt~0_104 0) (= 0 v_~x$r_buff0_thd3~0_278) (= 0 v_~__unbuffered_p2_EAX$r_buff0_thd1~0_8) (= v_~main$tmp_guard1~0_31 0) (= |v_#NULL.offset_6| 0) (= 0 v_~__unbuffered_p2_EAX$w_buff0~0_7) (= (select (select |v_#memory_int_395| |v_~#x~0.base_244|) |v_~#x~0.offset_244|) 0) (= v_~x$r_buff1_thd0~0_77 0) (= 0 v_~__unbuffered_p2_EAX$r_buff0_thd2~0_8) (= 0 v_~__unbuffered_p2_EAX$w_buff0_used~0_7) (= 0 v_~__unbuffered_p2_EAX$w_buff1~0_7) (= 0 v_~x$w_buff1~0_137) (= 0 |v_~#x~0.offset_244|) (= 0 v_~x$read_delayed_var~0.base_7) (= 0 v_~__unbuffered_p0_EAX~0_70) (= v_~x$r_buff1_thd2~0_55 0) (= 0 v_~__unbuffered_p2_EAX$r_buff0_thd3~0_6) (= v_~weak$$choice2~0_140 0) (= 0 v_~x$read_delayed~0_8) (= v_~x$mem_tmp~0_82 0) (= v_~__unbuffered_p2_EBX~0_33 0) (= 0 v_~x$r_buff0_thd0~0_89) (= 0 v_~x$w_buff1_used~0_483) (= 0 v_~__unbuffered_p2_EAX$mem_tmp~0_8) (= v_~main$tmp_guard0~0_33 0) (= 0 v_~x$w_buff0~0_164) (= 0 v_~x$r_buff1_thd3~0_181) (= v_~y~0_51 0) (= 0 v_~x$read_delayed_var~0.offset_7) (< |v_#StackHeapBarrier_24| |v_~#x~0.base_244|) (= 0 v_~x$w_buff0_used~0_778) (= v_~x$r_buff0_thd1~0_285 0) (= 0 v_~__unbuffered_p2_EAX$r_buff1_thd1~0_7) (= |v_#length_36| (store (store |v_#length_37| |v_~#x~0.base_244| 4) |v_ULTIMATE.start_main_~#t2464~0.base_22| 4)) (= (store |v_#memory_int_395| |v_ULTIMATE.start_main_~#t2464~0.base_22| (store (select |v_#memory_int_395| |v_ULTIMATE.start_main_~#t2464~0.base_22|) |v_ULTIMATE.start_main_~#t2464~0.offset_17| 0)) |v_#memory_int_394|) (< 0 |v_#StackHeapBarrier_24|) (= 0 v_~__unbuffered_p2_EAX$flush_delayed~0_7) (= 0 (select .cse1 |v_~#x~0.base_244|)) (= 0 v_~__unbuffered_p2_EAX$r_buff1_thd2~0_7) (= 0 v_~__unbuffered_p2_EAX~0_77) (= 0 v_~__unbuffered_p2_EAX$read_delayed_var~0.offset_44) (= 0 v_~__unbuffered_p2_EAX$r_buff1_thd0~0_6) (= 0 v_~__unbuffered_p2_EAX$w_buff1_used~0_7) (= 0 v_~weak$$choice0~0_74) (= 0 v_~weak$$choice1~0_28) (= v_~__unbuffered_p2_EAX$read_delayed~0_57 0) (= 0 |v_#NULL.base_6|) (= 0 v_~__unbuffered_p2_EAX$read_delayed_var~0.base_44) (= 0 v_~__unbuffered_p2_EAX$r_buff0_thd0~0_8) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t2464~0.base_22|)) (= v_~x$r_buff1_thd1~0_182 0) (= v_~x$flush_delayed~0_108 0) (= 0 |v_ULTIMATE.start_main_~#t2464~0.offset_17|) (= 0 v_~__unbuffered_p2_EAX$r_buff1_thd3~0_7) (= 0 v_~x$r_buff0_thd2~0_71)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_24|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_395|, #length=|v_#length_37|} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_164, ~x$flush_delayed~0=v_~x$flush_delayed~0_108, ~__unbuffered_p2_EAX$read_delayed_var~0.offset=v_~__unbuffered_p2_EAX$read_delayed_var~0.offset_44, ~__unbuffered_p2_EAX$read_delayed_var~0.base=v_~__unbuffered_p2_EAX$read_delayed_var~0.base_44, #NULL.offset=|v_#NULL.offset_6|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_182, ULTIMATE.start_main_~#t2464~0.base=|v_ULTIMATE.start_main_~#t2464~0.base_22|, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_278, ULTIMATE.start_main_#t~nondet72=|v_ULTIMATE.start_main_#t~nondet72_7|, ULTIMATE.start_main_~#t2466~0.offset=|v_ULTIMATE.start_main_~#t2466~0.offset_21|, ~weak$$choice1~0=v_~weak$$choice1~0_28, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_70, ~__unbuffered_p2_EAX$w_buff0_used~0=v_~__unbuffered_p2_EAX$w_buff0_used~0_7, #length=|v_#length_36|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_77, ~__unbuffered_p2_EAX$r_buff1_thd2~0=v_~__unbuffered_p2_EAX$r_buff1_thd2~0_7, ~__unbuffered_p2_EAX$r_buff0_thd0~0=v_~__unbuffered_p2_EAX$r_buff0_thd0~0_8, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_89, ~__unbuffered_p2_EAX$w_buff0~0=v_~__unbuffered_p2_EAX$w_buff0~0_7, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_33, ~#x~0.offset=|v_~#x~0.offset_244|, ~x$w_buff1~0=v_~x$w_buff1~0_137, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_483, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_55, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_21|, ULTIMATE.start_main_#t~ite77=|v_ULTIMATE.start_main_#t~ite77_115|, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_21|, ULTIMATE.start_main_#t~nondet81=|v_ULTIMATE.start_main_#t~nondet81_33|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_7, ULTIMATE.start_main_~#t2464~0.offset=|v_ULTIMATE.start_main_~#t2464~0.offset_17|, ULTIMATE.start_main_#t~ite84=|v_ULTIMATE.start_main_#t~ite84_51|, ~weak$$choice0~0=v_~weak$$choice0~0_74, #StackHeapBarrier=|v_#StackHeapBarrier_24|, ULTIMATE.start_main_#t~ite80=|v_ULTIMATE.start_main_#t~ite80_32|, ~__unbuffered_p2_EAX$r_buff0_thd1~0=v_~__unbuffered_p2_EAX$r_buff0_thd1~0_8, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_104, ULTIMATE.start_main_~#t2466~0.base=|v_ULTIMATE.start_main_~#t2466~0.base_24|, ~__unbuffered_p2_EAX$r_buff1_thd3~0=v_~__unbuffered_p2_EAX$r_buff1_thd3~0_7, ~__unbuffered_p2_EAX$w_buff1~0=v_~__unbuffered_p2_EAX$w_buff1~0_7, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_285, ULTIMATE.start_main_#t~nondet73=|v_ULTIMATE.start_main_#t~nondet73_20|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_181, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_31, ~x$mem_tmp~0=v_~x$mem_tmp~0_82, ULTIMATE.start_main_#t~nondet71=|v_ULTIMATE.start_main_#t~nondet71_8|, ULTIMATE.start_main_~#t2465~0.base=|v_ULTIMATE.start_main_~#t2465~0.base_31|, ~__unbuffered_p2_EAX$w_buff1_used~0=v_~__unbuffered_p2_EAX$w_buff1_used~0_7, ~__unbuffered_p2_EAX$r_buff0_thd2~0=v_~__unbuffered_p2_EAX$r_buff0_thd2~0_8, ~__unbuffered_p2_EAX$r_buff1_thd0~0=v_~__unbuffered_p2_EAX$r_buff1_thd0~0_6, ~y~0=v_~y~0_51, ULTIMATE.start_main_~#t2465~0.offset=|v_ULTIMATE.start_main_~#t2465~0.offset_28|, ULTIMATE.start_main_#t~mem74=|v_ULTIMATE.start_main_#t~mem74_20|, ~__unbuffered_p2_EAX$mem_tmp~0=v_~__unbuffered_p2_EAX$mem_tmp~0_8, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_33, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_77, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_71, ULTIMATE.start_main_#t~ite78=|v_ULTIMATE.start_main_#t~ite78_299|, ~__unbuffered_p2_EAX$flush_delayed~0=v_~__unbuffered_p2_EAX$flush_delayed~0_7, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_24|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_778, ~__unbuffered_p2_EAX$read_delayed~0=v_~__unbuffered_p2_EAX$read_delayed~0_57, ULTIMATE.start_main_#t~ite83=|v_ULTIMATE.start_main_#t~ite83_50|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_7, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, #valid=|v_#valid_71|, ULTIMATE.start_main_#t~mem82=|v_ULTIMATE.start_main_#t~mem82_37|, #memory_int=|v_#memory_int_394|, ~#x~0.base=|v_~#x~0.base_244|, ~__unbuffered_p2_EAX$r_buff1_thd1~0=v_~__unbuffered_p2_EAX$r_buff1_thd1~0_7, ~__unbuffered_p2_EAX$r_buff0_thd3~0=v_~__unbuffered_p2_EAX$r_buff0_thd3~0_6, ~weak$$choice2~0=v_~weak$$choice2~0_140, ~x$read_delayed~0=v_~x$read_delayed~0_8} AuxVars[] AssignedVars[~x$w_buff0~0, ~x$flush_delayed~0, ~__unbuffered_p2_EAX$read_delayed_var~0.offset, ~__unbuffered_p2_EAX$read_delayed_var~0.base, #NULL.offset, ~x$r_buff1_thd1~0, ULTIMATE.start_main_~#t2464~0.base, ~x$r_buff0_thd3~0, ULTIMATE.start_main_#t~nondet72, ULTIMATE.start_main_~#t2466~0.offset, ~weak$$choice1~0, ~__unbuffered_p0_EAX~0, ~__unbuffered_p2_EAX$w_buff0_used~0, #length, ~__unbuffered_p2_EAX~0, ~__unbuffered_p2_EAX$r_buff1_thd2~0, ~__unbuffered_p2_EAX$r_buff0_thd0~0, ~x$r_buff0_thd0~0, ~__unbuffered_p2_EAX$w_buff0~0, ~__unbuffered_p2_EBX~0, ~#x~0.offset, ~x$w_buff1~0, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite79, ULTIMATE.start_main_#t~ite77, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~nondet81, ~x$read_delayed_var~0.base, ULTIMATE.start_main_~#t2464~0.offset, ULTIMATE.start_main_#t~ite84, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite80, ~__unbuffered_p2_EAX$r_buff0_thd1~0, ~__unbuffered_cnt~0, ULTIMATE.start_main_~#t2466~0.base, ~__unbuffered_p2_EAX$r_buff1_thd3~0, ~__unbuffered_p2_EAX$w_buff1~0, ~x$r_buff0_thd1~0, ULTIMATE.start_main_#t~nondet73, ~x$r_buff1_thd3~0, ~main$tmp_guard1~0, ~x$mem_tmp~0, ULTIMATE.start_main_#t~nondet71, ULTIMATE.start_main_~#t2465~0.base, ~__unbuffered_p2_EAX$w_buff1_used~0, ~__unbuffered_p2_EAX$r_buff0_thd2~0, ~__unbuffered_p2_EAX$r_buff1_thd0~0, ~y~0, ULTIMATE.start_main_~#t2465~0.offset, ULTIMATE.start_main_#t~mem74, ~__unbuffered_p2_EAX$mem_tmp~0, ~main$tmp_guard0~0, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite78, ~__unbuffered_p2_EAX$flush_delayed~0, #NULL.base, ULTIMATE.start_main_#t~ite76, ~x$w_buff0_used~0, ~__unbuffered_p2_EAX$read_delayed~0, ULTIMATE.start_main_#t~ite83, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_#res, #valid, ULTIMATE.start_main_#t~mem82, #memory_int, ~#x~0.base, ~__unbuffered_p2_EAX$r_buff1_thd1~0, ~__unbuffered_p2_EAX$r_buff0_thd3~0, ~weak$$choice2~0, ~x$read_delayed~0] because there is no mapped edge [2019-12-07 17:46:31,939 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1126] [1126] L838-1-->L840: Formula: (and (= (store |v_#memory_int_282| |v_ULTIMATE.start_main_~#t2465~0.base_23| (store (select |v_#memory_int_282| |v_ULTIMATE.start_main_~#t2465~0.base_23|) |v_ULTIMATE.start_main_~#t2465~0.offset_22| 1)) |v_#memory_int_281|) (= |v_#valid_35| (store |v_#valid_36| |v_ULTIMATE.start_main_~#t2465~0.base_23| 1)) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t2465~0.base_23|)) (not (= |v_ULTIMATE.start_main_~#t2465~0.base_23| 0)) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t2465~0.base_23| 4)) (= 0 |v_ULTIMATE.start_main_~#t2465~0.offset_22|) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t2465~0.base_23|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_282|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_~#t2465~0.base=|v_ULTIMATE.start_main_~#t2465~0.base_23|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_281|, #length=|v_#length_21|, ULTIMATE.start_main_#t~nondet71=|v_ULTIMATE.start_main_#t~nondet71_4|, ULTIMATE.start_main_~#t2465~0.offset=|v_ULTIMATE.start_main_~#t2465~0.offset_22|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2465~0.base, #valid, #memory_int, #length, ULTIMATE.start_main_#t~nondet71, ULTIMATE.start_main_~#t2465~0.offset] because there is no mapped edge [2019-12-07 17:46:31,940 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1125] [1125] L840-1-->L842: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t2466~0.base_14|)) (= 0 |v_ULTIMATE.start_main_~#t2466~0.offset_14|) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t2466~0.base_14|) (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2466~0.base_14| 1)) (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t2466~0.base_14| 4)) (= |v_#memory_int_279| (store |v_#memory_int_280| |v_ULTIMATE.start_main_~#t2466~0.base_14| (store (select |v_#memory_int_280| |v_ULTIMATE.start_main_~#t2466~0.base_14|) |v_ULTIMATE.start_main_~#t2466~0.offset_14| 2))) (= (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2466~0.base_14|) 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_280|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_279|, #length=|v_#length_19|, ULTIMATE.start_main_~#t2466~0.base=|v_ULTIMATE.start_main_~#t2466~0.base_14|, ULTIMATE.start_main_#t~nondet72=|v_ULTIMATE.start_main_#t~nondet72_3|, ULTIMATE.start_main_~#t2466~0.offset=|v_ULTIMATE.start_main_~#t2466~0.offset_14|} AuxVars[] AssignedVars[#valid, #memory_int, #length, ULTIMATE.start_main_~#t2466~0.base, ULTIMATE.start_main_#t~nondet72, ULTIMATE.start_main_~#t2466~0.offset] because there is no mapped edge [2019-12-07 17:46:31,943 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1087] [1087] L780-2-->L780-4: Formula: (let ((.cse1 (= (mod ~x$w_buff1_used~0_In-883408411 256) 0)) (.cse0 (= 0 (mod ~x$r_buff1_thd2~0_In-883408411 256)))) (or (and (or .cse0 .cse1) (= (select (select |#memory_int_In-883408411| |~#x~0.base_In-883408411|) |~#x~0.offset_In-883408411|) |P1Thread1of1ForFork1_#t~mem30_Out-883408411|) (= |P1Thread1of1ForFork1_#t~ite31_Out-883408411| |P1Thread1of1ForFork1_#t~mem30_Out-883408411|)) (and (= |P1Thread1of1ForFork1_#t~mem30_In-883408411| |P1Thread1of1ForFork1_#t~mem30_Out-883408411|) (not .cse1) (not .cse0) (= |P1Thread1of1ForFork1_#t~ite31_Out-883408411| ~x$w_buff1~0_In-883408411)))) InVars {P1Thread1of1ForFork1_#t~mem30=|P1Thread1of1ForFork1_#t~mem30_In-883408411|, ~#x~0.offset=|~#x~0.offset_In-883408411|, ~x$w_buff1~0=~x$w_buff1~0_In-883408411, ~#x~0.base=|~#x~0.base_In-883408411|, #memory_int=|#memory_int_In-883408411|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-883408411, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-883408411} OutVars{P1Thread1of1ForFork1_#t~mem30=|P1Thread1of1ForFork1_#t~mem30_Out-883408411|, P1Thread1of1ForFork1_#t~ite31=|P1Thread1of1ForFork1_#t~ite31_Out-883408411|, ~#x~0.offset=|~#x~0.offset_In-883408411|, ~x$w_buff1~0=~x$w_buff1~0_In-883408411, ~#x~0.base=|~#x~0.base_In-883408411|, #memory_int=|#memory_int_In-883408411|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-883408411, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-883408411} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~mem30, P1Thread1of1ForFork1_#t~ite31] because there is no mapped edge [2019-12-07 17:46:31,943 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1014] [1014] L780-4-->L781: Formula: (= (store |v_#memory_int_69| |v_~#x~0.base_42| (store (select |v_#memory_int_69| |v_~#x~0.base_42|) |v_~#x~0.offset_42| |v_P1Thread1of1ForFork1_#t~ite31_6|)) |v_#memory_int_68|) InVars {~#x~0.offset=|v_~#x~0.offset_42|, P1Thread1of1ForFork1_#t~ite31=|v_P1Thread1of1ForFork1_#t~ite31_6|, #memory_int=|v_#memory_int_69|, ~#x~0.base=|v_~#x~0.base_42|} OutVars{P1Thread1of1ForFork1_#t~mem30=|v_P1Thread1of1ForFork1_#t~mem30_3|, ~#x~0.offset=|v_~#x~0.offset_42|, P1Thread1of1ForFork1_#t~ite31=|v_P1Thread1of1ForFork1_#t~ite31_5|, #memory_int=|v_#memory_int_68|, ~#x~0.base=|v_~#x~0.base_42|, P1Thread1of1ForFork1_#t~ite32=|v_P1Thread1of1ForFork1_#t~ite32_7|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~mem30, P1Thread1of1ForFork1_#t~ite31, #memory_int, P1Thread1of1ForFork1_#t~ite32] because there is no mapped edge [2019-12-07 17:46:31,943 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1084] [1084] L781-->L781-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd2~0_In241140032 256))) (.cse0 (= (mod ~x$w_buff0_used~0_In241140032 256) 0))) (or (and (= |P1Thread1of1ForFork1_#t~ite33_Out241140032| 0) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |P1Thread1of1ForFork1_#t~ite33_Out241140032| ~x$w_buff0_used~0_In241140032)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In241140032, ~x$w_buff0_used~0=~x$w_buff0_used~0_In241140032} OutVars{P1Thread1of1ForFork1_#t~ite33=|P1Thread1of1ForFork1_#t~ite33_Out241140032|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In241140032, ~x$w_buff0_used~0=~x$w_buff0_used~0_In241140032} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite33] because there is no mapped edge [2019-12-07 17:46:31,944 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1081] [1081] L782-->L782-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff1_thd2~0_In959597545 256))) (.cse0 (= (mod ~x$w_buff1_used~0_In959597545 256) 0)) (.cse2 (= (mod ~x$w_buff0_used~0_In959597545 256) 0)) (.cse3 (= (mod ~x$r_buff0_thd2~0_In959597545 256) 0))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite34_Out959597545| ~x$w_buff1_used~0_In959597545) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork1_#t~ite34_Out959597545| 0)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In959597545, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In959597545, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In959597545, ~x$w_buff0_used~0=~x$w_buff0_used~0_In959597545} OutVars{P1Thread1of1ForFork1_#t~ite34=|P1Thread1of1ForFork1_#t~ite34_Out959597545|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In959597545, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In959597545, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In959597545, ~x$w_buff0_used~0=~x$w_buff0_used~0_In959597545} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite34] because there is no mapped edge [2019-12-07 17:46:31,944 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1093] [1093] L783-->L784: Formula: (let ((.cse0 (= (mod ~x$r_buff0_thd2~0_In-220765501 256) 0)) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In-220765501 256))) (.cse2 (= ~x$r_buff0_thd2~0_Out-220765501 ~x$r_buff0_thd2~0_In-220765501))) (or (and (not .cse0) (not .cse1) (= ~x$r_buff0_thd2~0_Out-220765501 0)) (and .cse2 .cse0) (and .cse1 .cse2))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-220765501, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-220765501} OutVars{P1Thread1of1ForFork1_#t~ite35=|P1Thread1of1ForFork1_#t~ite35_Out-220765501|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out-220765501, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-220765501} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite35, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-12-07 17:46:31,945 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1097] [1097] L784-->L784-2: Formula: (let ((.cse2 (= (mod ~x$w_buff0_used~0_In-1011398210 256) 0)) (.cse3 (= 0 (mod ~x$r_buff0_thd2~0_In-1011398210 256))) (.cse1 (= (mod ~x$r_buff1_thd2~0_In-1011398210 256) 0)) (.cse0 (= (mod ~x$w_buff1_used~0_In-1011398210 256) 0))) (or (and (or .cse0 .cse1) (= ~x$r_buff1_thd2~0_In-1011398210 |P1Thread1of1ForFork1_#t~ite36_Out-1011398210|) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |P1Thread1of1ForFork1_#t~ite36_Out-1011398210|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1011398210, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1011398210, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1011398210, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1011398210} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-1011398210, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1011398210, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1011398210, P1Thread1of1ForFork1_#t~ite36=|P1Thread1of1ForFork1_#t~ite36_Out-1011398210|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1011398210} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite36] because there is no mapped edge [2019-12-07 17:46:31,948 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1032] [1032] L803-->L804: Formula: (and (= v_~x$r_buff0_thd3~0_105 v_~x$r_buff0_thd3~0_104) (not (= (mod v_~weak$$choice2~0_77 256) 0))) InVars {~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_105, ~weak$$choice2~0=v_~weak$$choice2~0_77} OutVars{P2Thread1of1ForFork2_#t~ite56=|v_P2Thread1of1ForFork2_#t~ite56_9|, P2Thread1of1ForFork2_#t~ite57=|v_P2Thread1of1ForFork2_#t~ite57_9|, P2Thread1of1ForFork2_#t~ite55=|v_P2Thread1of1ForFork2_#t~ite55_10|, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_104, ~weak$$choice2~0=v_~weak$$choice2~0_77} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite56, P2Thread1of1ForFork2_#t~ite57, P2Thread1of1ForFork2_#t~ite55, ~x$r_buff0_thd3~0] because there is no mapped edge [2019-12-07 17:46:31,949 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1083] [1083] L808-->L808-2: Formula: (let ((.cse0 (= 0 (mod ~x$flush_delayed~0_In-589175640 256)))) (or (and .cse0 (= |P2Thread1of1ForFork2_#t~mem62_Out-589175640| |P2Thread1of1ForFork2_#t~ite63_Out-589175640|) (= |P2Thread1of1ForFork2_#t~mem62_Out-589175640| (select (select |#memory_int_In-589175640| |~#x~0.base_In-589175640|) |~#x~0.offset_In-589175640|))) (and (not .cse0) (= |P2Thread1of1ForFork2_#t~mem62_In-589175640| |P2Thread1of1ForFork2_#t~mem62_Out-589175640|) (= ~x$mem_tmp~0_In-589175640 |P2Thread1of1ForFork2_#t~ite63_Out-589175640|)))) InVars {~x$flush_delayed~0=~x$flush_delayed~0_In-589175640, ~#x~0.offset=|~#x~0.offset_In-589175640|, ~#x~0.base=|~#x~0.base_In-589175640|, #memory_int=|#memory_int_In-589175640|, ~x$mem_tmp~0=~x$mem_tmp~0_In-589175640, P2Thread1of1ForFork2_#t~mem62=|P2Thread1of1ForFork2_#t~mem62_In-589175640|} OutVars{~x$flush_delayed~0=~x$flush_delayed~0_In-589175640, ~#x~0.offset=|~#x~0.offset_In-589175640|, P2Thread1of1ForFork2_#t~ite63=|P2Thread1of1ForFork2_#t~ite63_Out-589175640|, ~#x~0.base=|~#x~0.base_In-589175640|, #memory_int=|#memory_int_In-589175640|, ~x$mem_tmp~0=~x$mem_tmp~0_In-589175640, P2Thread1of1ForFork2_#t~mem62=|P2Thread1of1ForFork2_#t~mem62_Out-589175640|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite63, P2Thread1of1ForFork2_#t~mem62] because there is no mapped edge [2019-12-07 17:46:31,952 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1079] [1079] L815-2-->L815-4: Formula: (let ((.cse0 (= (mod ~x$r_buff1_thd3~0_In-1560808699 256) 0)) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In-1560808699 256)))) (or (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork2_#t~mem64_In-1560808699| |P2Thread1of1ForFork2_#t~mem64_Out-1560808699|) (= ~x$w_buff1~0_In-1560808699 |P2Thread1of1ForFork2_#t~ite65_Out-1560808699|)) (and (= |P2Thread1of1ForFork2_#t~mem64_Out-1560808699| (select (select |#memory_int_In-1560808699| |~#x~0.base_In-1560808699|) |~#x~0.offset_In-1560808699|)) (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~mem64_Out-1560808699| |P2Thread1of1ForFork2_#t~ite65_Out-1560808699|)))) InVars {~#x~0.offset=|~#x~0.offset_In-1560808699|, ~x$w_buff1~0=~x$w_buff1~0_In-1560808699, ~#x~0.base=|~#x~0.base_In-1560808699|, #memory_int=|#memory_int_In-1560808699|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1560808699, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1560808699, P2Thread1of1ForFork2_#t~mem64=|P2Thread1of1ForFork2_#t~mem64_In-1560808699|} OutVars{P2Thread1of1ForFork2_#t~ite65=|P2Thread1of1ForFork2_#t~ite65_Out-1560808699|, ~#x~0.offset=|~#x~0.offset_In-1560808699|, ~x$w_buff1~0=~x$w_buff1~0_In-1560808699, ~#x~0.base=|~#x~0.base_In-1560808699|, #memory_int=|#memory_int_In-1560808699|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1560808699, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1560808699, P2Thread1of1ForFork2_#t~mem64=|P2Thread1of1ForFork2_#t~mem64_Out-1560808699|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite65, P2Thread1of1ForFork2_#t~mem64] because there is no mapped edge [2019-12-07 17:46:31,952 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1033] [1033] L815-4-->L816: Formula: (= (store |v_#memory_int_131| |v_~#x~0.base_85| (store (select |v_#memory_int_131| |v_~#x~0.base_85|) |v_~#x~0.offset_85| |v_P2Thread1of1ForFork2_#t~ite65_10|)) |v_#memory_int_130|) InVars {P2Thread1of1ForFork2_#t~ite65=|v_P2Thread1of1ForFork2_#t~ite65_10|, ~#x~0.offset=|v_~#x~0.offset_85|, #memory_int=|v_#memory_int_131|, ~#x~0.base=|v_~#x~0.base_85|} OutVars{P2Thread1of1ForFork2_#t~ite65=|v_P2Thread1of1ForFork2_#t~ite65_9|, P2Thread1of1ForFork2_#t~ite66=|v_P2Thread1of1ForFork2_#t~ite66_5|, ~#x~0.offset=|v_~#x~0.offset_85|, #memory_int=|v_#memory_int_130|, ~#x~0.base=|v_~#x~0.base_85|, P2Thread1of1ForFork2_#t~mem64=|v_P2Thread1of1ForFork2_#t~mem64_5|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite65, P2Thread1of1ForFork2_#t~ite66, #memory_int, P2Thread1of1ForFork2_#t~mem64] because there is no mapped edge [2019-12-07 17:46:31,953 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1086] [1086] L816-->L816-2: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd3~0_In1761775048 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In1761775048 256)))) (or (and (= ~x$w_buff0_used~0_In1761775048 |P2Thread1of1ForFork2_#t~ite67_Out1761775048|) (or .cse0 .cse1)) (and (= 0 |P2Thread1of1ForFork2_#t~ite67_Out1761775048|) (not .cse1) (not .cse0)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1761775048, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1761775048} OutVars{P2Thread1of1ForFork2_#t~ite67=|P2Thread1of1ForFork2_#t~ite67_Out1761775048|, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1761775048, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1761775048} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite67] because there is no mapped edge [2019-12-07 17:46:31,953 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1095] [1095] L817-->L817-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff1_used~0_In1718553415 256))) (.cse1 (= 0 (mod ~x$r_buff1_thd3~0_In1718553415 256))) (.cse3 (= (mod ~x$w_buff0_used~0_In1718553415 256) 0)) (.cse2 (= (mod ~x$r_buff0_thd3~0_In1718553415 256) 0))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite68_Out1718553415|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse3 .cse2) (= ~x$w_buff1_used~0_In1718553415 |P2Thread1of1ForFork2_#t~ite68_Out1718553415|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In1718553415, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1718553415, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1718553415, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1718553415} OutVars{P2Thread1of1ForFork2_#t~ite68=|P2Thread1of1ForFork2_#t~ite68_Out1718553415|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1718553415, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1718553415, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1718553415, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1718553415} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite68] because there is no mapped edge [2019-12-07 17:46:31,954 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1077] [1077] L818-->L819: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In-1685145752 256) 0)) (.cse2 (= ~x$r_buff0_thd3~0_In-1685145752 ~x$r_buff0_thd3~0_Out-1685145752)) (.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In-1685145752 256)))) (or (and (not .cse0) (= 0 ~x$r_buff0_thd3~0_Out-1685145752) (not .cse1)) (and .cse1 .cse2) (and .cse2 .cse0))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1685145752, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1685145752} OutVars{P2Thread1of1ForFork2_#t~ite69=|P2Thread1of1ForFork2_#t~ite69_Out-1685145752|, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_Out-1685145752, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1685145752} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite69, ~x$r_buff0_thd3~0] because there is no mapped edge [2019-12-07 17:46:31,954 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1089] [1089] L819-->L819-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In-1018117050 256) 0)) (.cse1 (= 0 (mod ~x$r_buff0_thd3~0_In-1018117050 256))) (.cse2 (= 0 (mod ~x$w_buff1_used~0_In-1018117050 256))) (.cse3 (= 0 (mod ~x$r_buff1_thd3~0_In-1018117050 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork2_#t~ite70_Out-1018117050| 0)) (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork2_#t~ite70_Out-1018117050| ~x$r_buff1_thd3~0_In-1018117050)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1018117050, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1018117050, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1018117050, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1018117050} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-1018117050, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1018117050, P2Thread1of1ForFork2_#t~ite70=|P2Thread1of1ForFork2_#t~ite70_Out-1018117050|, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1018117050, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1018117050} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite70] because there is no mapped edge [2019-12-07 17:46:31,954 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1122] [1122] L819-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite70_34| v_~x$r_buff1_thd3~0_127) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_67 (+ v_~__unbuffered_cnt~0_68 1))) InVars {P2Thread1of1ForFork2_#t~ite70=|v_P2Thread1of1ForFork2_#t~ite70_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_68} OutVars{~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_127, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, P2Thread1of1ForFork2_#t~ite70=|v_P2Thread1of1ForFork2_#t~ite70_33|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[~x$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, P2Thread1of1ForFork2_#t~ite70, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 17:46:31,957 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1041] [1041] L761-->L762: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_97 256))) (= v_~x$r_buff0_thd1~0_107 v_~x$r_buff0_thd1~0_106)) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_107, ~weak$$choice2~0=v_~weak$$choice2~0_97} OutVars{P0Thread1of1ForFork0_#t~ite22=|v_P0Thread1of1ForFork0_#t~ite22_7|, P0Thread1of1ForFork0_#t~ite21=|v_P0Thread1of1ForFork0_#t~ite21_9|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_106, ~weak$$choice2~0=v_~weak$$choice2~0_97, P0Thread1of1ForFork0_#t~ite23=|v_P0Thread1of1ForFork0_#t~ite23_7|} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite22, P0Thread1of1ForFork0_#t~ite21, ~x$r_buff0_thd1~0, P0Thread1of1ForFork0_#t~ite23] because there is no mapped edge [2019-12-07 17:46:31,958 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1075] [1075] L764-->L764-2: Formula: (let ((.cse0 (= (mod ~x$flush_delayed~0_In68196668 256) 0))) (or (and (not .cse0) (= |P0Thread1of1ForFork0_#t~mem28_In68196668| |P0Thread1of1ForFork0_#t~mem28_Out68196668|) (= |P0Thread1of1ForFork0_#t~ite29_Out68196668| ~x$mem_tmp~0_In68196668)) (and .cse0 (= |P0Thread1of1ForFork0_#t~mem28_Out68196668| |P0Thread1of1ForFork0_#t~ite29_Out68196668|) (= |P0Thread1of1ForFork0_#t~mem28_Out68196668| (select (select |#memory_int_In68196668| |~#x~0.base_In68196668|) |~#x~0.offset_In68196668|))))) InVars {P0Thread1of1ForFork0_#t~mem28=|P0Thread1of1ForFork0_#t~mem28_In68196668|, ~x$flush_delayed~0=~x$flush_delayed~0_In68196668, ~#x~0.offset=|~#x~0.offset_In68196668|, ~#x~0.base=|~#x~0.base_In68196668|, #memory_int=|#memory_int_In68196668|, ~x$mem_tmp~0=~x$mem_tmp~0_In68196668} OutVars{P0Thread1of1ForFork0_#t~mem28=|P0Thread1of1ForFork0_#t~mem28_Out68196668|, ~x$flush_delayed~0=~x$flush_delayed~0_In68196668, ~#x~0.offset=|~#x~0.offset_In68196668|, P0Thread1of1ForFork0_#t~ite29=|P0Thread1of1ForFork0_#t~ite29_Out68196668|, ~#x~0.base=|~#x~0.base_In68196668|, #memory_int=|#memory_int_In68196668|, ~x$mem_tmp~0=~x$mem_tmp~0_In68196668} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~mem28, P0Thread1of1ForFork0_#t~ite29] because there is no mapped edge [2019-12-07 17:46:31,958 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1117] [1117] L764-2-->P0EXIT: Formula: (and (= |v_#memory_int_248| (store |v_#memory_int_249| |v_~#x~0.base_160| (store (select |v_#memory_int_249| |v_~#x~0.base_160|) |v_~#x~0.offset_160| |v_P0Thread1of1ForFork0_#t~ite29_28|))) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_49 (+ v_~__unbuffered_cnt~0_50 1)) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= v_~x$flush_delayed~0_92 0)) InVars {~#x~0.offset=|v_~#x~0.offset_160|, P0Thread1of1ForFork0_#t~ite29=|v_P0Thread1of1ForFork0_#t~ite29_28|, #memory_int=|v_#memory_int_249|, ~#x~0.base=|v_~#x~0.base_160|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_50} OutVars{P0Thread1of1ForFork0_#t~mem28=|v_P0Thread1of1ForFork0_#t~mem28_17|, P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, ~x$flush_delayed~0=v_~x$flush_delayed~0_92, ~#x~0.offset=|v_~#x~0.offset_160|, P0Thread1of1ForFork0_#t~ite29=|v_P0Thread1of1ForFork0_#t~ite29_27|, #memory_int=|v_#memory_int_248|, ~#x~0.base=|v_~#x~0.base_160|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_49} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~mem28, P0Thread1of1ForFork0_#res.offset, ~x$flush_delayed~0, P0Thread1of1ForFork0_#t~ite29, #memory_int, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 17:46:31,958 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1103] [1103] L784-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= v_~x$r_buff1_thd2~0_28 |v_P1Thread1of1ForFork1_#t~ite36_22|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_40 1) v_~__unbuffered_cnt~0_39)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40, P1Thread1of1ForFork1_#t~ite36=|v_P1Thread1of1ForFork1_#t~ite36_22|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_28, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_39, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|, P1Thread1of1ForFork1_#t~ite36=|v_P1Thread1of1ForFork1_#t~ite36_21|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#res.base, P1Thread1of1ForFork1_#t~ite36] because there is no mapped edge [2019-12-07 17:46:31,958 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [984] [984] L846-->L848-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_118 256) 0) (= (mod v_~x$r_buff0_thd0~0_14 256) 0)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_118} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_118} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 17:46:31,959 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1098] [1098] L848-2-->L848-5: Formula: (let ((.cse0 (= (mod ~x$w_buff1_used~0_In1934817401 256) 0)) (.cse2 (= (mod ~x$r_buff1_thd0~0_In1934817401 256) 0)) (.cse1 (= |ULTIMATE.start_main_#t~ite76_Out1934817401| |ULTIMATE.start_main_#t~ite75_Out1934817401|))) (or (and (= ~x$w_buff1~0_In1934817401 |ULTIMATE.start_main_#t~ite75_Out1934817401|) (not .cse0) .cse1 (not .cse2) (= |ULTIMATE.start_main_#t~mem74_In1934817401| |ULTIMATE.start_main_#t~mem74_Out1934817401|)) (and (= |ULTIMATE.start_main_#t~mem74_Out1934817401| |ULTIMATE.start_main_#t~ite75_Out1934817401|) (= (select (select |#memory_int_In1934817401| |~#x~0.base_In1934817401|) |~#x~0.offset_In1934817401|) |ULTIMATE.start_main_#t~mem74_Out1934817401|) (or .cse0 .cse2) .cse1))) InVars {~#x~0.offset=|~#x~0.offset_In1934817401|, ULTIMATE.start_main_#t~mem74=|ULTIMATE.start_main_#t~mem74_In1934817401|, ~x$w_buff1~0=~x$w_buff1~0_In1934817401, ~#x~0.base=|~#x~0.base_In1934817401|, #memory_int=|#memory_int_In1934817401|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1934817401, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1934817401} OutVars{ULTIMATE.start_main_#t~mem74=|ULTIMATE.start_main_#t~mem74_Out1934817401|, ~#x~0.offset=|~#x~0.offset_In1934817401|, ~x$w_buff1~0=~x$w_buff1~0_In1934817401, ~#x~0.base=|~#x~0.base_In1934817401|, #memory_int=|#memory_int_In1934817401|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1934817401, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1934817401, ULTIMATE.start_main_#t~ite75=|ULTIMATE.start_main_#t~ite75_Out1934817401|, ULTIMATE.start_main_#t~ite76=|ULTIMATE.start_main_#t~ite76_Out1934817401|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem74, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~ite76] because there is no mapped edge [2019-12-07 17:46:31,959 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1080] [1080] L849-->L849-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In128583879 256))) (.cse1 (= (mod ~x$r_buff0_thd0~0_In128583879 256) 0))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite77_Out128583879|) (not .cse1)) (and (= ~x$w_buff0_used~0_In128583879 |ULTIMATE.start_main_#t~ite77_Out128583879|) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In128583879, ~x$w_buff0_used~0=~x$w_buff0_used~0_In128583879} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In128583879, ULTIMATE.start_main_#t~ite77=|ULTIMATE.start_main_#t~ite77_Out128583879|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In128583879} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite77] because there is no mapped edge [2019-12-07 17:46:31,960 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1082] [1082] L850-->L850-2: Formula: (let ((.cse2 (= (mod ~x$w_buff0_used~0_In-1540997010 256) 0)) (.cse3 (= (mod ~x$r_buff0_thd0~0_In-1540997010 256) 0)) (.cse1 (= 0 (mod ~x$r_buff1_thd0~0_In-1540997010 256))) (.cse0 (= (mod ~x$w_buff1_used~0_In-1540997010 256) 0))) (or (and (or .cse0 .cse1) (= ~x$w_buff1_used~0_In-1540997010 |ULTIMATE.start_main_#t~ite78_Out-1540997010|) (or .cse2 .cse3)) (and (= 0 |ULTIMATE.start_main_#t~ite78_Out-1540997010|) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1540997010, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1540997010, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1540997010, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1540997010} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1540997010, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1540997010, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1540997010, ULTIMATE.start_main_#t~ite78=|ULTIMATE.start_main_#t~ite78_Out-1540997010|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1540997010} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite78] because there is no mapped edge [2019-12-07 17:46:31,960 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1078] [1078] L851-->L852: Formula: (let ((.cse1 (= ~x$r_buff0_thd0~0_In1201078314 ~x$r_buff0_thd0~0_Out1201078314)) (.cse0 (= 0 (mod ~x$r_buff0_thd0~0_In1201078314 256))) (.cse2 (= (mod ~x$w_buff0_used~0_In1201078314 256) 0))) (or (and .cse0 .cse1) (and .cse2 .cse1) (and (not .cse0) (= 0 ~x$r_buff0_thd0~0_Out1201078314) (not .cse2)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1201078314, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1201078314} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_Out1201078314, ULTIMATE.start_main_#t~ite79=|ULTIMATE.start_main_#t~ite79_Out1201078314|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1201078314} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite79] because there is no mapped edge [2019-12-07 17:46:31,960 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1096] [1096] L852-->L856: Formula: (let ((.cse3 (= ~x$r_buff1_thd0~0_Out-1259108784 0)) (.cse1 (= (mod ~x$w_buff1_used~0_In-1259108784 256) 0)) (.cse5 (= (mod ~x$w_buff0_used~0_In-1259108784 256) 0)) (.cse0 (= 0 (mod ~x$r_buff1_thd0~0_In-1259108784 256))) (.cse2 (= |ULTIMATE.start_main_#t~nondet81_In-1259108784| ~weak$$choice1~0_Out-1259108784)) (.cse4 (= 0 (mod ~x$r_buff0_thd0~0_In-1259108784 256))) (.cse6 (= ~x$r_buff1_thd0~0_Out-1259108784 ~x$r_buff1_thd0~0_In-1259108784))) (or (and (not .cse0) (not .cse1) .cse2 .cse3) (and .cse2 .cse3 (not .cse4) (not .cse5)) (and .cse2 .cse4 .cse1 .cse6) (and .cse2 .cse1 .cse5 .cse6) (and .cse0 .cse2 .cse5 .cse6) (and .cse0 .cse2 .cse4 .cse6))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1259108784, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1259108784, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1259108784, ULTIMATE.start_main_#t~nondet81=|ULTIMATE.start_main_#t~nondet81_In-1259108784|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1259108784} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1259108784, ~weak$$choice1~0=~weak$$choice1~0_Out-1259108784, ULTIMATE.start_main_#t~ite80=|ULTIMATE.start_main_#t~ite80_Out-1259108784|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1259108784, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_Out-1259108784, ULTIMATE.start_main_#t~nondet81=|ULTIMATE.start_main_#t~nondet81_Out-1259108784|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1259108784} AuxVars[] AssignedVars[~weak$$choice1~0, ULTIMATE.start_main_#t~ite80, ~x$r_buff1_thd0~0, ULTIMATE.start_main_#t~nondet81] because there is no mapped edge [2019-12-07 17:46:31,960 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1069] [1069] L856-->L856-3: Formula: (let ((.cse0 (not (= (mod ~__unbuffered_p2_EAX$read_delayed~0_In-388216409 256) 0))) (.cse1 (= 0 (mod ~weak$$choice1~0_In-388216409 256)))) (or (and (= |ULTIMATE.start_main_#t~mem82_In-388216409| |ULTIMATE.start_main_#t~mem82_Out-388216409|) .cse0 .cse1 (= ~__unbuffered_p2_EAX~0_In-388216409 |ULTIMATE.start_main_#t~ite83_Out-388216409|)) (and .cse0 (not .cse1) (= |ULTIMATE.start_main_#t~mem82_Out-388216409| (select (select |#memory_int_In-388216409| ~__unbuffered_p2_EAX$read_delayed_var~0.base_In-388216409) ~__unbuffered_p2_EAX$read_delayed_var~0.offset_In-388216409)) (= |ULTIMATE.start_main_#t~mem82_Out-388216409| |ULTIMATE.start_main_#t~ite83_Out-388216409|)))) InVars {~weak$$choice1~0=~weak$$choice1~0_In-388216409, ~__unbuffered_p2_EAX$read_delayed_var~0.offset=~__unbuffered_p2_EAX$read_delayed_var~0.offset_In-388216409, ~__unbuffered_p2_EAX$read_delayed_var~0.base=~__unbuffered_p2_EAX$read_delayed_var~0.base_In-388216409, ULTIMATE.start_main_#t~mem82=|ULTIMATE.start_main_#t~mem82_In-388216409|, #memory_int=|#memory_int_In-388216409|, ~__unbuffered_p2_EAX~0=~__unbuffered_p2_EAX~0_In-388216409, ~__unbuffered_p2_EAX$read_delayed~0=~__unbuffered_p2_EAX$read_delayed~0_In-388216409} OutVars{ULTIMATE.start_main_#t~ite83=|ULTIMATE.start_main_#t~ite83_Out-388216409|, ~weak$$choice1~0=~weak$$choice1~0_In-388216409, ~__unbuffered_p2_EAX$read_delayed_var~0.offset=~__unbuffered_p2_EAX$read_delayed_var~0.offset_In-388216409, ULTIMATE.start_main_#t~mem82=|ULTIMATE.start_main_#t~mem82_Out-388216409|, ~__unbuffered_p2_EAX$read_delayed_var~0.base=~__unbuffered_p2_EAX$read_delayed_var~0.base_In-388216409, #memory_int=|#memory_int_In-388216409|, ~__unbuffered_p2_EAX~0=~__unbuffered_p2_EAX~0_In-388216409, ~__unbuffered_p2_EAX$read_delayed~0=~__unbuffered_p2_EAX$read_delayed~0_In-388216409} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite83, ULTIMATE.start_main_#t~mem82] because there is no mapped edge [2019-12-07 17:46:31,961 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1130] [1130] L856-3-->L5: Formula: (and (= (mod v_~main$tmp_guard1~0_21 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|) (let ((.cse3 (= v_~__unbuffered_p2_EBX~0_21 0)) (.cse1 (= 1 v_~__unbuffered_p2_EAX~0_46)) (.cse0 (= v_~main$tmp_guard1~0_21 1)) (.cse4 (= 0 v_~__unbuffered_p0_EAX~0_48)) (.cse2 (= |v_ULTIMATE.start_main_#t~ite83_36| v_~__unbuffered_p2_EAX~0_46))) (or (and .cse0 (not .cse1) .cse2) (and .cse0 (not .cse3) .cse2) (and (= v_~main$tmp_guard1~0_21 0) .cse3 .cse1 .cse4 .cse2) (and .cse0 (not .cse4) .cse2)))) InVars {~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_48, ULTIMATE.start_main_#t~ite83=|v_ULTIMATE.start_main_#t~ite83_36|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_21} OutVars{ULTIMATE.start_main_#t~ite84=|v_ULTIMATE.start_main_#t~ite84_33|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_48, ULTIMATE.start_main_#t~ite83=|v_ULTIMATE.start_main_#t~ite83_35|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_21, ULTIMATE.start_main_#t~mem82=|v_ULTIMATE.start_main_#t~mem82_27|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_46, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite84, ULTIMATE.start_main_#t~ite83, ULTIMATE.start___VERIFIER_assert_~expression, ULTIMATE.start_main_#t~mem82, ~main$tmp_guard1~0, ~__unbuffered_p2_EAX~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 17:46:31,961 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1131] [1131] L5-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 17:46:32,033 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 05:46:32 BasicIcfg [2019-12-07 17:46:32,033 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 17:46:32,034 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 17:46:32,034 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 17:46:32,034 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 17:46:32,034 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:36:34" (3/4) ... [2019-12-07 17:46:32,035 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 17:46:32,036 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1160] [1160] ULTIMATE.startENTRY-->L838: Formula: (let ((.cse1 (store |v_#valid_73| 0 0))) (let ((.cse0 (store .cse1 |v_~#x~0.base_244| 1))) (and (< |v_#StackHeapBarrier_24| |v_ULTIMATE.start_main_~#t2464~0.base_22|) (= |v_#valid_71| (store .cse0 |v_ULTIMATE.start_main_~#t2464~0.base_22| 1)) (= v_~__unbuffered_cnt~0_104 0) (= 0 v_~x$r_buff0_thd3~0_278) (= 0 v_~__unbuffered_p2_EAX$r_buff0_thd1~0_8) (= v_~main$tmp_guard1~0_31 0) (= |v_#NULL.offset_6| 0) (= 0 v_~__unbuffered_p2_EAX$w_buff0~0_7) (= (select (select |v_#memory_int_395| |v_~#x~0.base_244|) |v_~#x~0.offset_244|) 0) (= v_~x$r_buff1_thd0~0_77 0) (= 0 v_~__unbuffered_p2_EAX$r_buff0_thd2~0_8) (= 0 v_~__unbuffered_p2_EAX$w_buff0_used~0_7) (= 0 v_~__unbuffered_p2_EAX$w_buff1~0_7) (= 0 v_~x$w_buff1~0_137) (= 0 |v_~#x~0.offset_244|) (= 0 v_~x$read_delayed_var~0.base_7) (= 0 v_~__unbuffered_p0_EAX~0_70) (= v_~x$r_buff1_thd2~0_55 0) (= 0 v_~__unbuffered_p2_EAX$r_buff0_thd3~0_6) (= v_~weak$$choice2~0_140 0) (= 0 v_~x$read_delayed~0_8) (= v_~x$mem_tmp~0_82 0) (= v_~__unbuffered_p2_EBX~0_33 0) (= 0 v_~x$r_buff0_thd0~0_89) (= 0 v_~x$w_buff1_used~0_483) (= 0 v_~__unbuffered_p2_EAX$mem_tmp~0_8) (= v_~main$tmp_guard0~0_33 0) (= 0 v_~x$w_buff0~0_164) (= 0 v_~x$r_buff1_thd3~0_181) (= v_~y~0_51 0) (= 0 v_~x$read_delayed_var~0.offset_7) (< |v_#StackHeapBarrier_24| |v_~#x~0.base_244|) (= 0 v_~x$w_buff0_used~0_778) (= v_~x$r_buff0_thd1~0_285 0) (= 0 v_~__unbuffered_p2_EAX$r_buff1_thd1~0_7) (= |v_#length_36| (store (store |v_#length_37| |v_~#x~0.base_244| 4) |v_ULTIMATE.start_main_~#t2464~0.base_22| 4)) (= (store |v_#memory_int_395| |v_ULTIMATE.start_main_~#t2464~0.base_22| (store (select |v_#memory_int_395| |v_ULTIMATE.start_main_~#t2464~0.base_22|) |v_ULTIMATE.start_main_~#t2464~0.offset_17| 0)) |v_#memory_int_394|) (< 0 |v_#StackHeapBarrier_24|) (= 0 v_~__unbuffered_p2_EAX$flush_delayed~0_7) (= 0 (select .cse1 |v_~#x~0.base_244|)) (= 0 v_~__unbuffered_p2_EAX$r_buff1_thd2~0_7) (= 0 v_~__unbuffered_p2_EAX~0_77) (= 0 v_~__unbuffered_p2_EAX$read_delayed_var~0.offset_44) (= 0 v_~__unbuffered_p2_EAX$r_buff1_thd0~0_6) (= 0 v_~__unbuffered_p2_EAX$w_buff1_used~0_7) (= 0 v_~weak$$choice0~0_74) (= 0 v_~weak$$choice1~0_28) (= v_~__unbuffered_p2_EAX$read_delayed~0_57 0) (= 0 |v_#NULL.base_6|) (= 0 v_~__unbuffered_p2_EAX$read_delayed_var~0.base_44) (= 0 v_~__unbuffered_p2_EAX$r_buff0_thd0~0_8) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t2464~0.base_22|)) (= v_~x$r_buff1_thd1~0_182 0) (= v_~x$flush_delayed~0_108 0) (= 0 |v_ULTIMATE.start_main_~#t2464~0.offset_17|) (= 0 v_~__unbuffered_p2_EAX$r_buff1_thd3~0_7) (= 0 v_~x$r_buff0_thd2~0_71)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_24|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_395|, #length=|v_#length_37|} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_164, ~x$flush_delayed~0=v_~x$flush_delayed~0_108, ~__unbuffered_p2_EAX$read_delayed_var~0.offset=v_~__unbuffered_p2_EAX$read_delayed_var~0.offset_44, ~__unbuffered_p2_EAX$read_delayed_var~0.base=v_~__unbuffered_p2_EAX$read_delayed_var~0.base_44, #NULL.offset=|v_#NULL.offset_6|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_182, ULTIMATE.start_main_~#t2464~0.base=|v_ULTIMATE.start_main_~#t2464~0.base_22|, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_278, ULTIMATE.start_main_#t~nondet72=|v_ULTIMATE.start_main_#t~nondet72_7|, ULTIMATE.start_main_~#t2466~0.offset=|v_ULTIMATE.start_main_~#t2466~0.offset_21|, ~weak$$choice1~0=v_~weak$$choice1~0_28, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_70, ~__unbuffered_p2_EAX$w_buff0_used~0=v_~__unbuffered_p2_EAX$w_buff0_used~0_7, #length=|v_#length_36|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_77, ~__unbuffered_p2_EAX$r_buff1_thd2~0=v_~__unbuffered_p2_EAX$r_buff1_thd2~0_7, ~__unbuffered_p2_EAX$r_buff0_thd0~0=v_~__unbuffered_p2_EAX$r_buff0_thd0~0_8, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_89, ~__unbuffered_p2_EAX$w_buff0~0=v_~__unbuffered_p2_EAX$w_buff0~0_7, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_33, ~#x~0.offset=|v_~#x~0.offset_244|, ~x$w_buff1~0=v_~x$w_buff1~0_137, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_483, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_55, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_21|, ULTIMATE.start_main_#t~ite77=|v_ULTIMATE.start_main_#t~ite77_115|, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_21|, ULTIMATE.start_main_#t~nondet81=|v_ULTIMATE.start_main_#t~nondet81_33|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_7, ULTIMATE.start_main_~#t2464~0.offset=|v_ULTIMATE.start_main_~#t2464~0.offset_17|, ULTIMATE.start_main_#t~ite84=|v_ULTIMATE.start_main_#t~ite84_51|, ~weak$$choice0~0=v_~weak$$choice0~0_74, #StackHeapBarrier=|v_#StackHeapBarrier_24|, ULTIMATE.start_main_#t~ite80=|v_ULTIMATE.start_main_#t~ite80_32|, ~__unbuffered_p2_EAX$r_buff0_thd1~0=v_~__unbuffered_p2_EAX$r_buff0_thd1~0_8, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_104, ULTIMATE.start_main_~#t2466~0.base=|v_ULTIMATE.start_main_~#t2466~0.base_24|, ~__unbuffered_p2_EAX$r_buff1_thd3~0=v_~__unbuffered_p2_EAX$r_buff1_thd3~0_7, ~__unbuffered_p2_EAX$w_buff1~0=v_~__unbuffered_p2_EAX$w_buff1~0_7, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_285, ULTIMATE.start_main_#t~nondet73=|v_ULTIMATE.start_main_#t~nondet73_20|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_181, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_31, ~x$mem_tmp~0=v_~x$mem_tmp~0_82, ULTIMATE.start_main_#t~nondet71=|v_ULTIMATE.start_main_#t~nondet71_8|, ULTIMATE.start_main_~#t2465~0.base=|v_ULTIMATE.start_main_~#t2465~0.base_31|, ~__unbuffered_p2_EAX$w_buff1_used~0=v_~__unbuffered_p2_EAX$w_buff1_used~0_7, ~__unbuffered_p2_EAX$r_buff0_thd2~0=v_~__unbuffered_p2_EAX$r_buff0_thd2~0_8, ~__unbuffered_p2_EAX$r_buff1_thd0~0=v_~__unbuffered_p2_EAX$r_buff1_thd0~0_6, ~y~0=v_~y~0_51, ULTIMATE.start_main_~#t2465~0.offset=|v_ULTIMATE.start_main_~#t2465~0.offset_28|, ULTIMATE.start_main_#t~mem74=|v_ULTIMATE.start_main_#t~mem74_20|, ~__unbuffered_p2_EAX$mem_tmp~0=v_~__unbuffered_p2_EAX$mem_tmp~0_8, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_33, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_77, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_71, ULTIMATE.start_main_#t~ite78=|v_ULTIMATE.start_main_#t~ite78_299|, ~__unbuffered_p2_EAX$flush_delayed~0=v_~__unbuffered_p2_EAX$flush_delayed~0_7, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_24|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_778, ~__unbuffered_p2_EAX$read_delayed~0=v_~__unbuffered_p2_EAX$read_delayed~0_57, ULTIMATE.start_main_#t~ite83=|v_ULTIMATE.start_main_#t~ite83_50|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_7, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, #valid=|v_#valid_71|, ULTIMATE.start_main_#t~mem82=|v_ULTIMATE.start_main_#t~mem82_37|, #memory_int=|v_#memory_int_394|, ~#x~0.base=|v_~#x~0.base_244|, ~__unbuffered_p2_EAX$r_buff1_thd1~0=v_~__unbuffered_p2_EAX$r_buff1_thd1~0_7, ~__unbuffered_p2_EAX$r_buff0_thd3~0=v_~__unbuffered_p2_EAX$r_buff0_thd3~0_6, ~weak$$choice2~0=v_~weak$$choice2~0_140, ~x$read_delayed~0=v_~x$read_delayed~0_8} AuxVars[] AssignedVars[~x$w_buff0~0, ~x$flush_delayed~0, ~__unbuffered_p2_EAX$read_delayed_var~0.offset, ~__unbuffered_p2_EAX$read_delayed_var~0.base, #NULL.offset, ~x$r_buff1_thd1~0, ULTIMATE.start_main_~#t2464~0.base, ~x$r_buff0_thd3~0, ULTIMATE.start_main_#t~nondet72, ULTIMATE.start_main_~#t2466~0.offset, ~weak$$choice1~0, ~__unbuffered_p0_EAX~0, ~__unbuffered_p2_EAX$w_buff0_used~0, #length, ~__unbuffered_p2_EAX~0, ~__unbuffered_p2_EAX$r_buff1_thd2~0, ~__unbuffered_p2_EAX$r_buff0_thd0~0, ~x$r_buff0_thd0~0, ~__unbuffered_p2_EAX$w_buff0~0, ~__unbuffered_p2_EBX~0, ~#x~0.offset, ~x$w_buff1~0, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite79, ULTIMATE.start_main_#t~ite77, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~nondet81, ~x$read_delayed_var~0.base, ULTIMATE.start_main_~#t2464~0.offset, ULTIMATE.start_main_#t~ite84, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite80, ~__unbuffered_p2_EAX$r_buff0_thd1~0, ~__unbuffered_cnt~0, ULTIMATE.start_main_~#t2466~0.base, ~__unbuffered_p2_EAX$r_buff1_thd3~0, ~__unbuffered_p2_EAX$w_buff1~0, ~x$r_buff0_thd1~0, ULTIMATE.start_main_#t~nondet73, ~x$r_buff1_thd3~0, ~main$tmp_guard1~0, ~x$mem_tmp~0, ULTIMATE.start_main_#t~nondet71, ULTIMATE.start_main_~#t2465~0.base, ~__unbuffered_p2_EAX$w_buff1_used~0, ~__unbuffered_p2_EAX$r_buff0_thd2~0, ~__unbuffered_p2_EAX$r_buff1_thd0~0, ~y~0, ULTIMATE.start_main_~#t2465~0.offset, ULTIMATE.start_main_#t~mem74, ~__unbuffered_p2_EAX$mem_tmp~0, ~main$tmp_guard0~0, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite78, ~__unbuffered_p2_EAX$flush_delayed~0, #NULL.base, ULTIMATE.start_main_#t~ite76, ~x$w_buff0_used~0, ~__unbuffered_p2_EAX$read_delayed~0, ULTIMATE.start_main_#t~ite83, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_#res, #valid, ULTIMATE.start_main_#t~mem82, #memory_int, ~#x~0.base, ~__unbuffered_p2_EAX$r_buff1_thd1~0, ~__unbuffered_p2_EAX$r_buff0_thd3~0, ~weak$$choice2~0, ~x$read_delayed~0] because there is no mapped edge [2019-12-07 17:46:32,036 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1126] [1126] L838-1-->L840: Formula: (and (= (store |v_#memory_int_282| |v_ULTIMATE.start_main_~#t2465~0.base_23| (store (select |v_#memory_int_282| |v_ULTIMATE.start_main_~#t2465~0.base_23|) |v_ULTIMATE.start_main_~#t2465~0.offset_22| 1)) |v_#memory_int_281|) (= |v_#valid_35| (store |v_#valid_36| |v_ULTIMATE.start_main_~#t2465~0.base_23| 1)) (= 0 (select |v_#valid_36| |v_ULTIMATE.start_main_~#t2465~0.base_23|)) (not (= |v_ULTIMATE.start_main_~#t2465~0.base_23| 0)) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t2465~0.base_23| 4)) (= 0 |v_ULTIMATE.start_main_~#t2465~0.offset_22|) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t2465~0.base_23|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_282|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_~#t2465~0.base=|v_ULTIMATE.start_main_~#t2465~0.base_23|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_281|, #length=|v_#length_21|, ULTIMATE.start_main_#t~nondet71=|v_ULTIMATE.start_main_#t~nondet71_4|, ULTIMATE.start_main_~#t2465~0.offset=|v_ULTIMATE.start_main_~#t2465~0.offset_22|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2465~0.base, #valid, #memory_int, #length, ULTIMATE.start_main_#t~nondet71, ULTIMATE.start_main_~#t2465~0.offset] because there is no mapped edge [2019-12-07 17:46:32,037 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1125] [1125] L840-1-->L842: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t2466~0.base_14|)) (= 0 |v_ULTIMATE.start_main_~#t2466~0.offset_14|) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t2466~0.base_14|) (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2466~0.base_14| 1)) (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t2466~0.base_14| 4)) (= |v_#memory_int_279| (store |v_#memory_int_280| |v_ULTIMATE.start_main_~#t2466~0.base_14| (store (select |v_#memory_int_280| |v_ULTIMATE.start_main_~#t2466~0.base_14|) |v_ULTIMATE.start_main_~#t2466~0.offset_14| 2))) (= (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2466~0.base_14|) 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_280|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_279|, #length=|v_#length_19|, ULTIMATE.start_main_~#t2466~0.base=|v_ULTIMATE.start_main_~#t2466~0.base_14|, ULTIMATE.start_main_#t~nondet72=|v_ULTIMATE.start_main_#t~nondet72_3|, ULTIMATE.start_main_~#t2466~0.offset=|v_ULTIMATE.start_main_~#t2466~0.offset_14|} AuxVars[] AssignedVars[#valid, #memory_int, #length, ULTIMATE.start_main_~#t2466~0.base, ULTIMATE.start_main_#t~nondet72, ULTIMATE.start_main_~#t2466~0.offset] because there is no mapped edge [2019-12-07 17:46:32,040 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1087] [1087] L780-2-->L780-4: Formula: (let ((.cse1 (= (mod ~x$w_buff1_used~0_In-883408411 256) 0)) (.cse0 (= 0 (mod ~x$r_buff1_thd2~0_In-883408411 256)))) (or (and (or .cse0 .cse1) (= (select (select |#memory_int_In-883408411| |~#x~0.base_In-883408411|) |~#x~0.offset_In-883408411|) |P1Thread1of1ForFork1_#t~mem30_Out-883408411|) (= |P1Thread1of1ForFork1_#t~ite31_Out-883408411| |P1Thread1of1ForFork1_#t~mem30_Out-883408411|)) (and (= |P1Thread1of1ForFork1_#t~mem30_In-883408411| |P1Thread1of1ForFork1_#t~mem30_Out-883408411|) (not .cse1) (not .cse0) (= |P1Thread1of1ForFork1_#t~ite31_Out-883408411| ~x$w_buff1~0_In-883408411)))) InVars {P1Thread1of1ForFork1_#t~mem30=|P1Thread1of1ForFork1_#t~mem30_In-883408411|, ~#x~0.offset=|~#x~0.offset_In-883408411|, ~x$w_buff1~0=~x$w_buff1~0_In-883408411, ~#x~0.base=|~#x~0.base_In-883408411|, #memory_int=|#memory_int_In-883408411|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-883408411, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-883408411} OutVars{P1Thread1of1ForFork1_#t~mem30=|P1Thread1of1ForFork1_#t~mem30_Out-883408411|, P1Thread1of1ForFork1_#t~ite31=|P1Thread1of1ForFork1_#t~ite31_Out-883408411|, ~#x~0.offset=|~#x~0.offset_In-883408411|, ~x$w_buff1~0=~x$w_buff1~0_In-883408411, ~#x~0.base=|~#x~0.base_In-883408411|, #memory_int=|#memory_int_In-883408411|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-883408411, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-883408411} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~mem30, P1Thread1of1ForFork1_#t~ite31] because there is no mapped edge [2019-12-07 17:46:32,040 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1014] [1014] L780-4-->L781: Formula: (= (store |v_#memory_int_69| |v_~#x~0.base_42| (store (select |v_#memory_int_69| |v_~#x~0.base_42|) |v_~#x~0.offset_42| |v_P1Thread1of1ForFork1_#t~ite31_6|)) |v_#memory_int_68|) InVars {~#x~0.offset=|v_~#x~0.offset_42|, P1Thread1of1ForFork1_#t~ite31=|v_P1Thread1of1ForFork1_#t~ite31_6|, #memory_int=|v_#memory_int_69|, ~#x~0.base=|v_~#x~0.base_42|} OutVars{P1Thread1of1ForFork1_#t~mem30=|v_P1Thread1of1ForFork1_#t~mem30_3|, ~#x~0.offset=|v_~#x~0.offset_42|, P1Thread1of1ForFork1_#t~ite31=|v_P1Thread1of1ForFork1_#t~ite31_5|, #memory_int=|v_#memory_int_68|, ~#x~0.base=|v_~#x~0.base_42|, P1Thread1of1ForFork1_#t~ite32=|v_P1Thread1of1ForFork1_#t~ite32_7|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~mem30, P1Thread1of1ForFork1_#t~ite31, #memory_int, P1Thread1of1ForFork1_#t~ite32] because there is no mapped edge [2019-12-07 17:46:32,040 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1084] [1084] L781-->L781-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd2~0_In241140032 256))) (.cse0 (= (mod ~x$w_buff0_used~0_In241140032 256) 0))) (or (and (= |P1Thread1of1ForFork1_#t~ite33_Out241140032| 0) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |P1Thread1of1ForFork1_#t~ite33_Out241140032| ~x$w_buff0_used~0_In241140032)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In241140032, ~x$w_buff0_used~0=~x$w_buff0_used~0_In241140032} OutVars{P1Thread1of1ForFork1_#t~ite33=|P1Thread1of1ForFork1_#t~ite33_Out241140032|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In241140032, ~x$w_buff0_used~0=~x$w_buff0_used~0_In241140032} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite33] because there is no mapped edge [2019-12-07 17:46:32,040 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1081] [1081] L782-->L782-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff1_thd2~0_In959597545 256))) (.cse0 (= (mod ~x$w_buff1_used~0_In959597545 256) 0)) (.cse2 (= (mod ~x$w_buff0_used~0_In959597545 256) 0)) (.cse3 (= (mod ~x$r_buff0_thd2~0_In959597545 256) 0))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite34_Out959597545| ~x$w_buff1_used~0_In959597545) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork1_#t~ite34_Out959597545| 0)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In959597545, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In959597545, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In959597545, ~x$w_buff0_used~0=~x$w_buff0_used~0_In959597545} OutVars{P1Thread1of1ForFork1_#t~ite34=|P1Thread1of1ForFork1_#t~ite34_Out959597545|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In959597545, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In959597545, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In959597545, ~x$w_buff0_used~0=~x$w_buff0_used~0_In959597545} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite34] because there is no mapped edge [2019-12-07 17:46:32,041 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1093] [1093] L783-->L784: Formula: (let ((.cse0 (= (mod ~x$r_buff0_thd2~0_In-220765501 256) 0)) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In-220765501 256))) (.cse2 (= ~x$r_buff0_thd2~0_Out-220765501 ~x$r_buff0_thd2~0_In-220765501))) (or (and (not .cse0) (not .cse1) (= ~x$r_buff0_thd2~0_Out-220765501 0)) (and .cse2 .cse0) (and .cse1 .cse2))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-220765501, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-220765501} OutVars{P1Thread1of1ForFork1_#t~ite35=|P1Thread1of1ForFork1_#t~ite35_Out-220765501|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out-220765501, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-220765501} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite35, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-12-07 17:46:32,041 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1097] [1097] L784-->L784-2: Formula: (let ((.cse2 (= (mod ~x$w_buff0_used~0_In-1011398210 256) 0)) (.cse3 (= 0 (mod ~x$r_buff0_thd2~0_In-1011398210 256))) (.cse1 (= (mod ~x$r_buff1_thd2~0_In-1011398210 256) 0)) (.cse0 (= (mod ~x$w_buff1_used~0_In-1011398210 256) 0))) (or (and (or .cse0 .cse1) (= ~x$r_buff1_thd2~0_In-1011398210 |P1Thread1of1ForFork1_#t~ite36_Out-1011398210|) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |P1Thread1of1ForFork1_#t~ite36_Out-1011398210|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1011398210, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1011398210, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1011398210, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1011398210} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-1011398210, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1011398210, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1011398210, P1Thread1of1ForFork1_#t~ite36=|P1Thread1of1ForFork1_#t~ite36_Out-1011398210|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1011398210} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite36] because there is no mapped edge [2019-12-07 17:46:32,044 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1032] [1032] L803-->L804: Formula: (and (= v_~x$r_buff0_thd3~0_105 v_~x$r_buff0_thd3~0_104) (not (= (mod v_~weak$$choice2~0_77 256) 0))) InVars {~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_105, ~weak$$choice2~0=v_~weak$$choice2~0_77} OutVars{P2Thread1of1ForFork2_#t~ite56=|v_P2Thread1of1ForFork2_#t~ite56_9|, P2Thread1of1ForFork2_#t~ite57=|v_P2Thread1of1ForFork2_#t~ite57_9|, P2Thread1of1ForFork2_#t~ite55=|v_P2Thread1of1ForFork2_#t~ite55_10|, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_104, ~weak$$choice2~0=v_~weak$$choice2~0_77} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite56, P2Thread1of1ForFork2_#t~ite57, P2Thread1of1ForFork2_#t~ite55, ~x$r_buff0_thd3~0] because there is no mapped edge [2019-12-07 17:46:32,045 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1083] [1083] L808-->L808-2: Formula: (let ((.cse0 (= 0 (mod ~x$flush_delayed~0_In-589175640 256)))) (or (and .cse0 (= |P2Thread1of1ForFork2_#t~mem62_Out-589175640| |P2Thread1of1ForFork2_#t~ite63_Out-589175640|) (= |P2Thread1of1ForFork2_#t~mem62_Out-589175640| (select (select |#memory_int_In-589175640| |~#x~0.base_In-589175640|) |~#x~0.offset_In-589175640|))) (and (not .cse0) (= |P2Thread1of1ForFork2_#t~mem62_In-589175640| |P2Thread1of1ForFork2_#t~mem62_Out-589175640|) (= ~x$mem_tmp~0_In-589175640 |P2Thread1of1ForFork2_#t~ite63_Out-589175640|)))) InVars {~x$flush_delayed~0=~x$flush_delayed~0_In-589175640, ~#x~0.offset=|~#x~0.offset_In-589175640|, ~#x~0.base=|~#x~0.base_In-589175640|, #memory_int=|#memory_int_In-589175640|, ~x$mem_tmp~0=~x$mem_tmp~0_In-589175640, P2Thread1of1ForFork2_#t~mem62=|P2Thread1of1ForFork2_#t~mem62_In-589175640|} OutVars{~x$flush_delayed~0=~x$flush_delayed~0_In-589175640, ~#x~0.offset=|~#x~0.offset_In-589175640|, P2Thread1of1ForFork2_#t~ite63=|P2Thread1of1ForFork2_#t~ite63_Out-589175640|, ~#x~0.base=|~#x~0.base_In-589175640|, #memory_int=|#memory_int_In-589175640|, ~x$mem_tmp~0=~x$mem_tmp~0_In-589175640, P2Thread1of1ForFork2_#t~mem62=|P2Thread1of1ForFork2_#t~mem62_Out-589175640|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite63, P2Thread1of1ForFork2_#t~mem62] because there is no mapped edge [2019-12-07 17:46:32,048 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1079] [1079] L815-2-->L815-4: Formula: (let ((.cse0 (= (mod ~x$r_buff1_thd3~0_In-1560808699 256) 0)) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In-1560808699 256)))) (or (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork2_#t~mem64_In-1560808699| |P2Thread1of1ForFork2_#t~mem64_Out-1560808699|) (= ~x$w_buff1~0_In-1560808699 |P2Thread1of1ForFork2_#t~ite65_Out-1560808699|)) (and (= |P2Thread1of1ForFork2_#t~mem64_Out-1560808699| (select (select |#memory_int_In-1560808699| |~#x~0.base_In-1560808699|) |~#x~0.offset_In-1560808699|)) (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~mem64_Out-1560808699| |P2Thread1of1ForFork2_#t~ite65_Out-1560808699|)))) InVars {~#x~0.offset=|~#x~0.offset_In-1560808699|, ~x$w_buff1~0=~x$w_buff1~0_In-1560808699, ~#x~0.base=|~#x~0.base_In-1560808699|, #memory_int=|#memory_int_In-1560808699|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1560808699, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1560808699, P2Thread1of1ForFork2_#t~mem64=|P2Thread1of1ForFork2_#t~mem64_In-1560808699|} OutVars{P2Thread1of1ForFork2_#t~ite65=|P2Thread1of1ForFork2_#t~ite65_Out-1560808699|, ~#x~0.offset=|~#x~0.offset_In-1560808699|, ~x$w_buff1~0=~x$w_buff1~0_In-1560808699, ~#x~0.base=|~#x~0.base_In-1560808699|, #memory_int=|#memory_int_In-1560808699|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1560808699, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1560808699, P2Thread1of1ForFork2_#t~mem64=|P2Thread1of1ForFork2_#t~mem64_Out-1560808699|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite65, P2Thread1of1ForFork2_#t~mem64] because there is no mapped edge [2019-12-07 17:46:32,048 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1033] [1033] L815-4-->L816: Formula: (= (store |v_#memory_int_131| |v_~#x~0.base_85| (store (select |v_#memory_int_131| |v_~#x~0.base_85|) |v_~#x~0.offset_85| |v_P2Thread1of1ForFork2_#t~ite65_10|)) |v_#memory_int_130|) InVars {P2Thread1of1ForFork2_#t~ite65=|v_P2Thread1of1ForFork2_#t~ite65_10|, ~#x~0.offset=|v_~#x~0.offset_85|, #memory_int=|v_#memory_int_131|, ~#x~0.base=|v_~#x~0.base_85|} OutVars{P2Thread1of1ForFork2_#t~ite65=|v_P2Thread1of1ForFork2_#t~ite65_9|, P2Thread1of1ForFork2_#t~ite66=|v_P2Thread1of1ForFork2_#t~ite66_5|, ~#x~0.offset=|v_~#x~0.offset_85|, #memory_int=|v_#memory_int_130|, ~#x~0.base=|v_~#x~0.base_85|, P2Thread1of1ForFork2_#t~mem64=|v_P2Thread1of1ForFork2_#t~mem64_5|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite65, P2Thread1of1ForFork2_#t~ite66, #memory_int, P2Thread1of1ForFork2_#t~mem64] because there is no mapped edge [2019-12-07 17:46:32,049 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1086] [1086] L816-->L816-2: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd3~0_In1761775048 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In1761775048 256)))) (or (and (= ~x$w_buff0_used~0_In1761775048 |P2Thread1of1ForFork2_#t~ite67_Out1761775048|) (or .cse0 .cse1)) (and (= 0 |P2Thread1of1ForFork2_#t~ite67_Out1761775048|) (not .cse1) (not .cse0)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1761775048, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1761775048} OutVars{P2Thread1of1ForFork2_#t~ite67=|P2Thread1of1ForFork2_#t~ite67_Out1761775048|, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1761775048, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1761775048} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite67] because there is no mapped edge [2019-12-07 17:46:32,049 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1095] [1095] L817-->L817-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff1_used~0_In1718553415 256))) (.cse1 (= 0 (mod ~x$r_buff1_thd3~0_In1718553415 256))) (.cse3 (= (mod ~x$w_buff0_used~0_In1718553415 256) 0)) (.cse2 (= (mod ~x$r_buff0_thd3~0_In1718553415 256) 0))) (or (and (= 0 |P2Thread1of1ForFork2_#t~ite68_Out1718553415|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse3 .cse2) (= ~x$w_buff1_used~0_In1718553415 |P2Thread1of1ForFork2_#t~ite68_Out1718553415|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In1718553415, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1718553415, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1718553415, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1718553415} OutVars{P2Thread1of1ForFork2_#t~ite68=|P2Thread1of1ForFork2_#t~ite68_Out1718553415|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1718553415, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1718553415, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1718553415, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1718553415} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite68] because there is no mapped edge [2019-12-07 17:46:32,050 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1077] [1077] L818-->L819: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In-1685145752 256) 0)) (.cse2 (= ~x$r_buff0_thd3~0_In-1685145752 ~x$r_buff0_thd3~0_Out-1685145752)) (.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In-1685145752 256)))) (or (and (not .cse0) (= 0 ~x$r_buff0_thd3~0_Out-1685145752) (not .cse1)) (and .cse1 .cse2) (and .cse2 .cse0))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1685145752, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1685145752} OutVars{P2Thread1of1ForFork2_#t~ite69=|P2Thread1of1ForFork2_#t~ite69_Out-1685145752|, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_Out-1685145752, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1685145752} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite69, ~x$r_buff0_thd3~0] because there is no mapped edge [2019-12-07 17:46:32,050 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1089] [1089] L819-->L819-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In-1018117050 256) 0)) (.cse1 (= 0 (mod ~x$r_buff0_thd3~0_In-1018117050 256))) (.cse2 (= 0 (mod ~x$w_buff1_used~0_In-1018117050 256))) (.cse3 (= 0 (mod ~x$r_buff1_thd3~0_In-1018117050 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork2_#t~ite70_Out-1018117050| 0)) (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork2_#t~ite70_Out-1018117050| ~x$r_buff1_thd3~0_In-1018117050)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1018117050, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1018117050, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1018117050, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1018117050} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-1018117050, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1018117050, P2Thread1of1ForFork2_#t~ite70=|P2Thread1of1ForFork2_#t~ite70_Out-1018117050|, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1018117050, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1018117050} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite70] because there is no mapped edge [2019-12-07 17:46:32,050 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1122] [1122] L819-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork2_#t~ite70_34| v_~x$r_buff1_thd3~0_127) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_67 (+ v_~__unbuffered_cnt~0_68 1))) InVars {P2Thread1of1ForFork2_#t~ite70=|v_P2Thread1of1ForFork2_#t~ite70_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_68} OutVars{~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_127, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, P2Thread1of1ForFork2_#t~ite70=|v_P2Thread1of1ForFork2_#t~ite70_33|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[~x$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, P2Thread1of1ForFork2_#t~ite70, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 17:46:32,053 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1041] [1041] L761-->L762: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_97 256))) (= v_~x$r_buff0_thd1~0_107 v_~x$r_buff0_thd1~0_106)) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_107, ~weak$$choice2~0=v_~weak$$choice2~0_97} OutVars{P0Thread1of1ForFork0_#t~ite22=|v_P0Thread1of1ForFork0_#t~ite22_7|, P0Thread1of1ForFork0_#t~ite21=|v_P0Thread1of1ForFork0_#t~ite21_9|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_106, ~weak$$choice2~0=v_~weak$$choice2~0_97, P0Thread1of1ForFork0_#t~ite23=|v_P0Thread1of1ForFork0_#t~ite23_7|} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite22, P0Thread1of1ForFork0_#t~ite21, ~x$r_buff0_thd1~0, P0Thread1of1ForFork0_#t~ite23] because there is no mapped edge [2019-12-07 17:46:32,054 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1075] [1075] L764-->L764-2: Formula: (let ((.cse0 (= (mod ~x$flush_delayed~0_In68196668 256) 0))) (or (and (not .cse0) (= |P0Thread1of1ForFork0_#t~mem28_In68196668| |P0Thread1of1ForFork0_#t~mem28_Out68196668|) (= |P0Thread1of1ForFork0_#t~ite29_Out68196668| ~x$mem_tmp~0_In68196668)) (and .cse0 (= |P0Thread1of1ForFork0_#t~mem28_Out68196668| |P0Thread1of1ForFork0_#t~ite29_Out68196668|) (= |P0Thread1of1ForFork0_#t~mem28_Out68196668| (select (select |#memory_int_In68196668| |~#x~0.base_In68196668|) |~#x~0.offset_In68196668|))))) InVars {P0Thread1of1ForFork0_#t~mem28=|P0Thread1of1ForFork0_#t~mem28_In68196668|, ~x$flush_delayed~0=~x$flush_delayed~0_In68196668, ~#x~0.offset=|~#x~0.offset_In68196668|, ~#x~0.base=|~#x~0.base_In68196668|, #memory_int=|#memory_int_In68196668|, ~x$mem_tmp~0=~x$mem_tmp~0_In68196668} OutVars{P0Thread1of1ForFork0_#t~mem28=|P0Thread1of1ForFork0_#t~mem28_Out68196668|, ~x$flush_delayed~0=~x$flush_delayed~0_In68196668, ~#x~0.offset=|~#x~0.offset_In68196668|, P0Thread1of1ForFork0_#t~ite29=|P0Thread1of1ForFork0_#t~ite29_Out68196668|, ~#x~0.base=|~#x~0.base_In68196668|, #memory_int=|#memory_int_In68196668|, ~x$mem_tmp~0=~x$mem_tmp~0_In68196668} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~mem28, P0Thread1of1ForFork0_#t~ite29] because there is no mapped edge [2019-12-07 17:46:32,054 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1117] [1117] L764-2-->P0EXIT: Formula: (and (= |v_#memory_int_248| (store |v_#memory_int_249| |v_~#x~0.base_160| (store (select |v_#memory_int_249| |v_~#x~0.base_160|) |v_~#x~0.offset_160| |v_P0Thread1of1ForFork0_#t~ite29_28|))) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_49 (+ v_~__unbuffered_cnt~0_50 1)) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= v_~x$flush_delayed~0_92 0)) InVars {~#x~0.offset=|v_~#x~0.offset_160|, P0Thread1of1ForFork0_#t~ite29=|v_P0Thread1of1ForFork0_#t~ite29_28|, #memory_int=|v_#memory_int_249|, ~#x~0.base=|v_~#x~0.base_160|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_50} OutVars{P0Thread1of1ForFork0_#t~mem28=|v_P0Thread1of1ForFork0_#t~mem28_17|, P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, ~x$flush_delayed~0=v_~x$flush_delayed~0_92, ~#x~0.offset=|v_~#x~0.offset_160|, P0Thread1of1ForFork0_#t~ite29=|v_P0Thread1of1ForFork0_#t~ite29_27|, #memory_int=|v_#memory_int_248|, ~#x~0.base=|v_~#x~0.base_160|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_49} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~mem28, P0Thread1of1ForFork0_#res.offset, ~x$flush_delayed~0, P0Thread1of1ForFork0_#t~ite29, #memory_int, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 17:46:32,054 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1103] [1103] L784-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= v_~x$r_buff1_thd2~0_28 |v_P1Thread1of1ForFork1_#t~ite36_22|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_40 1) v_~__unbuffered_cnt~0_39)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40, P1Thread1of1ForFork1_#t~ite36=|v_P1Thread1of1ForFork1_#t~ite36_22|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_28, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_39, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|, P1Thread1of1ForFork1_#t~ite36=|v_P1Thread1of1ForFork1_#t~ite36_21|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#res.base, P1Thread1of1ForFork1_#t~ite36] because there is no mapped edge [2019-12-07 17:46:32,055 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [984] [984] L846-->L848-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_118 256) 0) (= (mod v_~x$r_buff0_thd0~0_14 256) 0)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_118} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_118} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 17:46:32,055 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1098] [1098] L848-2-->L848-5: Formula: (let ((.cse0 (= (mod ~x$w_buff1_used~0_In1934817401 256) 0)) (.cse2 (= (mod ~x$r_buff1_thd0~0_In1934817401 256) 0)) (.cse1 (= |ULTIMATE.start_main_#t~ite76_Out1934817401| |ULTIMATE.start_main_#t~ite75_Out1934817401|))) (or (and (= ~x$w_buff1~0_In1934817401 |ULTIMATE.start_main_#t~ite75_Out1934817401|) (not .cse0) .cse1 (not .cse2) (= |ULTIMATE.start_main_#t~mem74_In1934817401| |ULTIMATE.start_main_#t~mem74_Out1934817401|)) (and (= |ULTIMATE.start_main_#t~mem74_Out1934817401| |ULTIMATE.start_main_#t~ite75_Out1934817401|) (= (select (select |#memory_int_In1934817401| |~#x~0.base_In1934817401|) |~#x~0.offset_In1934817401|) |ULTIMATE.start_main_#t~mem74_Out1934817401|) (or .cse0 .cse2) .cse1))) InVars {~#x~0.offset=|~#x~0.offset_In1934817401|, ULTIMATE.start_main_#t~mem74=|ULTIMATE.start_main_#t~mem74_In1934817401|, ~x$w_buff1~0=~x$w_buff1~0_In1934817401, ~#x~0.base=|~#x~0.base_In1934817401|, #memory_int=|#memory_int_In1934817401|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1934817401, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1934817401} OutVars{ULTIMATE.start_main_#t~mem74=|ULTIMATE.start_main_#t~mem74_Out1934817401|, ~#x~0.offset=|~#x~0.offset_In1934817401|, ~x$w_buff1~0=~x$w_buff1~0_In1934817401, ~#x~0.base=|~#x~0.base_In1934817401|, #memory_int=|#memory_int_In1934817401|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1934817401, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1934817401, ULTIMATE.start_main_#t~ite75=|ULTIMATE.start_main_#t~ite75_Out1934817401|, ULTIMATE.start_main_#t~ite76=|ULTIMATE.start_main_#t~ite76_Out1934817401|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem74, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~ite76] because there is no mapped edge [2019-12-07 17:46:32,055 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1080] [1080] L849-->L849-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In128583879 256))) (.cse1 (= (mod ~x$r_buff0_thd0~0_In128583879 256) 0))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite77_Out128583879|) (not .cse1)) (and (= ~x$w_buff0_used~0_In128583879 |ULTIMATE.start_main_#t~ite77_Out128583879|) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In128583879, ~x$w_buff0_used~0=~x$w_buff0_used~0_In128583879} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In128583879, ULTIMATE.start_main_#t~ite77=|ULTIMATE.start_main_#t~ite77_Out128583879|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In128583879} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite77] because there is no mapped edge [2019-12-07 17:46:32,056 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1082] [1082] L850-->L850-2: Formula: (let ((.cse2 (= (mod ~x$w_buff0_used~0_In-1540997010 256) 0)) (.cse3 (= (mod ~x$r_buff0_thd0~0_In-1540997010 256) 0)) (.cse1 (= 0 (mod ~x$r_buff1_thd0~0_In-1540997010 256))) (.cse0 (= (mod ~x$w_buff1_used~0_In-1540997010 256) 0))) (or (and (or .cse0 .cse1) (= ~x$w_buff1_used~0_In-1540997010 |ULTIMATE.start_main_#t~ite78_Out-1540997010|) (or .cse2 .cse3)) (and (= 0 |ULTIMATE.start_main_#t~ite78_Out-1540997010|) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1540997010, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1540997010, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1540997010, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1540997010} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1540997010, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1540997010, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1540997010, ULTIMATE.start_main_#t~ite78=|ULTIMATE.start_main_#t~ite78_Out-1540997010|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1540997010} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite78] because there is no mapped edge [2019-12-07 17:46:32,056 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1078] [1078] L851-->L852: Formula: (let ((.cse1 (= ~x$r_buff0_thd0~0_In1201078314 ~x$r_buff0_thd0~0_Out1201078314)) (.cse0 (= 0 (mod ~x$r_buff0_thd0~0_In1201078314 256))) (.cse2 (= (mod ~x$w_buff0_used~0_In1201078314 256) 0))) (or (and .cse0 .cse1) (and .cse2 .cse1) (and (not .cse0) (= 0 ~x$r_buff0_thd0~0_Out1201078314) (not .cse2)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1201078314, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1201078314} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_Out1201078314, ULTIMATE.start_main_#t~ite79=|ULTIMATE.start_main_#t~ite79_Out1201078314|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1201078314} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite79] because there is no mapped edge [2019-12-07 17:46:32,056 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1096] [1096] L852-->L856: Formula: (let ((.cse3 (= ~x$r_buff1_thd0~0_Out-1259108784 0)) (.cse1 (= (mod ~x$w_buff1_used~0_In-1259108784 256) 0)) (.cse5 (= (mod ~x$w_buff0_used~0_In-1259108784 256) 0)) (.cse0 (= 0 (mod ~x$r_buff1_thd0~0_In-1259108784 256))) (.cse2 (= |ULTIMATE.start_main_#t~nondet81_In-1259108784| ~weak$$choice1~0_Out-1259108784)) (.cse4 (= 0 (mod ~x$r_buff0_thd0~0_In-1259108784 256))) (.cse6 (= ~x$r_buff1_thd0~0_Out-1259108784 ~x$r_buff1_thd0~0_In-1259108784))) (or (and (not .cse0) (not .cse1) .cse2 .cse3) (and .cse2 .cse3 (not .cse4) (not .cse5)) (and .cse2 .cse4 .cse1 .cse6) (and .cse2 .cse1 .cse5 .cse6) (and .cse0 .cse2 .cse5 .cse6) (and .cse0 .cse2 .cse4 .cse6))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1259108784, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1259108784, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1259108784, ULTIMATE.start_main_#t~nondet81=|ULTIMATE.start_main_#t~nondet81_In-1259108784|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1259108784} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1259108784, ~weak$$choice1~0=~weak$$choice1~0_Out-1259108784, ULTIMATE.start_main_#t~ite80=|ULTIMATE.start_main_#t~ite80_Out-1259108784|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1259108784, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_Out-1259108784, ULTIMATE.start_main_#t~nondet81=|ULTIMATE.start_main_#t~nondet81_Out-1259108784|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1259108784} AuxVars[] AssignedVars[~weak$$choice1~0, ULTIMATE.start_main_#t~ite80, ~x$r_buff1_thd0~0, ULTIMATE.start_main_#t~nondet81] because there is no mapped edge [2019-12-07 17:46:32,057 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1069] [1069] L856-->L856-3: Formula: (let ((.cse0 (not (= (mod ~__unbuffered_p2_EAX$read_delayed~0_In-388216409 256) 0))) (.cse1 (= 0 (mod ~weak$$choice1~0_In-388216409 256)))) (or (and (= |ULTIMATE.start_main_#t~mem82_In-388216409| |ULTIMATE.start_main_#t~mem82_Out-388216409|) .cse0 .cse1 (= ~__unbuffered_p2_EAX~0_In-388216409 |ULTIMATE.start_main_#t~ite83_Out-388216409|)) (and .cse0 (not .cse1) (= |ULTIMATE.start_main_#t~mem82_Out-388216409| (select (select |#memory_int_In-388216409| ~__unbuffered_p2_EAX$read_delayed_var~0.base_In-388216409) ~__unbuffered_p2_EAX$read_delayed_var~0.offset_In-388216409)) (= |ULTIMATE.start_main_#t~mem82_Out-388216409| |ULTIMATE.start_main_#t~ite83_Out-388216409|)))) InVars {~weak$$choice1~0=~weak$$choice1~0_In-388216409, ~__unbuffered_p2_EAX$read_delayed_var~0.offset=~__unbuffered_p2_EAX$read_delayed_var~0.offset_In-388216409, ~__unbuffered_p2_EAX$read_delayed_var~0.base=~__unbuffered_p2_EAX$read_delayed_var~0.base_In-388216409, ULTIMATE.start_main_#t~mem82=|ULTIMATE.start_main_#t~mem82_In-388216409|, #memory_int=|#memory_int_In-388216409|, ~__unbuffered_p2_EAX~0=~__unbuffered_p2_EAX~0_In-388216409, ~__unbuffered_p2_EAX$read_delayed~0=~__unbuffered_p2_EAX$read_delayed~0_In-388216409} OutVars{ULTIMATE.start_main_#t~ite83=|ULTIMATE.start_main_#t~ite83_Out-388216409|, ~weak$$choice1~0=~weak$$choice1~0_In-388216409, ~__unbuffered_p2_EAX$read_delayed_var~0.offset=~__unbuffered_p2_EAX$read_delayed_var~0.offset_In-388216409, ULTIMATE.start_main_#t~mem82=|ULTIMATE.start_main_#t~mem82_Out-388216409|, ~__unbuffered_p2_EAX$read_delayed_var~0.base=~__unbuffered_p2_EAX$read_delayed_var~0.base_In-388216409, #memory_int=|#memory_int_In-388216409|, ~__unbuffered_p2_EAX~0=~__unbuffered_p2_EAX~0_In-388216409, ~__unbuffered_p2_EAX$read_delayed~0=~__unbuffered_p2_EAX$read_delayed~0_In-388216409} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite83, ULTIMATE.start_main_#t~mem82] because there is no mapped edge [2019-12-07 17:46:32,057 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1130] [1130] L856-3-->L5: Formula: (and (= (mod v_~main$tmp_guard1~0_21 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|) (let ((.cse3 (= v_~__unbuffered_p2_EBX~0_21 0)) (.cse1 (= 1 v_~__unbuffered_p2_EAX~0_46)) (.cse0 (= v_~main$tmp_guard1~0_21 1)) (.cse4 (= 0 v_~__unbuffered_p0_EAX~0_48)) (.cse2 (= |v_ULTIMATE.start_main_#t~ite83_36| v_~__unbuffered_p2_EAX~0_46))) (or (and .cse0 (not .cse1) .cse2) (and .cse0 (not .cse3) .cse2) (and (= v_~main$tmp_guard1~0_21 0) .cse3 .cse1 .cse4 .cse2) (and .cse0 (not .cse4) .cse2)))) InVars {~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_48, ULTIMATE.start_main_#t~ite83=|v_ULTIMATE.start_main_#t~ite83_36|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_21} OutVars{ULTIMATE.start_main_#t~ite84=|v_ULTIMATE.start_main_#t~ite84_33|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_48, ULTIMATE.start_main_#t~ite83=|v_ULTIMATE.start_main_#t~ite83_35|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_21, ULTIMATE.start_main_#t~mem82=|v_ULTIMATE.start_main_#t~mem82_27|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_46, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite84, ULTIMATE.start_main_#t~ite83, ULTIMATE.start___VERIFIER_assert_~expression, ULTIMATE.start_main_#t~mem82, ~main$tmp_guard1~0, ~__unbuffered_p2_EAX~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 17:46:32,057 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [1131] [1131] L5-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 17:46:32,119 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_b4a9cf03-0b0a-4e8f-b082-244f8da00a06/bin/uautomizer/witness.graphml [2019-12-07 17:46:32,119 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 17:46:32,120 INFO L168 Benchmark]: Toolchain (without parser) took 598358.44 ms. Allocated memory was 1.0 GB in the beginning and 7.5 GB in the end (delta: 6.4 GB). Free memory was 934.0 MB in the beginning and 3.0 GB in the end (delta: -2.1 GB). Peak memory consumption was 4.4 GB. Max. memory is 11.5 GB. [2019-12-07 17:46:32,120 INFO L168 Benchmark]: CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 17:46:32,120 INFO L168 Benchmark]: CACSL2BoogieTranslator took 405.12 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 93.3 MB). Free memory was 934.0 MB in the beginning and 1.1 GB in the end (delta: -120.3 MB). Peak memory consumption was 23.7 MB. Max. memory is 11.5 GB. [2019-12-07 17:46:32,120 INFO L168 Benchmark]: Boogie Procedure Inliner took 37.03 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 17:46:32,121 INFO L168 Benchmark]: Boogie Preprocessor took 34.06 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 17:46:32,121 INFO L168 Benchmark]: RCFGBuilder took 470.59 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 982.7 MB in the end (delta: 66.2 MB). Peak memory consumption was 66.2 MB. Max. memory is 11.5 GB. [2019-12-07 17:46:32,121 INFO L168 Benchmark]: TraceAbstraction took 597321.17 ms. Allocated memory was 1.1 GB in the beginning and 7.5 GB in the end (delta: 6.3 GB). Free memory was 982.7 MB in the beginning and 3.1 GB in the end (delta: -2.1 GB). Peak memory consumption was 4.2 GB. Max. memory is 11.5 GB. [2019-12-07 17:46:32,121 INFO L168 Benchmark]: Witness Printer took 85.59 ms. Allocated memory is still 7.5 GB. Free memory was 3.1 GB in the beginning and 3.0 GB in the end (delta: 91.1 MB). Peak memory consumption was 91.1 MB. Max. memory is 11.5 GB. [2019-12-07 17:46:32,122 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 405.12 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 93.3 MB). Free memory was 934.0 MB in the beginning and 1.1 GB in the end (delta: -120.3 MB). Peak memory consumption was 23.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 37.03 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 34.06 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 470.59 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 982.7 MB in the end (delta: 66.2 MB). Peak memory consumption was 66.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 597321.17 ms. Allocated memory was 1.1 GB in the beginning and 7.5 GB in the end (delta: 6.3 GB). Free memory was 982.7 MB in the beginning and 3.1 GB in the end (delta: -2.1 GB). Peak memory consumption was 4.2 GB. Max. memory is 11.5 GB. * Witness Printer took 85.59 ms. Allocated memory is still 7.5 GB. Free memory was 3.1 GB in the beginning and 3.0 GB in the end (delta: 91.1 MB). Peak memory consumption was 91.1 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 4.3s, 223 ProgramPointsBefore, 117 ProgramPointsAfterwards, 276 TransitionsBefore, 138 TransitionsAfterwards, 32976 CoEnabledTransitionPairs, 8 FixpointIterations, 50 TrivialSequentialCompositions, 34 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 62 ConcurrentYvCompositions, 36 ChoiceCompositions, 12209 VarBasedMoverChecksPositive, 278 VarBasedMoverChecksNegative, 32 SemBasedMoverChecksPositive, 347 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.0s, 0 MoverChecksTotal, 183707 CheckedPairsTotal, 146 TotalNumberOfCompositions - CounterExampleResult [Line: 5]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L838] FCALL, FORK 0 pthread_create(&t2464, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={5:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L840] FCALL, FORK 0 pthread_create(&t2465, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={5:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L842] FCALL, FORK 0 pthread_create(&t2466, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={5:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L794] 3 weak$$choice0 = __VERIFIER_nondet_bool() [L795] 3 weak$$choice2 = __VERIFIER_nondet_bool() [L796] 3 x$flush_delayed = weak$$choice2 [L797] EXPR 3 \read(x) [L797] 3 x$mem_tmp = x [L777] 2 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=3, weak$$choice1=0, weak$$choice2=1, x={5:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L780] 2 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=3, weak$$choice1=0, weak$$choice2=1, x={5:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L798] EXPR 3 !x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : x$w_buff1) [L798] EXPR 3 \read(x) [L798] EXPR 3 !x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : x$w_buff1) VAL [!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : x$w_buff1)=1, \read(x)=1, __unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=3, weak$$choice1=0, weak$$choice2=1, x={5:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L798] 3 x = !x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : x$w_buff1) [L781] 2 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L782] 2 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L799] EXPR 3 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : x$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=3, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : x$w_buff0))=0, x={5:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L799] 3 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : x$w_buff0)) [L800] EXPR 3 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff1 : x$w_buff1)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=3, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff1 : x$w_buff1))=0, x={5:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L800] 3 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff1 : x$w_buff1)) [L801] EXPR 3 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$w_buff0_used)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=3, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$w_buff0_used))=0, x={5:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L801] 3 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$w_buff0_used)) [L802] EXPR 3 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=3, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : (_Bool)0))=0, x={5:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L802] 3 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L804] EXPR 3 weak$$choice2 ? x$r_buff1_thd3 : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$r_buff1_thd3 : (x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=3, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$r_buff1_thd3 : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$r_buff1_thd3 : (x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : (_Bool)0))=0, x={5:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L804] 3 x$r_buff1_thd3 = weak$$choice2 ? x$r_buff1_thd3 : (!x$w_buff0_used || !x$r_buff0_thd3 && !x$w_buff1_used || !x$r_buff0_thd3 && !x$r_buff1_thd3 ? x$r_buff1_thd3 : (x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L805] 3 __unbuffered_p2_EAX$read_delayed = (_Bool)1 [L806] 3 __unbuffered_p2_EAX$read_delayed_var = &x [L807] EXPR 3 \read(x) [L807] 3 __unbuffered_p2_EAX = x [L808] 3 x = x$flush_delayed ? x$mem_tmp : x [L809] 3 x$flush_delayed = (_Bool)0 [L812] 3 __unbuffered_p2_EBX = y VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={5:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=3, weak$$choice1=0, weak$$choice2=1, x={5:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L747] 1 y = 1 [L752] 1 weak$$choice0 = __VERIFIER_nondet_bool() [L753] 1 weak$$choice2 = __VERIFIER_nondet_bool() [L754] 1 x$flush_delayed = weak$$choice2 [L755] EXPR 1 \read(x) [L755] 1 x$mem_tmp = x [L756] EXPR 1 !x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : x$w_buff1) [L756] EXPR 1 \read(x) [L756] EXPR 1 !x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : x$w_buff1) VAL [!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : x$w_buff1)=0, \read(x)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={5:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x={5:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L756] 1 x = !x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : x$w_buff1) [L757] EXPR 1 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : x$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={5:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : x$w_buff0))=0, x={5:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L815] 3 x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd3 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={5:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : x$w_buff0))=0, x={5:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L757] 1 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : x$w_buff0)) [L816] 3 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$w_buff0_used [L817] 3 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd3 || x$w_buff1_used && x$r_buff1_thd3 ? (_Bool)0 : x$w_buff1_used [L758] EXPR 1 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff1 : x$w_buff1)) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={5:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff1 : x$w_buff1))=0, x={5:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L758] 1 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff1 : x$w_buff1)) [L759] EXPR 1 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used)) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={5:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used))=0, x={5:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L759] 1 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used)) [L760] EXPR 1 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={5:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : (_Bool)0))=0, x={5:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L760] 1 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : (_Bool)0)) [L762] EXPR 1 weak$$choice2 ? x$r_buff1_thd1 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$r_buff1_thd1 : (x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={5:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? x$r_buff1_thd1 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$r_buff1_thd1 : (x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : (_Bool)0))=0, x={5:0}, x$flush_delayed=1, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L762] 1 x$r_buff1_thd1 = weak$$choice2 ? x$r_buff1_thd1 : (!x$w_buff0_used || !x$r_buff0_thd1 && !x$w_buff1_used || !x$r_buff0_thd1 && !x$r_buff1_thd1 ? x$r_buff1_thd1 : (x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : (_Bool)0)) [L763] EXPR 1 \read(x) [L763] 1 __unbuffered_p0_EAX = x [L844] 0 main$tmp_guard0 = __unbuffered_cnt == 3 VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={5:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x={5:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L848] 0 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L849] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L850] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 214 locations, 1 error locations. Result: UNSAFE, OverallTime: 597.1s, OverallIterations: 84, TraceHistogramMax: 1, AutomataDifference: 363.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 25378 SDtfs, 51249 SDslu, 302932 SDs, 0 SdLazy, 263153 SolverSat, 6175 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 201.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 4246 GetRequests, 250 SyntacticMatches, 134 SemanticMatches, 3862 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 56848 ImplicationChecksByTransitivity, 144.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=300418occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 81.7s AutomataMinimizationTime, 83 MinimizatonAttempts, 515979 StatesRemovedByMinimization, 75 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.2s SsaConstructionTime, 1.8s SatisfiabilityAnalysisTime, 47.1s InterpolantComputationTime, 5822 NumberOfCodeBlocks, 5822 NumberOfCodeBlocksAsserted, 84 NumberOfCheckSat, 5667 ConstructedInterpolants, 0 QuantifiedInterpolants, 7636750 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 83 InterpolantComputations, 83 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...