./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe029_power.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_35603829-dc64-461c-b156-ab08f21bc920/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_35603829-dc64-461c-b156-ab08f21bc920/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_35603829-dc64-461c-b156-ab08f21bc920/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_35603829-dc64-461c-b156-ab08f21bc920/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe029_power.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_35603829-dc64-461c-b156-ab08f21bc920/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_35603829-dc64-461c-b156-ab08f21bc920/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 71cd3df5157f425f115015ed72d90be02a963e5a .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:19:43,250 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:19:43,252 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:19:43,259 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:19:43,260 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:19:43,260 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:19:43,261 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:19:43,262 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:19:43,264 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:19:43,264 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:19:43,265 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:19:43,266 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:19:43,266 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:19:43,267 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:19:43,267 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:19:43,268 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:19:43,269 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:19:43,269 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:19:43,270 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:19:43,272 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:19:43,273 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:19:43,274 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:19:43,274 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:19:43,275 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:19:43,276 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:19:43,277 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:19:43,277 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:19:43,277 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:19:43,277 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:19:43,278 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:19:43,278 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:19:43,279 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:19:43,279 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:19:43,279 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:19:43,280 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:19:43,280 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:19:43,280 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:19:43,281 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:19:43,281 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:19:43,281 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:19:43,282 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:19:43,282 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_35603829-dc64-461c-b156-ab08f21bc920/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 18:19:43,291 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:19:43,292 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:19:43,292 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:19:43,292 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:19:43,293 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:19:43,293 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:19:43,293 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:19:43,293 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:19:43,293 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:19:43,293 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:19:43,293 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 18:19:43,293 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 18:19:43,294 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 18:19:43,294 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:19:43,294 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:19:43,294 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:19:43,294 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 18:19:43,294 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:19:43,294 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:19:43,294 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 18:19:43,295 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 18:19:43,295 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:19:43,295 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:19:43,295 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 18:19:43,295 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 18:19:43,295 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:19:43,295 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 18:19:43,295 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 18:19:43,296 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:19:43,296 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_35603829-dc64-461c-b156-ab08f21bc920/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 71cd3df5157f425f115015ed72d90be02a963e5a [2019-12-07 18:19:43,395 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:19:43,402 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:19:43,405 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:19:43,405 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:19:43,406 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:19:43,406 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_35603829-dc64-461c-b156-ab08f21bc920/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe029_power.opt.i [2019-12-07 18:19:43,442 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_35603829-dc64-461c-b156-ab08f21bc920/bin/uautomizer/data/e3ab6037f/7b550e2b34744359a5ac6accd4949b4d/FLAG1ca787122 [2019-12-07 18:19:43,929 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:19:43,930 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_35603829-dc64-461c-b156-ab08f21bc920/sv-benchmarks/c/pthread-wmm/safe029_power.opt.i [2019-12-07 18:19:43,942 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_35603829-dc64-461c-b156-ab08f21bc920/bin/uautomizer/data/e3ab6037f/7b550e2b34744359a5ac6accd4949b4d/FLAG1ca787122 [2019-12-07 18:19:43,951 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_35603829-dc64-461c-b156-ab08f21bc920/bin/uautomizer/data/e3ab6037f/7b550e2b34744359a5ac6accd4949b4d [2019-12-07 18:19:43,953 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:19:43,954 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:19:43,955 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:19:43,955 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:19:43,957 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:19:43,958 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:19:43" (1/1) ... [2019-12-07 18:19:43,959 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3482028c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:19:43, skipping insertion in model container [2019-12-07 18:19:43,960 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:19:43" (1/1) ... [2019-12-07 18:19:43,965 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:19:44,000 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:19:44,279 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:19:44,289 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:19:44,334 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:19:44,395 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:19:44,395 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:19:44 WrapperNode [2019-12-07 18:19:44,395 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:19:44,395 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:19:44,396 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:19:44,396 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:19:44,401 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:19:44" (1/1) ... [2019-12-07 18:19:44,414 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:19:44" (1/1) ... [2019-12-07 18:19:44,434 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:19:44,435 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:19:44,435 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:19:44,435 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:19:44,441 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:19:44" (1/1) ... [2019-12-07 18:19:44,441 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:19:44" (1/1) ... [2019-12-07 18:19:44,445 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:19:44" (1/1) ... [2019-12-07 18:19:44,445 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:19:44" (1/1) ... [2019-12-07 18:19:44,451 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:19:44" (1/1) ... [2019-12-07 18:19:44,453 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:19:44" (1/1) ... [2019-12-07 18:19:44,456 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:19:44" (1/1) ... [2019-12-07 18:19:44,459 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:19:44,459 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:19:44,459 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:19:44,459 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:19:44,460 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:19:44" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_35603829-dc64-461c-b156-ab08f21bc920/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:19:44,498 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 18:19:44,498 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 18:19:44,498 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 18:19:44,499 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 18:19:44,499 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 18:19:44,499 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 18:19:44,499 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 18:19:44,499 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 18:19:44,499 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 18:19:44,499 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:19:44,499 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:19:44,500 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 18:19:44,837 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:19:44,837 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 18:19:44,838 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:19:44 BoogieIcfgContainer [2019-12-07 18:19:44,838 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:19:44,838 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 18:19:44,839 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 18:19:44,840 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 18:19:44,840 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 06:19:43" (1/3) ... [2019-12-07 18:19:44,841 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@76dc9eda and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:19:44, skipping insertion in model container [2019-12-07 18:19:44,841 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:19:44" (2/3) ... [2019-12-07 18:19:44,841 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@76dc9eda and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:19:44, skipping insertion in model container [2019-12-07 18:19:44,841 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:19:44" (3/3) ... [2019-12-07 18:19:44,842 INFO L109 eAbstractionObserver]: Analyzing ICFG safe029_power.opt.i [2019-12-07 18:19:44,848 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 18:19:44,849 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 18:19:44,853 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 18:19:44,854 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 18:19:44,873 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,873 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,873 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,873 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,873 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,874 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,874 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,874 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,874 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,874 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,874 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,874 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,874 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,875 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,875 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,875 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,875 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,875 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,875 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,875 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,875 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,876 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,876 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,876 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,876 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,876 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,876 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,876 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,876 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,876 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,877 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,877 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,877 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,877 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,877 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,877 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,878 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,878 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,878 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,878 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,878 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,878 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,878 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,879 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,879 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,879 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,879 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,879 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,879 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,879 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,879 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,879 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,880 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,880 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,880 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,880 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,880 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,880 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,880 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,880 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,881 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,881 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,881 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,881 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:19:44,891 INFO L249 AbstractCegarLoop]: Starting to check reachability of 5 error locations. [2019-12-07 18:19:44,904 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 18:19:44,904 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 18:19:44,904 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 18:19:44,904 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:19:44,904 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:19:44,904 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 18:19:44,904 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:19:44,904 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 18:19:44,914 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 145 places, 179 transitions [2019-12-07 18:19:44,916 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 145 places, 179 transitions [2019-12-07 18:19:44,961 INFO L134 PetriNetUnfolder]: 41/177 cut-off events. [2019-12-07 18:19:44,961 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:19:44,969 INFO L76 FinitePrefix]: Finished finitePrefix Result has 184 conditions, 177 events. 41/177 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 462 event pairs. 6/140 useless extension candidates. Maximal degree in co-relation 150. Up to 2 conditions per place. [2019-12-07 18:19:44,980 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 145 places, 179 transitions [2019-12-07 18:19:45,002 INFO L134 PetriNetUnfolder]: 41/177 cut-off events. [2019-12-07 18:19:45,002 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:19:45,005 INFO L76 FinitePrefix]: Finished finitePrefix Result has 184 conditions, 177 events. 41/177 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 462 event pairs. 6/140 useless extension candidates. Maximal degree in co-relation 150. Up to 2 conditions per place. [2019-12-07 18:19:45,013 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 10378 [2019-12-07 18:19:45,014 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 18:19:47,443 WARN L192 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 77 [2019-12-07 18:19:47,517 INFO L206 etLargeBlockEncoding]: Checked pairs total: 47380 [2019-12-07 18:19:47,518 INFO L214 etLargeBlockEncoding]: Total number of compositions: 96 [2019-12-07 18:19:47,520 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 79 places, 90 transitions [2019-12-07 18:19:47,840 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 8608 states. [2019-12-07 18:19:47,842 INFO L276 IsEmpty]: Start isEmpty. Operand 8608 states. [2019-12-07 18:19:47,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-12-07 18:19:47,846 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:47,846 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-12-07 18:19:47,846 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:47,850 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:47,850 INFO L82 PathProgramCache]: Analyzing trace with hash 689103523, now seen corresponding path program 1 times [2019-12-07 18:19:47,856 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:47,856 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [78280666] [2019-12-07 18:19:47,856 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:47,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:47,995 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:47,996 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [78280666] [2019-12-07 18:19:47,996 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:47,997 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:19:47,997 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73689624] [2019-12-07 18:19:48,000 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:19:48,000 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:48,010 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:19:48,010 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:48,012 INFO L87 Difference]: Start difference. First operand 8608 states. Second operand 3 states. [2019-12-07 18:19:48,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:48,201 INFO L93 Difference]: Finished difference Result 8560 states and 27962 transitions. [2019-12-07 18:19:48,202 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:19:48,203 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 5 [2019-12-07 18:19:48,203 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:48,262 INFO L225 Difference]: With dead ends: 8560 [2019-12-07 18:19:48,262 INFO L226 Difference]: Without dead ends: 8391 [2019-12-07 18:19:48,263 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:48,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8391 states. [2019-12-07 18:19:48,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8391 to 8391. [2019-12-07 18:19:48,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8391 states. [2019-12-07 18:19:48,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8391 states to 8391 states and 27442 transitions. [2019-12-07 18:19:48,531 INFO L78 Accepts]: Start accepts. Automaton has 8391 states and 27442 transitions. Word has length 5 [2019-12-07 18:19:48,531 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:48,531 INFO L462 AbstractCegarLoop]: Abstraction has 8391 states and 27442 transitions. [2019-12-07 18:19:48,531 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:19:48,531 INFO L276 IsEmpty]: Start isEmpty. Operand 8391 states and 27442 transitions. [2019-12-07 18:19:48,533 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 18:19:48,533 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:48,533 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:48,533 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:48,534 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:48,534 INFO L82 PathProgramCache]: Analyzing trace with hash -1296433146, now seen corresponding path program 1 times [2019-12-07 18:19:48,534 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:48,534 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082954443] [2019-12-07 18:19:48,534 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:48,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:48,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:48,600 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2082954443] [2019-12-07 18:19:48,600 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:48,600 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:19:48,601 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [195644259] [2019-12-07 18:19:48,602 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:19:48,602 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:48,602 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:19:48,602 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:19:48,602 INFO L87 Difference]: Start difference. First operand 8391 states and 27442 transitions. Second operand 4 states. [2019-12-07 18:19:48,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:48,885 INFO L93 Difference]: Finished difference Result 13399 states and 41962 transitions. [2019-12-07 18:19:48,886 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:19:48,886 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 18:19:48,886 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:48,941 INFO L225 Difference]: With dead ends: 13399 [2019-12-07 18:19:48,941 INFO L226 Difference]: Without dead ends: 13392 [2019-12-07 18:19:48,941 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:49,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13392 states. [2019-12-07 18:19:49,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13392 to 11787. [2019-12-07 18:19:49,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11787 states. [2019-12-07 18:19:49,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11787 states to 11787 states and 37494 transitions. [2019-12-07 18:19:49,267 INFO L78 Accepts]: Start accepts. Automaton has 11787 states and 37494 transitions. Word has length 11 [2019-12-07 18:19:49,267 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:49,267 INFO L462 AbstractCegarLoop]: Abstraction has 11787 states and 37494 transitions. [2019-12-07 18:19:49,267 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:19:49,267 INFO L276 IsEmpty]: Start isEmpty. Operand 11787 states and 37494 transitions. [2019-12-07 18:19:49,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 18:19:49,270 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:49,270 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:49,270 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:49,270 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:49,271 INFO L82 PathProgramCache]: Analyzing trace with hash 825675890, now seen corresponding path program 1 times [2019-12-07 18:19:49,271 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:49,271 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434228373] [2019-12-07 18:19:49,271 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:49,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:49,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:49,326 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [434228373] [2019-12-07 18:19:49,326 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:49,326 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:19:49,326 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1496003365] [2019-12-07 18:19:49,326 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:19:49,327 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:49,327 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:19:49,327 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:19:49,327 INFO L87 Difference]: Start difference. First operand 11787 states and 37494 transitions. Second operand 4 states. [2019-12-07 18:19:49,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:49,527 INFO L93 Difference]: Finished difference Result 14846 states and 46774 transitions. [2019-12-07 18:19:49,527 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:19:49,527 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 18:19:49,527 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:49,558 INFO L225 Difference]: With dead ends: 14846 [2019-12-07 18:19:49,558 INFO L226 Difference]: Without dead ends: 14846 [2019-12-07 18:19:49,558 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:49,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14846 states. [2019-12-07 18:19:49,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14846 to 13070. [2019-12-07 18:19:49,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13070 states. [2019-12-07 18:19:49,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13070 states to 13070 states and 41519 transitions. [2019-12-07 18:19:49,819 INFO L78 Accepts]: Start accepts. Automaton has 13070 states and 41519 transitions. Word has length 11 [2019-12-07 18:19:49,819 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:49,819 INFO L462 AbstractCegarLoop]: Abstraction has 13070 states and 41519 transitions. [2019-12-07 18:19:49,819 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:19:49,819 INFO L276 IsEmpty]: Start isEmpty. Operand 13070 states and 41519 transitions. [2019-12-07 18:19:49,822 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2019-12-07 18:19:49,822 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:49,823 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:49,823 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:49,823 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:49,823 INFO L82 PathProgramCache]: Analyzing trace with hash 727521173, now seen corresponding path program 1 times [2019-12-07 18:19:49,823 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:49,823 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2111928175] [2019-12-07 18:19:49,823 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:49,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:49,890 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:49,890 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2111928175] [2019-12-07 18:19:49,890 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:49,890 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:19:49,890 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1854633278] [2019-12-07 18:19:49,891 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:19:49,891 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:49,891 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:19:49,891 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:49,892 INFO L87 Difference]: Start difference. First operand 13070 states and 41519 transitions. Second operand 5 states. [2019-12-07 18:19:50,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:50,183 INFO L93 Difference]: Finished difference Result 17840 states and 55421 transitions. [2019-12-07 18:19:50,183 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:19:50,184 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2019-12-07 18:19:50,184 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:50,250 INFO L225 Difference]: With dead ends: 17840 [2019-12-07 18:19:50,250 INFO L226 Difference]: Without dead ends: 17833 [2019-12-07 18:19:50,250 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:19:50,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17833 states. [2019-12-07 18:19:50,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17833 to 13112. [2019-12-07 18:19:50,449 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13112 states. [2019-12-07 18:19:50,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13112 states to 13112 states and 41511 transitions. [2019-12-07 18:19:50,469 INFO L78 Accepts]: Start accepts. Automaton has 13112 states and 41511 transitions. Word has length 17 [2019-12-07 18:19:50,469 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:50,469 INFO L462 AbstractCegarLoop]: Abstraction has 13112 states and 41511 transitions. [2019-12-07 18:19:50,469 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:19:50,469 INFO L276 IsEmpty]: Start isEmpty. Operand 13112 states and 41511 transitions. [2019-12-07 18:19:50,477 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 18:19:50,477 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:50,478 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:50,478 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:50,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:50,478 INFO L82 PathProgramCache]: Analyzing trace with hash -569311522, now seen corresponding path program 1 times [2019-12-07 18:19:50,478 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:50,478 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [166841262] [2019-12-07 18:19:50,478 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:50,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:50,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:50,505 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [166841262] [2019-12-07 18:19:50,506 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:50,506 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:19:50,506 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1764514647] [2019-12-07 18:19:50,506 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:19:50,506 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:50,506 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:19:50,506 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:50,506 INFO L87 Difference]: Start difference. First operand 13112 states and 41511 transitions. Second operand 3 states. [2019-12-07 18:19:50,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:50,574 INFO L93 Difference]: Finished difference Result 15933 states and 49812 transitions. [2019-12-07 18:19:50,575 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:19:50,575 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-12-07 18:19:50,575 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:50,594 INFO L225 Difference]: With dead ends: 15933 [2019-12-07 18:19:50,594 INFO L226 Difference]: Without dead ends: 15933 [2019-12-07 18:19:50,594 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:50,661 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15933 states. [2019-12-07 18:19:50,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15933 to 14126. [2019-12-07 18:19:50,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14126 states. [2019-12-07 18:19:50,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14126 states to 14126 states and 44593 transitions. [2019-12-07 18:19:50,881 INFO L78 Accepts]: Start accepts. Automaton has 14126 states and 44593 transitions. Word has length 25 [2019-12-07 18:19:50,882 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:50,882 INFO L462 AbstractCegarLoop]: Abstraction has 14126 states and 44593 transitions. [2019-12-07 18:19:50,882 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:19:50,882 INFO L276 IsEmpty]: Start isEmpty. Operand 14126 states and 44593 transitions. [2019-12-07 18:19:50,890 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 18:19:50,890 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:50,890 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:50,890 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:50,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:50,891 INFO L82 PathProgramCache]: Analyzing trace with hash -569496623, now seen corresponding path program 1 times [2019-12-07 18:19:50,891 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:50,891 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [284808926] [2019-12-07 18:19:50,891 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:50,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:50,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:50,935 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [284808926] [2019-12-07 18:19:50,936 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:50,936 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:19:50,936 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1162241759] [2019-12-07 18:19:50,936 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:19:50,936 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:50,936 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:19:50,936 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:19:50,936 INFO L87 Difference]: Start difference. First operand 14126 states and 44593 transitions. Second operand 4 states. [2019-12-07 18:19:50,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:50,955 INFO L93 Difference]: Finished difference Result 2310 states and 5267 transitions. [2019-12-07 18:19:50,956 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:19:50,956 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 25 [2019-12-07 18:19:50,956 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:50,957 INFO L225 Difference]: With dead ends: 2310 [2019-12-07 18:19:50,957 INFO L226 Difference]: Without dead ends: 2024 [2019-12-07 18:19:50,957 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:50,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2024 states. [2019-12-07 18:19:50,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2024 to 2024. [2019-12-07 18:19:50,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2024 states. [2019-12-07 18:19:50,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2024 states to 2024 states and 4476 transitions. [2019-12-07 18:19:50,974 INFO L78 Accepts]: Start accepts. Automaton has 2024 states and 4476 transitions. Word has length 25 [2019-12-07 18:19:50,975 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:50,975 INFO L462 AbstractCegarLoop]: Abstraction has 2024 states and 4476 transitions. [2019-12-07 18:19:50,975 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:19:50,975 INFO L276 IsEmpty]: Start isEmpty. Operand 2024 states and 4476 transitions. [2019-12-07 18:19:50,976 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 18:19:50,976 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:50,977 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:50,977 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:50,977 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:50,977 INFO L82 PathProgramCache]: Analyzing trace with hash 355873678, now seen corresponding path program 1 times [2019-12-07 18:19:50,977 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:50,977 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049404649] [2019-12-07 18:19:50,977 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:51,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:51,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:51,058 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2049404649] [2019-12-07 18:19:51,058 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:51,058 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:19:51,058 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [700493373] [2019-12-07 18:19:51,059 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:19:51,059 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:51,059 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:19:51,059 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:51,059 INFO L87 Difference]: Start difference. First operand 2024 states and 4476 transitions. Second operand 5 states. [2019-12-07 18:19:51,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:51,090 INFO L93 Difference]: Finished difference Result 426 states and 776 transitions. [2019-12-07 18:19:51,090 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:19:51,090 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 37 [2019-12-07 18:19:51,091 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:51,091 INFO L225 Difference]: With dead ends: 426 [2019-12-07 18:19:51,091 INFO L226 Difference]: Without dead ends: 380 [2019-12-07 18:19:51,091 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:19:51,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 380 states. [2019-12-07 18:19:51,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 380 to 345. [2019-12-07 18:19:51,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 345 states. [2019-12-07 18:19:51,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 345 states to 345 states and 621 transitions. [2019-12-07 18:19:51,094 INFO L78 Accepts]: Start accepts. Automaton has 345 states and 621 transitions. Word has length 37 [2019-12-07 18:19:51,094 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:51,095 INFO L462 AbstractCegarLoop]: Abstraction has 345 states and 621 transitions. [2019-12-07 18:19:51,095 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:19:51,095 INFO L276 IsEmpty]: Start isEmpty. Operand 345 states and 621 transitions. [2019-12-07 18:19:51,096 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-12-07 18:19:51,096 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:51,096 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:51,096 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:51,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:51,096 INFO L82 PathProgramCache]: Analyzing trace with hash -1678296005, now seen corresponding path program 1 times [2019-12-07 18:19:51,097 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:51,097 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847281222] [2019-12-07 18:19:51,097 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:51,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:51,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:51,178 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1847281222] [2019-12-07 18:19:51,178 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:51,178 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:19:51,179 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [903800457] [2019-12-07 18:19:51,179 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:19:51,179 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:51,179 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:19:51,180 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:51,180 INFO L87 Difference]: Start difference. First operand 345 states and 621 transitions. Second operand 5 states. [2019-12-07 18:19:51,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:51,302 INFO L93 Difference]: Finished difference Result 476 states and 857 transitions. [2019-12-07 18:19:51,303 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:19:51,303 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 52 [2019-12-07 18:19:51,303 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:51,303 INFO L225 Difference]: With dead ends: 476 [2019-12-07 18:19:51,304 INFO L226 Difference]: Without dead ends: 476 [2019-12-07 18:19:51,304 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:19:51,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 476 states. [2019-12-07 18:19:51,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 476 to 435. [2019-12-07 18:19:51,307 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 435 states. [2019-12-07 18:19:51,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 785 transitions. [2019-12-07 18:19:51,307 INFO L78 Accepts]: Start accepts. Automaton has 435 states and 785 transitions. Word has length 52 [2019-12-07 18:19:51,307 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:51,307 INFO L462 AbstractCegarLoop]: Abstraction has 435 states and 785 transitions. [2019-12-07 18:19:51,307 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:19:51,307 INFO L276 IsEmpty]: Start isEmpty. Operand 435 states and 785 transitions. [2019-12-07 18:19:51,308 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-12-07 18:19:51,308 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:51,308 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:51,308 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:51,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:51,308 INFO L82 PathProgramCache]: Analyzing trace with hash -856791897, now seen corresponding path program 2 times [2019-12-07 18:19:51,309 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:51,309 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539450266] [2019-12-07 18:19:51,309 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:51,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:51,371 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:51,371 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1539450266] [2019-12-07 18:19:51,372 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:51,372 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:19:51,372 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1376414529] [2019-12-07 18:19:51,372 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:19:51,372 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:51,372 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:19:51,372 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:19:51,372 INFO L87 Difference]: Start difference. First operand 435 states and 785 transitions. Second operand 6 states. [2019-12-07 18:19:51,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:51,615 INFO L93 Difference]: Finished difference Result 661 states and 1197 transitions. [2019-12-07 18:19:51,615 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:19:51,615 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 52 [2019-12-07 18:19:51,615 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:51,616 INFO L225 Difference]: With dead ends: 661 [2019-12-07 18:19:51,616 INFO L226 Difference]: Without dead ends: 661 [2019-12-07 18:19:51,616 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:19:51,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 661 states. [2019-12-07 18:19:51,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 661 to 480. [2019-12-07 18:19:51,620 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 480 states. [2019-12-07 18:19:51,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 875 transitions. [2019-12-07 18:19:51,621 INFO L78 Accepts]: Start accepts. Automaton has 480 states and 875 transitions. Word has length 52 [2019-12-07 18:19:51,621 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:51,621 INFO L462 AbstractCegarLoop]: Abstraction has 480 states and 875 transitions. [2019-12-07 18:19:51,621 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:19:51,621 INFO L276 IsEmpty]: Start isEmpty. Operand 480 states and 875 transitions. [2019-12-07 18:19:51,622 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-12-07 18:19:51,622 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:51,622 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:51,622 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:51,622 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:51,622 INFO L82 PathProgramCache]: Analyzing trace with hash 1692114105, now seen corresponding path program 3 times [2019-12-07 18:19:51,622 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:51,622 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [693395699] [2019-12-07 18:19:51,622 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:51,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:51,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:51,687 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [693395699] [2019-12-07 18:19:51,687 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:51,687 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:19:51,687 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [83747220] [2019-12-07 18:19:51,688 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:19:51,688 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:51,688 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:19:51,688 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:19:51,688 INFO L87 Difference]: Start difference. First operand 480 states and 875 transitions. Second operand 6 states. [2019-12-07 18:19:51,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:51,884 INFO L93 Difference]: Finished difference Result 682 states and 1232 transitions. [2019-12-07 18:19:51,884 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 18:19:51,884 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 52 [2019-12-07 18:19:51,884 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:51,885 INFO L225 Difference]: With dead ends: 682 [2019-12-07 18:19:51,885 INFO L226 Difference]: Without dead ends: 682 [2019-12-07 18:19:51,885 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 5 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:19:51,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 682 states. [2019-12-07 18:19:51,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 682 to 514. [2019-12-07 18:19:51,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 514 states. [2019-12-07 18:19:51,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 514 states to 514 states and 938 transitions. [2019-12-07 18:19:51,889 INFO L78 Accepts]: Start accepts. Automaton has 514 states and 938 transitions. Word has length 52 [2019-12-07 18:19:51,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:51,889 INFO L462 AbstractCegarLoop]: Abstraction has 514 states and 938 transitions. [2019-12-07 18:19:51,890 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:19:51,890 INFO L276 IsEmpty]: Start isEmpty. Operand 514 states and 938 transitions. [2019-12-07 18:19:51,890 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-12-07 18:19:51,890 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:51,890 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:51,891 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:51,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:51,891 INFO L82 PathProgramCache]: Analyzing trace with hash -1537444781, now seen corresponding path program 4 times [2019-12-07 18:19:51,891 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:51,891 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1926229452] [2019-12-07 18:19:51,891 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:51,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:51,963 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:51,964 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1926229452] [2019-12-07 18:19:51,964 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:51,964 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 18:19:51,964 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [835524029] [2019-12-07 18:19:51,964 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:19:51,964 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:51,964 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:19:51,965 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:19:51,965 INFO L87 Difference]: Start difference. First operand 514 states and 938 transitions. Second operand 7 states. [2019-12-07 18:19:52,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:52,198 INFO L93 Difference]: Finished difference Result 770 states and 1392 transitions. [2019-12-07 18:19:52,199 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 18:19:52,199 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 52 [2019-12-07 18:19:52,199 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:52,200 INFO L225 Difference]: With dead ends: 770 [2019-12-07 18:19:52,200 INFO L226 Difference]: Without dead ends: 770 [2019-12-07 18:19:52,200 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 6 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:19:52,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 770 states. [2019-12-07 18:19:52,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 770 to 500. [2019-12-07 18:19:52,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 500 states. [2019-12-07 18:19:52,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 500 states and 912 transitions. [2019-12-07 18:19:52,206 INFO L78 Accepts]: Start accepts. Automaton has 500 states and 912 transitions. Word has length 52 [2019-12-07 18:19:52,207 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:52,207 INFO L462 AbstractCegarLoop]: Abstraction has 500 states and 912 transitions. [2019-12-07 18:19:52,207 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:19:52,207 INFO L276 IsEmpty]: Start isEmpty. Operand 500 states and 912 transitions. [2019-12-07 18:19:52,208 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-12-07 18:19:52,208 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:52,208 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:52,208 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:52,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:52,208 INFO L82 PathProgramCache]: Analyzing trace with hash 1548250017, now seen corresponding path program 1 times [2019-12-07 18:19:52,209 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:52,209 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [715097905] [2019-12-07 18:19:52,209 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:52,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:52,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:52,344 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [715097905] [2019-12-07 18:19:52,344 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:52,344 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:19:52,344 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1788905776] [2019-12-07 18:19:52,345 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 18:19:52,345 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:52,345 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 18:19:52,345 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:19:52,345 INFO L87 Difference]: Start difference. First operand 500 states and 912 transitions. Second operand 9 states. [2019-12-07 18:19:52,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:52,652 INFO L93 Difference]: Finished difference Result 834 states and 1469 transitions. [2019-12-07 18:19:52,652 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 18:19:52,652 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 53 [2019-12-07 18:19:52,652 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:52,653 INFO L225 Difference]: With dead ends: 834 [2019-12-07 18:19:52,653 INFO L226 Difference]: Without dead ends: 834 [2019-12-07 18:19:52,653 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=71, Invalid=169, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:19:52,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 834 states. [2019-12-07 18:19:52,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 834 to 454. [2019-12-07 18:19:52,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. [2019-12-07 18:19:52,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 809 transitions. [2019-12-07 18:19:52,657 INFO L78 Accepts]: Start accepts. Automaton has 454 states and 809 transitions. Word has length 53 [2019-12-07 18:19:52,657 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:52,657 INFO L462 AbstractCegarLoop]: Abstraction has 454 states and 809 transitions. [2019-12-07 18:19:52,657 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 18:19:52,657 INFO L276 IsEmpty]: Start isEmpty. Operand 454 states and 809 transitions. [2019-12-07 18:19:52,658 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-12-07 18:19:52,658 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:52,658 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:52,658 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:52,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:52,658 INFO L82 PathProgramCache]: Analyzing trace with hash -1975941905, now seen corresponding path program 2 times [2019-12-07 18:19:52,659 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:52,659 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409524061] [2019-12-07 18:19:52,659 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:52,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:52,708 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:52,708 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [409524061] [2019-12-07 18:19:52,709 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:52,709 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:19:52,709 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2060597911] [2019-12-07 18:19:52,709 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:19:52,709 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:52,710 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:19:52,710 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:52,710 INFO L87 Difference]: Start difference. First operand 454 states and 809 transitions. Second operand 3 states. [2019-12-07 18:19:52,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:52,742 INFO L93 Difference]: Finished difference Result 453 states and 807 transitions. [2019-12-07 18:19:52,742 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:19:52,742 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 53 [2019-12-07 18:19:52,742 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:52,743 INFO L225 Difference]: With dead ends: 453 [2019-12-07 18:19:52,743 INFO L226 Difference]: Without dead ends: 453 [2019-12-07 18:19:52,743 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:52,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 453 states. [2019-12-07 18:19:52,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 453 to 350. [2019-12-07 18:19:52,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 350 states. [2019-12-07 18:19:52,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 350 states to 350 states and 614 transitions. [2019-12-07 18:19:52,747 INFO L78 Accepts]: Start accepts. Automaton has 350 states and 614 transitions. Word has length 53 [2019-12-07 18:19:52,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:52,748 INFO L462 AbstractCegarLoop]: Abstraction has 350 states and 614 transitions. [2019-12-07 18:19:52,748 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:19:52,748 INFO L276 IsEmpty]: Start isEmpty. Operand 350 states and 614 transitions. [2019-12-07 18:19:52,748 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-12-07 18:19:52,749 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:52,749 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:52,749 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:52,749 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:52,749 INFO L82 PathProgramCache]: Analyzing trace with hash 768058421, now seen corresponding path program 1 times [2019-12-07 18:19:52,749 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:52,749 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243791982] [2019-12-07 18:19:52,750 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:52,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:52,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:52,784 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [243791982] [2019-12-07 18:19:52,784 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:52,784 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:19:52,784 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1570933348] [2019-12-07 18:19:52,785 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:19:52,785 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:52,785 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:19:52,785 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:52,785 INFO L87 Difference]: Start difference. First operand 350 states and 614 transitions. Second operand 3 states. [2019-12-07 18:19:52,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:52,796 INFO L93 Difference]: Finished difference Result 344 states and 597 transitions. [2019-12-07 18:19:52,796 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:19:52,796 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 53 [2019-12-07 18:19:52,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:52,797 INFO L225 Difference]: With dead ends: 344 [2019-12-07 18:19:52,797 INFO L226 Difference]: Without dead ends: 344 [2019-12-07 18:19:52,797 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:19:52,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 344 states. [2019-12-07 18:19:52,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 344 to 344. [2019-12-07 18:19:52,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 344 states. [2019-12-07 18:19:52,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 344 states to 344 states and 597 transitions. [2019-12-07 18:19:52,802 INFO L78 Accepts]: Start accepts. Automaton has 344 states and 597 transitions. Word has length 53 [2019-12-07 18:19:52,803 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:52,803 INFO L462 AbstractCegarLoop]: Abstraction has 344 states and 597 transitions. [2019-12-07 18:19:52,803 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:19:52,803 INFO L276 IsEmpty]: Start isEmpty. Operand 344 states and 597 transitions. [2019-12-07 18:19:52,804 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-12-07 18:19:52,804 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:52,804 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:52,804 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:52,804 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:52,804 INFO L82 PathProgramCache]: Analyzing trace with hash 1826767497, now seen corresponding path program 1 times [2019-12-07 18:19:52,805 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:52,805 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [61168677] [2019-12-07 18:19:52,805 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:52,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:52,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:52,904 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [61168677] [2019-12-07 18:19:52,904 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:52,904 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:19:52,904 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [480821493] [2019-12-07 18:19:52,905 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:19:52,905 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:52,905 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:19:52,905 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:19:52,905 INFO L87 Difference]: Start difference. First operand 344 states and 597 transitions. Second operand 5 states. [2019-12-07 18:19:52,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:52,933 INFO L93 Difference]: Finished difference Result 524 states and 906 transitions. [2019-12-07 18:19:52,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:19:52,933 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 54 [2019-12-07 18:19:52,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:52,934 INFO L225 Difference]: With dead ends: 524 [2019-12-07 18:19:52,934 INFO L226 Difference]: Without dead ends: 197 [2019-12-07 18:19:52,934 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:19:52,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states. [2019-12-07 18:19:52,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 197. [2019-12-07 18:19:52,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 197 states. [2019-12-07 18:19:52,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 335 transitions. [2019-12-07 18:19:52,936 INFO L78 Accepts]: Start accepts. Automaton has 197 states and 335 transitions. Word has length 54 [2019-12-07 18:19:52,936 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:52,936 INFO L462 AbstractCegarLoop]: Abstraction has 197 states and 335 transitions. [2019-12-07 18:19:52,936 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:19:52,936 INFO L276 IsEmpty]: Start isEmpty. Operand 197 states and 335 transitions. [2019-12-07 18:19:52,936 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-12-07 18:19:52,937 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:52,937 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:52,937 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:52,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:52,937 INFO L82 PathProgramCache]: Analyzing trace with hash 584180705, now seen corresponding path program 2 times [2019-12-07 18:19:52,937 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:52,937 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [611973427] [2019-12-07 18:19:52,937 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:52,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:53,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:53,120 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [611973427] [2019-12-07 18:19:53,120 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:53,120 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 18:19:53,120 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [991776638] [2019-12-07 18:19:53,121 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 18:19:53,121 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:53,121 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 18:19:53,121 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=149, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:19:53,121 INFO L87 Difference]: Start difference. First operand 197 states and 335 transitions. Second operand 14 states. [2019-12-07 18:19:53,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:53,448 INFO L93 Difference]: Finished difference Result 355 states and 594 transitions. [2019-12-07 18:19:53,448 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 18:19:53,448 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 54 [2019-12-07 18:19:53,448 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:53,448 INFO L225 Difference]: With dead ends: 355 [2019-12-07 18:19:53,448 INFO L226 Difference]: Without dead ends: 323 [2019-12-07 18:19:53,449 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 75 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=100, Invalid=452, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:19:53,449 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 323 states. [2019-12-07 18:19:53,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 293. [2019-12-07 18:19:53,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 293 states. [2019-12-07 18:19:53,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 293 states to 293 states and 499 transitions. [2019-12-07 18:19:53,451 INFO L78 Accepts]: Start accepts. Automaton has 293 states and 499 transitions. Word has length 54 [2019-12-07 18:19:53,451 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:53,451 INFO L462 AbstractCegarLoop]: Abstraction has 293 states and 499 transitions. [2019-12-07 18:19:53,451 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 18:19:53,451 INFO L276 IsEmpty]: Start isEmpty. Operand 293 states and 499 transitions. [2019-12-07 18:19:53,452 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-12-07 18:19:53,452 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:53,452 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:53,452 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:53,452 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:53,452 INFO L82 PathProgramCache]: Analyzing trace with hash 1973947121, now seen corresponding path program 3 times [2019-12-07 18:19:53,452 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:53,453 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1940234597] [2019-12-07 18:19:53,453 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:53,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:53,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:53,618 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1940234597] [2019-12-07 18:19:53,618 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:53,618 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 18:19:53,618 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [593434104] [2019-12-07 18:19:53,618 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 18:19:53,618 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:53,618 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 18:19:53,619 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:19:53,619 INFO L87 Difference]: Start difference. First operand 293 states and 499 transitions. Second operand 14 states. [2019-12-07 18:19:53,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:53,921 INFO L93 Difference]: Finished difference Result 411 states and 680 transitions. [2019-12-07 18:19:53,921 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 18:19:53,921 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 54 [2019-12-07 18:19:53,921 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:53,922 INFO L225 Difference]: With dead ends: 411 [2019-12-07 18:19:53,922 INFO L226 Difference]: Without dead ends: 379 [2019-12-07 18:19:53,922 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 81 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=91, Invalid=461, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:19:53,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 379 states. [2019-12-07 18:19:53,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 379 to 297. [2019-12-07 18:19:53,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 297 states. [2019-12-07 18:19:53,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 297 states to 297 states and 506 transitions. [2019-12-07 18:19:53,925 INFO L78 Accepts]: Start accepts. Automaton has 297 states and 506 transitions. Word has length 54 [2019-12-07 18:19:53,925 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:53,925 INFO L462 AbstractCegarLoop]: Abstraction has 297 states and 506 transitions. [2019-12-07 18:19:53,925 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 18:19:53,925 INFO L276 IsEmpty]: Start isEmpty. Operand 297 states and 506 transitions. [2019-12-07 18:19:53,925 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-12-07 18:19:53,925 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:53,925 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:53,926 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:53,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:53,926 INFO L82 PathProgramCache]: Analyzing trace with hash -1111282689, now seen corresponding path program 4 times [2019-12-07 18:19:53,926 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:53,926 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [348435328] [2019-12-07 18:19:53,926 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:53,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:19:54,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:19:54,084 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [348435328] [2019-12-07 18:19:54,085 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:19:54,085 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 18:19:54,085 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [291369412] [2019-12-07 18:19:54,085 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 18:19:54,085 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:19:54,085 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 18:19:54,086 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:19:54,086 INFO L87 Difference]: Start difference. First operand 297 states and 506 transitions. Second operand 13 states. [2019-12-07 18:19:54,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:19:54,327 INFO L93 Difference]: Finished difference Result 399 states and 659 transitions. [2019-12-07 18:19:54,327 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 18:19:54,327 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 54 [2019-12-07 18:19:54,327 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:19:54,327 INFO L225 Difference]: With dead ends: 399 [2019-12-07 18:19:54,327 INFO L226 Difference]: Without dead ends: 367 [2019-12-07 18:19:54,328 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 66 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=90, Invalid=372, Unknown=0, NotChecked=0, Total=462 [2019-12-07 18:19:54,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 367 states. [2019-12-07 18:19:54,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 367 to 305. [2019-12-07 18:19:54,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 305 states. [2019-12-07 18:19:54,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 305 states to 305 states and 520 transitions. [2019-12-07 18:19:54,330 INFO L78 Accepts]: Start accepts. Automaton has 305 states and 520 transitions. Word has length 54 [2019-12-07 18:19:54,330 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:19:54,330 INFO L462 AbstractCegarLoop]: Abstraction has 305 states and 520 transitions. [2019-12-07 18:19:54,330 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 18:19:54,330 INFO L276 IsEmpty]: Start isEmpty. Operand 305 states and 520 transitions. [2019-12-07 18:19:54,331 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-12-07 18:19:54,331 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:19:54,331 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:19:54,331 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:19:54,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:19:54,331 INFO L82 PathProgramCache]: Analyzing trace with hash -695821945, now seen corresponding path program 5 times [2019-12-07 18:19:54,331 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:19:54,332 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1998469278] [2019-12-07 18:19:54,332 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:19:54,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:19:54,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:19:54,403 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:19:54,403 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 18:19:54,407 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [696] [696] ULTIMATE.startENTRY-->L777: Formula: (let ((.cse0 (store |v_#valid_42| 0 0))) (and (= 0 v_~x$w_buff1_used~0_344) (= v_~x$r_buff0_thd0~0_298 0) (= v_~x$r_buff0_thd1~0_128 0) (= 0 v_~weak$$choice0~0_26) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t2475~0.base_19|)) (= 0 |v_ULTIMATE.start_main_~#t2475~0.offset_16|) (= v_~x$r_buff1_thd2~0_87 0) (= v_~x$flush_delayed~0_47 0) (= 0 v_~x$read_delayed_var~0.base_7) (= 0 v_~x$w_buff1~0_200) (= v_~x$r_buff1_thd0~0_184 0) (= v_~y~0_77 0) (= 0 v_~x$w_buff0_used~0_631) (= v_~x$mem_tmp~0_31 0) (= 0 v_~x$read_delayed~0_7) (= v_~main$tmp_guard1~0_19 0) (= |v_#NULL.offset_5| 0) (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t2475~0.base_19| 4)) (= 0 v_~x$r_buff0_thd2~0_137) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t2475~0.base_19| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t2475~0.base_19|) |v_ULTIMATE.start_main_~#t2475~0.offset_16| 0)) |v_#memory_int_17|) (= 0 v_~x~0_143) (= v_~weak$$choice2~0_101 0) (= v_~x$r_buff1_thd1~0_135 0) (= 0 v_~__unbuffered_cnt~0_59) (= 0 v_~x$read_delayed_var~0.offset_7) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t2475~0.base_19|) (= (store .cse0 |v_ULTIMATE.start_main_~#t2475~0.base_19| 1) |v_#valid_40|) (= v_~main$tmp_guard0~0_24 0) (= 0 |v_#NULL.base_5|) (= 0 v_~x$w_buff0~0_255) (< 0 |v_#StackHeapBarrier_13|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_42|, #memory_int=|v_#memory_int_18|, #length=|v_#length_20|} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_255, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_36|, ~x$flush_delayed~0=v_~x$flush_delayed~0_47, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_27|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_135, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_31|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_35|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_57|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_36|, #length=|v_#length_19|, ULTIMATE.start_main_~#t2476~0.base=|v_ULTIMATE.start_main_~#t2476~0.base_20|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_298, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_30|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_25|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_45|, ~x$w_buff1~0=v_~x$w_buff1~0_200, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_25|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_344, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_87, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_38|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_38|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_28|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_7, ~weak$$choice0~0=v_~weak$$choice0~0_26, #StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_25|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_9|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_59, ~x~0=v_~x~0_143, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_128, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_23|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_29|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_19, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_38|, ~x$mem_tmp~0=v_~x$mem_tmp~0_31, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_27|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_39|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_21|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_40|, ULTIMATE.start_main_~#t2475~0.offset=|v_ULTIMATE.start_main_~#t2475~0.offset_16|, ~y~0=v_~y~0_77, ULTIMATE.start_main_#t~ite17=|v_ULTIMATE.start_main_#t~ite17_29|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_45|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_25|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_33|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_29|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_184, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_137, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_27|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_30|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_631, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_25|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_7, ULTIMATE.start_main_~#t2476~0.offset=|v_ULTIMATE.start_main_~#t2476~0.offset_16|, ULTIMATE.start_main_~#t2475~0.base=|v_ULTIMATE.start_main_~#t2475~0.base_19|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_16|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_16|, ~weak$$choice2~0=v_~weak$$choice2~0_101, ~x$read_delayed~0=v_~x$read_delayed~0_7} AuxVars[] AssignedVars[~x$w_buff0~0, ULTIMATE.start_main_#t~ite28, ~x$flush_delayed~0, #NULL.offset, ULTIMATE.start_main_#t~ite26, ~x$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, #length, ULTIMATE.start_main_~#t2476~0.base, ~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ~x$w_buff1~0, ULTIMATE.start_main_#t~ite35, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~x$read_delayed_var~0.base, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~nondet15, ~__unbuffered_cnt~0, ~x~0, ~x$r_buff0_thd1~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ~x$mem_tmp~0, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_~#t2475~0.offset, ~y~0, ULTIMATE.start_main_#t~ite17, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~x$w_buff0_used~0, ULTIMATE.start_main_#t~ite41, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_~#t2476~0.offset, ULTIMATE.start_main_~#t2475~0.base, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~weak$$choice2~0, ~x$read_delayed~0] because there is no mapped edge [2019-12-07 18:19:54,407 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [671] [671] L777-1-->L779: Formula: (and (= |v_#valid_21| (store |v_#valid_22| |v_ULTIMATE.start_main_~#t2476~0.base_10| 1)) (= |v_#memory_int_9| (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2476~0.base_10| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2476~0.base_10|) |v_ULTIMATE.start_main_~#t2476~0.offset_9| 1))) (not (= 0 |v_ULTIMATE.start_main_~#t2476~0.base_10|)) (< |v_#StackHeapBarrier_7| |v_ULTIMATE.start_main_~#t2476~0.base_10|) (= 0 |v_ULTIMATE.start_main_~#t2476~0.offset_9|) (= |v_#length_11| (store |v_#length_12| |v_ULTIMATE.start_main_~#t2476~0.base_10| 4)) (= (select |v_#valid_22| |v_ULTIMATE.start_main_~#t2476~0.base_10|) 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_7|, #valid=|v_#valid_22|, #memory_int=|v_#memory_int_10|, #length=|v_#length_12|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_7|, ULTIMATE.start_main_~#t2476~0.offset=|v_ULTIMATE.start_main_~#t2476~0.offset_9|, #valid=|v_#valid_21|, #memory_int=|v_#memory_int_9|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_11|, ULTIMATE.start_main_~#t2476~0.base=|v_ULTIMATE.start_main_~#t2476~0.base_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2476~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t2476~0.base] because there is no mapped edge [2019-12-07 18:19:54,408 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] P1ENTRY-->L4-3: Formula: (and (= ~x$w_buff1_used~0_Out-1735113814 ~x$w_buff0_used~0_In-1735113814) (= ~x$w_buff0~0_Out-1735113814 2) (= |P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_Out-1735113814| (ite (not (and (not (= (mod ~x$w_buff1_used~0_Out-1735113814 256) 0)) (not (= 0 (mod ~x$w_buff0_used~0_Out-1735113814 256))))) 1 0)) (= P1Thread1of1ForFork1___VERIFIER_assert_~expression_Out-1735113814 |P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_Out-1735113814|) (= 1 ~x$w_buff0_used~0_Out-1735113814) (not (= 0 P1Thread1of1ForFork1___VERIFIER_assert_~expression_Out-1735113814)) (= |P1Thread1of1ForFork1_#in~arg.base_In-1735113814| P1Thread1of1ForFork1_~arg.base_Out-1735113814) (= ~x$w_buff0~0_In-1735113814 ~x$w_buff1~0_Out-1735113814) (= P1Thread1of1ForFork1_~arg.offset_Out-1735113814 |P1Thread1of1ForFork1_#in~arg.offset_In-1735113814|)) InVars {~x$w_buff0~0=~x$w_buff0~0_In-1735113814, P1Thread1of1ForFork1_#in~arg.base=|P1Thread1of1ForFork1_#in~arg.base_In-1735113814|, P1Thread1of1ForFork1_#in~arg.offset=|P1Thread1of1ForFork1_#in~arg.offset_In-1735113814|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1735113814} OutVars{P1Thread1of1ForFork1___VERIFIER_assert_~expression=P1Thread1of1ForFork1___VERIFIER_assert_~expression_Out-1735113814, ~x$w_buff0~0=~x$w_buff0~0_Out-1735113814, P1Thread1of1ForFork1_~arg.offset=P1Thread1of1ForFork1_~arg.offset_Out-1735113814, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression=|P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_Out-1735113814|, P1Thread1of1ForFork1_~arg.base=P1Thread1of1ForFork1_~arg.base_Out-1735113814, ~x$w_buff1~0=~x$w_buff1~0_Out-1735113814, P1Thread1of1ForFork1_#in~arg.base=|P1Thread1of1ForFork1_#in~arg.base_In-1735113814|, P1Thread1of1ForFork1_#in~arg.offset=|P1Thread1of1ForFork1_#in~arg.offset_In-1735113814|, ~x$w_buff1_used~0=~x$w_buff1_used~0_Out-1735113814, ~x$w_buff0_used~0=~x$w_buff0_used~0_Out-1735113814} AuxVars[] AssignedVars[P1Thread1of1ForFork1___VERIFIER_assert_~expression, ~x$w_buff0~0, P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression, P1Thread1of1ForFork1_~arg.base, ~x$w_buff1~0, ~x$w_buff1_used~0, ~x$w_buff0_used~0] because there is no mapped edge [2019-12-07 18:19:54,409 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [641] [641] L726-2-->L726-5: Formula: (let ((.cse1 (= |P0Thread1of1ForFork0_#t~ite3_Out-580870201| |P0Thread1of1ForFork0_#t~ite4_Out-580870201|)) (.cse2 (= (mod ~x$r_buff1_thd1~0_In-580870201 256) 0)) (.cse0 (= (mod ~x$w_buff1_used~0_In-580870201 256) 0))) (or (and (not .cse0) (= |P0Thread1of1ForFork0_#t~ite3_Out-580870201| ~x$w_buff1~0_In-580870201) .cse1 (not .cse2)) (and .cse1 (or .cse2 .cse0) (= |P0Thread1of1ForFork0_#t~ite3_Out-580870201| ~x~0_In-580870201)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-580870201, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-580870201, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-580870201, ~x~0=~x~0_In-580870201} OutVars{P0Thread1of1ForFork0_#t~ite3=|P0Thread1of1ForFork0_#t~ite3_Out-580870201|, P0Thread1of1ForFork0_#t~ite4=|P0Thread1of1ForFork0_#t~ite4_Out-580870201|, ~x$w_buff1~0=~x$w_buff1~0_In-580870201, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-580870201, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-580870201, ~x~0=~x~0_In-580870201} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite3, P0Thread1of1ForFork0_#t~ite4] because there is no mapped edge [2019-12-07 18:19:54,409 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [654] [654] L755-->L755-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In778140942 256) 0)) (.cse1 (= 0 (mod ~x$r_buff0_thd2~0_In778140942 256)))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out778140942| ~x$w_buff0_used~0_In778140942)) (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out778140942| 0)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In778140942, ~x$w_buff0_used~0=~x$w_buff0_used~0_In778140942} OutVars{P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out778140942|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In778140942, ~x$w_buff0_used~0=~x$w_buff0_used~0_In778140942} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 18:19:54,409 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [648] [648] L727-->L727-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In714168910 256))) (.cse1 (= (mod ~x$r_buff0_thd1~0_In714168910 256) 0))) (or (and (not .cse0) (= |P0Thread1of1ForFork0_#t~ite5_Out714168910| 0) (not .cse1)) (and (= |P0Thread1of1ForFork0_#t~ite5_Out714168910| ~x$w_buff0_used~0_In714168910) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In714168910, ~x$w_buff0_used~0=~x$w_buff0_used~0_In714168910} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out714168910|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In714168910, ~x$w_buff0_used~0=~x$w_buff0_used~0_In714168910} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 18:19:54,410 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [652] [652] L728-->L728-2: Formula: (let ((.cse2 (= 0 (mod ~x$r_buff1_thd1~0_In1000501687 256))) (.cse3 (= (mod ~x$w_buff1_used~0_In1000501687 256) 0)) (.cse1 (= (mod ~x$w_buff0_used~0_In1000501687 256) 0)) (.cse0 (= (mod ~x$r_buff0_thd1~0_In1000501687 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork0_#t~ite6_Out1000501687|)) (and (or .cse2 .cse3) (= ~x$w_buff1_used~0_In1000501687 |P0Thread1of1ForFork0_#t~ite6_Out1000501687|) (or .cse1 .cse0)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In1000501687, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1000501687, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In1000501687, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1000501687} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out1000501687|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In1000501687, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1000501687, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In1000501687, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1000501687} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 18:19:54,410 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [643] [643] L729-->L729-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In71691091 256))) (.cse0 (= (mod ~x$r_buff0_thd1~0_In71691091 256) 0))) (or (and (= ~x$r_buff0_thd1~0_In71691091 |P0Thread1of1ForFork0_#t~ite7_Out71691091|) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= 0 |P0Thread1of1ForFork0_#t~ite7_Out71691091|)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In71691091, ~x$w_buff0_used~0=~x$w_buff0_used~0_In71691091} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In71691091, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out71691091|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In71691091} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-12-07 18:19:54,411 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [638] [638] L730-->L730-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff1_used~0_In-896808271 256))) (.cse1 (= (mod ~x$r_buff1_thd1~0_In-896808271 256) 0)) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In-896808271 256))) (.cse3 (= 0 (mod ~x$r_buff0_thd1~0_In-896808271 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite8_Out-896808271| 0)) (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P0Thread1of1ForFork0_#t~ite8_Out-896808271| ~x$r_buff1_thd1~0_In-896808271)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-896808271, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-896808271, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-896808271, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-896808271} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-896808271, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-896808271|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-896808271, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-896808271, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-896808271} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 18:19:54,411 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [672] [672] L730-2-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_43 1) v_~__unbuffered_cnt~0_42) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= v_~x$r_buff1_thd1~0_79 |v_P0Thread1of1ForFork0_#t~ite8_34|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_43} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_33|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_42, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_79} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, ~x$r_buff1_thd1~0] because there is no mapped edge [2019-12-07 18:19:54,411 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [636] [636] L756-->L756-2: Formula: (let ((.cse2 (= (mod ~x$r_buff0_thd2~0_In-1940460039 256) 0)) (.cse3 (= 0 (mod ~x$w_buff0_used~0_In-1940460039 256))) (.cse1 (= 0 (mod ~x$r_buff1_thd2~0_In-1940460039 256))) (.cse0 (= 0 (mod ~x$w_buff1_used~0_In-1940460039 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out-1940460039|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~x$w_buff1_used~0_In-1940460039 |P1Thread1of1ForFork1_#t~ite12_Out-1940460039|) (or .cse2 .cse3) (or .cse1 .cse0)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1940460039, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1940460039, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1940460039, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1940460039} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-1940460039, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1940460039, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-1940460039|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1940460039, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1940460039} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 18:19:54,411 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [653] [653] L757-->L758: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd2~0_In2129034695 256))) (.cse0 (= ~x$r_buff0_thd2~0_Out2129034695 ~x$r_buff0_thd2~0_In2129034695)) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In2129034695 256)))) (or (and .cse0 .cse1) (and (not .cse1) (not .cse2) (= ~x$r_buff0_thd2~0_Out2129034695 0)) (and .cse0 .cse2))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2129034695, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2129034695} OutVars{P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out2129034695|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out2129034695, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2129034695} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-12-07 18:19:54,412 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [639] [639] L758-->L758-2: Formula: (let ((.cse1 (= (mod ~x$r_buff1_thd2~0_In-607280704 256) 0)) (.cse0 (= (mod ~x$w_buff1_used~0_In-607280704 256) 0)) (.cse2 (= 0 (mod ~x$r_buff0_thd2~0_In-607280704 256))) (.cse3 (= (mod ~x$w_buff0_used~0_In-607280704 256) 0))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite14_Out-607280704| ~x$r_buff1_thd2~0_In-607280704) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork1_#t~ite14_Out-607280704|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-607280704, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-607280704, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-607280704, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-607280704} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-607280704, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-607280704, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-607280704, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-607280704|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-607280704} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 18:19:54,412 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [662] [662] L758-2-->P1EXIT: Formula: (and (= v_~__unbuffered_cnt~0_32 (+ v_~__unbuffered_cnt~0_33 1)) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= v_~x$r_buff1_thd2~0_45 |v_P1Thread1of1ForFork1_#t~ite14_28|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_33, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_28|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_45, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_32, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_27|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 18:19:54,412 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [585] [585] L783-->L785-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_91 256) 0) (= (mod v_~x$r_buff0_thd0~0_49 256) 0)) (not (= (mod v_~main$tmp_guard0~0_8 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_49, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_91} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_49, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_91} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 18:19:54,412 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [649] [649] L785-2-->L785-4: Formula: (let ((.cse1 (= (mod ~x$r_buff1_thd0~0_In-646028090 256) 0)) (.cse0 (= (mod ~x$w_buff1_used~0_In-646028090 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite17_Out-646028090| ~x$w_buff1~0_In-646028090) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~x~0_In-646028090 |ULTIMATE.start_main_#t~ite17_Out-646028090|)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-646028090, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-646028090, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-646028090, ~x~0=~x~0_In-646028090} OutVars{ULTIMATE.start_main_#t~ite17=|ULTIMATE.start_main_#t~ite17_Out-646028090|, ~x$w_buff1~0=~x$w_buff1~0_In-646028090, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-646028090, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-646028090, ~x~0=~x~0_In-646028090} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite17] because there is no mapped edge [2019-12-07 18:19:54,412 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [609] [609] L785-4-->L786: Formula: (= v_~x~0_39 |v_ULTIMATE.start_main_#t~ite17_8|) InVars {ULTIMATE.start_main_#t~ite17=|v_ULTIMATE.start_main_#t~ite17_8|} OutVars{ULTIMATE.start_main_#t~ite17=|v_ULTIMATE.start_main_#t~ite17_7|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_8|, ~x~0=v_~x~0_39} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite17, ULTIMATE.start_main_#t~ite18, ~x~0] because there is no mapped edge [2019-12-07 18:19:54,413 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [650] [650] L786-->L786-2: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In-1816168862 256) 0)) (.cse0 (= 0 (mod ~x$r_buff0_thd0~0_In-1816168862 256)))) (or (and (= ~x$w_buff0_used~0_In-1816168862 |ULTIMATE.start_main_#t~ite19_Out-1816168862|) (or .cse0 .cse1)) (and (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite19_Out-1816168862|) (not .cse0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1816168862, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1816168862} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1816168862, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-1816168862|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1816168862} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 18:19:54,413 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [656] [656] L787-->L787-2: Formula: (let ((.cse3 (= (mod ~x$w_buff1_used~0_In1282439239 256) 0)) (.cse2 (= (mod ~x$r_buff1_thd0~0_In1282439239 256) 0)) (.cse0 (= (mod ~x$r_buff0_thd0~0_In1282439239 256) 0)) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In1282439239 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite20_Out1282439239| ~x$w_buff1_used~0_In1282439239)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= |ULTIMATE.start_main_#t~ite20_Out1282439239| 0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1282439239, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1282439239, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1282439239, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1282439239} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1282439239, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1282439239, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out1282439239|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1282439239, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1282439239} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 18:19:54,413 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [645] [645] L788-->L788-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd0~0_In540860393 256))) (.cse0 (= (mod ~x$w_buff0_used~0_In540860393 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite21_Out540860393| ~x$r_buff0_thd0~0_In540860393)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite21_Out540860393| 0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In540860393, ~x$w_buff0_used~0=~x$w_buff0_used~0_In540860393} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In540860393, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out540860393|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In540860393} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 18:19:54,414 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [640] [640] L789-->L789-2: Formula: (let ((.cse2 (= 0 (mod ~x$r_buff1_thd0~0_In-1905224744 256))) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In-1905224744 256))) (.cse1 (= (mod ~x$w_buff0_used~0_In-1905224744 256) 0)) (.cse0 (= (mod ~x$r_buff0_thd0~0_In-1905224744 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite22_Out-1905224744|)) (and (or .cse2 .cse3) (or .cse1 .cse0) (= ~x$r_buff1_thd0~0_In-1905224744 |ULTIMATE.start_main_#t~ite22_Out-1905224744|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1905224744, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1905224744, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1905224744, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1905224744} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1905224744, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1905224744, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1905224744, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-1905224744|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1905224744} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 18:19:54,415 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L800-->L800-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In573747497 256)))) (or (and .cse0 (= |ULTIMATE.start_main_#t~ite38_Out573747497| |ULTIMATE.start_main_#t~ite37_Out573747497|) (let ((.cse1 (= 0 (mod ~x$r_buff0_thd0~0_In573747497 256)))) (or (and .cse1 (= 0 (mod ~x$r_buff1_thd0~0_In573747497 256))) (and (= 0 (mod ~x$w_buff1_used~0_In573747497 256)) .cse1) (= 0 (mod ~x$w_buff0_used~0_In573747497 256)))) (= ~x$w_buff1_used~0_In573747497 |ULTIMATE.start_main_#t~ite37_Out573747497|)) (and (= ~x$w_buff1_used~0_In573747497 |ULTIMATE.start_main_#t~ite38_Out573747497|) (not .cse0) (= |ULTIMATE.start_main_#t~ite37_In573747497| |ULTIMATE.start_main_#t~ite37_Out573747497|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In573747497, ~x$w_buff1_used~0=~x$w_buff1_used~0_In573747497, ULTIMATE.start_main_#t~ite37=|ULTIMATE.start_main_#t~ite37_In573747497|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In573747497, ~weak$$choice2~0=~weak$$choice2~0_In573747497, ~x$w_buff0_used~0=~x$w_buff0_used~0_In573747497} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In573747497, ~x$w_buff1_used~0=~x$w_buff1_used~0_In573747497, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out573747497|, ULTIMATE.start_main_#t~ite37=|ULTIMATE.start_main_#t~ite37_Out573747497|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In573747497, ~weak$$choice2~0=~weak$$choice2~0_In573747497, ~x$w_buff0_used~0=~x$w_buff0_used~0_In573747497} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_#t~ite37] because there is no mapped edge [2019-12-07 18:19:54,416 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [590] [590] L801-->L802: Formula: (and (= v_~x$r_buff0_thd0~0_57 v_~x$r_buff0_thd0~0_56) (not (= (mod v_~weak$$choice2~0_21 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_57, ~weak$$choice2~0=v_~weak$$choice2~0_21} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_56, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_7|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_8|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_7|, ~weak$$choice2~0=v_~weak$$choice2~0_21} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 18:19:54,416 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [664] [664] L804-->L4: Formula: (and (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6| (mod v_~main$tmp_guard1~0_10 256)) (= v_~x~0_75 v_~x$mem_tmp~0_14) (= v_~x$flush_delayed~0_25 0) (not (= (mod v_~x$flush_delayed~0_26 256) 0))) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_26, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_10, ~x$mem_tmp~0=v_~x$mem_tmp~0_14} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_8, ~x$flush_delayed~0=v_~x$flush_delayed~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_10, ~x$mem_tmp~0=v_~x$mem_tmp~0_14, ~x~0=v_~x~0_75, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_21|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~x$flush_delayed~0, ~x~0, ULTIMATE.start_main_#t~ite45, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:19:54,416 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [669] [669] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_9|)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_9|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_9|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:19:54,460 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 06:19:54 BasicIcfg [2019-12-07 18:19:54,460 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 18:19:54,460 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:19:54,460 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:19:54,460 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:19:54,461 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:19:44" (3/4) ... [2019-12-07 18:19:54,462 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 18:19:54,463 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [696] [696] ULTIMATE.startENTRY-->L777: Formula: (let ((.cse0 (store |v_#valid_42| 0 0))) (and (= 0 v_~x$w_buff1_used~0_344) (= v_~x$r_buff0_thd0~0_298 0) (= v_~x$r_buff0_thd1~0_128 0) (= 0 v_~weak$$choice0~0_26) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t2475~0.base_19|)) (= 0 |v_ULTIMATE.start_main_~#t2475~0.offset_16|) (= v_~x$r_buff1_thd2~0_87 0) (= v_~x$flush_delayed~0_47 0) (= 0 v_~x$read_delayed_var~0.base_7) (= 0 v_~x$w_buff1~0_200) (= v_~x$r_buff1_thd0~0_184 0) (= v_~y~0_77 0) (= 0 v_~x$w_buff0_used~0_631) (= v_~x$mem_tmp~0_31 0) (= 0 v_~x$read_delayed~0_7) (= v_~main$tmp_guard1~0_19 0) (= |v_#NULL.offset_5| 0) (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t2475~0.base_19| 4)) (= 0 v_~x$r_buff0_thd2~0_137) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t2475~0.base_19| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t2475~0.base_19|) |v_ULTIMATE.start_main_~#t2475~0.offset_16| 0)) |v_#memory_int_17|) (= 0 v_~x~0_143) (= v_~weak$$choice2~0_101 0) (= v_~x$r_buff1_thd1~0_135 0) (= 0 v_~__unbuffered_cnt~0_59) (= 0 v_~x$read_delayed_var~0.offset_7) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t2475~0.base_19|) (= (store .cse0 |v_ULTIMATE.start_main_~#t2475~0.base_19| 1) |v_#valid_40|) (= v_~main$tmp_guard0~0_24 0) (= 0 |v_#NULL.base_5|) (= 0 v_~x$w_buff0~0_255) (< 0 |v_#StackHeapBarrier_13|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_42|, #memory_int=|v_#memory_int_18|, #length=|v_#length_20|} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_255, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_36|, ~x$flush_delayed~0=v_~x$flush_delayed~0_47, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_27|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_135, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_31|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_35|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_57|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_36|, #length=|v_#length_19|, ULTIMATE.start_main_~#t2476~0.base=|v_ULTIMATE.start_main_~#t2476~0.base_20|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_298, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_30|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_25|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_45|, ~x$w_buff1~0=v_~x$w_buff1~0_200, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_25|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_344, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_87, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_38|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_38|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_28|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_7, ~weak$$choice0~0=v_~weak$$choice0~0_26, #StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_25|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_9|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_59, ~x~0=v_~x~0_143, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_128, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_23|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_29|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_19, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_38|, ~x$mem_tmp~0=v_~x$mem_tmp~0_31, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_27|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_39|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_21|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_40|, ULTIMATE.start_main_~#t2475~0.offset=|v_ULTIMATE.start_main_~#t2475~0.offset_16|, ~y~0=v_~y~0_77, ULTIMATE.start_main_#t~ite17=|v_ULTIMATE.start_main_#t~ite17_29|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_45|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_25|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_33|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_29|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_184, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_137, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_27|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_30|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_631, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_25|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_7, ULTIMATE.start_main_~#t2476~0.offset=|v_ULTIMATE.start_main_~#t2476~0.offset_16|, ULTIMATE.start_main_~#t2475~0.base=|v_ULTIMATE.start_main_~#t2475~0.base_19|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_16|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_16|, ~weak$$choice2~0=v_~weak$$choice2~0_101, ~x$read_delayed~0=v_~x$read_delayed~0_7} AuxVars[] AssignedVars[~x$w_buff0~0, ULTIMATE.start_main_#t~ite28, ~x$flush_delayed~0, #NULL.offset, ULTIMATE.start_main_#t~ite26, ~x$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, #length, ULTIMATE.start_main_~#t2476~0.base, ~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ~x$w_buff1~0, ULTIMATE.start_main_#t~ite35, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~x$read_delayed_var~0.base, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~nondet15, ~__unbuffered_cnt~0, ~x~0, ~x$r_buff0_thd1~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ~x$mem_tmp~0, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_~#t2475~0.offset, ~y~0, ULTIMATE.start_main_#t~ite17, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~x$w_buff0_used~0, ULTIMATE.start_main_#t~ite41, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_~#t2476~0.offset, ULTIMATE.start_main_~#t2475~0.base, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~weak$$choice2~0, ~x$read_delayed~0] because there is no mapped edge [2019-12-07 18:19:54,463 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [671] [671] L777-1-->L779: Formula: (and (= |v_#valid_21| (store |v_#valid_22| |v_ULTIMATE.start_main_~#t2476~0.base_10| 1)) (= |v_#memory_int_9| (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2476~0.base_10| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2476~0.base_10|) |v_ULTIMATE.start_main_~#t2476~0.offset_9| 1))) (not (= 0 |v_ULTIMATE.start_main_~#t2476~0.base_10|)) (< |v_#StackHeapBarrier_7| |v_ULTIMATE.start_main_~#t2476~0.base_10|) (= 0 |v_ULTIMATE.start_main_~#t2476~0.offset_9|) (= |v_#length_11| (store |v_#length_12| |v_ULTIMATE.start_main_~#t2476~0.base_10| 4)) (= (select |v_#valid_22| |v_ULTIMATE.start_main_~#t2476~0.base_10|) 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_7|, #valid=|v_#valid_22|, #memory_int=|v_#memory_int_10|, #length=|v_#length_12|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_7|, ULTIMATE.start_main_~#t2476~0.offset=|v_ULTIMATE.start_main_~#t2476~0.offset_9|, #valid=|v_#valid_21|, #memory_int=|v_#memory_int_9|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_11|, ULTIMATE.start_main_~#t2476~0.base=|v_ULTIMATE.start_main_~#t2476~0.base_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2476~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t2476~0.base] because there is no mapped edge [2019-12-07 18:19:54,463 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] P1ENTRY-->L4-3: Formula: (and (= ~x$w_buff1_used~0_Out-1735113814 ~x$w_buff0_used~0_In-1735113814) (= ~x$w_buff0~0_Out-1735113814 2) (= |P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_Out-1735113814| (ite (not (and (not (= (mod ~x$w_buff1_used~0_Out-1735113814 256) 0)) (not (= 0 (mod ~x$w_buff0_used~0_Out-1735113814 256))))) 1 0)) (= P1Thread1of1ForFork1___VERIFIER_assert_~expression_Out-1735113814 |P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_Out-1735113814|) (= 1 ~x$w_buff0_used~0_Out-1735113814) (not (= 0 P1Thread1of1ForFork1___VERIFIER_assert_~expression_Out-1735113814)) (= |P1Thread1of1ForFork1_#in~arg.base_In-1735113814| P1Thread1of1ForFork1_~arg.base_Out-1735113814) (= ~x$w_buff0~0_In-1735113814 ~x$w_buff1~0_Out-1735113814) (= P1Thread1of1ForFork1_~arg.offset_Out-1735113814 |P1Thread1of1ForFork1_#in~arg.offset_In-1735113814|)) InVars {~x$w_buff0~0=~x$w_buff0~0_In-1735113814, P1Thread1of1ForFork1_#in~arg.base=|P1Thread1of1ForFork1_#in~arg.base_In-1735113814|, P1Thread1of1ForFork1_#in~arg.offset=|P1Thread1of1ForFork1_#in~arg.offset_In-1735113814|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1735113814} OutVars{P1Thread1of1ForFork1___VERIFIER_assert_~expression=P1Thread1of1ForFork1___VERIFIER_assert_~expression_Out-1735113814, ~x$w_buff0~0=~x$w_buff0~0_Out-1735113814, P1Thread1of1ForFork1_~arg.offset=P1Thread1of1ForFork1_~arg.offset_Out-1735113814, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression=|P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_Out-1735113814|, P1Thread1of1ForFork1_~arg.base=P1Thread1of1ForFork1_~arg.base_Out-1735113814, ~x$w_buff1~0=~x$w_buff1~0_Out-1735113814, P1Thread1of1ForFork1_#in~arg.base=|P1Thread1of1ForFork1_#in~arg.base_In-1735113814|, P1Thread1of1ForFork1_#in~arg.offset=|P1Thread1of1ForFork1_#in~arg.offset_In-1735113814|, ~x$w_buff1_used~0=~x$w_buff1_used~0_Out-1735113814, ~x$w_buff0_used~0=~x$w_buff0_used~0_Out-1735113814} AuxVars[] AssignedVars[P1Thread1of1ForFork1___VERIFIER_assert_~expression, ~x$w_buff0~0, P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression, P1Thread1of1ForFork1_~arg.base, ~x$w_buff1~0, ~x$w_buff1_used~0, ~x$w_buff0_used~0] because there is no mapped edge [2019-12-07 18:19:54,464 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [641] [641] L726-2-->L726-5: Formula: (let ((.cse1 (= |P0Thread1of1ForFork0_#t~ite3_Out-580870201| |P0Thread1of1ForFork0_#t~ite4_Out-580870201|)) (.cse2 (= (mod ~x$r_buff1_thd1~0_In-580870201 256) 0)) (.cse0 (= (mod ~x$w_buff1_used~0_In-580870201 256) 0))) (or (and (not .cse0) (= |P0Thread1of1ForFork0_#t~ite3_Out-580870201| ~x$w_buff1~0_In-580870201) .cse1 (not .cse2)) (and .cse1 (or .cse2 .cse0) (= |P0Thread1of1ForFork0_#t~ite3_Out-580870201| ~x~0_In-580870201)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-580870201, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-580870201, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-580870201, ~x~0=~x~0_In-580870201} OutVars{P0Thread1of1ForFork0_#t~ite3=|P0Thread1of1ForFork0_#t~ite3_Out-580870201|, P0Thread1of1ForFork0_#t~ite4=|P0Thread1of1ForFork0_#t~ite4_Out-580870201|, ~x$w_buff1~0=~x$w_buff1~0_In-580870201, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-580870201, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-580870201, ~x~0=~x~0_In-580870201} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite3, P0Thread1of1ForFork0_#t~ite4] because there is no mapped edge [2019-12-07 18:19:54,464 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [654] [654] L755-->L755-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In778140942 256) 0)) (.cse1 (= 0 (mod ~x$r_buff0_thd2~0_In778140942 256)))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out778140942| ~x$w_buff0_used~0_In778140942)) (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out778140942| 0)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In778140942, ~x$w_buff0_used~0=~x$w_buff0_used~0_In778140942} OutVars{P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out778140942|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In778140942, ~x$w_buff0_used~0=~x$w_buff0_used~0_In778140942} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 18:19:54,464 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [648] [648] L727-->L727-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In714168910 256))) (.cse1 (= (mod ~x$r_buff0_thd1~0_In714168910 256) 0))) (or (and (not .cse0) (= |P0Thread1of1ForFork0_#t~ite5_Out714168910| 0) (not .cse1)) (and (= |P0Thread1of1ForFork0_#t~ite5_Out714168910| ~x$w_buff0_used~0_In714168910) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In714168910, ~x$w_buff0_used~0=~x$w_buff0_used~0_In714168910} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out714168910|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In714168910, ~x$w_buff0_used~0=~x$w_buff0_used~0_In714168910} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 18:19:54,464 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [652] [652] L728-->L728-2: Formula: (let ((.cse2 (= 0 (mod ~x$r_buff1_thd1~0_In1000501687 256))) (.cse3 (= (mod ~x$w_buff1_used~0_In1000501687 256) 0)) (.cse1 (= (mod ~x$w_buff0_used~0_In1000501687 256) 0)) (.cse0 (= (mod ~x$r_buff0_thd1~0_In1000501687 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork0_#t~ite6_Out1000501687|)) (and (or .cse2 .cse3) (= ~x$w_buff1_used~0_In1000501687 |P0Thread1of1ForFork0_#t~ite6_Out1000501687|) (or .cse1 .cse0)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In1000501687, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1000501687, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In1000501687, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1000501687} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out1000501687|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In1000501687, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1000501687, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In1000501687, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1000501687} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 18:19:54,464 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [643] [643] L729-->L729-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In71691091 256))) (.cse0 (= (mod ~x$r_buff0_thd1~0_In71691091 256) 0))) (or (and (= ~x$r_buff0_thd1~0_In71691091 |P0Thread1of1ForFork0_#t~ite7_Out71691091|) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= 0 |P0Thread1of1ForFork0_#t~ite7_Out71691091|)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In71691091, ~x$w_buff0_used~0=~x$w_buff0_used~0_In71691091} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In71691091, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out71691091|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In71691091} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-12-07 18:19:54,465 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [638] [638] L730-->L730-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff1_used~0_In-896808271 256))) (.cse1 (= (mod ~x$r_buff1_thd1~0_In-896808271 256) 0)) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In-896808271 256))) (.cse3 (= 0 (mod ~x$r_buff0_thd1~0_In-896808271 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite8_Out-896808271| 0)) (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P0Thread1of1ForFork0_#t~ite8_Out-896808271| ~x$r_buff1_thd1~0_In-896808271)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-896808271, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-896808271, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-896808271, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-896808271} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-896808271, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-896808271|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-896808271, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-896808271, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-896808271} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 18:19:54,465 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [672] [672] L730-2-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_43 1) v_~__unbuffered_cnt~0_42) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= v_~x$r_buff1_thd1~0_79 |v_P0Thread1of1ForFork0_#t~ite8_34|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_43} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_33|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_42, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_79} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, ~x$r_buff1_thd1~0] because there is no mapped edge [2019-12-07 18:19:54,465 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [636] [636] L756-->L756-2: Formula: (let ((.cse2 (= (mod ~x$r_buff0_thd2~0_In-1940460039 256) 0)) (.cse3 (= 0 (mod ~x$w_buff0_used~0_In-1940460039 256))) (.cse1 (= 0 (mod ~x$r_buff1_thd2~0_In-1940460039 256))) (.cse0 (= 0 (mod ~x$w_buff1_used~0_In-1940460039 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out-1940460039|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~x$w_buff1_used~0_In-1940460039 |P1Thread1of1ForFork1_#t~ite12_Out-1940460039|) (or .cse2 .cse3) (or .cse1 .cse0)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1940460039, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1940460039, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1940460039, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1940460039} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-1940460039, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1940460039, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-1940460039|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1940460039, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1940460039} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 18:19:54,465 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [653] [653] L757-->L758: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd2~0_In2129034695 256))) (.cse0 (= ~x$r_buff0_thd2~0_Out2129034695 ~x$r_buff0_thd2~0_In2129034695)) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In2129034695 256)))) (or (and .cse0 .cse1) (and (not .cse1) (not .cse2) (= ~x$r_buff0_thd2~0_Out2129034695 0)) (and .cse0 .cse2))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2129034695, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2129034695} OutVars{P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out2129034695|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out2129034695, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2129034695} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-12-07 18:19:54,465 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [639] [639] L758-->L758-2: Formula: (let ((.cse1 (= (mod ~x$r_buff1_thd2~0_In-607280704 256) 0)) (.cse0 (= (mod ~x$w_buff1_used~0_In-607280704 256) 0)) (.cse2 (= 0 (mod ~x$r_buff0_thd2~0_In-607280704 256))) (.cse3 (= (mod ~x$w_buff0_used~0_In-607280704 256) 0))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork1_#t~ite14_Out-607280704| ~x$r_buff1_thd2~0_In-607280704) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork1_#t~ite14_Out-607280704|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-607280704, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-607280704, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-607280704, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-607280704} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-607280704, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-607280704, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-607280704, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-607280704|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-607280704} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 18:19:54,465 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [662] [662] L758-2-->P1EXIT: Formula: (and (= v_~__unbuffered_cnt~0_32 (+ v_~__unbuffered_cnt~0_33 1)) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= v_~x$r_buff1_thd2~0_45 |v_P1Thread1of1ForFork1_#t~ite14_28|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_33, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_28|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_45, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_32, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_27|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 18:19:54,466 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [585] [585] L783-->L785-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_91 256) 0) (= (mod v_~x$r_buff0_thd0~0_49 256) 0)) (not (= (mod v_~main$tmp_guard0~0_8 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_49, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_91} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_49, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_91} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 18:19:54,466 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [649] [649] L785-2-->L785-4: Formula: (let ((.cse1 (= (mod ~x$r_buff1_thd0~0_In-646028090 256) 0)) (.cse0 (= (mod ~x$w_buff1_used~0_In-646028090 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite17_Out-646028090| ~x$w_buff1~0_In-646028090) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~x~0_In-646028090 |ULTIMATE.start_main_#t~ite17_Out-646028090|)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-646028090, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-646028090, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-646028090, ~x~0=~x~0_In-646028090} OutVars{ULTIMATE.start_main_#t~ite17=|ULTIMATE.start_main_#t~ite17_Out-646028090|, ~x$w_buff1~0=~x$w_buff1~0_In-646028090, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-646028090, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-646028090, ~x~0=~x~0_In-646028090} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite17] because there is no mapped edge [2019-12-07 18:19:54,466 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [609] [609] L785-4-->L786: Formula: (= v_~x~0_39 |v_ULTIMATE.start_main_#t~ite17_8|) InVars {ULTIMATE.start_main_#t~ite17=|v_ULTIMATE.start_main_#t~ite17_8|} OutVars{ULTIMATE.start_main_#t~ite17=|v_ULTIMATE.start_main_#t~ite17_7|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_8|, ~x~0=v_~x~0_39} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite17, ULTIMATE.start_main_#t~ite18, ~x~0] because there is no mapped edge [2019-12-07 18:19:54,466 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [650] [650] L786-->L786-2: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In-1816168862 256) 0)) (.cse0 (= 0 (mod ~x$r_buff0_thd0~0_In-1816168862 256)))) (or (and (= ~x$w_buff0_used~0_In-1816168862 |ULTIMATE.start_main_#t~ite19_Out-1816168862|) (or .cse0 .cse1)) (and (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite19_Out-1816168862|) (not .cse0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1816168862, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1816168862} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1816168862, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-1816168862|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1816168862} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 18:19:54,466 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [656] [656] L787-->L787-2: Formula: (let ((.cse3 (= (mod ~x$w_buff1_used~0_In1282439239 256) 0)) (.cse2 (= (mod ~x$r_buff1_thd0~0_In1282439239 256) 0)) (.cse0 (= (mod ~x$r_buff0_thd0~0_In1282439239 256) 0)) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In1282439239 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite20_Out1282439239| ~x$w_buff1_used~0_In1282439239)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= |ULTIMATE.start_main_#t~ite20_Out1282439239| 0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1282439239, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1282439239, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1282439239, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1282439239} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1282439239, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1282439239, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out1282439239|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1282439239, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1282439239} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 18:19:54,466 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [645] [645] L788-->L788-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd0~0_In540860393 256))) (.cse0 (= (mod ~x$w_buff0_used~0_In540860393 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite21_Out540860393| ~x$r_buff0_thd0~0_In540860393)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite21_Out540860393| 0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In540860393, ~x$w_buff0_used~0=~x$w_buff0_used~0_In540860393} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In540860393, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out540860393|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In540860393} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 18:19:54,466 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [640] [640] L789-->L789-2: Formula: (let ((.cse2 (= 0 (mod ~x$r_buff1_thd0~0_In-1905224744 256))) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In-1905224744 256))) (.cse1 (= (mod ~x$w_buff0_used~0_In-1905224744 256) 0)) (.cse0 (= (mod ~x$r_buff0_thd0~0_In-1905224744 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite22_Out-1905224744|)) (and (or .cse2 .cse3) (or .cse1 .cse0) (= ~x$r_buff1_thd0~0_In-1905224744 |ULTIMATE.start_main_#t~ite22_Out-1905224744|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1905224744, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1905224744, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1905224744, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1905224744} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1905224744, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1905224744, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1905224744, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-1905224744|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1905224744} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 18:19:54,468 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L800-->L800-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In573747497 256)))) (or (and .cse0 (= |ULTIMATE.start_main_#t~ite38_Out573747497| |ULTIMATE.start_main_#t~ite37_Out573747497|) (let ((.cse1 (= 0 (mod ~x$r_buff0_thd0~0_In573747497 256)))) (or (and .cse1 (= 0 (mod ~x$r_buff1_thd0~0_In573747497 256))) (and (= 0 (mod ~x$w_buff1_used~0_In573747497 256)) .cse1) (= 0 (mod ~x$w_buff0_used~0_In573747497 256)))) (= ~x$w_buff1_used~0_In573747497 |ULTIMATE.start_main_#t~ite37_Out573747497|)) (and (= ~x$w_buff1_used~0_In573747497 |ULTIMATE.start_main_#t~ite38_Out573747497|) (not .cse0) (= |ULTIMATE.start_main_#t~ite37_In573747497| |ULTIMATE.start_main_#t~ite37_Out573747497|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In573747497, ~x$w_buff1_used~0=~x$w_buff1_used~0_In573747497, ULTIMATE.start_main_#t~ite37=|ULTIMATE.start_main_#t~ite37_In573747497|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In573747497, ~weak$$choice2~0=~weak$$choice2~0_In573747497, ~x$w_buff0_used~0=~x$w_buff0_used~0_In573747497} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In573747497, ~x$w_buff1_used~0=~x$w_buff1_used~0_In573747497, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out573747497|, ULTIMATE.start_main_#t~ite37=|ULTIMATE.start_main_#t~ite37_Out573747497|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In573747497, ~weak$$choice2~0=~weak$$choice2~0_In573747497, ~x$w_buff0_used~0=~x$w_buff0_used~0_In573747497} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_#t~ite37] because there is no mapped edge [2019-12-07 18:19:54,468 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [590] [590] L801-->L802: Formula: (and (= v_~x$r_buff0_thd0~0_57 v_~x$r_buff0_thd0~0_56) (not (= (mod v_~weak$$choice2~0_21 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_57, ~weak$$choice2~0=v_~weak$$choice2~0_21} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_56, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_7|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_8|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_7|, ~weak$$choice2~0=v_~weak$$choice2~0_21} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 18:19:54,468 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [664] [664] L804-->L4: Formula: (and (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6| (mod v_~main$tmp_guard1~0_10 256)) (= v_~x~0_75 v_~x$mem_tmp~0_14) (= v_~x$flush_delayed~0_25 0) (not (= (mod v_~x$flush_delayed~0_26 256) 0))) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_26, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_10, ~x$mem_tmp~0=v_~x$mem_tmp~0_14} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_8, ~x$flush_delayed~0=v_~x$flush_delayed~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_10, ~x$mem_tmp~0=v_~x$mem_tmp~0_14, ~x~0=v_~x~0_75, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_21|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~x$flush_delayed~0, ~x~0, ULTIMATE.start_main_#t~ite45, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:19:54,469 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [669] [669] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_9|)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_9|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_9|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:19:54,516 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_35603829-dc64-461c-b156-ab08f21bc920/bin/uautomizer/witness.graphml [2019-12-07 18:19:54,516 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:19:54,517 INFO L168 Benchmark]: Toolchain (without parser) took 10562.82 ms. Allocated memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: 439.9 MB). Free memory was 937.1 MB in the beginning and 904.4 MB in the end (delta: 32.7 MB). Peak memory consumption was 472.6 MB. Max. memory is 11.5 GB. [2019-12-07 18:19:54,517 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:19:54,517 INFO L168 Benchmark]: CACSL2BoogieTranslator took 440.48 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 134.7 MB). Free memory was 937.1 MB in the beginning and 1.1 GB in the end (delta: -168.1 MB). Peak memory consumption was 18.2 MB. Max. memory is 11.5 GB. [2019-12-07 18:19:54,518 INFO L168 Benchmark]: Boogie Procedure Inliner took 38.98 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:19:54,518 INFO L168 Benchmark]: Boogie Preprocessor took 24.29 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:19:54,518 INFO L168 Benchmark]: RCFGBuilder took 378.81 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 50.9 MB). Peak memory consumption was 50.9 MB. Max. memory is 11.5 GB. [2019-12-07 18:19:54,518 INFO L168 Benchmark]: TraceAbstraction took 9621.65 ms. Allocated memory was 1.2 GB in the beginning and 1.5 GB in the end (delta: 305.1 MB). Free memory was 1.0 GB in the beginning and 927.9 MB in the end (delta: 121.0 MB). Peak memory consumption was 426.2 MB. Max. memory is 11.5 GB. [2019-12-07 18:19:54,519 INFO L168 Benchmark]: Witness Printer took 55.53 ms. Allocated memory is still 1.5 GB. Free memory was 927.9 MB in the beginning and 904.4 MB in the end (delta: 23.5 MB). Peak memory consumption was 23.5 MB. Max. memory is 11.5 GB. [2019-12-07 18:19:54,520 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 440.48 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 134.7 MB). Free memory was 937.1 MB in the beginning and 1.1 GB in the end (delta: -168.1 MB). Peak memory consumption was 18.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 38.98 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 24.29 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 378.81 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 50.9 MB). Peak memory consumption was 50.9 MB. Max. memory is 11.5 GB. * TraceAbstraction took 9621.65 ms. Allocated memory was 1.2 GB in the beginning and 1.5 GB in the end (delta: 305.1 MB). Free memory was 1.0 GB in the beginning and 927.9 MB in the end (delta: 121.0 MB). Peak memory consumption was 426.2 MB. Max. memory is 11.5 GB. * Witness Printer took 55.53 ms. Allocated memory is still 1.5 GB. Free memory was 927.9 MB in the beginning and 904.4 MB in the end (delta: 23.5 MB). Peak memory consumption was 23.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 2.6s, 145 ProgramPointsBefore, 79 ProgramPointsAfterwards, 179 TransitionsBefore, 90 TransitionsAfterwards, 10378 CoEnabledTransitionPairs, 7 FixpointIterations, 27 TrivialSequentialCompositions, 41 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 28 ConcurrentYvCompositions, 26 ChoiceCompositions, 3606 VarBasedMoverChecksPositive, 166 VarBasedMoverChecksNegative, 18 SemBasedMoverChecksPositive, 205 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.7s, 0 MoverChecksTotal, 47380 CheckedPairsTotal, 96 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L777] FCALL, FORK 0 pthread_create(&t2475, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L779] FCALL, FORK 0 pthread_create(&t2476, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L745] 2 x$r_buff1_thd0 = x$r_buff0_thd0 [L746] 2 x$r_buff1_thd1 = x$r_buff0_thd1 [L747] 2 x$r_buff1_thd2 = x$r_buff0_thd2 [L748] 2 x$r_buff0_thd2 = (_Bool)1 [L751] 2 y = 1 VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L754] EXPR 2 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L720] 1 y = 2 [L723] 1 x = 1 VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L754] 2 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L726] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L726] 1 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L727] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L728] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L729] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L755] 2 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L756] 2 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L781] 0 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [\result={0:0}, __unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L786] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L787] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L788] 0 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L789] 0 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L792] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L793] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L794] 0 x$flush_delayed = weak$$choice2 [L795] 0 x$mem_tmp = x VAL [\result={0:0}, __unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L796] EXPR 0 !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) VAL [\result={0:0}, __unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L796] 0 x = !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) [L797] EXPR 0 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) VAL [\result={0:0}, __unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L797] 0 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) [L798] EXPR 0 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) VAL [\result={0:0}, __unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L798] 0 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) [L799] EXPR 0 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) VAL [\result={0:0}, __unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L799] 0 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) [L800] 0 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L802] EXPR 0 weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, __unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L802] 0 x$r_buff1_thd0 = weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L803] 0 main$tmp_guard1 = !(x == 2 && y == 2) VAL [\result={0:0}, __unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 3 procedures, 139 locations, 2 error locations. Result: UNSAFE, OverallTime: 9.5s, OverallIterations: 19, TraceHistogramMax: 1, AutomataDifference: 3.3s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 1900 SDtfs, 1727 SDslu, 4868 SDs, 0 SdLazy, 3258 SolverSat, 175 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 189 GetRequests, 34 SyntacticMatches, 18 SemanticMatches, 137 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 288 ImplicationChecksByTransitivity, 1.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=14126occurred in iteration=5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 1.4s AutomataMinimizationTime, 18 MinimizatonAttempts, 11261 StatesRemovedByMinimization, 14 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.1s InterpolantComputationTime, 768 NumberOfCodeBlocks, 768 NumberOfCodeBlocksAsserted, 19 NumberOfCheckSat, 696 ConstructedInterpolants, 0 QuantifiedInterpolants, 126341 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 18 InterpolantComputations, 18 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...