./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe030_power.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_75c79b48-f731-4fa4-a9dc-2857b72a94e0/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_75c79b48-f731-4fa4-a9dc-2857b72a94e0/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_75c79b48-f731-4fa4-a9dc-2857b72a94e0/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_75c79b48-f731-4fa4-a9dc-2857b72a94e0/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe030_power.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_75c79b48-f731-4fa4-a9dc-2857b72a94e0/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_75c79b48-f731-4fa4-a9dc-2857b72a94e0/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash f876662a86f1aceded2e700e24741bef1c5d97c0 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:10:12,910 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:10:12,912 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:10:12,919 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:10:12,919 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:10:12,920 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:10:12,921 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:10:12,922 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:10:12,923 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:10:12,924 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:10:12,925 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:10:12,925 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:10:12,926 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:10:12,926 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:10:12,927 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:10:12,928 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:10:12,928 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:10:12,929 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:10:12,930 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:10:12,931 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:10:12,932 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:10:12,933 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:10:12,934 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:10:12,934 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:10:12,936 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:10:12,936 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:10:12,936 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:10:12,937 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:10:12,937 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:10:12,937 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:10:12,938 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:10:12,938 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:10:12,938 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:10:12,939 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:10:12,939 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:10:12,940 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:10:12,940 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:10:12,940 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:10:12,940 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:10:12,941 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:10:12,941 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:10:12,942 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_75c79b48-f731-4fa4-a9dc-2857b72a94e0/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 18:10:12,951 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:10:12,951 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:10:12,952 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:10:12,952 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:10:12,952 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:10:12,952 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:10:12,952 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:10:12,953 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:10:12,953 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:10:12,953 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:10:12,953 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 18:10:12,953 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 18:10:12,953 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 18:10:12,953 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:10:12,953 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:10:12,954 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:10:12,954 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 18:10:12,954 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:10:12,954 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:10:12,954 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 18:10:12,954 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 18:10:12,954 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:10:12,955 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:10:12,955 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 18:10:12,955 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 18:10:12,955 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:10:12,955 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 18:10:12,955 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 18:10:12,955 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:10:12,955 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_75c79b48-f731-4fa4-a9dc-2857b72a94e0/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> f876662a86f1aceded2e700e24741bef1c5d97c0 [2019-12-07 18:10:13,053 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:10:13,062 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:10:13,065 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:10:13,066 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:10:13,067 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:10:13,067 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_75c79b48-f731-4fa4-a9dc-2857b72a94e0/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe030_power.opt.i [2019-12-07 18:10:13,115 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_75c79b48-f731-4fa4-a9dc-2857b72a94e0/bin/uautomizer/data/5c3e398fa/2a28815c184d40ca849b19fbc23fd7b3/FLAG15acf63a5 [2019-12-07 18:10:13,484 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:10:13,484 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_75c79b48-f731-4fa4-a9dc-2857b72a94e0/sv-benchmarks/c/pthread-wmm/safe030_power.opt.i [2019-12-07 18:10:13,495 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_75c79b48-f731-4fa4-a9dc-2857b72a94e0/bin/uautomizer/data/5c3e398fa/2a28815c184d40ca849b19fbc23fd7b3/FLAG15acf63a5 [2019-12-07 18:10:13,503 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_75c79b48-f731-4fa4-a9dc-2857b72a94e0/bin/uautomizer/data/5c3e398fa/2a28815c184d40ca849b19fbc23fd7b3 [2019-12-07 18:10:13,505 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:10:13,506 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:10:13,507 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:10:13,507 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:10:13,509 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:10:13,510 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:10:13" (1/1) ... [2019-12-07 18:10:13,511 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3f8fae9c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:10:13, skipping insertion in model container [2019-12-07 18:10:13,512 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:10:13" (1/1) ... [2019-12-07 18:10:13,517 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:10:13,546 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:10:13,789 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:10:13,796 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:10:13,839 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:10:13,888 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:10:13,889 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:10:13 WrapperNode [2019-12-07 18:10:13,889 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:10:13,889 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:10:13,890 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:10:13,890 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:10:13,896 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:10:13" (1/1) ... [2019-12-07 18:10:13,912 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:10:13" (1/1) ... [2019-12-07 18:10:13,942 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:10:13,942 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:10:13,943 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:10:13,943 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:10:13,949 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:10:13" (1/1) ... [2019-12-07 18:10:13,949 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:10:13" (1/1) ... [2019-12-07 18:10:13,953 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:10:13" (1/1) ... [2019-12-07 18:10:13,954 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:10:13" (1/1) ... [2019-12-07 18:10:13,963 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:10:13" (1/1) ... [2019-12-07 18:10:13,967 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:10:13" (1/1) ... [2019-12-07 18:10:13,970 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:10:13" (1/1) ... [2019-12-07 18:10:13,975 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:10:13,975 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:10:13,975 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:10:13,975 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:10:13,976 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:10:13" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_75c79b48-f731-4fa4-a9dc-2857b72a94e0/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:10:14,023 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 18:10:14,023 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 18:10:14,023 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 18:10:14,023 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 18:10:14,024 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 18:10:14,024 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 18:10:14,024 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 18:10:14,024 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 18:10:14,024 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 18:10:14,024 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 18:10:14,024 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 18:10:14,024 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:10:14,024 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:10:14,026 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 18:10:14,373 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:10:14,373 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 18:10:14,374 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:10:14 BoogieIcfgContainer [2019-12-07 18:10:14,374 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:10:14,375 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 18:10:14,375 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 18:10:14,376 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 18:10:14,376 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 06:10:13" (1/3) ... [2019-12-07 18:10:14,377 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1fff680e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:10:14, skipping insertion in model container [2019-12-07 18:10:14,377 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:10:13" (2/3) ... [2019-12-07 18:10:14,377 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1fff680e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:10:14, skipping insertion in model container [2019-12-07 18:10:14,377 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:10:14" (3/3) ... [2019-12-07 18:10:14,378 INFO L109 eAbstractionObserver]: Analyzing ICFG safe030_power.opt.i [2019-12-07 18:10:14,384 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 18:10:14,384 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 18:10:14,389 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 18:10:14,389 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 18:10:14,412 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,412 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,413 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,413 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,413 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,413 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,414 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,414 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,414 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,414 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,414 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,415 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,415 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,415 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,415 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,415 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,416 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,416 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,416 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,416 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,416 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,416 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,417 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,417 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,417 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,417 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,417 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,418 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,418 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,418 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,418 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,418 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,419 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,419 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,419 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,419 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,420 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,420 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,420 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,420 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,420 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,420 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,421 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,421 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,421 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,422 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,422 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,422 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,422 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,422 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,422 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,423 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,423 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,423 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,423 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,423 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,423 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,424 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,424 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,424 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,424 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,424 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,424 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,425 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,425 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,425 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,425 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,425 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,425 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,426 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:10:14,437 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 18:10:14,449 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 18:10:14,449 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 18:10:14,450 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 18:10:14,450 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:10:14,450 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:10:14,450 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 18:10:14,450 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:10:14,450 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 18:10:14,460 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 161 places, 192 transitions [2019-12-07 18:10:14,461 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 161 places, 192 transitions [2019-12-07 18:10:14,510 INFO L134 PetriNetUnfolder]: 41/189 cut-off events. [2019-12-07 18:10:14,510 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:10:14,519 INFO L76 FinitePrefix]: Finished finitePrefix Result has 199 conditions, 189 events. 41/189 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 462 event pairs. 9/155 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-12-07 18:10:14,530 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 161 places, 192 transitions [2019-12-07 18:10:14,556 INFO L134 PetriNetUnfolder]: 41/189 cut-off events. [2019-12-07 18:10:14,556 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:10:14,559 INFO L76 FinitePrefix]: Finished finitePrefix Result has 199 conditions, 189 events. 41/189 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 462 event pairs. 9/155 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-12-07 18:10:14,568 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 11490 [2019-12-07 18:10:14,569 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 18:10:17,357 WARN L192 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 85 DAG size of output: 83 [2019-12-07 18:10:17,432 INFO L206 etLargeBlockEncoding]: Checked pairs total: 46210 [2019-12-07 18:10:17,432 INFO L214 etLargeBlockEncoding]: Total number of compositions: 110 [2019-12-07 18:10:17,435 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 81 places, 86 transitions [2019-12-07 18:10:18,095 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 15658 states. [2019-12-07 18:10:18,097 INFO L276 IsEmpty]: Start isEmpty. Operand 15658 states. [2019-12-07 18:10:18,101 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-12-07 18:10:18,101 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:18,102 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:18,102 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:18,105 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:18,106 INFO L82 PathProgramCache]: Analyzing trace with hash 430910871, now seen corresponding path program 1 times [2019-12-07 18:10:18,111 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:18,111 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1866162767] [2019-12-07 18:10:18,111 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:18,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:18,259 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:18,260 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1866162767] [2019-12-07 18:10:18,260 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:18,261 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:10:18,261 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [893542267] [2019-12-07 18:10:18,264 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:10:18,264 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:18,273 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:10:18,274 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:10:18,275 INFO L87 Difference]: Start difference. First operand 15658 states. Second operand 3 states. [2019-12-07 18:10:18,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:18,486 INFO L93 Difference]: Finished difference Result 15586 states and 57554 transitions. [2019-12-07 18:10:18,487 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:10:18,487 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-12-07 18:10:18,488 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:18,597 INFO L225 Difference]: With dead ends: 15586 [2019-12-07 18:10:18,597 INFO L226 Difference]: Without dead ends: 15248 [2019-12-07 18:10:18,598 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:10:18,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15248 states. [2019-12-07 18:10:19,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15248 to 15248. [2019-12-07 18:10:19,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15248 states. [2019-12-07 18:10:19,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15248 states to 15248 states and 56345 transitions. [2019-12-07 18:10:19,163 INFO L78 Accepts]: Start accepts. Automaton has 15248 states and 56345 transitions. Word has length 7 [2019-12-07 18:10:19,164 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:19,164 INFO L462 AbstractCegarLoop]: Abstraction has 15248 states and 56345 transitions. [2019-12-07 18:10:19,164 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:10:19,164 INFO L276 IsEmpty]: Start isEmpty. Operand 15248 states and 56345 transitions. [2019-12-07 18:10:19,167 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:10:19,168 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:19,168 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:19,168 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:19,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:19,168 INFO L82 PathProgramCache]: Analyzing trace with hash 1550259791, now seen corresponding path program 1 times [2019-12-07 18:10:19,168 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:19,168 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1719608422] [2019-12-07 18:10:19,168 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:19,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:19,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:19,232 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1719608422] [2019-12-07 18:10:19,232 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:19,232 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:10:19,232 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [375342760] [2019-12-07 18:10:19,233 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:10:19,233 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:19,233 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:10:19,233 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:10:19,233 INFO L87 Difference]: Start difference. First operand 15248 states and 56345 transitions. Second operand 4 states. [2019-12-07 18:10:19,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:19,539 INFO L93 Difference]: Finished difference Result 24364 states and 86703 transitions. [2019-12-07 18:10:19,540 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:10:19,540 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 18:10:19,540 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:19,641 INFO L225 Difference]: With dead ends: 24364 [2019-12-07 18:10:19,641 INFO L226 Difference]: Without dead ends: 24350 [2019-12-07 18:10:19,642 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:10:19,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24350 states. [2019-12-07 18:10:20,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24350 to 21678. [2019-12-07 18:10:20,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21678 states. [2019-12-07 18:10:20,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21678 states to 21678 states and 78082 transitions. [2019-12-07 18:10:20,147 INFO L78 Accepts]: Start accepts. Automaton has 21678 states and 78082 transitions. Word has length 13 [2019-12-07 18:10:20,147 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:20,147 INFO L462 AbstractCegarLoop]: Abstraction has 21678 states and 78082 transitions. [2019-12-07 18:10:20,147 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:10:20,147 INFO L276 IsEmpty]: Start isEmpty. Operand 21678 states and 78082 transitions. [2019-12-07 18:10:20,149 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:10:20,149 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:20,149 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:20,150 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:20,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:20,150 INFO L82 PathProgramCache]: Analyzing trace with hash -1785022215, now seen corresponding path program 1 times [2019-12-07 18:10:20,150 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:20,150 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1453536565] [2019-12-07 18:10:20,150 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:20,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:20,203 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:20,204 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1453536565] [2019-12-07 18:10:20,204 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:20,204 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:10:20,204 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1597142240] [2019-12-07 18:10:20,204 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:10:20,205 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:20,205 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:10:20,205 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:10:20,205 INFO L87 Difference]: Start difference. First operand 21678 states and 78082 transitions. Second operand 4 states. [2019-12-07 18:10:20,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:20,446 INFO L93 Difference]: Finished difference Result 26634 states and 94744 transitions. [2019-12-07 18:10:20,446 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:10:20,446 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 18:10:20,446 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:20,498 INFO L225 Difference]: With dead ends: 26634 [2019-12-07 18:10:20,498 INFO L226 Difference]: Without dead ends: 26634 [2019-12-07 18:10:20,498 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:10:20,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26634 states. [2019-12-07 18:10:20,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26634 to 23780. [2019-12-07 18:10:20,869 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23780 states. [2019-12-07 18:10:20,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23780 states to 23780 states and 85353 transitions. [2019-12-07 18:10:20,912 INFO L78 Accepts]: Start accepts. Automaton has 23780 states and 85353 transitions. Word has length 13 [2019-12-07 18:10:20,912 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:20,912 INFO L462 AbstractCegarLoop]: Abstraction has 23780 states and 85353 transitions. [2019-12-07 18:10:20,912 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:10:20,912 INFO L276 IsEmpty]: Start isEmpty. Operand 23780 states and 85353 transitions. [2019-12-07 18:10:20,917 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 18:10:20,917 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:20,917 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:20,917 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:20,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:20,917 INFO L82 PathProgramCache]: Analyzing trace with hash -1491137103, now seen corresponding path program 1 times [2019-12-07 18:10:20,918 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:20,918 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1460764738] [2019-12-07 18:10:20,918 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:20,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:20,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:20,981 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1460764738] [2019-12-07 18:10:20,982 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:20,982 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:10:20,982 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1399493379] [2019-12-07 18:10:20,982 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:10:20,982 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:20,982 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:10:20,982 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:10:20,983 INFO L87 Difference]: Start difference. First operand 23780 states and 85353 transitions. Second operand 5 states. [2019-12-07 18:10:21,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:21,427 INFO L93 Difference]: Finished difference Result 32276 states and 113793 transitions. [2019-12-07 18:10:21,428 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:10:21,428 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 18:10:21,428 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:21,483 INFO L225 Difference]: With dead ends: 32276 [2019-12-07 18:10:21,483 INFO L226 Difference]: Without dead ends: 32262 [2019-12-07 18:10:21,484 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:10:21,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32262 states. [2019-12-07 18:10:21,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32262 to 23678. [2019-12-07 18:10:21,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23678 states. [2019-12-07 18:10:21,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23678 states to 23678 states and 84856 transitions. [2019-12-07 18:10:21,921 INFO L78 Accepts]: Start accepts. Automaton has 23678 states and 84856 transitions. Word has length 19 [2019-12-07 18:10:21,922 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:21,922 INFO L462 AbstractCegarLoop]: Abstraction has 23678 states and 84856 transitions. [2019-12-07 18:10:21,922 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:10:21,922 INFO L276 IsEmpty]: Start isEmpty. Operand 23678 states and 84856 transitions. [2019-12-07 18:10:21,939 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 18:10:21,939 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:21,939 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:21,939 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:21,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:21,939 INFO L82 PathProgramCache]: Analyzing trace with hash -1614044955, now seen corresponding path program 1 times [2019-12-07 18:10:21,939 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:21,940 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [275847189] [2019-12-07 18:10:21,940 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:21,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:21,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:21,990 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [275847189] [2019-12-07 18:10:21,990 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:21,990 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:10:21,990 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1040734947] [2019-12-07 18:10:21,990 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:10:21,990 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:21,990 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:10:21,991 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:10:21,991 INFO L87 Difference]: Start difference. First operand 23678 states and 84856 transitions. Second operand 5 states. [2019-12-07 18:10:22,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:22,314 INFO L93 Difference]: Finished difference Result 30866 states and 109434 transitions. [2019-12-07 18:10:22,314 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:10:22,315 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 27 [2019-12-07 18:10:22,315 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:22,368 INFO L225 Difference]: With dead ends: 30866 [2019-12-07 18:10:22,368 INFO L226 Difference]: Without dead ends: 30850 [2019-12-07 18:10:22,369 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:10:22,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30850 states. [2019-12-07 18:10:22,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30850 to 27838. [2019-12-07 18:10:22,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27838 states. [2019-12-07 18:10:22,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27838 states to 27838 states and 99028 transitions. [2019-12-07 18:10:22,825 INFO L78 Accepts]: Start accepts. Automaton has 27838 states and 99028 transitions. Word has length 27 [2019-12-07 18:10:22,825 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:22,825 INFO L462 AbstractCegarLoop]: Abstraction has 27838 states and 99028 transitions. [2019-12-07 18:10:22,825 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:10:22,826 INFO L276 IsEmpty]: Start isEmpty. Operand 27838 states and 99028 transitions. [2019-12-07 18:10:22,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-12-07 18:10:22,848 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:22,849 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:22,849 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:22,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:22,849 INFO L82 PathProgramCache]: Analyzing trace with hash -633448160, now seen corresponding path program 1 times [2019-12-07 18:10:22,849 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:22,849 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [375186448] [2019-12-07 18:10:22,849 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:22,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:22,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:22,886 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [375186448] [2019-12-07 18:10:22,886 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:22,886 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:10:22,886 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [315593501] [2019-12-07 18:10:22,886 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:10:22,886 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:22,887 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:10:22,887 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:10:22,887 INFO L87 Difference]: Start difference. First operand 27838 states and 99028 transitions. Second operand 3 states. [2019-12-07 18:10:23,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:23,013 INFO L93 Difference]: Finished difference Result 33728 states and 120449 transitions. [2019-12-07 18:10:23,014 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:10:23,014 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 32 [2019-12-07 18:10:23,014 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:23,071 INFO L225 Difference]: With dead ends: 33728 [2019-12-07 18:10:23,072 INFO L226 Difference]: Without dead ends: 33728 [2019-12-07 18:10:23,072 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:10:23,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33728 states. [2019-12-07 18:10:23,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33728 to 31198. [2019-12-07 18:10:23,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31198 states. [2019-12-07 18:10:23,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31198 states to 31198 states and 111684 transitions. [2019-12-07 18:10:23,638 INFO L78 Accepts]: Start accepts. Automaton has 31198 states and 111684 transitions. Word has length 32 [2019-12-07 18:10:23,638 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:23,638 INFO L462 AbstractCegarLoop]: Abstraction has 31198 states and 111684 transitions. [2019-12-07 18:10:23,638 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:10:23,638 INFO L276 IsEmpty]: Start isEmpty. Operand 31198 states and 111684 transitions. [2019-12-07 18:10:23,662 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-12-07 18:10:23,662 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:23,662 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:23,662 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:23,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:23,663 INFO L82 PathProgramCache]: Analyzing trace with hash 775187136, now seen corresponding path program 1 times [2019-12-07 18:10:23,663 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:23,663 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1473031599] [2019-12-07 18:10:23,663 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:23,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:23,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:23,687 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1473031599] [2019-12-07 18:10:23,687 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:23,687 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:10:23,687 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [246897937] [2019-12-07 18:10:23,687 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:10:23,687 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:23,688 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:10:23,688 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:10:23,688 INFO L87 Difference]: Start difference. First operand 31198 states and 111684 transitions. Second operand 3 states. [2019-12-07 18:10:23,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:23,732 INFO L93 Difference]: Finished difference Result 17541 states and 54208 transitions. [2019-12-07 18:10:23,733 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:10:23,733 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 32 [2019-12-07 18:10:23,733 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:23,752 INFO L225 Difference]: With dead ends: 17541 [2019-12-07 18:10:23,752 INFO L226 Difference]: Without dead ends: 17541 [2019-12-07 18:10:23,752 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:10:23,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17541 states. [2019-12-07 18:10:23,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17541 to 17541. [2019-12-07 18:10:23,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17541 states. [2019-12-07 18:10:23,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17541 states to 17541 states and 54208 transitions. [2019-12-07 18:10:23,984 INFO L78 Accepts]: Start accepts. Automaton has 17541 states and 54208 transitions. Word has length 32 [2019-12-07 18:10:23,984 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:23,984 INFO L462 AbstractCegarLoop]: Abstraction has 17541 states and 54208 transitions. [2019-12-07 18:10:23,984 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:10:23,984 INFO L276 IsEmpty]: Start isEmpty. Operand 17541 states and 54208 transitions. [2019-12-07 18:10:23,995 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 18:10:23,996 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:23,996 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:23,996 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:23,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:23,996 INFO L82 PathProgramCache]: Analyzing trace with hash 1291274326, now seen corresponding path program 1 times [2019-12-07 18:10:23,996 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:23,996 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289155458] [2019-12-07 18:10:23,996 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:24,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:24,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:24,026 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1289155458] [2019-12-07 18:10:24,026 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:24,026 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:10:24,026 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280556341] [2019-12-07 18:10:24,027 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:10:24,027 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:24,027 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:10:24,027 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:10:24,027 INFO L87 Difference]: Start difference. First operand 17541 states and 54208 transitions. Second operand 3 states. [2019-12-07 18:10:24,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:24,097 INFO L93 Difference]: Finished difference Result 17541 states and 54000 transitions. [2019-12-07 18:10:24,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:10:24,097 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 33 [2019-12-07 18:10:24,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:24,117 INFO L225 Difference]: With dead ends: 17541 [2019-12-07 18:10:24,117 INFO L226 Difference]: Without dead ends: 17541 [2019-12-07 18:10:24,117 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:10:24,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17541 states. [2019-12-07 18:10:24,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17541 to 17541. [2019-12-07 18:10:24,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17541 states. [2019-12-07 18:10:24,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17541 states to 17541 states and 54000 transitions. [2019-12-07 18:10:24,394 INFO L78 Accepts]: Start accepts. Automaton has 17541 states and 54000 transitions. Word has length 33 [2019-12-07 18:10:24,394 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:24,394 INFO L462 AbstractCegarLoop]: Abstraction has 17541 states and 54000 transitions. [2019-12-07 18:10:24,394 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:10:24,394 INFO L276 IsEmpty]: Start isEmpty. Operand 17541 states and 54000 transitions. [2019-12-07 18:10:24,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 18:10:24,405 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:24,405 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:24,405 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:24,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:24,406 INFO L82 PathProgramCache]: Analyzing trace with hash -986581286, now seen corresponding path program 1 times [2019-12-07 18:10:24,406 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:24,406 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1212628468] [2019-12-07 18:10:24,406 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:24,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:24,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:24,482 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1212628468] [2019-12-07 18:10:24,482 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:24,483 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:10:24,483 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1616772508] [2019-12-07 18:10:24,483 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:10:24,483 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:24,483 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:10:24,483 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:10:24,483 INFO L87 Difference]: Start difference. First operand 17541 states and 54000 transitions. Second operand 6 states. [2019-12-07 18:10:24,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:24,698 INFO L93 Difference]: Finished difference Result 39110 states and 121229 transitions. [2019-12-07 18:10:24,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 18:10:24,698 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 33 [2019-12-07 18:10:24,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:24,725 INFO L225 Difference]: With dead ends: 39110 [2019-12-07 18:10:24,725 INFO L226 Difference]: Without dead ends: 24298 [2019-12-07 18:10:24,725 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=47, Invalid=85, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:10:24,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24298 states. [2019-12-07 18:10:25,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24298 to 21545. [2019-12-07 18:10:25,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21545 states. [2019-12-07 18:10:25,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21545 states to 21545 states and 64972 transitions. [2019-12-07 18:10:25,037 INFO L78 Accepts]: Start accepts. Automaton has 21545 states and 64972 transitions. Word has length 33 [2019-12-07 18:10:25,037 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:25,037 INFO L462 AbstractCegarLoop]: Abstraction has 21545 states and 64972 transitions. [2019-12-07 18:10:25,037 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:10:25,037 INFO L276 IsEmpty]: Start isEmpty. Operand 21545 states and 64972 transitions. [2019-12-07 18:10:25,047 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 18:10:25,048 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:25,048 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:25,048 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:25,048 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:25,048 INFO L82 PathProgramCache]: Analyzing trace with hash 1833353799, now seen corresponding path program 1 times [2019-12-07 18:10:25,048 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:25,048 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1218952341] [2019-12-07 18:10:25,048 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:25,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:25,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:25,094 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1218952341] [2019-12-07 18:10:25,094 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:25,094 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:10:25,094 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [238624061] [2019-12-07 18:10:25,094 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:10:25,094 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:25,094 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:10:25,095 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:10:25,095 INFO L87 Difference]: Start difference. First operand 21545 states and 64972 transitions. Second operand 6 states. [2019-12-07 18:10:25,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:25,440 INFO L93 Difference]: Finished difference Result 25124 states and 75040 transitions. [2019-12-07 18:10:25,441 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 18:10:25,441 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 34 [2019-12-07 18:10:25,441 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:25,471 INFO L225 Difference]: With dead ends: 25124 [2019-12-07 18:10:25,471 INFO L226 Difference]: Without dead ends: 24712 [2019-12-07 18:10:25,471 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=111, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:10:25,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24712 states. [2019-12-07 18:10:25,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24712 to 19573. [2019-12-07 18:10:25,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19573 states. [2019-12-07 18:10:25,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19573 states to 19573 states and 59529 transitions. [2019-12-07 18:10:25,774 INFO L78 Accepts]: Start accepts. Automaton has 19573 states and 59529 transitions. Word has length 34 [2019-12-07 18:10:25,774 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:25,774 INFO L462 AbstractCegarLoop]: Abstraction has 19573 states and 59529 transitions. [2019-12-07 18:10:25,774 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:10:25,774 INFO L276 IsEmpty]: Start isEmpty. Operand 19573 states and 59529 transitions. [2019-12-07 18:10:25,782 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 18:10:25,782 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:25,782 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:25,782 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:25,783 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:25,783 INFO L82 PathProgramCache]: Analyzing trace with hash 638623931, now seen corresponding path program 1 times [2019-12-07 18:10:25,783 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:25,783 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [624193531] [2019-12-07 18:10:25,783 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:25,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:25,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:25,866 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [624193531] [2019-12-07 18:10:25,866 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:25,866 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 18:10:25,866 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1278204983] [2019-12-07 18:10:25,866 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 18:10:25,867 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:25,867 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 18:10:25,867 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:10:25,867 INFO L87 Difference]: Start difference. First operand 19573 states and 59529 transitions. Second operand 9 states. [2019-12-07 18:10:26,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:26,179 INFO L93 Difference]: Finished difference Result 33215 states and 102732 transitions. [2019-12-07 18:10:26,179 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 18:10:26,179 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 34 [2019-12-07 18:10:26,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:26,211 INFO L225 Difference]: With dead ends: 33215 [2019-12-07 18:10:26,211 INFO L226 Difference]: Without dead ends: 28391 [2019-12-07 18:10:26,211 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:10:26,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28391 states. [2019-12-07 18:10:26,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28391 to 22159. [2019-12-07 18:10:26,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22159 states. [2019-12-07 18:10:26,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22159 states to 22159 states and 67445 transitions. [2019-12-07 18:10:26,524 INFO L78 Accepts]: Start accepts. Automaton has 22159 states and 67445 transitions. Word has length 34 [2019-12-07 18:10:26,525 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:26,525 INFO L462 AbstractCegarLoop]: Abstraction has 22159 states and 67445 transitions. [2019-12-07 18:10:26,525 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 18:10:26,525 INFO L276 IsEmpty]: Start isEmpty. Operand 22159 states and 67445 transitions. [2019-12-07 18:10:26,536 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 18:10:26,536 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:26,536 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:26,536 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:26,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:26,536 INFO L82 PathProgramCache]: Analyzing trace with hash 1676958407, now seen corresponding path program 2 times [2019-12-07 18:10:26,537 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:26,537 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [423839734] [2019-12-07 18:10:26,537 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:26,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:26,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:26,627 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [423839734] [2019-12-07 18:10:26,627 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:26,627 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:10:26,627 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1237224376] [2019-12-07 18:10:26,628 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 18:10:26,628 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:26,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 18:10:26,628 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:10:26,628 INFO L87 Difference]: Start difference. First operand 22159 states and 67445 transitions. Second operand 8 states. [2019-12-07 18:10:26,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:26,903 INFO L93 Difference]: Finished difference Result 34550 states and 107182 transitions. [2019-12-07 18:10:26,903 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 18:10:26,903 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 34 [2019-12-07 18:10:26,904 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:26,939 INFO L225 Difference]: With dead ends: 34550 [2019-12-07 18:10:26,939 INFO L226 Difference]: Without dead ends: 30101 [2019-12-07 18:10:26,939 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=101, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:10:27,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30101 states. [2019-12-07 18:10:27,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30101 to 21773. [2019-12-07 18:10:27,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21773 states. [2019-12-07 18:10:27,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21773 states to 21773 states and 66256 transitions. [2019-12-07 18:10:27,272 INFO L78 Accepts]: Start accepts. Automaton has 21773 states and 66256 transitions. Word has length 34 [2019-12-07 18:10:27,272 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:27,272 INFO L462 AbstractCegarLoop]: Abstraction has 21773 states and 66256 transitions. [2019-12-07 18:10:27,272 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 18:10:27,272 INFO L276 IsEmpty]: Start isEmpty. Operand 21773 states and 66256 transitions. [2019-12-07 18:10:27,284 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-12-07 18:10:27,284 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:27,284 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:27,284 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:27,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:27,285 INFO L82 PathProgramCache]: Analyzing trace with hash 1945525913, now seen corresponding path program 1 times [2019-12-07 18:10:27,285 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:27,285 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2106741665] [2019-12-07 18:10:27,285 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:27,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:27,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:27,412 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2106741665] [2019-12-07 18:10:27,412 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:27,412 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:10:27,412 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1151023221] [2019-12-07 18:10:27,413 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 18:10:27,413 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:27,413 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 18:10:27,413 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=68, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:10:27,413 INFO L87 Difference]: Start difference. First operand 21773 states and 66256 transitions. Second operand 10 states. [2019-12-07 18:10:27,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:27,941 INFO L93 Difference]: Finished difference Result 40696 states and 127252 transitions. [2019-12-07 18:10:27,941 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 18:10:27,941 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 35 [2019-12-07 18:10:27,941 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:28,041 INFO L225 Difference]: With dead ends: 40696 [2019-12-07 18:10:28,041 INFO L226 Difference]: Without dead ends: 37810 [2019-12-07 18:10:28,041 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 48 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=80, Invalid=300, Unknown=0, NotChecked=0, Total=380 [2019-12-07 18:10:28,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37810 states. [2019-12-07 18:10:28,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37810 to 22515. [2019-12-07 18:10:28,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22515 states. [2019-12-07 18:10:28,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22515 states to 22515 states and 68330 transitions. [2019-12-07 18:10:28,400 INFO L78 Accepts]: Start accepts. Automaton has 22515 states and 68330 transitions. Word has length 35 [2019-12-07 18:10:28,400 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:28,400 INFO L462 AbstractCegarLoop]: Abstraction has 22515 states and 68330 transitions. [2019-12-07 18:10:28,400 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 18:10:28,400 INFO L276 IsEmpty]: Start isEmpty. Operand 22515 states and 68330 transitions. [2019-12-07 18:10:28,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-12-07 18:10:28,414 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:28,414 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:28,414 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:28,414 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:28,414 INFO L82 PathProgramCache]: Analyzing trace with hash -359923411, now seen corresponding path program 2 times [2019-12-07 18:10:28,414 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:28,415 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1782434782] [2019-12-07 18:10:28,415 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:28,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:28,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:28,481 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1782434782] [2019-12-07 18:10:28,481 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:28,481 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:10:28,481 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [89121448] [2019-12-07 18:10:28,482 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 18:10:28,482 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:28,482 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 18:10:28,482 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:10:28,482 INFO L87 Difference]: Start difference. First operand 22515 states and 68330 transitions. Second operand 8 states. [2019-12-07 18:10:28,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:28,728 INFO L93 Difference]: Finished difference Result 40385 states and 124525 transitions. [2019-12-07 18:10:28,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 18:10:28,728 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 35 [2019-12-07 18:10:28,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:28,773 INFO L225 Difference]: With dead ends: 40385 [2019-12-07 18:10:28,773 INFO L226 Difference]: Without dead ends: 35712 [2019-12-07 18:10:28,773 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=42, Invalid=140, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:10:28,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35712 states. [2019-12-07 18:10:29,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35712 to 22919. [2019-12-07 18:10:29,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22919 states. [2019-12-07 18:10:29,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22919 states to 22919 states and 69419 transitions. [2019-12-07 18:10:29,144 INFO L78 Accepts]: Start accepts. Automaton has 22919 states and 69419 transitions. Word has length 35 [2019-12-07 18:10:29,144 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:29,144 INFO L462 AbstractCegarLoop]: Abstraction has 22919 states and 69419 transitions. [2019-12-07 18:10:29,144 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 18:10:29,144 INFO L276 IsEmpty]: Start isEmpty. Operand 22919 states and 69419 transitions. [2019-12-07 18:10:29,157 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-12-07 18:10:29,157 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:29,157 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:29,157 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:29,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:29,157 INFO L82 PathProgramCache]: Analyzing trace with hash 338185064, now seen corresponding path program 1 times [2019-12-07 18:10:29,157 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:29,158 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534705118] [2019-12-07 18:10:29,158 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:29,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:29,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:29,224 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1534705118] [2019-12-07 18:10:29,224 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:29,224 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:10:29,224 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [513453475] [2019-12-07 18:10:29,224 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:10:29,224 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:29,224 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:10:29,225 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:10:29,225 INFO L87 Difference]: Start difference. First operand 22919 states and 69419 transitions. Second operand 6 states. [2019-12-07 18:10:29,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:29,409 INFO L93 Difference]: Finished difference Result 35756 states and 111208 transitions. [2019-12-07 18:10:29,410 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 18:10:29,410 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 36 [2019-12-07 18:10:29,410 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:29,427 INFO L225 Difference]: With dead ends: 35756 [2019-12-07 18:10:29,427 INFO L226 Difference]: Without dead ends: 15026 [2019-12-07 18:10:29,428 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:10:29,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15026 states. [2019-12-07 18:10:29,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15026 to 12496. [2019-12-07 18:10:29,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12496 states. [2019-12-07 18:10:29,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12496 states to 12496 states and 38727 transitions. [2019-12-07 18:10:29,616 INFO L78 Accepts]: Start accepts. Automaton has 12496 states and 38727 transitions. Word has length 36 [2019-12-07 18:10:29,616 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:29,616 INFO L462 AbstractCegarLoop]: Abstraction has 12496 states and 38727 transitions. [2019-12-07 18:10:29,616 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:10:29,616 INFO L276 IsEmpty]: Start isEmpty. Operand 12496 states and 38727 transitions. [2019-12-07 18:10:29,624 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-12-07 18:10:29,624 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:29,624 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:29,624 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:29,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:29,625 INFO L82 PathProgramCache]: Analyzing trace with hash 1810599033, now seen corresponding path program 1 times [2019-12-07 18:10:29,625 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:29,625 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1732953455] [2019-12-07 18:10:29,625 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:29,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:29,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:29,701 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1732953455] [2019-12-07 18:10:29,701 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:29,701 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:10:29,701 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [552646682] [2019-12-07 18:10:29,702 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:10:29,702 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:29,702 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:10:29,702 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:10:29,702 INFO L87 Difference]: Start difference. First operand 12496 states and 38727 transitions. Second operand 6 states. [2019-12-07 18:10:29,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:29,792 INFO L93 Difference]: Finished difference Result 9494 states and 27691 transitions. [2019-12-07 18:10:29,792 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:10:29,792 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 36 [2019-12-07 18:10:29,793 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:29,802 INFO L225 Difference]: With dead ends: 9494 [2019-12-07 18:10:29,802 INFO L226 Difference]: Without dead ends: 8647 [2019-12-07 18:10:29,802 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:10:29,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8647 states. [2019-12-07 18:10:29,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8647 to 8374. [2019-12-07 18:10:29,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8374 states. [2019-12-07 18:10:29,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8374 states to 8374 states and 24818 transitions. [2019-12-07 18:10:29,932 INFO L78 Accepts]: Start accepts. Automaton has 8374 states and 24818 transitions. Word has length 36 [2019-12-07 18:10:29,932 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:29,932 INFO L462 AbstractCegarLoop]: Abstraction has 8374 states and 24818 transitions. [2019-12-07 18:10:29,932 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:10:29,932 INFO L276 IsEmpty]: Start isEmpty. Operand 8374 states and 24818 transitions. [2019-12-07 18:10:29,936 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-12-07 18:10:29,936 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:29,936 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:29,936 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:29,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:29,937 INFO L82 PathProgramCache]: Analyzing trace with hash 1686572430, now seen corresponding path program 2 times [2019-12-07 18:10:29,937 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:29,937 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [104895415] [2019-12-07 18:10:29,937 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:29,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:30,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:30,040 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [104895415] [2019-12-07 18:10:30,040 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:30,040 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:10:30,040 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [742314586] [2019-12-07 18:10:30,041 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:10:30,041 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:30,041 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:10:30,041 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:10:30,041 INFO L87 Difference]: Start difference. First operand 8374 states and 24818 transitions. Second operand 11 states. [2019-12-07 18:10:30,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:30,390 INFO L93 Difference]: Finished difference Result 14581 states and 43862 transitions. [2019-12-07 18:10:30,390 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 18:10:30,390 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 36 [2019-12-07 18:10:30,391 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:30,401 INFO L225 Difference]: With dead ends: 14581 [2019-12-07 18:10:30,401 INFO L226 Difference]: Without dead ends: 12013 [2019-12-07 18:10:30,401 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 56 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=83, Invalid=297, Unknown=0, NotChecked=0, Total=380 [2019-12-07 18:10:30,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12013 states. [2019-12-07 18:10:30,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12013 to 8170. [2019-12-07 18:10:30,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8170 states. [2019-12-07 18:10:30,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8170 states to 8170 states and 23985 transitions. [2019-12-07 18:10:30,513 INFO L78 Accepts]: Start accepts. Automaton has 8170 states and 23985 transitions. Word has length 36 [2019-12-07 18:10:30,513 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:30,514 INFO L462 AbstractCegarLoop]: Abstraction has 8170 states and 23985 transitions. [2019-12-07 18:10:30,514 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:10:30,514 INFO L276 IsEmpty]: Start isEmpty. Operand 8170 states and 23985 transitions. [2019-12-07 18:10:30,518 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 18:10:30,518 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:30,518 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:30,518 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:30,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:30,518 INFO L82 PathProgramCache]: Analyzing trace with hash 1164744073, now seen corresponding path program 1 times [2019-12-07 18:10:30,518 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:30,518 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [817573964] [2019-12-07 18:10:30,518 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:30,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:30,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:30,537 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [817573964] [2019-12-07 18:10:30,537 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:30,537 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:10:30,537 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [275740695] [2019-12-07 18:10:30,537 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:10:30,537 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:30,538 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:10:30,538 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:10:30,538 INFO L87 Difference]: Start difference. First operand 8170 states and 23985 transitions. Second operand 3 states. [2019-12-07 18:10:30,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:30,562 INFO L93 Difference]: Finished difference Result 8170 states and 23353 transitions. [2019-12-07 18:10:30,563 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:10:30,563 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 37 [2019-12-07 18:10:30,563 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:30,569 INFO L225 Difference]: With dead ends: 8170 [2019-12-07 18:10:30,570 INFO L226 Difference]: Without dead ends: 8170 [2019-12-07 18:10:30,570 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:10:30,597 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8170 states. [2019-12-07 18:10:30,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8170 to 8170. [2019-12-07 18:10:30,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8170 states. [2019-12-07 18:10:30,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8170 states to 8170 states and 23353 transitions. [2019-12-07 18:10:30,663 INFO L78 Accepts]: Start accepts. Automaton has 8170 states and 23353 transitions. Word has length 37 [2019-12-07 18:10:30,664 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:30,664 INFO L462 AbstractCegarLoop]: Abstraction has 8170 states and 23353 transitions. [2019-12-07 18:10:30,664 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:10:30,664 INFO L276 IsEmpty]: Start isEmpty. Operand 8170 states and 23353 transitions. [2019-12-07 18:10:30,667 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 18:10:30,667 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:30,667 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:30,668 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:30,668 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:30,668 INFO L82 PathProgramCache]: Analyzing trace with hash 871404576, now seen corresponding path program 1 times [2019-12-07 18:10:30,668 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:30,668 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1064578989] [2019-12-07 18:10:30,668 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:30,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:30,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:30,767 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1064578989] [2019-12-07 18:10:30,767 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:30,767 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:10:30,767 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1661674892] [2019-12-07 18:10:30,767 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:10:30,767 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:30,768 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:10:30,768 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:10:30,768 INFO L87 Difference]: Start difference. First operand 8170 states and 23353 transitions. Second operand 11 states. [2019-12-07 18:10:31,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:31,174 INFO L93 Difference]: Finished difference Result 11297 states and 31990 transitions. [2019-12-07 18:10:31,174 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-12-07 18:10:31,174 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 37 [2019-12-07 18:10:31,174 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:31,183 INFO L225 Difference]: With dead ends: 11297 [2019-12-07 18:10:31,183 INFO L226 Difference]: Without dead ends: 9886 [2019-12-07 18:10:31,184 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 122 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=148, Invalid=554, Unknown=0, NotChecked=0, Total=702 [2019-12-07 18:10:31,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9886 states. [2019-12-07 18:10:31,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9886 to 8174. [2019-12-07 18:10:31,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8174 states. [2019-12-07 18:10:31,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8174 states to 8174 states and 23365 transitions. [2019-12-07 18:10:31,292 INFO L78 Accepts]: Start accepts. Automaton has 8174 states and 23365 transitions. Word has length 37 [2019-12-07 18:10:31,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:31,292 INFO L462 AbstractCegarLoop]: Abstraction has 8174 states and 23365 transitions. [2019-12-07 18:10:31,292 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:10:31,292 INFO L276 IsEmpty]: Start isEmpty. Operand 8174 states and 23365 transitions. [2019-12-07 18:10:31,296 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 18:10:31,296 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:31,296 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:31,296 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:31,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:31,296 INFO L82 PathProgramCache]: Analyzing trace with hash -1236357120, now seen corresponding path program 2 times [2019-12-07 18:10:31,297 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:31,297 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [369633549] [2019-12-07 18:10:31,297 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:31,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:31,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:31,361 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [369633549] [2019-12-07 18:10:31,361 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:31,361 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:10:31,361 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [885729374] [2019-12-07 18:10:31,361 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 18:10:31,361 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:31,361 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 18:10:31,361 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:10:31,362 INFO L87 Difference]: Start difference. First operand 8174 states and 23365 transitions. Second operand 8 states. [2019-12-07 18:10:31,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:31,512 INFO L93 Difference]: Finished difference Result 10353 states and 29220 transitions. [2019-12-07 18:10:31,512 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 18:10:31,512 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 37 [2019-12-07 18:10:31,513 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:31,520 INFO L225 Difference]: With dead ends: 10353 [2019-12-07 18:10:31,520 INFO L226 Difference]: Without dead ends: 9326 [2019-12-07 18:10:31,521 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=47, Invalid=135, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:10:31,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9326 states. [2019-12-07 18:10:31,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9326 to 8173. [2019-12-07 18:10:31,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8173 states. [2019-12-07 18:10:31,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8173 states to 8173 states and 23329 transitions. [2019-12-07 18:10:31,624 INFO L78 Accepts]: Start accepts. Automaton has 8173 states and 23329 transitions. Word has length 37 [2019-12-07 18:10:31,624 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:31,625 INFO L462 AbstractCegarLoop]: Abstraction has 8173 states and 23329 transitions. [2019-12-07 18:10:31,625 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 18:10:31,625 INFO L276 IsEmpty]: Start isEmpty. Operand 8173 states and 23329 transitions. [2019-12-07 18:10:31,628 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 18:10:31,628 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:31,628 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:31,628 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:31,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:31,629 INFO L82 PathProgramCache]: Analyzing trace with hash -1903008522, now seen corresponding path program 3 times [2019-12-07 18:10:31,629 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:31,629 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1694444463] [2019-12-07 18:10:31,629 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:31,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:31,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:31,738 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1694444463] [2019-12-07 18:10:31,738 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:31,738 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:10:31,738 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1919459090] [2019-12-07 18:10:31,738 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:10:31,738 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:31,738 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:10:31,739 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:10:31,739 INFO L87 Difference]: Start difference. First operand 8173 states and 23329 transitions. Second operand 11 states. [2019-12-07 18:10:32,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:32,176 INFO L93 Difference]: Finished difference Result 10897 states and 30777 transitions. [2019-12-07 18:10:32,176 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2019-12-07 18:10:32,176 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 37 [2019-12-07 18:10:32,176 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:32,184 INFO L225 Difference]: With dead ends: 10897 [2019-12-07 18:10:32,184 INFO L226 Difference]: Without dead ends: 9195 [2019-12-07 18:10:32,185 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 158 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=166, Invalid=646, Unknown=0, NotChecked=0, Total=812 [2019-12-07 18:10:32,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9195 states. [2019-12-07 18:10:32,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9195 to 7603. [2019-12-07 18:10:32,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7603 states. [2019-12-07 18:10:32,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7603 states to 7603 states and 21808 transitions. [2019-12-07 18:10:32,283 INFO L78 Accepts]: Start accepts. Automaton has 7603 states and 21808 transitions. Word has length 37 [2019-12-07 18:10:32,283 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:32,283 INFO L462 AbstractCegarLoop]: Abstraction has 7603 states and 21808 transitions. [2019-12-07 18:10:32,283 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:10:32,283 INFO L276 IsEmpty]: Start isEmpty. Operand 7603 states and 21808 transitions. [2019-12-07 18:10:32,286 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 18:10:32,287 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:32,287 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:32,287 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:32,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:32,287 INFO L82 PathProgramCache]: Analyzing trace with hash -1884635564, now seen corresponding path program 1 times [2019-12-07 18:10:32,287 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:32,287 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [753897997] [2019-12-07 18:10:32,287 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:32,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:32,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:32,419 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [753897997] [2019-12-07 18:10:32,419 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:32,419 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 18:10:32,420 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1401352422] [2019-12-07 18:10:32,420 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 18:10:32,420 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:32,420 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 18:10:32,420 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=124, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:10:32,420 INFO L87 Difference]: Start difference. First operand 7603 states and 21808 transitions. Second operand 13 states. [2019-12-07 18:10:33,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:33,015 INFO L93 Difference]: Finished difference Result 13820 states and 39568 transitions. [2019-12-07 18:10:33,015 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2019-12-07 18:10:33,015 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 38 [2019-12-07 18:10:33,015 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:33,024 INFO L225 Difference]: With dead ends: 13820 [2019-12-07 18:10:33,024 INFO L226 Difference]: Without dead ends: 9266 [2019-12-07 18:10:33,024 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 216 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=185, Invalid=871, Unknown=0, NotChecked=0, Total=1056 [2019-12-07 18:10:33,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9266 states. [2019-12-07 18:10:33,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9266 to 6584. [2019-12-07 18:10:33,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6584 states. [2019-12-07 18:10:33,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6584 states to 6584 states and 19035 transitions. [2019-12-07 18:10:33,116 INFO L78 Accepts]: Start accepts. Automaton has 6584 states and 19035 transitions. Word has length 38 [2019-12-07 18:10:33,116 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:33,116 INFO L462 AbstractCegarLoop]: Abstraction has 6584 states and 19035 transitions. [2019-12-07 18:10:33,116 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 18:10:33,116 INFO L276 IsEmpty]: Start isEmpty. Operand 6584 states and 19035 transitions. [2019-12-07 18:10:33,119 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 18:10:33,119 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:33,119 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:33,119 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:33,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:33,119 INFO L82 PathProgramCache]: Analyzing trace with hash 1932854924, now seen corresponding path program 2 times [2019-12-07 18:10:33,119 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:33,120 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659444596] [2019-12-07 18:10:33,120 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:33,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:33,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:33,218 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1659444596] [2019-12-07 18:10:33,218 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:33,219 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:10:33,219 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [353725911] [2019-12-07 18:10:33,219 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:10:33,219 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:33,219 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:10:33,219 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:10:33,220 INFO L87 Difference]: Start difference. First operand 6584 states and 19035 transitions. Second operand 11 states. [2019-12-07 18:10:33,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:33,504 INFO L93 Difference]: Finished difference Result 8019 states and 23149 transitions. [2019-12-07 18:10:33,504 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 18:10:33,504 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2019-12-07 18:10:33,504 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:33,511 INFO L225 Difference]: With dead ends: 8019 [2019-12-07 18:10:33,511 INFO L226 Difference]: Without dead ends: 7554 [2019-12-07 18:10:33,511 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=47, Invalid=193, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:10:33,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7554 states. [2019-12-07 18:10:33,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7554 to 6600. [2019-12-07 18:10:33,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6600 states. [2019-12-07 18:10:33,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6600 states to 6600 states and 19059 transitions. [2019-12-07 18:10:33,607 INFO L78 Accepts]: Start accepts. Automaton has 6600 states and 19059 transitions. Word has length 38 [2019-12-07 18:10:33,607 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:33,607 INFO L462 AbstractCegarLoop]: Abstraction has 6600 states and 19059 transitions. [2019-12-07 18:10:33,607 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:10:33,607 INFO L276 IsEmpty]: Start isEmpty. Operand 6600 states and 19059 transitions. [2019-12-07 18:10:33,610 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 18:10:33,610 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:33,610 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:33,610 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:33,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:33,610 INFO L82 PathProgramCache]: Analyzing trace with hash -731117194, now seen corresponding path program 3 times [2019-12-07 18:10:33,610 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:33,610 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1201840500] [2019-12-07 18:10:33,610 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:33,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:33,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:33,715 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1201840500] [2019-12-07 18:10:33,715 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:33,715 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:10:33,715 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1178366222] [2019-12-07 18:10:33,716 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:10:33,716 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:33,716 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:10:33,716 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:10:33,716 INFO L87 Difference]: Start difference. First operand 6600 states and 19059 transitions. Second operand 11 states. [2019-12-07 18:10:33,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:33,992 INFO L93 Difference]: Finished difference Result 8009 states and 23135 transitions. [2019-12-07 18:10:33,992 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 18:10:33,992 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2019-12-07 18:10:33,992 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:33,999 INFO L225 Difference]: With dead ends: 8009 [2019-12-07 18:10:33,999 INFO L226 Difference]: Without dead ends: 7548 [2019-12-07 18:10:33,999 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=192, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:10:34,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7548 states. [2019-12-07 18:10:34,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7548 to 6592. [2019-12-07 18:10:34,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6592 states. [2019-12-07 18:10:34,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6592 states to 6592 states and 19047 transitions. [2019-12-07 18:10:34,087 INFO L78 Accepts]: Start accepts. Automaton has 6592 states and 19047 transitions. Word has length 38 [2019-12-07 18:10:34,087 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:34,087 INFO L462 AbstractCegarLoop]: Abstraction has 6592 states and 19047 transitions. [2019-12-07 18:10:34,087 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:10:34,087 INFO L276 IsEmpty]: Start isEmpty. Operand 6592 states and 19047 transitions. [2019-12-07 18:10:34,090 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 18:10:34,090 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:34,090 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:34,090 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:34,090 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:34,090 INFO L82 PathProgramCache]: Analyzing trace with hash -2139214782, now seen corresponding path program 4 times [2019-12-07 18:10:34,090 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:34,090 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1283718853] [2019-12-07 18:10:34,090 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:34,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:34,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:34,369 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1283718853] [2019-12-07 18:10:34,369 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:34,369 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 18:10:34,369 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1119551733] [2019-12-07 18:10:34,369 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 18:10:34,370 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:34,370 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 18:10:34,370 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=171, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:10:34,370 INFO L87 Difference]: Start difference. First operand 6592 states and 19047 transitions. Second operand 15 states. [2019-12-07 18:10:35,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:35,598 INFO L93 Difference]: Finished difference Result 13759 states and 39702 transitions. [2019-12-07 18:10:35,599 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2019-12-07 18:10:35,599 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 38 [2019-12-07 18:10:35,599 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:35,609 INFO L225 Difference]: With dead ends: 13759 [2019-12-07 18:10:35,609 INFO L226 Difference]: Without dead ends: 11486 [2019-12-07 18:10:35,610 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 299 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=228, Invalid=1254, Unknown=0, NotChecked=0, Total=1482 [2019-12-07 18:10:35,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11486 states. [2019-12-07 18:10:35,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11486 to 7676. [2019-12-07 18:10:35,709 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7676 states. [2019-12-07 18:10:35,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7676 states to 7676 states and 21901 transitions. [2019-12-07 18:10:35,718 INFO L78 Accepts]: Start accepts. Automaton has 7676 states and 21901 transitions. Word has length 38 [2019-12-07 18:10:35,718 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:35,718 INFO L462 AbstractCegarLoop]: Abstraction has 7676 states and 21901 transitions. [2019-12-07 18:10:35,718 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 18:10:35,718 INFO L276 IsEmpty]: Start isEmpty. Operand 7676 states and 21901 transitions. [2019-12-07 18:10:35,722 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 18:10:35,722 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:35,722 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:35,722 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:35,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:35,722 INFO L82 PathProgramCache]: Analyzing trace with hash -1523076140, now seen corresponding path program 5 times [2019-12-07 18:10:35,722 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:35,723 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [524269946] [2019-12-07 18:10:35,723 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:35,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:35,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:35,948 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [524269946] [2019-12-07 18:10:35,948 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:35,949 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 18:10:35,949 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1523212220] [2019-12-07 18:10:35,949 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 18:10:35,949 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:35,949 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 18:10:35,949 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=174, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:10:35,949 INFO L87 Difference]: Start difference. First operand 7676 states and 21901 transitions. Second operand 15 states. [2019-12-07 18:10:36,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:36,588 INFO L93 Difference]: Finished difference Result 9048 states and 25898 transitions. [2019-12-07 18:10:36,588 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 18:10:36,588 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 38 [2019-12-07 18:10:36,589 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:36,596 INFO L225 Difference]: With dead ends: 9048 [2019-12-07 18:10:36,596 INFO L226 Difference]: Without dead ends: 8638 [2019-12-07 18:10:36,596 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 59 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=80, Invalid=426, Unknown=0, NotChecked=0, Total=506 [2019-12-07 18:10:36,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8638 states. [2019-12-07 18:10:36,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8638 to 7667. [2019-12-07 18:10:36,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7667 states. [2019-12-07 18:10:36,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7667 states to 7667 states and 21882 transitions. [2019-12-07 18:10:36,689 INFO L78 Accepts]: Start accepts. Automaton has 7667 states and 21882 transitions. Word has length 38 [2019-12-07 18:10:36,689 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:36,690 INFO L462 AbstractCegarLoop]: Abstraction has 7667 states and 21882 transitions. [2019-12-07 18:10:36,690 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 18:10:36,690 INFO L276 IsEmpty]: Start isEmpty. Operand 7667 states and 21882 transitions. [2019-12-07 18:10:36,693 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 18:10:36,693 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:36,693 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:36,693 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:36,693 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:36,694 INFO L82 PathProgramCache]: Analyzing trace with hash -734855924, now seen corresponding path program 6 times [2019-12-07 18:10:36,694 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:36,694 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [636424243] [2019-12-07 18:10:36,694 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:36,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:36,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:36,853 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [636424243] [2019-12-07 18:10:36,854 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:36,854 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 18:10:36,854 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [923831278] [2019-12-07 18:10:36,854 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 18:10:36,854 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:36,854 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 18:10:36,854 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=148, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:10:36,854 INFO L87 Difference]: Start difference. First operand 7667 states and 21882 transitions. Second operand 14 states. [2019-12-07 18:10:37,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:37,523 INFO L93 Difference]: Finished difference Result 9132 states and 26061 transitions. [2019-12-07 18:10:37,524 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 18:10:37,524 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 38 [2019-12-07 18:10:37,524 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:37,537 INFO L225 Difference]: With dead ends: 9132 [2019-12-07 18:10:37,537 INFO L226 Difference]: Without dead ends: 8659 [2019-12-07 18:10:37,538 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 84 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=104, Invalid=496, Unknown=0, NotChecked=0, Total=600 [2019-12-07 18:10:37,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8659 states. [2019-12-07 18:10:37,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8659 to 7699. [2019-12-07 18:10:37,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7699 states. [2019-12-07 18:10:37,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7699 states to 7699 states and 21931 transitions. [2019-12-07 18:10:37,639 INFO L78 Accepts]: Start accepts. Automaton has 7699 states and 21931 transitions. Word has length 38 [2019-12-07 18:10:37,639 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:37,639 INFO L462 AbstractCegarLoop]: Abstraction has 7699 states and 21931 transitions. [2019-12-07 18:10:37,639 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 18:10:37,639 INFO L276 IsEmpty]: Start isEmpty. Operand 7699 states and 21931 transitions. [2019-12-07 18:10:37,643 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 18:10:37,643 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:37,643 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:37,643 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:37,643 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:37,643 INFO L82 PathProgramCache]: Analyzing trace with hash 1440783590, now seen corresponding path program 7 times [2019-12-07 18:10:37,643 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:37,643 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1828975421] [2019-12-07 18:10:37,644 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:37,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:37,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:37,777 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1828975421] [2019-12-07 18:10:37,777 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:37,777 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 18:10:37,777 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1585857988] [2019-12-07 18:10:37,778 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 18:10:37,778 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:37,778 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 18:10:37,778 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=105, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:10:37,778 INFO L87 Difference]: Start difference. First operand 7699 states and 21931 transitions. Second operand 12 states. [2019-12-07 18:10:38,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:38,336 INFO L93 Difference]: Finished difference Result 9096 states and 25991 transitions. [2019-12-07 18:10:38,337 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 18:10:38,338 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2019-12-07 18:10:38,338 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:38,351 INFO L225 Difference]: With dead ends: 9096 [2019-12-07 18:10:38,351 INFO L226 Difference]: Without dead ends: 8543 [2019-12-07 18:10:38,351 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=57, Invalid=249, Unknown=0, NotChecked=0, Total=306 [2019-12-07 18:10:38,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8543 states. [2019-12-07 18:10:38,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8543 to 7607. [2019-12-07 18:10:38,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7607 states. [2019-12-07 18:10:38,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7607 states to 7607 states and 21781 transitions. [2019-12-07 18:10:38,479 INFO L78 Accepts]: Start accepts. Automaton has 7607 states and 21781 transitions. Word has length 38 [2019-12-07 18:10:38,480 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:38,480 INFO L462 AbstractCegarLoop]: Abstraction has 7607 states and 21781 transitions. [2019-12-07 18:10:38,480 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 18:10:38,480 INFO L276 IsEmpty]: Start isEmpty. Operand 7607 states and 21781 transitions. [2019-12-07 18:10:38,485 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 18:10:38,485 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:38,485 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:38,485 INFO L410 AbstractCegarLoop]: === Iteration 29 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:38,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:38,485 INFO L82 PathProgramCache]: Analyzing trace with hash -1120219738, now seen corresponding path program 8 times [2019-12-07 18:10:38,486 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:38,486 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [751929427] [2019-12-07 18:10:38,486 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:38,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:38,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:38,606 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [751929427] [2019-12-07 18:10:38,606 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:38,607 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:10:38,607 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [954385113] [2019-12-07 18:10:38,607 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:10:38,607 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:38,607 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:10:38,607 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:10:38,607 INFO L87 Difference]: Start difference. First operand 7607 states and 21781 transitions. Second operand 11 states. [2019-12-07 18:10:39,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:39,052 INFO L93 Difference]: Finished difference Result 13999 states and 40211 transitions. [2019-12-07 18:10:39,052 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 18:10:39,052 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2019-12-07 18:10:39,052 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:39,063 INFO L225 Difference]: With dead ends: 13999 [2019-12-07 18:10:39,063 INFO L226 Difference]: Without dead ends: 11946 [2019-12-07 18:10:39,063 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=72, Invalid=270, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:10:39,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11946 states. [2019-12-07 18:10:39,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11946 to 8073. [2019-12-07 18:10:39,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8073 states. [2019-12-07 18:10:39,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8073 states to 8073 states and 23093 transitions. [2019-12-07 18:10:39,201 INFO L78 Accepts]: Start accepts. Automaton has 8073 states and 23093 transitions. Word has length 38 [2019-12-07 18:10:39,201 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:39,201 INFO L462 AbstractCegarLoop]: Abstraction has 8073 states and 23093 transitions. [2019-12-07 18:10:39,201 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:10:39,201 INFO L276 IsEmpty]: Start isEmpty. Operand 8073 states and 23093 transitions. [2019-12-07 18:10:39,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 18:10:39,206 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:39,207 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:39,207 INFO L410 AbstractCegarLoop]: === Iteration 30 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:39,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:39,207 INFO L82 PathProgramCache]: Analyzing trace with hash 510775440, now seen corresponding path program 9 times [2019-12-07 18:10:39,207 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:39,207 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [336736271] [2019-12-07 18:10:39,207 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:39,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:39,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:39,347 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [336736271] [2019-12-07 18:10:39,347 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:39,347 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:10:39,347 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1203027980] [2019-12-07 18:10:39,347 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:10:39,347 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:39,347 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:10:39,347 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:10:39,347 INFO L87 Difference]: Start difference. First operand 8073 states and 23093 transitions. Second operand 11 states. [2019-12-07 18:10:39,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:39,633 INFO L93 Difference]: Finished difference Result 9550 states and 27346 transitions. [2019-12-07 18:10:39,634 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 18:10:39,634 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2019-12-07 18:10:39,634 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:39,642 INFO L225 Difference]: With dead ends: 9550 [2019-12-07 18:10:39,642 INFO L226 Difference]: Without dead ends: 9089 [2019-12-07 18:10:39,642 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=192, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:10:39,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9089 states. [2019-12-07 18:10:39,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9089 to 8065. [2019-12-07 18:10:39,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8065 states. [2019-12-07 18:10:39,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8065 states to 8065 states and 23081 transitions. [2019-12-07 18:10:39,740 INFO L78 Accepts]: Start accepts. Automaton has 8065 states and 23081 transitions. Word has length 38 [2019-12-07 18:10:39,741 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:39,741 INFO L462 AbstractCegarLoop]: Abstraction has 8065 states and 23081 transitions. [2019-12-07 18:10:39,741 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:10:39,741 INFO L276 IsEmpty]: Start isEmpty. Operand 8065 states and 23081 transitions. [2019-12-07 18:10:39,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 18:10:39,744 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:39,744 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:39,745 INFO L410 AbstractCegarLoop]: === Iteration 31 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:39,745 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:39,745 INFO L82 PathProgramCache]: Analyzing trace with hash -897322148, now seen corresponding path program 10 times [2019-12-07 18:10:39,745 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:39,745 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [481093981] [2019-12-07 18:10:39,745 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:39,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:39,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:39,882 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [481093981] [2019-12-07 18:10:39,882 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:39,882 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 18:10:39,882 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2011668057] [2019-12-07 18:10:39,882 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 18:10:39,882 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:39,883 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 18:10:39,883 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=106, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:10:39,883 INFO L87 Difference]: Start difference. First operand 8065 states and 23081 transitions. Second operand 12 states. [2019-12-07 18:10:41,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:41,020 INFO L93 Difference]: Finished difference Result 15203 states and 43927 transitions. [2019-12-07 18:10:41,021 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2019-12-07 18:10:41,021 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2019-12-07 18:10:41,021 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:41,041 INFO L225 Difference]: With dead ends: 15203 [2019-12-07 18:10:41,041 INFO L226 Difference]: Without dead ends: 13240 [2019-12-07 18:10:41,041 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 151 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=132, Invalid=624, Unknown=0, NotChecked=0, Total=756 [2019-12-07 18:10:41,078 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13240 states. [2019-12-07 18:10:41,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13240 to 8283. [2019-12-07 18:10:41,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8283 states. [2019-12-07 18:10:41,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8283 states to 8283 states and 23702 transitions. [2019-12-07 18:10:41,165 INFO L78 Accepts]: Start accepts. Automaton has 8283 states and 23702 transitions. Word has length 38 [2019-12-07 18:10:41,165 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:41,165 INFO L462 AbstractCegarLoop]: Abstraction has 8283 states and 23702 transitions. [2019-12-07 18:10:41,165 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 18:10:41,165 INFO L276 IsEmpty]: Start isEmpty. Operand 8283 states and 23702 transitions. [2019-12-07 18:10:41,170 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 18:10:41,170 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:41,170 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:41,170 INFO L410 AbstractCegarLoop]: === Iteration 32 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:41,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:41,170 INFO L82 PathProgramCache]: Analyzing trace with hash 1364866022, now seen corresponding path program 11 times [2019-12-07 18:10:41,170 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:41,170 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786254832] [2019-12-07 18:10:41,170 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:41,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:41,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:41,343 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [786254832] [2019-12-07 18:10:41,343 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:41,343 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 18:10:41,344 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [920494938] [2019-12-07 18:10:41,344 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 18:10:41,344 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:41,344 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 18:10:41,344 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:10:41,344 INFO L87 Difference]: Start difference. First operand 8283 states and 23702 transitions. Second operand 13 states. [2019-12-07 18:10:42,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:42,640 INFO L93 Difference]: Finished difference Result 17645 states and 50987 transitions. [2019-12-07 18:10:42,641 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-12-07 18:10:42,641 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 38 [2019-12-07 18:10:42,642 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:42,664 INFO L225 Difference]: With dead ends: 17645 [2019-12-07 18:10:42,664 INFO L226 Difference]: Without dead ends: 15222 [2019-12-07 18:10:42,665 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 137 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=149, Invalid=663, Unknown=0, NotChecked=0, Total=812 [2019-12-07 18:10:42,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15222 states. [2019-12-07 18:10:42,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15222 to 8372. [2019-12-07 18:10:42,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8372 states. [2019-12-07 18:10:42,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8372 states to 8372 states and 23968 transitions. [2019-12-07 18:10:42,800 INFO L78 Accepts]: Start accepts. Automaton has 8372 states and 23968 transitions. Word has length 38 [2019-12-07 18:10:42,800 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:42,800 INFO L462 AbstractCegarLoop]: Abstraction has 8372 states and 23968 transitions. [2019-12-07 18:10:42,800 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 18:10:42,800 INFO L276 IsEmpty]: Start isEmpty. Operand 8372 states and 23968 transitions. [2019-12-07 18:10:42,804 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 18:10:42,805 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:42,805 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:42,805 INFO L410 AbstractCegarLoop]: === Iteration 33 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:42,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:42,805 INFO L82 PathProgramCache]: Analyzing trace with hash 507036710, now seen corresponding path program 12 times [2019-12-07 18:10:42,805 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:42,805 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [247791213] [2019-12-07 18:10:42,805 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:42,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:42,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:42,953 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [247791213] [2019-12-07 18:10:42,954 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:42,954 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 18:10:42,954 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1121683327] [2019-12-07 18:10:42,954 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 18:10:42,954 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:42,954 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 18:10:42,954 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=148, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:10:42,954 INFO L87 Difference]: Start difference. First operand 8372 states and 23968 transitions. Second operand 14 states. [2019-12-07 18:10:44,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:44,766 INFO L93 Difference]: Finished difference Result 15172 states and 43927 transitions. [2019-12-07 18:10:44,766 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2019-12-07 18:10:44,766 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 38 [2019-12-07 18:10:44,766 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:44,780 INFO L225 Difference]: With dead ends: 15172 [2019-12-07 18:10:44,780 INFO L226 Difference]: Without dead ends: 14056 [2019-12-07 18:10:44,781 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 214 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=174, Invalid=882, Unknown=0, NotChecked=0, Total=1056 [2019-12-07 18:10:44,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14056 states. [2019-12-07 18:10:44,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14056 to 8464. [2019-12-07 18:10:44,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8464 states. [2019-12-07 18:10:44,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8464 states to 8464 states and 24249 transitions. [2019-12-07 18:10:44,913 INFO L78 Accepts]: Start accepts. Automaton has 8464 states and 24249 transitions. Word has length 38 [2019-12-07 18:10:44,913 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:44,913 INFO L462 AbstractCegarLoop]: Abstraction has 8464 states and 24249 transitions. [2019-12-07 18:10:44,914 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 18:10:44,914 INFO L276 IsEmpty]: Start isEmpty. Operand 8464 states and 24249 transitions. [2019-12-07 18:10:44,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 18:10:44,918 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:44,918 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:44,918 INFO L410 AbstractCegarLoop]: === Iteration 34 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:44,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:44,919 INFO L82 PathProgramCache]: Analyzing trace with hash 173103266, now seen corresponding path program 13 times [2019-12-07 18:10:44,919 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:44,919 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1226414670] [2019-12-07 18:10:44,919 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:44,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:45,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:45,019 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1226414670] [2019-12-07 18:10:45,019 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:45,019 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:10:45,019 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [922623019] [2019-12-07 18:10:45,019 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 18:10:45,019 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:45,019 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 18:10:45,019 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:10:45,019 INFO L87 Difference]: Start difference. First operand 8464 states and 24249 transitions. Second operand 10 states. [2019-12-07 18:10:45,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:45,399 INFO L93 Difference]: Finished difference Result 14695 states and 42446 transitions. [2019-12-07 18:10:45,399 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-12-07 18:10:45,399 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 38 [2019-12-07 18:10:45,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:45,411 INFO L225 Difference]: With dead ends: 14695 [2019-12-07 18:10:45,411 INFO L226 Difference]: Without dead ends: 12882 [2019-12-07 18:10:45,411 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=65, Invalid=241, Unknown=0, NotChecked=0, Total=306 [2019-12-07 18:10:45,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12882 states. [2019-12-07 18:10:45,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12882 to 8582. [2019-12-07 18:10:45,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8582 states. [2019-12-07 18:10:45,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8582 states to 8582 states and 24647 transitions. [2019-12-07 18:10:45,532 INFO L78 Accepts]: Start accepts. Automaton has 8582 states and 24647 transitions. Word has length 38 [2019-12-07 18:10:45,532 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:45,532 INFO L462 AbstractCegarLoop]: Abstraction has 8582 states and 24647 transitions. [2019-12-07 18:10:45,532 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 18:10:45,532 INFO L276 IsEmpty]: Start isEmpty. Operand 8582 states and 24647 transitions. [2019-12-07 18:10:45,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 18:10:45,537 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:45,538 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:45,538 INFO L410 AbstractCegarLoop]: === Iteration 35 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:45,538 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:45,538 INFO L82 PathProgramCache]: Analyzing trace with hash -1234994322, now seen corresponding path program 14 times [2019-12-07 18:10:45,538 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:45,538 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1977307060] [2019-12-07 18:10:45,538 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:45,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:45,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:45,640 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1977307060] [2019-12-07 18:10:45,640 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:45,640 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:10:45,640 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [552306699] [2019-12-07 18:10:45,640 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:10:45,641 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:45,641 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:10:45,641 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:10:45,641 INFO L87 Difference]: Start difference. First operand 8582 states and 24647 transitions. Second operand 11 states. [2019-12-07 18:10:45,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:45,962 INFO L93 Difference]: Finished difference Result 9079 states and 25953 transitions. [2019-12-07 18:10:45,962 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 18:10:45,963 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2019-12-07 18:10:45,963 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:45,970 INFO L225 Difference]: With dead ends: 9079 [2019-12-07 18:10:45,970 INFO L226 Difference]: Without dead ends: 8571 [2019-12-07 18:10:45,970 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=60, Invalid=246, Unknown=0, NotChecked=0, Total=306 [2019-12-07 18:10:45,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8571 states. [2019-12-07 18:10:46,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8571 to 8571. [2019-12-07 18:10:46,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8571 states. [2019-12-07 18:10:46,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8571 states to 8571 states and 24629 transitions. [2019-12-07 18:10:46,077 INFO L78 Accepts]: Start accepts. Automaton has 8571 states and 24629 transitions. Word has length 38 [2019-12-07 18:10:46,077 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:46,077 INFO L462 AbstractCegarLoop]: Abstraction has 8571 states and 24629 transitions. [2019-12-07 18:10:46,078 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:10:46,078 INFO L276 IsEmpty]: Start isEmpty. Operand 8571 states and 24629 transitions. [2019-12-07 18:10:46,082 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 18:10:46,082 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:46,082 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:46,082 INFO L410 AbstractCegarLoop]: === Iteration 36 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:46,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:46,082 INFO L82 PathProgramCache]: Analyzing trace with hash -1451272932, now seen corresponding path program 15 times [2019-12-07 18:10:46,082 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:46,083 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1618110288] [2019-12-07 18:10:46,083 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:46,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:46,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:46,156 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1618110288] [2019-12-07 18:10:46,156 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:46,156 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:10:46,156 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [822258396] [2019-12-07 18:10:46,156 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 18:10:46,156 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:46,156 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 18:10:46,157 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:10:46,157 INFO L87 Difference]: Start difference. First operand 8571 states and 24629 transitions. Second operand 10 states. [2019-12-07 18:10:46,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:46,807 INFO L93 Difference]: Finished difference Result 16118 states and 46408 transitions. [2019-12-07 18:10:46,808 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 18:10:46,808 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 38 [2019-12-07 18:10:46,808 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:46,826 INFO L225 Difference]: With dead ends: 16118 [2019-12-07 18:10:46,826 INFO L226 Difference]: Without dead ends: 14151 [2019-12-07 18:10:46,827 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 77 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=97, Invalid=365, Unknown=0, NotChecked=0, Total=462 [2019-12-07 18:10:46,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14151 states. [2019-12-07 18:10:46,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14151 to 8635. [2019-12-07 18:10:46,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8635 states. [2019-12-07 18:10:46,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8635 states to 8635 states and 24855 transitions. [2019-12-07 18:10:46,954 INFO L78 Accepts]: Start accepts. Automaton has 8635 states and 24855 transitions. Word has length 38 [2019-12-07 18:10:46,954 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:46,954 INFO L462 AbstractCegarLoop]: Abstraction has 8635 states and 24855 transitions. [2019-12-07 18:10:46,954 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 18:10:46,954 INFO L276 IsEmpty]: Start isEmpty. Operand 8635 states and 24855 transitions. [2019-12-07 18:10:46,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 18:10:46,959 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:46,959 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:46,959 INFO L410 AbstractCegarLoop]: === Iteration 37 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:46,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:46,960 INFO L82 PathProgramCache]: Analyzing trace with hash 810915238, now seen corresponding path program 16 times [2019-12-07 18:10:46,960 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:46,960 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [978770994] [2019-12-07 18:10:46,960 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:46,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:47,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:47,023 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [978770994] [2019-12-07 18:10:47,023 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:47,023 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 18:10:47,023 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2087771953] [2019-12-07 18:10:47,024 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 18:10:47,024 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:47,024 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 18:10:47,024 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:10:47,024 INFO L87 Difference]: Start difference. First operand 8635 states and 24855 transitions. Second operand 9 states. [2019-12-07 18:10:47,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:47,181 INFO L93 Difference]: Finished difference Result 10070 states and 28976 transitions. [2019-12-07 18:10:47,182 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 18:10:47,182 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 38 [2019-12-07 18:10:47,182 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:47,190 INFO L225 Difference]: With dead ends: 10070 [2019-12-07 18:10:47,190 INFO L226 Difference]: Without dead ends: 9505 [2019-12-07 18:10:47,190 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:10:47,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9505 states. [2019-12-07 18:10:47,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9505 to 8505. [2019-12-07 18:10:47,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8505 states. [2019-12-07 18:10:47,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8505 states to 8505 states and 24599 transitions. [2019-12-07 18:10:47,292 INFO L78 Accepts]: Start accepts. Automaton has 8505 states and 24599 transitions. Word has length 38 [2019-12-07 18:10:47,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:47,292 INFO L462 AbstractCegarLoop]: Abstraction has 8505 states and 24599 transitions. [2019-12-07 18:10:47,292 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 18:10:47,292 INFO L276 IsEmpty]: Start isEmpty. Operand 8505 states and 24599 transitions. [2019-12-07 18:10:47,296 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 18:10:47,296 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:47,297 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:47,297 INFO L410 AbstractCegarLoop]: === Iteration 38 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:47,297 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:47,297 INFO L82 PathProgramCache]: Analyzing trace with hash 2089288892, now seen corresponding path program 1 times [2019-12-07 18:10:47,297 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:47,297 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1168760928] [2019-12-07 18:10:47,297 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:47,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:47,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:47,314 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1168760928] [2019-12-07 18:10:47,314 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:47,314 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:10:47,314 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2145381942] [2019-12-07 18:10:47,315 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:10:47,315 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:47,315 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:10:47,315 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:10:47,315 INFO L87 Difference]: Start difference. First operand 8505 states and 24599 transitions. Second operand 4 states. [2019-12-07 18:10:47,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:47,323 INFO L93 Difference]: Finished difference Result 1115 states and 2230 transitions. [2019-12-07 18:10:47,323 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:10:47,323 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 38 [2019-12-07 18:10:47,323 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:47,324 INFO L225 Difference]: With dead ends: 1115 [2019-12-07 18:10:47,324 INFO L226 Difference]: Without dead ends: 1107 [2019-12-07 18:10:47,324 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:10:47,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1107 states. [2019-12-07 18:10:47,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1107 to 1091. [2019-12-07 18:10:47,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1091 states. [2019-12-07 18:10:47,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1091 states to 1091 states and 2185 transitions. [2019-12-07 18:10:47,331 INFO L78 Accepts]: Start accepts. Automaton has 1091 states and 2185 transitions. Word has length 38 [2019-12-07 18:10:47,331 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:47,331 INFO L462 AbstractCegarLoop]: Abstraction has 1091 states and 2185 transitions. [2019-12-07 18:10:47,332 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:10:47,332 INFO L276 IsEmpty]: Start isEmpty. Operand 1091 states and 2185 transitions. [2019-12-07 18:10:47,332 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-12-07 18:10:47,332 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:47,332 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:47,332 INFO L410 AbstractCegarLoop]: === Iteration 39 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:47,332 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:47,332 INFO L82 PathProgramCache]: Analyzing trace with hash 2121919124, now seen corresponding path program 1 times [2019-12-07 18:10:47,333 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:47,333 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1033338717] [2019-12-07 18:10:47,333 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:47,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:47,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:47,356 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1033338717] [2019-12-07 18:10:47,356 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:47,356 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:10:47,356 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1004868211] [2019-12-07 18:10:47,356 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:10:47,356 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:47,356 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:10:47,356 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:10:47,357 INFO L87 Difference]: Start difference. First operand 1091 states and 2185 transitions. Second operand 5 states. [2019-12-07 18:10:47,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:47,367 INFO L93 Difference]: Finished difference Result 239 states and 418 transitions. [2019-12-07 18:10:47,367 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:10:47,367 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 45 [2019-12-07 18:10:47,367 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:47,368 INFO L225 Difference]: With dead ends: 239 [2019-12-07 18:10:47,368 INFO L226 Difference]: Without dead ends: 231 [2019-12-07 18:10:47,368 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:10:47,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 231 states. [2019-12-07 18:10:47,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 231 to 207. [2019-12-07 18:10:47,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2019-12-07 18:10:47,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 364 transitions. [2019-12-07 18:10:47,370 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 364 transitions. Word has length 45 [2019-12-07 18:10:47,370 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:47,370 INFO L462 AbstractCegarLoop]: Abstraction has 207 states and 364 transitions. [2019-12-07 18:10:47,370 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:10:47,370 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 364 transitions. [2019-12-07 18:10:47,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 18:10:47,370 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:47,370 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:47,370 INFO L410 AbstractCegarLoop]: === Iteration 40 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:47,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:47,371 INFO L82 PathProgramCache]: Analyzing trace with hash -1590264344, now seen corresponding path program 1 times [2019-12-07 18:10:47,371 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:47,371 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1045719173] [2019-12-07 18:10:47,371 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:47,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:47,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:47,505 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1045719173] [2019-12-07 18:10:47,505 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:47,505 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 18:10:47,505 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1874024361] [2019-12-07 18:10:47,506 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 18:10:47,506 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:47,506 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 18:10:47,506 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=129, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:10:47,506 INFO L87 Difference]: Start difference. First operand 207 states and 364 transitions. Second operand 13 states. [2019-12-07 18:10:47,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:47,743 INFO L93 Difference]: Finished difference Result 349 states and 597 transitions. [2019-12-07 18:10:47,743 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 18:10:47,743 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 56 [2019-12-07 18:10:47,744 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:47,744 INFO L225 Difference]: With dead ends: 349 [2019-12-07 18:10:47,744 INFO L226 Difference]: Without dead ends: 239 [2019-12-07 18:10:47,744 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=78, Invalid=384, Unknown=0, NotChecked=0, Total=462 [2019-12-07 18:10:47,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239 states. [2019-12-07 18:10:47,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239 to 215. [2019-12-07 18:10:47,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 215 states. [2019-12-07 18:10:47,746 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215 states to 215 states and 376 transitions. [2019-12-07 18:10:47,746 INFO L78 Accepts]: Start accepts. Automaton has 215 states and 376 transitions. Word has length 56 [2019-12-07 18:10:47,746 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:47,746 INFO L462 AbstractCegarLoop]: Abstraction has 215 states and 376 transitions. [2019-12-07 18:10:47,746 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 18:10:47,746 INFO L276 IsEmpty]: Start isEmpty. Operand 215 states and 376 transitions. [2019-12-07 18:10:47,746 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 18:10:47,746 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:47,746 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:47,747 INFO L410 AbstractCegarLoop]: === Iteration 41 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:47,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:47,747 INFO L82 PathProgramCache]: Analyzing trace with hash 1710889504, now seen corresponding path program 2 times [2019-12-07 18:10:47,747 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:47,747 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123972058] [2019-12-07 18:10:47,747 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:47,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:10:47,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:10:47,880 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2123972058] [2019-12-07 18:10:47,880 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:10:47,880 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 18:10:47,880 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [676445027] [2019-12-07 18:10:47,881 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 18:10:47,881 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:10:47,881 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 18:10:47,881 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:10:47,881 INFO L87 Difference]: Start difference. First operand 215 states and 376 transitions. Second operand 13 states. [2019-12-07 18:10:48,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:10:48,063 INFO L93 Difference]: Finished difference Result 301 states and 504 transitions. [2019-12-07 18:10:48,063 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 18:10:48,063 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 56 [2019-12-07 18:10:48,063 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:10:48,063 INFO L225 Difference]: With dead ends: 301 [2019-12-07 18:10:48,063 INFO L226 Difference]: Without dead ends: 191 [2019-12-07 18:10:48,063 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 58 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=83, Invalid=337, Unknown=0, NotChecked=0, Total=420 [2019-12-07 18:10:48,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191 states. [2019-12-07 18:10:48,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191 to 191. [2019-12-07 18:10:48,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 191 states. [2019-12-07 18:10:48,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191 states to 191 states and 330 transitions. [2019-12-07 18:10:48,065 INFO L78 Accepts]: Start accepts. Automaton has 191 states and 330 transitions. Word has length 56 [2019-12-07 18:10:48,065 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:10:48,065 INFO L462 AbstractCegarLoop]: Abstraction has 191 states and 330 transitions. [2019-12-07 18:10:48,065 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 18:10:48,065 INFO L276 IsEmpty]: Start isEmpty. Operand 191 states and 330 transitions. [2019-12-07 18:10:48,065 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 18:10:48,065 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:10:48,066 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:10:48,066 INFO L410 AbstractCegarLoop]: === Iteration 42 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:10:48,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:10:48,066 INFO L82 PathProgramCache]: Analyzing trace with hash -1475134232, now seen corresponding path program 3 times [2019-12-07 18:10:48,066 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:10:48,066 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [995855011] [2019-12-07 18:10:48,066 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:10:48,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:10:48,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:10:48,124 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:10:48,124 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 18:10:48,126 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [743] [743] ULTIMATE.startENTRY-->L798: Formula: (let ((.cse0 (store |v_#valid_61| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= 0 v_~y$r_buff1_thd1~0_54) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t2492~0.base_27|) (= 0 v_~y$r_buff1_thd3~0_115) (= 0 v_~y$r_buff1_thd2~0_106) (= v_~weak$$choice2~0_112 0) (= v_~y$r_buff0_thd1~0_53 0) (= v_~y$r_buff0_thd0~0_348 0) (= v_~y$w_buff0_used~0_737 0) (= v_~y$w_buff1~0_230 0) (= v_~y$read_delayed~0_6 0) (= 0 v_~y$r_buff0_thd3~0_169) (= 0 v_~y$w_buff0~0_338) (< 0 |v_#StackHeapBarrier_18|) (= 0 v_~y$r_buff0_thd2~0_108) (= (store .cse0 |v_ULTIMATE.start_main_~#t2492~0.base_27| 1) |v_#valid_59|) (= v_~y$mem_tmp~0_19 0) (= v_~z~0_90 0) (= v_~x~0_77 0) (= v_~y$w_buff1_used~0_407 0) (= v_~main$tmp_guard0~0_21 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t2492~0.base_27|)) (= |v_#NULL.offset_5| 0) (= v_~main$tmp_guard1~0_36 0) (= 0 v_~__unbuffered_cnt~0_90) (= v_~y$r_buff1_thd0~0_237 0) (= (store |v_#length_26| |v_ULTIMATE.start_main_~#t2492~0.base_27| 4) |v_#length_25|) (= 0 |v_ULTIMATE.start_main_~#t2492~0.offset_20|) (= 0 v_~y$flush_delayed~0_38) (= 0 v_~y$read_delayed_var~0.offset_6) (= v_~y~0_150 0) (= 0 |v_#NULL.base_5|) (= |v_#memory_int_23| (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t2492~0.base_27| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t2492~0.base_27|) |v_ULTIMATE.start_main_~#t2492~0.offset_20| 0))) (= 0 v_~weak$$choice0~0_12))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_61|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_34|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_39|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_62|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_31|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_71|, ULTIMATE.start_main_~#t2494~0.base=|v_ULTIMATE.start_main_~#t2494~0.base_20|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~y$mem_tmp~0=v_~y$mem_tmp~0_19, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_115, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_53, ~y$flush_delayed~0=v_~y$flush_delayed~0_38, #length=|v_#length_25|, ULTIMATE.start_main_~#t2494~0.offset=|v_ULTIMATE.start_main_~#t2494~0.offset_16|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_29|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_33|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_17|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_118|, ULTIMATE.start_main_~#t2493~0.offset=|v_ULTIMATE.start_main_~#t2493~0.offset_17|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_45|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_34|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_37|, ~weak$$choice0~0=v_~weak$$choice0~0_12, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_40|, ~y$w_buff1~0=v_~y$w_buff1~0_230, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_108, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_9|, ULTIMATE.start_main_~#t2492~0.offset=|v_ULTIMATE.start_main_~#t2492~0.offset_20|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_90, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_237, ~x~0=v_~x~0_77, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_737, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_45|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_36, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_37|, ULTIMATE.start_main_~#t2493~0.base=|v_ULTIMATE.start_main_~#t2493~0.base_20|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_43|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_24|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_62|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_54, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_33|, ~y$w_buff0~0=v_~y$w_buff0~0_338, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_169, ~y~0=v_~y~0_150, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_37|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_17|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_206|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ULTIMATE.start_main_~#t2492~0.base=|v_ULTIMATE.start_main_~#t2492~0.base_27|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_21, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_34|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_114|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_106, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_42|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_18|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_348, #valid=|v_#valid_59|, #memory_int=|v_#memory_int_23|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_10|, ~z~0=v_~z~0_90, ~weak$$choice2~0=v_~weak$$choice2~0_112, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_407} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_~#t2494~0.base, ~y$read_delayed~0, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ULTIMATE.start_main_~#t2494~0.offset, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_~#t2493~0.offset, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t2492~0.offset, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_~#t2493~0.base, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_~#t2492~0.base, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 18:10:48,126 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [707] [707] L798-1-->L800: Formula: (and (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t2493~0.base_9| 4)) (= |v_ULTIMATE.start_main_~#t2493~0.offset_9| 0) (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2493~0.base_9| 1)) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2493~0.base_9| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2493~0.base_9|) |v_ULTIMATE.start_main_~#t2493~0.offset_9| 1))) (= 0 (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2493~0.base_9|)) (not (= |v_ULTIMATE.start_main_~#t2493~0.base_9| 0)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2493~0.base_9|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t2493~0.offset=|v_ULTIMATE.start_main_~#t2493~0.offset_9|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_4|, #length=|v_#length_15|, ULTIMATE.start_main_~#t2493~0.base=|v_ULTIMATE.start_main_~#t2493~0.base_9|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_~#t2493~0.offset, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t2493~0.base] because there is no mapped edge [2019-12-07 18:10:48,127 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L800-1-->L802: Formula: (and (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t2494~0.base_10|)) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2494~0.base_10| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2494~0.base_10|) |v_ULTIMATE.start_main_~#t2494~0.offset_9| 2)) |v_#memory_int_11|) (= (store |v_#valid_32| |v_ULTIMATE.start_main_~#t2494~0.base_10| 1) |v_#valid_31|) (not (= 0 |v_ULTIMATE.start_main_~#t2494~0.base_10|)) (= (store |v_#length_14| |v_ULTIMATE.start_main_~#t2494~0.base_10| 4) |v_#length_13|) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t2494~0.base_10|) (= 0 |v_ULTIMATE.start_main_~#t2494~0.offset_9|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_12|, #length=|v_#length_14|} OutVars{ULTIMATE.start_main_~#t2494~0.base=|v_ULTIMATE.start_main_~#t2494~0.base_10|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_13|, ULTIMATE.start_main_~#t2494~0.offset=|v_ULTIMATE.start_main_~#t2494~0.offset_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2494~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length, ULTIMATE.start_main_~#t2494~0.offset] because there is no mapped edge [2019-12-07 18:10:48,127 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] P2ENTRY-->L4-3: Formula: (and (= ~y$w_buff1_used~0_Out-1642538921 ~y$w_buff0_used~0_In-1642538921) (= ~y$w_buff0_used~0_Out-1642538921 1) (not (= 0 P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out-1642538921)) (= ~y$w_buff1~0_Out-1642538921 ~y$w_buff0~0_In-1642538921) (= |P2Thread1of1ForFork0_#in~arg.base_In-1642538921| P2Thread1of1ForFork0_~arg.base_Out-1642538921) (= P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out-1642538921 |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out-1642538921|) (= |P2Thread1of1ForFork0_#in~arg.offset_In-1642538921| P2Thread1of1ForFork0_~arg.offset_Out-1642538921) (= |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out-1642538921| (ite (not (and (not (= 0 (mod ~y$w_buff1_used~0_Out-1642538921 256))) (not (= 0 (mod ~y$w_buff0_used~0_Out-1642538921 256))))) 1 0)) (= 2 ~y$w_buff0~0_Out-1642538921)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|P2Thread1of1ForFork0_#in~arg.offset_In-1642538921|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1642538921, ~y$w_buff0~0=~y$w_buff0~0_In-1642538921, P2Thread1of1ForFork0_#in~arg.base=|P2Thread1of1ForFork0_#in~arg.base_In-1642538921|} OutVars{P2Thread1of1ForFork0_~arg.base=P2Thread1of1ForFork0_~arg.base_Out-1642538921, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out-1642538921|, P2Thread1of1ForFork0_#in~arg.offset=|P2Thread1of1ForFork0_#in~arg.offset_In-1642538921|, ~y$w_buff0_used~0=~y$w_buff0_used~0_Out-1642538921, ~y$w_buff1~0=~y$w_buff1~0_Out-1642538921, ~y$w_buff0~0=~y$w_buff0~0_Out-1642538921, P2Thread1of1ForFork0_~arg.offset=P2Thread1of1ForFork0_~arg.offset_Out-1642538921, P2Thread1of1ForFork0_#in~arg.base=|P2Thread1of1ForFork0_#in~arg.base_In-1642538921|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out-1642538921, ~y$w_buff1_used~0=~y$w_buff1_used~0_Out-1642538921} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 18:10:48,128 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_60 1) (= (+ v_~__unbuffered_cnt~0_57 1) v_~__unbuffered_cnt~0_56) (= |v_P0Thread1of1ForFork1_#in~arg.base_17| v_P0Thread1of1ForFork1_~arg.base_15) (= 0 |v_P0Thread1of1ForFork1_#res.offset_7|) (= v_P0Thread1of1ForFork1_~arg.offset_15 |v_P0Thread1of1ForFork1_#in~arg.offset_17|) (= v_~z~0_51 2) (= 0 |v_P0Thread1of1ForFork1_#res.base_7|)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_17|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_57, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_17|} OutVars{P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_7|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_17|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_7|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_15, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56, ~z~0=v_~z~0_51, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_17|, ~x~0=v_~x~0_60, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_15} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, ~x~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-12-07 18:10:48,128 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [673] [673] L776-->L776-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In230798634 256))) (.cse1 (= (mod ~y$r_buff0_thd3~0_In230798634 256) 0))) (or (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out230798634| 0) (not .cse1)) (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite11_Out230798634| ~y$w_buff0_used~0_In230798634)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In230798634, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In230798634} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In230798634, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out230798634|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In230798634} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 18:10:48,128 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L746-2-->L746-5: Formula: (let ((.cse0 (= |P1Thread1of1ForFork2_#t~ite3_Out1126165676| |P1Thread1of1ForFork2_#t~ite4_Out1126165676|)) (.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In1126165676 256))) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1126165676 256)))) (or (and .cse0 (not .cse1) (= |P1Thread1of1ForFork2_#t~ite3_Out1126165676| ~y$w_buff1~0_In1126165676) (not .cse2)) (and .cse0 (or .cse1 .cse2) (= ~y~0_In1126165676 |P1Thread1of1ForFork2_#t~ite3_Out1126165676|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1126165676, ~y$w_buff1~0=~y$w_buff1~0_In1126165676, ~y~0=~y~0_In1126165676, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1126165676} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1126165676, ~y$w_buff1~0=~y$w_buff1~0_In1126165676, P1Thread1of1ForFork2_#t~ite4=|P1Thread1of1ForFork2_#t~ite4_Out1126165676|, ~y~0=~y~0_In1126165676, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out1126165676|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1126165676} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 18:10:48,129 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L777-->L777-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In2078274004 256))) (.cse0 (= (mod ~y$r_buff1_thd3~0_In2078274004 256) 0)) (.cse3 (= (mod ~y$r_buff0_thd3~0_In2078274004 256) 0)) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In2078274004 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite12_Out2078274004| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~y$w_buff1_used~0_In2078274004 |P2Thread1of1ForFork0_#t~ite12_Out2078274004|) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In2078274004, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2078274004, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In2078274004, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2078274004} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In2078274004, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2078274004, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out2078274004|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In2078274004, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2078274004} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 18:10:48,129 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L747-->L747-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In159198614 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In159198614 256)))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite5_Out159198614|) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite5_Out159198614| ~y$w_buff0_used~0_In159198614)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In159198614, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In159198614} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In159198614, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In159198614, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out159198614|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 18:10:48,129 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [672] [672] L748-->L748-2: Formula: (let ((.cse1 (= (mod ~y$r_buff1_thd2~0_In-452886690 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In-452886690 256) 0)) (.cse3 (= (mod ~y$r_buff0_thd2~0_In-452886690 256) 0)) (.cse2 (= (mod ~y$w_buff0_used~0_In-452886690 256) 0))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite6_Out-452886690|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (= ~y$w_buff1_used~0_In-452886690 |P1Thread1of1ForFork2_#t~ite6_Out-452886690|) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-452886690, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-452886690, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-452886690, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-452886690} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-452886690, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-452886690, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-452886690, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out-452886690|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-452886690} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 18:10:48,130 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L749-->L749-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-197686713 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-197686713 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite7_Out-197686713| 0) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |P1Thread1of1ForFork2_#t~ite7_Out-197686713| ~y$r_buff0_thd2~0_In-197686713)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-197686713, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-197686713} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-197686713, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-197686713, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out-197686713|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 18:10:48,130 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [676] [676] L750-->L750-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In1855236685 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In1855236685 256))) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In1855236685 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In1855236685 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite8_Out1855236685| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P1Thread1of1ForFork2_#t~ite8_Out1855236685| ~y$r_buff1_thd2~0_In1855236685) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1855236685, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1855236685, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1855236685, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1855236685} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1855236685, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1855236685, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out1855236685|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1855236685, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1855236685} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 18:10:48,130 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L750-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_34| v_~y$r_buff1_thd2~0_71) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74)) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_71, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_33|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 18:10:48,130 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [671] [671] L778-->L779: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1353549744 256))) (.cse2 (= ~y$r_buff0_thd3~0_In-1353549744 ~y$r_buff0_thd3~0_Out-1353549744)) (.cse0 (= (mod ~y$r_buff0_thd3~0_In-1353549744 256) 0))) (or (and (not .cse0) (= 0 ~y$r_buff0_thd3~0_Out-1353549744) (not .cse1)) (and .cse2 .cse1) (and .cse2 .cse0))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1353549744, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1353549744} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1353549744, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-1353549744, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-1353549744|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 18:10:48,130 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L779-->L779-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff0_used~0_In-1067130461 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In-1067130461 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-1067130461 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd3~0_In-1067130461 256) 0))) (or (and (= ~y$r_buff1_thd3~0_In-1067130461 |P2Thread1of1ForFork0_#t~ite14_Out-1067130461|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= 0 |P2Thread1of1ForFork0_#t~ite14_Out-1067130461|)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1067130461, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1067130461, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1067130461, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1067130461} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out-1067130461|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1067130461, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1067130461, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1067130461, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1067130461} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 18:10:48,130 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L779-2-->P2EXIT: Formula: (and (= v_~__unbuffered_cnt~0_68 (+ v_~__unbuffered_cnt~0_69 1)) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_32| v_~y$r_buff1_thd3~0_66) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_69} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_31|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_66, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_68, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 18:10:48,130 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [618] [618] L802-1-->L808: Formula: (and (= v_~main$tmp_guard0~0_7 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:10:48,131 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L808-2-->L808-5: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In882087595 256))) (.cse2 (= (mod ~y$r_buff1_thd0~0_In882087595 256) 0)) (.cse0 (= |ULTIMATE.start_main_#t~ite19_Out882087595| |ULTIMATE.start_main_#t~ite18_Out882087595|))) (or (and .cse0 (= ~y$w_buff1~0_In882087595 |ULTIMATE.start_main_#t~ite18_Out882087595|) (not .cse1) (not .cse2)) (and (or .cse1 .cse2) .cse0 (= |ULTIMATE.start_main_#t~ite18_Out882087595| ~y~0_In882087595)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In882087595, ~y~0=~y~0_In882087595, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In882087595, ~y$w_buff1_used~0=~y$w_buff1_used~0_In882087595} OutVars{~y$w_buff1~0=~y$w_buff1~0_In882087595, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out882087595|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out882087595|, ~y~0=~y~0_In882087595, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In882087595, ~y$w_buff1_used~0=~y$w_buff1_used~0_In882087595} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 18:10:48,131 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [679] [679] L809-->L809-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In688827863 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In688827863 256)))) (or (and (= |ULTIMATE.start_main_#t~ite20_Out688827863| 0) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite20_Out688827863| ~y$w_buff0_used~0_In688827863)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In688827863, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In688827863} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In688827863, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In688827863, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out688827863|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 18:10:48,131 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [675] [675] L810-->L810-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In1574320100 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In1574320100 256) 0)) (.cse3 (= (mod ~y$r_buff1_thd0~0_In1574320100 256) 0)) (.cse2 (= (mod ~y$w_buff1_used~0_In1574320100 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite21_Out1574320100| 0)) (and (or .cse0 .cse1) (= ~y$w_buff1_used~0_In1574320100 |ULTIMATE.start_main_#t~ite21_Out1574320100|) (or .cse3 .cse2)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1574320100, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1574320100, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1574320100, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1574320100} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1574320100, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1574320100, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out1574320100|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1574320100, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1574320100} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 18:10:48,132 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L811-->L811-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In555250721 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In555250721 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite22_Out555250721|)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite22_Out555250721| ~y$r_buff0_thd0~0_In555250721)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In555250721, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In555250721} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In555250721, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In555250721, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out555250721|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 18:10:48,132 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [682] [682] L812-->L812-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-32514386 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-32514386 256))) (.cse3 (= (mod ~y$r_buff1_thd0~0_In-32514386 256) 0)) (.cse2 (= (mod ~y$w_buff1_used~0_In-32514386 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite23_Out-32514386| 0)) (and (= |ULTIMATE.start_main_#t~ite23_Out-32514386| ~y$r_buff1_thd0~0_In-32514386) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-32514386, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-32514386, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-32514386, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-32514386} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-32514386, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-32514386, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-32514386, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-32514386|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-32514386} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 18:10:48,133 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L820-->L820-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In582057751 256)))) (or (and (= ~y$w_buff0~0_In582057751 |ULTIMATE.start_main_#t~ite30_Out582057751|) (= |ULTIMATE.start_main_#t~ite29_In582057751| |ULTIMATE.start_main_#t~ite29_Out582057751|) (not .cse0)) (and .cse0 (= |ULTIMATE.start_main_#t~ite29_Out582057751| |ULTIMATE.start_main_#t~ite30_Out582057751|) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In582057751 256)))) (or (= (mod ~y$w_buff0_used~0_In582057751 256) 0) (and .cse1 (= (mod ~y$w_buff1_used~0_In582057751 256) 0)) (and (= (mod ~y$r_buff1_thd0~0_In582057751 256) 0) .cse1))) (= ~y$w_buff0~0_In582057751 |ULTIMATE.start_main_#t~ite29_Out582057751|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In582057751, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_In582057751|, ~y$w_buff0~0=~y$w_buff0~0_In582057751, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In582057751, ~weak$$choice2~0=~weak$$choice2~0_In582057751, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In582057751, ~y$w_buff1_used~0=~y$w_buff1_used~0_In582057751} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out582057751|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In582057751, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out582057751|, ~y$w_buff0~0=~y$w_buff0~0_In582057751, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In582057751, ~weak$$choice2~0=~weak$$choice2~0_In582057751, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In582057751, ~y$w_buff1_used~0=~y$w_buff1_used~0_In582057751} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 18:10:48,133 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L821-->L821-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-1876976199 256) 0))) (or (and (= ~y$w_buff1~0_In-1876976199 |ULTIMATE.start_main_#t~ite33_Out-1876976199|) (not .cse0) (= |ULTIMATE.start_main_#t~ite32_In-1876976199| |ULTIMATE.start_main_#t~ite32_Out-1876976199|)) (and (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-1876976199 256) 0))) (or (and (= (mod ~y$r_buff1_thd0~0_In-1876976199 256) 0) .cse1) (= 0 (mod ~y$w_buff0_used~0_In-1876976199 256)) (and (= (mod ~y$w_buff1_used~0_In-1876976199 256) 0) .cse1))) .cse0 (= ~y$w_buff1~0_In-1876976199 |ULTIMATE.start_main_#t~ite32_Out-1876976199|) (= |ULTIMATE.start_main_#t~ite33_Out-1876976199| |ULTIMATE.start_main_#t~ite32_Out-1876976199|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1876976199, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1876976199, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1876976199, ~weak$$choice2~0=~weak$$choice2~0_In-1876976199, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1876976199, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_In-1876976199|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1876976199} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1876976199, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1876976199, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1876976199, ~weak$$choice2~0=~weak$$choice2~0_In-1876976199, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_Out-1876976199|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1876976199, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out-1876976199|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1876976199} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_#t~ite33] because there is no mapped edge [2019-12-07 18:10:48,134 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L822-->L822-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-889150515 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite35_In-889150515| |ULTIMATE.start_main_#t~ite35_Out-889150515|) (= |ULTIMATE.start_main_#t~ite36_Out-889150515| ~y$w_buff0_used~0_In-889150515)) (and (= |ULTIMATE.start_main_#t~ite36_Out-889150515| |ULTIMATE.start_main_#t~ite35_Out-889150515|) .cse0 (= ~y$w_buff0_used~0_In-889150515 |ULTIMATE.start_main_#t~ite35_Out-889150515|) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-889150515 256) 0))) (or (and (= (mod ~y$r_buff1_thd0~0_In-889150515 256) 0) .cse1) (= (mod ~y$w_buff0_used~0_In-889150515 256) 0) (and (= (mod ~y$w_buff1_used~0_In-889150515 256) 0) .cse1)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-889150515, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-889150515, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_In-889150515|, ~weak$$choice2~0=~weak$$choice2~0_In-889150515, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-889150515, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-889150515} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-889150515, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-889150515, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_Out-889150515|, ULTIMATE.start_main_#t~ite36=|ULTIMATE.start_main_#t~ite36_Out-889150515|, ~weak$$choice2~0=~weak$$choice2~0_In-889150515, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-889150515, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-889150515} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36] because there is no mapped edge [2019-12-07 18:10:48,135 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [737] [737] L824-->L825-8: Formula: (and (= v_~y$r_buff1_thd0~0_226 |v_ULTIMATE.start_main_#t~ite45_60|) (not (= 0 (mod v_~weak$$choice2~0_105 256))) (= |v_ULTIMATE.start_main_#t~ite43_49| |v_ULTIMATE.start_main_#t~ite43_48|) (= |v_ULTIMATE.start_main_#t~ite44_49| |v_ULTIMATE.start_main_#t~ite44_48|) (= v_~y$r_buff0_thd0~0_339 v_~y$r_buff0_thd0~0_338)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_339, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_49|, ~weak$$choice2~0=v_~weak$$choice2~0_105, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_226, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_49|} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_37|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_35|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_338, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_48|, ~weak$$choice2~0=v_~weak$$choice2~0_105, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_226, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_19|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_60|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_48|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-12-07 18:10:48,135 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [701] [701] L827-->L830-1: Formula: (and (= (mod v_~main$tmp_guard1~0_21 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_~y~0_89 v_~y$mem_tmp~0_11) (= 0 v_~y$flush_delayed~0_23) (not (= (mod v_~y$flush_delayed~0_24 256) 0))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_24, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_23, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_23|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ~y~0=v_~y~0_89, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:10:48,135 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [703] [703] L830-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:10:48,194 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 06:10:48 BasicIcfg [2019-12-07 18:10:48,194 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 18:10:48,194 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:10:48,194 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:10:48,194 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:10:48,195 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:10:14" (3/4) ... [2019-12-07 18:10:48,197 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 18:10:48,197 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [743] [743] ULTIMATE.startENTRY-->L798: Formula: (let ((.cse0 (store |v_#valid_61| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= 0 v_~y$r_buff1_thd1~0_54) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t2492~0.base_27|) (= 0 v_~y$r_buff1_thd3~0_115) (= 0 v_~y$r_buff1_thd2~0_106) (= v_~weak$$choice2~0_112 0) (= v_~y$r_buff0_thd1~0_53 0) (= v_~y$r_buff0_thd0~0_348 0) (= v_~y$w_buff0_used~0_737 0) (= v_~y$w_buff1~0_230 0) (= v_~y$read_delayed~0_6 0) (= 0 v_~y$r_buff0_thd3~0_169) (= 0 v_~y$w_buff0~0_338) (< 0 |v_#StackHeapBarrier_18|) (= 0 v_~y$r_buff0_thd2~0_108) (= (store .cse0 |v_ULTIMATE.start_main_~#t2492~0.base_27| 1) |v_#valid_59|) (= v_~y$mem_tmp~0_19 0) (= v_~z~0_90 0) (= v_~x~0_77 0) (= v_~y$w_buff1_used~0_407 0) (= v_~main$tmp_guard0~0_21 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t2492~0.base_27|)) (= |v_#NULL.offset_5| 0) (= v_~main$tmp_guard1~0_36 0) (= 0 v_~__unbuffered_cnt~0_90) (= v_~y$r_buff1_thd0~0_237 0) (= (store |v_#length_26| |v_ULTIMATE.start_main_~#t2492~0.base_27| 4) |v_#length_25|) (= 0 |v_ULTIMATE.start_main_~#t2492~0.offset_20|) (= 0 v_~y$flush_delayed~0_38) (= 0 v_~y$read_delayed_var~0.offset_6) (= v_~y~0_150 0) (= 0 |v_#NULL.base_5|) (= |v_#memory_int_23| (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t2492~0.base_27| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t2492~0.base_27|) |v_ULTIMATE.start_main_~#t2492~0.offset_20| 0))) (= 0 v_~weak$$choice0~0_12))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_61|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_34|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_39|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_62|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_31|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_71|, ULTIMATE.start_main_~#t2494~0.base=|v_ULTIMATE.start_main_~#t2494~0.base_20|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~y$mem_tmp~0=v_~y$mem_tmp~0_19, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_115, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_53, ~y$flush_delayed~0=v_~y$flush_delayed~0_38, #length=|v_#length_25|, ULTIMATE.start_main_~#t2494~0.offset=|v_ULTIMATE.start_main_~#t2494~0.offset_16|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_29|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_33|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_17|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_118|, ULTIMATE.start_main_~#t2493~0.offset=|v_ULTIMATE.start_main_~#t2493~0.offset_17|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_45|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_34|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_37|, ~weak$$choice0~0=v_~weak$$choice0~0_12, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_40|, ~y$w_buff1~0=v_~y$w_buff1~0_230, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_108, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_9|, ULTIMATE.start_main_~#t2492~0.offset=|v_ULTIMATE.start_main_~#t2492~0.offset_20|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_90, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_237, ~x~0=v_~x~0_77, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_737, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_45|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_36, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_37|, ULTIMATE.start_main_~#t2493~0.base=|v_ULTIMATE.start_main_~#t2493~0.base_20|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_43|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_24|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_62|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_54, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_33|, ~y$w_buff0~0=v_~y$w_buff0~0_338, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_169, ~y~0=v_~y~0_150, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_37|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_17|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_206|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ULTIMATE.start_main_~#t2492~0.base=|v_ULTIMATE.start_main_~#t2492~0.base_27|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_21, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_34|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_114|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_106, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_42|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_18|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_348, #valid=|v_#valid_59|, #memory_int=|v_#memory_int_23|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_10|, ~z~0=v_~z~0_90, ~weak$$choice2~0=v_~weak$$choice2~0_112, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_407} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_~#t2494~0.base, ~y$read_delayed~0, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ULTIMATE.start_main_~#t2494~0.offset, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_~#t2493~0.offset, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t2492~0.offset, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_~#t2493~0.base, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_~#t2492~0.base, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 18:10:48,197 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [707] [707] L798-1-->L800: Formula: (and (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t2493~0.base_9| 4)) (= |v_ULTIMATE.start_main_~#t2493~0.offset_9| 0) (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2493~0.base_9| 1)) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2493~0.base_9| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2493~0.base_9|) |v_ULTIMATE.start_main_~#t2493~0.offset_9| 1))) (= 0 (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2493~0.base_9|)) (not (= |v_ULTIMATE.start_main_~#t2493~0.base_9| 0)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2493~0.base_9|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t2493~0.offset=|v_ULTIMATE.start_main_~#t2493~0.offset_9|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_4|, #length=|v_#length_15|, ULTIMATE.start_main_~#t2493~0.base=|v_ULTIMATE.start_main_~#t2493~0.base_9|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_~#t2493~0.offset, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t2493~0.base] because there is no mapped edge [2019-12-07 18:10:48,198 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L800-1-->L802: Formula: (and (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t2494~0.base_10|)) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2494~0.base_10| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2494~0.base_10|) |v_ULTIMATE.start_main_~#t2494~0.offset_9| 2)) |v_#memory_int_11|) (= (store |v_#valid_32| |v_ULTIMATE.start_main_~#t2494~0.base_10| 1) |v_#valid_31|) (not (= 0 |v_ULTIMATE.start_main_~#t2494~0.base_10|)) (= (store |v_#length_14| |v_ULTIMATE.start_main_~#t2494~0.base_10| 4) |v_#length_13|) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t2494~0.base_10|) (= 0 |v_ULTIMATE.start_main_~#t2494~0.offset_9|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_12|, #length=|v_#length_14|} OutVars{ULTIMATE.start_main_~#t2494~0.base=|v_ULTIMATE.start_main_~#t2494~0.base_10|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_13|, ULTIMATE.start_main_~#t2494~0.offset=|v_ULTIMATE.start_main_~#t2494~0.offset_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2494~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length, ULTIMATE.start_main_~#t2494~0.offset] because there is no mapped edge [2019-12-07 18:10:48,198 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] P2ENTRY-->L4-3: Formula: (and (= ~y$w_buff1_used~0_Out-1642538921 ~y$w_buff0_used~0_In-1642538921) (= ~y$w_buff0_used~0_Out-1642538921 1) (not (= 0 P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out-1642538921)) (= ~y$w_buff1~0_Out-1642538921 ~y$w_buff0~0_In-1642538921) (= |P2Thread1of1ForFork0_#in~arg.base_In-1642538921| P2Thread1of1ForFork0_~arg.base_Out-1642538921) (= P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out-1642538921 |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out-1642538921|) (= |P2Thread1of1ForFork0_#in~arg.offset_In-1642538921| P2Thread1of1ForFork0_~arg.offset_Out-1642538921) (= |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out-1642538921| (ite (not (and (not (= 0 (mod ~y$w_buff1_used~0_Out-1642538921 256))) (not (= 0 (mod ~y$w_buff0_used~0_Out-1642538921 256))))) 1 0)) (= 2 ~y$w_buff0~0_Out-1642538921)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|P2Thread1of1ForFork0_#in~arg.offset_In-1642538921|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1642538921, ~y$w_buff0~0=~y$w_buff0~0_In-1642538921, P2Thread1of1ForFork0_#in~arg.base=|P2Thread1of1ForFork0_#in~arg.base_In-1642538921|} OutVars{P2Thread1of1ForFork0_~arg.base=P2Thread1of1ForFork0_~arg.base_Out-1642538921, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out-1642538921|, P2Thread1of1ForFork0_#in~arg.offset=|P2Thread1of1ForFork0_#in~arg.offset_In-1642538921|, ~y$w_buff0_used~0=~y$w_buff0_used~0_Out-1642538921, ~y$w_buff1~0=~y$w_buff1~0_Out-1642538921, ~y$w_buff0~0=~y$w_buff0~0_Out-1642538921, P2Thread1of1ForFork0_~arg.offset=P2Thread1of1ForFork0_~arg.offset_Out-1642538921, P2Thread1of1ForFork0_#in~arg.base=|P2Thread1of1ForFork0_#in~arg.base_In-1642538921|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out-1642538921, ~y$w_buff1_used~0=~y$w_buff1_used~0_Out-1642538921} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 18:10:48,199 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_60 1) (= (+ v_~__unbuffered_cnt~0_57 1) v_~__unbuffered_cnt~0_56) (= |v_P0Thread1of1ForFork1_#in~arg.base_17| v_P0Thread1of1ForFork1_~arg.base_15) (= 0 |v_P0Thread1of1ForFork1_#res.offset_7|) (= v_P0Thread1of1ForFork1_~arg.offset_15 |v_P0Thread1of1ForFork1_#in~arg.offset_17|) (= v_~z~0_51 2) (= 0 |v_P0Thread1of1ForFork1_#res.base_7|)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_17|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_57, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_17|} OutVars{P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_7|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_17|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_7|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_15, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56, ~z~0=v_~z~0_51, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_17|, ~x~0=v_~x~0_60, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_15} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, ~x~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-12-07 18:10:48,199 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [673] [673] L776-->L776-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In230798634 256))) (.cse1 (= (mod ~y$r_buff0_thd3~0_In230798634 256) 0))) (or (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out230798634| 0) (not .cse1)) (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite11_Out230798634| ~y$w_buff0_used~0_In230798634)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In230798634, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In230798634} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In230798634, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out230798634|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In230798634} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 18:10:48,200 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L746-2-->L746-5: Formula: (let ((.cse0 (= |P1Thread1of1ForFork2_#t~ite3_Out1126165676| |P1Thread1of1ForFork2_#t~ite4_Out1126165676|)) (.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In1126165676 256))) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1126165676 256)))) (or (and .cse0 (not .cse1) (= |P1Thread1of1ForFork2_#t~ite3_Out1126165676| ~y$w_buff1~0_In1126165676) (not .cse2)) (and .cse0 (or .cse1 .cse2) (= ~y~0_In1126165676 |P1Thread1of1ForFork2_#t~ite3_Out1126165676|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1126165676, ~y$w_buff1~0=~y$w_buff1~0_In1126165676, ~y~0=~y~0_In1126165676, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1126165676} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1126165676, ~y$w_buff1~0=~y$w_buff1~0_In1126165676, P1Thread1of1ForFork2_#t~ite4=|P1Thread1of1ForFork2_#t~ite4_Out1126165676|, ~y~0=~y~0_In1126165676, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out1126165676|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1126165676} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 18:10:48,200 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L777-->L777-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In2078274004 256))) (.cse0 (= (mod ~y$r_buff1_thd3~0_In2078274004 256) 0)) (.cse3 (= (mod ~y$r_buff0_thd3~0_In2078274004 256) 0)) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In2078274004 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite12_Out2078274004| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~y$w_buff1_used~0_In2078274004 |P2Thread1of1ForFork0_#t~ite12_Out2078274004|) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In2078274004, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2078274004, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In2078274004, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2078274004} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In2078274004, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2078274004, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out2078274004|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In2078274004, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2078274004} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 18:10:48,201 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L747-->L747-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In159198614 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In159198614 256)))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite5_Out159198614|) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite5_Out159198614| ~y$w_buff0_used~0_In159198614)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In159198614, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In159198614} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In159198614, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In159198614, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out159198614|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 18:10:48,201 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [672] [672] L748-->L748-2: Formula: (let ((.cse1 (= (mod ~y$r_buff1_thd2~0_In-452886690 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In-452886690 256) 0)) (.cse3 (= (mod ~y$r_buff0_thd2~0_In-452886690 256) 0)) (.cse2 (= (mod ~y$w_buff0_used~0_In-452886690 256) 0))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite6_Out-452886690|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (= ~y$w_buff1_used~0_In-452886690 |P1Thread1of1ForFork2_#t~ite6_Out-452886690|) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-452886690, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-452886690, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-452886690, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-452886690} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-452886690, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-452886690, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-452886690, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out-452886690|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-452886690} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 18:10:48,202 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L749-->L749-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-197686713 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-197686713 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite7_Out-197686713| 0) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |P1Thread1of1ForFork2_#t~ite7_Out-197686713| ~y$r_buff0_thd2~0_In-197686713)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-197686713, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-197686713} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-197686713, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-197686713, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out-197686713|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 18:10:48,202 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [676] [676] L750-->L750-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In1855236685 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In1855236685 256))) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In1855236685 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In1855236685 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite8_Out1855236685| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P1Thread1of1ForFork2_#t~ite8_Out1855236685| ~y$r_buff1_thd2~0_In1855236685) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1855236685, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1855236685, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1855236685, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1855236685} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1855236685, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1855236685, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out1855236685|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1855236685, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1855236685} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 18:10:48,202 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L750-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_34| v_~y$r_buff1_thd2~0_71) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74)) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_71, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_33|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 18:10:48,202 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [671] [671] L778-->L779: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1353549744 256))) (.cse2 (= ~y$r_buff0_thd3~0_In-1353549744 ~y$r_buff0_thd3~0_Out-1353549744)) (.cse0 (= (mod ~y$r_buff0_thd3~0_In-1353549744 256) 0))) (or (and (not .cse0) (= 0 ~y$r_buff0_thd3~0_Out-1353549744) (not .cse1)) (and .cse2 .cse1) (and .cse2 .cse0))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1353549744, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1353549744} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1353549744, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-1353549744, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-1353549744|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 18:10:48,203 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L779-->L779-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff0_used~0_In-1067130461 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In-1067130461 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-1067130461 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd3~0_In-1067130461 256) 0))) (or (and (= ~y$r_buff1_thd3~0_In-1067130461 |P2Thread1of1ForFork0_#t~ite14_Out-1067130461|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= 0 |P2Thread1of1ForFork0_#t~ite14_Out-1067130461|)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1067130461, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1067130461, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1067130461, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1067130461} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out-1067130461|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1067130461, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1067130461, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1067130461, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1067130461} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 18:10:48,203 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L779-2-->P2EXIT: Formula: (and (= v_~__unbuffered_cnt~0_68 (+ v_~__unbuffered_cnt~0_69 1)) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_32| v_~y$r_buff1_thd3~0_66) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_69} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_31|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_66, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_68, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 18:10:48,203 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [618] [618] L802-1-->L808: Formula: (and (= v_~main$tmp_guard0~0_7 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:10:48,203 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L808-2-->L808-5: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In882087595 256))) (.cse2 (= (mod ~y$r_buff1_thd0~0_In882087595 256) 0)) (.cse0 (= |ULTIMATE.start_main_#t~ite19_Out882087595| |ULTIMATE.start_main_#t~ite18_Out882087595|))) (or (and .cse0 (= ~y$w_buff1~0_In882087595 |ULTIMATE.start_main_#t~ite18_Out882087595|) (not .cse1) (not .cse2)) (and (or .cse1 .cse2) .cse0 (= |ULTIMATE.start_main_#t~ite18_Out882087595| ~y~0_In882087595)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In882087595, ~y~0=~y~0_In882087595, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In882087595, ~y$w_buff1_used~0=~y$w_buff1_used~0_In882087595} OutVars{~y$w_buff1~0=~y$w_buff1~0_In882087595, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out882087595|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out882087595|, ~y~0=~y~0_In882087595, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In882087595, ~y$w_buff1_used~0=~y$w_buff1_used~0_In882087595} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 18:10:48,204 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [679] [679] L809-->L809-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In688827863 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In688827863 256)))) (or (and (= |ULTIMATE.start_main_#t~ite20_Out688827863| 0) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite20_Out688827863| ~y$w_buff0_used~0_In688827863)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In688827863, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In688827863} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In688827863, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In688827863, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out688827863|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 18:10:48,204 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [675] [675] L810-->L810-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In1574320100 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In1574320100 256) 0)) (.cse3 (= (mod ~y$r_buff1_thd0~0_In1574320100 256) 0)) (.cse2 (= (mod ~y$w_buff1_used~0_In1574320100 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite21_Out1574320100| 0)) (and (or .cse0 .cse1) (= ~y$w_buff1_used~0_In1574320100 |ULTIMATE.start_main_#t~ite21_Out1574320100|) (or .cse3 .cse2)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1574320100, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1574320100, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1574320100, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1574320100} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1574320100, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1574320100, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out1574320100|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1574320100, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1574320100} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 18:10:48,204 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L811-->L811-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In555250721 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In555250721 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite22_Out555250721|)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite22_Out555250721| ~y$r_buff0_thd0~0_In555250721)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In555250721, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In555250721} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In555250721, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In555250721, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out555250721|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 18:10:48,205 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [682] [682] L812-->L812-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-32514386 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-32514386 256))) (.cse3 (= (mod ~y$r_buff1_thd0~0_In-32514386 256) 0)) (.cse2 (= (mod ~y$w_buff1_used~0_In-32514386 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite23_Out-32514386| 0)) (and (= |ULTIMATE.start_main_#t~ite23_Out-32514386| ~y$r_buff1_thd0~0_In-32514386) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-32514386, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-32514386, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-32514386, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-32514386} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-32514386, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-32514386, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-32514386, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-32514386|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-32514386} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 18:10:48,206 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L820-->L820-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In582057751 256)))) (or (and (= ~y$w_buff0~0_In582057751 |ULTIMATE.start_main_#t~ite30_Out582057751|) (= |ULTIMATE.start_main_#t~ite29_In582057751| |ULTIMATE.start_main_#t~ite29_Out582057751|) (not .cse0)) (and .cse0 (= |ULTIMATE.start_main_#t~ite29_Out582057751| |ULTIMATE.start_main_#t~ite30_Out582057751|) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In582057751 256)))) (or (= (mod ~y$w_buff0_used~0_In582057751 256) 0) (and .cse1 (= (mod ~y$w_buff1_used~0_In582057751 256) 0)) (and (= (mod ~y$r_buff1_thd0~0_In582057751 256) 0) .cse1))) (= ~y$w_buff0~0_In582057751 |ULTIMATE.start_main_#t~ite29_Out582057751|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In582057751, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_In582057751|, ~y$w_buff0~0=~y$w_buff0~0_In582057751, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In582057751, ~weak$$choice2~0=~weak$$choice2~0_In582057751, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In582057751, ~y$w_buff1_used~0=~y$w_buff1_used~0_In582057751} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out582057751|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In582057751, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out582057751|, ~y$w_buff0~0=~y$w_buff0~0_In582057751, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In582057751, ~weak$$choice2~0=~weak$$choice2~0_In582057751, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In582057751, ~y$w_buff1_used~0=~y$w_buff1_used~0_In582057751} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 18:10:48,206 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L821-->L821-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-1876976199 256) 0))) (or (and (= ~y$w_buff1~0_In-1876976199 |ULTIMATE.start_main_#t~ite33_Out-1876976199|) (not .cse0) (= |ULTIMATE.start_main_#t~ite32_In-1876976199| |ULTIMATE.start_main_#t~ite32_Out-1876976199|)) (and (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-1876976199 256) 0))) (or (and (= (mod ~y$r_buff1_thd0~0_In-1876976199 256) 0) .cse1) (= 0 (mod ~y$w_buff0_used~0_In-1876976199 256)) (and (= (mod ~y$w_buff1_used~0_In-1876976199 256) 0) .cse1))) .cse0 (= ~y$w_buff1~0_In-1876976199 |ULTIMATE.start_main_#t~ite32_Out-1876976199|) (= |ULTIMATE.start_main_#t~ite33_Out-1876976199| |ULTIMATE.start_main_#t~ite32_Out-1876976199|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1876976199, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1876976199, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1876976199, ~weak$$choice2~0=~weak$$choice2~0_In-1876976199, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1876976199, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_In-1876976199|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1876976199} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1876976199, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1876976199, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1876976199, ~weak$$choice2~0=~weak$$choice2~0_In-1876976199, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_Out-1876976199|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1876976199, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out-1876976199|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1876976199} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_#t~ite33] because there is no mapped edge [2019-12-07 18:10:48,207 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L822-->L822-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-889150515 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite35_In-889150515| |ULTIMATE.start_main_#t~ite35_Out-889150515|) (= |ULTIMATE.start_main_#t~ite36_Out-889150515| ~y$w_buff0_used~0_In-889150515)) (and (= |ULTIMATE.start_main_#t~ite36_Out-889150515| |ULTIMATE.start_main_#t~ite35_Out-889150515|) .cse0 (= ~y$w_buff0_used~0_In-889150515 |ULTIMATE.start_main_#t~ite35_Out-889150515|) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-889150515 256) 0))) (or (and (= (mod ~y$r_buff1_thd0~0_In-889150515 256) 0) .cse1) (= (mod ~y$w_buff0_used~0_In-889150515 256) 0) (and (= (mod ~y$w_buff1_used~0_In-889150515 256) 0) .cse1)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-889150515, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-889150515, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_In-889150515|, ~weak$$choice2~0=~weak$$choice2~0_In-889150515, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-889150515, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-889150515} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-889150515, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-889150515, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_Out-889150515|, ULTIMATE.start_main_#t~ite36=|ULTIMATE.start_main_#t~ite36_Out-889150515|, ~weak$$choice2~0=~weak$$choice2~0_In-889150515, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-889150515, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-889150515} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36] because there is no mapped edge [2019-12-07 18:10:48,208 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [737] [737] L824-->L825-8: Formula: (and (= v_~y$r_buff1_thd0~0_226 |v_ULTIMATE.start_main_#t~ite45_60|) (not (= 0 (mod v_~weak$$choice2~0_105 256))) (= |v_ULTIMATE.start_main_#t~ite43_49| |v_ULTIMATE.start_main_#t~ite43_48|) (= |v_ULTIMATE.start_main_#t~ite44_49| |v_ULTIMATE.start_main_#t~ite44_48|) (= v_~y$r_buff0_thd0~0_339 v_~y$r_buff0_thd0~0_338)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_339, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_49|, ~weak$$choice2~0=v_~weak$$choice2~0_105, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_226, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_49|} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_37|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_35|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_338, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_48|, ~weak$$choice2~0=v_~weak$$choice2~0_105, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_226, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_19|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_60|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_48|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-12-07 18:10:48,208 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [701] [701] L827-->L830-1: Formula: (and (= (mod v_~main$tmp_guard1~0_21 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_~y~0_89 v_~y$mem_tmp~0_11) (= 0 v_~y$flush_delayed~0_23) (not (= (mod v_~y$flush_delayed~0_24 256) 0))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_24, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_23, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_23|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ~y~0=v_~y~0_89, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:10:48,208 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [703] [703] L830-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:10:48,262 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_75c79b48-f731-4fa4-a9dc-2857b72a94e0/bin/uautomizer/witness.graphml [2019-12-07 18:10:48,262 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:10:48,263 INFO L168 Benchmark]: Toolchain (without parser) took 34757.02 ms. Allocated memory was 1.0 GB in the beginning and 2.9 GB in the end (delta: 1.9 GB). Free memory was 937.1 MB in the beginning and 1.9 GB in the end (delta: -964.9 MB). Peak memory consumption was 912.6 MB. Max. memory is 11.5 GB. [2019-12-07 18:10:48,263 INFO L168 Benchmark]: CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:10:48,263 INFO L168 Benchmark]: CACSL2BoogieTranslator took 382.44 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 134.7 MB). Free memory was 937.1 MB in the beginning and 1.1 GB in the end (delta: -164.3 MB). Peak memory consumption was 18.2 MB. Max. memory is 11.5 GB. [2019-12-07 18:10:48,264 INFO L168 Benchmark]: Boogie Procedure Inliner took 52.82 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:10:48,264 INFO L168 Benchmark]: Boogie Preprocessor took 32.32 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:10:48,264 INFO L168 Benchmark]: RCFGBuilder took 398.95 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.2 MB). Peak memory consumption was 55.2 MB. Max. memory is 11.5 GB. [2019-12-07 18:10:48,264 INFO L168 Benchmark]: TraceAbstraction took 33819.20 ms. Allocated memory was 1.2 GB in the beginning and 2.9 GB in the end (delta: 1.7 GB). Free memory was 1.0 GB in the beginning and 1.9 GB in the end (delta: -873.7 MB). Peak memory consumption was 869.0 MB. Max. memory is 11.5 GB. [2019-12-07 18:10:48,265 INFO L168 Benchmark]: Witness Printer took 67.97 ms. Allocated memory is still 2.9 GB. Free memory was 1.9 GB in the beginning and 1.9 GB in the end (delta: 12.6 MB). Peak memory consumption was 12.6 MB. Max. memory is 11.5 GB. [2019-12-07 18:10:48,266 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 382.44 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 134.7 MB). Free memory was 937.1 MB in the beginning and 1.1 GB in the end (delta: -164.3 MB). Peak memory consumption was 18.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 52.82 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 32.32 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 398.95 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.2 MB). Peak memory consumption was 55.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 33819.20 ms. Allocated memory was 1.2 GB in the beginning and 2.9 GB in the end (delta: 1.7 GB). Free memory was 1.0 GB in the beginning and 1.9 GB in the end (delta: -873.7 MB). Peak memory consumption was 869.0 MB. Max. memory is 11.5 GB. * Witness Printer took 67.97 ms. Allocated memory is still 2.9 GB. Free memory was 1.9 GB in the beginning and 1.9 GB in the end (delta: 12.6 MB). Peak memory consumption was 12.6 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 2.9s, 161 ProgramPointsBefore, 81 ProgramPointsAfterwards, 192 TransitionsBefore, 86 TransitionsAfterwards, 11490 CoEnabledTransitionPairs, 7 FixpointIterations, 30 TrivialSequentialCompositions, 46 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 34 ConcurrentYvCompositions, 30 ChoiceCompositions, 4050 VarBasedMoverChecksPositive, 194 VarBasedMoverChecksNegative, 29 SemBasedMoverChecksPositive, 227 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.8s, 0 MoverChecksTotal, 46210 CheckedPairsTotal, 110 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L798] FCALL, FORK 0 pthread_create(&t2492, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L800] FCALL, FORK 0 pthread_create(&t2493, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L802] FCALL, FORK 0 pthread_create(&t2494, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L765] 3 y$r_buff1_thd0 = y$r_buff0_thd0 [L766] 3 y$r_buff1_thd1 = y$r_buff0_thd1 [L767] 3 y$r_buff1_thd2 = y$r_buff0_thd2 [L768] 3 y$r_buff1_thd3 = y$r_buff0_thd3 [L769] 3 y$r_buff0_thd3 = (_Bool)1 [L772] 3 z = 1 VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L775] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L740] 2 x = 2 [L743] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L775] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L746] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L776] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L746] 2 y = y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) [L777] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L747] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L748] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L749] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L808] EXPR 0 y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L808] 0 y = y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L809] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L810] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L811] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L812] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L815] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L816] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L817] 0 y$flush_delayed = weak$$choice2 [L818] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L819] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L819] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L820] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L821] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L822] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L823] EXPR 0 weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L823] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L825] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L826] 0 main$tmp_guard1 = !(x == 2 && y == 2 && z == 2) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 152 locations, 2 error locations. Result: UNSAFE, OverallTime: 33.6s, OverallIterations: 42, TraceHistogramMax: 1, AutomataDifference: 17.5s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 6686 SDtfs, 9194 SDslu, 30794 SDs, 0 SdLazy, 14700 SolverSat, 606 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 9.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 646 GetRequests, 45 SyntacticMatches, 29 SemanticMatches, 572 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2112 ImplicationChecksByTransitivity, 5.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=31198occurred in iteration=6, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 8.0s AutomataMinimizationTime, 41 MinimizatonAttempts, 125740 StatesRemovedByMinimization, 35 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 3.4s InterpolantComputationTime, 1496 NumberOfCodeBlocks, 1496 NumberOfCodeBlocksAsserted, 42 NumberOfCheckSat, 1399 ConstructedInterpolants, 0 QuantifiedInterpolants, 294382 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 41 InterpolantComputations, 41 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...